Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	108320	1			T1	9		T2	5		T3	13
all_values[1]	108320	1			T1	9		T2	5		T3	13
all_values[2]	108320	1			T1	9		T2	5		T3	13
all_values[3]	108320	1			T1	9		T2	5		T3	13
all_values[4]	108320	1			T1	9		T2	5		T3	13
all_values[5]	108320	1			T1	9		T2	5		T3	13
all_values[6]	108320	1			T1	9		T2	5		T3	13
all_values[7]	108320	1			T1	9		T2	5		T3	13

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

437384

1

T1

48

T2

21

T3

48

auto[1]

429176

1

T1

24

T2

19

T3

56

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

810015

1

T1

56

T2

34

T3

95

auto[1]

56545

1

T1

16

T2

6

T3

9

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	32149	1			T3	8		T5	123		T6	2
all_values[0]	auto[0]	auto[1]	21728	1			T1	6		T2	3		T3	2
all_values[0]	auto[1]	auto[0]	31855	1			T2	1		T3	1		T5	291
all_values[0]	auto[1]	auto[1]	22588	1			T1	3		T2	1		T3	2
all_values[1]	auto[0]	auto[0]	52776	1			T1	9		T2	4		T3	13
all_values[1]	auto[0]	auto[1]	1634	1			T24	6		T13	4		T111	1
all_values[1]	auto[1]	auto[0]	51969	1			T2	1		T5	508		T6	4
all_values[1]	auto[1]	auto[1]	1941	1			T5	1		T12	4		T13	4
all_values[2]	auto[0]	auto[0]	52793	1			T1	3		T2	2		T3	1
all_values[2]	auto[0]	auto[1]	2810	1			T1	3		T3	2		T5	9
all_values[2]	auto[1]	auto[0]	50162	1			T1	1		T2	2		T3	7
all_values[2]	auto[1]	auto[1]	2555	1			T1	2		T2	1		T3	3
all_values[3]	auto[0]	auto[0]	56288	1			T2	2		T4	11		T5	549
all_values[3]	auto[0]	auto[1]	372	1			T2	1		T5	3		T23	1
all_values[3]	auto[1]	auto[0]	51357	1			T1	7		T2	2		T3	13
all_values[3]	auto[1]	auto[1]	303	1			T1	2		T12	1		T13	2
all_values[4]	auto[0]	auto[0]	54431	1			T1	3		T2	4		T3	13
all_values[4]	auto[0]	auto[1]	418	1			T5	4		T13	1		T15	2
all_values[4]	auto[1]	auto[0]	52975	1			T1	6		T2	1		T4	7
all_values[4]	auto[1]	auto[1]	496	1			T13	1		T15	9		T34	2
all_values[5]	auto[0]	auto[0]	55703	1			T1	6		T3	3		T4	4
all_values[5]	auto[0]	auto[1]	188	1			T13	3		T15	5		T34	4
all_values[5]	auto[1]	auto[0]	52230	1			T1	3		T2	5		T3	10
all_values[5]	auto[1]	auto[1]	199	1			T5	4		T13	2		T15	4
all_values[6]	auto[0]	auto[0]	52552	1			T1	9		T2	2		T3	3
all_values[6]	auto[0]	auto[1]	206	1			T15	5		T33	2		T34	2
all_values[6]	auto[1]	auto[0]	55367	1			T2	3		T3	10		T4	11
all_values[6]	auto[1]	auto[1]	195	1			T5	4		T15	4		T34	2
all_values[7]	auto[0]	auto[0]	52932	1			T1	9		T2	3		T3	3
all_values[7]	auto[0]	auto[1]	404	1			T5	5		T11	1		T13	1
all_values[7]	auto[1]	auto[0]	54476	1			T2	2		T3	10		T4	7
all_values[7]	auto[1]	auto[1]	508	1			T5	1		T11	1		T13	3