Group : uart_agent_pkg::uart_agent_cov::uart_reset_cg
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Group : uart_agent_pkg::uart_agent_cov::uart_reset_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_agent_0.1/uart_agent_cov.sv



Summary for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 13 0 13 100.00
Crosses 22 0 22 100.00


Variables for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_dir 2 0 2 100.00 100 1 1 0
cp_rst_pos 11 0 11 100.00 100 1 1 0


Crosses for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
uart_reset_cg_cc 22 0 22 100.00 100 1 1 0


Summary for Variable cp_dir

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_dir

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[UartTx] 2610 1 T1 1 T2 1 T3 1
auto[UartRx] 2610 1 T1 1 T2 1 T3 1



Summary for Variable cp_rst_pos

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 11 0 11 100.00


User Defined Bins for cp_rst_pos

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0] 4595 1 T1 2 T2 2 T3 2
values[1] 51 1 T13 1 T33 2 T34 2
values[2] 63 1 T5 1 T13 1 T23 1
values[3] 53 1 T5 1 T13 2 T15 1
values[4] 55 1 T23 1 T34 2 T17 1
values[5] 53 1 T23 2 T35 2 T17 1
values[6] 68 1 T5 1 T13 2 T15 1
values[7] 70 1 T13 2 T33 1 T34 1
values[8] 55 1 T5 1 T13 1 T15 1
values[9] 62 1 T5 2 T13 2 T34 1
values[10] 66 1 T23 1 T15 1 T18 1



Summary for Cross uart_reset_cg_cc

Samples crossed: cp_dir cp_rst_pos
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 22 0 22 100.00


Automatically Generated Cross Bins for uart_reset_cg_cc

Bins
cp_dircp_rst_posCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[UartTx] values[0] 2401 1 T1 1 T2 1 T3 1
auto[UartTx] values[1] 16 1 T33 1 T34 1 T106 1
auto[UartTx] values[2] 21 1 T23 1 T18 1 T100 1
auto[UartTx] values[3] 17 1 T5 1 T13 1 T33 1
auto[UartTx] values[4] 20 1 T34 1 T18 1 T137 1
auto[UartTx] values[5] 14 1 T23 1 T35 1 T49 1
auto[UartTx] values[6] 26 1 T5 1 T13 1 T15 1
auto[UartTx] values[7] 28 1 T13 2 T18 1 T107 1
auto[UartTx] values[8] 17 1 T5 1 T100 1 T108 1
auto[UartTx] values[9] 20 1 T13 1 T34 1 T35 1
auto[UartTx] values[10] 25 1 T15 1 T100 2 T19 1
auto[UartRx] values[0] 2194 1 T1 1 T2 1 T3 1
auto[UartRx] values[1] 35 1 T13 1 T33 1 T34 1
auto[UartRx] values[2] 42 1 T5 1 T13 1 T33 2
auto[UartRx] values[3] 36 1 T13 1 T15 1 T33 1
auto[UartRx] values[4] 35 1 T23 1 T34 1 T17 1
auto[UartRx] values[5] 39 1 T23 1 T35 1 T17 1
auto[UartRx] values[6] 42 1 T13 1 T33 1 T35 1
auto[UartRx] values[7] 42 1 T33 1 T34 1 T18 1
auto[UartRx] values[8] 38 1 T13 1 T15 1 T33 1
auto[UartRx] values[9] 42 1 T5 2 T13 1 T35 2
auto[UartRx] values[10] 41 1 T23 1 T18 1 T137 3

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