Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	2255	1			T2	2		T3	1		T5	3
auto[BaudRate115200]	2068	1			T2	1		T5	7		T6	1
auto[BaudRate230400]	2041	1			T1	1		T2	1		T5	9
auto[BaudRate128Kbps]	2076	1			T1	2		T2	2		T3	1
auto[BaudRate256Kbps]	2408	1			T1	1		T2	1		T3	2
auto[BaudRate1Mbps]	1868	1			T1	2		T2	3		T3	2
auto[BaudRate1p5Mbps]	1267	1			T6	5		T8	1		T37	1

---

Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	1499	1			T2	10		T24	29		T16	16
freqs[25]	1471	1			T3	6		T9	9		T31	8
freqs[48]	497	1			T8	11		T113	18		T174	9
freqs[50]	983	1			T13	47		T23	68		T35	112
freqs[100]	890	1			T14	12		T20	7		T43	6

---

Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	238	1			T2	2		T24	2		T16	2
auto[BaudRate9600]	freqs[25]	202	1			T3	1		T9	2		T31	1
auto[BaudRate9600]	freqs[48]	61	1			T8	1		T174	1		T248	1
auto[BaudRate9600]	freqs[50]	128	1			T13	8		T23	11		T35	14
auto[BaudRate9600]	freqs[100]	167	1			T14	12		T20	7		T34	2
auto[BaudRate115200]	freqs[24]	210	1			T2	1		T24	5		T16	3
auto[BaudRate115200]	freqs[25]	189	1			T9	2		T31	1		T116	1
auto[BaudRate115200]	freqs[48]	78	1			T8	2		T113	3		T174	1
auto[BaudRate115200]	freqs[50]	149	1			T13	10		T23	5		T35	9
auto[BaudRate115200]	freqs[100]	135	1			T253	1		T34	5		T114	5
auto[BaudRate230400]	freqs[24]	231	1			T2	1		T24	7		T16	2
auto[BaudRate230400]	freqs[25]	250	1			T9	1		T31	2		T116	3
auto[BaudRate230400]	freqs[48]	55	1			T8	2		T174	2		T127	2
auto[BaudRate230400]	freqs[50]	125	1			T13	3		T23	2		T35	15
auto[BaudRate230400]	freqs[100]	115	1			T253	2		T34	8		T114	4
auto[BaudRate128Kbps]	freqs[24]	223	1			T2	2		T24	2		T16	4
auto[BaudRate128Kbps]	freqs[25]	207	1			T3	1		T9	1		T31	1
auto[BaudRate128Kbps]	freqs[48]	70	1			T113	3		T174	3		T99	2
auto[BaudRate128Kbps]	freqs[50]	170	1			T13	13		T23	15		T35	23
auto[BaudRate128Kbps]	freqs[100]	108	1			T34	2		T114	5		T131	1
auto[BaudRate256Kbps]	freqs[24]	224	1			T2	1		T24	4		T16	3
auto[BaudRate256Kbps]	freqs[25]	251	1			T3	2		T9	1		T31	1
auto[BaudRate256Kbps]	freqs[48]	80	1			T8	3		T113	3		T174	2
auto[BaudRate256Kbps]	freqs[50]	134	1			T13	3		T23	6		T35	12
auto[BaudRate256Kbps]	freqs[100]	128	1			T43	1		T256	2		T253	2
auto[BaudRate1Mbps]	freqs[24]	258	1			T2	3		T24	7		T110	1
auto[BaudRate1Mbps]	freqs[25]	258	1			T3	2		T9	2		T31	2
auto[BaudRate1Mbps]	freqs[48]	58	1			T8	2		T113	3		T248	1
auto[BaudRate1Mbps]	freqs[50]	142	1			T13	6		T23	8		T35	17
auto[BaudRate1Mbps]	freqs[100]	116	1			T43	2		T253	1		T34	4
auto[BaudRate1p5Mbps]	freqs[25]	114	1			T258	1		T257	2		T289	2
auto[BaudRate1p5Mbps]	freqs[48]	95	1			T8	1		T113	6		T99	2
auto[BaudRate1p5Mbps]	freqs[50]	135	1			T13	4		T23	21		T35	22
auto[BaudRate1p5Mbps]	freqs[100]	121	1			T43	3		T34	6		T114	3

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded