Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::rx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::rx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
94.92	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	67	0	67	100.00
Crosses	130	10	120	92.31

Variables for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	65	0	65	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
rx_fifo_level_cg_cc	130	10	120	92.31	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	29565524	1			T1	4		T2	23		T3	39
all_levels[1]	188537	1			T1	1		T4	12		T5	188
all_levels[2]	2422	1			T1	1		T2	2		T4	5
all_levels[3]	1062	1			T2	2		T3	1		T6	3
all_levels[4]	680	1			T8	5		T11	1		T24	3
all_levels[5]	532	1			T2	1		T8	3		T12	1
all_levels[6]	465	1			T1	1		T11	2		T39	1
all_levels[7]	375	1			T12	1		T24	2		T13	2
all_levels[8]	331	1			T2	1		T3	1		T11	1
all_levels[9]	254	1			T8	1		T39	1		T23	2
all_levels[10]	206	1			T23	1		T46	1		T33	2
all_levels[11]	187	1			T23	1		T41	2		T118	1
all_levels[12]	186	1			T1	5		T11	1		T24	1
all_levels[13]	140	1			T1	1		T24	1		T16	1
all_levels[14]	135	1			T24	1		T118	1		T119	1
all_levels[15]	132	1			T24	1		T15	1		T119	3
all_levels[16]	105	1			T24	1		T15	1		T45	1
all_levels[17]	111	1			T24	1		T23	1		T15	1
all_levels[18]	87	1			T12	1		T24	1		T15	1
all_levels[19]	98	1			T119	3		T120	1		T35	1
all_levels[20]	94	1			T39	1		T13	1		T15	1
all_levels[21]	79	1			T2	1		T39	4		T33	1
all_levels[22]	82	1			T35	1		T114	2		T121	1
all_levels[23]	59	1			T24	1		T15	1		T119	1
all_levels[24]	56	1			T2	1		T16	1		T122	1
all_levels[25]	50	1			T33	1		T35	1		T17	1
all_levels[26]	50	1			T118	3		T123	1		T124	1
all_levels[27]	36	1			T41	1		T125	1		T126	1
all_levels[28]	51	1			T24	1		T46	1		T41	1
all_levels[29]	44	1			T13	2		T127	1		T19	1
all_levels[30]	38	1			T128	1		T19	1		T49	1
all_levels[31]	39	1			T68	1		T129	1		T130	1
all_levels[32]	34	1			T46	1		T106	1		T131	1
all_levels[33]	47	1			T123	1		T68	1		T132	1
all_levels[34]	24	1			T133	1		T106	1		T131	1
all_levels[35]	17	1			T129	1		T134	1		T135	1
all_levels[36]	28	1			T39	1		T125	1		T136	2
all_levels[37]	35	1			T137	1		T123	1		T71	2
all_levels[38]	26	1			T138	1		T139	3		T135	2
all_levels[39]	22	1			T140	1		T135	1		T141	1
all_levels[40]	24	1			T34	1		T97	1		T142	1
all_levels[41]	21	1			T114	1		T100	1		T107	1
all_levels[42]	19	1			T35	1		T142	1		T140	1
all_levels[43]	15	1			T33	1		T41	1		T143	1
all_levels[44]	16	1			T123	1		T143	1		T141	1
all_levels[45]	7	1			T46	1		T143	1		T135	1
all_levels[46]	15	1			T121	3		T142	1		T132	1
all_levels[47]	16	1			T133	1		T144	1		T145	1
all_levels[48]	16	1			T100	1		T146	1		T147	2
all_levels[49]	12	1			T37	1		T35	1		T144	2
all_levels[50]	12	1			T106	1		T148	1		T149	1
all_levels[51]	3	1			T35	1		T150	1		T151	1
all_levels[52]	12	1			T1	2		T122	2		T146	1
all_levels[53]	11	1			T152	1		T153	2		T154	1
all_levels[54]	8	1			T155	1		T156	1		T157	1
all_levels[55]	11	1			T114	1		T158	1		T159	1
all_levels[56]	9	1			T160	1		T161	1		T162	1
all_levels[57]	9	1			T17	1		T163	1		T164	1
all_levels[58]	7	1			T137	1		T165	1		T166	1
all_levels[59]	3	1			T167	1		T168	1		T169	1
all_levels[60]	4	1			T36	1		T154	1		T169	1
all_levels[61]	11	1			T23	1		T133	1		T170	2
all_levels[62]	9	1			T39	1		T139	2		T164	1
all_levels[63]	13	1			T135	2		T51	1		T171	1
all_levels[64]	106	1			T46	1		T116	3		T35	1

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29758112

1

T1

10

T2

22

T3

41

auto[1]

4757

1

T1

5

T2

9

T5

2

---

Summary for Cross rx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	10	120	92.31	10

Automatically Generated Cross Bins for rx_fifo_level_cg_cc

Uncovered bins

cp_lvl	cp_rst	COUNT	AT LEAST	NUMBER	STATUS
[all_levels[44] , all_levels[45]]	[auto[1]]	--	--	2
[all_levels[50] , all_levels[51]]	[auto[1]]	--	--	2
[all_levels[54] , all_levels[55]]	[auto[1]]	--	--	2
[all_levels[57] , all_levels[58] , all_levels[59] , all_levels[60]]	[auto[1]]	--	--	4

Covered bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	29561206	1			T1	4		T2	15		T3	39
all_levels[0]	auto[1]	4318	1			T2	8		T5	2		T7	11
all_levels[1]	auto[0]	188451	1			T1	1		T4	12		T5	188
all_levels[1]	auto[1]	86	1			T172	2		T114	1		T173	1
all_levels[2]	auto[0]	2386	1			T1	1		T2	1		T4	5
all_levels[2]	auto[1]	36	1			T2	1		T41	1		T174	2
all_levels[3]	auto[0]	1035	1			T2	2		T3	1		T6	3
all_levels[3]	auto[1]	27	1			T31	2		T175	1		T176	2
all_levels[4]	auto[0]	661	1			T8	5		T11	1		T24	3
all_levels[4]	auto[1]	19	1			T128	1		T137	2		T177	1
all_levels[5]	auto[0]	520	1			T2	1		T8	3		T12	1
all_levels[5]	auto[1]	12	1			T178	2		T179	2		T180	2
all_levels[6]	auto[0]	442	1			T1	1		T11	2		T39	1
all_levels[6]	auto[1]	23	1			T119	1		T170	4		T181	1
all_levels[7]	auto[0]	365	1			T12	1		T24	2		T13	2
all_levels[7]	auto[1]	10	1			T182	2		T183	1		T184	1
all_levels[8]	auto[0]	323	1			T2	1		T3	1		T11	1
all_levels[8]	auto[1]	8	1			T185	1		T186	1		T187	2
all_levels[9]	auto[0]	247	1			T8	1		T39	1		T23	2
all_levels[9]	auto[1]	7	1			T188	1		T189	1		T190	1
all_levels[10]	auto[0]	199	1			T23	1		T46	1		T33	2
all_levels[10]	auto[1]	7	1			T142	2		T191	1		T192	1
all_levels[11]	auto[0]	176	1			T23	1		T41	1		T118	1
all_levels[11]	auto[1]	11	1			T41	1		T120	1		T100	1
all_levels[12]	auto[0]	178	1			T1	1		T11	1		T24	1
all_levels[12]	auto[1]	8	1			T1	4		T41	1		T49	1
all_levels[13]	auto[0]	130	1			T1	1		T24	1		T16	1
all_levels[13]	auto[1]	10	1			T173	1		T139	1		T193	1
all_levels[14]	auto[0]	125	1			T24	1		T118	1		T119	1
all_levels[14]	auto[1]	10	1			T194	2		T72	1		T181	1
all_levels[15]	auto[0]	127	1			T24	1		T15	1		T119	3
all_levels[15]	auto[1]	5	1			T172	1		T194	1		T195	1
all_levels[16]	auto[0]	100	1			T24	1		T15	1		T45	1
all_levels[16]	auto[1]	5	1			T147	1		T196	1		T197	1
all_levels[17]	auto[0]	101	1			T24	1		T23	1		T15	1
all_levels[17]	auto[1]	10	1			T153	1		T198	2		T199	1
all_levels[18]	auto[0]	86	1			T12	1		T24	1		T15	1
all_levels[18]	auto[1]	1	1			T118	1		-	-		-	-
all_levels[19]	auto[0]	90	1			T119	3		T120	1		T35	1
all_levels[19]	auto[1]	8	1			T200	1		T201	1		T202	1
all_levels[20]	auto[0]	86	1			T39	1		T13	1		T15	1
all_levels[20]	auto[1]	8	1			T193	1		T203	1		T204	2
all_levels[21]	auto[0]	69	1			T2	1		T39	1		T33	1
all_levels[21]	auto[1]	10	1			T39	3		T121	1		T205	1
all_levels[22]	auto[0]	74	1			T35	1		T114	2		T121	1
all_levels[22]	auto[1]	8	1			T128	1		T68	2		T206	1
all_levels[23]	auto[0]	55	1			T24	1		T15	1		T119	1
all_levels[23]	auto[1]	4	1			T97	2		T197	1		T207	1
all_levels[24]	auto[0]	51	1			T2	1		T16	1		T122	1
all_levels[24]	auto[1]	5	1			T155	2		T205	1		T208	1
all_levels[25]	auto[0]	41	1			T33	1		T35	1		T17	1
all_levels[25]	auto[1]	9	1			T209	1		T210	4		T211	1
all_levels[26]	auto[0]	44	1			T118	1		T123	1		T124	1
all_levels[26]	auto[1]	6	1			T118	2		T126	1		T212	2
all_levels[27]	auto[0]	34	1			T41	1		T125	1		T126	1
all_levels[27]	auto[1]	2	1			T213	1		T214	1		-	-
all_levels[28]	auto[0]	47	1			T24	1		T46	1		T41	1
all_levels[28]	auto[1]	4	1			T215	1		T216	3		-	-
all_levels[29]	auto[0]	42	1			T13	2		T127	1		T19	1
all_levels[29]	auto[1]	2	1			T191	1		T217	1		-	-
all_levels[30]	auto[0]	36	1			T128	1		T19	1		T49	1
all_levels[30]	auto[1]	2	1			T218	1		T198	1		-	-
all_levels[31]	auto[0]	36	1			T68	1		T129	1		T130	1
all_levels[31]	auto[1]	3	1			T219	1		T220	2		-	-
all_levels[32]	auto[0]	30	1			T46	1		T106	1		T131	1
all_levels[32]	auto[1]	4	1			T182	3		T221	1		-	-
all_levels[33]	auto[0]	35	1			T123	1		T68	1		T132	1
all_levels[33]	auto[1]	12	1			T143	2		T222	2		T223	1
all_levels[34]	auto[0]	23	1			T133	1		T106	1		T131	1
all_levels[34]	auto[1]	1	1			T181	1		-	-		-	-
all_levels[35]	auto[0]	16	1			T129	1		T134	1		T135	1
all_levels[35]	auto[1]	1	1			T224	1		-	-		-	-
all_levels[36]	auto[0]	22	1			T39	1		T125	1		T136	1
all_levels[36]	auto[1]	6	1			T136	1		T225	2		T166	2
all_levels[37]	auto[0]	32	1			T137	1		T123	1		T71	1
all_levels[37]	auto[1]	3	1			T71	1		T159	2		-	-
all_levels[38]	auto[0]	20	1			T138	1		T139	1		T135	2
all_levels[38]	auto[1]	6	1			T139	2		T226	2		T227	1
all_levels[39]	auto[0]	19	1			T140	1		T135	1		T141	1
all_levels[39]	auto[1]	3	1			T228	3		-	-		-	-
all_levels[40]	auto[0]	23	1			T34	1		T97	1		T142	1
all_levels[40]	auto[1]	1	1			T135	1		-	-		-	-
all_levels[41]	auto[0]	20	1			T114	1		T100	1		T107	1
all_levels[41]	auto[1]	1	1			T229	1		-	-		-	-
all_levels[42]	auto[0]	16	1			T35	1		T142	1		T140	1
all_levels[42]	auto[1]	3	1			T230	2		T231	1		-	-
all_levels[43]	auto[0]	14	1			T33	1		T41	1		T143	1
all_levels[43]	auto[1]	1	1			T232	1		-	-		-	-
all_levels[44]	auto[0]	16	1			T123	1		T143	1		T141	1
all_levels[45]	auto[0]	7	1			T46	1		T143	1		T135	1
all_levels[46]	auto[0]	12	1			T121	1		T142	1		T132	1
all_levels[46]	auto[1]	3	1			T121	2		T233	1		-	-
all_levels[47]	auto[0]	14	1			T133	1		T144	1		T145	1
all_levels[47]	auto[1]	2	1			T197	1		T234	1		-	-
all_levels[48]	auto[0]	13	1			T100	1		T146	1		T147	1
all_levels[48]	auto[1]	3	1			T147	1		T148	1		T227	1
all_levels[49]	auto[0]	11	1			T37	1		T35	1		T144	1
all_levels[49]	auto[1]	1	1			T144	1		-	-		-	-
all_levels[50]	auto[0]	12	1			T106	1		T148	1		T149	1
all_levels[51]	auto[0]	3	1			T35	1		T150	1		T151	1
all_levels[52]	auto[0]	10	1			T1	1		T122	1		T146	1
all_levels[52]	auto[1]	2	1			T1	1		T122	1		-	-
all_levels[53]	auto[0]	10	1			T152	1		T153	2		T154	1
all_levels[53]	auto[1]	1	1			T235	1		-	-		-	-
all_levels[54]	auto[0]	8	1			T155	1		T156	1		T157	1
all_levels[55]	auto[0]	11	1			T114	1		T158	1		T159	1
all_levels[56]	auto[0]	7	1			T160	1		T161	1		T162	1
all_levels[56]	auto[1]	2	1			T236	2		-	-		-	-
all_levels[57]	auto[0]	9	1			T17	1		T163	1		T164	1
all_levels[58]	auto[0]	7	1			T137	1		T165	1		T166	1
all_levels[59]	auto[0]	3	1			T167	1		T168	1		T169	1
all_levels[60]	auto[0]	4	1			T36	1		T154	1		T169	1
all_levels[61]	auto[0]	10	1			T23	1		T133	1		T170	1
all_levels[61]	auto[1]	1	1			T170	1		-	-		-	-
all_levels[62]	auto[0]	8	1			T39	1		T139	1		T164	1
all_levels[62]	auto[1]	1	1			T139	1		-	-		-	-
all_levels[63]	auto[0]	9	1			T135	2		T51	1		T171	1
all_levels[63]	auto[1]	4	1			T237	4		-	-		-	-
all_levels[64]	auto[0]	95	1			T46	1		T116	2		T35	1
all_levels[64]	auto[1]	11	1			T116	1		T208	3		T238	1