Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	108320	1			T1	9		T2	5		T3	13
all_pins[1]	108320	1			T1	9		T2	5		T3	13
all_pins[2]	108320	1			T1	9		T2	5		T3	13
all_pins[3]	108320	1			T1	9		T2	5		T3	13
all_pins[4]	108320	1			T1	9		T2	5		T3	13
all_pins[5]	108320	1			T1	9		T2	5		T3	13
all_pins[6]	108320	1			T1	9		T2	5		T3	13
all_pins[7]	108320	1			T1	9		T2	5		T3	13

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	836914	1			T1	65		T2	37		T3	99
values[0x1]	29646	1			T1	7		T2	3		T3	5
transitions[0x0=>0x1]	28187	1			T1	5		T2	3		T3	5
transitions[0x1=>0x0]	27748	1			T1	4		T2	3		T3	4

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	85643	1			T1	6		T2	4		T3	11
all_pins[0]	values[0x1]	22677	1			T1	3		T2	1		T3	2
all_pins[0]	transitions[0x0=>0x1]	21864	1			T1	3		T2	1		T3	2
all_pins[0]	transitions[0x1=>0x0]	1127	1			T12	4		T13	3		T15	1
all_pins[1]	values[0x0]	106380	1			T1	9		T2	5		T3	13
all_pins[1]	values[0x1]	1940	1			T5	1		T12	4		T13	4
all_pins[1]	transitions[0x0=>0x1]	1824	1			T5	1		T12	2		T13	4
all_pins[1]	transitions[0x1=>0x0]	2488	1			T1	2		T2	1		T3	3
all_pins[2]	values[0x0]	105716	1			T1	7		T2	4		T3	10
all_pins[2]	values[0x1]	2604	1			T1	2		T2	1		T3	3
all_pins[2]	transitions[0x0=>0x1]	2525	1			T2	1		T3	3		T4	3
all_pins[2]	transitions[0x1=>0x0]	224	1			T13	2		T46	1		T34	1
all_pins[3]	values[0x0]	108017	1			T1	7		T2	5		T3	13
all_pins[3]	values[0x1]	303	1			T1	2		T12	1		T13	2
all_pins[3]	transitions[0x0=>0x1]	270	1			T1	2		T12	1		T13	2
all_pins[3]	transitions[0x1=>0x0]	463	1			T13	1		T15	7		T34	2
all_pins[4]	values[0x0]	107824	1			T1	9		T2	5		T3	13
all_pins[4]	values[0x1]	496	1			T13	1		T15	9		T34	2
all_pins[4]	transitions[0x0=>0x1]	418	1			T13	1		T15	5		T21	2
all_pins[4]	transitions[0x1=>0x0]	165	1			T5	4		T13	2		T34	2
all_pins[5]	values[0x0]	108077	1			T1	9		T2	5		T3	13
all_pins[5]	values[0x1]	243	1			T5	4		T13	2		T15	4
all_pins[5]	transitions[0x0=>0x1]	197	1			T13	2		T15	4		T34	2
all_pins[5]	transitions[0x1=>0x0]	829	1			T2	1		T4	5		T8	1
all_pins[6]	values[0x0]	107445	1			T1	9		T2	4		T3	13
all_pins[6]	values[0x1]	875	1			T2	1		T4	5		T5	4
all_pins[6]	transitions[0x0=>0x1]	808	1			T2	1		T4	5		T5	3
all_pins[6]	transitions[0x1=>0x0]	441	1			T11	1		T13	3		T15	3
all_pins[7]	values[0x0]	107812	1			T1	9		T2	5		T3	13
all_pins[7]	values[0x1]	508	1			T5	1		T11	1		T13	3
all_pins[7]	transitions[0x0=>0x1]	281	1			T5	1		T11	1		T13	1
all_pins[7]	transitions[0x1=>0x0]	22011	1			T1	2		T2	1		T3	1