Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::tx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::tx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	35	0	35	100.00
Crosses	66	0	66	100.00

Variables for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	33	0	33	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tx_fifo_level_cg_cc	66	0	66	100.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	6751980	1			T1	9		T2	22		T3	10
all_levels[1]	1937278	1			T2	2		T3	1		T5	11983
all_levels[2]	319471	1			T3	1		T5	2019		T8	2
all_levels[3]	405258	1			T2	1		T3	2		T4	1
all_levels[4]	289075	1			T5	2201		T9	1		T11	2
all_levels[5]	217034	1			T3	2		T4	3		T5	1999
all_levels[6]	235266	1			T2	1		T3	2		T5	1094
all_levels[7]	355661	1			T2	1		T5	1651		T8	1
all_levels[8]	302548	1			T5	1561		T6	16		T8	8
all_levels[9]	190648	1			T1	2		T2	2		T4	1
all_levels[10]	188746	1			T3	3		T4	2		T5	1816
all_levels[11]	204631	1			T5	1636		T11	2		T12	2
all_levels[12]	307764	1			T5	1292		T37	2		T24	588
all_levels[13]	195260	1			T4	1		T5	1696		T8	13
all_levels[14]	167281	1			T4	1		T5	1225		T6	14
all_levels[15]	204451	1			T4	55		T5	1546		T6	7
all_levels[16]	276832	1			T5	1638		T8	2		T24	574
all_levels[17]	310359	1			T3	2		T5	1303		T9	7
all_levels[18]	228644	1			T5	1539		T31	1		T24	571
all_levels[19]	183525	1			T5	1499		T24	580		T13	12
all_levels[20]	243253	1			T5	1370		T8	5		T24	565
all_levels[21]	161049	1			T3	2		T5	1332		T8	1
all_levels[22]	231922	1			T3	12		T5	1053		T8	12
all_levels[23]	159050	1			T5	1382		T6	2		T8	7
all_levels[24]	166525	1			T5	1353		T6	7		T8	9
all_levels[25]	146885	1			T5	1255		T11	8		T39	4
all_levels[26]	227132	1			T1	5		T5	1620		T9	1
all_levels[27]	197572	1			T5	1454		T38	3		T24	561
all_levels[28]	326603	1			T5	1909		T37	3		T24	577
all_levels[29]	181108	1			T5	1572		T6	2		T24	534
all_levels[30]	374994	1			T5	1635		T24	646		T13	6
all_levels[31]	429531	1			T5	3910		T6	32		T37	2
all_levels[32]	13645122	1			T3	5		T5	54769		T6	237

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29758112

1

T1

10

T2

22

T3

41

auto[1]

4346

1

T1

6

T2

7

T3

1

---

Summary for Cross tx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	66	0	66	100.00

Automatically Generated Cross Bins for tx_fifo_level_cg_cc

Bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	6749621	1			T1	7		T2	15		T3	10
all_levels[0]	auto[1]	2359	1			T1	2		T2	7		T5	1
all_levels[1]	auto[0]	1936926	1			T2	2		T3	1		T5	11983
all_levels[1]	auto[1]	352	1			T120	3		T35	4		T172	6
all_levels[2]	auto[0]	319425	1			T3	1		T5	2019		T8	2
all_levels[2]	auto[1]	46	1			T174	2		T100	1		T292	1
all_levels[3]	auto[0]	405100	1			T2	1		T3	2		T4	1
all_levels[3]	auto[1]	158	1			T9	1		T118	1		T36	4
all_levels[4]	auto[0]	289047	1			T5	2201		T9	1		T11	2
all_levels[4]	auto[1]	28	1			T38	3		T130	1		T293	2
all_levels[5]	auto[0]	217010	1			T3	2		T4	3		T5	1999
all_levels[5]	auto[1]	24	1			T15	2		T126	1		T294	1
all_levels[6]	auto[0]	235242	1			T2	1		T3	2		T5	1094
all_levels[6]	auto[1]	24	1			T120	2		T114	2		T257	1
all_levels[7]	auto[0]	355535	1			T2	1		T5	1651		T8	1
all_levels[7]	auto[1]	126	1			T18	2		T100	7		T19	3
all_levels[8]	auto[0]	302518	1			T5	1561		T6	16		T8	8
all_levels[8]	auto[1]	30	1			T119	3		T122	1		T182	2
all_levels[9]	auto[0]	190622	1			T1	2		T2	2		T4	1
all_levels[9]	auto[1]	26	1			T118	2		T172	1		T100	1
all_levels[10]	auto[0]	188715	1			T3	3		T4	2		T5	1816
all_levels[10]	auto[1]	31	1			T8	1		T111	1		T204	1
all_levels[11]	auto[0]	204609	1			T5	1636		T11	2		T12	2
all_levels[11]	auto[1]	22	1			T41	4		T249	1		T252	1
all_levels[12]	auto[0]	307729	1			T5	1292		T37	2		T24	588
all_levels[12]	auto[1]	35	1			T16	1		T46	1		T50	1
all_levels[13]	auto[0]	195229	1			T4	1		T5	1696		T8	13
all_levels[13]	auto[1]	31	1			T110	1		T279	3		T124	1
all_levels[14]	auto[0]	167259	1			T4	1		T5	1225		T6	14
all_levels[14]	auto[1]	22	1			T174	2		T122	1		T97	2
all_levels[15]	auto[0]	204262	1			T4	55		T5	1546		T6	7
all_levels[15]	auto[1]	189	1			T39	1		T282	11		T18	13
all_levels[16]	auto[0]	276820	1			T5	1638		T8	2		T24	574
all_levels[16]	auto[1]	12	1			T173	2		T100	1		T177	1
all_levels[17]	auto[0]	310334	1			T3	2		T5	1303		T9	5
all_levels[17]	auto[1]	25	1			T9	2		T120	1		T97	2
all_levels[18]	auto[0]	228621	1			T5	1539		T31	1		T24	571
all_levels[18]	auto[1]	23	1			T121	2		T205	1		T188	1
all_levels[19]	auto[0]	183500	1			T5	1499		T24	580		T13	12
all_levels[19]	auto[1]	25	1			T45	1		T174	2		T137	1
all_levels[20]	auto[0]	243230	1			T5	1370		T8	5		T24	565
all_levels[20]	auto[1]	23	1			T40	1		T175	2		T176	1
all_levels[21]	auto[0]	161030	1			T3	2		T5	1332		T8	1
all_levels[21]	auto[1]	19	1			T74	1		T50	1		T218	1
all_levels[22]	auto[0]	231900	1			T3	12		T5	1053		T8	12
all_levels[22]	auto[1]	22	1			T41	1		T260	1		T176	2
all_levels[23]	auto[0]	159029	1			T5	1382		T6	2		T8	7
all_levels[23]	auto[1]	21	1			T49	1		T72	1		T143	1
all_levels[24]	auto[0]	166505	1			T5	1353		T6	7		T8	9
all_levels[24]	auto[1]	20	1			T31	3		T269	3		T155	2
all_levels[25]	auto[0]	146859	1			T5	1255		T11	8		T39	2
all_levels[25]	auto[1]	26	1			T39	2		T41	2		T128	1
all_levels[26]	auto[0]	227116	1			T1	1		T5	1620		T9	1
all_levels[26]	auto[1]	16	1			T1	4		T295	2		T296	1
all_levels[27]	auto[0]	197554	1			T5	1454		T38	2		T24	561
all_levels[27]	auto[1]	18	1			T38	1		T41	1		T118	1
all_levels[28]	auto[0]	326578	1			T5	1909		T37	3		T24	577
all_levels[28]	auto[1]	25	1			T111	2		T172	1		T264	2
all_levels[29]	auto[0]	181091	1			T5	1572		T6	2		T24	534
all_levels[29]	auto[1]	17	1			T297	1		T298	1		T299	2
all_levels[30]	auto[0]	374977	1			T5	1635		T24	646		T13	6
all_levels[30]	auto[1]	17	1			T253	1		T250	2		T49	1
all_levels[31]	auto[0]	429513	1			T5	3910		T6	32		T37	2
all_levels[31]	auto[1]	18	1			T137	1		T97	2		T71	1
all_levels[32]	auto[0]	13644606	1			T3	4		T5	54766		T6	237
all_levels[32]	auto[1]	516	1			T3	1		T5	3		T9	2