Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.55	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	4	44	91.67

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	4	44	91.67	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	860	1			T5	4		T13	7		T15	18
all_values[1]	860	1			T5	4		T13	7		T15	18
all_values[2]	860	1			T5	4		T13	7		T15	18
all_values[3]	860	1			T5	4		T13	7		T15	18
all_values[4]	860	1			T5	4		T13	7		T15	18
all_values[5]	860	1			T5	4		T13	7		T15	18
all_values[6]	860	1			T5	4		T13	7		T15	18
all_values[7]	860	1			T5	4		T13	7		T15	18

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3699

1

T5

17

T13

21

T15

93

auto[1]

3181

1

T5

15

T13

35

T15

51

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2500

1

T5

8

T13

23

T15

59

auto[1]

4380

1

T5

24

T13

33

T15

85

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4047

1

T5

16

T13

37

T15

91

auto[1]

2833

1

T5

16

T13

19

T15

53

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	4	44	91.67	4
Automatically Generated Cross Bins	48	4	44	91.67	4
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	*	[auto[0]]	--	--	2
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	277	1			T5	1		T13	2		T15	5
all_values[0]	auto[0]	auto[1]	auto[1]	241	1			T13	3		T15	5		T33	1
all_values[0]	auto[1]	auto[0]	auto[1]	177	1			T13	2		T15	6		T33	2
all_values[0]	auto[1]	auto[1]	auto[1]	165	1			T5	3		T15	2		T34	3
all_values[1]	auto[0]	auto[0]	auto[0]	279	1			T5	1		T15	9		T33	2
all_values[1]	auto[0]	auto[1]	auto[0]	229	1			T5	2		T13	3		T15	3
all_values[1]	auto[1]	auto[0]	auto[1]	193	1			T15	4		T33	1		T34	4
all_values[1]	auto[1]	auto[1]	auto[1]	159	1			T5	1		T13	4		T15	2
all_values[2]	auto[0]	auto[0]	auto[0]	195	1			T5	4		T13	3		T15	11
all_values[2]	auto[0]	auto[0]	auto[1]	83	1			T13	1		T34	1		T35	3
all_values[2]	auto[0]	auto[1]	auto[0]	155	1			T13	2		T15	1		T33	2
all_values[2]	auto[0]	auto[1]	auto[1]	82	1			T15	1		T34	3		T35	2
all_values[2]	auto[1]	auto[0]	auto[1]	183	1			T15	3		T33	1		T34	4
all_values[2]	auto[1]	auto[1]	auto[1]	162	1			T13	1		T15	2		T34	3
all_values[3]	auto[0]	auto[0]	auto[0]	180	1			T5	1		T13	1		T15	4
all_values[3]	auto[0]	auto[0]	auto[1]	96	1			T5	1		T15	2		T35	2
all_values[3]	auto[0]	auto[1]	auto[0]	149	1			T13	4		T15	4		T33	1
all_values[3]	auto[0]	auto[1]	auto[1]	69	1			T13	1		T15	1		T36	1
all_values[3]	auto[1]	auto[0]	auto[1]	212	1			T5	2		T15	6		T33	1
all_values[3]	auto[1]	auto[1]	auto[1]	154	1			T13	1		T15	1		T33	1
all_values[4]	auto[0]	auto[0]	auto[0]	185	1			T13	2		T15	4		T33	1
all_values[4]	auto[0]	auto[0]	auto[1]	90	1			T5	2		T13	1		T15	1
all_values[4]	auto[0]	auto[1]	auto[0]	149	1			T13	1		T15	1		T34	3
all_values[4]	auto[0]	auto[1]	auto[1]	79	1			T13	1		T15	4		T34	1
all_values[4]	auto[1]	auto[0]	auto[1]	190	1			T5	2		T13	2		T15	3
all_values[4]	auto[1]	auto[1]	auto[1]	167	1			T15	5		T34	3		T35	3
all_values[5]	auto[0]	auto[0]	auto[0]	192	1			T15	4		T33	2		T34	3
all_values[5]	auto[0]	auto[0]	auto[1]	75	1			T13	1		T15	1		T34	1
all_values[5]	auto[0]	auto[1]	auto[0]	149	1			T15	3		T33	1		T34	2
all_values[5]	auto[0]	auto[1]	auto[1]	93	1			T5	1		T13	1		T15	2
all_values[5]	auto[1]	auto[0]	auto[1]	186	1			T13	1		T15	6		T33	1
all_values[5]	auto[1]	auto[1]	auto[1]	165	1			T5	3		T13	4		T15	2
all_values[6]	auto[0]	auto[0]	auto[0]	189	1			T13	4		T15	7		T33	1
all_values[6]	auto[0]	auto[0]	auto[1]	81	1			T15	2		T33	1		T36	1
all_values[6]	auto[0]	auto[1]	auto[0]	152	1			T13	2		T34	4		T35	6
all_values[6]	auto[0]	auto[1]	auto[1]	86	1			T5	2		T15	3		T34	1
all_values[6]	auto[1]	auto[0]	auto[1]	196	1			T13	1		T15	4		T33	2
all_values[6]	auto[1]	auto[1]	auto[1]	156	1			T5	2		T15	2		T34	2
all_values[7]	auto[0]	auto[0]	auto[0]	152	1			T15	6		T34	6		T35	3
all_values[7]	auto[0]	auto[0]	auto[1]	93	1			T5	1		T15	2		T34	1
all_values[7]	auto[0]	auto[1]	auto[0]	145	1			T13	1		T15	2		T35	4
all_values[7]	auto[0]	auto[1]	auto[1]	102	1			T13	3		T15	3		T33	1
all_values[7]	auto[1]	auto[0]	auto[1]	195	1			T5	2		T15	3		T33	2
all_values[7]	auto[1]	auto[1]	auto[1]	173	1			T5	1		T13	3		T15	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal