| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 99.27 | 99.27 | 97.95 | 100.00 | 98.80 | 100.00 | 99.59 |
| T1255 | /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.680643363 | Jun 04 12:49:45 PM PDT 24 | Jun 04 12:49:46 PM PDT 24 | 34051209 ps | ||
| T1256 | /workspace/coverage/cover_reg_top/20.uart_intr_test.4284991324 | Jun 04 12:50:01 PM PDT 24 | Jun 04 12:50:04 PM PDT 24 | 13509451 ps | ||
| T1257 | /workspace/coverage/cover_reg_top/11.uart_tl_errors.144367380 | Jun 04 12:49:49 PM PDT 24 | Jun 04 12:49:51 PM PDT 24 | 20794386 ps | ||
| T1258 | /workspace/coverage/cover_reg_top/3.uart_tl_errors.3700198136 | Jun 04 12:49:42 PM PDT 24 | Jun 04 12:49:45 PM PDT 24 | 141182436 ps | ||
| T1259 | /workspace/coverage/cover_reg_top/26.uart_intr_test.1578362672 | Jun 04 12:49:57 PM PDT 24 | Jun 04 12:49:59 PM PDT 24 | 30300444 ps | ||
| T1260 | /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.1413098935 | Jun 04 12:49:57 PM PDT 24 | Jun 04 12:49:58 PM PDT 24 | 71264540 ps | ||
| T1261 | /workspace/coverage/cover_reg_top/32.uart_intr_test.2060597312 | Jun 04 12:49:59 PM PDT 24 | Jun 04 12:50:02 PM PDT 24 | 13870449 ps | ||
| T1262 | /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.2805724119 | Jun 04 12:50:01 PM PDT 24 | Jun 04 12:50:04 PM PDT 24 | 156971233 ps | ||
| T1263 | /workspace/coverage/cover_reg_top/3.uart_csr_rw.2804158818 | Jun 04 12:49:41 PM PDT 24 | Jun 04 12:49:42 PM PDT 24 | 22473918 ps | ||
| T1264 | /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.1618210844 | Jun 04 12:49:49 PM PDT 24 | Jun 04 12:49:52 PM PDT 24 | 108937781 ps | ||
| T1265 | /workspace/coverage/cover_reg_top/6.uart_csr_rw.399734455 | Jun 04 12:49:48 PM PDT 24 | Jun 04 12:49:49 PM PDT 24 | 16485662 ps | ||
| T1266 | /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.524970856 | Jun 04 12:50:00 PM PDT 24 | Jun 04 12:50:03 PM PDT 24 | 126384661 ps | ||
| T1267 | /workspace/coverage/cover_reg_top/5.uart_csr_rw.3786780990 | Jun 04 12:49:46 PM PDT 24 | Jun 04 12:49:47 PM PDT 24 | 49266155 ps | ||
| T1268 | /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.1734624431 | Jun 04 12:50:00 PM PDT 24 | Jun 04 12:50:03 PM PDT 24 | 45349966 ps | ||
| T1269 | /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.1883506184 | Jun 04 12:49:39 PM PDT 24 | Jun 04 12:49:41 PM PDT 24 | 254445499 ps | ||
| T1270 | /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.397395228 | Jun 04 12:49:47 PM PDT 24 | Jun 04 12:49:49 PM PDT 24 | 244781380 ps | ||
| T1271 | /workspace/coverage/cover_reg_top/46.uart_intr_test.1252136306 | Jun 04 12:50:12 PM PDT 24 | Jun 04 12:50:14 PM PDT 24 | 12621600 ps | ||
| T1272 | /workspace/coverage/cover_reg_top/12.uart_tl_errors.1487579998 | Jun 04 12:49:59 PM PDT 24 | Jun 04 12:50:03 PM PDT 24 | 126959160 ps | ||
| T1273 | /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.4294284082 | Jun 04 12:49:42 PM PDT 24 | Jun 04 12:49:43 PM PDT 24 | 55060281 ps | ||
| T1274 | /workspace/coverage/cover_reg_top/24.uart_intr_test.3458871595 | Jun 04 12:49:58 PM PDT 24 | Jun 04 12:50:00 PM PDT 24 | 13626280 ps | ||
| T1275 | /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.3485506320 | Jun 04 12:49:39 PM PDT 24 | Jun 04 12:49:41 PM PDT 24 | 15918686 ps | ||
| T117 | /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.4231742510 | Jun 04 12:50:02 PM PDT 24 | Jun 04 12:50:05 PM PDT 24 | 75115104 ps | ||
| T1276 | /workspace/coverage/cover_reg_top/40.uart_intr_test.1351267500 | Jun 04 12:50:02 PM PDT 24 | Jun 04 12:50:04 PM PDT 24 | 48152417 ps | ||
| T1277 | /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.891479377 | Jun 04 12:49:38 PM PDT 24 | Jun 04 12:49:40 PM PDT 24 | 43097759 ps | ||
| T1278 | /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.4143213360 | Jun 04 12:49:40 PM PDT 24 | Jun 04 12:49:41 PM PDT 24 | 45274829 ps | ||
| T1279 | /workspace/coverage/cover_reg_top/31.uart_intr_test.1797751535 | Jun 04 12:50:03 PM PDT 24 | Jun 04 12:50:05 PM PDT 24 | 80091531 ps | ||
| T1280 | /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.855250556 | Jun 04 12:49:48 PM PDT 24 | Jun 04 12:49:51 PM PDT 24 | 47990246 ps | ||
| T1281 | /workspace/coverage/cover_reg_top/39.uart_intr_test.1555957565 | Jun 04 12:50:03 PM PDT 24 | Jun 04 12:50:05 PM PDT 24 | 24530150 ps | ||
| T1282 | /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.1252305034 | Jun 04 12:49:47 PM PDT 24 | Jun 04 12:49:49 PM PDT 24 | 78704819 ps | ||
| T1283 | /workspace/coverage/cover_reg_top/18.uart_tl_errors.1958764631 | Jun 04 12:49:56 PM PDT 24 | Jun 04 12:49:59 PM PDT 24 | 239851301 ps | ||
| T1284 | /workspace/coverage/cover_reg_top/33.uart_intr_test.3589400966 | Jun 04 12:50:01 PM PDT 24 | Jun 04 12:50:04 PM PDT 24 | 13515305 ps | ||
| T1285 | /workspace/coverage/cover_reg_top/29.uart_intr_test.2922378986 | Jun 04 12:50:00 PM PDT 24 | Jun 04 12:50:03 PM PDT 24 | 14663556 ps | ||
| T1286 | /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.2392785644 | Jun 04 12:49:50 PM PDT 24 | Jun 04 12:49:52 PM PDT 24 | 86752443 ps | ||
| T1287 | /workspace/coverage/cover_reg_top/7.uart_tl_errors.1351290612 | Jun 04 12:49:46 PM PDT 24 | Jun 04 12:49:48 PM PDT 24 | 30444034 ps | ||
| T1288 | /workspace/coverage/cover_reg_top/17.uart_intr_test.2648494112 | Jun 04 12:49:58 PM PDT 24 | Jun 04 12:50:00 PM PDT 24 | 40557988 ps | ||
| T1289 | /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.2905306607 | Jun 04 12:49:37 PM PDT 24 | Jun 04 12:49:38 PM PDT 24 | 228770463 ps | ||
| T1290 | /workspace/coverage/cover_reg_top/9.uart_csr_rw.3107074025 | Jun 04 12:49:49 PM PDT 24 | Jun 04 12:49:50 PM PDT 24 | 16421864 ps | ||
| T1291 | /workspace/coverage/cover_reg_top/13.uart_tl_errors.2981779252 | Jun 04 12:49:58 PM PDT 24 | Jun 04 12:50:02 PM PDT 24 | 33978327 ps | ||
| T62 | /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.1645578905 | Jun 04 12:49:35 PM PDT 24 | Jun 04 12:49:37 PM PDT 24 | 140995818 ps | ||
| T1292 | /workspace/coverage/cover_reg_top/19.uart_intr_test.1878344214 | Jun 04 12:49:59 PM PDT 24 | Jun 04 12:50:01 PM PDT 24 | 51076695 ps | ||
| T1293 | /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.2445567306 | Jun 04 12:49:50 PM PDT 24 | Jun 04 12:49:52 PM PDT 24 | 174945379 ps | ||
| T1294 | /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.213088571 | Jun 04 12:50:00 PM PDT 24 | Jun 04 12:50:03 PM PDT 24 | 96076492 ps | ||
| T1295 | /workspace/coverage/cover_reg_top/34.uart_intr_test.489739215 | Jun 04 12:50:00 PM PDT 24 | Jun 04 12:50:03 PM PDT 24 | 13287809 ps | ||
| T1296 | /workspace/coverage/cover_reg_top/15.uart_tl_errors.2512988956 | Jun 04 12:49:56 PM PDT 24 | Jun 04 12:49:59 PM PDT 24 | 24658162 ps | ||
| T1297 | /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.3960181003 | Jun 04 12:49:58 PM PDT 24 | Jun 04 12:50:00 PM PDT 24 | 16097012 ps | ||
| T1298 | /workspace/coverage/cover_reg_top/17.uart_tl_errors.1321410245 | Jun 04 12:49:58 PM PDT 24 | Jun 04 12:50:01 PM PDT 24 | 105409801 ps | ||
| T1299 | /workspace/coverage/cover_reg_top/15.uart_intr_test.983311741 | Jun 04 12:49:58 PM PDT 24 | Jun 04 12:50:01 PM PDT 24 | 42971794 ps | ||
| T1300 | /workspace/coverage/cover_reg_top/14.uart_tl_errors.3196790497 | Jun 04 12:50:00 PM PDT 24 | Jun 04 12:50:04 PM PDT 24 | 32757671 ps | ||
| T63 | /workspace/coverage/cover_reg_top/2.uart_csr_rw.1629884351 | Jun 04 12:49:43 PM PDT 24 | Jun 04 12:49:44 PM PDT 24 | 11166242 ps | ||
| T1301 | /workspace/coverage/cover_reg_top/19.uart_tl_errors.3428967025 | Jun 04 12:50:02 PM PDT 24 | Jun 04 12:50:06 PM PDT 24 | 86954089 ps | ||
| T1302 | /workspace/coverage/cover_reg_top/41.uart_intr_test.2618860500 | Jun 04 12:50:10 PM PDT 24 | Jun 04 12:50:11 PM PDT 24 | 35140885 ps | ||
| T1303 | /workspace/coverage/cover_reg_top/7.uart_intr_test.2889350036 | Jun 04 12:49:47 PM PDT 24 | Jun 04 12:49:49 PM PDT 24 | 27771130 ps | ||
| T1304 | /workspace/coverage/cover_reg_top/5.uart_intr_test.3465585959 | Jun 04 12:49:48 PM PDT 24 | Jun 04 12:49:50 PM PDT 24 | 12927691 ps | ||
| T1305 | /workspace/coverage/cover_reg_top/16.uart_tl_errors.2496953486 | Jun 04 12:49:57 PM PDT 24 | Jun 04 12:50:01 PM PDT 24 | 863309566 ps | ||
| T1306 | /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.1558819397 | Jun 04 12:49:47 PM PDT 24 | Jun 04 12:49:49 PM PDT 24 | 18372220 ps | ||
| T1307 | /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.958666920 | Jun 04 12:49:52 PM PDT 24 | Jun 04 12:49:54 PM PDT 24 | 342862544 ps | ||
| T1308 | /workspace/coverage/cover_reg_top/8.uart_intr_test.982710988 | Jun 04 12:49:48 PM PDT 24 | Jun 04 12:49:50 PM PDT 24 | 34674457 ps | ||
| T1309 | /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.3718283967 | Jun 04 12:49:41 PM PDT 24 | Jun 04 12:49:42 PM PDT 24 | 18356719 ps | ||
| T1310 | /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.2811175165 | Jun 04 12:49:47 PM PDT 24 | Jun 04 12:49:48 PM PDT 24 | 25665695 ps | ||
| T1311 | /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.719456077 | Jun 04 12:49:42 PM PDT 24 | Jun 04 12:49:43 PM PDT 24 | 26196490 ps | ||
| T1312 | /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.512742712 | Jun 04 12:49:55 PM PDT 24 | Jun 04 12:49:57 PM PDT 24 | 418355717 ps | ||
| T1313 | /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.590678292 | Jun 04 12:49:58 PM PDT 24 | Jun 04 12:50:01 PM PDT 24 | 136229109 ps | ||
| T1314 | /workspace/coverage/cover_reg_top/28.uart_intr_test.2780026917 | Jun 04 12:50:01 PM PDT 24 | Jun 04 12:50:04 PM PDT 24 | 25016896 ps | ||
| T64 | /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.1136834217 | Jun 04 12:49:37 PM PDT 24 | Jun 04 12:49:40 PM PDT 24 | 650937838 ps | ||
| T1315 | /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.2883964343 | Jun 04 12:49:50 PM PDT 24 | Jun 04 12:49:52 PM PDT 24 | 95889070 ps | ||
| T1316 | /workspace/coverage/cover_reg_top/49.uart_intr_test.3544048534 | Jun 04 12:50:11 PM PDT 24 | Jun 04 12:50:12 PM PDT 24 | 12909014 ps | ||
| T1317 | /workspace/coverage/cover_reg_top/37.uart_intr_test.3764036891 | Jun 04 12:50:00 PM PDT 24 | Jun 04 12:50:03 PM PDT 24 | 40849727 ps |
| Test location | /workspace/coverage/default/81.uart_stress_all_with_rand_reset.2317100612 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 110129187490 ps |
| CPU time | 601.73 seconds |
| Started | Jun 04 12:41:16 PM PDT 24 |
| Finished | Jun 04 12:51:18 PM PDT 24 |
| Peak memory | 216016 kb |
| Host | smart-646c324c-68d2-4209-90da-be82cbc1b845 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317100612 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 81.uart_stress_all_with_rand_reset.2317100612 |
| Directory | /workspace/81.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/85.uart_stress_all_with_rand_reset.107485338 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 223253787792 ps |
| CPU time | 817.96 seconds |
| Started | Jun 04 12:41:17 PM PDT 24 |
| Finished | Jun 04 12:54:56 PM PDT 24 |
| Peak memory | 225088 kb |
| Host | smart-cedf0126-abbf-49d1-9f8d-d7e3dbfc5b56 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107485338 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 85.uart_stress_all_with_rand_reset.107485338 |
| Directory | /workspace/85.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/13.uart_stress_all_with_rand_reset.4160659003 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 591702798449 ps |
| CPU time | 634.28 seconds |
| Started | Jun 04 12:37:48 PM PDT 24 |
| Finished | Jun 04 12:48:23 PM PDT 24 |
| Peak memory | 216704 kb |
| Host | smart-e4b20a6b-2c0a-4aa0-b6cc-6c6117aab053 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160659003 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 13.uart_stress_all_with_rand_reset.4160659003 |
| Directory | /workspace/13.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/42.uart_stress_all.2318366610 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 225841622671 ps |
| CPU time | 149.61 seconds |
| Started | Jun 04 12:40:17 PM PDT 24 |
| Finished | Jun 04 12:42:48 PM PDT 24 |
| Peak memory | 200256 kb |
| Host | smart-020887c2-fb37-4b17-a016-4d1c98672843 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318366610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.2318366610 |
| Directory | /workspace/42.uart_stress_all/latest |
| Test location | /workspace/coverage/default/22.uart_stress_all_with_rand_reset.2611013466 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 296543151111 ps |
| CPU time | 623.07 seconds |
| Started | Jun 04 12:38:33 PM PDT 24 |
| Finished | Jun 04 12:48:57 PM PDT 24 |
| Peak memory | 216828 kb |
| Host | smart-f2b233f0-86ba-4957-9b74-ece1fe86c6fb |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611013466 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 22.uart_stress_all_with_rand_reset.2611013466 |
| Directory | /workspace/22.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/36.uart_long_xfer_wo_dly.3436005315 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 60620825632 ps |
| CPU time | 343.91 seconds |
| Started | Jun 04 12:39:49 PM PDT 24 |
| Finished | Jun 04 12:45:34 PM PDT 24 |
| Peak memory | 200140 kb |
| Host | smart-7bf6a3fb-e8ca-4fd5-9828-13c856d9f71b |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3436005315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.3436005315 |
| Directory | /workspace/36.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/29.uart_fifo_full.4042480874 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 157411892746 ps |
| CPU time | 673.53 seconds |
| Started | Jun 04 12:39:11 PM PDT 24 |
| Finished | Jun 04 12:50:26 PM PDT 24 |
| Peak memory | 200180 kb |
| Host | smart-7c497d26-c57b-497b-b9f4-b6547771f68b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4042480874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.4042480874 |
| Directory | /workspace/29.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/2.uart_sec_cm.1151303230 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 57816199 ps |
| CPU time | 0.85 seconds |
| Started | Jun 04 12:36:51 PM PDT 24 |
| Finished | Jun 04 12:36:52 PM PDT 24 |
| Peak memory | 218444 kb |
| Host | smart-bfdbd2bc-b9e3-43a3-9a1f-55eed8b62428 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151303230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.1151303230 |
| Directory | /workspace/2.uart_sec_cm/latest |
| Test location | /workspace/coverage/default/47.uart_stress_all_with_rand_reset.696670001 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 94561604096 ps |
| CPU time | 713.42 seconds |
| Started | Jun 04 12:40:45 PM PDT 24 |
| Finished | Jun 04 12:52:40 PM PDT 24 |
| Peak memory | 230664 kb |
| Host | smart-42a287f8-0e6a-4d20-94d8-3ef0e28372c8 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696670001 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 47.uart_stress_all_with_rand_reset.696670001 |
| Directory | /workspace/47.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/99.uart_stress_all_with_rand_reset.2143079430 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 194438755308 ps |
| CPU time | 1281.27 seconds |
| Started | Jun 04 12:41:26 PM PDT 24 |
| Finished | Jun 04 01:02:48 PM PDT 24 |
| Peak memory | 225176 kb |
| Host | smart-f1044f8b-001b-4888-9246-64669fbc45ab |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143079430 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 99.uart_stress_all_with_rand_reset.2143079430 |
| Directory | /workspace/99.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/74.uart_stress_all_with_rand_reset.1860130453 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 424787938843 ps |
| CPU time | 638.55 seconds |
| Started | Jun 04 12:41:13 PM PDT 24 |
| Finished | Jun 04 12:51:53 PM PDT 24 |
| Peak memory | 216264 kb |
| Host | smart-dfcb1b72-7203-4728-833a-b5b639be7dd2 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860130453 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 74.uart_stress_all_with_rand_reset.1860130453 |
| Directory | /workspace/74.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/5.uart_stress_all.2291478432 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 317576040495 ps |
| CPU time | 580.52 seconds |
| Started | Jun 04 12:37:07 PM PDT 24 |
| Finished | Jun 04 12:46:48 PM PDT 24 |
| Peak memory | 200124 kb |
| Host | smart-d2805eb8-88b1-4f2c-919b-67b182d09a16 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291478432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.2291478432 |
| Directory | /workspace/5.uart_stress_all/latest |
| Test location | /workspace/coverage/default/70.uart_stress_all_with_rand_reset.53977979 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 223573758979 ps |
| CPU time | 1216.72 seconds |
| Started | Jun 04 12:41:06 PM PDT 24 |
| Finished | Jun 04 01:01:24 PM PDT 24 |
| Peak memory | 224864 kb |
| Host | smart-c983c790-80a1-442e-a207-937db974795b |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53977979 -assert nopostpro c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 70.uart_stress_all_with_rand_reset.53977979 |
| Directory | /workspace/70.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/29.uart_stress_all.11095543 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 286073050404 ps |
| CPU time | 1127.31 seconds |
| Started | Jun 04 12:39:07 PM PDT 24 |
| Finished | Jun 04 12:57:56 PM PDT 24 |
| Peak memory | 208580 kb |
| Host | smart-917d6147-e4b9-4a3a-a0de-78926ab5b000 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11095543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.11095543 |
| Directory | /workspace/29.uart_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.2192302644 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 82854883 ps |
| CPU time | 1.28 seconds |
| Started | Jun 04 12:49:48 PM PDT 24 |
| Finished | Jun 04 12:49:50 PM PDT 24 |
| Peak memory | 199492 kb |
| Host | smart-d30ac8c5-5337-4ee4-90ab-2c6357636636 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192302644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.2192302644 |
| Directory | /workspace/8.uart_tl_intg_err/latest |
| Test location | /workspace/coverage/default/54.uart_fifo_reset.410242971 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 44734239689 ps |
| CPU time | 35.04 seconds |
| Started | Jun 04 12:40:56 PM PDT 24 |
| Finished | Jun 04 12:41:32 PM PDT 24 |
| Peak memory | 200204 kb |
| Host | smart-69da1a26-aee4-4fe2-828e-0107f858cb87 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=410242971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.410242971 |
| Directory | /workspace/54.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/149.uart_fifo_reset.829545744 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 135115246232 ps |
| CPU time | 164.26 seconds |
| Started | Jun 04 12:41:45 PM PDT 24 |
| Finished | Jun 04 12:44:30 PM PDT 24 |
| Peak memory | 200232 kb |
| Host | smart-93844f42-a52b-4f95-b12d-d249ae6c34c3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=829545744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.829545744 |
| Directory | /workspace/149.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/11.uart_alert_test.3420358015 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 12466690 ps |
| CPU time | 0.58 seconds |
| Started | Jun 04 12:37:33 PM PDT 24 |
| Finished | Jun 04 12:37:35 PM PDT 24 |
| Peak memory | 195580 kb |
| Host | smart-c03132f2-90f5-4a8d-866a-2c8be863772e |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420358015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.3420358015 |
| Directory | /workspace/11.uart_alert_test/latest |
| Test location | /workspace/coverage/default/267.uart_fifo_reset.4220359625 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 148276522283 ps |
| CPU time | 119.73 seconds |
| Started | Jun 04 12:42:38 PM PDT 24 |
| Finished | Jun 04 12:44:39 PM PDT 24 |
| Peak memory | 200140 kb |
| Host | smart-199cb260-0212-4b8c-bcbf-8a2c408592ac |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4220359625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.4220359625 |
| Directory | /workspace/267.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/12.uart_stress_all_with_rand_reset.3920113380 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 602806658623 ps |
| CPU time | 491.15 seconds |
| Started | Jun 04 12:37:45 PM PDT 24 |
| Finished | Jun 04 12:45:57 PM PDT 24 |
| Peak memory | 216700 kb |
| Host | smart-313e49d4-256e-4cdb-a7ac-9f7426061f05 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920113380 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 12.uart_stress_all_with_rand_reset.3920113380 |
| Directory | /workspace/12.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/13.uart_stress_all.1391154880 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 163062049952 ps |
| CPU time | 170.94 seconds |
| Started | Jun 04 12:37:47 PM PDT 24 |
| Finished | Jun 04 12:40:39 PM PDT 24 |
| Peak memory | 200348 kb |
| Host | smart-19655f57-bb67-4d00-96be-c082f649feb5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391154880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.1391154880 |
| Directory | /workspace/13.uart_stress_all/latest |
| Test location | /workspace/coverage/default/89.uart_stress_all_with_rand_reset.918972634 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 529253393904 ps |
| CPU time | 1076.53 seconds |
| Started | Jun 04 12:41:25 PM PDT 24 |
| Finished | Jun 04 12:59:22 PM PDT 24 |
| Peak memory | 217464 kb |
| Host | smart-708978fd-f880-4ce2-a54b-e57d843a6398 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918972634 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 89.uart_stress_all_with_rand_reset.918972634 |
| Directory | /workspace/89.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.1645578905 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 140995818 ps |
| CPU time | 1.63 seconds |
| Started | Jun 04 12:49:35 PM PDT 24 |
| Finished | Jun 04 12:49:37 PM PDT 24 |
| Peak memory | 197732 kb |
| Host | smart-696698a9-53c7-4c95-8027-47cd17e7b585 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645578905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.1645578905 |
| Directory | /workspace/0.uart_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.1546351894 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 17304609 ps |
| CPU time | 0.7 seconds |
| Started | Jun 04 12:49:49 PM PDT 24 |
| Finished | Jun 04 12:49:51 PM PDT 24 |
| Peak memory | 197276 kb |
| Host | smart-030332fd-7153-4d06-ac22-f768c82d7bca |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546351894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_cs r_outstanding.1546351894 |
| Directory | /workspace/10.uart_same_csr_outstanding/latest |
| Test location | /workspace/coverage/default/17.uart_fifo_reset.1549886547 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 260469932508 ps |
| CPU time | 85.05 seconds |
| Started | Jun 04 12:38:03 PM PDT 24 |
| Finished | Jun 04 12:39:28 PM PDT 24 |
| Peak memory | 200280 kb |
| Host | smart-fd37f5a1-3c39-4b12-89ee-768ebec6edce |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1549886547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.1549886547 |
| Directory | /workspace/17.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/34.uart_stress_all_with_rand_reset.2955382957 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 116214267061 ps |
| CPU time | 1430.33 seconds |
| Started | Jun 04 12:39:38 PM PDT 24 |
| Finished | Jun 04 01:03:30 PM PDT 24 |
| Peak memory | 226112 kb |
| Host | smart-9e80692d-b6da-4030-939e-972868e80479 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955382957 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 34.uart_stress_all_with_rand_reset.2955382957 |
| Directory | /workspace/34.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/22.uart_stress_all.115518225 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 146947576378 ps |
| CPU time | 248.62 seconds |
| Started | Jun 04 12:38:34 PM PDT 24 |
| Finished | Jun 04 12:42:44 PM PDT 24 |
| Peak memory | 200244 kb |
| Host | smart-b67acd96-52a2-4118-9c41-628a2de3f849 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115518225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.115518225 |
| Directory | /workspace/22.uart_stress_all/latest |
| Test location | /workspace/coverage/default/35.uart_stress_all_with_rand_reset.2474132623 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 562023992741 ps |
| CPU time | 1233.1 seconds |
| Started | Jun 04 12:39:36 PM PDT 24 |
| Finished | Jun 04 01:00:10 PM PDT 24 |
| Peak memory | 227996 kb |
| Host | smart-1f4fe50b-913c-49ce-b399-baf284191caf |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474132623 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 35.uart_stress_all_with_rand_reset.2474132623 |
| Directory | /workspace/35.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.4231742510 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 75115104 ps |
| CPU time | 1.35 seconds |
| Started | Jun 04 12:50:02 PM PDT 24 |
| Finished | Jun 04 12:50:05 PM PDT 24 |
| Peak memory | 199352 kb |
| Host | smart-112abfcd-9417-4c07-9f14-47cfe1056e57 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231742510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.4231742510 |
| Directory | /workspace/17.uart_tl_intg_err/latest |
| Test location | /workspace/coverage/default/25.uart_stress_all.1863619328 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 169481315655 ps |
| CPU time | 273.82 seconds |
| Started | Jun 04 12:38:54 PM PDT 24 |
| Finished | Jun 04 12:43:29 PM PDT 24 |
| Peak memory | 200380 kb |
| Host | smart-39d2496d-5499-40a4-968c-a9521ae3cd7f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863619328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.1863619328 |
| Directory | /workspace/25.uart_stress_all/latest |
| Test location | /workspace/coverage/default/124.uart_fifo_reset.2331992771 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 133797027708 ps |
| CPU time | 163.01 seconds |
| Started | Jun 04 12:41:35 PM PDT 24 |
| Finished | Jun 04 12:44:19 PM PDT 24 |
| Peak memory | 200140 kb |
| Host | smart-5b2a86f4-bab3-4803-9e32-37e25e1f21f4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2331992771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.2331992771 |
| Directory | /workspace/124.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/111.uart_fifo_reset.284436084 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 121735172956 ps |
| CPU time | 73.61 seconds |
| Started | Jun 04 12:41:36 PM PDT 24 |
| Finished | Jun 04 12:42:50 PM PDT 24 |
| Peak memory | 200224 kb |
| Host | smart-b5e7c568-1396-49eb-8e5f-dc20d3a62cc9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=284436084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.284436084 |
| Directory | /workspace/111.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/165.uart_fifo_reset.4098580305 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 23177861996 ps |
| CPU time | 43.03 seconds |
| Started | Jun 04 12:41:52 PM PDT 24 |
| Finished | Jun 04 12:42:36 PM PDT 24 |
| Peak memory | 200240 kb |
| Host | smart-488bf200-8eef-4bba-a837-a2e28bbf17e3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4098580305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.4098580305 |
| Directory | /workspace/165.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/281.uart_fifo_reset.1320355972 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 40833757068 ps |
| CPU time | 15.83 seconds |
| Started | Jun 04 12:42:49 PM PDT 24 |
| Finished | Jun 04 12:43:06 PM PDT 24 |
| Peak memory | 200228 kb |
| Host | smart-7d6d625e-0b94-4c25-b1a7-ccd24daf80b3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1320355972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.1320355972 |
| Directory | /workspace/281.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/34.uart_stress_all.1165027538 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 454146881678 ps |
| CPU time | 119.77 seconds |
| Started | Jun 04 12:39:38 PM PDT 24 |
| Finished | Jun 04 12:41:39 PM PDT 24 |
| Peak memory | 200148 kb |
| Host | smart-26e3ac4e-5a2b-4860-ae42-62e7fbb94ee4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165027538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.1165027538 |
| Directory | /workspace/34.uart_stress_all/latest |
| Test location | /workspace/coverage/default/38.uart_fifo_overflow.1011113785 |
| Short name | T1093 |
| Test name | |
| Test status | |
| Simulation time | 33694209084 ps |
| CPU time | 15.96 seconds |
| Started | Jun 04 12:39:57 PM PDT 24 |
| Finished | Jun 04 12:40:14 PM PDT 24 |
| Peak memory | 200072 kb |
| Host | smart-a60d4392-5f06-406b-89cb-bebaf47b97a2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1011113785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.1011113785 |
| Directory | /workspace/38.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/0.uart_fifo_reset.3267922105 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 51987742203 ps |
| CPU time | 48.17 seconds |
| Started | Jun 04 12:36:28 PM PDT 24 |
| Finished | Jun 04 12:37:17 PM PDT 24 |
| Peak memory | 200140 kb |
| Host | smart-21878a95-2296-4221-90d5-5d4898d7c77d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3267922105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.3267922105 |
| Directory | /workspace/0.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/11.uart_stress_all_with_rand_reset.1455577592 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 286044847287 ps |
| CPU time | 799.35 seconds |
| Started | Jun 04 12:37:33 PM PDT 24 |
| Finished | Jun 04 12:50:54 PM PDT 24 |
| Peak memory | 225164 kb |
| Host | smart-7e0a068d-3703-4ba2-aad1-c07999a83cdc |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455577592 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 11.uart_stress_all_with_rand_reset.1455577592 |
| Directory | /workspace/11.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/18.uart_stress_all_with_rand_reset.2318713087 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 166539263811 ps |
| CPU time | 494.33 seconds |
| Started | Jun 04 12:38:13 PM PDT 24 |
| Finished | Jun 04 12:46:29 PM PDT 24 |
| Peak memory | 226868 kb |
| Host | smart-204df4a9-afeb-4a9e-a005-48fa14ea0577 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318713087 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 18.uart_stress_all_with_rand_reset.2318713087 |
| Directory | /workspace/18.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/295.uart_fifo_reset.1728316515 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 32136000322 ps |
| CPU time | 15.91 seconds |
| Started | Jun 04 12:43:00 PM PDT 24 |
| Finished | Jun 04 12:43:17 PM PDT 24 |
| Peak memory | 200348 kb |
| Host | smart-d1355313-5229-487d-8abd-5a2e3d014062 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1728316515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.1728316515 |
| Directory | /workspace/295.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/84.uart_fifo_reset.1092783403 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 144505211097 ps |
| CPU time | 95.62 seconds |
| Started | Jun 04 12:41:19 PM PDT 24 |
| Finished | Jun 04 12:42:55 PM PDT 24 |
| Peak memory | 200208 kb |
| Host | smart-7a1c4083-3317-44c3-9e78-adfb733f7681 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1092783403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.1092783403 |
| Directory | /workspace/84.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/9.uart_fifo_reset.3099762933 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 53004758279 ps |
| CPU time | 45.22 seconds |
| Started | Jun 04 12:37:25 PM PDT 24 |
| Finished | Jun 04 12:38:11 PM PDT 24 |
| Peak memory | 200296 kb |
| Host | smart-9124e37c-bd1b-4721-9b3d-824173e8daeb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3099762933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.3099762933 |
| Directory | /workspace/9.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/1.uart_stress_all_with_rand_reset.799709189 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 99179776361 ps |
| CPU time | 640.61 seconds |
| Started | Jun 04 12:36:40 PM PDT 24 |
| Finished | Jun 04 12:47:22 PM PDT 24 |
| Peak memory | 224988 kb |
| Host | smart-5ee28027-bf7f-40dc-bf78-739be332f8c8 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799709189 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 1.uart_stress_all_with_rand_reset.799709189 |
| Directory | /workspace/1.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/120.uart_fifo_reset.1572013935 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 69375007550 ps |
| CPU time | 174.34 seconds |
| Started | Jun 04 12:41:35 PM PDT 24 |
| Finished | Jun 04 12:44:30 PM PDT 24 |
| Peak memory | 200252 kb |
| Host | smart-7f477098-7aa7-4c6e-8be5-d4e75af2ba3f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1572013935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.1572013935 |
| Directory | /workspace/120.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/122.uart_fifo_reset.1205738263 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 180920687090 ps |
| CPU time | 62.5 seconds |
| Started | Jun 04 12:41:33 PM PDT 24 |
| Finished | Jun 04 12:42:36 PM PDT 24 |
| Peak memory | 200124 kb |
| Host | smart-120c13be-d41d-4bea-abda-5e1272923f2d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1205738263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.1205738263 |
| Directory | /workspace/122.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/123.uart_fifo_reset.1816827779 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 41105720823 ps |
| CPU time | 72.64 seconds |
| Started | Jun 04 12:41:33 PM PDT 24 |
| Finished | Jun 04 12:42:46 PM PDT 24 |
| Peak memory | 200252 kb |
| Host | smart-d6a7a8e4-1902-4699-aaa8-e1ebc63b55b4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1816827779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.1816827779 |
| Directory | /workspace/123.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/125.uart_fifo_reset.1807613360 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 82999349864 ps |
| CPU time | 202.33 seconds |
| Started | Jun 04 12:41:38 PM PDT 24 |
| Finished | Jun 04 12:45:00 PM PDT 24 |
| Peak memory | 200124 kb |
| Host | smart-a363d89f-80dd-4946-ae16-029ac8cb3ebc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1807613360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.1807613360 |
| Directory | /workspace/125.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/138.uart_fifo_reset.2497164916 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 31113761302 ps |
| CPU time | 16.41 seconds |
| Started | Jun 04 12:41:42 PM PDT 24 |
| Finished | Jun 04 12:41:59 PM PDT 24 |
| Peak memory | 200212 kb |
| Host | smart-3d9257c2-fa03-43bc-80fc-0246004534b3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2497164916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.2497164916 |
| Directory | /workspace/138.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/2.uart_tx_rx.4030498020 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 52873673205 ps |
| CPU time | 42.02 seconds |
| Started | Jun 04 12:36:39 PM PDT 24 |
| Finished | Jun 04 12:37:22 PM PDT 24 |
| Peak memory | 200216 kb |
| Host | smart-989cbdd3-0b30-4450-8f90-e2bd84bfcf28 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4030498020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.4030498020 |
| Directory | /workspace/2.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/290.uart_fifo_reset.1030039680 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 96325733439 ps |
| CPU time | 21.6 seconds |
| Started | Jun 04 12:42:52 PM PDT 24 |
| Finished | Jun 04 12:43:14 PM PDT 24 |
| Peak memory | 200300 kb |
| Host | smart-a1884796-174d-44e2-8d44-d1b42c156d6c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1030039680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.1030039680 |
| Directory | /workspace/290.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/43.uart_fifo_reset.1297733013 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 134204153886 ps |
| CPU time | 63.93 seconds |
| Started | Jun 04 12:40:28 PM PDT 24 |
| Finished | Jun 04 12:41:33 PM PDT 24 |
| Peak memory | 200256 kb |
| Host | smart-1297d0ed-d058-4711-90a4-d62887943fe0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1297733013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.1297733013 |
| Directory | /workspace/43.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/100.uart_fifo_reset.2523323297 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 12999271405 ps |
| CPU time | 88.84 seconds |
| Started | Jun 04 12:41:26 PM PDT 24 |
| Finished | Jun 04 12:42:56 PM PDT 24 |
| Peak memory | 200276 kb |
| Host | smart-926d89c6-38a2-4cca-bde4-f698bab1f16c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2523323297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.2523323297 |
| Directory | /workspace/100.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/106.uart_fifo_reset.2886956004 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 55841726789 ps |
| CPU time | 183.47 seconds |
| Started | Jun 04 12:41:34 PM PDT 24 |
| Finished | Jun 04 12:44:38 PM PDT 24 |
| Peak memory | 200184 kb |
| Host | smart-5a98828f-1e0e-483f-b4d2-6afcf2e85dfe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2886956004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.2886956004 |
| Directory | /workspace/106.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/109.uart_fifo_reset.2709467490 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 23280398404 ps |
| CPU time | 39.94 seconds |
| Started | Jun 04 12:41:32 PM PDT 24 |
| Finished | Jun 04 12:42:13 PM PDT 24 |
| Peak memory | 200332 kb |
| Host | smart-a81f6d0e-d5ea-475b-a464-ff8d376c47b3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2709467490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.2709467490 |
| Directory | /workspace/109.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/115.uart_fifo_reset.1589145992 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 23953749748 ps |
| CPU time | 19.55 seconds |
| Started | Jun 04 12:41:35 PM PDT 24 |
| Finished | Jun 04 12:41:56 PM PDT 24 |
| Peak memory | 199940 kb |
| Host | smart-c8fc244c-22fd-4d4d-a372-13a00c5b970e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1589145992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.1589145992 |
| Directory | /workspace/115.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/129.uart_fifo_reset.227838004 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 109886903462 ps |
| CPU time | 46.93 seconds |
| Started | Jun 04 12:41:37 PM PDT 24 |
| Finished | Jun 04 12:42:24 PM PDT 24 |
| Peak memory | 200224 kb |
| Host | smart-f7723436-2672-4251-9cd6-fe3665ba0a60 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=227838004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.227838004 |
| Directory | /workspace/129.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/135.uart_fifo_reset.824771168 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 124344745793 ps |
| CPU time | 53.62 seconds |
| Started | Jun 04 12:41:33 PM PDT 24 |
| Finished | Jun 04 12:42:27 PM PDT 24 |
| Peak memory | 200368 kb |
| Host | smart-7ae665b5-3a38-4c6c-be72-649e2129ccea |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=824771168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.824771168 |
| Directory | /workspace/135.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/152.uart_fifo_reset.3722126141 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 23860624615 ps |
| CPU time | 47.17 seconds |
| Started | Jun 04 12:41:41 PM PDT 24 |
| Finished | Jun 04 12:42:28 PM PDT 24 |
| Peak memory | 200220 kb |
| Host | smart-540045ef-d703-4838-8817-03b7f2ef5e0e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3722126141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.3722126141 |
| Directory | /workspace/152.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/166.uart_fifo_reset.2279138447 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 176692109764 ps |
| CPU time | 74.8 seconds |
| Started | Jun 04 12:41:53 PM PDT 24 |
| Finished | Jun 04 12:43:08 PM PDT 24 |
| Peak memory | 200264 kb |
| Host | smart-49b47df4-0d17-4c89-829a-5d695b9bc36f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2279138447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.2279138447 |
| Directory | /workspace/166.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/172.uart_fifo_reset.3521923150 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 66706427888 ps |
| CPU time | 67.23 seconds |
| Started | Jun 04 12:41:52 PM PDT 24 |
| Finished | Jun 04 12:43:00 PM PDT 24 |
| Peak memory | 200272 kb |
| Host | smart-bcefeafe-3103-4fc8-86c4-20fd85a586b9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3521923150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.3521923150 |
| Directory | /workspace/172.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/174.uart_fifo_reset.350070238 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 68126504607 ps |
| CPU time | 27.34 seconds |
| Started | Jun 04 12:41:52 PM PDT 24 |
| Finished | Jun 04 12:42:20 PM PDT 24 |
| Peak memory | 200352 kb |
| Host | smart-84e2e98f-de01-42d2-a732-650733b5934c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=350070238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.350070238 |
| Directory | /workspace/174.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/193.uart_fifo_reset.1823463563 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 146033268180 ps |
| CPU time | 29.71 seconds |
| Started | Jun 04 12:42:12 PM PDT 24 |
| Finished | Jun 04 12:42:43 PM PDT 24 |
| Peak memory | 200132 kb |
| Host | smart-8e281fe6-37ce-4c25-b4fe-7fce056ac436 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1823463563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.1823463563 |
| Directory | /workspace/193.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/196.uart_fifo_reset.342701078 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 94640621046 ps |
| CPU time | 35.99 seconds |
| Started | Jun 04 12:42:14 PM PDT 24 |
| Finished | Jun 04 12:42:51 PM PDT 24 |
| Peak memory | 200288 kb |
| Host | smart-ab169074-966c-4ff4-abf6-ae95f706e6b3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=342701078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.342701078 |
| Directory | /workspace/196.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/210.uart_fifo_reset.1421859586 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 74766144554 ps |
| CPU time | 117.54 seconds |
| Started | Jun 04 12:42:11 PM PDT 24 |
| Finished | Jun 04 12:44:09 PM PDT 24 |
| Peak memory | 200280 kb |
| Host | smart-52579635-a918-4e44-95e7-ae7d5671d0a8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1421859586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.1421859586 |
| Directory | /workspace/210.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/223.uart_fifo_reset.942086439 |
| Short name | T919 |
| Test name | |
| Test status | |
| Simulation time | 7677229096 ps |
| CPU time | 18.28 seconds |
| Started | Jun 04 12:42:21 PM PDT 24 |
| Finished | Jun 04 12:42:40 PM PDT 24 |
| Peak memory | 200184 kb |
| Host | smart-4890c449-483a-4a67-8443-10788ca59466 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=942086439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.942086439 |
| Directory | /workspace/223.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/260.uart_fifo_reset.2709777131 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 41536247940 ps |
| CPU time | 22.82 seconds |
| Started | Jun 04 12:42:41 PM PDT 24 |
| Finished | Jun 04 12:43:04 PM PDT 24 |
| Peak memory | 200224 kb |
| Host | smart-cf50f47f-d130-4e02-95b0-b734b48a8696 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2709777131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.2709777131 |
| Directory | /workspace/260.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/29.uart_fifo_reset.3927746139 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 80306218503 ps |
| CPU time | 63.57 seconds |
| Started | Jun 04 12:39:07 PM PDT 24 |
| Finished | Jun 04 12:40:11 PM PDT 24 |
| Peak memory | 200160 kb |
| Host | smart-bb16d792-ae75-4737-84e9-58879c607fa6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3927746139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.3927746139 |
| Directory | /workspace/29.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/294.uart_fifo_reset.1399940873 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 8441527627 ps |
| CPU time | 16.69 seconds |
| Started | Jun 04 12:42:58 PM PDT 24 |
| Finished | Jun 04 12:43:15 PM PDT 24 |
| Peak memory | 200192 kb |
| Host | smart-5accc1c8-b532-43ca-86bd-3c89beac7e1b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1399940873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.1399940873 |
| Directory | /workspace/294.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/4.uart_fifo_reset.1999994793 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 34952364173 ps |
| CPU time | 61.63 seconds |
| Started | Jun 04 12:37:04 PM PDT 24 |
| Finished | Jun 04 12:38:07 PM PDT 24 |
| Peak memory | 200248 kb |
| Host | smart-6ad6cf67-70f8-4fdc-aee7-50f82e3c0d17 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1999994793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.1999994793 |
| Directory | /workspace/4.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/87.uart_fifo_reset.502508757 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 34837557572 ps |
| CPU time | 44.13 seconds |
| Started | Jun 04 12:41:25 PM PDT 24 |
| Finished | Jun 04 12:42:10 PM PDT 24 |
| Peak memory | 200292 kb |
| Host | smart-f009c8b8-efec-4ab3-8306-a45577f9d2bf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=502508757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.502508757 |
| Directory | /workspace/87.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/90.uart_fifo_reset.1222955034 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 28324778013 ps |
| CPU time | 11.58 seconds |
| Started | Jun 04 12:41:28 PM PDT 24 |
| Finished | Jun 04 12:41:40 PM PDT 24 |
| Peak memory | 200196 kb |
| Host | smart-7b0050c2-88e0-4b36-8a74-c5ce893398dc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1222955034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.1222955034 |
| Directory | /workspace/90.uart_fifo_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.1664660505 |
| Short name | T1184 |
| Test name | |
| Test status | |
| Simulation time | 22022304 ps |
| CPU time | 0.67 seconds |
| Started | Jun 04 12:49:39 PM PDT 24 |
| Finished | Jun 04 12:49:41 PM PDT 24 |
| Peak memory | 195516 kb |
| Host | smart-da1b3b82-9631-42bc-99d4-29c25effed13 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664660505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.1664660505 |
| Directory | /workspace/0.uart_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.4294284082 |
| Short name | T1273 |
| Test name | |
| Test status | |
| Simulation time | 55060281 ps |
| CPU time | 0.61 seconds |
| Started | Jun 04 12:49:42 PM PDT 24 |
| Finished | Jun 04 12:49:43 PM PDT 24 |
| Peak memory | 195640 kb |
| Host | smart-015faf47-c8de-497b-8e2c-a5e879cf5c0e |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294284082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.4294284082 |
| Directory | /workspace/0.uart_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.365935173 |
| Short name | T1248 |
| Test name | |
| Test status | |
| Simulation time | 96392397 ps |
| CPU time | 0.7 seconds |
| Started | Jun 04 12:49:37 PM PDT 24 |
| Finished | Jun 04 12:49:38 PM PDT 24 |
| Peak memory | 198552 kb |
| Host | smart-90d9186c-3fb9-40a8-89b9-b5033ccc7d21 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365935173 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.365935173 |
| Directory | /workspace/0.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.uart_csr_rw.3918466309 |
| Short name | T1250 |
| Test name | |
| Test status | |
| Simulation time | 12857456 ps |
| CPU time | 0.6 seconds |
| Started | Jun 04 12:49:39 PM PDT 24 |
| Finished | Jun 04 12:49:41 PM PDT 24 |
| Peak memory | 195548 kb |
| Host | smart-a2b2db9d-3fb9-4db4-8152-530a3b870221 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918466309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.3918466309 |
| Directory | /workspace/0.uart_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/0.uart_intr_test.3402560287 |
| Short name | T1187 |
| Test name | |
| Test status | |
| Simulation time | 34092452 ps |
| CPU time | 0.55 seconds |
| Started | Jun 04 12:49:38 PM PDT 24 |
| Finished | Jun 04 12:49:40 PM PDT 24 |
| Peak memory | 194488 kb |
| Host | smart-57de9af0-9b93-46dd-a41a-155051718229 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402560287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.3402560287 |
| Directory | /workspace/0.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.891479377 |
| Short name | T1277 |
| Test name | |
| Test status | |
| Simulation time | 43097759 ps |
| CPU time | 0.68 seconds |
| Started | Jun 04 12:49:38 PM PDT 24 |
| Finished | Jun 04 12:49:40 PM PDT 24 |
| Peak memory | 195940 kb |
| Host | smart-b968512a-678e-4b1c-81c8-d7f49ae2717b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891479377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr_ outstanding.891479377 |
| Directory | /workspace/0.uart_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/0.uart_tl_errors.3315677096 |
| Short name | T1183 |
| Test name | |
| Test status | |
| Simulation time | 40305890 ps |
| CPU time | 2.1 seconds |
| Started | Jun 04 12:49:37 PM PDT 24 |
| Finished | Jun 04 12:49:40 PM PDT 24 |
| Peak memory | 200152 kb |
| Host | smart-e4e4ddfa-fa76-42e7-ba91-17d008f75c41 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315677096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.3315677096 |
| Directory | /workspace/0.uart_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.3991900871 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 52861747 ps |
| CPU time | 0.96 seconds |
| Started | Jun 04 12:49:36 PM PDT 24 |
| Finished | Jun 04 12:49:38 PM PDT 24 |
| Peak memory | 199320 kb |
| Host | smart-95488d89-cca3-4e14-b5d7-604490a8177f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991900871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.3991900871 |
| Directory | /workspace/0.uart_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.2098659447 |
| Short name | T1224 |
| Test name | |
| Test status | |
| Simulation time | 31532687 ps |
| CPU time | 0.67 seconds |
| Started | Jun 04 12:49:39 PM PDT 24 |
| Finished | Jun 04 12:49:41 PM PDT 24 |
| Peak memory | 195176 kb |
| Host | smart-422efe7d-6322-44eb-8599-298ea0a5e694 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098659447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.2098659447 |
| Directory | /workspace/1.uart_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.703940877 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 1150745628 ps |
| CPU time | 1.56 seconds |
| Started | Jun 04 12:49:39 PM PDT 24 |
| Finished | Jun 04 12:49:42 PM PDT 24 |
| Peak memory | 197496 kb |
| Host | smart-0f1c1c9d-e4ef-46bd-a900-f757ebd4cbc9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703940877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.703940877 |
| Directory | /workspace/1.uart_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.3691857815 |
| Short name | T1215 |
| Test name | |
| Test status | |
| Simulation time | 58096615 ps |
| CPU time | 0.6 seconds |
| Started | Jun 04 12:49:40 PM PDT 24 |
| Finished | Jun 04 12:49:41 PM PDT 24 |
| Peak memory | 195620 kb |
| Host | smart-63106d87-10ed-499b-af28-d915d5c1b1b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691857815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.3691857815 |
| Directory | /workspace/1.uart_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.1167777986 |
| Short name | T1210 |
| Test name | |
| Test status | |
| Simulation time | 60688922 ps |
| CPU time | 0.82 seconds |
| Started | Jun 04 12:49:40 PM PDT 24 |
| Finished | Jun 04 12:49:41 PM PDT 24 |
| Peak memory | 198980 kb |
| Host | smart-dea4f7f8-83b7-4a47-a8e9-d2e290da31ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167777986 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.1167777986 |
| Directory | /workspace/1.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.uart_csr_rw.624582085 |
| Short name | T1201 |
| Test name | |
| Test status | |
| Simulation time | 15430624 ps |
| CPU time | 0.6 seconds |
| Started | Jun 04 12:49:40 PM PDT 24 |
| Finished | Jun 04 12:49:42 PM PDT 24 |
| Peak memory | 195600 kb |
| Host | smart-302da42f-d0d8-43b3-b6fa-00fdda964da0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624582085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.624582085 |
| Directory | /workspace/1.uart_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/1.uart_intr_test.233582175 |
| Short name | T1222 |
| Test name | |
| Test status | |
| Simulation time | 20994557 ps |
| CPU time | 0.53 seconds |
| Started | Jun 04 12:49:38 PM PDT 24 |
| Finished | Jun 04 12:49:39 PM PDT 24 |
| Peak memory | 194616 kb |
| Host | smart-5a7f6b44-b7d7-4e3f-a7d5-e92a34efbdc1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233582175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.233582175 |
| Directory | /workspace/1.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.2905306607 |
| Short name | T1289 |
| Test name | |
| Test status | |
| Simulation time | 228770463 ps |
| CPU time | 0.64 seconds |
| Started | Jun 04 12:49:37 PM PDT 24 |
| Finished | Jun 04 12:49:38 PM PDT 24 |
| Peak memory | 195836 kb |
| Host | smart-40952e45-b38a-4545-b235-3296c41ea2db |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905306607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr _outstanding.2905306607 |
| Directory | /workspace/1.uart_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/1.uart_tl_errors.272299390 |
| Short name | T1252 |
| Test name | |
| Test status | |
| Simulation time | 517342127 ps |
| CPU time | 2.52 seconds |
| Started | Jun 04 12:49:38 PM PDT 24 |
| Finished | Jun 04 12:49:42 PM PDT 24 |
| Peak memory | 200344 kb |
| Host | smart-ab66d87a-145b-43ef-8a58-30230f4c4e9c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272299390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.272299390 |
| Directory | /workspace/1.uart_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.2884091579 |
| Short name | T1202 |
| Test name | |
| Test status | |
| Simulation time | 54165734 ps |
| CPU time | 0.98 seconds |
| Started | Jun 04 12:49:41 PM PDT 24 |
| Finished | Jun 04 12:49:42 PM PDT 24 |
| Peak memory | 199220 kb |
| Host | smart-3535b20e-a868-4ddc-af46-70f28b4036ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884091579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.2884091579 |
| Directory | /workspace/1.uart_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.1252305034 |
| Short name | T1282 |
| Test name | |
| Test status | |
| Simulation time | 78704819 ps |
| CPU time | 0.72 seconds |
| Started | Jun 04 12:49:47 PM PDT 24 |
| Finished | Jun 04 12:49:49 PM PDT 24 |
| Peak memory | 199516 kb |
| Host | smart-89f3ad9c-2330-4543-982b-d4e0fa5b1cfe |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252305034 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.1252305034 |
| Directory | /workspace/10.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/10.uart_csr_rw.1426098681 |
| Short name | T1218 |
| Test name | |
| Test status | |
| Simulation time | 16165554 ps |
| CPU time | 0.59 seconds |
| Started | Jun 04 12:49:47 PM PDT 24 |
| Finished | Jun 04 12:49:48 PM PDT 24 |
| Peak memory | 195540 kb |
| Host | smart-bdff6ee4-5de8-4995-897c-c3ef960c5b00 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426098681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.1426098681 |
| Directory | /workspace/10.uart_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/10.uart_intr_test.3079653717 |
| Short name | T1204 |
| Test name | |
| Test status | |
| Simulation time | 30951464 ps |
| CPU time | 0.58 seconds |
| Started | Jun 04 12:49:47 PM PDT 24 |
| Finished | Jun 04 12:49:48 PM PDT 24 |
| Peak memory | 194628 kb |
| Host | smart-76505f24-6f3f-4e2b-874e-c7b14432335e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079653717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.3079653717 |
| Directory | /workspace/10.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/10.uart_tl_errors.1137054865 |
| Short name | T1254 |
| Test name | |
| Test status | |
| Simulation time | 26733334 ps |
| CPU time | 1.45 seconds |
| Started | Jun 04 12:49:46 PM PDT 24 |
| Finished | Jun 04 12:49:48 PM PDT 24 |
| Peak memory | 200176 kb |
| Host | smart-4819f075-d740-49a7-b3d3-6769d476acc3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137054865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.1137054865 |
| Directory | /workspace/10.uart_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.855250556 |
| Short name | T1280 |
| Test name | |
| Test status | |
| Simulation time | 47990246 ps |
| CPU time | 0.93 seconds |
| Started | Jun 04 12:49:48 PM PDT 24 |
| Finished | Jun 04 12:49:51 PM PDT 24 |
| Peak memory | 199032 kb |
| Host | smart-1caf1232-ead9-4087-b5db-38b2de98eb89 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855250556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.855250556 |
| Directory | /workspace/10.uart_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.2989615322 |
| Short name | T1229 |
| Test name | |
| Test status | |
| Simulation time | 70316166 ps |
| CPU time | 0.84 seconds |
| Started | Jun 04 12:50:01 PM PDT 24 |
| Finished | Jun 04 12:50:04 PM PDT 24 |
| Peak memory | 200056 kb |
| Host | smart-8201c122-4f62-4479-bb87-bac1e2649afd |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989615322 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.2989615322 |
| Directory | /workspace/11.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/11.uart_csr_rw.3106842242 |
| Short name | T1200 |
| Test name | |
| Test status | |
| Simulation time | 16723620 ps |
| CPU time | 0.6 seconds |
| Started | Jun 04 12:49:58 PM PDT 24 |
| Finished | Jun 04 12:50:01 PM PDT 24 |
| Peak memory | 195672 kb |
| Host | smart-ee2e7070-e975-40cd-8044-cb44554ee780 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106842242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.3106842242 |
| Directory | /workspace/11.uart_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/11.uart_intr_test.3234581428 |
| Short name | T1219 |
| Test name | |
| Test status | |
| Simulation time | 34833638 ps |
| CPU time | 0.57 seconds |
| Started | Jun 04 12:49:59 PM PDT 24 |
| Finished | Jun 04 12:50:02 PM PDT 24 |
| Peak memory | 194592 kb |
| Host | smart-6da9c3da-e8c9-4a7e-bf8e-cc499e9c3767 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234581428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.3234581428 |
| Directory | /workspace/11.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.1094706204 |
| Short name | T1244 |
| Test name | |
| Test status | |
| Simulation time | 27016070 ps |
| CPU time | 0.74 seconds |
| Started | Jun 04 12:49:59 PM PDT 24 |
| Finished | Jun 04 12:50:02 PM PDT 24 |
| Peak memory | 197344 kb |
| Host | smart-73522300-02cd-4994-9455-1e6e91183211 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094706204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_cs r_outstanding.1094706204 |
| Directory | /workspace/11.uart_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/11.uart_tl_errors.144367380 |
| Short name | T1257 |
| Test name | |
| Test status | |
| Simulation time | 20794386 ps |
| CPU time | 1.13 seconds |
| Started | Jun 04 12:49:49 PM PDT 24 |
| Finished | Jun 04 12:49:51 PM PDT 24 |
| Peak memory | 200120 kb |
| Host | smart-a35b0237-52d2-49d5-8590-cb4d5f870aef |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144367380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.144367380 |
| Directory | /workspace/11.uart_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.1988504601 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 358368607 ps |
| CPU time | 1.06 seconds |
| Started | Jun 04 12:49:53 PM PDT 24 |
| Finished | Jun 04 12:49:55 PM PDT 24 |
| Peak memory | 198608 kb |
| Host | smart-892eb246-f0bc-47ee-943f-82422be99340 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988504601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.1988504601 |
| Directory | /workspace/11.uart_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.1413098935 |
| Short name | T1260 |
| Test name | |
| Test status | |
| Simulation time | 71264540 ps |
| CPU time | 0.68 seconds |
| Started | Jun 04 12:49:57 PM PDT 24 |
| Finished | Jun 04 12:49:58 PM PDT 24 |
| Peak memory | 197848 kb |
| Host | smart-729cea93-7ad1-4aa8-afdf-9f6231e5b341 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413098935 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.1413098935 |
| Directory | /workspace/12.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/12.uart_csr_rw.650825083 |
| Short name | T1213 |
| Test name | |
| Test status | |
| Simulation time | 11025996 ps |
| CPU time | 0.57 seconds |
| Started | Jun 04 12:50:00 PM PDT 24 |
| Finished | Jun 04 12:50:03 PM PDT 24 |
| Peak memory | 195808 kb |
| Host | smart-eecb48a8-220e-4485-8828-f5e5ead19a5c |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650825083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.650825083 |
| Directory | /workspace/12.uart_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/12.uart_intr_test.278860213 |
| Short name | T1194 |
| Test name | |
| Test status | |
| Simulation time | 31193043 ps |
| CPU time | 0.57 seconds |
| Started | Jun 04 12:49:57 PM PDT 24 |
| Finished | Jun 04 12:49:58 PM PDT 24 |
| Peak memory | 194508 kb |
| Host | smart-9d1a7def-ce6a-4c15-a6a1-0bdf63b39a6d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278860213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.278860213 |
| Directory | /workspace/12.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.3283781726 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 60065267 ps |
| CPU time | 0.79 seconds |
| Started | Jun 04 12:49:58 PM PDT 24 |
| Finished | Jun 04 12:50:00 PM PDT 24 |
| Peak memory | 197368 kb |
| Host | smart-359eb8d0-a80c-421d-a105-73cefaa87348 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283781726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_cs r_outstanding.3283781726 |
| Directory | /workspace/12.uart_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/12.uart_tl_errors.1487579998 |
| Short name | T1272 |
| Test name | |
| Test status | |
| Simulation time | 126959160 ps |
| CPU time | 1.53 seconds |
| Started | Jun 04 12:49:59 PM PDT 24 |
| Finished | Jun 04 12:50:03 PM PDT 24 |
| Peak memory | 200340 kb |
| Host | smart-ba0a3072-1085-41ad-86c8-d4dedd2241fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487579998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.1487579998 |
| Directory | /workspace/12.uart_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.712214785 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 249957149 ps |
| CPU time | 1.32 seconds |
| Started | Jun 04 12:50:01 PM PDT 24 |
| Finished | Jun 04 12:50:04 PM PDT 24 |
| Peak memory | 199624 kb |
| Host | smart-a594ad8b-205a-4317-a7cb-c10a6a525bba |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712214785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.712214785 |
| Directory | /workspace/12.uart_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.4106224567 |
| Short name | T1253 |
| Test name | |
| Test status | |
| Simulation time | 22995062 ps |
| CPU time | 0.75 seconds |
| Started | Jun 04 12:49:58 PM PDT 24 |
| Finished | Jun 04 12:50:01 PM PDT 24 |
| Peak memory | 199060 kb |
| Host | smart-a5d244d5-16de-4841-8557-2bcfc099bb42 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106224567 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.4106224567 |
| Directory | /workspace/13.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/13.uart_csr_rw.2334414729 |
| Short name | T1231 |
| Test name | |
| Test status | |
| Simulation time | 20029121 ps |
| CPU time | 0.62 seconds |
| Started | Jun 04 12:49:59 PM PDT 24 |
| Finished | Jun 04 12:50:01 PM PDT 24 |
| Peak memory | 195732 kb |
| Host | smart-baa24fe4-0520-44d1-b07f-0e212bf93ccd |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334414729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.2334414729 |
| Directory | /workspace/13.uart_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/13.uart_intr_test.4182576246 |
| Short name | T1223 |
| Test name | |
| Test status | |
| Simulation time | 16499181 ps |
| CPU time | 0.56 seconds |
| Started | Jun 04 12:49:59 PM PDT 24 |
| Finished | Jun 04 12:50:02 PM PDT 24 |
| Peak memory | 194640 kb |
| Host | smart-9c34b1b4-a139-4b0c-8d92-043faec79045 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182576246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.4182576246 |
| Directory | /workspace/13.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.2805724119 |
| Short name | T1262 |
| Test name | |
| Test status | |
| Simulation time | 156971233 ps |
| CPU time | 0.74 seconds |
| Started | Jun 04 12:50:01 PM PDT 24 |
| Finished | Jun 04 12:50:04 PM PDT 24 |
| Peak memory | 197844 kb |
| Host | smart-217656cb-3fd2-4e5c-9dda-f58bf9a0d007 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805724119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_cs r_outstanding.2805724119 |
| Directory | /workspace/13.uart_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/13.uart_tl_errors.2981779252 |
| Short name | T1291 |
| Test name | |
| Test status | |
| Simulation time | 33978327 ps |
| CPU time | 1.78 seconds |
| Started | Jun 04 12:49:58 PM PDT 24 |
| Finished | Jun 04 12:50:02 PM PDT 24 |
| Peak memory | 200232 kb |
| Host | smart-d978ab84-9437-4e57-b78f-f960afc724f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981779252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.2981779252 |
| Directory | /workspace/13.uart_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.1734624431 |
| Short name | T1268 |
| Test name | |
| Test status | |
| Simulation time | 45349966 ps |
| CPU time | 1 seconds |
| Started | Jun 04 12:50:00 PM PDT 24 |
| Finished | Jun 04 12:50:03 PM PDT 24 |
| Peak memory | 199184 kb |
| Host | smart-7da7b0f0-c9d7-4aac-b475-fced5f40972b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734624431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.1734624431 |
| Directory | /workspace/13.uart_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.524970856 |
| Short name | T1266 |
| Test name | |
| Test status | |
| Simulation time | 126384661 ps |
| CPU time | 0.87 seconds |
| Started | Jun 04 12:50:00 PM PDT 24 |
| Finished | Jun 04 12:50:03 PM PDT 24 |
| Peak memory | 200124 kb |
| Host | smart-4fe4f9d2-e817-43c6-a681-ad6aa85ab74c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524970856 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.524970856 |
| Directory | /workspace/14.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/14.uart_csr_rw.2747625070 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 15949039 ps |
| CPU time | 0.61 seconds |
| Started | Jun 04 12:49:57 PM PDT 24 |
| Finished | Jun 04 12:49:59 PM PDT 24 |
| Peak memory | 195728 kb |
| Host | smart-6b7b21ef-ee49-41ec-8073-88bac46c41c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747625070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.2747625070 |
| Directory | /workspace/14.uart_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/14.uart_intr_test.136680443 |
| Short name | T1198 |
| Test name | |
| Test status | |
| Simulation time | 37837311 ps |
| CPU time | 0.56 seconds |
| Started | Jun 04 12:49:58 PM PDT 24 |
| Finished | Jun 04 12:50:00 PM PDT 24 |
| Peak memory | 194624 kb |
| Host | smart-ee179b8b-5e18-4c1d-9c5c-a0c9063e20fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136680443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.136680443 |
| Directory | /workspace/14.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.634118616 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 71553632 ps |
| CPU time | 0.66 seconds |
| Started | Jun 04 12:49:57 PM PDT 24 |
| Finished | Jun 04 12:49:59 PM PDT 24 |
| Peak memory | 195812 kb |
| Host | smart-b1e7289b-4a07-4752-980f-413adc4d7d8e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634118616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_csr _outstanding.634118616 |
| Directory | /workspace/14.uart_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/14.uart_tl_errors.3196790497 |
| Short name | T1300 |
| Test name | |
| Test status | |
| Simulation time | 32757671 ps |
| CPU time | 0.97 seconds |
| Started | Jun 04 12:50:00 PM PDT 24 |
| Finished | Jun 04 12:50:04 PM PDT 24 |
| Peak memory | 200088 kb |
| Host | smart-8e742c4d-8ff4-49dc-9007-44be92952c23 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196790497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.3196790497 |
| Directory | /workspace/14.uart_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.512742712 |
| Short name | T1312 |
| Test name | |
| Test status | |
| Simulation time | 418355717 ps |
| CPU time | 1.3 seconds |
| Started | Jun 04 12:49:55 PM PDT 24 |
| Finished | Jun 04 12:49:57 PM PDT 24 |
| Peak memory | 199656 kb |
| Host | smart-61592891-56db-4a4a-b209-692ce3e23aff |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512742712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.512742712 |
| Directory | /workspace/14.uart_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.472175288 |
| Short name | T1246 |
| Test name | |
| Test status | |
| Simulation time | 52037047 ps |
| CPU time | 0.71 seconds |
| Started | Jun 04 12:49:56 PM PDT 24 |
| Finished | Jun 04 12:49:58 PM PDT 24 |
| Peak memory | 198728 kb |
| Host | smart-50cba599-8d38-4aea-9c1e-9abfe814d5b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472175288 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.472175288 |
| Directory | /workspace/15.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/15.uart_csr_rw.2676042813 |
| Short name | T1185 |
| Test name | |
| Test status | |
| Simulation time | 89996924 ps |
| CPU time | 0.6 seconds |
| Started | Jun 04 12:49:58 PM PDT 24 |
| Finished | Jun 04 12:50:00 PM PDT 24 |
| Peak memory | 195572 kb |
| Host | smart-548bbea2-8226-4329-851f-87342c3643e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676042813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.2676042813 |
| Directory | /workspace/15.uart_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/15.uart_intr_test.983311741 |
| Short name | T1299 |
| Test name | |
| Test status | |
| Simulation time | 42971794 ps |
| CPU time | 0.59 seconds |
| Started | Jun 04 12:49:58 PM PDT 24 |
| Finished | Jun 04 12:50:01 PM PDT 24 |
| Peak memory | 194612 kb |
| Host | smart-0979ac67-db61-41d3-bad9-784faf002fc2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983311741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.983311741 |
| Directory | /workspace/15.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.71296378 |
| Short name | T1243 |
| Test name | |
| Test status | |
| Simulation time | 57260304 ps |
| CPU time | 0.66 seconds |
| Started | Jun 04 12:50:04 PM PDT 24 |
| Finished | Jun 04 12:50:05 PM PDT 24 |
| Peak memory | 195868 kb |
| Host | smart-8f7aa73f-03b7-4743-a3f7-94c63375d312 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71296378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_csr_ outstanding.71296378 |
| Directory | /workspace/15.uart_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/15.uart_tl_errors.2512988956 |
| Short name | T1296 |
| Test name | |
| Test status | |
| Simulation time | 24658162 ps |
| CPU time | 1.25 seconds |
| Started | Jun 04 12:49:56 PM PDT 24 |
| Finished | Jun 04 12:49:59 PM PDT 24 |
| Peak memory | 200188 kb |
| Host | smart-f9f702f2-5dca-4804-b3f3-caf87a873fd0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512988956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.2512988956 |
| Directory | /workspace/15.uart_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.1486492329 |
| Short name | T1239 |
| Test name | |
| Test status | |
| Simulation time | 192110210 ps |
| CPU time | 0.97 seconds |
| Started | Jun 04 12:50:00 PM PDT 24 |
| Finished | Jun 04 12:50:04 PM PDT 24 |
| Peak memory | 199220 kb |
| Host | smart-7352534f-c9ed-4599-9e5a-684f969aca79 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486492329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.1486492329 |
| Directory | /workspace/15.uart_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.3988203113 |
| Short name | T1199 |
| Test name | |
| Test status | |
| Simulation time | 131234184 ps |
| CPU time | 0.8 seconds |
| Started | Jun 04 12:49:58 PM PDT 24 |
| Finished | Jun 04 12:50:00 PM PDT 24 |
| Peak memory | 200124 kb |
| Host | smart-4835e38f-8f39-4514-b0c0-b4bc49e23e55 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988203113 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.3988203113 |
| Directory | /workspace/16.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/16.uart_csr_rw.89141985 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 14208461 ps |
| CPU time | 0.63 seconds |
| Started | Jun 04 12:49:58 PM PDT 24 |
| Finished | Jun 04 12:50:00 PM PDT 24 |
| Peak memory | 195500 kb |
| Host | smart-db5f467f-c614-4292-946b-60ef006d3243 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89141985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.89141985 |
| Directory | /workspace/16.uart_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/16.uart_intr_test.226228237 |
| Short name | T1216 |
| Test name | |
| Test status | |
| Simulation time | 49962809 ps |
| CPU time | 0.6 seconds |
| Started | Jun 04 12:50:02 PM PDT 24 |
| Finished | Jun 04 12:50:04 PM PDT 24 |
| Peak memory | 194448 kb |
| Host | smart-851fabc1-745a-4471-8747-580cca0d3059 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226228237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.226228237 |
| Directory | /workspace/16.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.3960181003 |
| Short name | T1297 |
| Test name | |
| Test status | |
| Simulation time | 16097012 ps |
| CPU time | 0.73 seconds |
| Started | Jun 04 12:49:58 PM PDT 24 |
| Finished | Jun 04 12:50:00 PM PDT 24 |
| Peak memory | 196220 kb |
| Host | smart-a60bf1a9-1ec9-482c-bd9b-b4ca2d35054c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960181003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_cs r_outstanding.3960181003 |
| Directory | /workspace/16.uart_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/16.uart_tl_errors.2496953486 |
| Short name | T1305 |
| Test name | |
| Test status | |
| Simulation time | 863309566 ps |
| CPU time | 2.45 seconds |
| Started | Jun 04 12:49:57 PM PDT 24 |
| Finished | Jun 04 12:50:01 PM PDT 24 |
| Peak memory | 200168 kb |
| Host | smart-10766b80-4864-495d-a33e-e7722ab1fdaf |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496953486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.2496953486 |
| Directory | /workspace/16.uart_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.213088571 |
| Short name | T1294 |
| Test name | |
| Test status | |
| Simulation time | 96076492 ps |
| CPU time | 1.43 seconds |
| Started | Jun 04 12:50:00 PM PDT 24 |
| Finished | Jun 04 12:50:03 PM PDT 24 |
| Peak memory | 199704 kb |
| Host | smart-22adc4a4-a6ef-44c1-90e1-ea5e6bbe4a42 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213088571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.213088571 |
| Directory | /workspace/16.uart_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.825128123 |
| Short name | T1227 |
| Test name | |
| Test status | |
| Simulation time | 20625681 ps |
| CPU time | 0.68 seconds |
| Started | Jun 04 12:49:58 PM PDT 24 |
| Finished | Jun 04 12:50:00 PM PDT 24 |
| Peak memory | 198644 kb |
| Host | smart-e330b2a5-06fa-449b-962f-4a438034adf6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825128123 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.825128123 |
| Directory | /workspace/17.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/17.uart_csr_rw.1378020633 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 20193752 ps |
| CPU time | 0.61 seconds |
| Started | Jun 04 12:49:58 PM PDT 24 |
| Finished | Jun 04 12:50:00 PM PDT 24 |
| Peak memory | 195640 kb |
| Host | smart-a52e24d9-56dc-4020-b5f9-2657c0406a00 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378020633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.1378020633 |
| Directory | /workspace/17.uart_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/17.uart_intr_test.2648494112 |
| Short name | T1288 |
| Test name | |
| Test status | |
| Simulation time | 40557988 ps |
| CPU time | 0.56 seconds |
| Started | Jun 04 12:49:58 PM PDT 24 |
| Finished | Jun 04 12:50:00 PM PDT 24 |
| Peak memory | 194700 kb |
| Host | smart-260764b5-bde9-4f22-b9bd-aaf163dbc69c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648494112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.2648494112 |
| Directory | /workspace/17.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.3171777107 |
| Short name | T1226 |
| Test name | |
| Test status | |
| Simulation time | 64485621 ps |
| CPU time | 0.72 seconds |
| Started | Jun 04 12:49:56 PM PDT 24 |
| Finished | Jun 04 12:49:58 PM PDT 24 |
| Peak memory | 197160 kb |
| Host | smart-e38c84d3-d1cd-4f49-a010-222806669c74 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171777107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_cs r_outstanding.3171777107 |
| Directory | /workspace/17.uart_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/17.uart_tl_errors.1321410245 |
| Short name | T1298 |
| Test name | |
| Test status | |
| Simulation time | 105409801 ps |
| CPU time | 1.93 seconds |
| Started | Jun 04 12:49:58 PM PDT 24 |
| Finished | Jun 04 12:50:01 PM PDT 24 |
| Peak memory | 200224 kb |
| Host | smart-2cb68efe-79e3-4d49-8b07-d13474dae4b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321410245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.1321410245 |
| Directory | /workspace/17.uart_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.213928081 |
| Short name | T1193 |
| Test name | |
| Test status | |
| Simulation time | 30622989 ps |
| CPU time | 1.02 seconds |
| Started | Jun 04 12:49:59 PM PDT 24 |
| Finished | Jun 04 12:50:02 PM PDT 24 |
| Peak memory | 200132 kb |
| Host | smart-78455006-c757-4ad8-889b-6f2cfeb83aa0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213928081 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.213928081 |
| Directory | /workspace/18.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/18.uart_csr_rw.3979121999 |
| Short name | T1240 |
| Test name | |
| Test status | |
| Simulation time | 171527319 ps |
| CPU time | 0.64 seconds |
| Started | Jun 04 12:50:00 PM PDT 24 |
| Finished | Jun 04 12:50:03 PM PDT 24 |
| Peak memory | 195724 kb |
| Host | smart-f363283f-8513-4fb2-993f-d3890206de4a |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979121999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.3979121999 |
| Directory | /workspace/18.uart_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/18.uart_intr_test.3397209073 |
| Short name | T1251 |
| Test name | |
| Test status | |
| Simulation time | 140651317 ps |
| CPU time | 0.59 seconds |
| Started | Jun 04 12:49:58 PM PDT 24 |
| Finished | Jun 04 12:50:00 PM PDT 24 |
| Peak memory | 194512 kb |
| Host | smart-a62bd880-10e8-4820-9990-70a0927660dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397209073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.3397209073 |
| Directory | /workspace/18.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.3662904739 |
| Short name | T1217 |
| Test name | |
| Test status | |
| Simulation time | 134723640 ps |
| CPU time | 0.72 seconds |
| Started | Jun 04 12:49:58 PM PDT 24 |
| Finished | Jun 04 12:50:01 PM PDT 24 |
| Peak memory | 197824 kb |
| Host | smart-e24ba188-ffef-4755-ae89-52f0ade15b14 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662904739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_cs r_outstanding.3662904739 |
| Directory | /workspace/18.uart_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/18.uart_tl_errors.1958764631 |
| Short name | T1283 |
| Test name | |
| Test status | |
| Simulation time | 239851301 ps |
| CPU time | 1.49 seconds |
| Started | Jun 04 12:49:56 PM PDT 24 |
| Finished | Jun 04 12:49:59 PM PDT 24 |
| Peak memory | 200188 kb |
| Host | smart-6eb10597-1b3c-4d42-8cca-aef0f0a9190b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958764631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.1958764631 |
| Directory | /workspace/18.uart_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.891428086 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 416911621 ps |
| CPU time | 1.33 seconds |
| Started | Jun 04 12:49:58 PM PDT 24 |
| Finished | Jun 04 12:50:02 PM PDT 24 |
| Peak memory | 199620 kb |
| Host | smart-457a1fda-094e-4cfe-af9f-d1f289f83a69 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891428086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.891428086 |
| Directory | /workspace/18.uart_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.1857847050 |
| Short name | T1209 |
| Test name | |
| Test status | |
| Simulation time | 27905922 ps |
| CPU time | 1.36 seconds |
| Started | Jun 04 12:50:01 PM PDT 24 |
| Finished | Jun 04 12:50:04 PM PDT 24 |
| Peak memory | 200528 kb |
| Host | smart-d03a05f1-07fd-494f-bc12-7797d4932608 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857847050 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.1857847050 |
| Directory | /workspace/19.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/19.uart_csr_rw.3479638647 |
| Short name | T1188 |
| Test name | |
| Test status | |
| Simulation time | 42681369 ps |
| CPU time | 0.57 seconds |
| Started | Jun 04 12:49:56 PM PDT 24 |
| Finished | Jun 04 12:49:57 PM PDT 24 |
| Peak memory | 195592 kb |
| Host | smart-8e5f8ddf-42d6-4adc-b1f2-2668bd470008 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479638647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.3479638647 |
| Directory | /workspace/19.uart_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/19.uart_intr_test.1878344214 |
| Short name | T1292 |
| Test name | |
| Test status | |
| Simulation time | 51076695 ps |
| CPU time | 0.6 seconds |
| Started | Jun 04 12:49:59 PM PDT 24 |
| Finished | Jun 04 12:50:01 PM PDT 24 |
| Peak memory | 194604 kb |
| Host | smart-64676ad5-4c1b-4e0e-90a3-ba26cb852885 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878344214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.1878344214 |
| Directory | /workspace/19.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.2639384998 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 13904564 ps |
| CPU time | 0.65 seconds |
| Started | Jun 04 12:49:59 PM PDT 24 |
| Finished | Jun 04 12:50:02 PM PDT 24 |
| Peak memory | 196084 kb |
| Host | smart-3dbdc34b-cbeb-411d-b6c1-60caaac2ace8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639384998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_cs r_outstanding.2639384998 |
| Directory | /workspace/19.uart_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/19.uart_tl_errors.3428967025 |
| Short name | T1301 |
| Test name | |
| Test status | |
| Simulation time | 86954089 ps |
| CPU time | 2.25 seconds |
| Started | Jun 04 12:50:02 PM PDT 24 |
| Finished | Jun 04 12:50:06 PM PDT 24 |
| Peak memory | 200160 kb |
| Host | smart-b973dbcb-27e0-4f26-b804-238e1ed39a0e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428967025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.3428967025 |
| Directory | /workspace/19.uart_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.590678292 |
| Short name | T1313 |
| Test name | |
| Test status | |
| Simulation time | 136229109 ps |
| CPU time | 0.91 seconds |
| Started | Jun 04 12:49:58 PM PDT 24 |
| Finished | Jun 04 12:50:01 PM PDT 24 |
| Peak memory | 199052 kb |
| Host | smart-f95b543e-f65f-4b1f-b506-03155da1ccc3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590678292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.590678292 |
| Directory | /workspace/19.uart_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.719456077 |
| Short name | T1311 |
| Test name | |
| Test status | |
| Simulation time | 26196490 ps |
| CPU time | 0.66 seconds |
| Started | Jun 04 12:49:42 PM PDT 24 |
| Finished | Jun 04 12:49:43 PM PDT 24 |
| Peak memory | 195664 kb |
| Host | smart-cd5c660f-c1db-4b44-8db6-7a4aceac2c03 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719456077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.719456077 |
| Directory | /workspace/2.uart_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.2748693055 |
| Short name | T1182 |
| Test name | |
| Test status | |
| Simulation time | 134600111 ps |
| CPU time | 1.57 seconds |
| Started | Jun 04 12:49:41 PM PDT 24 |
| Finished | Jun 04 12:49:43 PM PDT 24 |
| Peak memory | 197880 kb |
| Host | smart-5f3bce7a-0ed9-4526-80db-566cdf7b7503 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748693055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.2748693055 |
| Directory | /workspace/2.uart_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.3485506320 |
| Short name | T1275 |
| Test name | |
| Test status | |
| Simulation time | 15918686 ps |
| CPU time | 0.61 seconds |
| Started | Jun 04 12:49:39 PM PDT 24 |
| Finished | Jun 04 12:49:41 PM PDT 24 |
| Peak memory | 195636 kb |
| Host | smart-356416ba-7f2a-45d5-8b17-73909a9aa836 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485506320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.3485506320 |
| Directory | /workspace/2.uart_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.3364985062 |
| Short name | T1179 |
| Test name | |
| Test status | |
| Simulation time | 31922200 ps |
| CPU time | 0.92 seconds |
| Started | Jun 04 12:49:39 PM PDT 24 |
| Finished | Jun 04 12:49:40 PM PDT 24 |
| Peak memory | 200000 kb |
| Host | smart-c8a6ca35-36da-448e-829b-dc95556d836b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364985062 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.3364985062 |
| Directory | /workspace/2.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.uart_csr_rw.1629884351 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 11166242 ps |
| CPU time | 0.66 seconds |
| Started | Jun 04 12:49:43 PM PDT 24 |
| Finished | Jun 04 12:49:44 PM PDT 24 |
| Peak memory | 195512 kb |
| Host | smart-d99de98f-89af-4549-b529-7c0594b73fc2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629884351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.1629884351 |
| Directory | /workspace/2.uart_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/2.uart_intr_test.3772126855 |
| Short name | T1196 |
| Test name | |
| Test status | |
| Simulation time | 38276081 ps |
| CPU time | 0.57 seconds |
| Started | Jun 04 12:49:37 PM PDT 24 |
| Finished | Jun 04 12:49:38 PM PDT 24 |
| Peak memory | 194472 kb |
| Host | smart-2ef01030-18da-48da-8d10-ed7633235058 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772126855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.3772126855 |
| Directory | /workspace/2.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.3632326458 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 24233755 ps |
| CPU time | 0.67 seconds |
| Started | Jun 04 12:49:39 PM PDT 24 |
| Finished | Jun 04 12:49:41 PM PDT 24 |
| Peak memory | 195172 kb |
| Host | smart-aca516be-b85f-4c8d-9690-340e619811bb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632326458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr _outstanding.3632326458 |
| Directory | /workspace/2.uart_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/2.uart_tl_errors.3449672990 |
| Short name | T1225 |
| Test name | |
| Test status | |
| Simulation time | 91455041 ps |
| CPU time | 2 seconds |
| Started | Jun 04 12:49:39 PM PDT 24 |
| Finished | Jun 04 12:49:42 PM PDT 24 |
| Peak memory | 200172 kb |
| Host | smart-0ba77f37-7921-4369-bf1a-6bd9cfb9fb7c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449672990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.3449672990 |
| Directory | /workspace/2.uart_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.1883506184 |
| Short name | T1269 |
| Test name | |
| Test status | |
| Simulation time | 254445499 ps |
| CPU time | 1.24 seconds |
| Started | Jun 04 12:49:39 PM PDT 24 |
| Finished | Jun 04 12:49:41 PM PDT 24 |
| Peak memory | 199348 kb |
| Host | smart-f61f4b55-a7bf-4251-a777-1d252f7db0e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883506184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.1883506184 |
| Directory | /workspace/2.uart_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/20.uart_intr_test.4284991324 |
| Short name | T1256 |
| Test name | |
| Test status | |
| Simulation time | 13509451 ps |
| CPU time | 0.65 seconds |
| Started | Jun 04 12:50:01 PM PDT 24 |
| Finished | Jun 04 12:50:04 PM PDT 24 |
| Peak memory | 194792 kb |
| Host | smart-22c5e9cc-213f-454c-96af-d856db64e343 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284991324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.4284991324 |
| Directory | /workspace/20.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/21.uart_intr_test.3030127370 |
| Short name | T1197 |
| Test name | |
| Test status | |
| Simulation time | 109044975 ps |
| CPU time | 0.57 seconds |
| Started | Jun 04 12:50:00 PM PDT 24 |
| Finished | Jun 04 12:50:03 PM PDT 24 |
| Peak memory | 194484 kb |
| Host | smart-121a7582-e009-4274-980a-c0471f6b32b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030127370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.3030127370 |
| Directory | /workspace/21.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/22.uart_intr_test.3932264072 |
| Short name | T1186 |
| Test name | |
| Test status | |
| Simulation time | 45129939 ps |
| CPU time | 0.62 seconds |
| Started | Jun 04 12:50:01 PM PDT 24 |
| Finished | Jun 04 12:50:03 PM PDT 24 |
| Peak memory | 194788 kb |
| Host | smart-bedd547a-ff57-4aae-8c67-36e822647073 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932264072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.3932264072 |
| Directory | /workspace/22.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/23.uart_intr_test.3558951813 |
| Short name | T1236 |
| Test name | |
| Test status | |
| Simulation time | 38541067 ps |
| CPU time | 0.59 seconds |
| Started | Jun 04 12:50:00 PM PDT 24 |
| Finished | Jun 04 12:50:02 PM PDT 24 |
| Peak memory | 194512 kb |
| Host | smart-93010990-0ed1-4267-b77e-9e989a38348f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558951813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.3558951813 |
| Directory | /workspace/23.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/24.uart_intr_test.3458871595 |
| Short name | T1274 |
| Test name | |
| Test status | |
| Simulation time | 13626280 ps |
| CPU time | 0.58 seconds |
| Started | Jun 04 12:49:58 PM PDT 24 |
| Finished | Jun 04 12:50:00 PM PDT 24 |
| Peak memory | 194500 kb |
| Host | smart-8ddd8210-1e56-4ade-8cdd-ca11304b8b07 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458871595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.3458871595 |
| Directory | /workspace/24.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/25.uart_intr_test.4200675005 |
| Short name | T1238 |
| Test name | |
| Test status | |
| Simulation time | 34829110 ps |
| CPU time | 0.61 seconds |
| Started | Jun 04 12:50:00 PM PDT 24 |
| Finished | Jun 04 12:50:03 PM PDT 24 |
| Peak memory | 194772 kb |
| Host | smart-e3d3b638-7185-47af-a3c9-d8a02b629aaf |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200675005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.4200675005 |
| Directory | /workspace/25.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/26.uart_intr_test.1578362672 |
| Short name | T1259 |
| Test name | |
| Test status | |
| Simulation time | 30300444 ps |
| CPU time | 0.59 seconds |
| Started | Jun 04 12:49:57 PM PDT 24 |
| Finished | Jun 04 12:49:59 PM PDT 24 |
| Peak memory | 194524 kb |
| Host | smart-662e63ee-8d91-4e60-91c0-81436de4edab |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578362672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.1578362672 |
| Directory | /workspace/26.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/27.uart_intr_test.1748549027 |
| Short name | T1249 |
| Test name | |
| Test status | |
| Simulation time | 16192962 ps |
| CPU time | 0.58 seconds |
| Started | Jun 04 12:49:57 PM PDT 24 |
| Finished | Jun 04 12:49:59 PM PDT 24 |
| Peak memory | 194568 kb |
| Host | smart-4c36bc4c-3c0b-4e31-b2f9-f16ccdf263cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748549027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.1748549027 |
| Directory | /workspace/27.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/28.uart_intr_test.2780026917 |
| Short name | T1314 |
| Test name | |
| Test status | |
| Simulation time | 25016896 ps |
| CPU time | 0.59 seconds |
| Started | Jun 04 12:50:01 PM PDT 24 |
| Finished | Jun 04 12:50:04 PM PDT 24 |
| Peak memory | 194576 kb |
| Host | smart-f3979e88-210b-40fb-9702-22f9439095b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780026917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.2780026917 |
| Directory | /workspace/28.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/29.uart_intr_test.2922378986 |
| Short name | T1285 |
| Test name | |
| Test status | |
| Simulation time | 14663556 ps |
| CPU time | 0.58 seconds |
| Started | Jun 04 12:50:00 PM PDT 24 |
| Finished | Jun 04 12:50:03 PM PDT 24 |
| Peak memory | 194552 kb |
| Host | smart-79cc7416-4214-4f67-849e-2c7c5a9266de |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922378986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.2922378986 |
| Directory | /workspace/29.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.3828154175 |
| Short name | T1214 |
| Test name | |
| Test status | |
| Simulation time | 15230822 ps |
| CPU time | 0.74 seconds |
| Started | Jun 04 12:49:36 PM PDT 24 |
| Finished | Jun 04 12:49:37 PM PDT 24 |
| Peak memory | 196556 kb |
| Host | smart-9311dbee-c543-4567-9e67-9576b5ba1222 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828154175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.3828154175 |
| Directory | /workspace/3.uart_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.1136834217 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 650937838 ps |
| CPU time | 2.23 seconds |
| Started | Jun 04 12:49:37 PM PDT 24 |
| Finished | Jun 04 12:49:40 PM PDT 24 |
| Peak memory | 198004 kb |
| Host | smart-bcd00784-fc39-4da0-833b-560b72894093 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136834217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.1136834217 |
| Directory | /workspace/3.uart_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.3718283967 |
| Short name | T1309 |
| Test name | |
| Test status | |
| Simulation time | 18356719 ps |
| CPU time | 0.61 seconds |
| Started | Jun 04 12:49:41 PM PDT 24 |
| Finished | Jun 04 12:49:42 PM PDT 24 |
| Peak memory | 195644 kb |
| Host | smart-b9701e19-cf4f-4aa6-8404-8b62c22f2885 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718283967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.3718283967 |
| Directory | /workspace/3.uart_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.2811175165 |
| Short name | T1310 |
| Test name | |
| Test status | |
| Simulation time | 25665695 ps |
| CPU time | 0.71 seconds |
| Started | Jun 04 12:49:47 PM PDT 24 |
| Finished | Jun 04 12:49:48 PM PDT 24 |
| Peak memory | 197984 kb |
| Host | smart-947c2ff0-5f1b-45e9-9660-1952f331d55d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811175165 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.2811175165 |
| Directory | /workspace/3.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.uart_csr_rw.2804158818 |
| Short name | T1263 |
| Test name | |
| Test status | |
| Simulation time | 22473918 ps |
| CPU time | 0.59 seconds |
| Started | Jun 04 12:49:41 PM PDT 24 |
| Finished | Jun 04 12:49:42 PM PDT 24 |
| Peak memory | 195640 kb |
| Host | smart-d2ab75a6-1015-4435-bd7c-fe16573ba158 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804158818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.2804158818 |
| Directory | /workspace/3.uart_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/3.uart_intr_test.3008535502 |
| Short name | T1192 |
| Test name | |
| Test status | |
| Simulation time | 14479754 ps |
| CPU time | 0.57 seconds |
| Started | Jun 04 12:49:40 PM PDT 24 |
| Finished | Jun 04 12:49:42 PM PDT 24 |
| Peak memory | 194612 kb |
| Host | smart-4a438799-e4be-4559-b3e8-0172962858c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008535502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.3008535502 |
| Directory | /workspace/3.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.855080692 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 31010253 ps |
| CPU time | 0.75 seconds |
| Started | Jun 04 12:49:39 PM PDT 24 |
| Finished | Jun 04 12:49:40 PM PDT 24 |
| Peak memory | 197392 kb |
| Host | smart-476d6ca3-2ef5-47ca-98ef-9c965d4bfbe6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855080692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr_ outstanding.855080692 |
| Directory | /workspace/3.uart_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/3.uart_tl_errors.3700198136 |
| Short name | T1258 |
| Test name | |
| Test status | |
| Simulation time | 141182436 ps |
| CPU time | 2.5 seconds |
| Started | Jun 04 12:49:42 PM PDT 24 |
| Finished | Jun 04 12:49:45 PM PDT 24 |
| Peak memory | 200156 kb |
| Host | smart-fc4b791f-ed06-43df-888a-3959ae945019 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700198136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.3700198136 |
| Directory | /workspace/3.uart_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.4143213360 |
| Short name | T1278 |
| Test name | |
| Test status | |
| Simulation time | 45274829 ps |
| CPU time | 0.92 seconds |
| Started | Jun 04 12:49:40 PM PDT 24 |
| Finished | Jun 04 12:49:41 PM PDT 24 |
| Peak memory | 198928 kb |
| Host | smart-2e2fd2bb-18ac-43e7-8db9-2d801e81b885 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143213360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.4143213360 |
| Directory | /workspace/3.uart_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/30.uart_intr_test.253452483 |
| Short name | T1245 |
| Test name | |
| Test status | |
| Simulation time | 44900210 ps |
| CPU time | 0.57 seconds |
| Started | Jun 04 12:50:01 PM PDT 24 |
| Finished | Jun 04 12:50:04 PM PDT 24 |
| Peak memory | 194564 kb |
| Host | smart-dd9be6c9-f593-49e4-9aff-fc67dfd8200f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253452483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.253452483 |
| Directory | /workspace/30.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/31.uart_intr_test.1797751535 |
| Short name | T1279 |
| Test name | |
| Test status | |
| Simulation time | 80091531 ps |
| CPU time | 0.58 seconds |
| Started | Jun 04 12:50:03 PM PDT 24 |
| Finished | Jun 04 12:50:05 PM PDT 24 |
| Peak memory | 194660 kb |
| Host | smart-11c4ef7a-1739-4943-ac3e-1577c9fabc4e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797751535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.1797751535 |
| Directory | /workspace/31.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/32.uart_intr_test.2060597312 |
| Short name | T1261 |
| Test name | |
| Test status | |
| Simulation time | 13870449 ps |
| CPU time | 0.62 seconds |
| Started | Jun 04 12:49:59 PM PDT 24 |
| Finished | Jun 04 12:50:02 PM PDT 24 |
| Peak memory | 194584 kb |
| Host | smart-48fcaaa8-ca1f-4c08-a782-a7da0a1571c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060597312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.2060597312 |
| Directory | /workspace/32.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/33.uart_intr_test.3589400966 |
| Short name | T1284 |
| Test name | |
| Test status | |
| Simulation time | 13515305 ps |
| CPU time | 0.59 seconds |
| Started | Jun 04 12:50:01 PM PDT 24 |
| Finished | Jun 04 12:50:04 PM PDT 24 |
| Peak memory | 194584 kb |
| Host | smart-c9ce7d63-adc6-4a65-a117-1d78cca5275e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589400966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.3589400966 |
| Directory | /workspace/33.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/34.uart_intr_test.489739215 |
| Short name | T1295 |
| Test name | |
| Test status | |
| Simulation time | 13287809 ps |
| CPU time | 0.57 seconds |
| Started | Jun 04 12:50:00 PM PDT 24 |
| Finished | Jun 04 12:50:03 PM PDT 24 |
| Peak memory | 194640 kb |
| Host | smart-cdf5b75d-d562-4cc4-8234-2ea099949544 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489739215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.489739215 |
| Directory | /workspace/34.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/35.uart_intr_test.3077166734 |
| Short name | T1220 |
| Test name | |
| Test status | |
| Simulation time | 13193471 ps |
| CPU time | 0.57 seconds |
| Started | Jun 04 12:50:02 PM PDT 24 |
| Finished | Jun 04 12:50:04 PM PDT 24 |
| Peak memory | 194480 kb |
| Host | smart-2cf4745e-2ab9-4c2f-8fb1-89e6959794bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077166734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.3077166734 |
| Directory | /workspace/35.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/36.uart_intr_test.197874091 |
| Short name | T1235 |
| Test name | |
| Test status | |
| Simulation time | 13239415 ps |
| CPU time | 0.57 seconds |
| Started | Jun 04 12:50:00 PM PDT 24 |
| Finished | Jun 04 12:50:02 PM PDT 24 |
| Peak memory | 194456 kb |
| Host | smart-00e119ce-5f70-495f-9697-74359de5bccc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197874091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.197874091 |
| Directory | /workspace/36.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/37.uart_intr_test.3764036891 |
| Short name | T1317 |
| Test name | |
| Test status | |
| Simulation time | 40849727 ps |
| CPU time | 0.55 seconds |
| Started | Jun 04 12:50:00 PM PDT 24 |
| Finished | Jun 04 12:50:03 PM PDT 24 |
| Peak memory | 194480 kb |
| Host | smart-dc7e77c2-b001-44d4-b0ad-aed5c972bf4e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764036891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.3764036891 |
| Directory | /workspace/37.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/38.uart_intr_test.278429173 |
| Short name | T1191 |
| Test name | |
| Test status | |
| Simulation time | 13186627 ps |
| CPU time | 0.6 seconds |
| Started | Jun 04 12:49:59 PM PDT 24 |
| Finished | Jun 04 12:50:01 PM PDT 24 |
| Peak memory | 194460 kb |
| Host | smart-9cd1a2f6-b059-47e8-80b8-8957a939d03d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278429173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.278429173 |
| Directory | /workspace/38.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/39.uart_intr_test.1555957565 |
| Short name | T1281 |
| Test name | |
| Test status | |
| Simulation time | 24530150 ps |
| CPU time | 0.56 seconds |
| Started | Jun 04 12:50:03 PM PDT 24 |
| Finished | Jun 04 12:50:05 PM PDT 24 |
| Peak memory | 194700 kb |
| Host | smart-26e6afa4-8fa9-477a-87f1-21fbfa26512a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555957565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.1555957565 |
| Directory | /workspace/39.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.3803549989 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 70570523 ps |
| CPU time | 0.63 seconds |
| Started | Jun 04 12:49:48 PM PDT 24 |
| Finished | Jun 04 12:49:50 PM PDT 24 |
| Peak memory | 195164 kb |
| Host | smart-61696cab-fc0e-4667-9e19-fe5a680a4c81 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803549989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.3803549989 |
| Directory | /workspace/4.uart_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.2883964343 |
| Short name | T1315 |
| Test name | |
| Test status | |
| Simulation time | 95889070 ps |
| CPU time | 1.49 seconds |
| Started | Jun 04 12:49:50 PM PDT 24 |
| Finished | Jun 04 12:49:52 PM PDT 24 |
| Peak memory | 197824 kb |
| Host | smart-fab8f4f6-1c02-41f4-bb72-a8ee7571d885 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883964343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.2883964343 |
| Directory | /workspace/4.uart_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.1558819397 |
| Short name | T1306 |
| Test name | |
| Test status | |
| Simulation time | 18372220 ps |
| CPU time | 0.64 seconds |
| Started | Jun 04 12:49:47 PM PDT 24 |
| Finished | Jun 04 12:49:49 PM PDT 24 |
| Peak memory | 195668 kb |
| Host | smart-d0679159-4dee-4d6c-91c0-b922dce78b90 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558819397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.1558819397 |
| Directory | /workspace/4.uart_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.1805257202 |
| Short name | T1212 |
| Test name | |
| Test status | |
| Simulation time | 41558983 ps |
| CPU time | 0.75 seconds |
| Started | Jun 04 12:49:47 PM PDT 24 |
| Finished | Jun 04 12:49:49 PM PDT 24 |
| Peak memory | 198620 kb |
| Host | smart-a1794de8-4a01-4da4-b685-460c65169e3d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805257202 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.1805257202 |
| Directory | /workspace/4.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.uart_csr_rw.3482298596 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 23747839 ps |
| CPU time | 0.63 seconds |
| Started | Jun 04 12:49:49 PM PDT 24 |
| Finished | Jun 04 12:49:51 PM PDT 24 |
| Peak memory | 195748 kb |
| Host | smart-b412b611-77c6-4c6a-8b84-78e8c40eeabe |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482298596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.3482298596 |
| Directory | /workspace/4.uart_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/4.uart_intr_test.2795656564 |
| Short name | T1211 |
| Test name | |
| Test status | |
| Simulation time | 17009142 ps |
| CPU time | 0.59 seconds |
| Started | Jun 04 12:49:48 PM PDT 24 |
| Finished | Jun 04 12:49:50 PM PDT 24 |
| Peak memory | 194624 kb |
| Host | smart-1dbacecc-201d-40b3-9c90-6456dab4cf3a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795656564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.2795656564 |
| Directory | /workspace/4.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.2704267675 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 40679161 ps |
| CPU time | 0.61 seconds |
| Started | Jun 04 12:49:47 PM PDT 24 |
| Finished | Jun 04 12:49:49 PM PDT 24 |
| Peak memory | 195808 kb |
| Host | smart-e3f5a399-15f5-459b-ae08-36506a80fe91 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704267675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr _outstanding.2704267675 |
| Directory | /workspace/4.uart_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/4.uart_tl_errors.2384783960 |
| Short name | T1242 |
| Test name | |
| Test status | |
| Simulation time | 164455756 ps |
| CPU time | 1.07 seconds |
| Started | Jun 04 12:49:45 PM PDT 24 |
| Finished | Jun 04 12:49:46 PM PDT 24 |
| Peak memory | 200004 kb |
| Host | smart-936734fb-aaa2-40c9-a419-9117e6d52061 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384783960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.2384783960 |
| Directory | /workspace/4.uart_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.3308626578 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 81212809 ps |
| CPU time | 0.96 seconds |
| Started | Jun 04 12:49:51 PM PDT 24 |
| Finished | Jun 04 12:49:53 PM PDT 24 |
| Peak memory | 199412 kb |
| Host | smart-b6295379-b25a-4fcb-8ab3-2d67a7fc60c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308626578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.3308626578 |
| Directory | /workspace/4.uart_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/40.uart_intr_test.1351267500 |
| Short name | T1276 |
| Test name | |
| Test status | |
| Simulation time | 48152417 ps |
| CPU time | 0.56 seconds |
| Started | Jun 04 12:50:02 PM PDT 24 |
| Finished | Jun 04 12:50:04 PM PDT 24 |
| Peak memory | 194532 kb |
| Host | smart-21337a77-74f6-48f8-993b-5915a8f29a3d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351267500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.1351267500 |
| Directory | /workspace/40.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/41.uart_intr_test.2618860500 |
| Short name | T1302 |
| Test name | |
| Test status | |
| Simulation time | 35140885 ps |
| CPU time | 0.6 seconds |
| Started | Jun 04 12:50:10 PM PDT 24 |
| Finished | Jun 04 12:50:11 PM PDT 24 |
| Peak memory | 194580 kb |
| Host | smart-9093512b-7a12-4102-8073-68d1fb32b2c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618860500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.2618860500 |
| Directory | /workspace/41.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/42.uart_intr_test.200402838 |
| Short name | T1180 |
| Test name | |
| Test status | |
| Simulation time | 33010180 ps |
| CPU time | 0.56 seconds |
| Started | Jun 04 12:50:13 PM PDT 24 |
| Finished | Jun 04 12:50:16 PM PDT 24 |
| Peak memory | 194580 kb |
| Host | smart-2f28b779-58d5-4685-8dad-061780dedaa0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200402838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.200402838 |
| Directory | /workspace/42.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/43.uart_intr_test.2447919232 |
| Short name | T1233 |
| Test name | |
| Test status | |
| Simulation time | 156435393 ps |
| CPU time | 0.54 seconds |
| Started | Jun 04 12:50:12 PM PDT 24 |
| Finished | Jun 04 12:50:14 PM PDT 24 |
| Peak memory | 194580 kb |
| Host | smart-4577d6ae-7689-4248-beee-10ac2e0e6d60 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447919232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.2447919232 |
| Directory | /workspace/43.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/44.uart_intr_test.1658495433 |
| Short name | T1205 |
| Test name | |
| Test status | |
| Simulation time | 14195739 ps |
| CPU time | 0.58 seconds |
| Started | Jun 04 12:50:09 PM PDT 24 |
| Finished | Jun 04 12:50:10 PM PDT 24 |
| Peak memory | 194480 kb |
| Host | smart-2b84e58e-e78e-4849-8a15-0af6c206b5a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658495433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.1658495433 |
| Directory | /workspace/44.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/45.uart_intr_test.351005545 |
| Short name | T1206 |
| Test name | |
| Test status | |
| Simulation time | 27163337 ps |
| CPU time | 0.57 seconds |
| Started | Jun 04 12:50:10 PM PDT 24 |
| Finished | Jun 04 12:50:12 PM PDT 24 |
| Peak memory | 194628 kb |
| Host | smart-be10da05-f16c-474e-90f4-2e58a4243505 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351005545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.351005545 |
| Directory | /workspace/45.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/46.uart_intr_test.1252136306 |
| Short name | T1271 |
| Test name | |
| Test status | |
| Simulation time | 12621600 ps |
| CPU time | 0.57 seconds |
| Started | Jun 04 12:50:12 PM PDT 24 |
| Finished | Jun 04 12:50:14 PM PDT 24 |
| Peak memory | 194640 kb |
| Host | smart-25264da1-d139-4f67-9c00-af17f4daade5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252136306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.1252136306 |
| Directory | /workspace/46.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/47.uart_intr_test.3917865884 |
| Short name | T1207 |
| Test name | |
| Test status | |
| Simulation time | 32763341 ps |
| CPU time | 0.57 seconds |
| Started | Jun 04 12:50:10 PM PDT 24 |
| Finished | Jun 04 12:50:12 PM PDT 24 |
| Peak memory | 194572 kb |
| Host | smart-d9cc5406-2a39-4c3e-a11e-38f69f7c9834 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917865884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.3917865884 |
| Directory | /workspace/47.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/48.uart_intr_test.334207590 |
| Short name | T1181 |
| Test name | |
| Test status | |
| Simulation time | 50298237 ps |
| CPU time | 0.6 seconds |
| Started | Jun 04 12:50:11 PM PDT 24 |
| Finished | Jun 04 12:50:13 PM PDT 24 |
| Peak memory | 194492 kb |
| Host | smart-0c7e03b6-7710-4ef2-a42c-5981c0f7cc61 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334207590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.334207590 |
| Directory | /workspace/48.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/49.uart_intr_test.3544048534 |
| Short name | T1316 |
| Test name | |
| Test status | |
| Simulation time | 12909014 ps |
| CPU time | 0.55 seconds |
| Started | Jun 04 12:50:11 PM PDT 24 |
| Finished | Jun 04 12:50:12 PM PDT 24 |
| Peak memory | 194532 kb |
| Host | smart-6b5a7a8c-3e12-45ea-b9c3-eced9d1fb3ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544048534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.3544048534 |
| Directory | /workspace/49.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.397395228 |
| Short name | T1270 |
| Test name | |
| Test status | |
| Simulation time | 244781380 ps |
| CPU time | 1.05 seconds |
| Started | Jun 04 12:49:47 PM PDT 24 |
| Finished | Jun 04 12:49:49 PM PDT 24 |
| Peak memory | 200132 kb |
| Host | smart-e0a4f996-aa87-4094-8deb-65b102368855 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397395228 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.397395228 |
| Directory | /workspace/5.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/5.uart_csr_rw.3786780990 |
| Short name | T1267 |
| Test name | |
| Test status | |
| Simulation time | 49266155 ps |
| CPU time | 0.57 seconds |
| Started | Jun 04 12:49:46 PM PDT 24 |
| Finished | Jun 04 12:49:47 PM PDT 24 |
| Peak memory | 195504 kb |
| Host | smart-4ca5d398-b290-4773-be03-1be972756058 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786780990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.3786780990 |
| Directory | /workspace/5.uart_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/5.uart_intr_test.3465585959 |
| Short name | T1304 |
| Test name | |
| Test status | |
| Simulation time | 12927691 ps |
| CPU time | 0.57 seconds |
| Started | Jun 04 12:49:48 PM PDT 24 |
| Finished | Jun 04 12:49:50 PM PDT 24 |
| Peak memory | 194612 kb |
| Host | smart-0d561bfd-d66b-4cb1-93d5-f74db2de04b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465585959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.3465585959 |
| Directory | /workspace/5.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.2392785644 |
| Short name | T1286 |
| Test name | |
| Test status | |
| Simulation time | 86752443 ps |
| CPU time | 0.74 seconds |
| Started | Jun 04 12:49:50 PM PDT 24 |
| Finished | Jun 04 12:49:52 PM PDT 24 |
| Peak memory | 195972 kb |
| Host | smart-d663e916-a884-484a-85b4-4a3086608fcf |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392785644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr _outstanding.2392785644 |
| Directory | /workspace/5.uart_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/5.uart_tl_errors.3851686112 |
| Short name | T1232 |
| Test name | |
| Test status | |
| Simulation time | 59756072 ps |
| CPU time | 1.38 seconds |
| Started | Jun 04 12:49:53 PM PDT 24 |
| Finished | Jun 04 12:49:55 PM PDT 24 |
| Peak memory | 200172 kb |
| Host | smart-08c0d878-3b3b-4f84-8ecd-c8e1a7ab1143 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851686112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.3851686112 |
| Directory | /workspace/5.uart_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.3150836560 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 73892461 ps |
| CPU time | 1.27 seconds |
| Started | Jun 04 12:49:51 PM PDT 24 |
| Finished | Jun 04 12:49:53 PM PDT 24 |
| Peak memory | 199600 kb |
| Host | smart-332dfae4-29ae-4163-b1ee-94a6337fa885 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150836560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.3150836560 |
| Directory | /workspace/5.uart_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.1618210844 |
| Short name | T1264 |
| Test name | |
| Test status | |
| Simulation time | 108937781 ps |
| CPU time | 1.53 seconds |
| Started | Jun 04 12:49:49 PM PDT 24 |
| Finished | Jun 04 12:49:52 PM PDT 24 |
| Peak memory | 200336 kb |
| Host | smart-686db130-baf4-4c13-9e86-0da8c61a6fb8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618210844 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.1618210844 |
| Directory | /workspace/6.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/6.uart_csr_rw.399734455 |
| Short name | T1265 |
| Test name | |
| Test status | |
| Simulation time | 16485662 ps |
| CPU time | 0.59 seconds |
| Started | Jun 04 12:49:48 PM PDT 24 |
| Finished | Jun 04 12:49:49 PM PDT 24 |
| Peak memory | 195544 kb |
| Host | smart-b7888f73-a494-4d39-8f5c-2d18551e5ad0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399734455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.399734455 |
| Directory | /workspace/6.uart_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/6.uart_intr_test.3185787499 |
| Short name | T1237 |
| Test name | |
| Test status | |
| Simulation time | 17285391 ps |
| CPU time | 0.57 seconds |
| Started | Jun 04 12:49:48 PM PDT 24 |
| Finished | Jun 04 12:49:49 PM PDT 24 |
| Peak memory | 194664 kb |
| Host | smart-c19359df-1018-4cc3-96bc-36eecd17ff93 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185787499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.3185787499 |
| Directory | /workspace/6.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.2794620685 |
| Short name | T1241 |
| Test name | |
| Test status | |
| Simulation time | 51618437 ps |
| CPU time | 0.74 seconds |
| Started | Jun 04 12:49:51 PM PDT 24 |
| Finished | Jun 04 12:49:52 PM PDT 24 |
| Peak memory | 197320 kb |
| Host | smart-0fd9a374-387a-4657-96a7-e68ec4a2a1ca |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794620685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr _outstanding.2794620685 |
| Directory | /workspace/6.uart_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/6.uart_tl_errors.1063289145 |
| Short name | T1189 |
| Test name | |
| Test status | |
| Simulation time | 64367328 ps |
| CPU time | 1.56 seconds |
| Started | Jun 04 12:49:44 PM PDT 24 |
| Finished | Jun 04 12:49:46 PM PDT 24 |
| Peak memory | 200296 kb |
| Host | smart-d4d52004-c240-4078-91e0-93200a2033c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063289145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.1063289145 |
| Directory | /workspace/6.uart_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.958666920 |
| Short name | T1307 |
| Test name | |
| Test status | |
| Simulation time | 342862544 ps |
| CPU time | 1.3 seconds |
| Started | Jun 04 12:49:52 PM PDT 24 |
| Finished | Jun 04 12:49:54 PM PDT 24 |
| Peak memory | 199544 kb |
| Host | smart-edd9eb66-46e9-4ce9-a196-01a85a3ceb4e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958666920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.958666920 |
| Directory | /workspace/6.uart_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.501104849 |
| Short name | T1221 |
| Test name | |
| Test status | |
| Simulation time | 14241011 ps |
| CPU time | 0.63 seconds |
| Started | Jun 04 12:49:47 PM PDT 24 |
| Finished | Jun 04 12:49:49 PM PDT 24 |
| Peak memory | 197936 kb |
| Host | smart-a5455d44-e944-4d0a-86ae-d84a9a62680f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501104849 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.501104849 |
| Directory | /workspace/7.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/7.uart_csr_rw.1030575493 |
| Short name | T1228 |
| Test name | |
| Test status | |
| Simulation time | 20671344 ps |
| CPU time | 0.55 seconds |
| Started | Jun 04 12:49:49 PM PDT 24 |
| Finished | Jun 04 12:49:51 PM PDT 24 |
| Peak memory | 195560 kb |
| Host | smart-60cbcfb1-7037-4f50-81d5-123a36e174a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030575493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.1030575493 |
| Directory | /workspace/7.uart_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/7.uart_intr_test.2889350036 |
| Short name | T1303 |
| Test name | |
| Test status | |
| Simulation time | 27771130 ps |
| CPU time | 0.56 seconds |
| Started | Jun 04 12:49:47 PM PDT 24 |
| Finished | Jun 04 12:49:49 PM PDT 24 |
| Peak memory | 194508 kb |
| Host | smart-fa97674c-a9b6-4ca1-be17-c2357290dc01 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889350036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.2889350036 |
| Directory | /workspace/7.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.3972700603 |
| Short name | T1247 |
| Test name | |
| Test status | |
| Simulation time | 30845101 ps |
| CPU time | 0.72 seconds |
| Started | Jun 04 12:49:46 PM PDT 24 |
| Finished | Jun 04 12:49:48 PM PDT 24 |
| Peak memory | 197060 kb |
| Host | smart-36bd7779-6ab1-4260-b2da-84217fa725ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972700603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr _outstanding.3972700603 |
| Directory | /workspace/7.uart_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/7.uart_tl_errors.1351290612 |
| Short name | T1287 |
| Test name | |
| Test status | |
| Simulation time | 30444034 ps |
| CPU time | 1.57 seconds |
| Started | Jun 04 12:49:46 PM PDT 24 |
| Finished | Jun 04 12:49:48 PM PDT 24 |
| Peak memory | 200328 kb |
| Host | smart-c48374eb-f3e2-41f1-949d-132b06b40f58 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351290612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.1351290612 |
| Directory | /workspace/7.uart_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.3913355553 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 170044697 ps |
| CPU time | 1.33 seconds |
| Started | Jun 04 12:49:50 PM PDT 24 |
| Finished | Jun 04 12:49:53 PM PDT 24 |
| Peak memory | 199388 kb |
| Host | smart-3e20639a-bbe9-46e4-9c64-5c780946d210 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913355553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.3913355553 |
| Directory | /workspace/7.uart_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.680643363 |
| Short name | T1255 |
| Test name | |
| Test status | |
| Simulation time | 34051209 ps |
| CPU time | 0.74 seconds |
| Started | Jun 04 12:49:45 PM PDT 24 |
| Finished | Jun 04 12:49:46 PM PDT 24 |
| Peak memory | 199288 kb |
| Host | smart-3ef750f6-149b-4588-8994-6773b72ba62a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680643363 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.680643363 |
| Directory | /workspace/8.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/8.uart_csr_rw.2468646447 |
| Short name | T1190 |
| Test name | |
| Test status | |
| Simulation time | 12929622 ps |
| CPU time | 0.58 seconds |
| Started | Jun 04 12:49:50 PM PDT 24 |
| Finished | Jun 04 12:49:52 PM PDT 24 |
| Peak memory | 195548 kb |
| Host | smart-65356834-6dee-4542-94cb-3874401656b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468646447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.2468646447 |
| Directory | /workspace/8.uart_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/8.uart_intr_test.982710988 |
| Short name | T1308 |
| Test name | |
| Test status | |
| Simulation time | 34674457 ps |
| CPU time | 0.57 seconds |
| Started | Jun 04 12:49:48 PM PDT 24 |
| Finished | Jun 04 12:49:50 PM PDT 24 |
| Peak memory | 194580 kb |
| Host | smart-770973d9-ec77-4353-84f4-c95421095816 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982710988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.982710988 |
| Directory | /workspace/8.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.3804131883 |
| Short name | T1230 |
| Test name | |
| Test status | |
| Simulation time | 19123866 ps |
| CPU time | 0.76 seconds |
| Started | Jun 04 12:49:51 PM PDT 24 |
| Finished | Jun 04 12:49:53 PM PDT 24 |
| Peak memory | 196380 kb |
| Host | smart-dc343d57-481c-4938-b91b-21d0de95d13d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804131883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr _outstanding.3804131883 |
| Directory | /workspace/8.uart_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/8.uart_tl_errors.3266440463 |
| Short name | T1234 |
| Test name | |
| Test status | |
| Simulation time | 113805799 ps |
| CPU time | 2.29 seconds |
| Started | Jun 04 12:49:46 PM PDT 24 |
| Finished | Jun 04 12:49:49 PM PDT 24 |
| Peak memory | 200304 kb |
| Host | smart-3a9e6181-847b-4175-8ca3-fc73bc8fc103 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266440463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.3266440463 |
| Directory | /workspace/8.uart_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.2124096408 |
| Short name | T1203 |
| Test name | |
| Test status | |
| Simulation time | 22938951 ps |
| CPU time | 1.1 seconds |
| Started | Jun 04 12:49:48 PM PDT 24 |
| Finished | Jun 04 12:49:51 PM PDT 24 |
| Peak memory | 200228 kb |
| Host | smart-1e00fb7c-f2d7-4c23-b839-aa9284d0393b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124096408 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.2124096408 |
| Directory | /workspace/9.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/9.uart_csr_rw.3107074025 |
| Short name | T1290 |
| Test name | |
| Test status | |
| Simulation time | 16421864 ps |
| CPU time | 0.59 seconds |
| Started | Jun 04 12:49:49 PM PDT 24 |
| Finished | Jun 04 12:49:50 PM PDT 24 |
| Peak memory | 195652 kb |
| Host | smart-24a3214e-6f0b-4b32-b191-8094b0b49b03 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107074025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.3107074025 |
| Directory | /workspace/9.uart_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/9.uart_intr_test.1508427398 |
| Short name | T1208 |
| Test name | |
| Test status | |
| Simulation time | 43383606 ps |
| CPU time | 0.62 seconds |
| Started | Jun 04 12:49:47 PM PDT 24 |
| Finished | Jun 04 12:49:49 PM PDT 24 |
| Peak memory | 194688 kb |
| Host | smart-b099ccfa-b899-411f-8dae-ca348d35840f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508427398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.1508427398 |
| Directory | /workspace/9.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.1987903583 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 20276890 ps |
| CPU time | 0.64 seconds |
| Started | Jun 04 12:49:48 PM PDT 24 |
| Finished | Jun 04 12:49:50 PM PDT 24 |
| Peak memory | 196808 kb |
| Host | smart-ae0bbcac-3aa7-4e9a-ab66-673b4b6c9f28 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987903583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr _outstanding.1987903583 |
| Directory | /workspace/9.uart_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/9.uart_tl_errors.913017561 |
| Short name | T1195 |
| Test name | |
| Test status | |
| Simulation time | 67361404 ps |
| CPU time | 1.52 seconds |
| Started | Jun 04 12:49:48 PM PDT 24 |
| Finished | Jun 04 12:49:51 PM PDT 24 |
| Peak memory | 200296 kb |
| Host | smart-6e4c17a9-990f-4c16-8df2-0ee2b4941796 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913017561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.913017561 |
| Directory | /workspace/9.uart_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.2445567306 |
| Short name | T1293 |
| Test name | |
| Test status | |
| Simulation time | 174945379 ps |
| CPU time | 1.26 seconds |
| Started | Jun 04 12:49:50 PM PDT 24 |
| Finished | Jun 04 12:49:52 PM PDT 24 |
| Peak memory | 199408 kb |
| Host | smart-76670896-c23d-4262-b40a-a399e6a1ec1a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445567306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.2445567306 |
| Directory | /workspace/9.uart_tl_intg_err/latest |
| Test location | /workspace/coverage/default/0.uart_alert_test.2042028020 |
| Short name | T1046 |
| Test name | |
| Test status | |
| Simulation time | 20642279 ps |
| CPU time | 0.53 seconds |
| Started | Jun 04 12:36:43 PM PDT 24 |
| Finished | Jun 04 12:36:44 PM PDT 24 |
| Peak memory | 194996 kb |
| Host | smart-f9b575f7-cc03-4fd5-bee9-7546a4339138 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042028020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.2042028020 |
| Directory | /workspace/0.uart_alert_test/latest |
| Test location | /workspace/coverage/default/0.uart_fifo_full.2736725733 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 428420124276 ps |
| CPU time | 98.1 seconds |
| Started | Jun 04 12:36:30 PM PDT 24 |
| Finished | Jun 04 12:38:09 PM PDT 24 |
| Peak memory | 200336 kb |
| Host | smart-2deef2fd-7a8e-4ebd-8d9f-6530ac9336de |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2736725733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.2736725733 |
| Directory | /workspace/0.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/0.uart_fifo_overflow.3028495468 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 104288984501 ps |
| CPU time | 73.93 seconds |
| Started | Jun 04 12:36:30 PM PDT 24 |
| Finished | Jun 04 12:37:45 PM PDT 24 |
| Peak memory | 200140 kb |
| Host | smart-5b05c79a-2a5f-4017-a48c-30f0a29d68c8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3028495468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.3028495468 |
| Directory | /workspace/0.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/0.uart_intr.3991448423 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 7805072040 ps |
| CPU time | 4.13 seconds |
| Started | Jun 04 12:36:31 PM PDT 24 |
| Finished | Jun 04 12:36:36 PM PDT 24 |
| Peak memory | 200116 kb |
| Host | smart-05cb772d-bf68-4711-abc8-97ce7f4e42d9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991448423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.3991448423 |
| Directory | /workspace/0.uart_intr/latest |
| Test location | /workspace/coverage/default/0.uart_long_xfer_wo_dly.1876084755 |
| Short name | T1008 |
| Test name | |
| Test status | |
| Simulation time | 64871165662 ps |
| CPU time | 248.86 seconds |
| Started | Jun 04 12:36:39 PM PDT 24 |
| Finished | Jun 04 12:40:49 PM PDT 24 |
| Peak memory | 200088 kb |
| Host | smart-08992bc1-a118-412a-8b45-098848929221 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1876084755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.1876084755 |
| Directory | /workspace/0.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/0.uart_loopback.1143776322 |
| Short name | T970 |
| Test name | |
| Test status | |
| Simulation time | 1790341367 ps |
| CPU time | 2.36 seconds |
| Started | Jun 04 12:36:41 PM PDT 24 |
| Finished | Jun 04 12:36:45 PM PDT 24 |
| Peak memory | 197344 kb |
| Host | smart-5d4a767d-6177-41a3-ae1b-0f805cb32cb5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1143776322 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_loopback.1143776322 |
| Directory | /workspace/0.uart_loopback/latest |
| Test location | /workspace/coverage/default/0.uart_noise_filter.2527076588 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 61832497369 ps |
| CPU time | 16.73 seconds |
| Started | Jun 04 12:36:38 PM PDT 24 |
| Finished | Jun 04 12:36:56 PM PDT 24 |
| Peak memory | 196016 kb |
| Host | smart-62cc454b-1d3c-4037-b0f0-df0ec039f5b6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2527076588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_noise_filter.2527076588 |
| Directory | /workspace/0.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/0.uart_perf.1794976468 |
| Short name | T1039 |
| Test name | |
| Test status | |
| Simulation time | 13918992045 ps |
| CPU time | 200.79 seconds |
| Started | Jun 04 12:36:43 PM PDT 24 |
| Finished | Jun 04 12:40:05 PM PDT 24 |
| Peak memory | 200176 kb |
| Host | smart-3cd25b42-fcda-4629-9849-1f77d1cf25ec |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1794976468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.1794976468 |
| Directory | /workspace/0.uart_perf/latest |
| Test location | /workspace/coverage/default/0.uart_rx_oversample.1412579585 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 5546847548 ps |
| CPU time | 12.51 seconds |
| Started | Jun 04 12:36:33 PM PDT 24 |
| Finished | Jun 04 12:36:46 PM PDT 24 |
| Peak memory | 198360 kb |
| Host | smart-5f495277-9117-41a5-bf4a-01e434d5840d |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1412579585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.1412579585 |
| Directory | /workspace/0.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/0.uart_rx_parity_err.3239067286 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 73026010264 ps |
| CPU time | 32.71 seconds |
| Started | Jun 04 12:36:41 PM PDT 24 |
| Finished | Jun 04 12:37:15 PM PDT 24 |
| Peak memory | 199316 kb |
| Host | smart-7dcddae8-1bdc-49e2-8e05-04e32231c2f2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3239067286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.3239067286 |
| Directory | /workspace/0.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/0.uart_rx_start_bit_filter.1490563378 |
| Short name | T1069 |
| Test name | |
| Test status | |
| Simulation time | 75689285103 ps |
| CPU time | 70.69 seconds |
| Started | Jun 04 12:36:39 PM PDT 24 |
| Finished | Jun 04 12:37:51 PM PDT 24 |
| Peak memory | 195916 kb |
| Host | smart-dc976476-8389-4028-b4d1-ec6982f26142 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1490563378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.1490563378 |
| Directory | /workspace/0.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/0.uart_sec_cm.2271154318 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 123233095 ps |
| CPU time | 0.9 seconds |
| Started | Jun 04 12:36:41 PM PDT 24 |
| Finished | Jun 04 12:36:43 PM PDT 24 |
| Peak memory | 218416 kb |
| Host | smart-9c5b772c-e618-44f3-8fd0-a3c251472ba3 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271154318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.2271154318 |
| Directory | /workspace/0.uart_sec_cm/latest |
| Test location | /workspace/coverage/default/0.uart_smoke.1963820572 |
| Short name | T1073 |
| Test name | |
| Test status | |
| Simulation time | 5787338195 ps |
| CPU time | 4.92 seconds |
| Started | Jun 04 12:36:30 PM PDT 24 |
| Finished | Jun 04 12:36:36 PM PDT 24 |
| Peak memory | 199924 kb |
| Host | smart-d820a55a-1c13-4f51-8c20-6220aa9fc90e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1963820572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_smoke.1963820572 |
| Directory | /workspace/0.uart_smoke/latest |
| Test location | /workspace/coverage/default/0.uart_stress_all.3371006398 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 204794247302 ps |
| CPU time | 87.57 seconds |
| Started | Jun 04 12:36:41 PM PDT 24 |
| Finished | Jun 04 12:38:09 PM PDT 24 |
| Peak memory | 200280 kb |
| Host | smart-e9f48f0c-4968-4167-be1e-989004010d3d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371006398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.3371006398 |
| Directory | /workspace/0.uart_stress_all/latest |
| Test location | /workspace/coverage/default/0.uart_stress_all_with_rand_reset.3662007033 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 23974025658 ps |
| CPU time | 285.72 seconds |
| Started | Jun 04 12:36:40 PM PDT 24 |
| Finished | Jun 04 12:41:27 PM PDT 24 |
| Peak memory | 216652 kb |
| Host | smart-23ef3c2d-3c3c-4e4b-8222-b753f7a6f8bc |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662007033 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 0.uart_stress_all_with_rand_reset.3662007033 |
| Directory | /workspace/0.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/0.uart_tx_ovrd.665509819 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 2557802886 ps |
| CPU time | 2.73 seconds |
| Started | Jun 04 12:36:40 PM PDT 24 |
| Finished | Jun 04 12:36:44 PM PDT 24 |
| Peak memory | 199064 kb |
| Host | smart-0b3e2790-d2b4-48c9-a032-754f5d73ee9c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=665509819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.665509819 |
| Directory | /workspace/0.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/0.uart_tx_rx.2284012206 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 11666967531 ps |
| CPU time | 10.11 seconds |
| Started | Jun 04 12:36:28 PM PDT 24 |
| Finished | Jun 04 12:36:39 PM PDT 24 |
| Peak memory | 197996 kb |
| Host | smart-36f3c35e-1c35-4286-9833-fadaf5c9e142 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2284012206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.2284012206 |
| Directory | /workspace/0.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/1.uart_alert_test.29345576 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 49232459 ps |
| CPU time | 0.55 seconds |
| Started | Jun 04 12:36:40 PM PDT 24 |
| Finished | Jun 04 12:36:42 PM PDT 24 |
| Peak memory | 195580 kb |
| Host | smart-ad9f34f4-12e6-41d9-acaf-8b14fb1ccf25 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29345576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.29345576 |
| Directory | /workspace/1.uart_alert_test/latest |
| Test location | /workspace/coverage/default/1.uart_fifo_full.2800612046 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 147974554278 ps |
| CPU time | 243.91 seconds |
| Started | Jun 04 12:36:40 PM PDT 24 |
| Finished | Jun 04 12:40:46 PM PDT 24 |
| Peak memory | 200220 kb |
| Host | smart-ecddb007-7fbe-4c84-9773-fccd7b6330ba |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2800612046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.2800612046 |
| Directory | /workspace/1.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/1.uart_fifo_overflow.3068276098 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 52501831121 ps |
| CPU time | 27.99 seconds |
| Started | Jun 04 12:36:40 PM PDT 24 |
| Finished | Jun 04 12:37:09 PM PDT 24 |
| Peak memory | 200200 kb |
| Host | smart-5f979985-e81d-482c-87ba-e25d6d6891fc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3068276098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.3068276098 |
| Directory | /workspace/1.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/1.uart_fifo_reset.1281746390 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 152362746837 ps |
| CPU time | 20.9 seconds |
| Started | Jun 04 12:36:38 PM PDT 24 |
| Finished | Jun 04 12:36:59 PM PDT 24 |
| Peak memory | 200144 kb |
| Host | smart-4deba8dd-ec04-4bfe-a006-7f579abef691 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1281746390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.1281746390 |
| Directory | /workspace/1.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/1.uart_intr.1026713666 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 15962047599 ps |
| CPU time | 16.94 seconds |
| Started | Jun 04 12:36:42 PM PDT 24 |
| Finished | Jun 04 12:37:00 PM PDT 24 |
| Peak memory | 197948 kb |
| Host | smart-c0587a9a-01bc-4295-a7f9-3adc466eab40 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026713666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.1026713666 |
| Directory | /workspace/1.uart_intr/latest |
| Test location | /workspace/coverage/default/1.uart_long_xfer_wo_dly.4270448285 |
| Short name | T990 |
| Test name | |
| Test status | |
| Simulation time | 90281130880 ps |
| CPU time | 859.06 seconds |
| Started | Jun 04 12:36:41 PM PDT 24 |
| Finished | Jun 04 12:51:01 PM PDT 24 |
| Peak memory | 200164 kb |
| Host | smart-b319b1a8-0e32-4711-bb51-15d4c9f6d31f |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4270448285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.4270448285 |
| Directory | /workspace/1.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/1.uart_loopback.35629101 |
| Short name | T1105 |
| Test name | |
| Test status | |
| Simulation time | 10508396145 ps |
| CPU time | 12.05 seconds |
| Started | Jun 04 12:36:38 PM PDT 24 |
| Finished | Jun 04 12:36:51 PM PDT 24 |
| Peak memory | 200148 kb |
| Host | smart-6c4b7e32-5757-4554-b5e0-4b8b71a81118 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=35629101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_loopback.35629101 |
| Directory | /workspace/1.uart_loopback/latest |
| Test location | /workspace/coverage/default/1.uart_noise_filter.4285929449 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 114192906199 ps |
| CPU time | 311.45 seconds |
| Started | Jun 04 12:36:39 PM PDT 24 |
| Finished | Jun 04 12:41:52 PM PDT 24 |
| Peak memory | 200332 kb |
| Host | smart-861cfaad-2fed-4de4-81fe-12ae11f8d0b5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4285929449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_noise_filter.4285929449 |
| Directory | /workspace/1.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/1.uart_perf.2413098066 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 9926242615 ps |
| CPU time | 577.2 seconds |
| Started | Jun 04 12:36:42 PM PDT 24 |
| Finished | Jun 04 12:46:20 PM PDT 24 |
| Peak memory | 200200 kb |
| Host | smart-0cf2ca15-8bc7-45e8-96eb-4cea41ada69b |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2413098066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.2413098066 |
| Directory | /workspace/1.uart_perf/latest |
| Test location | /workspace/coverage/default/1.uart_rx_oversample.1248767060 |
| Short name | T987 |
| Test name | |
| Test status | |
| Simulation time | 3817257809 ps |
| CPU time | 7.02 seconds |
| Started | Jun 04 12:36:39 PM PDT 24 |
| Finished | Jun 04 12:36:48 PM PDT 24 |
| Peak memory | 198764 kb |
| Host | smart-24daca79-16f8-4838-a7dd-5e11c5926a26 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1248767060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.1248767060 |
| Directory | /workspace/1.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/1.uart_rx_parity_err.173986140 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 85795101998 ps |
| CPU time | 190.59 seconds |
| Started | Jun 04 12:36:38 PM PDT 24 |
| Finished | Jun 04 12:39:50 PM PDT 24 |
| Peak memory | 200220 kb |
| Host | smart-db17afa3-ff35-441f-8fda-82e0c3a8429b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=173986140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.173986140 |
| Directory | /workspace/1.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/1.uart_rx_start_bit_filter.3489701859 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 2354721603 ps |
| CPU time | 2.36 seconds |
| Started | Jun 04 12:36:40 PM PDT 24 |
| Finished | Jun 04 12:36:43 PM PDT 24 |
| Peak memory | 195904 kb |
| Host | smart-bdc7df8b-b2b2-4415-89a0-7595bedb3316 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3489701859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.3489701859 |
| Directory | /workspace/1.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/1.uart_sec_cm.4136674689 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 44390263 ps |
| CPU time | 0.77 seconds |
| Started | Jun 04 12:36:40 PM PDT 24 |
| Finished | Jun 04 12:36:42 PM PDT 24 |
| Peak memory | 218440 kb |
| Host | smart-afbee9d0-d093-4008-ab73-83c340da9aff |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136674689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.4136674689 |
| Directory | /workspace/1.uart_sec_cm/latest |
| Test location | /workspace/coverage/default/1.uart_smoke.3562855429 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 652119961 ps |
| CPU time | 1.88 seconds |
| Started | Jun 04 12:36:42 PM PDT 24 |
| Finished | Jun 04 12:36:45 PM PDT 24 |
| Peak memory | 200056 kb |
| Host | smart-b156ed71-acab-4b39-9776-ab86faf2ec49 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3562855429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_smoke.3562855429 |
| Directory | /workspace/1.uart_smoke/latest |
| Test location | /workspace/coverage/default/1.uart_stress_all.2492305018 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 81312561621 ps |
| CPU time | 221.46 seconds |
| Started | Jun 04 12:36:47 PM PDT 24 |
| Finished | Jun 04 12:40:29 PM PDT 24 |
| Peak memory | 200276 kb |
| Host | smart-106bd9a5-5dc3-471f-9ae5-f165cdae32c2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492305018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.2492305018 |
| Directory | /workspace/1.uart_stress_all/latest |
| Test location | /workspace/coverage/default/1.uart_tx_ovrd.3231148190 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 1531283996 ps |
| CPU time | 2.91 seconds |
| Started | Jun 04 12:36:39 PM PDT 24 |
| Finished | Jun 04 12:36:43 PM PDT 24 |
| Peak memory | 198676 kb |
| Host | smart-50a7c207-17b7-48e7-8ce1-83600b0752c2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3231148190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.3231148190 |
| Directory | /workspace/1.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/1.uart_tx_rx.3941625227 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 16772290795 ps |
| CPU time | 7.54 seconds |
| Started | Jun 04 12:36:40 PM PDT 24 |
| Finished | Jun 04 12:36:48 PM PDT 24 |
| Peak memory | 198960 kb |
| Host | smart-2b2c690c-d8f4-4045-b27d-66fc9e96977e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3941625227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.3941625227 |
| Directory | /workspace/1.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/10.uart_alert_test.3106208125 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 22540505 ps |
| CPU time | 0.59 seconds |
| Started | Jun 04 12:37:34 PM PDT 24 |
| Finished | Jun 04 12:37:36 PM PDT 24 |
| Peak memory | 194948 kb |
| Host | smart-46875fc4-b7ba-4d24-8c0a-a5ba6ab546d5 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106208125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.3106208125 |
| Directory | /workspace/10.uart_alert_test/latest |
| Test location | /workspace/coverage/default/10.uart_fifo_full.1413626326 |
| Short name | T1098 |
| Test name | |
| Test status | |
| Simulation time | 121119655898 ps |
| CPU time | 326.03 seconds |
| Started | Jun 04 12:37:26 PM PDT 24 |
| Finished | Jun 04 12:42:53 PM PDT 24 |
| Peak memory | 200192 kb |
| Host | smart-4ce4be14-1d9f-4867-9931-eb0dde01a391 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1413626326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.1413626326 |
| Directory | /workspace/10.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/10.uart_fifo_overflow.1218802672 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 149254683536 ps |
| CPU time | 47.42 seconds |
| Started | Jun 04 12:37:25 PM PDT 24 |
| Finished | Jun 04 12:38:14 PM PDT 24 |
| Peak memory | 200300 kb |
| Host | smart-230a282f-b970-44bc-83c9-3a203c6f509f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1218802672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.1218802672 |
| Directory | /workspace/10.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/10.uart_fifo_reset.200649153 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 21920831348 ps |
| CPU time | 46.9 seconds |
| Started | Jun 04 12:37:24 PM PDT 24 |
| Finished | Jun 04 12:38:12 PM PDT 24 |
| Peak memory | 200228 kb |
| Host | smart-4683a2b8-23df-47f6-b953-74224d62227b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=200649153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.200649153 |
| Directory | /workspace/10.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/10.uart_intr.3520486909 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 10240670743 ps |
| CPU time | 17.69 seconds |
| Started | Jun 04 12:37:25 PM PDT 24 |
| Finished | Jun 04 12:37:43 PM PDT 24 |
| Peak memory | 196768 kb |
| Host | smart-40e2dd27-be61-48cb-b6bf-cb974bc38263 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520486909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.3520486909 |
| Directory | /workspace/10.uart_intr/latest |
| Test location | /workspace/coverage/default/10.uart_long_xfer_wo_dly.912756781 |
| Short name | T1150 |
| Test name | |
| Test status | |
| Simulation time | 123678439231 ps |
| CPU time | 205.68 seconds |
| Started | Jun 04 12:37:25 PM PDT 24 |
| Finished | Jun 04 12:40:52 PM PDT 24 |
| Peak memory | 200216 kb |
| Host | smart-2b54ee5c-c2c6-4496-a4e1-912c5b189f42 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=912756781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.912756781 |
| Directory | /workspace/10.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/10.uart_loopback.3929997389 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 7759731155 ps |
| CPU time | 4.24 seconds |
| Started | Jun 04 12:37:25 PM PDT 24 |
| Finished | Jun 04 12:37:31 PM PDT 24 |
| Peak memory | 200172 kb |
| Host | smart-ccd1fc65-0fab-4d34-b756-81e133e76fae |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3929997389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_loopback.3929997389 |
| Directory | /workspace/10.uart_loopback/latest |
| Test location | /workspace/coverage/default/10.uart_noise_filter.441145067 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 54563288071 ps |
| CPU time | 86.8 seconds |
| Started | Jun 04 12:37:24 PM PDT 24 |
| Finished | Jun 04 12:38:52 PM PDT 24 |
| Peak memory | 200076 kb |
| Host | smart-0b8265dc-1a18-4144-bbd7-603c1e1081c9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=441145067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_noise_filter.441145067 |
| Directory | /workspace/10.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/10.uart_perf.2455709470 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 10724927215 ps |
| CPU time | 126.53 seconds |
| Started | Jun 04 12:37:25 PM PDT 24 |
| Finished | Jun 04 12:39:33 PM PDT 24 |
| Peak memory | 200136 kb |
| Host | smart-b4ad9bfe-ac1c-47a5-bca0-fe784a2d063f |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2455709470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.2455709470 |
| Directory | /workspace/10.uart_perf/latest |
| Test location | /workspace/coverage/default/10.uart_rx_oversample.533423447 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 1375650586 ps |
| CPU time | 5.65 seconds |
| Started | Jun 04 12:37:25 PM PDT 24 |
| Finished | Jun 04 12:37:31 PM PDT 24 |
| Peak memory | 198124 kb |
| Host | smart-b07311cd-d833-4fec-9e44-ade0e27abc73 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=533423447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.533423447 |
| Directory | /workspace/10.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/10.uart_rx_parity_err.3005634411 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 124259405426 ps |
| CPU time | 58.88 seconds |
| Started | Jun 04 12:37:25 PM PDT 24 |
| Finished | Jun 04 12:38:26 PM PDT 24 |
| Peak memory | 200116 kb |
| Host | smart-fd0f88c1-721c-4327-abb4-dbb05bb646c2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3005634411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.3005634411 |
| Directory | /workspace/10.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/10.uart_rx_start_bit_filter.2338577633 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 32257224445 ps |
| CPU time | 13.93 seconds |
| Started | Jun 04 12:37:24 PM PDT 24 |
| Finished | Jun 04 12:37:38 PM PDT 24 |
| Peak memory | 196200 kb |
| Host | smart-2b16b6dc-45d1-4f32-a2eb-7b32fca4527e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2338577633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.2338577633 |
| Directory | /workspace/10.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/10.uart_smoke.4243305426 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 933500759 ps |
| CPU time | 2.55 seconds |
| Started | Jun 04 12:37:26 PM PDT 24 |
| Finished | Jun 04 12:37:31 PM PDT 24 |
| Peak memory | 199956 kb |
| Host | smart-b0a80733-b5fd-4fb9-a44f-6720e83d0d57 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4243305426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_smoke.4243305426 |
| Directory | /workspace/10.uart_smoke/latest |
| Test location | /workspace/coverage/default/10.uart_stress_all.2680190839 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 225110461799 ps |
| CPU time | 677.59 seconds |
| Started | Jun 04 12:37:32 PM PDT 24 |
| Finished | Jun 04 12:48:50 PM PDT 24 |
| Peak memory | 200240 kb |
| Host | smart-40f0cb23-2c23-4a53-b225-db4481665a1d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680190839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.2680190839 |
| Directory | /workspace/10.uart_stress_all/latest |
| Test location | /workspace/coverage/default/10.uart_stress_all_with_rand_reset.2412807481 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 131758697654 ps |
| CPU time | 391.35 seconds |
| Started | Jun 04 12:37:26 PM PDT 24 |
| Finished | Jun 04 12:43:58 PM PDT 24 |
| Peak memory | 216340 kb |
| Host | smart-1f6576df-94f5-4698-a26e-9423c2c26a39 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412807481 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 10.uart_stress_all_with_rand_reset.2412807481 |
| Directory | /workspace/10.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/10.uart_tx_ovrd.548515198 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 1045119595 ps |
| CPU time | 2.91 seconds |
| Started | Jun 04 12:37:27 PM PDT 24 |
| Finished | Jun 04 12:37:31 PM PDT 24 |
| Peak memory | 199704 kb |
| Host | smart-7a75f45b-6ef2-4fb5-8044-1c18c947aaa4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=548515198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.548515198 |
| Directory | /workspace/10.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/10.uart_tx_rx.1916783391 |
| Short name | T1102 |
| Test name | |
| Test status | |
| Simulation time | 29108932790 ps |
| CPU time | 14.93 seconds |
| Started | Jun 04 12:37:24 PM PDT 24 |
| Finished | Jun 04 12:37:40 PM PDT 24 |
| Peak memory | 200188 kb |
| Host | smart-2ea1053f-ac16-4fac-b865-1ac97cc2bfe0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1916783391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.1916783391 |
| Directory | /workspace/10.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/101.uart_fifo_reset.117754406 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 72236496342 ps |
| CPU time | 30.86 seconds |
| Started | Jun 04 12:41:25 PM PDT 24 |
| Finished | Jun 04 12:41:57 PM PDT 24 |
| Peak memory | 200208 kb |
| Host | smart-fd71d428-54ef-467f-845f-aeaaec915f21 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=117754406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.117754406 |
| Directory | /workspace/101.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/102.uart_fifo_reset.3031737051 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 86870882648 ps |
| CPU time | 167.44 seconds |
| Started | Jun 04 12:41:26 PM PDT 24 |
| Finished | Jun 04 12:44:14 PM PDT 24 |
| Peak memory | 200228 kb |
| Host | smart-c508edf3-00b5-43f9-8239-b8a84f4cb2e4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3031737051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.3031737051 |
| Directory | /workspace/102.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/103.uart_fifo_reset.1460976810 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 33855423858 ps |
| CPU time | 55.13 seconds |
| Started | Jun 04 12:41:26 PM PDT 24 |
| Finished | Jun 04 12:42:22 PM PDT 24 |
| Peak memory | 200132 kb |
| Host | smart-7dc040f2-b132-44b5-8349-524a82ad0e51 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1460976810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.1460976810 |
| Directory | /workspace/103.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/104.uart_fifo_reset.157282668 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 14389632300 ps |
| CPU time | 25.15 seconds |
| Started | Jun 04 12:41:37 PM PDT 24 |
| Finished | Jun 04 12:42:02 PM PDT 24 |
| Peak memory | 199988 kb |
| Host | smart-c81bd617-21d6-46c6-b1b3-4aed2e485d28 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=157282668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.157282668 |
| Directory | /workspace/104.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/105.uart_fifo_reset.852428476 |
| Short name | T939 |
| Test name | |
| Test status | |
| Simulation time | 10312078023 ps |
| CPU time | 5.22 seconds |
| Started | Jun 04 12:41:36 PM PDT 24 |
| Finished | Jun 04 12:41:42 PM PDT 24 |
| Peak memory | 199960 kb |
| Host | smart-5c83b3c0-1270-4ecd-9687-22194106f4ff |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=852428476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.852428476 |
| Directory | /workspace/105.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/107.uart_fifo_reset.1315512777 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 117817359024 ps |
| CPU time | 52.76 seconds |
| Started | Jun 04 12:41:35 PM PDT 24 |
| Finished | Jun 04 12:42:29 PM PDT 24 |
| Peak memory | 200332 kb |
| Host | smart-ed7c7f15-d673-4c10-adac-f2bfe7aefad8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1315512777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.1315512777 |
| Directory | /workspace/107.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/108.uart_fifo_reset.4280514568 |
| Short name | T961 |
| Test name | |
| Test status | |
| Simulation time | 40656837163 ps |
| CPU time | 67.18 seconds |
| Started | Jun 04 12:41:35 PM PDT 24 |
| Finished | Jun 04 12:42:43 PM PDT 24 |
| Peak memory | 200252 kb |
| Host | smart-b9d79f78-8516-41fe-bc85-94f141074db5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4280514568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.4280514568 |
| Directory | /workspace/108.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/11.uart_fifo_full.3732864314 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 114250615064 ps |
| CPU time | 58.4 seconds |
| Started | Jun 04 12:37:35 PM PDT 24 |
| Finished | Jun 04 12:38:35 PM PDT 24 |
| Peak memory | 200360 kb |
| Host | smart-f80f92cd-5351-49fc-84be-d3e9f7b6cf17 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3732864314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.3732864314 |
| Directory | /workspace/11.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/11.uart_fifo_overflow.3210219621 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 37180700020 ps |
| CPU time | 61.44 seconds |
| Started | Jun 04 12:37:34 PM PDT 24 |
| Finished | Jun 04 12:38:37 PM PDT 24 |
| Peak memory | 200196 kb |
| Host | smart-b7d68238-157b-4c21-81ed-d7e267fd901d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3210219621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.3210219621 |
| Directory | /workspace/11.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/11.uart_fifo_reset.3893189022 |
| Short name | T1053 |
| Test name | |
| Test status | |
| Simulation time | 64189721742 ps |
| CPU time | 115.24 seconds |
| Started | Jun 04 12:37:36 PM PDT 24 |
| Finished | Jun 04 12:39:32 PM PDT 24 |
| Peak memory | 200216 kb |
| Host | smart-4aca697d-85e8-4f10-b602-660081015580 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3893189022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.3893189022 |
| Directory | /workspace/11.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/11.uart_intr.2105854122 |
| Short name | T1061 |
| Test name | |
| Test status | |
| Simulation time | 185858661200 ps |
| CPU time | 343.75 seconds |
| Started | Jun 04 12:37:33 PM PDT 24 |
| Finished | Jun 04 12:43:19 PM PDT 24 |
| Peak memory | 200060 kb |
| Host | smart-64dc2270-a772-42b0-aec8-5325e6a2d23e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105854122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.2105854122 |
| Directory | /workspace/11.uart_intr/latest |
| Test location | /workspace/coverage/default/11.uart_long_xfer_wo_dly.2319743289 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 117147393099 ps |
| CPU time | 735.48 seconds |
| Started | Jun 04 12:37:33 PM PDT 24 |
| Finished | Jun 04 12:49:50 PM PDT 24 |
| Peak memory | 200252 kb |
| Host | smart-58012610-8cf7-4ecb-aeba-04a57dc57a51 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2319743289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.2319743289 |
| Directory | /workspace/11.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/11.uart_loopback.3782468837 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 574374727 ps |
| CPU time | 2.8 seconds |
| Started | Jun 04 12:37:34 PM PDT 24 |
| Finished | Jun 04 12:37:38 PM PDT 24 |
| Peak memory | 198592 kb |
| Host | smart-4f468fe2-e4a0-4473-958f-007016a934db |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3782468837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_loopback.3782468837 |
| Directory | /workspace/11.uart_loopback/latest |
| Test location | /workspace/coverage/default/11.uart_noise_filter.2029571124 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 49220960909 ps |
| CPU time | 118.77 seconds |
| Started | Jun 04 12:37:34 PM PDT 24 |
| Finished | Jun 04 12:39:34 PM PDT 24 |
| Peak memory | 200260 kb |
| Host | smart-138d0afb-5cf3-4b1b-b06d-3b5842346e6e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2029571124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_noise_filter.2029571124 |
| Directory | /workspace/11.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/11.uart_perf.2101369628 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 16005437902 ps |
| CPU time | 431.06 seconds |
| Started | Jun 04 12:37:36 PM PDT 24 |
| Finished | Jun 04 12:44:48 PM PDT 24 |
| Peak memory | 200168 kb |
| Host | smart-0e404c8f-7b4f-4898-a32a-5c324b64fbcd |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2101369628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.2101369628 |
| Directory | /workspace/11.uart_perf/latest |
| Test location | /workspace/coverage/default/11.uart_rx_oversample.3415021014 |
| Short name | T960 |
| Test name | |
| Test status | |
| Simulation time | 2348091164 ps |
| CPU time | 16.13 seconds |
| Started | Jun 04 12:37:36 PM PDT 24 |
| Finished | Jun 04 12:37:53 PM PDT 24 |
| Peak memory | 199120 kb |
| Host | smart-1ed1dd77-16ee-4383-96e6-1eb74ae2da79 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3415021014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.3415021014 |
| Directory | /workspace/11.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/11.uart_rx_parity_err.2921341471 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 128697141876 ps |
| CPU time | 193.74 seconds |
| Started | Jun 04 12:37:38 PM PDT 24 |
| Finished | Jun 04 12:40:53 PM PDT 24 |
| Peak memory | 200252 kb |
| Host | smart-fe12b4dc-ba0c-449e-8469-64f523579939 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2921341471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.2921341471 |
| Directory | /workspace/11.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/11.uart_rx_start_bit_filter.1926666306 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 1553930849 ps |
| CPU time | 3.18 seconds |
| Started | Jun 04 12:37:34 PM PDT 24 |
| Finished | Jun 04 12:37:39 PM PDT 24 |
| Peak memory | 195716 kb |
| Host | smart-9ed3a0cd-0f13-488a-b705-7ad2fcd91ddb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1926666306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.1926666306 |
| Directory | /workspace/11.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/11.uart_smoke.580453347 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 680032785 ps |
| CPU time | 1.86 seconds |
| Started | Jun 04 12:37:33 PM PDT 24 |
| Finished | Jun 04 12:37:36 PM PDT 24 |
| Peak memory | 198908 kb |
| Host | smart-d9842afe-3493-4bf4-86f7-8f9caef02329 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=580453347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_smoke.580453347 |
| Directory | /workspace/11.uart_smoke/latest |
| Test location | /workspace/coverage/default/11.uart_stress_all.3469616582 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 552920926079 ps |
| CPU time | 83.72 seconds |
| Started | Jun 04 12:37:38 PM PDT 24 |
| Finished | Jun 04 12:39:02 PM PDT 24 |
| Peak memory | 200364 kb |
| Host | smart-fc95ac53-ab0b-408c-8346-130808c085ea |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469616582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.3469616582 |
| Directory | /workspace/11.uart_stress_all/latest |
| Test location | /workspace/coverage/default/11.uart_tx_ovrd.69020219 |
| Short name | T934 |
| Test name | |
| Test status | |
| Simulation time | 2178868675 ps |
| CPU time | 2.57 seconds |
| Started | Jun 04 12:37:34 PM PDT 24 |
| Finished | Jun 04 12:37:38 PM PDT 24 |
| Peak memory | 198248 kb |
| Host | smart-de875d61-b008-4ea7-9884-b8b605abc8a3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=69020219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.69020219 |
| Directory | /workspace/11.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/11.uart_tx_rx.290213154 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 48518102334 ps |
| CPU time | 78.42 seconds |
| Started | Jun 04 12:37:34 PM PDT 24 |
| Finished | Jun 04 12:38:54 PM PDT 24 |
| Peak memory | 200224 kb |
| Host | smart-40115ef3-58f4-4556-a66a-336d506a6da5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=290213154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.290213154 |
| Directory | /workspace/11.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/110.uart_fifo_reset.3707974518 |
| Short name | T1135 |
| Test name | |
| Test status | |
| Simulation time | 59314414029 ps |
| CPU time | 68.6 seconds |
| Started | Jun 04 12:41:33 PM PDT 24 |
| Finished | Jun 04 12:42:42 PM PDT 24 |
| Peak memory | 200144 kb |
| Host | smart-49e8690b-6150-4a50-8b34-eaff84fe19d1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3707974518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.3707974518 |
| Directory | /workspace/110.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/112.uart_fifo_reset.107038674 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 39576704720 ps |
| CPU time | 15.1 seconds |
| Started | Jun 04 12:41:33 PM PDT 24 |
| Finished | Jun 04 12:41:48 PM PDT 24 |
| Peak memory | 200200 kb |
| Host | smart-cc550c6d-b355-437c-abb3-cecdce0dae54 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=107038674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.107038674 |
| Directory | /workspace/112.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/113.uart_fifo_reset.2603996790 |
| Short name | T1155 |
| Test name | |
| Test status | |
| Simulation time | 49139785308 ps |
| CPU time | 22.5 seconds |
| Started | Jun 04 12:41:34 PM PDT 24 |
| Finished | Jun 04 12:41:58 PM PDT 24 |
| Peak memory | 200204 kb |
| Host | smart-1153f488-0d4e-4c91-9567-4b3badfdba69 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2603996790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.2603996790 |
| Directory | /workspace/113.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/114.uart_fifo_reset.2312111443 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 239333786690 ps |
| CPU time | 119.91 seconds |
| Started | Jun 04 12:41:34 PM PDT 24 |
| Finished | Jun 04 12:43:36 PM PDT 24 |
| Peak memory | 200392 kb |
| Host | smart-87251a5a-f517-4ec9-831e-797bbc67b9be |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2312111443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.2312111443 |
| Directory | /workspace/114.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/116.uart_fifo_reset.2542160782 |
| Short name | T1080 |
| Test name | |
| Test status | |
| Simulation time | 40649890563 ps |
| CPU time | 15.35 seconds |
| Started | Jun 04 12:41:33 PM PDT 24 |
| Finished | Jun 04 12:41:49 PM PDT 24 |
| Peak memory | 200220 kb |
| Host | smart-ad2b2e03-8251-44f7-92b7-e204c066dca3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2542160782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.2542160782 |
| Directory | /workspace/116.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/117.uart_fifo_reset.2659119325 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 19076800622 ps |
| CPU time | 38.92 seconds |
| Started | Jun 04 12:41:32 PM PDT 24 |
| Finished | Jun 04 12:42:12 PM PDT 24 |
| Peak memory | 200168 kb |
| Host | smart-b16b5c22-fbe1-4421-a6e6-a40ef5ce35e6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2659119325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.2659119325 |
| Directory | /workspace/117.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/118.uart_fifo_reset.3414096011 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 10451089751 ps |
| CPU time | 16.67 seconds |
| Started | Jun 04 12:41:38 PM PDT 24 |
| Finished | Jun 04 12:41:55 PM PDT 24 |
| Peak memory | 199920 kb |
| Host | smart-9f3af92b-0dfe-449b-bf1b-2baf9023baf9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3414096011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.3414096011 |
| Directory | /workspace/118.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/119.uart_fifo_reset.1605491764 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 38705079189 ps |
| CPU time | 37.2 seconds |
| Started | Jun 04 12:41:32 PM PDT 24 |
| Finished | Jun 04 12:42:09 PM PDT 24 |
| Peak memory | 200256 kb |
| Host | smart-125a09e9-87a4-4184-94ec-cabf405230ec |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1605491764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.1605491764 |
| Directory | /workspace/119.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/12.uart_alert_test.346736427 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 45867070 ps |
| CPU time | 0.56 seconds |
| Started | Jun 04 12:37:46 PM PDT 24 |
| Finished | Jun 04 12:37:48 PM PDT 24 |
| Peak memory | 195560 kb |
| Host | smart-d3bbfb82-7cf4-4a6b-9756-bfb91cb878b1 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346736427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.346736427 |
| Directory | /workspace/12.uart_alert_test/latest |
| Test location | /workspace/coverage/default/12.uart_fifo_full.59442716 |
| Short name | T984 |
| Test name | |
| Test status | |
| Simulation time | 39108887353 ps |
| CPU time | 17.94 seconds |
| Started | Jun 04 12:37:33 PM PDT 24 |
| Finished | Jun 04 12:37:52 PM PDT 24 |
| Peak memory | 200148 kb |
| Host | smart-d70ca89c-10eb-45f2-8d1b-6af746e3eb04 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=59442716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.59442716 |
| Directory | /workspace/12.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/12.uart_fifo_overflow.2359305175 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 11875584545 ps |
| CPU time | 19.45 seconds |
| Started | Jun 04 12:37:35 PM PDT 24 |
| Finished | Jun 04 12:37:56 PM PDT 24 |
| Peak memory | 200156 kb |
| Host | smart-d62ec20e-766a-4794-bbd1-b87ed3fea106 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2359305175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.2359305175 |
| Directory | /workspace/12.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/12.uart_fifo_reset.856453807 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 90432861206 ps |
| CPU time | 327.24 seconds |
| Started | Jun 04 12:37:34 PM PDT 24 |
| Finished | Jun 04 12:43:03 PM PDT 24 |
| Peak memory | 200200 kb |
| Host | smart-f96a3e9e-ce08-4b42-9977-63ba8e9736fe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=856453807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.856453807 |
| Directory | /workspace/12.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/12.uart_intr.3929177814 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 34051309808 ps |
| CPU time | 57.79 seconds |
| Started | Jun 04 12:37:45 PM PDT 24 |
| Finished | Jun 04 12:38:43 PM PDT 24 |
| Peak memory | 199720 kb |
| Host | smart-b7bfae50-f1fe-4379-8c29-d63f4c9da45e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929177814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.3929177814 |
| Directory | /workspace/12.uart_intr/latest |
| Test location | /workspace/coverage/default/12.uart_long_xfer_wo_dly.926509247 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 155000975557 ps |
| CPU time | 341.91 seconds |
| Started | Jun 04 12:37:46 PM PDT 24 |
| Finished | Jun 04 12:43:29 PM PDT 24 |
| Peak memory | 200224 kb |
| Host | smart-b1e9fc2c-3579-4842-8303-a59559354717 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=926509247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.926509247 |
| Directory | /workspace/12.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/12.uart_loopback.884355151 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 12691545332 ps |
| CPU time | 24.32 seconds |
| Started | Jun 04 12:37:45 PM PDT 24 |
| Finished | Jun 04 12:38:11 PM PDT 24 |
| Peak memory | 200068 kb |
| Host | smart-311ca70d-70d6-4d7f-ace2-60250f62b918 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=884355151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_loopback.884355151 |
| Directory | /workspace/12.uart_loopback/latest |
| Test location | /workspace/coverage/default/12.uart_noise_filter.1421656807 |
| Short name | T1124 |
| Test name | |
| Test status | |
| Simulation time | 60077720371 ps |
| CPU time | 22.72 seconds |
| Started | Jun 04 12:37:44 PM PDT 24 |
| Finished | Jun 04 12:38:08 PM PDT 24 |
| Peak memory | 197748 kb |
| Host | smart-760a461f-13b7-44bd-a43d-a9bd3346234b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1421656807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_noise_filter.1421656807 |
| Directory | /workspace/12.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/12.uart_perf.2554423355 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 17445238791 ps |
| CPU time | 791.1 seconds |
| Started | Jun 04 12:37:46 PM PDT 24 |
| Finished | Jun 04 12:50:58 PM PDT 24 |
| Peak memory | 200216 kb |
| Host | smart-b5c695d4-89f5-42a1-8e09-f90325907ad1 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2554423355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.2554423355 |
| Directory | /workspace/12.uart_perf/latest |
| Test location | /workspace/coverage/default/12.uart_rx_oversample.879348204 |
| Short name | T1016 |
| Test name | |
| Test status | |
| Simulation time | 6652139350 ps |
| CPU time | 29.58 seconds |
| Started | Jun 04 12:37:45 PM PDT 24 |
| Finished | Jun 04 12:38:15 PM PDT 24 |
| Peak memory | 199412 kb |
| Host | smart-5edd7f5b-1cde-4412-98f8-39e4a7f50536 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=879348204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.879348204 |
| Directory | /workspace/12.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/12.uart_rx_parity_err.3756091464 |
| Short name | T1157 |
| Test name | |
| Test status | |
| Simulation time | 54592141779 ps |
| CPU time | 21.33 seconds |
| Started | Jun 04 12:37:47 PM PDT 24 |
| Finished | Jun 04 12:38:10 PM PDT 24 |
| Peak memory | 199092 kb |
| Host | smart-25ad1e7b-fffa-484d-8d12-fdcff166a03a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3756091464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.3756091464 |
| Directory | /workspace/12.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/12.uart_rx_start_bit_filter.202714270 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 1422284365 ps |
| CPU time | 2.33 seconds |
| Started | Jun 04 12:37:45 PM PDT 24 |
| Finished | Jun 04 12:37:48 PM PDT 24 |
| Peak memory | 195600 kb |
| Host | smart-6b16d6d0-82ff-4b7d-94b9-1d6d563613f6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=202714270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.202714270 |
| Directory | /workspace/12.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/12.uart_smoke.510992695 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 5343596861 ps |
| CPU time | 25.52 seconds |
| Started | Jun 04 12:37:34 PM PDT 24 |
| Finished | Jun 04 12:38:01 PM PDT 24 |
| Peak memory | 199504 kb |
| Host | smart-4ce6c3f1-6d83-4027-92d8-483508845053 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=510992695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_smoke.510992695 |
| Directory | /workspace/12.uart_smoke/latest |
| Test location | /workspace/coverage/default/12.uart_stress_all.620740502 |
| Short name | T1108 |
| Test name | |
| Test status | |
| Simulation time | 362943923255 ps |
| CPU time | 607.75 seconds |
| Started | Jun 04 12:37:44 PM PDT 24 |
| Finished | Jun 04 12:47:52 PM PDT 24 |
| Peak memory | 208608 kb |
| Host | smart-c075606c-891d-43c1-aef1-8ae52acd7c83 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620740502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.620740502 |
| Directory | /workspace/12.uart_stress_all/latest |
| Test location | /workspace/coverage/default/12.uart_tx_ovrd.455667540 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 1724406105 ps |
| CPU time | 2.63 seconds |
| Started | Jun 04 12:37:46 PM PDT 24 |
| Finished | Jun 04 12:37:50 PM PDT 24 |
| Peak memory | 198924 kb |
| Host | smart-790dd0ac-b552-4e44-bae7-ff45f4576feb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=455667540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.455667540 |
| Directory | /workspace/12.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/12.uart_tx_rx.4274728706 |
| Short name | T971 |
| Test name | |
| Test status | |
| Simulation time | 4648344746 ps |
| CPU time | 10.11 seconds |
| Started | Jun 04 12:37:34 PM PDT 24 |
| Finished | Jun 04 12:37:45 PM PDT 24 |
| Peak memory | 200256 kb |
| Host | smart-86f55bb3-6fd7-4280-9fed-18be5e59c6f7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4274728706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.4274728706 |
| Directory | /workspace/12.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/121.uart_fifo_reset.1392411667 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 72783254030 ps |
| CPU time | 109.48 seconds |
| Started | Jun 04 12:41:32 PM PDT 24 |
| Finished | Jun 04 12:43:22 PM PDT 24 |
| Peak memory | 200184 kb |
| Host | smart-5fd2bdc9-1568-4b8b-8bac-a0f365daf987 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1392411667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.1392411667 |
| Directory | /workspace/121.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/126.uart_fifo_reset.3344963886 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 72291344189 ps |
| CPU time | 75.15 seconds |
| Started | Jun 04 12:41:33 PM PDT 24 |
| Finished | Jun 04 12:42:49 PM PDT 24 |
| Peak memory | 200284 kb |
| Host | smart-42a8ee63-6695-4ddb-8941-cccdb1d1ef13 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3344963886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.3344963886 |
| Directory | /workspace/126.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/127.uart_fifo_reset.3844087534 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 48981088599 ps |
| CPU time | 103.79 seconds |
| Started | Jun 04 12:41:34 PM PDT 24 |
| Finished | Jun 04 12:43:18 PM PDT 24 |
| Peak memory | 199976 kb |
| Host | smart-1ad948b4-4889-41d2-8be2-b53deb942fe6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3844087534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.3844087534 |
| Directory | /workspace/127.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/128.uart_fifo_reset.3669993060 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 64589586947 ps |
| CPU time | 29.05 seconds |
| Started | Jun 04 12:41:35 PM PDT 24 |
| Finished | Jun 04 12:42:05 PM PDT 24 |
| Peak memory | 200160 kb |
| Host | smart-dc081349-bd33-4c80-af01-944a6960136f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3669993060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.3669993060 |
| Directory | /workspace/128.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/13.uart_alert_test.4122225445 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 17587459 ps |
| CPU time | 0.57 seconds |
| Started | Jun 04 12:37:46 PM PDT 24 |
| Finished | Jun 04 12:37:48 PM PDT 24 |
| Peak memory | 195228 kb |
| Host | smart-cef63262-a3a7-42c4-bae4-fdf2ab475327 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122225445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.4122225445 |
| Directory | /workspace/13.uart_alert_test/latest |
| Test location | /workspace/coverage/default/13.uart_fifo_full.3744545703 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 76090359559 ps |
| CPU time | 33.21 seconds |
| Started | Jun 04 12:37:46 PM PDT 24 |
| Finished | Jun 04 12:38:21 PM PDT 24 |
| Peak memory | 200132 kb |
| Host | smart-5e7799a7-9c39-4c31-8e26-313ae5ade07b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3744545703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.3744545703 |
| Directory | /workspace/13.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/13.uart_fifo_overflow.2890392183 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 107270641167 ps |
| CPU time | 249.32 seconds |
| Started | Jun 04 12:37:45 PM PDT 24 |
| Finished | Jun 04 12:41:55 PM PDT 24 |
| Peak memory | 200140 kb |
| Host | smart-3e480f29-6796-4f19-acb6-23bc0425d732 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2890392183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.2890392183 |
| Directory | /workspace/13.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/13.uart_fifo_reset.2312509117 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 94320515778 ps |
| CPU time | 56.6 seconds |
| Started | Jun 04 12:37:47 PM PDT 24 |
| Finished | Jun 04 12:38:45 PM PDT 24 |
| Peak memory | 200220 kb |
| Host | smart-df24b5be-7dad-4058-81fb-c9bc56a1a9d8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2312509117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.2312509117 |
| Directory | /workspace/13.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/13.uart_intr.3627471387 |
| Short name | T995 |
| Test name | |
| Test status | |
| Simulation time | 54399030096 ps |
| CPU time | 12.15 seconds |
| Started | Jun 04 12:37:46 PM PDT 24 |
| Finished | Jun 04 12:38:00 PM PDT 24 |
| Peak memory | 200184 kb |
| Host | smart-b9ad270e-f026-45a4-bb92-584bd0c81dea |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627471387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.3627471387 |
| Directory | /workspace/13.uart_intr/latest |
| Test location | /workspace/coverage/default/13.uart_long_xfer_wo_dly.1763012370 |
| Short name | T1022 |
| Test name | |
| Test status | |
| Simulation time | 136187217698 ps |
| CPU time | 453.46 seconds |
| Started | Jun 04 12:37:46 PM PDT 24 |
| Finished | Jun 04 12:45:21 PM PDT 24 |
| Peak memory | 199764 kb |
| Host | smart-c79e2967-eb8c-4077-aad2-fb246bb96c69 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1763012370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.1763012370 |
| Directory | /workspace/13.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/13.uart_loopback.1072220937 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 4379572300 ps |
| CPU time | 5.69 seconds |
| Started | Jun 04 12:37:47 PM PDT 24 |
| Finished | Jun 04 12:37:54 PM PDT 24 |
| Peak memory | 199288 kb |
| Host | smart-9c4ddaf1-ec57-4d7b-9082-27fe06259aed |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1072220937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_loopback.1072220937 |
| Directory | /workspace/13.uart_loopback/latest |
| Test location | /workspace/coverage/default/13.uart_noise_filter.3031552973 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 6992368640 ps |
| CPU time | 12.2 seconds |
| Started | Jun 04 12:37:46 PM PDT 24 |
| Finished | Jun 04 12:38:00 PM PDT 24 |
| Peak memory | 197168 kb |
| Host | smart-ea565063-ba85-4058-898b-05cbec513180 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3031552973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_noise_filter.3031552973 |
| Directory | /workspace/13.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/13.uart_perf.723621230 |
| Short name | T921 |
| Test name | |
| Test status | |
| Simulation time | 14633578001 ps |
| CPU time | 404.25 seconds |
| Started | Jun 04 12:37:45 PM PDT 24 |
| Finished | Jun 04 12:44:31 PM PDT 24 |
| Peak memory | 200288 kb |
| Host | smart-d463d462-f521-4ebf-b31f-5ad777750560 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=723621230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.723621230 |
| Directory | /workspace/13.uart_perf/latest |
| Test location | /workspace/coverage/default/13.uart_rx_oversample.786211331 |
| Short name | T930 |
| Test name | |
| Test status | |
| Simulation time | 2623612419 ps |
| CPU time | 6.88 seconds |
| Started | Jun 04 12:37:45 PM PDT 24 |
| Finished | Jun 04 12:37:53 PM PDT 24 |
| Peak memory | 198708 kb |
| Host | smart-b9703e25-f25f-432e-a241-f2cad86976b5 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=786211331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.786211331 |
| Directory | /workspace/13.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/13.uart_rx_parity_err.310340667 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 166159053078 ps |
| CPU time | 36.89 seconds |
| Started | Jun 04 12:37:46 PM PDT 24 |
| Finished | Jun 04 12:38:24 PM PDT 24 |
| Peak memory | 200176 kb |
| Host | smart-49cf0e2d-16db-457a-89fb-3c08622f0314 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=310340667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.310340667 |
| Directory | /workspace/13.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/13.uart_rx_start_bit_filter.3617880374 |
| Short name | T936 |
| Test name | |
| Test status | |
| Simulation time | 5351072302 ps |
| CPU time | 4.93 seconds |
| Started | Jun 04 12:37:45 PM PDT 24 |
| Finished | Jun 04 12:37:51 PM PDT 24 |
| Peak memory | 196644 kb |
| Host | smart-23f6e51d-9ff5-4991-98e6-7fad23dd9cb3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3617880374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.3617880374 |
| Directory | /workspace/13.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/13.uart_smoke.1851642110 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 5991549387 ps |
| CPU time | 21.66 seconds |
| Started | Jun 04 12:37:47 PM PDT 24 |
| Finished | Jun 04 12:38:10 PM PDT 24 |
| Peak memory | 199504 kb |
| Host | smart-a9ba8644-8227-4a29-b1e0-bc191cd3205c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1851642110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_smoke.1851642110 |
| Directory | /workspace/13.uart_smoke/latest |
| Test location | /workspace/coverage/default/13.uart_tx_ovrd.2731186193 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 861259145 ps |
| CPU time | 2.6 seconds |
| Started | Jun 04 12:37:44 PM PDT 24 |
| Finished | Jun 04 12:37:47 PM PDT 24 |
| Peak memory | 198472 kb |
| Host | smart-bd55ba56-b20d-4714-b3d4-bb0e61087b79 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2731186193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.2731186193 |
| Directory | /workspace/13.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/13.uart_tx_rx.3728056018 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 31370013501 ps |
| CPU time | 47.35 seconds |
| Started | Jun 04 12:37:47 PM PDT 24 |
| Finished | Jun 04 12:38:36 PM PDT 24 |
| Peak memory | 200196 kb |
| Host | smart-9c1ab0f4-c19e-469a-834b-c2fbe43e1b24 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3728056018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.3728056018 |
| Directory | /workspace/13.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/130.uart_fifo_reset.4259005204 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 117482035716 ps |
| CPU time | 108.02 seconds |
| Started | Jun 04 12:41:36 PM PDT 24 |
| Finished | Jun 04 12:43:25 PM PDT 24 |
| Peak memory | 199876 kb |
| Host | smart-c35b5aac-95d4-488c-a57e-e0bb62ccb6b7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4259005204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.4259005204 |
| Directory | /workspace/130.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/131.uart_fifo_reset.2349845977 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 21430417603 ps |
| CPU time | 34.61 seconds |
| Started | Jun 04 12:41:33 PM PDT 24 |
| Finished | Jun 04 12:42:08 PM PDT 24 |
| Peak memory | 200128 kb |
| Host | smart-ee6ecf86-0407-4969-9d6b-5b1f6b9a29b3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2349845977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.2349845977 |
| Directory | /workspace/131.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/132.uart_fifo_reset.3859238592 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 42835832020 ps |
| CPU time | 19.91 seconds |
| Started | Jun 04 12:41:32 PM PDT 24 |
| Finished | Jun 04 12:41:53 PM PDT 24 |
| Peak memory | 200336 kb |
| Host | smart-0b86fdf4-3234-4e28-9950-048c54261f89 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3859238592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.3859238592 |
| Directory | /workspace/132.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/133.uart_fifo_reset.1136564492 |
| Short name | T1129 |
| Test name | |
| Test status | |
| Simulation time | 37293298391 ps |
| CPU time | 69.21 seconds |
| Started | Jun 04 12:41:35 PM PDT 24 |
| Finished | Jun 04 12:42:45 PM PDT 24 |
| Peak memory | 200296 kb |
| Host | smart-7c7abff5-6a62-4f7d-a46f-2d68f32dac29 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1136564492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.1136564492 |
| Directory | /workspace/133.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/134.uart_fifo_reset.3096902531 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 96756700869 ps |
| CPU time | 168.6 seconds |
| Started | Jun 04 12:41:35 PM PDT 24 |
| Finished | Jun 04 12:44:25 PM PDT 24 |
| Peak memory | 200224 kb |
| Host | smart-836227de-18f0-4d18-8ab8-83c4f7a1a4f0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3096902531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.3096902531 |
| Directory | /workspace/134.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/136.uart_fifo_reset.3301454503 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 99459296041 ps |
| CPU time | 268.77 seconds |
| Started | Jun 04 12:41:50 PM PDT 24 |
| Finished | Jun 04 12:46:19 PM PDT 24 |
| Peak memory | 200120 kb |
| Host | smart-10025871-aa3a-4434-a3a3-09f62b737b81 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3301454503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.3301454503 |
| Directory | /workspace/136.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/137.uart_fifo_reset.1614102362 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 29280200981 ps |
| CPU time | 22.47 seconds |
| Started | Jun 04 12:41:43 PM PDT 24 |
| Finished | Jun 04 12:42:06 PM PDT 24 |
| Peak memory | 200120 kb |
| Host | smart-dc67d2ad-2e91-4755-88b3-9908e0df89de |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1614102362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.1614102362 |
| Directory | /workspace/137.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/139.uart_fifo_reset.4152509943 |
| Short name | T997 |
| Test name | |
| Test status | |
| Simulation time | 116879545029 ps |
| CPU time | 52.25 seconds |
| Started | Jun 04 12:41:42 PM PDT 24 |
| Finished | Jun 04 12:42:35 PM PDT 24 |
| Peak memory | 200260 kb |
| Host | smart-2f5d8218-eb7f-4003-b702-a06f30ad6616 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4152509943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.4152509943 |
| Directory | /workspace/139.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/14.uart_alert_test.1892177149 |
| Short name | T1032 |
| Test name | |
| Test status | |
| Simulation time | 25024946 ps |
| CPU time | 0.56 seconds |
| Started | Jun 04 12:37:55 PM PDT 24 |
| Finished | Jun 04 12:37:57 PM PDT 24 |
| Peak memory | 195596 kb |
| Host | smart-5b356236-6a34-4090-afb3-88abb7e90aa4 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892177149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.1892177149 |
| Directory | /workspace/14.uart_alert_test/latest |
| Test location | /workspace/coverage/default/14.uart_fifo_full.1705264139 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 237723193216 ps |
| CPU time | 358.72 seconds |
| Started | Jun 04 12:37:45 PM PDT 24 |
| Finished | Jun 04 12:43:44 PM PDT 24 |
| Peak memory | 200104 kb |
| Host | smart-a928bd90-ddde-42f7-8d5a-f60af9bfac21 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1705264139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.1705264139 |
| Directory | /workspace/14.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/14.uart_fifo_overflow.250813708 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 45347655299 ps |
| CPU time | 75.55 seconds |
| Started | Jun 04 12:37:46 PM PDT 24 |
| Finished | Jun 04 12:39:03 PM PDT 24 |
| Peak memory | 200100 kb |
| Host | smart-d7a5a119-6d31-4633-ac5d-1258b10093b5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=250813708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.250813708 |
| Directory | /workspace/14.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/14.uart_fifo_reset.3035589934 |
| Short name | T1018 |
| Test name | |
| Test status | |
| Simulation time | 30009620371 ps |
| CPU time | 16.21 seconds |
| Started | Jun 04 12:37:45 PM PDT 24 |
| Finished | Jun 04 12:38:03 PM PDT 24 |
| Peak memory | 200096 kb |
| Host | smart-57801900-e1e8-43c7-9125-e06fd51cc194 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3035589934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.3035589934 |
| Directory | /workspace/14.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/14.uart_intr.2827653179 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 72912980791 ps |
| CPU time | 24.24 seconds |
| Started | Jun 04 12:38:00 PM PDT 24 |
| Finished | Jun 04 12:38:25 PM PDT 24 |
| Peak memory | 200168 kb |
| Host | smart-6a243ec2-0739-4c48-b7dd-db25b7b395aa |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827653179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.2827653179 |
| Directory | /workspace/14.uart_intr/latest |
| Test location | /workspace/coverage/default/14.uart_long_xfer_wo_dly.319806332 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 130365550570 ps |
| CPU time | 1075.09 seconds |
| Started | Jun 04 12:38:01 PM PDT 24 |
| Finished | Jun 04 12:55:56 PM PDT 24 |
| Peak memory | 200224 kb |
| Host | smart-1a395144-0733-47ab-9a28-533ad44f84fe |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=319806332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.319806332 |
| Directory | /workspace/14.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/14.uart_loopback.66895113 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 178737303 ps |
| CPU time | 0.64 seconds |
| Started | Jun 04 12:38:01 PM PDT 24 |
| Finished | Jun 04 12:38:03 PM PDT 24 |
| Peak memory | 196032 kb |
| Host | smart-0b44b8b6-cbaa-46c4-927c-cd4cd5925426 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=66895113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_loopback.66895113 |
| Directory | /workspace/14.uart_loopback/latest |
| Test location | /workspace/coverage/default/14.uart_noise_filter.2123552433 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 151757466718 ps |
| CPU time | 428.54 seconds |
| Started | Jun 04 12:38:01 PM PDT 24 |
| Finished | Jun 04 12:45:10 PM PDT 24 |
| Peak memory | 199964 kb |
| Host | smart-4815859d-7b6f-4863-b4e6-75826780f4ed |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2123552433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_noise_filter.2123552433 |
| Directory | /workspace/14.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/14.uart_perf.3160467811 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 4837293493 ps |
| CPU time | 135.27 seconds |
| Started | Jun 04 12:37:53 PM PDT 24 |
| Finished | Jun 04 12:40:09 PM PDT 24 |
| Peak memory | 200184 kb |
| Host | smart-8f17b624-c8a0-490c-9916-daae6ed4bc28 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3160467811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.3160467811 |
| Directory | /workspace/14.uart_perf/latest |
| Test location | /workspace/coverage/default/14.uart_rx_oversample.1936432864 |
| Short name | T982 |
| Test name | |
| Test status | |
| Simulation time | 4451937604 ps |
| CPU time | 19.31 seconds |
| Started | Jun 04 12:37:44 PM PDT 24 |
| Finished | Jun 04 12:38:04 PM PDT 24 |
| Peak memory | 199580 kb |
| Host | smart-975f30ff-a5de-42f6-b282-2bba0a0e999f |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1936432864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.1936432864 |
| Directory | /workspace/14.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/14.uart_rx_parity_err.2542603992 |
| Short name | T1085 |
| Test name | |
| Test status | |
| Simulation time | 111279940090 ps |
| CPU time | 170.89 seconds |
| Started | Jun 04 12:37:58 PM PDT 24 |
| Finished | Jun 04 12:40:49 PM PDT 24 |
| Peak memory | 200160 kb |
| Host | smart-8ed254ec-1616-4aa8-b4d4-d52604db832c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2542603992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.2542603992 |
| Directory | /workspace/14.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/14.uart_rx_start_bit_filter.3869668001 |
| Short name | T1109 |
| Test name | |
| Test status | |
| Simulation time | 2949094719 ps |
| CPU time | 5.04 seconds |
| Started | Jun 04 12:37:56 PM PDT 24 |
| Finished | Jun 04 12:38:02 PM PDT 24 |
| Peak memory | 196140 kb |
| Host | smart-15629a4d-2fba-42e9-af35-2c0fc0b201b0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3869668001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.3869668001 |
| Directory | /workspace/14.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/14.uart_smoke.4071466653 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 6163906244 ps |
| CPU time | 10.3 seconds |
| Started | Jun 04 12:37:45 PM PDT 24 |
| Finished | Jun 04 12:37:57 PM PDT 24 |
| Peak memory | 199800 kb |
| Host | smart-3987f9d8-659f-46e8-99dd-f9d8d6629de6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4071466653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_smoke.4071466653 |
| Directory | /workspace/14.uart_smoke/latest |
| Test location | /workspace/coverage/default/14.uart_stress_all.4256198337 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 282262806394 ps |
| CPU time | 421.68 seconds |
| Started | Jun 04 12:37:54 PM PDT 24 |
| Finished | Jun 04 12:44:57 PM PDT 24 |
| Peak memory | 200212 kb |
| Host | smart-1cf3d2ac-2468-4756-b3de-683f67b485e2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256198337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.4256198337 |
| Directory | /workspace/14.uart_stress_all/latest |
| Test location | /workspace/coverage/default/14.uart_stress_all_with_rand_reset.72404325 |
| Short name | T951 |
| Test name | |
| Test status | |
| Simulation time | 89171599272 ps |
| CPU time | 969.43 seconds |
| Started | Jun 04 12:37:54 PM PDT 24 |
| Finished | Jun 04 12:54:05 PM PDT 24 |
| Peak memory | 232580 kb |
| Host | smart-e49afa95-9db1-4cc1-956a-93668ede7616 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72404325 -assert nopostpro c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 14.uart_stress_all_with_rand_reset.72404325 |
| Directory | /workspace/14.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/14.uart_tx_ovrd.347136282 |
| Short name | T1019 |
| Test name | |
| Test status | |
| Simulation time | 521181401 ps |
| CPU time | 1.86 seconds |
| Started | Jun 04 12:37:54 PM PDT 24 |
| Finished | Jun 04 12:37:57 PM PDT 24 |
| Peak memory | 200240 kb |
| Host | smart-5187e757-46dd-4ea1-bffb-535a921989e3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=347136282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.347136282 |
| Directory | /workspace/14.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/14.uart_tx_rx.3968076218 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 54055373736 ps |
| CPU time | 21.16 seconds |
| Started | Jun 04 12:37:46 PM PDT 24 |
| Finished | Jun 04 12:38:08 PM PDT 24 |
| Peak memory | 200112 kb |
| Host | smart-4fee8bb2-09c6-4679-adc2-5094c0f9f69f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3968076218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.3968076218 |
| Directory | /workspace/14.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/140.uart_fifo_reset.2713207626 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 63354620967 ps |
| CPU time | 57.09 seconds |
| Started | Jun 04 12:41:41 PM PDT 24 |
| Finished | Jun 04 12:42:39 PM PDT 24 |
| Peak memory | 200332 kb |
| Host | smart-0a0380a8-ed95-48f3-9a49-f55bcb901f80 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2713207626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.2713207626 |
| Directory | /workspace/140.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/141.uart_fifo_reset.1689958170 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 48035832606 ps |
| CPU time | 18.28 seconds |
| Started | Jun 04 12:41:42 PM PDT 24 |
| Finished | Jun 04 12:42:01 PM PDT 24 |
| Peak memory | 200396 kb |
| Host | smart-fc4b22ec-a347-4ed4-a940-e8b9d6aab7b5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1689958170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.1689958170 |
| Directory | /workspace/141.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/142.uart_fifo_reset.3494280084 |
| Short name | T948 |
| Test name | |
| Test status | |
| Simulation time | 193325549441 ps |
| CPU time | 144.28 seconds |
| Started | Jun 04 12:41:50 PM PDT 24 |
| Finished | Jun 04 12:44:15 PM PDT 24 |
| Peak memory | 200148 kb |
| Host | smart-2d4205a6-7636-4098-bd42-fd32737a93a9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3494280084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.3494280084 |
| Directory | /workspace/142.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/143.uart_fifo_reset.4086817726 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 73534015920 ps |
| CPU time | 44.34 seconds |
| Started | Jun 04 12:41:42 PM PDT 24 |
| Finished | Jun 04 12:42:28 PM PDT 24 |
| Peak memory | 200304 kb |
| Host | smart-2f93bc43-d2fb-4fe8-9df4-5711e04abceb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4086817726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.4086817726 |
| Directory | /workspace/143.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/144.uart_fifo_reset.2640042446 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 202328542721 ps |
| CPU time | 344.35 seconds |
| Started | Jun 04 12:41:49 PM PDT 24 |
| Finished | Jun 04 12:47:35 PM PDT 24 |
| Peak memory | 200204 kb |
| Host | smart-6380a07e-caa6-4385-bfb7-d131d83c035d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2640042446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.2640042446 |
| Directory | /workspace/144.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/145.uart_fifo_reset.2780121502 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 81006214352 ps |
| CPU time | 40.64 seconds |
| Started | Jun 04 12:41:41 PM PDT 24 |
| Finished | Jun 04 12:42:22 PM PDT 24 |
| Peak memory | 200132 kb |
| Host | smart-54e02299-4f8c-46a8-950e-87ba9bbe4a4f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2780121502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.2780121502 |
| Directory | /workspace/145.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/146.uart_fifo_reset.1182537042 |
| Short name | T1091 |
| Test name | |
| Test status | |
| Simulation time | 12116304276 ps |
| CPU time | 17.88 seconds |
| Started | Jun 04 12:41:41 PM PDT 24 |
| Finished | Jun 04 12:42:00 PM PDT 24 |
| Peak memory | 200160 kb |
| Host | smart-b6100abd-4bcd-4514-a84d-5c401d59a223 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1182537042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.1182537042 |
| Directory | /workspace/146.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/147.uart_fifo_reset.4215699404 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 21915396993 ps |
| CPU time | 15.97 seconds |
| Started | Jun 04 12:41:43 PM PDT 24 |
| Finished | Jun 04 12:42:00 PM PDT 24 |
| Peak memory | 199944 kb |
| Host | smart-901553de-bb43-4303-9217-b768bfdb72ea |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4215699404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.4215699404 |
| Directory | /workspace/147.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/148.uart_fifo_reset.4090075763 |
| Short name | T1031 |
| Test name | |
| Test status | |
| Simulation time | 407561929189 ps |
| CPU time | 96.73 seconds |
| Started | Jun 04 12:41:50 PM PDT 24 |
| Finished | Jun 04 12:43:27 PM PDT 24 |
| Peak memory | 200124 kb |
| Host | smart-53a21863-1b7b-45e3-9746-3f22c9f8cdf8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4090075763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.4090075763 |
| Directory | /workspace/148.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/15.uart_alert_test.1836038645 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 18253597 ps |
| CPU time | 0.57 seconds |
| Started | Jun 04 12:37:56 PM PDT 24 |
| Finished | Jun 04 12:37:57 PM PDT 24 |
| Peak memory | 195708 kb |
| Host | smart-d7b06320-dfd5-49bc-ae14-fb092a5d3553 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836038645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.1836038645 |
| Directory | /workspace/15.uart_alert_test/latest |
| Test location | /workspace/coverage/default/15.uart_fifo_full.384739920 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 30929462239 ps |
| CPU time | 23.01 seconds |
| Started | Jun 04 12:37:58 PM PDT 24 |
| Finished | Jun 04 12:38:22 PM PDT 24 |
| Peak memory | 200148 kb |
| Host | smart-810caeb6-7e7d-42d3-9ee1-e2969061a885 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=384739920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.384739920 |
| Directory | /workspace/15.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/15.uart_fifo_overflow.11877712 |
| Short name | T1043 |
| Test name | |
| Test status | |
| Simulation time | 103365117042 ps |
| CPU time | 39.89 seconds |
| Started | Jun 04 12:37:54 PM PDT 24 |
| Finished | Jun 04 12:38:34 PM PDT 24 |
| Peak memory | 200040 kb |
| Host | smart-d6314bb6-d243-4c5f-8bdb-8ed4101ec9d2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=11877712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.11877712 |
| Directory | /workspace/15.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/15.uart_fifo_reset.2775330147 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 162859840987 ps |
| CPU time | 51.73 seconds |
| Started | Jun 04 12:37:54 PM PDT 24 |
| Finished | Jun 04 12:38:46 PM PDT 24 |
| Peak memory | 200092 kb |
| Host | smart-b903d9fb-9974-46d7-8a10-92b3b389da7b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2775330147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.2775330147 |
| Directory | /workspace/15.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/15.uart_intr.3144292411 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 337606489389 ps |
| CPU time | 142.53 seconds |
| Started | Jun 04 12:38:04 PM PDT 24 |
| Finished | Jun 04 12:40:27 PM PDT 24 |
| Peak memory | 199672 kb |
| Host | smart-34ff0cb0-fb53-4849-a915-a79691c247d1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144292411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.3144292411 |
| Directory | /workspace/15.uart_intr/latest |
| Test location | /workspace/coverage/default/15.uart_long_xfer_wo_dly.3281894774 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 71012207176 ps |
| CPU time | 135.17 seconds |
| Started | Jun 04 12:37:57 PM PDT 24 |
| Finished | Jun 04 12:40:13 PM PDT 24 |
| Peak memory | 200268 kb |
| Host | smart-a1bf7100-8908-4070-868c-f22a847e4378 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3281894774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.3281894774 |
| Directory | /workspace/15.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/15.uart_loopback.2360888257 |
| Short name | T1164 |
| Test name | |
| Test status | |
| Simulation time | 9621163327 ps |
| CPU time | 6.59 seconds |
| Started | Jun 04 12:37:54 PM PDT 24 |
| Finished | Jun 04 12:38:02 PM PDT 24 |
| Peak memory | 200028 kb |
| Host | smart-43021f3c-be83-4895-97d2-abb5997a44a3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2360888257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_loopback.2360888257 |
| Directory | /workspace/15.uart_loopback/latest |
| Test location | /workspace/coverage/default/15.uart_noise_filter.851679449 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 32008973194 ps |
| CPU time | 38.96 seconds |
| Started | Jun 04 12:37:56 PM PDT 24 |
| Finished | Jun 04 12:38:35 PM PDT 24 |
| Peak memory | 199236 kb |
| Host | smart-1239bdcb-e05d-4994-adcd-18f751b6c038 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=851679449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_noise_filter.851679449 |
| Directory | /workspace/15.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/15.uart_perf.3924187470 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 6353049518 ps |
| CPU time | 92.66 seconds |
| Started | Jun 04 12:37:55 PM PDT 24 |
| Finished | Jun 04 12:39:28 PM PDT 24 |
| Peak memory | 200156 kb |
| Host | smart-6aee1b45-5d69-4f25-9930-2d2973ef1579 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3924187470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.3924187470 |
| Directory | /workspace/15.uart_perf/latest |
| Test location | /workspace/coverage/default/15.uart_rx_oversample.1045089645 |
| Short name | T1048 |
| Test name | |
| Test status | |
| Simulation time | 4684583410 ps |
| CPU time | 8.84 seconds |
| Started | Jun 04 12:37:56 PM PDT 24 |
| Finished | Jun 04 12:38:06 PM PDT 24 |
| Peak memory | 198328 kb |
| Host | smart-1ad7cf6f-88c9-4ed5-ba3c-6f802e443fd1 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1045089645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.1045089645 |
| Directory | /workspace/15.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/15.uart_rx_parity_err.558584637 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 88767984143 ps |
| CPU time | 184.68 seconds |
| Started | Jun 04 12:37:55 PM PDT 24 |
| Finished | Jun 04 12:41:00 PM PDT 24 |
| Peak memory | 200228 kb |
| Host | smart-8044f3e8-d17e-4cf4-87f0-d7c26ea8cf51 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=558584637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.558584637 |
| Directory | /workspace/15.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/15.uart_rx_start_bit_filter.266457028 |
| Short name | T1021 |
| Test name | |
| Test status | |
| Simulation time | 3986375392 ps |
| CPU time | 6.74 seconds |
| Started | Jun 04 12:37:56 PM PDT 24 |
| Finished | Jun 04 12:38:03 PM PDT 24 |
| Peak memory | 196504 kb |
| Host | smart-9d166c8f-ab60-40ea-aa79-aac481455fde |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=266457028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.266457028 |
| Directory | /workspace/15.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/15.uart_smoke.4097541675 |
| Short name | T928 |
| Test name | |
| Test status | |
| Simulation time | 626694951 ps |
| CPU time | 2.91 seconds |
| Started | Jun 04 12:38:02 PM PDT 24 |
| Finished | Jun 04 12:38:05 PM PDT 24 |
| Peak memory | 200116 kb |
| Host | smart-2f3c9b86-0d92-458f-bb42-7e73f781b56c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4097541675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_smoke.4097541675 |
| Directory | /workspace/15.uart_smoke/latest |
| Test location | /workspace/coverage/default/15.uart_stress_all.1508606541 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 116063220032 ps |
| CPU time | 198.11 seconds |
| Started | Jun 04 12:37:54 PM PDT 24 |
| Finished | Jun 04 12:41:13 PM PDT 24 |
| Peak memory | 200128 kb |
| Host | smart-f5218590-be56-4271-bf15-53fde0be4b97 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508606541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.1508606541 |
| Directory | /workspace/15.uart_stress_all/latest |
| Test location | /workspace/coverage/default/15.uart_stress_all_with_rand_reset.3852311301 |
| Short name | T1097 |
| Test name | |
| Test status | |
| Simulation time | 41261692360 ps |
| CPU time | 518.13 seconds |
| Started | Jun 04 12:37:55 PM PDT 24 |
| Finished | Jun 04 12:46:34 PM PDT 24 |
| Peak memory | 215844 kb |
| Host | smart-4dce71f0-8f4c-47ad-b220-1236d6b0c106 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852311301 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 15.uart_stress_all_with_rand_reset.3852311301 |
| Directory | /workspace/15.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/15.uart_tx_ovrd.1574427946 |
| Short name | T1086 |
| Test name | |
| Test status | |
| Simulation time | 7315728992 ps |
| CPU time | 8.34 seconds |
| Started | Jun 04 12:37:55 PM PDT 24 |
| Finished | Jun 04 12:38:04 PM PDT 24 |
| Peak memory | 200144 kb |
| Host | smart-226f0a15-9b07-4b69-a22a-f9e6fa31de00 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1574427946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.1574427946 |
| Directory | /workspace/15.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/15.uart_tx_rx.105747999 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 89180623786 ps |
| CPU time | 56.07 seconds |
| Started | Jun 04 12:37:55 PM PDT 24 |
| Finished | Jun 04 12:38:52 PM PDT 24 |
| Peak memory | 200092 kb |
| Host | smart-87a432e4-83d8-46a7-82f6-cb016540cb7c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=105747999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.105747999 |
| Directory | /workspace/15.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/150.uart_fifo_reset.1076904839 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 40755001653 ps |
| CPU time | 64.67 seconds |
| Started | Jun 04 12:41:45 PM PDT 24 |
| Finished | Jun 04 12:42:51 PM PDT 24 |
| Peak memory | 200204 kb |
| Host | smart-c46a6ee0-785a-4038-9166-fe6c2bdc52d2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1076904839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.1076904839 |
| Directory | /workspace/150.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/151.uart_fifo_reset.866781769 |
| Short name | T1177 |
| Test name | |
| Test status | |
| Simulation time | 177629723430 ps |
| CPU time | 34.74 seconds |
| Started | Jun 04 12:41:44 PM PDT 24 |
| Finished | Jun 04 12:42:19 PM PDT 24 |
| Peak memory | 200132 kb |
| Host | smart-67c757bd-f6e2-4889-bcaa-fb13b14d356e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=866781769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.866781769 |
| Directory | /workspace/151.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/153.uart_fifo_reset.1684814208 |
| Short name | T933 |
| Test name | |
| Test status | |
| Simulation time | 33596071972 ps |
| CPU time | 46.85 seconds |
| Started | Jun 04 12:41:42 PM PDT 24 |
| Finished | Jun 04 12:42:30 PM PDT 24 |
| Peak memory | 200096 kb |
| Host | smart-7b7d3404-c5e9-474c-87d5-3ecf1d85bcf4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1684814208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.1684814208 |
| Directory | /workspace/153.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/154.uart_fifo_reset.120210966 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 98040437219 ps |
| CPU time | 286.93 seconds |
| Started | Jun 04 12:41:41 PM PDT 24 |
| Finished | Jun 04 12:46:29 PM PDT 24 |
| Peak memory | 200252 kb |
| Host | smart-13c4ef8a-a7a9-4013-be55-75a7868ad4f3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=120210966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.120210966 |
| Directory | /workspace/154.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/155.uart_fifo_reset.4025296982 |
| Short name | T1113 |
| Test name | |
| Test status | |
| Simulation time | 178847943879 ps |
| CPU time | 230.09 seconds |
| Started | Jun 04 12:41:42 PM PDT 24 |
| Finished | Jun 04 12:45:33 PM PDT 24 |
| Peak memory | 200232 kb |
| Host | smart-630f1425-25ab-474b-a230-b4b1572cd5a6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4025296982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.4025296982 |
| Directory | /workspace/155.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/156.uart_fifo_reset.3134457619 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 137071603335 ps |
| CPU time | 36 seconds |
| Started | Jun 04 12:41:45 PM PDT 24 |
| Finished | Jun 04 12:42:22 PM PDT 24 |
| Peak memory | 200160 kb |
| Host | smart-c89fa923-a989-4b30-a869-50b450ac08d3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3134457619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.3134457619 |
| Directory | /workspace/156.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/157.uart_fifo_reset.2736065057 |
| Short name | T1156 |
| Test name | |
| Test status | |
| Simulation time | 43002819088 ps |
| CPU time | 34.76 seconds |
| Started | Jun 04 12:41:42 PM PDT 24 |
| Finished | Jun 04 12:42:17 PM PDT 24 |
| Peak memory | 200196 kb |
| Host | smart-611258ca-f30c-4634-8ad5-d9fcf172e941 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2736065057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.2736065057 |
| Directory | /workspace/157.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/158.uart_fifo_reset.138982720 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 65439428363 ps |
| CPU time | 18.18 seconds |
| Started | Jun 04 12:41:43 PM PDT 24 |
| Finished | Jun 04 12:42:02 PM PDT 24 |
| Peak memory | 200144 kb |
| Host | smart-4708dbd6-5ed1-4770-801a-d8ea7e3c8af4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=138982720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.138982720 |
| Directory | /workspace/158.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/159.uart_fifo_reset.3626391768 |
| Short name | T1029 |
| Test name | |
| Test status | |
| Simulation time | 26838664188 ps |
| CPU time | 13.68 seconds |
| Started | Jun 04 12:41:42 PM PDT 24 |
| Finished | Jun 04 12:41:57 PM PDT 24 |
| Peak memory | 200208 kb |
| Host | smart-85b9507b-43d3-4965-a0c0-cfae98dd820d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3626391768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.3626391768 |
| Directory | /workspace/159.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/16.uart_alert_test.1730208100 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 13406543 ps |
| CPU time | 0.57 seconds |
| Started | Jun 04 12:38:02 PM PDT 24 |
| Finished | Jun 04 12:38:04 PM PDT 24 |
| Peak memory | 195600 kb |
| Host | smart-012b2c15-0b62-4850-a597-799ed1e26355 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730208100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.1730208100 |
| Directory | /workspace/16.uart_alert_test/latest |
| Test location | /workspace/coverage/default/16.uart_fifo_full.4191894011 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 141366299135 ps |
| CPU time | 144.68 seconds |
| Started | Jun 04 12:37:54 PM PDT 24 |
| Finished | Jun 04 12:40:19 PM PDT 24 |
| Peak memory | 200220 kb |
| Host | smart-14acf72e-f355-4b7e-a5d8-cfc95b2fb597 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4191894011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.4191894011 |
| Directory | /workspace/16.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/16.uart_fifo_overflow.4214255054 |
| Short name | T1055 |
| Test name | |
| Test status | |
| Simulation time | 109622023935 ps |
| CPU time | 184.1 seconds |
| Started | Jun 04 12:37:56 PM PDT 24 |
| Finished | Jun 04 12:41:01 PM PDT 24 |
| Peak memory | 200216 kb |
| Host | smart-efdeb095-7aa6-4614-bf03-377b40fcc8f1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4214255054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.4214255054 |
| Directory | /workspace/16.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/16.uart_fifo_reset.1630041558 |
| Short name | T1115 |
| Test name | |
| Test status | |
| Simulation time | 108069765452 ps |
| CPU time | 505.99 seconds |
| Started | Jun 04 12:38:07 PM PDT 24 |
| Finished | Jun 04 12:46:33 PM PDT 24 |
| Peak memory | 200156 kb |
| Host | smart-776c7024-7fa0-49ec-9836-595bb4730fdd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1630041558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.1630041558 |
| Directory | /workspace/16.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/16.uart_intr.1979071291 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 212931042669 ps |
| CPU time | 316.16 seconds |
| Started | Jun 04 12:38:08 PM PDT 24 |
| Finished | Jun 04 12:43:25 PM PDT 24 |
| Peak memory | 197268 kb |
| Host | smart-28f9b6c1-00ff-4da5-aab5-f7319c827ee8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979071291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.1979071291 |
| Directory | /workspace/16.uart_intr/latest |
| Test location | /workspace/coverage/default/16.uart_long_xfer_wo_dly.583990434 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 108529266815 ps |
| CPU time | 539.81 seconds |
| Started | Jun 04 12:38:04 PM PDT 24 |
| Finished | Jun 04 12:47:05 PM PDT 24 |
| Peak memory | 200220 kb |
| Host | smart-aee87b4a-d94c-426d-adb8-137acce0bedb |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=583990434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.583990434 |
| Directory | /workspace/16.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/16.uart_loopback.900934122 |
| Short name | T1142 |
| Test name | |
| Test status | |
| Simulation time | 6140681632 ps |
| CPU time | 5.65 seconds |
| Started | Jun 04 12:38:08 PM PDT 24 |
| Finished | Jun 04 12:38:14 PM PDT 24 |
| Peak memory | 200032 kb |
| Host | smart-f9d6ecb2-c2c2-4389-9154-3285af5d3533 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=900934122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_loopback.900934122 |
| Directory | /workspace/16.uart_loopback/latest |
| Test location | /workspace/coverage/default/16.uart_noise_filter.158025355 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 22839606174 ps |
| CPU time | 42.59 seconds |
| Started | Jun 04 12:38:05 PM PDT 24 |
| Finished | Jun 04 12:38:49 PM PDT 24 |
| Peak memory | 198280 kb |
| Host | smart-5ecf75c8-1840-4208-8dd2-052b4b780cc7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=158025355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_noise_filter.158025355 |
| Directory | /workspace/16.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/16.uart_perf.2808791943 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 4925777905 ps |
| CPU time | 70.17 seconds |
| Started | Jun 04 12:38:10 PM PDT 24 |
| Finished | Jun 04 12:39:21 PM PDT 24 |
| Peak memory | 200204 kb |
| Host | smart-d49f688a-9340-4a87-a6d3-97bcc9e96cc2 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2808791943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.2808791943 |
| Directory | /workspace/16.uart_perf/latest |
| Test location | /workspace/coverage/default/16.uart_rx_oversample.592687777 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 2019767549 ps |
| CPU time | 5.03 seconds |
| Started | Jun 04 12:38:02 PM PDT 24 |
| Finished | Jun 04 12:38:08 PM PDT 24 |
| Peak memory | 199416 kb |
| Host | smart-0082eb18-b40c-4c51-8bb2-3dcad62cd6d1 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=592687777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.592687777 |
| Directory | /workspace/16.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/16.uart_rx_parity_err.860613366 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 14514205911 ps |
| CPU time | 13.35 seconds |
| Started | Jun 04 12:38:06 PM PDT 24 |
| Finished | Jun 04 12:38:20 PM PDT 24 |
| Peak memory | 200000 kb |
| Host | smart-ba7ea633-fb44-415d-ab81-8f195f23f465 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=860613366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.860613366 |
| Directory | /workspace/16.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/16.uart_rx_start_bit_filter.2970239718 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 49113058354 ps |
| CPU time | 76.93 seconds |
| Started | Jun 04 12:38:08 PM PDT 24 |
| Finished | Jun 04 12:39:26 PM PDT 24 |
| Peak memory | 196192 kb |
| Host | smart-f9f8d571-41bc-4ef8-b87f-f58e74f438bd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2970239718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.2970239718 |
| Directory | /workspace/16.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/16.uart_smoke.591632759 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 638899221 ps |
| CPU time | 2.17 seconds |
| Started | Jun 04 12:37:57 PM PDT 24 |
| Finished | Jun 04 12:38:00 PM PDT 24 |
| Peak memory | 200084 kb |
| Host | smart-f1e7a3d7-46a7-465b-ab4c-ceb86666973f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=591632759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_smoke.591632759 |
| Directory | /workspace/16.uart_smoke/latest |
| Test location | /workspace/coverage/default/16.uart_stress_all_with_rand_reset.3668586024 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 85385491331 ps |
| CPU time | 877.4 seconds |
| Started | Jun 04 12:38:04 PM PDT 24 |
| Finished | Jun 04 12:52:43 PM PDT 24 |
| Peak memory | 215644 kb |
| Host | smart-3affb353-f8ea-4960-85be-305685cdd36f |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668586024 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 16.uart_stress_all_with_rand_reset.3668586024 |
| Directory | /workspace/16.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/16.uart_tx_ovrd.2320067635 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 7389401321 ps |
| CPU time | 9.64 seconds |
| Started | Jun 04 12:38:09 PM PDT 24 |
| Finished | Jun 04 12:38:19 PM PDT 24 |
| Peak memory | 199908 kb |
| Host | smart-c254912a-a02f-4496-a556-e0abc621ea75 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2320067635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.2320067635 |
| Directory | /workspace/16.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/16.uart_tx_rx.1698857713 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 9110438552 ps |
| CPU time | 5.78 seconds |
| Started | Jun 04 12:37:53 PM PDT 24 |
| Finished | Jun 04 12:37:59 PM PDT 24 |
| Peak memory | 200260 kb |
| Host | smart-1924730b-d914-4d2a-9b31-dee181c38903 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1698857713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.1698857713 |
| Directory | /workspace/16.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/160.uart_fifo_reset.3065042781 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 25176319789 ps |
| CPU time | 20.06 seconds |
| Started | Jun 04 12:41:42 PM PDT 24 |
| Finished | Jun 04 12:42:03 PM PDT 24 |
| Peak memory | 200224 kb |
| Host | smart-bc74e456-61ea-4976-9918-0cd809e97033 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3065042781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.3065042781 |
| Directory | /workspace/160.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/161.uart_fifo_reset.1683338523 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 123471053310 ps |
| CPU time | 64.09 seconds |
| Started | Jun 04 12:41:41 PM PDT 24 |
| Finished | Jun 04 12:42:45 PM PDT 24 |
| Peak memory | 200212 kb |
| Host | smart-c551cf1e-dd68-489d-845a-b4f584c3abf3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1683338523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.1683338523 |
| Directory | /workspace/161.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/162.uart_fifo_reset.4247486029 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 148094328334 ps |
| CPU time | 123.22 seconds |
| Started | Jun 04 12:41:51 PM PDT 24 |
| Finished | Jun 04 12:43:55 PM PDT 24 |
| Peak memory | 200196 kb |
| Host | smart-90ef43eb-2df1-40a3-b7a9-0b7d2cd5a32b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4247486029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.4247486029 |
| Directory | /workspace/162.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/163.uart_fifo_reset.520177022 |
| Short name | T1014 |
| Test name | |
| Test status | |
| Simulation time | 182209081761 ps |
| CPU time | 20.11 seconds |
| Started | Jun 04 12:41:53 PM PDT 24 |
| Finished | Jun 04 12:42:13 PM PDT 24 |
| Peak memory | 200004 kb |
| Host | smart-54e53358-fd18-4577-b135-85c045c5748d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=520177022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.520177022 |
| Directory | /workspace/163.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/164.uart_fifo_reset.695439569 |
| Short name | T1146 |
| Test name | |
| Test status | |
| Simulation time | 40098460137 ps |
| CPU time | 29.9 seconds |
| Started | Jun 04 12:41:55 PM PDT 24 |
| Finished | Jun 04 12:42:25 PM PDT 24 |
| Peak memory | 200312 kb |
| Host | smart-056ee43c-3d09-42cc-9227-0cfd11646b1f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=695439569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.695439569 |
| Directory | /workspace/164.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/167.uart_fifo_reset.2918875094 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 50308157189 ps |
| CPU time | 103.63 seconds |
| Started | Jun 04 12:41:52 PM PDT 24 |
| Finished | Jun 04 12:43:37 PM PDT 24 |
| Peak memory | 200260 kb |
| Host | smart-fadfc658-1b1c-486c-9d0a-682b06823216 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2918875094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.2918875094 |
| Directory | /workspace/167.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/168.uart_fifo_reset.406133547 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 9803196066 ps |
| CPU time | 20.69 seconds |
| Started | Jun 04 12:41:51 PM PDT 24 |
| Finished | Jun 04 12:42:12 PM PDT 24 |
| Peak memory | 200324 kb |
| Host | smart-31086140-5e1e-4bce-acd0-116b25e59bd3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=406133547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.406133547 |
| Directory | /workspace/168.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/169.uart_fifo_reset.2625889941 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 211248556587 ps |
| CPU time | 100.35 seconds |
| Started | Jun 04 12:41:52 PM PDT 24 |
| Finished | Jun 04 12:43:34 PM PDT 24 |
| Peak memory | 200196 kb |
| Host | smart-6d844efe-d48a-4926-83fc-c733024a1216 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2625889941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.2625889941 |
| Directory | /workspace/169.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/17.uart_alert_test.2909654281 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 12204922 ps |
| CPU time | 0.57 seconds |
| Started | Jun 04 12:38:04 PM PDT 24 |
| Finished | Jun 04 12:38:06 PM PDT 24 |
| Peak memory | 195568 kb |
| Host | smart-24060867-61cd-4e1f-9cca-d1dc9020f015 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909654281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.2909654281 |
| Directory | /workspace/17.uart_alert_test/latest |
| Test location | /workspace/coverage/default/17.uart_fifo_full.763889665 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 240054828354 ps |
| CPU time | 720.75 seconds |
| Started | Jun 04 12:38:04 PM PDT 24 |
| Finished | Jun 04 12:50:06 PM PDT 24 |
| Peak memory | 200172 kb |
| Host | smart-d5bbf9f3-40ea-447b-9782-1d58a7f89067 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=763889665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.763889665 |
| Directory | /workspace/17.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/17.uart_fifo_overflow.2718877329 |
| Short name | T976 |
| Test name | |
| Test status | |
| Simulation time | 8614395747 ps |
| CPU time | 16.36 seconds |
| Started | Jun 04 12:38:04 PM PDT 24 |
| Finished | Jun 04 12:38:21 PM PDT 24 |
| Peak memory | 200112 kb |
| Host | smart-f1a07bbc-5f2c-4682-bee8-9ffda3091be3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2718877329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.2718877329 |
| Directory | /workspace/17.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/17.uart_intr.887994045 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 301772472367 ps |
| CPU time | 39.28 seconds |
| Started | Jun 04 12:38:05 PM PDT 24 |
| Finished | Jun 04 12:38:45 PM PDT 24 |
| Peak memory | 199492 kb |
| Host | smart-896f5e2e-62d2-4660-9d32-8124b7136e16 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887994045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.887994045 |
| Directory | /workspace/17.uart_intr/latest |
| Test location | /workspace/coverage/default/17.uart_long_xfer_wo_dly.3696388429 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 115963384189 ps |
| CPU time | 268.77 seconds |
| Started | Jun 04 12:38:02 PM PDT 24 |
| Finished | Jun 04 12:42:32 PM PDT 24 |
| Peak memory | 200320 kb |
| Host | smart-ad8099fb-d315-4398-9784-94f1a5931f59 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3696388429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.3696388429 |
| Directory | /workspace/17.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/17.uart_loopback.2463205263 |
| Short name | T1160 |
| Test name | |
| Test status | |
| Simulation time | 7335584496 ps |
| CPU time | 5.59 seconds |
| Started | Jun 04 12:38:03 PM PDT 24 |
| Finished | Jun 04 12:38:09 PM PDT 24 |
| Peak memory | 199180 kb |
| Host | smart-de1a6ea5-4117-4fc3-9f69-e4bd30a3e6e8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2463205263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_loopback.2463205263 |
| Directory | /workspace/17.uart_loopback/latest |
| Test location | /workspace/coverage/default/17.uart_noise_filter.1412388717 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 590746565860 ps |
| CPU time | 91.52 seconds |
| Started | Jun 04 12:38:04 PM PDT 24 |
| Finished | Jun 04 12:39:36 PM PDT 24 |
| Peak memory | 208112 kb |
| Host | smart-731e7141-7404-4745-b76a-6744d287fec1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1412388717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_noise_filter.1412388717 |
| Directory | /workspace/17.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/17.uart_perf.2666902172 |
| Short name | T983 |
| Test name | |
| Test status | |
| Simulation time | 24056051414 ps |
| CPU time | 167.87 seconds |
| Started | Jun 04 12:38:08 PM PDT 24 |
| Finished | Jun 04 12:40:56 PM PDT 24 |
| Peak memory | 200176 kb |
| Host | smart-b88dd520-ec12-48df-b0ed-4f1de9f75dc1 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2666902172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.2666902172 |
| Directory | /workspace/17.uart_perf/latest |
| Test location | /workspace/coverage/default/17.uart_rx_oversample.2438568783 |
| Short name | T1010 |
| Test name | |
| Test status | |
| Simulation time | 4737892779 ps |
| CPU time | 10.59 seconds |
| Started | Jun 04 12:38:03 PM PDT 24 |
| Finished | Jun 04 12:38:14 PM PDT 24 |
| Peak memory | 199544 kb |
| Host | smart-f78fa26f-0f95-4200-8919-e96cc20856fc |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2438568783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.2438568783 |
| Directory | /workspace/17.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/17.uart_rx_parity_err.601017195 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 202325619365 ps |
| CPU time | 49.83 seconds |
| Started | Jun 04 12:38:06 PM PDT 24 |
| Finished | Jun 04 12:38:56 PM PDT 24 |
| Peak memory | 200156 kb |
| Host | smart-981ee94d-c726-41f4-bb92-10196be76320 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=601017195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.601017195 |
| Directory | /workspace/17.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/17.uart_rx_start_bit_filter.225135526 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 38724329661 ps |
| CPU time | 16.97 seconds |
| Started | Jun 04 12:38:04 PM PDT 24 |
| Finished | Jun 04 12:38:22 PM PDT 24 |
| Peak memory | 195908 kb |
| Host | smart-3a2838ca-098d-4d6a-82bc-d8494357c39d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=225135526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.225135526 |
| Directory | /workspace/17.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/17.uart_smoke.4208207263 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 690046029 ps |
| CPU time | 2.07 seconds |
| Started | Jun 04 12:38:04 PM PDT 24 |
| Finished | Jun 04 12:38:07 PM PDT 24 |
| Peak memory | 199740 kb |
| Host | smart-88a1377b-ca30-4e77-8694-1cb4dada7c42 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4208207263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_smoke.4208207263 |
| Directory | /workspace/17.uart_smoke/latest |
| Test location | /workspace/coverage/default/17.uart_stress_all.474540156 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 85861500638 ps |
| CPU time | 129.95 seconds |
| Started | Jun 04 12:38:06 PM PDT 24 |
| Finished | Jun 04 12:40:17 PM PDT 24 |
| Peak memory | 208652 kb |
| Host | smart-ed34adca-0bdb-4e5c-83b9-44d4bb5ad4fa |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474540156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.474540156 |
| Directory | /workspace/17.uart_stress_all/latest |
| Test location | /workspace/coverage/default/17.uart_stress_all_with_rand_reset.2958768805 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 107731879474 ps |
| CPU time | 501.4 seconds |
| Started | Jun 04 12:38:07 PM PDT 24 |
| Finished | Jun 04 12:46:29 PM PDT 24 |
| Peak memory | 216768 kb |
| Host | smart-a2706a09-ba89-4456-9697-4e93e36c2ba8 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958768805 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 17.uart_stress_all_with_rand_reset.2958768805 |
| Directory | /workspace/17.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/17.uart_tx_ovrd.1869352585 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 7941426348 ps |
| CPU time | 16.18 seconds |
| Started | Jun 04 12:38:04 PM PDT 24 |
| Finished | Jun 04 12:38:21 PM PDT 24 |
| Peak memory | 200092 kb |
| Host | smart-e0570646-424a-4914-a915-e0d82a4dc7ce |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1869352585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.1869352585 |
| Directory | /workspace/17.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/17.uart_tx_rx.2581303681 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 48474278511 ps |
| CPU time | 66.44 seconds |
| Started | Jun 04 12:38:06 PM PDT 24 |
| Finished | Jun 04 12:39:13 PM PDT 24 |
| Peak memory | 200188 kb |
| Host | smart-26e0583f-8c6c-4125-b8bd-0a8c19533a2f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2581303681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.2581303681 |
| Directory | /workspace/17.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/170.uart_fifo_reset.546408594 |
| Short name | T1001 |
| Test name | |
| Test status | |
| Simulation time | 42112308854 ps |
| CPU time | 21.99 seconds |
| Started | Jun 04 12:41:51 PM PDT 24 |
| Finished | Jun 04 12:42:13 PM PDT 24 |
| Peak memory | 200228 kb |
| Host | smart-f9ada833-3a00-4505-a9ed-11daff5035e9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=546408594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.546408594 |
| Directory | /workspace/170.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/171.uart_fifo_reset.91261171 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 16879699294 ps |
| CPU time | 26.84 seconds |
| Started | Jun 04 12:41:52 PM PDT 24 |
| Finished | Jun 04 12:42:20 PM PDT 24 |
| Peak memory | 200128 kb |
| Host | smart-f15b1c9d-db4a-46b5-93e6-b717c77fc373 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=91261171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.91261171 |
| Directory | /workspace/171.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/173.uart_fifo_reset.2963838320 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 102730349199 ps |
| CPU time | 176.94 seconds |
| Started | Jun 04 12:41:52 PM PDT 24 |
| Finished | Jun 04 12:44:50 PM PDT 24 |
| Peak memory | 200232 kb |
| Host | smart-80f3004e-ed66-4a55-a40b-9fa5eeccb3cb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2963838320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.2963838320 |
| Directory | /workspace/173.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/175.uart_fifo_reset.211546350 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 273799715419 ps |
| CPU time | 126.99 seconds |
| Started | Jun 04 12:41:53 PM PDT 24 |
| Finished | Jun 04 12:44:00 PM PDT 24 |
| Peak memory | 200380 kb |
| Host | smart-7b2df75f-afa5-488f-ac31-be8269f3b9b8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=211546350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.211546350 |
| Directory | /workspace/175.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/176.uart_fifo_reset.584411062 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 30836962999 ps |
| CPU time | 59.41 seconds |
| Started | Jun 04 12:41:52 PM PDT 24 |
| Finished | Jun 04 12:42:52 PM PDT 24 |
| Peak memory | 200176 kb |
| Host | smart-fdfaab70-c246-4d9b-bf21-d1541c68da17 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=584411062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.584411062 |
| Directory | /workspace/176.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/177.uart_fifo_reset.1491526450 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 33536488298 ps |
| CPU time | 54.76 seconds |
| Started | Jun 04 12:41:58 PM PDT 24 |
| Finished | Jun 04 12:42:53 PM PDT 24 |
| Peak memory | 200132 kb |
| Host | smart-dfeb13d2-e30e-4cad-9761-c0c06e7c5d2a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1491526450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.1491526450 |
| Directory | /workspace/177.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/178.uart_fifo_reset.2685435937 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 45298818506 ps |
| CPU time | 70.73 seconds |
| Started | Jun 04 12:41:51 PM PDT 24 |
| Finished | Jun 04 12:43:03 PM PDT 24 |
| Peak memory | 200192 kb |
| Host | smart-79a13141-6fed-4ea4-be28-892e841038e4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2685435937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.2685435937 |
| Directory | /workspace/178.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/179.uart_fifo_reset.3984760563 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 46832949149 ps |
| CPU time | 77.03 seconds |
| Started | Jun 04 12:41:54 PM PDT 24 |
| Finished | Jun 04 12:43:12 PM PDT 24 |
| Peak memory | 200348 kb |
| Host | smart-70acf95a-0fb1-456d-a874-11e4acef478b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3984760563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.3984760563 |
| Directory | /workspace/179.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/18.uart_alert_test.1738325320 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 20218408 ps |
| CPU time | 0.6 seconds |
| Started | Jun 04 12:38:14 PM PDT 24 |
| Finished | Jun 04 12:38:15 PM PDT 24 |
| Peak memory | 195556 kb |
| Host | smart-63806686-abb3-43bc-8ce0-b062039e2b88 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738325320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.1738325320 |
| Directory | /workspace/18.uart_alert_test/latest |
| Test location | /workspace/coverage/default/18.uart_fifo_full.2466078758 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 58246326507 ps |
| CPU time | 70.9 seconds |
| Started | Jun 04 12:38:13 PM PDT 24 |
| Finished | Jun 04 12:39:25 PM PDT 24 |
| Peak memory | 200504 kb |
| Host | smart-faa282c9-8042-40ac-873b-68f760f99233 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2466078758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.2466078758 |
| Directory | /workspace/18.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/18.uart_fifo_overflow.1525783654 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 155937113831 ps |
| CPU time | 248.97 seconds |
| Started | Jun 04 12:38:15 PM PDT 24 |
| Finished | Jun 04 12:42:25 PM PDT 24 |
| Peak memory | 200164 kb |
| Host | smart-439c06f3-66df-491d-8d44-855c0a5b2da3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1525783654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.1525783654 |
| Directory | /workspace/18.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/18.uart_fifo_reset.1806800831 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 14674782741 ps |
| CPU time | 26.82 seconds |
| Started | Jun 04 12:38:12 PM PDT 24 |
| Finished | Jun 04 12:38:40 PM PDT 24 |
| Peak memory | 200256 kb |
| Host | smart-e2e44a61-b42d-4131-8903-255e943da98c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1806800831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.1806800831 |
| Directory | /workspace/18.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/18.uart_intr.3097807807 |
| Short name | T1138 |
| Test name | |
| Test status | |
| Simulation time | 153348008952 ps |
| CPU time | 228.01 seconds |
| Started | Jun 04 12:38:14 PM PDT 24 |
| Finished | Jun 04 12:42:03 PM PDT 24 |
| Peak memory | 196840 kb |
| Host | smart-695f52bd-a126-4826-8d58-8b7670b6bcd6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097807807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.3097807807 |
| Directory | /workspace/18.uart_intr/latest |
| Test location | /workspace/coverage/default/18.uart_long_xfer_wo_dly.3328254496 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 59112900344 ps |
| CPU time | 227.11 seconds |
| Started | Jun 04 12:38:12 PM PDT 24 |
| Finished | Jun 04 12:42:00 PM PDT 24 |
| Peak memory | 200204 kb |
| Host | smart-fae77bed-32ad-4014-bf81-1a468f13fee3 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3328254496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.3328254496 |
| Directory | /workspace/18.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/18.uart_loopback.2463275455 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 1980752014 ps |
| CPU time | 1.47 seconds |
| Started | Jun 04 12:38:16 PM PDT 24 |
| Finished | Jun 04 12:38:18 PM PDT 24 |
| Peak memory | 197656 kb |
| Host | smart-4e33960e-ee34-4e13-8f3c-9c386af519d5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2463275455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_loopback.2463275455 |
| Directory | /workspace/18.uart_loopback/latest |
| Test location | /workspace/coverage/default/18.uart_noise_filter.1892249598 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 180916308523 ps |
| CPU time | 98.16 seconds |
| Started | Jun 04 12:38:16 PM PDT 24 |
| Finished | Jun 04 12:39:55 PM PDT 24 |
| Peak memory | 200340 kb |
| Host | smart-af5a1730-01ea-47ac-9757-49f4d9af767e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1892249598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_noise_filter.1892249598 |
| Directory | /workspace/18.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/18.uart_perf.3785322496 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 17799014307 ps |
| CPU time | 473.83 seconds |
| Started | Jun 04 12:38:13 PM PDT 24 |
| Finished | Jun 04 12:46:08 PM PDT 24 |
| Peak memory | 200232 kb |
| Host | smart-2bc3d2b8-1615-45aa-aa2e-9f4afc1b6be0 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3785322496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.3785322496 |
| Directory | /workspace/18.uart_perf/latest |
| Test location | /workspace/coverage/default/18.uart_rx_oversample.4073728755 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 5470677233 ps |
| CPU time | 50.02 seconds |
| Started | Jun 04 12:38:16 PM PDT 24 |
| Finished | Jun 04 12:39:07 PM PDT 24 |
| Peak memory | 199460 kb |
| Host | smart-aad9616f-c8b9-4825-b008-8772bcd9d79c |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4073728755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.4073728755 |
| Directory | /workspace/18.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/18.uart_rx_parity_err.2554312361 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 40677098513 ps |
| CPU time | 37.05 seconds |
| Started | Jun 04 12:38:14 PM PDT 24 |
| Finished | Jun 04 12:38:53 PM PDT 24 |
| Peak memory | 200320 kb |
| Host | smart-0428939c-f383-4432-93b7-e6d7b777a2a7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2554312361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.2554312361 |
| Directory | /workspace/18.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/18.uart_rx_start_bit_filter.2509847766 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 3821706129 ps |
| CPU time | 6.76 seconds |
| Started | Jun 04 12:38:14 PM PDT 24 |
| Finished | Jun 04 12:38:22 PM PDT 24 |
| Peak memory | 196516 kb |
| Host | smart-de02b84a-697c-4e73-b95a-12151c996582 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2509847766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.2509847766 |
| Directory | /workspace/18.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/18.uart_smoke.3192825373 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 428588120 ps |
| CPU time | 3.45 seconds |
| Started | Jun 04 12:38:04 PM PDT 24 |
| Finished | Jun 04 12:38:08 PM PDT 24 |
| Peak memory | 200192 kb |
| Host | smart-f91de91e-c624-4988-8a2f-83777e0fef88 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3192825373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_smoke.3192825373 |
| Directory | /workspace/18.uart_smoke/latest |
| Test location | /workspace/coverage/default/18.uart_stress_all.744363010 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 489343293522 ps |
| CPU time | 429.73 seconds |
| Started | Jun 04 12:38:12 PM PDT 24 |
| Finished | Jun 04 12:45:22 PM PDT 24 |
| Peak memory | 200180 kb |
| Host | smart-24f8e9a0-8bda-45ce-9b77-569cabda29b2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744363010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.744363010 |
| Directory | /workspace/18.uart_stress_all/latest |
| Test location | /workspace/coverage/default/18.uart_tx_ovrd.1756268380 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 892590016 ps |
| CPU time | 3.14 seconds |
| Started | Jun 04 12:38:15 PM PDT 24 |
| Finished | Jun 04 12:38:20 PM PDT 24 |
| Peak memory | 198824 kb |
| Host | smart-a6f2b4c1-9e76-45a5-8cdc-e913fb637aa7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1756268380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.1756268380 |
| Directory | /workspace/18.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/18.uart_tx_rx.2002239613 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 9739185187 ps |
| CPU time | 15.87 seconds |
| Started | Jun 04 12:38:14 PM PDT 24 |
| Finished | Jun 04 12:38:31 PM PDT 24 |
| Peak memory | 196888 kb |
| Host | smart-e6d9b073-3a4d-45e1-a51b-e7f84734d3f5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2002239613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.2002239613 |
| Directory | /workspace/18.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/180.uart_fifo_reset.3028353376 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 81672160771 ps |
| CPU time | 36.87 seconds |
| Started | Jun 04 12:42:01 PM PDT 24 |
| Finished | Jun 04 12:42:39 PM PDT 24 |
| Peak memory | 200260 kb |
| Host | smart-43282a4e-f2b1-4fba-9bd7-3bf8d8f4f234 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3028353376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.3028353376 |
| Directory | /workspace/180.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/181.uart_fifo_reset.2147519993 |
| Short name | T1133 |
| Test name | |
| Test status | |
| Simulation time | 65048168396 ps |
| CPU time | 16.02 seconds |
| Started | Jun 04 12:42:01 PM PDT 24 |
| Finished | Jun 04 12:42:18 PM PDT 24 |
| Peak memory | 200256 kb |
| Host | smart-3c668f52-732f-435b-8642-6f371dbe7f24 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2147519993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.2147519993 |
| Directory | /workspace/181.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/182.uart_fifo_reset.3621499513 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 82189751084 ps |
| CPU time | 141.21 seconds |
| Started | Jun 04 12:42:02 PM PDT 24 |
| Finished | Jun 04 12:44:24 PM PDT 24 |
| Peak memory | 200168 kb |
| Host | smart-a4439d50-df9a-4993-aced-f8428ec9f70d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3621499513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.3621499513 |
| Directory | /workspace/182.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/183.uart_fifo_reset.3974690982 |
| Short name | T1137 |
| Test name | |
| Test status | |
| Simulation time | 7028338165 ps |
| CPU time | 7.16 seconds |
| Started | Jun 04 12:42:01 PM PDT 24 |
| Finished | Jun 04 12:42:09 PM PDT 24 |
| Peak memory | 199936 kb |
| Host | smart-d1c14514-6551-46b3-a56b-0ccfeee4f863 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3974690982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.3974690982 |
| Directory | /workspace/183.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/184.uart_fifo_reset.3823288228 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 166804122711 ps |
| CPU time | 69.43 seconds |
| Started | Jun 04 12:42:01 PM PDT 24 |
| Finished | Jun 04 12:43:11 PM PDT 24 |
| Peak memory | 200200 kb |
| Host | smart-15da5226-f287-448f-8b0f-f6f223a4ebb4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3823288228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.3823288228 |
| Directory | /workspace/184.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/185.uart_fifo_reset.1985391775 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 58864092167 ps |
| CPU time | 26.26 seconds |
| Started | Jun 04 12:42:03 PM PDT 24 |
| Finished | Jun 04 12:42:30 PM PDT 24 |
| Peak memory | 200168 kb |
| Host | smart-ccf0a3ce-7a20-4499-ac0a-f37cef4e7265 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1985391775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.1985391775 |
| Directory | /workspace/185.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/186.uart_fifo_reset.3668217233 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 210586246123 ps |
| CPU time | 126.24 seconds |
| Started | Jun 04 12:42:01 PM PDT 24 |
| Finished | Jun 04 12:44:09 PM PDT 24 |
| Peak memory | 200188 kb |
| Host | smart-4d04719c-185a-44a6-abb4-35b6f6af11c2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3668217233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.3668217233 |
| Directory | /workspace/186.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/187.uart_fifo_reset.1802009620 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 70616567908 ps |
| CPU time | 41.64 seconds |
| Started | Jun 04 12:42:00 PM PDT 24 |
| Finished | Jun 04 12:42:42 PM PDT 24 |
| Peak memory | 200328 kb |
| Host | smart-725eba24-bf09-430e-afb9-2b683cb03faa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1802009620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.1802009620 |
| Directory | /workspace/187.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/188.uart_fifo_reset.2933859642 |
| Short name | T1000 |
| Test name | |
| Test status | |
| Simulation time | 14829927344 ps |
| CPU time | 35.09 seconds |
| Started | Jun 04 12:42:02 PM PDT 24 |
| Finished | Jun 04 12:42:38 PM PDT 24 |
| Peak memory | 200332 kb |
| Host | smart-662c0ff8-f792-40ce-abc8-56baa06a8a2a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2933859642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.2933859642 |
| Directory | /workspace/188.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/189.uart_fifo_reset.4267949734 |
| Short name | T1028 |
| Test name | |
| Test status | |
| Simulation time | 33555555170 ps |
| CPU time | 54.5 seconds |
| Started | Jun 04 12:42:02 PM PDT 24 |
| Finished | Jun 04 12:42:57 PM PDT 24 |
| Peak memory | 200292 kb |
| Host | smart-a7418de5-2a07-464b-8e5b-b14f22baae7f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4267949734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.4267949734 |
| Directory | /workspace/189.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/19.uart_alert_test.3165789617 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 15711605 ps |
| CPU time | 0.57 seconds |
| Started | Jun 04 12:38:23 PM PDT 24 |
| Finished | Jun 04 12:38:25 PM PDT 24 |
| Peak memory | 195624 kb |
| Host | smart-e2606211-19ad-46f4-b0a7-2fdeee08c543 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165789617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.3165789617 |
| Directory | /workspace/19.uart_alert_test/latest |
| Test location | /workspace/coverage/default/19.uart_fifo_full.1581294385 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 24787709714 ps |
| CPU time | 13.47 seconds |
| Started | Jun 04 12:38:13 PM PDT 24 |
| Finished | Jun 04 12:38:27 PM PDT 24 |
| Peak memory | 200184 kb |
| Host | smart-89304924-6b7a-425f-879b-3e31408de550 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1581294385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.1581294385 |
| Directory | /workspace/19.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/19.uart_fifo_overflow.3230338074 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 20559037498 ps |
| CPU time | 33.11 seconds |
| Started | Jun 04 12:38:16 PM PDT 24 |
| Finished | Jun 04 12:38:51 PM PDT 24 |
| Peak memory | 198000 kb |
| Host | smart-4c132dc1-7dc4-420d-a69c-412ff4efb7e5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3230338074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.3230338074 |
| Directory | /workspace/19.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/19.uart_fifo_reset.3460674095 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 16087625724 ps |
| CPU time | 31.58 seconds |
| Started | Jun 04 12:38:14 PM PDT 24 |
| Finished | Jun 04 12:38:47 PM PDT 24 |
| Peak memory | 200100 kb |
| Host | smart-9390867a-fdbf-4152-8b18-b0d8d87e5f5f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3460674095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.3460674095 |
| Directory | /workspace/19.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/19.uart_intr.2744062823 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 75115433146 ps |
| CPU time | 165.13 seconds |
| Started | Jun 04 12:38:13 PM PDT 24 |
| Finished | Jun 04 12:41:00 PM PDT 24 |
| Peak memory | 199412 kb |
| Host | smart-910bdc35-6124-4218-b3fb-132ebe186025 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744062823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.2744062823 |
| Directory | /workspace/19.uart_intr/latest |
| Test location | /workspace/coverage/default/19.uart_long_xfer_wo_dly.3994318481 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 122335850717 ps |
| CPU time | 563.39 seconds |
| Started | Jun 04 12:38:15 PM PDT 24 |
| Finished | Jun 04 12:47:40 PM PDT 24 |
| Peak memory | 200320 kb |
| Host | smart-2e355f00-3655-4692-a221-3793adae7bbb |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3994318481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.3994318481 |
| Directory | /workspace/19.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/19.uart_loopback.3052088736 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 7908039710 ps |
| CPU time | 14.17 seconds |
| Started | Jun 04 12:38:13 PM PDT 24 |
| Finished | Jun 04 12:38:29 PM PDT 24 |
| Peak memory | 200132 kb |
| Host | smart-8e7044ff-4e66-42fa-b33a-26810fa84fcb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3052088736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_loopback.3052088736 |
| Directory | /workspace/19.uart_loopback/latest |
| Test location | /workspace/coverage/default/19.uart_noise_filter.461419341 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 150110118323 ps |
| CPU time | 125.67 seconds |
| Started | Jun 04 12:38:16 PM PDT 24 |
| Finished | Jun 04 12:40:23 PM PDT 24 |
| Peak memory | 200452 kb |
| Host | smart-5806d230-8f0a-4fa4-a52a-53ba82d1cafc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=461419341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_noise_filter.461419341 |
| Directory | /workspace/19.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/19.uart_perf.3116707830 |
| Short name | T1170 |
| Test name | |
| Test status | |
| Simulation time | 25143177673 ps |
| CPU time | 361.66 seconds |
| Started | Jun 04 12:38:16 PM PDT 24 |
| Finished | Jun 04 12:44:19 PM PDT 24 |
| Peak memory | 200176 kb |
| Host | smart-ab7d9d08-e977-4eb3-a36f-0c9c23398c59 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3116707830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.3116707830 |
| Directory | /workspace/19.uart_perf/latest |
| Test location | /workspace/coverage/default/19.uart_rx_oversample.558491700 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 5355348152 ps |
| CPU time | 41.61 seconds |
| Started | Jun 04 12:38:13 PM PDT 24 |
| Finished | Jun 04 12:38:55 PM PDT 24 |
| Peak memory | 198924 kb |
| Host | smart-6052fb9f-0fcd-417e-b69a-aa72a84bda70 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=558491700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.558491700 |
| Directory | /workspace/19.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/19.uart_rx_parity_err.1934775229 |
| Short name | T1178 |
| Test name | |
| Test status | |
| Simulation time | 111514027667 ps |
| CPU time | 77.86 seconds |
| Started | Jun 04 12:38:13 PM PDT 24 |
| Finished | Jun 04 12:39:31 PM PDT 24 |
| Peak memory | 200136 kb |
| Host | smart-e1fd4f7d-c5cb-41b1-8f0c-d4259b18ab55 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1934775229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.1934775229 |
| Directory | /workspace/19.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/19.uart_rx_start_bit_filter.607129301 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 44376122564 ps |
| CPU time | 15.95 seconds |
| Started | Jun 04 12:38:14 PM PDT 24 |
| Finished | Jun 04 12:38:31 PM PDT 24 |
| Peak memory | 195920 kb |
| Host | smart-711f3a88-af81-458c-b42f-ced555d5caf5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=607129301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.607129301 |
| Directory | /workspace/19.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/19.uart_smoke.582659625 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 696364888 ps |
| CPU time | 1.24 seconds |
| Started | Jun 04 12:38:14 PM PDT 24 |
| Finished | Jun 04 12:38:16 PM PDT 24 |
| Peak memory | 198652 kb |
| Host | smart-52e0e2ef-7c04-4384-a856-d855fe8d18a2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=582659625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_smoke.582659625 |
| Directory | /workspace/19.uart_smoke/latest |
| Test location | /workspace/coverage/default/19.uart_stress_all.3729511438 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 73576175641 ps |
| CPU time | 139.36 seconds |
| Started | Jun 04 12:38:15 PM PDT 24 |
| Finished | Jun 04 12:40:35 PM PDT 24 |
| Peak memory | 200144 kb |
| Host | smart-bbaaa34a-3926-46e6-817b-872283f47fce |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729511438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.3729511438 |
| Directory | /workspace/19.uart_stress_all/latest |
| Test location | /workspace/coverage/default/19.uart_stress_all_with_rand_reset.210117967 |
| Short name | T1165 |
| Test name | |
| Test status | |
| Simulation time | 97903887858 ps |
| CPU time | 553.57 seconds |
| Started | Jun 04 12:38:12 PM PDT 24 |
| Finished | Jun 04 12:47:27 PM PDT 24 |
| Peak memory | 216556 kb |
| Host | smart-d022ecde-7089-433e-8c75-ec638ad6ff8f |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210117967 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 19.uart_stress_all_with_rand_reset.210117967 |
| Directory | /workspace/19.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/19.uart_tx_ovrd.4036011327 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 6614896844 ps |
| CPU time | 20.65 seconds |
| Started | Jun 04 12:38:13 PM PDT 24 |
| Finished | Jun 04 12:38:35 PM PDT 24 |
| Peak memory | 200128 kb |
| Host | smart-c70a9d4a-52d4-42ab-9fd1-4c6bf4bf3206 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4036011327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.4036011327 |
| Directory | /workspace/19.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/19.uart_tx_rx.4156443434 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 23910689877 ps |
| CPU time | 41.63 seconds |
| Started | Jun 04 12:38:14 PM PDT 24 |
| Finished | Jun 04 12:38:56 PM PDT 24 |
| Peak memory | 200224 kb |
| Host | smart-199fe5a2-d198-4dbc-9a28-273f242b32af |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4156443434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.4156443434 |
| Directory | /workspace/19.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/190.uart_fifo_reset.1099275385 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 83837216088 ps |
| CPU time | 90.37 seconds |
| Started | Jun 04 12:42:12 PM PDT 24 |
| Finished | Jun 04 12:43:45 PM PDT 24 |
| Peak memory | 200140 kb |
| Host | smart-66e307f6-0054-4b9a-8108-4d0d81a9d3dd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1099275385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.1099275385 |
| Directory | /workspace/190.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/191.uart_fifo_reset.660660293 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 25320539052 ps |
| CPU time | 7.42 seconds |
| Started | Jun 04 12:42:10 PM PDT 24 |
| Finished | Jun 04 12:42:18 PM PDT 24 |
| Peak memory | 200292 kb |
| Host | smart-8943df06-ea42-4147-b586-e5e22db5c92a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=660660293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.660660293 |
| Directory | /workspace/191.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/192.uart_fifo_reset.288374310 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 29949646120 ps |
| CPU time | 32.99 seconds |
| Started | Jun 04 12:42:13 PM PDT 24 |
| Finished | Jun 04 12:42:47 PM PDT 24 |
| Peak memory | 200540 kb |
| Host | smart-ab47c416-7e0d-44e6-b106-a682eebcc58b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=288374310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.288374310 |
| Directory | /workspace/192.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/194.uart_fifo_reset.976038861 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 67860005482 ps |
| CPU time | 32.78 seconds |
| Started | Jun 04 12:42:14 PM PDT 24 |
| Finished | Jun 04 12:42:48 PM PDT 24 |
| Peak memory | 200312 kb |
| Host | smart-4988be3e-6325-476c-ba02-b4a1aac938f5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=976038861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.976038861 |
| Directory | /workspace/194.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/195.uart_fifo_reset.2885618607 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 123091027285 ps |
| CPU time | 58.8 seconds |
| Started | Jun 04 12:42:11 PM PDT 24 |
| Finished | Jun 04 12:43:12 PM PDT 24 |
| Peak memory | 200132 kb |
| Host | smart-074d818e-d2cf-4780-b1a1-ac7ecbea42bf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2885618607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.2885618607 |
| Directory | /workspace/195.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/197.uart_fifo_reset.2288976493 |
| Short name | T1162 |
| Test name | |
| Test status | |
| Simulation time | 36637871472 ps |
| CPU time | 44.04 seconds |
| Started | Jun 04 12:42:10 PM PDT 24 |
| Finished | Jun 04 12:42:55 PM PDT 24 |
| Peak memory | 200156 kb |
| Host | smart-42cd5288-7500-4611-8c72-a197f73bdfa6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2288976493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.2288976493 |
| Directory | /workspace/197.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/198.uart_fifo_reset.1657412046 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 85390361695 ps |
| CPU time | 79.68 seconds |
| Started | Jun 04 12:42:11 PM PDT 24 |
| Finished | Jun 04 12:43:32 PM PDT 24 |
| Peak memory | 200256 kb |
| Host | smart-f44c5f6a-8af4-4e3b-980b-65700b176991 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1657412046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.1657412046 |
| Directory | /workspace/198.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/199.uart_fifo_reset.2753153688 |
| Short name | T1118 |
| Test name | |
| Test status | |
| Simulation time | 115167573903 ps |
| CPU time | 122.13 seconds |
| Started | Jun 04 12:42:11 PM PDT 24 |
| Finished | Jun 04 12:44:15 PM PDT 24 |
| Peak memory | 200308 kb |
| Host | smart-a68e2318-5003-4de6-bfdb-2bd6bd076d8c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2753153688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.2753153688 |
| Directory | /workspace/199.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/2.uart_alert_test.1728607864 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 34258469 ps |
| CPU time | 0.62 seconds |
| Started | Jun 04 12:36:51 PM PDT 24 |
| Finished | Jun 04 12:36:53 PM PDT 24 |
| Peak memory | 195600 kb |
| Host | smart-0e7e3500-6c5d-4435-991a-4d5f821c3928 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728607864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.1728607864 |
| Directory | /workspace/2.uart_alert_test/latest |
| Test location | /workspace/coverage/default/2.uart_fifo_full.745803458 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 74097015094 ps |
| CPU time | 42.33 seconds |
| Started | Jun 04 12:36:40 PM PDT 24 |
| Finished | Jun 04 12:37:24 PM PDT 24 |
| Peak memory | 200164 kb |
| Host | smart-65dd192d-4bc7-4bb9-b223-bbb282a89ded |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=745803458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.745803458 |
| Directory | /workspace/2.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/2.uart_fifo_overflow.3083920494 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 135891761438 ps |
| CPU time | 218.75 seconds |
| Started | Jun 04 12:36:38 PM PDT 24 |
| Finished | Jun 04 12:40:17 PM PDT 24 |
| Peak memory | 200220 kb |
| Host | smart-b432bcc4-321c-4277-99cd-793bd7fb0679 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3083920494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.3083920494 |
| Directory | /workspace/2.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/2.uart_fifo_reset.3904429025 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 8387979326 ps |
| CPU time | 6.53 seconds |
| Started | Jun 04 12:36:42 PM PDT 24 |
| Finished | Jun 04 12:36:50 PM PDT 24 |
| Peak memory | 199980 kb |
| Host | smart-b91a0f4f-4f2c-4ec6-9da2-9a49b6609959 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3904429025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.3904429025 |
| Directory | /workspace/2.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/2.uart_intr.3439313327 |
| Short name | T975 |
| Test name | |
| Test status | |
| Simulation time | 132872829943 ps |
| CPU time | 104.72 seconds |
| Started | Jun 04 12:36:47 PM PDT 24 |
| Finished | Jun 04 12:38:32 PM PDT 24 |
| Peak memory | 200120 kb |
| Host | smart-8b7639dc-e372-4fba-818a-8416ab3d8d2a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439313327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.3439313327 |
| Directory | /workspace/2.uart_intr/latest |
| Test location | /workspace/coverage/default/2.uart_long_xfer_wo_dly.2730093031 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 179896841032 ps |
| CPU time | 1293.02 seconds |
| Started | Jun 04 12:36:51 PM PDT 24 |
| Finished | Jun 04 12:58:26 PM PDT 24 |
| Peak memory | 200332 kb |
| Host | smart-875d5c42-920d-40d2-ab5e-11dfc9f73da7 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2730093031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.2730093031 |
| Directory | /workspace/2.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/2.uart_loopback.1759245184 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 9604255393 ps |
| CPU time | 5.85 seconds |
| Started | Jun 04 12:36:41 PM PDT 24 |
| Finished | Jun 04 12:36:48 PM PDT 24 |
| Peak memory | 198936 kb |
| Host | smart-d3926962-a284-46e9-987e-89b6000be0f6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1759245184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_loopback.1759245184 |
| Directory | /workspace/2.uart_loopback/latest |
| Test location | /workspace/coverage/default/2.uart_noise_filter.1695496883 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 43084602627 ps |
| CPU time | 20.13 seconds |
| Started | Jun 04 12:36:40 PM PDT 24 |
| Finished | Jun 04 12:37:01 PM PDT 24 |
| Peak memory | 200348 kb |
| Host | smart-23b0295c-b0af-4b10-9c00-714a97a87765 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1695496883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_noise_filter.1695496883 |
| Directory | /workspace/2.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/2.uart_perf.1642617457 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 7784919905 ps |
| CPU time | 105.21 seconds |
| Started | Jun 04 12:36:52 PM PDT 24 |
| Finished | Jun 04 12:38:39 PM PDT 24 |
| Peak memory | 200220 kb |
| Host | smart-2620f4d3-51db-46b8-aff0-9d4130870b35 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1642617457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.1642617457 |
| Directory | /workspace/2.uart_perf/latest |
| Test location | /workspace/coverage/default/2.uart_rx_oversample.2200469050 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 2696393590 ps |
| CPU time | 17.17 seconds |
| Started | Jun 04 12:36:38 PM PDT 24 |
| Finished | Jun 04 12:36:56 PM PDT 24 |
| Peak memory | 199048 kb |
| Host | smart-5dc1c352-9189-4001-a00d-5f9c7665e17f |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2200469050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.2200469050 |
| Directory | /workspace/2.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/2.uart_rx_parity_err.4001342521 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 106806795750 ps |
| CPU time | 150.07 seconds |
| Started | Jun 04 12:36:44 PM PDT 24 |
| Finished | Jun 04 12:39:15 PM PDT 24 |
| Peak memory | 200200 kb |
| Host | smart-91dda93c-43af-491e-bc3e-15fc3d85e104 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4001342521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.4001342521 |
| Directory | /workspace/2.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/2.uart_rx_start_bit_filter.2953860387 |
| Short name | T958 |
| Test name | |
| Test status | |
| Simulation time | 38801385259 ps |
| CPU time | 68.11 seconds |
| Started | Jun 04 12:36:38 PM PDT 24 |
| Finished | Jun 04 12:37:47 PM PDT 24 |
| Peak memory | 196000 kb |
| Host | smart-d90fef16-d14b-41c4-be74-63246968a520 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2953860387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.2953860387 |
| Directory | /workspace/2.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/2.uart_smoke.3500626981 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 6298205623 ps |
| CPU time | 6.49 seconds |
| Started | Jun 04 12:36:38 PM PDT 24 |
| Finished | Jun 04 12:36:46 PM PDT 24 |
| Peak memory | 199820 kb |
| Host | smart-723196d4-dc0b-4574-b052-de6d22721a64 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3500626981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_smoke.3500626981 |
| Directory | /workspace/2.uart_smoke/latest |
| Test location | /workspace/coverage/default/2.uart_stress_all.3529457297 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 563690701330 ps |
| CPU time | 80.92 seconds |
| Started | Jun 04 12:36:54 PM PDT 24 |
| Finished | Jun 04 12:38:16 PM PDT 24 |
| Peak memory | 200240 kb |
| Host | smart-b65201d1-a4e4-4b87-a644-3d8e913bef94 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529457297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.3529457297 |
| Directory | /workspace/2.uart_stress_all/latest |
| Test location | /workspace/coverage/default/2.uart_stress_all_with_rand_reset.2603372546 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 17812519626 ps |
| CPU time | 207.2 seconds |
| Started | Jun 04 12:36:51 PM PDT 24 |
| Finished | Jun 04 12:40:20 PM PDT 24 |
| Peak memory | 216844 kb |
| Host | smart-6de1dbd1-be9d-4ee4-84bb-fdbb7d96721c |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603372546 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 2.uart_stress_all_with_rand_reset.2603372546 |
| Directory | /workspace/2.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/2.uart_tx_ovrd.2297450609 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 1098179865 ps |
| CPU time | 3.98 seconds |
| Started | Jun 04 12:36:38 PM PDT 24 |
| Finished | Jun 04 12:36:42 PM PDT 24 |
| Peak memory | 198572 kb |
| Host | smart-eab511e4-e5ee-4fa2-9acd-a9a296d1601f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2297450609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.2297450609 |
| Directory | /workspace/2.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/20.uart_alert_test.1402552493 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 45805761 ps |
| CPU time | 0.61 seconds |
| Started | Jun 04 12:38:22 PM PDT 24 |
| Finished | Jun 04 12:38:24 PM PDT 24 |
| Peak memory | 195620 kb |
| Host | smart-c31768fc-6c4c-4f44-b544-0f7703bdd8fe |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402552493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.1402552493 |
| Directory | /workspace/20.uart_alert_test/latest |
| Test location | /workspace/coverage/default/20.uart_fifo_full.4156377200 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 7562558827 ps |
| CPU time | 12.42 seconds |
| Started | Jun 04 12:38:22 PM PDT 24 |
| Finished | Jun 04 12:38:35 PM PDT 24 |
| Peak memory | 200136 kb |
| Host | smart-d368d80c-9976-4781-959d-2244881051c0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4156377200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.4156377200 |
| Directory | /workspace/20.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/20.uart_fifo_overflow.2909589300 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 89673318372 ps |
| CPU time | 45.06 seconds |
| Started | Jun 04 12:38:24 PM PDT 24 |
| Finished | Jun 04 12:39:10 PM PDT 24 |
| Peak memory | 200176 kb |
| Host | smart-08838f90-8230-4717-b80a-f737ea135ed1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2909589300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.2909589300 |
| Directory | /workspace/20.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/20.uart_fifo_reset.3779688165 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 26881168935 ps |
| CPU time | 24.32 seconds |
| Started | Jun 04 12:38:22 PM PDT 24 |
| Finished | Jun 04 12:38:48 PM PDT 24 |
| Peak memory | 200192 kb |
| Host | smart-75e23d22-2e98-47c5-a52a-392a23a56ce3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3779688165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.3779688165 |
| Directory | /workspace/20.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/20.uart_intr.931804627 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 67142880511 ps |
| CPU time | 100.45 seconds |
| Started | Jun 04 12:38:23 PM PDT 24 |
| Finished | Jun 04 12:40:05 PM PDT 24 |
| Peak memory | 200136 kb |
| Host | smart-f00fdb1f-f95c-40b6-b742-c79da012bdca |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931804627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.931804627 |
| Directory | /workspace/20.uart_intr/latest |
| Test location | /workspace/coverage/default/20.uart_long_xfer_wo_dly.553913154 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 123461793823 ps |
| CPU time | 249.8 seconds |
| Started | Jun 04 12:38:32 PM PDT 24 |
| Finished | Jun 04 12:42:43 PM PDT 24 |
| Peak memory | 200068 kb |
| Host | smart-45ab043f-1e48-4d89-8bce-d3330b3ab164 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=553913154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.553913154 |
| Directory | /workspace/20.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/20.uart_loopback.3967246391 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 1408611270 ps |
| CPU time | 2.91 seconds |
| Started | Jun 04 12:38:22 PM PDT 24 |
| Finished | Jun 04 12:38:26 PM PDT 24 |
| Peak memory | 196112 kb |
| Host | smart-f1254020-58b1-4200-a259-dc648eff35a3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3967246391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_loopback.3967246391 |
| Directory | /workspace/20.uart_loopback/latest |
| Test location | /workspace/coverage/default/20.uart_noise_filter.4086585212 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 124046772974 ps |
| CPU time | 64.91 seconds |
| Started | Jun 04 12:38:32 PM PDT 24 |
| Finished | Jun 04 12:39:38 PM PDT 24 |
| Peak memory | 208608 kb |
| Host | smart-054718b5-f5d4-43ea-a45a-3c175484604a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4086585212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_noise_filter.4086585212 |
| Directory | /workspace/20.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/20.uart_perf.3973332121 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 8589337234 ps |
| CPU time | 235.4 seconds |
| Started | Jun 04 12:38:21 PM PDT 24 |
| Finished | Jun 04 12:42:17 PM PDT 24 |
| Peak memory | 200140 kb |
| Host | smart-f49eaea2-d691-4d23-9137-11c5c2242b40 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3973332121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.3973332121 |
| Directory | /workspace/20.uart_perf/latest |
| Test location | /workspace/coverage/default/20.uart_rx_oversample.2065278111 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 1400757834 ps |
| CPU time | 1.11 seconds |
| Started | Jun 04 12:38:32 PM PDT 24 |
| Finished | Jun 04 12:38:34 PM PDT 24 |
| Peak memory | 195768 kb |
| Host | smart-637f6b51-86c4-465e-8b7b-591ad97916e5 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2065278111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.2065278111 |
| Directory | /workspace/20.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/20.uart_rx_parity_err.1073185081 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 71999312252 ps |
| CPU time | 112.48 seconds |
| Started | Jun 04 12:38:24 PM PDT 24 |
| Finished | Jun 04 12:40:17 PM PDT 24 |
| Peak memory | 199828 kb |
| Host | smart-65a70d31-87a5-4604-8cc6-c3639673fdd6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1073185081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.1073185081 |
| Directory | /workspace/20.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/20.uart_rx_start_bit_filter.1760610881 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 42749993584 ps |
| CPU time | 59.09 seconds |
| Started | Jun 04 12:38:22 PM PDT 24 |
| Finished | Jun 04 12:39:22 PM PDT 24 |
| Peak memory | 195964 kb |
| Host | smart-dece53d5-e4b7-4a45-91e6-4e794711a03e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1760610881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.1760610881 |
| Directory | /workspace/20.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/20.uart_smoke.4003592763 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 87023158 ps |
| CPU time | 0.88 seconds |
| Started | Jun 04 12:38:22 PM PDT 24 |
| Finished | Jun 04 12:38:24 PM PDT 24 |
| Peak memory | 197244 kb |
| Host | smart-91d6367d-396f-45d2-bf51-962dc1ba4160 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4003592763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_smoke.4003592763 |
| Directory | /workspace/20.uart_smoke/latest |
| Test location | /workspace/coverage/default/20.uart_stress_all.502702291 |
| Short name | T985 |
| Test name | |
| Test status | |
| Simulation time | 363937661872 ps |
| CPU time | 601.2 seconds |
| Started | Jun 04 12:38:23 PM PDT 24 |
| Finished | Jun 04 12:48:25 PM PDT 24 |
| Peak memory | 200292 kb |
| Host | smart-9870533b-d547-4a25-8128-9c859b725f0e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502702291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.502702291 |
| Directory | /workspace/20.uart_stress_all/latest |
| Test location | /workspace/coverage/default/20.uart_stress_all_with_rand_reset.3341674479 |
| Short name | T942 |
| Test name | |
| Test status | |
| Simulation time | 140349094814 ps |
| CPU time | 894.95 seconds |
| Started | Jun 04 12:38:23 PM PDT 24 |
| Finished | Jun 04 12:53:19 PM PDT 24 |
| Peak memory | 216688 kb |
| Host | smart-51c8702e-6d88-49a3-ac8a-494c9a624b52 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341674479 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 20.uart_stress_all_with_rand_reset.3341674479 |
| Directory | /workspace/20.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/20.uart_tx_ovrd.3251015092 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 913745024 ps |
| CPU time | 3.48 seconds |
| Started | Jun 04 12:38:21 PM PDT 24 |
| Finished | Jun 04 12:38:26 PM PDT 24 |
| Peak memory | 198940 kb |
| Host | smart-d6edbdb7-cc24-45ad-84ab-1241353c8009 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3251015092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.3251015092 |
| Directory | /workspace/20.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/20.uart_tx_rx.349477413 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 88623524506 ps |
| CPU time | 42.38 seconds |
| Started | Jun 04 12:38:22 PM PDT 24 |
| Finished | Jun 04 12:39:06 PM PDT 24 |
| Peak memory | 200284 kb |
| Host | smart-f5b4f8fd-392a-4ccb-ad6f-08c862802dd3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=349477413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.349477413 |
| Directory | /workspace/20.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/200.uart_fifo_reset.3584189870 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 106413821739 ps |
| CPU time | 172.73 seconds |
| Started | Jun 04 12:42:11 PM PDT 24 |
| Finished | Jun 04 12:45:06 PM PDT 24 |
| Peak memory | 199320 kb |
| Host | smart-0b3bf0da-830a-413f-bc43-787f3d7c0f75 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3584189870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.3584189870 |
| Directory | /workspace/200.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/201.uart_fifo_reset.450643779 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 71938297335 ps |
| CPU time | 36.42 seconds |
| Started | Jun 04 12:42:12 PM PDT 24 |
| Finished | Jun 04 12:42:50 PM PDT 24 |
| Peak memory | 200136 kb |
| Host | smart-abdf1f61-dfa4-4504-a64d-1867a6b3cd4c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=450643779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.450643779 |
| Directory | /workspace/201.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/202.uart_fifo_reset.184475448 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 15361235470 ps |
| CPU time | 28.41 seconds |
| Started | Jun 04 12:42:12 PM PDT 24 |
| Finished | Jun 04 12:42:42 PM PDT 24 |
| Peak memory | 200348 kb |
| Host | smart-294583cc-ed9d-4acc-8cf5-cf1269846a9a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=184475448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.184475448 |
| Directory | /workspace/202.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/203.uart_fifo_reset.1380189278 |
| Short name | T973 |
| Test name | |
| Test status | |
| Simulation time | 24442939849 ps |
| CPU time | 50.92 seconds |
| Started | Jun 04 12:42:11 PM PDT 24 |
| Finished | Jun 04 12:43:04 PM PDT 24 |
| Peak memory | 200296 kb |
| Host | smart-a65d076d-e678-4a21-a43c-d83f7d3cb37e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1380189278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.1380189278 |
| Directory | /workspace/203.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/204.uart_fifo_reset.2532792904 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 72230361724 ps |
| CPU time | 15.94 seconds |
| Started | Jun 04 12:42:12 PM PDT 24 |
| Finished | Jun 04 12:42:29 PM PDT 24 |
| Peak memory | 200264 kb |
| Host | smart-ac9f9e9d-bcdc-464b-88e2-857cd68ddd17 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2532792904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.2532792904 |
| Directory | /workspace/204.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/205.uart_fifo_reset.2878991377 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 90665536252 ps |
| CPU time | 60.22 seconds |
| Started | Jun 04 12:42:10 PM PDT 24 |
| Finished | Jun 04 12:43:11 PM PDT 24 |
| Peak memory | 200140 kb |
| Host | smart-947a9478-20f8-49a5-878e-9b0434e6e723 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2878991377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.2878991377 |
| Directory | /workspace/205.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/206.uart_fifo_reset.915784979 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 50659265914 ps |
| CPU time | 37.06 seconds |
| Started | Jun 04 12:42:12 PM PDT 24 |
| Finished | Jun 04 12:42:51 PM PDT 24 |
| Peak memory | 200192 kb |
| Host | smart-27e75820-ecea-4546-a212-aface314a901 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=915784979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.915784979 |
| Directory | /workspace/206.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/207.uart_fifo_reset.3498111420 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 15186566021 ps |
| CPU time | 26.76 seconds |
| Started | Jun 04 12:42:12 PM PDT 24 |
| Finished | Jun 04 12:42:40 PM PDT 24 |
| Peak memory | 200168 kb |
| Host | smart-6ce01023-5055-4994-94b2-7dd02f2f1e8a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3498111420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.3498111420 |
| Directory | /workspace/207.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/208.uart_fifo_reset.1612028076 |
| Short name | T992 |
| Test name | |
| Test status | |
| Simulation time | 102578710474 ps |
| CPU time | 145.85 seconds |
| Started | Jun 04 12:42:12 PM PDT 24 |
| Finished | Jun 04 12:44:40 PM PDT 24 |
| Peak memory | 200040 kb |
| Host | smart-5fcab5c1-cf1b-4969-8921-da0eb4a0dd7e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1612028076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.1612028076 |
| Directory | /workspace/208.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/209.uart_fifo_reset.1177909662 |
| Short name | T999 |
| Test name | |
| Test status | |
| Simulation time | 37950619872 ps |
| CPU time | 62.26 seconds |
| Started | Jun 04 12:42:11 PM PDT 24 |
| Finished | Jun 04 12:43:14 PM PDT 24 |
| Peak memory | 200156 kb |
| Host | smart-4b479c4a-78e2-435f-9005-2dad3fba864e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1177909662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.1177909662 |
| Directory | /workspace/209.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/21.uart_alert_test.731510801 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 15211507 ps |
| CPU time | 0.55 seconds |
| Started | Jun 04 12:38:34 PM PDT 24 |
| Finished | Jun 04 12:38:35 PM PDT 24 |
| Peak memory | 195708 kb |
| Host | smart-2e7981ad-1ee5-4b75-878c-2840667f5050 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731510801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.731510801 |
| Directory | /workspace/21.uart_alert_test/latest |
| Test location | /workspace/coverage/default/21.uart_fifo_full.780762265 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 25406299289 ps |
| CPU time | 22.23 seconds |
| Started | Jun 04 12:38:32 PM PDT 24 |
| Finished | Jun 04 12:38:55 PM PDT 24 |
| Peak memory | 200248 kb |
| Host | smart-e36fef39-07a8-475a-aeec-6d7d3e82f168 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=780762265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.780762265 |
| Directory | /workspace/21.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/21.uart_fifo_overflow.1359256207 |
| Short name | T1103 |
| Test name | |
| Test status | |
| Simulation time | 5067749485 ps |
| CPU time | 9.02 seconds |
| Started | Jun 04 12:38:22 PM PDT 24 |
| Finished | Jun 04 12:38:32 PM PDT 24 |
| Peak memory | 199956 kb |
| Host | smart-eb005c9c-430a-4cfa-9fbf-c986e9af5a9d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1359256207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.1359256207 |
| Directory | /workspace/21.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/21.uart_fifo_reset.106179152 |
| Short name | T1114 |
| Test name | |
| Test status | |
| Simulation time | 89971200225 ps |
| CPU time | 229.7 seconds |
| Started | Jun 04 12:38:23 PM PDT 24 |
| Finished | Jun 04 12:42:14 PM PDT 24 |
| Peak memory | 200248 kb |
| Host | smart-0cf59489-da94-4748-82d8-2cf902565f96 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=106179152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.106179152 |
| Directory | /workspace/21.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/21.uart_intr.2748796695 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 7013978601 ps |
| CPU time | 12.11 seconds |
| Started | Jun 04 12:38:21 PM PDT 24 |
| Finished | Jun 04 12:38:34 PM PDT 24 |
| Peak memory | 198028 kb |
| Host | smart-2c550654-2f8a-4072-8180-194d8a5c654b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748796695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.2748796695 |
| Directory | /workspace/21.uart_intr/latest |
| Test location | /workspace/coverage/default/21.uart_long_xfer_wo_dly.1947947897 |
| Short name | T991 |
| Test name | |
| Test status | |
| Simulation time | 187577456178 ps |
| CPU time | 187.92 seconds |
| Started | Jun 04 12:38:34 PM PDT 24 |
| Finished | Jun 04 12:41:43 PM PDT 24 |
| Peak memory | 200212 kb |
| Host | smart-37f8dd96-f0d3-4a3b-ac1c-82d58f098216 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1947947897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.1947947897 |
| Directory | /workspace/21.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/21.uart_loopback.544158796 |
| Short name | T946 |
| Test name | |
| Test status | |
| Simulation time | 6842688459 ps |
| CPU time | 21.08 seconds |
| Started | Jun 04 12:38:32 PM PDT 24 |
| Finished | Jun 04 12:38:54 PM PDT 24 |
| Peak memory | 199856 kb |
| Host | smart-796c62ab-8eeb-47ad-86e5-b40a8a6ab9b8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=544158796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_loopback.544158796 |
| Directory | /workspace/21.uart_loopback/latest |
| Test location | /workspace/coverage/default/21.uart_noise_filter.650796129 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 22163518357 ps |
| CPU time | 16.01 seconds |
| Started | Jun 04 12:38:34 PM PDT 24 |
| Finished | Jun 04 12:38:51 PM PDT 24 |
| Peak memory | 197036 kb |
| Host | smart-d6971222-022a-4731-89d8-accc48b50122 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=650796129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_noise_filter.650796129 |
| Directory | /workspace/21.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/21.uart_perf.3329799572 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 8660770436 ps |
| CPU time | 119.44 seconds |
| Started | Jun 04 12:38:33 PM PDT 24 |
| Finished | Jun 04 12:40:33 PM PDT 24 |
| Peak memory | 200112 kb |
| Host | smart-1c134add-01f4-47bb-8ec4-2ac48dd60e23 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3329799572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.3329799572 |
| Directory | /workspace/21.uart_perf/latest |
| Test location | /workspace/coverage/default/21.uart_rx_oversample.3678714617 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 1550468696 ps |
| CPU time | 1.19 seconds |
| Started | Jun 04 12:38:32 PM PDT 24 |
| Finished | Jun 04 12:38:34 PM PDT 24 |
| Peak memory | 197536 kb |
| Host | smart-7444df0f-3ad0-4239-9ab6-fce7097c4abd |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3678714617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.3678714617 |
| Directory | /workspace/21.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/21.uart_rx_parity_err.1911847413 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 76660439365 ps |
| CPU time | 56.63 seconds |
| Started | Jun 04 12:38:35 PM PDT 24 |
| Finished | Jun 04 12:39:32 PM PDT 24 |
| Peak memory | 200164 kb |
| Host | smart-c2d5bbf3-765f-41df-b57d-c57e8ffeb130 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1911847413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.1911847413 |
| Directory | /workspace/21.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/21.uart_rx_start_bit_filter.1101284176 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 604010731 ps |
| CPU time | 1.1 seconds |
| Started | Jun 04 12:38:32 PM PDT 24 |
| Finished | Jun 04 12:38:34 PM PDT 24 |
| Peak memory | 195720 kb |
| Host | smart-b84b0924-7fc5-4189-b2ea-4656b982e7b8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1101284176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.1101284176 |
| Directory | /workspace/21.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/21.uart_smoke.1946733718 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 281265388 ps |
| CPU time | 1.06 seconds |
| Started | Jun 04 12:38:32 PM PDT 24 |
| Finished | Jun 04 12:38:34 PM PDT 24 |
| Peak memory | 198332 kb |
| Host | smart-1bb46025-bbb6-4762-bdbe-f801ab6137e7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1946733718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_smoke.1946733718 |
| Directory | /workspace/21.uart_smoke/latest |
| Test location | /workspace/coverage/default/21.uart_stress_all.2221974503 |
| Short name | T937 |
| Test name | |
| Test status | |
| Simulation time | 140809316226 ps |
| CPU time | 240.57 seconds |
| Started | Jun 04 12:38:31 PM PDT 24 |
| Finished | Jun 04 12:42:32 PM PDT 24 |
| Peak memory | 200252 kb |
| Host | smart-105f2f2b-2c19-4169-8268-e818a6316c35 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221974503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.2221974503 |
| Directory | /workspace/21.uart_stress_all/latest |
| Test location | /workspace/coverage/default/21.uart_stress_all_with_rand_reset.1223496105 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 99023941829 ps |
| CPU time | 429.91 seconds |
| Started | Jun 04 12:38:33 PM PDT 24 |
| Finished | Jun 04 12:45:44 PM PDT 24 |
| Peak memory | 216592 kb |
| Host | smart-3687438f-3045-4f13-aebf-a3860f8aa010 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223496105 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 21.uart_stress_all_with_rand_reset.1223496105 |
| Directory | /workspace/21.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/21.uart_tx_ovrd.2443903155 |
| Short name | T1168 |
| Test name | |
| Test status | |
| Simulation time | 448146576 ps |
| CPU time | 1.52 seconds |
| Started | Jun 04 12:38:34 PM PDT 24 |
| Finished | Jun 04 12:38:36 PM PDT 24 |
| Peak memory | 198528 kb |
| Host | smart-49299d8c-9a7f-422c-984e-0bfcc28538f2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2443903155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.2443903155 |
| Directory | /workspace/21.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/21.uart_tx_rx.172972292 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 138477431935 ps |
| CPU time | 71.49 seconds |
| Started | Jun 04 12:38:21 PM PDT 24 |
| Finished | Jun 04 12:39:34 PM PDT 24 |
| Peak memory | 200180 kb |
| Host | smart-383194b4-4741-40a7-805e-4ab013669328 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=172972292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.172972292 |
| Directory | /workspace/21.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/211.uart_fifo_reset.2809952517 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 139063100344 ps |
| CPU time | 218.47 seconds |
| Started | Jun 04 12:42:10 PM PDT 24 |
| Finished | Jun 04 12:45:49 PM PDT 24 |
| Peak memory | 200216 kb |
| Host | smart-2b6473bc-2814-4961-a873-92370d2034cc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2809952517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.2809952517 |
| Directory | /workspace/211.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/212.uart_fifo_reset.2400696824 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 54820986996 ps |
| CPU time | 84.48 seconds |
| Started | Jun 04 12:42:25 PM PDT 24 |
| Finished | Jun 04 12:43:50 PM PDT 24 |
| Peak memory | 200168 kb |
| Host | smart-f672b73b-7016-44c7-960c-f7e7cce53590 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2400696824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.2400696824 |
| Directory | /workspace/212.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/213.uart_fifo_reset.3325741973 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 46384596868 ps |
| CPU time | 20.12 seconds |
| Started | Jun 04 12:42:20 PM PDT 24 |
| Finished | Jun 04 12:42:40 PM PDT 24 |
| Peak memory | 200080 kb |
| Host | smart-c033bffd-b939-4128-a9d4-0b8fc387b243 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3325741973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.3325741973 |
| Directory | /workspace/213.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/214.uart_fifo_reset.1981914004 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 199621691567 ps |
| CPU time | 47.74 seconds |
| Started | Jun 04 12:42:24 PM PDT 24 |
| Finished | Jun 04 12:43:12 PM PDT 24 |
| Peak memory | 200280 kb |
| Host | smart-5ccee665-2756-45ce-8e50-7eadcb923029 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1981914004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.1981914004 |
| Directory | /workspace/214.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/215.uart_fifo_reset.1526910638 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 53541451755 ps |
| CPU time | 38.67 seconds |
| Started | Jun 04 12:42:21 PM PDT 24 |
| Finished | Jun 04 12:43:00 PM PDT 24 |
| Peak memory | 200148 kb |
| Host | smart-0ad4a09c-3e96-445d-bb1d-021bce75a00e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1526910638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.1526910638 |
| Directory | /workspace/215.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/216.uart_fifo_reset.777778669 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 128679869076 ps |
| CPU time | 215.64 seconds |
| Started | Jun 04 12:42:25 PM PDT 24 |
| Finished | Jun 04 12:46:01 PM PDT 24 |
| Peak memory | 200212 kb |
| Host | smart-61290dfe-3012-4e02-b7cd-95611d8f21cf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=777778669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.777778669 |
| Directory | /workspace/216.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/217.uart_fifo_reset.1002391840 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 33924979222 ps |
| CPU time | 57.45 seconds |
| Started | Jun 04 12:42:19 PM PDT 24 |
| Finished | Jun 04 12:43:17 PM PDT 24 |
| Peak memory | 200232 kb |
| Host | smart-2473d798-519d-4c17-9725-ddf426b3f66b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1002391840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.1002391840 |
| Directory | /workspace/217.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/218.uart_fifo_reset.2601505564 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 201512844690 ps |
| CPU time | 194.91 seconds |
| Started | Jun 04 12:42:20 PM PDT 24 |
| Finished | Jun 04 12:45:35 PM PDT 24 |
| Peak memory | 200156 kb |
| Host | smart-5618cdd8-0426-45c1-a23c-516327861aeb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2601505564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.2601505564 |
| Directory | /workspace/218.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/219.uart_fifo_reset.1548682606 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 46912348556 ps |
| CPU time | 43.34 seconds |
| Started | Jun 04 12:42:19 PM PDT 24 |
| Finished | Jun 04 12:43:03 PM PDT 24 |
| Peak memory | 200268 kb |
| Host | smart-29e6ed03-fe70-4201-8da6-dd222c5c16cd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1548682606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.1548682606 |
| Directory | /workspace/219.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/22.uart_alert_test.3657132917 |
| Short name | T1040 |
| Test name | |
| Test status | |
| Simulation time | 14887844 ps |
| CPU time | 0.56 seconds |
| Started | Jun 04 12:38:35 PM PDT 24 |
| Finished | Jun 04 12:38:36 PM PDT 24 |
| Peak memory | 194600 kb |
| Host | smart-631161c1-d156-400d-8233-f662e8354cff |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657132917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.3657132917 |
| Directory | /workspace/22.uart_alert_test/latest |
| Test location | /workspace/coverage/default/22.uart_fifo_full.3226410864 |
| Short name | T1127 |
| Test name | |
| Test status | |
| Simulation time | 28542457534 ps |
| CPU time | 51.49 seconds |
| Started | Jun 04 12:38:33 PM PDT 24 |
| Finished | Jun 04 12:39:26 PM PDT 24 |
| Peak memory | 200108 kb |
| Host | smart-cd886073-993a-44ef-8409-1bbcce02077a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3226410864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.3226410864 |
| Directory | /workspace/22.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/22.uart_fifo_overflow.3752547309 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 53186647084 ps |
| CPU time | 91.73 seconds |
| Started | Jun 04 12:38:34 PM PDT 24 |
| Finished | Jun 04 12:40:07 PM PDT 24 |
| Peak memory | 200300 kb |
| Host | smart-ffb56d32-1411-4c90-ab40-24639a06bf01 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3752547309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.3752547309 |
| Directory | /workspace/22.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/22.uart_fifo_reset.1096088214 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 59072196827 ps |
| CPU time | 25.81 seconds |
| Started | Jun 04 12:38:36 PM PDT 24 |
| Finished | Jun 04 12:39:02 PM PDT 24 |
| Peak memory | 200312 kb |
| Host | smart-741ae0f1-c599-421e-9a67-de8309553fd8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1096088214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.1096088214 |
| Directory | /workspace/22.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/22.uart_intr.2291380030 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 66020697423 ps |
| CPU time | 102.37 seconds |
| Started | Jun 04 12:38:33 PM PDT 24 |
| Finished | Jun 04 12:40:16 PM PDT 24 |
| Peak memory | 200100 kb |
| Host | smart-f995bc76-c813-4e27-9bb4-f374f34d5e0b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291380030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.2291380030 |
| Directory | /workspace/22.uart_intr/latest |
| Test location | /workspace/coverage/default/22.uart_long_xfer_wo_dly.3292856463 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 44305964847 ps |
| CPU time | 226.93 seconds |
| Started | Jun 04 12:38:33 PM PDT 24 |
| Finished | Jun 04 12:42:21 PM PDT 24 |
| Peak memory | 200152 kb |
| Host | smart-d0a060ae-3dc6-4270-afaa-a643af1b14f4 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3292856463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.3292856463 |
| Directory | /workspace/22.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/22.uart_loopback.266393756 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 5874328869 ps |
| CPU time | 3.84 seconds |
| Started | Jun 04 12:38:34 PM PDT 24 |
| Finished | Jun 04 12:38:39 PM PDT 24 |
| Peak memory | 200220 kb |
| Host | smart-9b444f43-bb5f-4b6f-b3e3-e49ac93428d7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=266393756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_loopback.266393756 |
| Directory | /workspace/22.uart_loopback/latest |
| Test location | /workspace/coverage/default/22.uart_noise_filter.32288752 |
| Short name | T1036 |
| Test name | |
| Test status | |
| Simulation time | 169463095617 ps |
| CPU time | 70.14 seconds |
| Started | Jun 04 12:38:34 PM PDT 24 |
| Finished | Jun 04 12:39:45 PM PDT 24 |
| Peak memory | 200480 kb |
| Host | smart-04cbb397-f8f4-481a-99f3-d33d1596fcac |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=32288752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_noise_filter.32288752 |
| Directory | /workspace/22.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/22.uart_perf.1906471656 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 25273232420 ps |
| CPU time | 310.72 seconds |
| Started | Jun 04 12:38:34 PM PDT 24 |
| Finished | Jun 04 12:43:45 PM PDT 24 |
| Peak memory | 200168 kb |
| Host | smart-b3469beb-4eb9-43be-bdd6-ddd0e948700b |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1906471656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.1906471656 |
| Directory | /workspace/22.uart_perf/latest |
| Test location | /workspace/coverage/default/22.uart_rx_oversample.914470604 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 2341845173 ps |
| CPU time | 4.04 seconds |
| Started | Jun 04 12:38:33 PM PDT 24 |
| Finished | Jun 04 12:38:37 PM PDT 24 |
| Peak memory | 198520 kb |
| Host | smart-73a2e46b-fa81-4b12-8d64-7dbf058a03e6 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=914470604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.914470604 |
| Directory | /workspace/22.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/22.uart_rx_parity_err.3993883108 |
| Short name | T988 |
| Test name | |
| Test status | |
| Simulation time | 83252392823 ps |
| CPU time | 62.7 seconds |
| Started | Jun 04 12:38:33 PM PDT 24 |
| Finished | Jun 04 12:39:36 PM PDT 24 |
| Peak memory | 200088 kb |
| Host | smart-1836f4b4-397b-4582-b104-e14b357b6370 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3993883108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.3993883108 |
| Directory | /workspace/22.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/22.uart_rx_start_bit_filter.3788424856 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 1903827627 ps |
| CPU time | 3.7 seconds |
| Started | Jun 04 12:38:32 PM PDT 24 |
| Finished | Jun 04 12:38:37 PM PDT 24 |
| Peak memory | 195720 kb |
| Host | smart-ed1f85a8-7847-428e-8ad6-1c7f2cc8dbd5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3788424856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.3788424856 |
| Directory | /workspace/22.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/22.uart_smoke.1274903333 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 261992409 ps |
| CPU time | 1.35 seconds |
| Started | Jun 04 12:38:34 PM PDT 24 |
| Finished | Jun 04 12:38:37 PM PDT 24 |
| Peak memory | 198612 kb |
| Host | smart-eded1d4b-a673-4954-a47b-604e78b50992 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1274903333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_smoke.1274903333 |
| Directory | /workspace/22.uart_smoke/latest |
| Test location | /workspace/coverage/default/22.uart_tx_ovrd.3617948086 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 6845833079 ps |
| CPU time | 22.39 seconds |
| Started | Jun 04 12:38:36 PM PDT 24 |
| Finished | Jun 04 12:38:59 PM PDT 24 |
| Peak memory | 200276 kb |
| Host | smart-2fcad9fe-749d-47c8-9fc7-6a00a99e5f33 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3617948086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.3617948086 |
| Directory | /workspace/22.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/22.uart_tx_rx.2249421671 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 190145430997 ps |
| CPU time | 17.07 seconds |
| Started | Jun 04 12:38:32 PM PDT 24 |
| Finished | Jun 04 12:38:49 PM PDT 24 |
| Peak memory | 200244 kb |
| Host | smart-c007e459-ed7a-4c61-a367-cc5e612c6132 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2249421671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.2249421671 |
| Directory | /workspace/22.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/220.uart_fifo_reset.3232828261 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 118416760949 ps |
| CPU time | 56.62 seconds |
| Started | Jun 04 12:42:20 PM PDT 24 |
| Finished | Jun 04 12:43:17 PM PDT 24 |
| Peak memory | 200208 kb |
| Host | smart-7217c0e3-ee7f-4fb2-ac22-6eb78388254d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3232828261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.3232828261 |
| Directory | /workspace/220.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/221.uart_fifo_reset.1812282911 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 110565026265 ps |
| CPU time | 51.18 seconds |
| Started | Jun 04 12:42:19 PM PDT 24 |
| Finished | Jun 04 12:43:11 PM PDT 24 |
| Peak memory | 200364 kb |
| Host | smart-81e30e50-ef8b-4bf3-be42-c017cf3ebe78 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1812282911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.1812282911 |
| Directory | /workspace/221.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/222.uart_fifo_reset.888879738 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 27632442856 ps |
| CPU time | 13.58 seconds |
| Started | Jun 04 12:42:18 PM PDT 24 |
| Finished | Jun 04 12:42:33 PM PDT 24 |
| Peak memory | 200236 kb |
| Host | smart-8fcf1de8-380f-4bdc-b7bc-22f1651f4a23 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=888879738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.888879738 |
| Directory | /workspace/222.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/224.uart_fifo_reset.3268119082 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 37864754451 ps |
| CPU time | 22.25 seconds |
| Started | Jun 04 12:42:21 PM PDT 24 |
| Finished | Jun 04 12:42:44 PM PDT 24 |
| Peak memory | 200164 kb |
| Host | smart-b5aec191-a0f4-4e87-9d16-b0bb7a31ec6d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3268119082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.3268119082 |
| Directory | /workspace/224.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/225.uart_fifo_reset.2485212420 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 133944143612 ps |
| CPU time | 53.58 seconds |
| Started | Jun 04 12:42:23 PM PDT 24 |
| Finished | Jun 04 12:43:18 PM PDT 24 |
| Peak memory | 200220 kb |
| Host | smart-47872144-5629-4853-8284-71c946635953 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2485212420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.2485212420 |
| Directory | /workspace/225.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/226.uart_fifo_reset.3734486940 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 17497978098 ps |
| CPU time | 26.75 seconds |
| Started | Jun 04 12:42:22 PM PDT 24 |
| Finished | Jun 04 12:42:49 PM PDT 24 |
| Peak memory | 200196 kb |
| Host | smart-715b76b0-5461-4b24-a07b-978373e35f51 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3734486940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.3734486940 |
| Directory | /workspace/226.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/227.uart_fifo_reset.596640543 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 201778718989 ps |
| CPU time | 219.55 seconds |
| Started | Jun 04 12:42:18 PM PDT 24 |
| Finished | Jun 04 12:45:58 PM PDT 24 |
| Peak memory | 200276 kb |
| Host | smart-a53795f4-70d5-4c40-b184-034844495615 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=596640543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.596640543 |
| Directory | /workspace/227.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/228.uart_fifo_reset.4066142873 |
| Short name | T1122 |
| Test name | |
| Test status | |
| Simulation time | 236188536858 ps |
| CPU time | 32.68 seconds |
| Started | Jun 04 12:42:22 PM PDT 24 |
| Finished | Jun 04 12:42:55 PM PDT 24 |
| Peak memory | 200164 kb |
| Host | smart-e1be47e0-f2aa-4c41-9309-5f3c1645e781 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4066142873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.4066142873 |
| Directory | /workspace/228.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/229.uart_fifo_reset.2496156770 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 93930564479 ps |
| CPU time | 137.02 seconds |
| Started | Jun 04 12:42:19 PM PDT 24 |
| Finished | Jun 04 12:44:37 PM PDT 24 |
| Peak memory | 200228 kb |
| Host | smart-034a60fb-c7d5-4fae-91ec-a0b56a459afe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2496156770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.2496156770 |
| Directory | /workspace/229.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/23.uart_alert_test.1646228846 |
| Short name | T978 |
| Test name | |
| Test status | |
| Simulation time | 65412467 ps |
| CPU time | 0.56 seconds |
| Started | Jun 04 12:38:45 PM PDT 24 |
| Finished | Jun 04 12:38:46 PM PDT 24 |
| Peak memory | 195728 kb |
| Host | smart-f8b0db3f-b4aa-4836-a4ae-1c77fa694ea6 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646228846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.1646228846 |
| Directory | /workspace/23.uart_alert_test/latest |
| Test location | /workspace/coverage/default/23.uart_fifo_full.3145835646 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 40102987707 ps |
| CPU time | 17.23 seconds |
| Started | Jun 04 12:38:34 PM PDT 24 |
| Finished | Jun 04 12:38:52 PM PDT 24 |
| Peak memory | 200220 kb |
| Host | smart-759956d7-51d1-482d-a8fd-ffa8770776b9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3145835646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.3145835646 |
| Directory | /workspace/23.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/23.uart_fifo_overflow.406362897 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 16011821097 ps |
| CPU time | 26.21 seconds |
| Started | Jun 04 12:38:32 PM PDT 24 |
| Finished | Jun 04 12:38:59 PM PDT 24 |
| Peak memory | 200156 kb |
| Host | smart-803015f8-0e82-4787-91b5-d025e4912c02 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=406362897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.406362897 |
| Directory | /workspace/23.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/23.uart_fifo_reset.123542823 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 83744642964 ps |
| CPU time | 36.64 seconds |
| Started | Jun 04 12:38:43 PM PDT 24 |
| Finished | Jun 04 12:39:20 PM PDT 24 |
| Peak memory | 200316 kb |
| Host | smart-ce98b535-36c4-4888-a3f1-a8e5cf39f21b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=123542823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.123542823 |
| Directory | /workspace/23.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/23.uart_intr.1736035104 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 33532329230 ps |
| CPU time | 29.59 seconds |
| Started | Jun 04 12:38:45 PM PDT 24 |
| Finished | Jun 04 12:39:16 PM PDT 24 |
| Peak memory | 199828 kb |
| Host | smart-992bb13f-c506-4c96-9c4e-fe84d2af588b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736035104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.1736035104 |
| Directory | /workspace/23.uart_intr/latest |
| Test location | /workspace/coverage/default/23.uart_long_xfer_wo_dly.3489061719 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 171154912810 ps |
| CPU time | 306.32 seconds |
| Started | Jun 04 12:38:43 PM PDT 24 |
| Finished | Jun 04 12:43:50 PM PDT 24 |
| Peak memory | 200252 kb |
| Host | smart-f7b1757b-3b07-43e1-8bda-f9a3e61e5056 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3489061719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.3489061719 |
| Directory | /workspace/23.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/23.uart_loopback.2163965067 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 4626767525 ps |
| CPU time | 8.4 seconds |
| Started | Jun 04 12:38:42 PM PDT 24 |
| Finished | Jun 04 12:38:51 PM PDT 24 |
| Peak memory | 198916 kb |
| Host | smart-45963a2c-7ab4-4b95-9df9-9e4ac586d3c1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2163965067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_loopback.2163965067 |
| Directory | /workspace/23.uart_loopback/latest |
| Test location | /workspace/coverage/default/23.uart_noise_filter.4156705769 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 89182593646 ps |
| CPU time | 44.31 seconds |
| Started | Jun 04 12:38:45 PM PDT 24 |
| Finished | Jun 04 12:39:30 PM PDT 24 |
| Peak memory | 208640 kb |
| Host | smart-a36faf4d-5975-48bf-857f-43c383724ede |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4156705769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_noise_filter.4156705769 |
| Directory | /workspace/23.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/23.uart_perf.4129688669 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 27245095272 ps |
| CPU time | 1416.86 seconds |
| Started | Jun 04 12:38:46 PM PDT 24 |
| Finished | Jun 04 01:02:24 PM PDT 24 |
| Peak memory | 200360 kb |
| Host | smart-2d88c23c-267b-434b-8434-6ba117f45e49 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4129688669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.4129688669 |
| Directory | /workspace/23.uart_perf/latest |
| Test location | /workspace/coverage/default/23.uart_rx_oversample.1471525710 |
| Short name | T955 |
| Test name | |
| Test status | |
| Simulation time | 3903500276 ps |
| CPU time | 35.08 seconds |
| Started | Jun 04 12:38:44 PM PDT 24 |
| Finished | Jun 04 12:39:21 PM PDT 24 |
| Peak memory | 198660 kb |
| Host | smart-cdedd8c7-6b0f-44c6-9de7-d99c5bf48335 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1471525710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.1471525710 |
| Directory | /workspace/23.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/23.uart_rx_parity_err.2441381589 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 72473782866 ps |
| CPU time | 15.58 seconds |
| Started | Jun 04 12:38:44 PM PDT 24 |
| Finished | Jun 04 12:39:01 PM PDT 24 |
| Peak memory | 200096 kb |
| Host | smart-5a5fd26e-77b6-4d09-9ee9-594f879b593d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2441381589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.2441381589 |
| Directory | /workspace/23.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/23.uart_rx_start_bit_filter.572831935 |
| Short name | T1002 |
| Test name | |
| Test status | |
| Simulation time | 1816704699 ps |
| CPU time | 3.53 seconds |
| Started | Jun 04 12:38:45 PM PDT 24 |
| Finished | Jun 04 12:38:50 PM PDT 24 |
| Peak memory | 195560 kb |
| Host | smart-f01149ea-f7cc-446b-8b21-c52cb018e270 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=572831935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.572831935 |
| Directory | /workspace/23.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/23.uart_smoke.2789952261 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 290146027 ps |
| CPU time | 1.6 seconds |
| Started | Jun 04 12:38:34 PM PDT 24 |
| Finished | Jun 04 12:38:36 PM PDT 24 |
| Peak memory | 199700 kb |
| Host | smart-fd648d7c-56d3-4c17-a5fb-748df442489e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2789952261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_smoke.2789952261 |
| Directory | /workspace/23.uart_smoke/latest |
| Test location | /workspace/coverage/default/23.uart_stress_all.2156932980 |
| Short name | T1173 |
| Test name | |
| Test status | |
| Simulation time | 280311828404 ps |
| CPU time | 114.67 seconds |
| Started | Jun 04 12:38:45 PM PDT 24 |
| Finished | Jun 04 12:40:41 PM PDT 24 |
| Peak memory | 208568 kb |
| Host | smart-145b4f2f-0c94-44e7-916b-a6b466e3513a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156932980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.2156932980 |
| Directory | /workspace/23.uart_stress_all/latest |
| Test location | /workspace/coverage/default/23.uart_stress_all_with_rand_reset.2990851958 |
| Short name | T940 |
| Test name | |
| Test status | |
| Simulation time | 117639054075 ps |
| CPU time | 1475.4 seconds |
| Started | Jun 04 12:38:45 PM PDT 24 |
| Finished | Jun 04 01:03:21 PM PDT 24 |
| Peak memory | 230668 kb |
| Host | smart-231d737d-fd1a-4133-8f9e-73c7befdb50e |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990851958 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 23.uart_stress_all_with_rand_reset.2990851958 |
| Directory | /workspace/23.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/23.uart_tx_ovrd.2725066064 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 7277830265 ps |
| CPU time | 23.17 seconds |
| Started | Jun 04 12:38:43 PM PDT 24 |
| Finished | Jun 04 12:39:07 PM PDT 24 |
| Peak memory | 200044 kb |
| Host | smart-f9b75d4e-b43b-4fb3-98d9-856b2803d0fa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2725066064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.2725066064 |
| Directory | /workspace/23.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/23.uart_tx_rx.566062202 |
| Short name | T1062 |
| Test name | |
| Test status | |
| Simulation time | 53280779328 ps |
| CPU time | 31.85 seconds |
| Started | Jun 04 12:38:34 PM PDT 24 |
| Finished | Jun 04 12:39:07 PM PDT 24 |
| Peak memory | 200304 kb |
| Host | smart-9ebbefef-e810-477d-abcf-c47545d89767 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=566062202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.566062202 |
| Directory | /workspace/23.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/230.uart_fifo_reset.2599598702 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 43799695424 ps |
| CPU time | 69.8 seconds |
| Started | Jun 04 12:42:20 PM PDT 24 |
| Finished | Jun 04 12:43:30 PM PDT 24 |
| Peak memory | 200208 kb |
| Host | smart-4070b2cf-d649-4819-9d47-7988700eaafa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2599598702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.2599598702 |
| Directory | /workspace/230.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/231.uart_fifo_reset.475033056 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 119529922280 ps |
| CPU time | 56.51 seconds |
| Started | Jun 04 12:42:20 PM PDT 24 |
| Finished | Jun 04 12:43:17 PM PDT 24 |
| Peak memory | 200416 kb |
| Host | smart-f9ac8e43-5544-4924-83c3-c584b0828e7b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=475033056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.475033056 |
| Directory | /workspace/231.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/232.uart_fifo_reset.1536596308 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 40327002969 ps |
| CPU time | 72.85 seconds |
| Started | Jun 04 12:42:24 PM PDT 24 |
| Finished | Jun 04 12:43:38 PM PDT 24 |
| Peak memory | 200132 kb |
| Host | smart-48b8f7ce-a1c3-40b7-b02c-2547ba59c8d6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1536596308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.1536596308 |
| Directory | /workspace/232.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/233.uart_fifo_reset.2011935715 |
| Short name | T1038 |
| Test name | |
| Test status | |
| Simulation time | 239125516976 ps |
| CPU time | 109.83 seconds |
| Started | Jun 04 12:42:26 PM PDT 24 |
| Finished | Jun 04 12:44:16 PM PDT 24 |
| Peak memory | 200136 kb |
| Host | smart-be620498-ca3d-4eb8-b246-a09d24a28477 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2011935715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.2011935715 |
| Directory | /workspace/233.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/234.uart_fifo_reset.2084948506 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 114978324961 ps |
| CPU time | 117.38 seconds |
| Started | Jun 04 12:42:23 PM PDT 24 |
| Finished | Jun 04 12:44:22 PM PDT 24 |
| Peak memory | 200192 kb |
| Host | smart-adbad889-0df1-4fe5-848f-52ad161932b8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2084948506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.2084948506 |
| Directory | /workspace/234.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/235.uart_fifo_reset.805820144 |
| Short name | T996 |
| Test name | |
| Test status | |
| Simulation time | 14534731818 ps |
| CPU time | 23.81 seconds |
| Started | Jun 04 12:42:36 PM PDT 24 |
| Finished | Jun 04 12:43:00 PM PDT 24 |
| Peak memory | 200024 kb |
| Host | smart-5dd77d96-7b6e-4e96-baff-dce134d55370 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=805820144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.805820144 |
| Directory | /workspace/235.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/236.uart_fifo_reset.1291447961 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 115018728828 ps |
| CPU time | 45.32 seconds |
| Started | Jun 04 12:42:30 PM PDT 24 |
| Finished | Jun 04 12:43:16 PM PDT 24 |
| Peak memory | 200244 kb |
| Host | smart-9f714289-8431-4dad-99f2-0347732b8b03 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1291447961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.1291447961 |
| Directory | /workspace/236.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/237.uart_fifo_reset.1842161691 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 27881298442 ps |
| CPU time | 28.74 seconds |
| Started | Jun 04 12:42:36 PM PDT 24 |
| Finished | Jun 04 12:43:05 PM PDT 24 |
| Peak memory | 200040 kb |
| Host | smart-8486e9bd-5c33-4618-aa6d-2a8cece8efc6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1842161691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.1842161691 |
| Directory | /workspace/237.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/238.uart_fifo_reset.2153399518 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 22747161142 ps |
| CPU time | 50.83 seconds |
| Started | Jun 04 12:42:28 PM PDT 24 |
| Finished | Jun 04 12:43:20 PM PDT 24 |
| Peak memory | 200208 kb |
| Host | smart-fe6d5e32-61f2-4a9d-9979-3f4da0d41b8d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2153399518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.2153399518 |
| Directory | /workspace/238.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/239.uart_fifo_reset.3943128608 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 16227525415 ps |
| CPU time | 8.25 seconds |
| Started | Jun 04 12:42:36 PM PDT 24 |
| Finished | Jun 04 12:42:45 PM PDT 24 |
| Peak memory | 199292 kb |
| Host | smart-434855ec-9847-474e-a94e-93b19893b7ad |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3943128608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.3943128608 |
| Directory | /workspace/239.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/24.uart_alert_test.2258998986 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 18129315 ps |
| CPU time | 0.57 seconds |
| Started | Jun 04 12:38:46 PM PDT 24 |
| Finished | Jun 04 12:38:47 PM PDT 24 |
| Peak memory | 195620 kb |
| Host | smart-7006a50d-b668-4719-b718-addf94f337c5 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258998986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.2258998986 |
| Directory | /workspace/24.uart_alert_test/latest |
| Test location | /workspace/coverage/default/24.uart_fifo_full.551351738 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 144809888038 ps |
| CPU time | 453.63 seconds |
| Started | Jun 04 12:38:44 PM PDT 24 |
| Finished | Jun 04 12:46:19 PM PDT 24 |
| Peak memory | 200244 kb |
| Host | smart-b1a189a5-a54a-45f7-86f3-d02afaa91ae8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=551351738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.551351738 |
| Directory | /workspace/24.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/24.uart_fifo_overflow.1871462372 |
| Short name | T923 |
| Test name | |
| Test status | |
| Simulation time | 32488223529 ps |
| CPU time | 48.59 seconds |
| Started | Jun 04 12:38:44 PM PDT 24 |
| Finished | Jun 04 12:39:33 PM PDT 24 |
| Peak memory | 200232 kb |
| Host | smart-532bedde-aa7c-4c06-9fba-6766a2f91993 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1871462372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.1871462372 |
| Directory | /workspace/24.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/24.uart_fifo_reset.1558851614 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 16955890835 ps |
| CPU time | 31.31 seconds |
| Started | Jun 04 12:38:44 PM PDT 24 |
| Finished | Jun 04 12:39:16 PM PDT 24 |
| Peak memory | 200144 kb |
| Host | smart-bcab71f3-1913-44be-8937-b673e214981b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1558851614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.1558851614 |
| Directory | /workspace/24.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/24.uart_intr.3623268469 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 58588369978 ps |
| CPU time | 96.07 seconds |
| Started | Jun 04 12:38:46 PM PDT 24 |
| Finished | Jun 04 12:40:23 PM PDT 24 |
| Peak memory | 199764 kb |
| Host | smart-59317177-3be0-45c9-bd8f-efc4742e36d2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623268469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.3623268469 |
| Directory | /workspace/24.uart_intr/latest |
| Test location | /workspace/coverage/default/24.uart_long_xfer_wo_dly.1292306176 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 79942671646 ps |
| CPU time | 480.54 seconds |
| Started | Jun 04 12:38:46 PM PDT 24 |
| Finished | Jun 04 12:46:47 PM PDT 24 |
| Peak memory | 200192 kb |
| Host | smart-027ff4bb-5575-4639-8742-2bec9f342e89 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1292306176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.1292306176 |
| Directory | /workspace/24.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/24.uart_loopback.1569789394 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 6816360467 ps |
| CPU time | 6.25 seconds |
| Started | Jun 04 12:38:44 PM PDT 24 |
| Finished | Jun 04 12:38:51 PM PDT 24 |
| Peak memory | 196532 kb |
| Host | smart-ccfd4104-3151-4cf6-8a12-7df265f75220 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1569789394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_loopback.1569789394 |
| Directory | /workspace/24.uart_loopback/latest |
| Test location | /workspace/coverage/default/24.uart_noise_filter.1547431474 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 68149022798 ps |
| CPU time | 31.11 seconds |
| Started | Jun 04 12:38:44 PM PDT 24 |
| Finished | Jun 04 12:39:16 PM PDT 24 |
| Peak memory | 198516 kb |
| Host | smart-5b0abe9f-bd25-455e-b1f5-cc32f8232e32 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1547431474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_noise_filter.1547431474 |
| Directory | /workspace/24.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/24.uart_perf.3567873246 |
| Short name | T1063 |
| Test name | |
| Test status | |
| Simulation time | 14554812316 ps |
| CPU time | 196.48 seconds |
| Started | Jun 04 12:38:44 PM PDT 24 |
| Finished | Jun 04 12:42:02 PM PDT 24 |
| Peak memory | 200184 kb |
| Host | smart-529621e5-85f2-486b-a7b4-41b5a83dae5b |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3567873246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.3567873246 |
| Directory | /workspace/24.uart_perf/latest |
| Test location | /workspace/coverage/default/24.uart_rx_oversample.3447944242 |
| Short name | T963 |
| Test name | |
| Test status | |
| Simulation time | 3204151502 ps |
| CPU time | 21.98 seconds |
| Started | Jun 04 12:38:46 PM PDT 24 |
| Finished | Jun 04 12:39:10 PM PDT 24 |
| Peak memory | 199212 kb |
| Host | smart-91c9a30e-b7e6-4c5c-a609-3de51ba652de |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3447944242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.3447944242 |
| Directory | /workspace/24.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/24.uart_rx_parity_err.3471119771 |
| Short name | T1106 |
| Test name | |
| Test status | |
| Simulation time | 120333171736 ps |
| CPU time | 54.73 seconds |
| Started | Jun 04 12:38:44 PM PDT 24 |
| Finished | Jun 04 12:39:40 PM PDT 24 |
| Peak memory | 200176 kb |
| Host | smart-5e64abda-afa0-4181-87c7-07af981f53e6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3471119771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.3471119771 |
| Directory | /workspace/24.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/24.uart_rx_start_bit_filter.2799788303 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 689269486 ps |
| CPU time | 1.83 seconds |
| Started | Jun 04 12:38:45 PM PDT 24 |
| Finished | Jun 04 12:38:48 PM PDT 24 |
| Peak memory | 195868 kb |
| Host | smart-6b88610b-01af-4633-9e54-4f5996163075 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2799788303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.2799788303 |
| Directory | /workspace/24.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/24.uart_smoke.1284141903 |
| Short name | T1166 |
| Test name | |
| Test status | |
| Simulation time | 274390547 ps |
| CPU time | 2.6 seconds |
| Started | Jun 04 12:38:44 PM PDT 24 |
| Finished | Jun 04 12:38:47 PM PDT 24 |
| Peak memory | 198484 kb |
| Host | smart-bfb492c6-3022-40bc-9eab-36eff35377e0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1284141903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_smoke.1284141903 |
| Directory | /workspace/24.uart_smoke/latest |
| Test location | /workspace/coverage/default/24.uart_stress_all.393065807 |
| Short name | T1037 |
| Test name | |
| Test status | |
| Simulation time | 347722275867 ps |
| CPU time | 578.85 seconds |
| Started | Jun 04 12:38:45 PM PDT 24 |
| Finished | Jun 04 12:48:25 PM PDT 24 |
| Peak memory | 200352 kb |
| Host | smart-a2d7c4a0-fcf4-4d83-9aa8-06460f21ad09 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393065807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.393065807 |
| Directory | /workspace/24.uart_stress_all/latest |
| Test location | /workspace/coverage/default/24.uart_stress_all_with_rand_reset.3292930491 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 364302968032 ps |
| CPU time | 512.53 seconds |
| Started | Jun 04 12:38:44 PM PDT 24 |
| Finished | Jun 04 12:47:17 PM PDT 24 |
| Peak memory | 216664 kb |
| Host | smart-5271c2ab-fd3b-4d05-b4ef-9bfd335e67ac |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292930491 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 24.uart_stress_all_with_rand_reset.3292930491 |
| Directory | /workspace/24.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/24.uart_tx_ovrd.966976103 |
| Short name | T969 |
| Test name | |
| Test status | |
| Simulation time | 6629263582 ps |
| CPU time | 8.33 seconds |
| Started | Jun 04 12:38:46 PM PDT 24 |
| Finished | Jun 04 12:38:55 PM PDT 24 |
| Peak memory | 199556 kb |
| Host | smart-9b52aa42-8efb-47d0-8636-c1e38b150052 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=966976103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.966976103 |
| Directory | /workspace/24.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/24.uart_tx_rx.178993194 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 34278894809 ps |
| CPU time | 8.25 seconds |
| Started | Jun 04 12:38:43 PM PDT 24 |
| Finished | Jun 04 12:38:52 PM PDT 24 |
| Peak memory | 200116 kb |
| Host | smart-ba6b0adf-0d93-4282-afa2-4ec9cba159b1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=178993194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.178993194 |
| Directory | /workspace/24.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/240.uart_fifo_reset.2730289046 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 28580250276 ps |
| CPU time | 71.93 seconds |
| Started | Jun 04 12:42:36 PM PDT 24 |
| Finished | Jun 04 12:43:48 PM PDT 24 |
| Peak memory | 200276 kb |
| Host | smart-d9bf59ef-05eb-42bd-b910-549c1e258b75 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2730289046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.2730289046 |
| Directory | /workspace/240.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/241.uart_fifo_reset.90010388 |
| Short name | T1059 |
| Test name | |
| Test status | |
| Simulation time | 50973882877 ps |
| CPU time | 44.33 seconds |
| Started | Jun 04 12:42:29 PM PDT 24 |
| Finished | Jun 04 12:43:14 PM PDT 24 |
| Peak memory | 200248 kb |
| Host | smart-4928c95d-4730-42b7-8869-fa4de89ec435 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=90010388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.90010388 |
| Directory | /workspace/241.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/242.uart_fifo_reset.1947305405 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 79450496964 ps |
| CPU time | 58.34 seconds |
| Started | Jun 04 12:42:30 PM PDT 24 |
| Finished | Jun 04 12:43:29 PM PDT 24 |
| Peak memory | 200292 kb |
| Host | smart-d8bcec28-7a26-4296-b255-f7a42c0a0890 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1947305405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.1947305405 |
| Directory | /workspace/242.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/243.uart_fifo_reset.550714126 |
| Short name | T1075 |
| Test name | |
| Test status | |
| Simulation time | 42415834878 ps |
| CPU time | 48.86 seconds |
| Started | Jun 04 12:42:31 PM PDT 24 |
| Finished | Jun 04 12:43:20 PM PDT 24 |
| Peak memory | 200196 kb |
| Host | smart-bb968ac2-5266-47d5-bef0-01695c94e6dd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=550714126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.550714126 |
| Directory | /workspace/243.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/244.uart_fifo_reset.4077810098 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 123193267540 ps |
| CPU time | 287.57 seconds |
| Started | Jun 04 12:42:28 PM PDT 24 |
| Finished | Jun 04 12:47:17 PM PDT 24 |
| Peak memory | 200200 kb |
| Host | smart-5e06319f-5c7c-4f7f-ae08-88835abdc85e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4077810098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.4077810098 |
| Directory | /workspace/244.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/245.uart_fifo_reset.379593516 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 59466144982 ps |
| CPU time | 49.33 seconds |
| Started | Jun 04 12:42:29 PM PDT 24 |
| Finished | Jun 04 12:43:19 PM PDT 24 |
| Peak memory | 200188 kb |
| Host | smart-fc53418b-be94-47f9-84e7-9652217c0483 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=379593516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.379593516 |
| Directory | /workspace/245.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/246.uart_fifo_reset.3705523267 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 45455961561 ps |
| CPU time | 18.4 seconds |
| Started | Jun 04 12:42:32 PM PDT 24 |
| Finished | Jun 04 12:42:51 PM PDT 24 |
| Peak memory | 200148 kb |
| Host | smart-95178150-6352-402c-ba7a-d890c3ddc759 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3705523267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.3705523267 |
| Directory | /workspace/246.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/247.uart_fifo_reset.3236493592 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 94035021401 ps |
| CPU time | 201.65 seconds |
| Started | Jun 04 12:42:29 PM PDT 24 |
| Finished | Jun 04 12:45:52 PM PDT 24 |
| Peak memory | 200200 kb |
| Host | smart-66b05d62-6af3-4993-892c-f2f2f57a79ac |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3236493592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.3236493592 |
| Directory | /workspace/247.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/248.uart_fifo_reset.2210876582 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 55040760363 ps |
| CPU time | 43.17 seconds |
| Started | Jun 04 12:42:39 PM PDT 24 |
| Finished | Jun 04 12:43:23 PM PDT 24 |
| Peak memory | 200212 kb |
| Host | smart-d3b0577c-f6c5-44e3-970c-ea8f0f787492 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2210876582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.2210876582 |
| Directory | /workspace/248.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/249.uart_fifo_reset.2644935642 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 133566952326 ps |
| CPU time | 44.33 seconds |
| Started | Jun 04 12:42:41 PM PDT 24 |
| Finished | Jun 04 12:43:25 PM PDT 24 |
| Peak memory | 200204 kb |
| Host | smart-de334dfe-5090-4dd8-859a-202d355fd8a0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2644935642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.2644935642 |
| Directory | /workspace/249.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/25.uart_alert_test.1494897833 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 44843007 ps |
| CPU time | 0.53 seconds |
| Started | Jun 04 12:38:57 PM PDT 24 |
| Finished | Jun 04 12:38:58 PM PDT 24 |
| Peak memory | 194660 kb |
| Host | smart-fbadf0f7-c931-412d-9f80-024c8646d50b |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494897833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.1494897833 |
| Directory | /workspace/25.uart_alert_test/latest |
| Test location | /workspace/coverage/default/25.uart_fifo_full.3527047278 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 326937748744 ps |
| CPU time | 71.68 seconds |
| Started | Jun 04 12:38:53 PM PDT 24 |
| Finished | Jun 04 12:40:06 PM PDT 24 |
| Peak memory | 200144 kb |
| Host | smart-7c5c3378-4866-4219-876d-97140113edd7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3527047278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.3527047278 |
| Directory | /workspace/25.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/25.uart_fifo_overflow.1799662513 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 52480984824 ps |
| CPU time | 26.19 seconds |
| Started | Jun 04 12:38:54 PM PDT 24 |
| Finished | Jun 04 12:39:21 PM PDT 24 |
| Peak memory | 200016 kb |
| Host | smart-11de0f20-b6ce-4a42-8685-79c750cef0db |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1799662513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.1799662513 |
| Directory | /workspace/25.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/25.uart_fifo_reset.2255654515 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 122238452575 ps |
| CPU time | 188.28 seconds |
| Started | Jun 04 12:38:53 PM PDT 24 |
| Finished | Jun 04 12:42:02 PM PDT 24 |
| Peak memory | 200160 kb |
| Host | smart-a6b74ef3-4bd1-48f3-b2f5-6962b18bb9b1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2255654515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.2255654515 |
| Directory | /workspace/25.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/25.uart_intr.2019833170 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 236398865013 ps |
| CPU time | 379.48 seconds |
| Started | Jun 04 12:38:53 PM PDT 24 |
| Finished | Jun 04 12:45:13 PM PDT 24 |
| Peak memory | 200148 kb |
| Host | smart-4fd80441-9ac5-48a9-92a9-d05f847d743f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019833170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.2019833170 |
| Directory | /workspace/25.uart_intr/latest |
| Test location | /workspace/coverage/default/25.uart_long_xfer_wo_dly.3276051622 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 118019118175 ps |
| CPU time | 732.1 seconds |
| Started | Jun 04 12:38:55 PM PDT 24 |
| Finished | Jun 04 12:51:08 PM PDT 24 |
| Peak memory | 200216 kb |
| Host | smart-01ad063e-6ae5-4b73-bd7a-0519d686c0a2 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3276051622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.3276051622 |
| Directory | /workspace/25.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/25.uart_loopback.1637443668 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 7281827590 ps |
| CPU time | 14.98 seconds |
| Started | Jun 04 12:38:54 PM PDT 24 |
| Finished | Jun 04 12:39:11 PM PDT 24 |
| Peak memory | 199532 kb |
| Host | smart-daf5face-b302-4397-b7d4-612b0fe8995d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1637443668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_loopback.1637443668 |
| Directory | /workspace/25.uart_loopback/latest |
| Test location | /workspace/coverage/default/25.uart_noise_filter.2949029529 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 96732018599 ps |
| CPU time | 115.62 seconds |
| Started | Jun 04 12:38:53 PM PDT 24 |
| Finished | Jun 04 12:40:50 PM PDT 24 |
| Peak memory | 199492 kb |
| Host | smart-48577f57-f344-4364-9aec-43fb6196eed1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2949029529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_noise_filter.2949029529 |
| Directory | /workspace/25.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/25.uart_perf.600323454 |
| Short name | T962 |
| Test name | |
| Test status | |
| Simulation time | 16800123248 ps |
| CPU time | 259.13 seconds |
| Started | Jun 04 12:38:54 PM PDT 24 |
| Finished | Jun 04 12:43:14 PM PDT 24 |
| Peak memory | 200308 kb |
| Host | smart-79cd4a75-4a98-4910-9651-8a92536f7d63 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=600323454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.600323454 |
| Directory | /workspace/25.uart_perf/latest |
| Test location | /workspace/coverage/default/25.uart_rx_oversample.3420170678 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 3540088909 ps |
| CPU time | 28.03 seconds |
| Started | Jun 04 12:38:55 PM PDT 24 |
| Finished | Jun 04 12:39:24 PM PDT 24 |
| Peak memory | 198420 kb |
| Host | smart-76d2d4d3-98d6-41bf-b176-6f0fafad86fb |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3420170678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.3420170678 |
| Directory | /workspace/25.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/25.uart_rx_parity_err.1287593281 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 22024791048 ps |
| CPU time | 34.39 seconds |
| Started | Jun 04 12:38:54 PM PDT 24 |
| Finished | Jun 04 12:39:29 PM PDT 24 |
| Peak memory | 200208 kb |
| Host | smart-25486895-5bd3-48f5-ad52-a63bae52a0ef |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1287593281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.1287593281 |
| Directory | /workspace/25.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/25.uart_rx_start_bit_filter.3307039483 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 686348241 ps |
| CPU time | 1.24 seconds |
| Started | Jun 04 12:38:54 PM PDT 24 |
| Finished | Jun 04 12:38:57 PM PDT 24 |
| Peak memory | 196012 kb |
| Host | smart-4f945bdc-abbe-489d-9d63-0d83962eb49f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3307039483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.3307039483 |
| Directory | /workspace/25.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/25.uart_smoke.74839318 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 268739628 ps |
| CPU time | 1.5 seconds |
| Started | Jun 04 12:38:43 PM PDT 24 |
| Finished | Jun 04 12:38:45 PM PDT 24 |
| Peak memory | 198500 kb |
| Host | smart-7f9652cf-9e48-44de-8d87-e061891346e7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=74839318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_smoke.74839318 |
| Directory | /workspace/25.uart_smoke/latest |
| Test location | /workspace/coverage/default/25.uart_stress_all_with_rand_reset.2294104117 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 227082099695 ps |
| CPU time | 833.44 seconds |
| Started | Jun 04 12:38:53 PM PDT 24 |
| Finished | Jun 04 12:52:48 PM PDT 24 |
| Peak memory | 228236 kb |
| Host | smart-979f4b21-a0ba-4470-87bd-cf82d9bafb9f |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294104117 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 25.uart_stress_all_with_rand_reset.2294104117 |
| Directory | /workspace/25.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/25.uart_tx_ovrd.2980609954 |
| Short name | T1110 |
| Test name | |
| Test status | |
| Simulation time | 1858592292 ps |
| CPU time | 2.14 seconds |
| Started | Jun 04 12:38:54 PM PDT 24 |
| Finished | Jun 04 12:38:57 PM PDT 24 |
| Peak memory | 198552 kb |
| Host | smart-d7c00c48-e743-4c8f-8512-a61f60cbde62 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2980609954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.2980609954 |
| Directory | /workspace/25.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/25.uart_tx_rx.1438977414 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 43850167155 ps |
| CPU time | 20.63 seconds |
| Started | Jun 04 12:38:52 PM PDT 24 |
| Finished | Jun 04 12:39:14 PM PDT 24 |
| Peak memory | 200208 kb |
| Host | smart-344d4728-49f2-474a-841d-efb36cebee8c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1438977414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.1438977414 |
| Directory | /workspace/25.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/250.uart_fifo_reset.862105096 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 13764363742 ps |
| CPU time | 30.65 seconds |
| Started | Jun 04 12:42:39 PM PDT 24 |
| Finished | Jun 04 12:43:10 PM PDT 24 |
| Peak memory | 200220 kb |
| Host | smart-c74aac32-f2d7-47b5-95f3-bfc78058e511 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=862105096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.862105096 |
| Directory | /workspace/250.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/251.uart_fifo_reset.3196244011 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 50402487468 ps |
| CPU time | 25.54 seconds |
| Started | Jun 04 12:42:42 PM PDT 24 |
| Finished | Jun 04 12:43:08 PM PDT 24 |
| Peak memory | 200160 kb |
| Host | smart-cf18203a-4842-4c7e-8ab0-85e92ac8392f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3196244011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.3196244011 |
| Directory | /workspace/251.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/252.uart_fifo_reset.2372776528 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 89415444772 ps |
| CPU time | 26.66 seconds |
| Started | Jun 04 12:42:39 PM PDT 24 |
| Finished | Jun 04 12:43:06 PM PDT 24 |
| Peak memory | 200364 kb |
| Host | smart-819bc83b-f5ad-4ea0-9f7f-ebfe076dcbfe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2372776528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.2372776528 |
| Directory | /workspace/252.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/253.uart_fifo_reset.2307887558 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 17460272241 ps |
| CPU time | 11.24 seconds |
| Started | Jun 04 12:42:38 PM PDT 24 |
| Finished | Jun 04 12:42:50 PM PDT 24 |
| Peak memory | 200336 kb |
| Host | smart-5b799351-7245-4eb6-ba6a-57f05e9212b4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2307887558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.2307887558 |
| Directory | /workspace/253.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/254.uart_fifo_reset.3547142590 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 69204073577 ps |
| CPU time | 35.72 seconds |
| Started | Jun 04 12:42:40 PM PDT 24 |
| Finished | Jun 04 12:43:16 PM PDT 24 |
| Peak memory | 200104 kb |
| Host | smart-3cd6d0ee-ac3d-4df2-8354-653ac3cb039b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3547142590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.3547142590 |
| Directory | /workspace/254.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/255.uart_fifo_reset.801503168 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 15652353580 ps |
| CPU time | 14.42 seconds |
| Started | Jun 04 12:42:39 PM PDT 24 |
| Finished | Jun 04 12:42:54 PM PDT 24 |
| Peak memory | 200180 kb |
| Host | smart-189bb92b-8294-4689-a47c-c6cb3e1b4170 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=801503168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.801503168 |
| Directory | /workspace/255.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/256.uart_fifo_reset.2672969723 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 89158898391 ps |
| CPU time | 161.93 seconds |
| Started | Jun 04 12:42:39 PM PDT 24 |
| Finished | Jun 04 12:45:21 PM PDT 24 |
| Peak memory | 200224 kb |
| Host | smart-65b35390-3f40-4e1c-b006-43ba85d62148 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2672969723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.2672969723 |
| Directory | /workspace/256.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/257.uart_fifo_reset.3474604507 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 121741126381 ps |
| CPU time | 13.35 seconds |
| Started | Jun 04 12:42:40 PM PDT 24 |
| Finished | Jun 04 12:42:54 PM PDT 24 |
| Peak memory | 200132 kb |
| Host | smart-2b0212f2-5a06-4001-a1ff-5709aaac10ec |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3474604507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.3474604507 |
| Directory | /workspace/257.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/258.uart_fifo_reset.1281948068 |
| Short name | T925 |
| Test name | |
| Test status | |
| Simulation time | 11739887067 ps |
| CPU time | 21.88 seconds |
| Started | Jun 04 12:42:39 PM PDT 24 |
| Finished | Jun 04 12:43:01 PM PDT 24 |
| Peak memory | 200332 kb |
| Host | smart-401b64e1-e332-4bed-a110-3c48a5a4f581 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1281948068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.1281948068 |
| Directory | /workspace/258.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/259.uart_fifo_reset.3165116153 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 14766028082 ps |
| CPU time | 26.84 seconds |
| Started | Jun 04 12:42:40 PM PDT 24 |
| Finished | Jun 04 12:43:08 PM PDT 24 |
| Peak memory | 199200 kb |
| Host | smart-1a104360-55ff-4163-b4e1-41643e06a0b5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3165116153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.3165116153 |
| Directory | /workspace/259.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/26.uart_alert_test.3158826803 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 34015076 ps |
| CPU time | 0.55 seconds |
| Started | Jun 04 12:38:52 PM PDT 24 |
| Finished | Jun 04 12:38:54 PM PDT 24 |
| Peak memory | 194600 kb |
| Host | smart-3f105c6c-892b-43a0-a405-00849d0f4eac |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158826803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.3158826803 |
| Directory | /workspace/26.uart_alert_test/latest |
| Test location | /workspace/coverage/default/26.uart_fifo_full.1742778429 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 118151465183 ps |
| CPU time | 503.95 seconds |
| Started | Jun 04 12:38:53 PM PDT 24 |
| Finished | Jun 04 12:47:19 PM PDT 24 |
| Peak memory | 200144 kb |
| Host | smart-7412d73a-42eb-48ff-8505-d3c1603bda71 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1742778429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.1742778429 |
| Directory | /workspace/26.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/26.uart_fifo_overflow.1684791683 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 105126995666 ps |
| CPU time | 49.07 seconds |
| Started | Jun 04 12:38:58 PM PDT 24 |
| Finished | Jun 04 12:39:48 PM PDT 24 |
| Peak memory | 200152 kb |
| Host | smart-61ca4de1-0e18-41b9-ab7c-6cad251558eb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1684791683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.1684791683 |
| Directory | /workspace/26.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/26.uart_fifo_reset.3710815611 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 76275006257 ps |
| CPU time | 279.23 seconds |
| Started | Jun 04 12:38:55 PM PDT 24 |
| Finished | Jun 04 12:43:35 PM PDT 24 |
| Peak memory | 200352 kb |
| Host | smart-df9e762a-0ed2-4d82-b4dd-6f334faed1e9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3710815611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.3710815611 |
| Directory | /workspace/26.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/26.uart_intr.2733795607 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 255741996790 ps |
| CPU time | 407.25 seconds |
| Started | Jun 04 12:38:54 PM PDT 24 |
| Finished | Jun 04 12:45:42 PM PDT 24 |
| Peak memory | 198468 kb |
| Host | smart-72b620b0-c08c-46e3-830f-fb3056af3b65 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733795607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.2733795607 |
| Directory | /workspace/26.uart_intr/latest |
| Test location | /workspace/coverage/default/26.uart_long_xfer_wo_dly.1213310984 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 93313015031 ps |
| CPU time | 315.21 seconds |
| Started | Jun 04 12:38:53 PM PDT 24 |
| Finished | Jun 04 12:44:09 PM PDT 24 |
| Peak memory | 200260 kb |
| Host | smart-3fdff2fd-8c6c-4834-8da3-e0eec07c9172 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1213310984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.1213310984 |
| Directory | /workspace/26.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/26.uart_loopback.546908519 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 3281073948 ps |
| CPU time | 2.29 seconds |
| Started | Jun 04 12:38:53 PM PDT 24 |
| Finished | Jun 04 12:38:56 PM PDT 24 |
| Peak memory | 199000 kb |
| Host | smart-ab0db823-5217-4b0b-9dc0-73a7375467a8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=546908519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_loopback.546908519 |
| Directory | /workspace/26.uart_loopback/latest |
| Test location | /workspace/coverage/default/26.uart_noise_filter.2624636646 |
| Short name | T953 |
| Test name | |
| Test status | |
| Simulation time | 16317900409 ps |
| CPU time | 10.19 seconds |
| Started | Jun 04 12:38:55 PM PDT 24 |
| Finished | Jun 04 12:39:06 PM PDT 24 |
| Peak memory | 194920 kb |
| Host | smart-837b799f-9b5a-4044-84a3-2bdf140a3511 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2624636646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_noise_filter.2624636646 |
| Directory | /workspace/26.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/26.uart_perf.3709776329 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 9742485116 ps |
| CPU time | 285.29 seconds |
| Started | Jun 04 12:38:58 PM PDT 24 |
| Finished | Jun 04 12:43:44 PM PDT 24 |
| Peak memory | 200184 kb |
| Host | smart-37f633fc-9965-4391-84ba-314ae4c4ad24 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3709776329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.3709776329 |
| Directory | /workspace/26.uart_perf/latest |
| Test location | /workspace/coverage/default/26.uart_rx_oversample.1734696435 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 2341098005 ps |
| CPU time | 3.39 seconds |
| Started | Jun 04 12:38:52 PM PDT 24 |
| Finished | Jun 04 12:38:57 PM PDT 24 |
| Peak memory | 198552 kb |
| Host | smart-81b7c353-f9db-4358-821e-c9893f66a6f4 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1734696435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.1734696435 |
| Directory | /workspace/26.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/26.uart_rx_parity_err.3012033638 |
| Short name | T1005 |
| Test name | |
| Test status | |
| Simulation time | 20041772750 ps |
| CPU time | 38.75 seconds |
| Started | Jun 04 12:38:54 PM PDT 24 |
| Finished | Jun 04 12:39:34 PM PDT 24 |
| Peak memory | 199968 kb |
| Host | smart-ba26fe65-bef1-4a0a-bfc0-f398377cd1c4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3012033638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.3012033638 |
| Directory | /workspace/26.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/26.uart_rx_start_bit_filter.2038204293 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 3068568265 ps |
| CPU time | 1.77 seconds |
| Started | Jun 04 12:38:55 PM PDT 24 |
| Finished | Jun 04 12:38:58 PM PDT 24 |
| Peak memory | 196172 kb |
| Host | smart-00e894fd-d182-4d76-8351-4f294ec4f7c5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2038204293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.2038204293 |
| Directory | /workspace/26.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/26.uart_smoke.859528418 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 502826129 ps |
| CPU time | 2.53 seconds |
| Started | Jun 04 12:38:52 PM PDT 24 |
| Finished | Jun 04 12:38:55 PM PDT 24 |
| Peak memory | 200040 kb |
| Host | smart-a519ab78-777d-49df-8031-585f1d51464a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=859528418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_smoke.859528418 |
| Directory | /workspace/26.uart_smoke/latest |
| Test location | /workspace/coverage/default/26.uart_stress_all.1586658461 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 688564670986 ps |
| CPU time | 747.74 seconds |
| Started | Jun 04 12:38:57 PM PDT 24 |
| Finished | Jun 04 12:51:26 PM PDT 24 |
| Peak memory | 208764 kb |
| Host | smart-87726e29-5f62-4263-8f87-6d2368c23e00 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586658461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.1586658461 |
| Directory | /workspace/26.uart_stress_all/latest |
| Test location | /workspace/coverage/default/26.uart_stress_all_with_rand_reset.1617565986 |
| Short name | T944 |
| Test name | |
| Test status | |
| Simulation time | 50169284728 ps |
| CPU time | 387.26 seconds |
| Started | Jun 04 12:38:53 PM PDT 24 |
| Finished | Jun 04 12:45:21 PM PDT 24 |
| Peak memory | 215692 kb |
| Host | smart-c7017c0f-fad7-4871-97f9-cfd61dd5b852 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617565986 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 26.uart_stress_all_with_rand_reset.1617565986 |
| Directory | /workspace/26.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/26.uart_tx_ovrd.662360068 |
| Short name | T1083 |
| Test name | |
| Test status | |
| Simulation time | 6607639018 ps |
| CPU time | 9.45 seconds |
| Started | Jun 04 12:38:52 PM PDT 24 |
| Finished | Jun 04 12:39:03 PM PDT 24 |
| Peak memory | 200040 kb |
| Host | smart-fd368da6-a2d7-4db1-8687-9d5102355dad |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=662360068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.662360068 |
| Directory | /workspace/26.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/26.uart_tx_rx.1923068752 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 16163448839 ps |
| CPU time | 28.01 seconds |
| Started | Jun 04 12:38:53 PM PDT 24 |
| Finished | Jun 04 12:39:22 PM PDT 24 |
| Peak memory | 200284 kb |
| Host | smart-3529d7fa-275f-4ab2-9955-d539bc81a22e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1923068752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.1923068752 |
| Directory | /workspace/26.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/261.uart_fifo_reset.1312875258 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 55825135182 ps |
| CPU time | 43.87 seconds |
| Started | Jun 04 12:42:39 PM PDT 24 |
| Finished | Jun 04 12:43:24 PM PDT 24 |
| Peak memory | 200176 kb |
| Host | smart-18b8b261-c0aa-48fb-b80f-17023790040d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1312875258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.1312875258 |
| Directory | /workspace/261.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/262.uart_fifo_reset.2321213315 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 51382998112 ps |
| CPU time | 20.54 seconds |
| Started | Jun 04 12:42:38 PM PDT 24 |
| Finished | Jun 04 12:43:00 PM PDT 24 |
| Peak memory | 199828 kb |
| Host | smart-4d7aec88-7017-46c8-9fc2-12a249bba94a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2321213315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.2321213315 |
| Directory | /workspace/262.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/263.uart_fifo_reset.4292089840 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 11104306715 ps |
| CPU time | 10.68 seconds |
| Started | Jun 04 12:42:40 PM PDT 24 |
| Finished | Jun 04 12:42:51 PM PDT 24 |
| Peak memory | 200156 kb |
| Host | smart-ae3f541c-1ab3-439b-a2a5-24a4d6f2ee99 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4292089840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.4292089840 |
| Directory | /workspace/263.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/264.uart_fifo_reset.2644189208 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 98775578564 ps |
| CPU time | 157.98 seconds |
| Started | Jun 04 12:42:40 PM PDT 24 |
| Finished | Jun 04 12:45:19 PM PDT 24 |
| Peak memory | 200152 kb |
| Host | smart-28d3ae2e-3312-4efb-930f-b86372022b89 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2644189208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.2644189208 |
| Directory | /workspace/264.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/265.uart_fifo_reset.2602737069 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 12220863684 ps |
| CPU time | 17.18 seconds |
| Started | Jun 04 12:42:38 PM PDT 24 |
| Finished | Jun 04 12:42:56 PM PDT 24 |
| Peak memory | 199044 kb |
| Host | smart-5f72ce40-acf5-47ee-9f06-1b1ea5193a15 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2602737069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.2602737069 |
| Directory | /workspace/265.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/266.uart_fifo_reset.2052255858 |
| Short name | T1044 |
| Test name | |
| Test status | |
| Simulation time | 140177928577 ps |
| CPU time | 62.63 seconds |
| Started | Jun 04 12:42:40 PM PDT 24 |
| Finished | Jun 04 12:43:43 PM PDT 24 |
| Peak memory | 200092 kb |
| Host | smart-bf0b3428-a318-4fcf-b1c3-07cb853601b3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2052255858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.2052255858 |
| Directory | /workspace/266.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/268.uart_fifo_reset.2239847687 |
| Short name | T1169 |
| Test name | |
| Test status | |
| Simulation time | 141394669359 ps |
| CPU time | 114.33 seconds |
| Started | Jun 04 12:42:49 PM PDT 24 |
| Finished | Jun 04 12:44:44 PM PDT 24 |
| Peak memory | 200172 kb |
| Host | smart-2c160ccb-b46c-46f7-acf5-22ad5477a7b0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2239847687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.2239847687 |
| Directory | /workspace/268.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/269.uart_fifo_reset.2637942431 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 59481434948 ps |
| CPU time | 48.77 seconds |
| Started | Jun 04 12:42:50 PM PDT 24 |
| Finished | Jun 04 12:43:40 PM PDT 24 |
| Peak memory | 199776 kb |
| Host | smart-7eeb0dde-7843-46d6-b83b-5a926d163fdd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2637942431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.2637942431 |
| Directory | /workspace/269.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/27.uart_alert_test.2493164715 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 171513415 ps |
| CPU time | 0.54 seconds |
| Started | Jun 04 12:38:59 PM PDT 24 |
| Finished | Jun 04 12:39:00 PM PDT 24 |
| Peak memory | 195616 kb |
| Host | smart-3ea1dc67-930b-40f0-bee0-53f4f82b9c75 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493164715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.2493164715 |
| Directory | /workspace/27.uart_alert_test/latest |
| Test location | /workspace/coverage/default/27.uart_fifo_full.2336167969 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 187659192960 ps |
| CPU time | 66.45 seconds |
| Started | Jun 04 12:38:58 PM PDT 24 |
| Finished | Jun 04 12:40:06 PM PDT 24 |
| Peak memory | 200216 kb |
| Host | smart-5349e3e2-f4d4-46dd-9049-99aa7e221621 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2336167969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.2336167969 |
| Directory | /workspace/27.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/27.uart_fifo_overflow.3238261068 |
| Short name | T1117 |
| Test name | |
| Test status | |
| Simulation time | 39846740924 ps |
| CPU time | 58.47 seconds |
| Started | Jun 04 12:38:54 PM PDT 24 |
| Finished | Jun 04 12:39:54 PM PDT 24 |
| Peak memory | 200116 kb |
| Host | smart-fe7716f2-a7cf-4cdf-a337-7e48c3301ada |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3238261068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.3238261068 |
| Directory | /workspace/27.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/27.uart_fifo_reset.1995828233 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 405609457950 ps |
| CPU time | 36.14 seconds |
| Started | Jun 04 12:38:55 PM PDT 24 |
| Finished | Jun 04 12:39:32 PM PDT 24 |
| Peak memory | 200368 kb |
| Host | smart-51886e7e-7cc8-4eb8-b9be-195e487b857e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1995828233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.1995828233 |
| Directory | /workspace/27.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/27.uart_intr.4090039346 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 17071549991 ps |
| CPU time | 26.44 seconds |
| Started | Jun 04 12:38:54 PM PDT 24 |
| Finished | Jun 04 12:39:22 PM PDT 24 |
| Peak memory | 200264 kb |
| Host | smart-09ab941c-5b6e-4576-855a-dfc1902741e2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090039346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.4090039346 |
| Directory | /workspace/27.uart_intr/latest |
| Test location | /workspace/coverage/default/27.uart_long_xfer_wo_dly.3965613751 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 104687494174 ps |
| CPU time | 808.35 seconds |
| Started | Jun 04 12:38:59 PM PDT 24 |
| Finished | Jun 04 12:52:28 PM PDT 24 |
| Peak memory | 200184 kb |
| Host | smart-3910b295-91ad-44a1-a46e-bb0ca43b0e51 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3965613751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.3965613751 |
| Directory | /workspace/27.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/27.uart_loopback.2453318746 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 7558991544 ps |
| CPU time | 7.25 seconds |
| Started | Jun 04 12:39:00 PM PDT 24 |
| Finished | Jun 04 12:39:08 PM PDT 24 |
| Peak memory | 198904 kb |
| Host | smart-0dcb6f4b-6e78-4156-9dfc-b8e2fb42cd22 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2453318746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_loopback.2453318746 |
| Directory | /workspace/27.uart_loopback/latest |
| Test location | /workspace/coverage/default/27.uart_noise_filter.2211068248 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 143970869813 ps |
| CPU time | 210.04 seconds |
| Started | Jun 04 12:39:03 PM PDT 24 |
| Finished | Jun 04 12:42:34 PM PDT 24 |
| Peak memory | 200288 kb |
| Host | smart-1565b5f1-1a6b-4b93-8772-1cb65bae8b7c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2211068248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_noise_filter.2211068248 |
| Directory | /workspace/27.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/27.uart_perf.3736190191 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 21528164369 ps |
| CPU time | 1140.55 seconds |
| Started | Jun 04 12:39:01 PM PDT 24 |
| Finished | Jun 04 12:58:04 PM PDT 24 |
| Peak memory | 200196 kb |
| Host | smart-b96593d6-0f89-4904-9b92-de9bc0c20d54 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3736190191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.3736190191 |
| Directory | /workspace/27.uart_perf/latest |
| Test location | /workspace/coverage/default/27.uart_rx_oversample.1374622502 |
| Short name | T1158 |
| Test name | |
| Test status | |
| Simulation time | 6450945694 ps |
| CPU time | 56.72 seconds |
| Started | Jun 04 12:38:58 PM PDT 24 |
| Finished | Jun 04 12:39:56 PM PDT 24 |
| Peak memory | 200176 kb |
| Host | smart-220d8086-4e15-4931-a3f3-f7281aedff15 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1374622502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.1374622502 |
| Directory | /workspace/27.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/27.uart_rx_parity_err.1190671537 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 134866305615 ps |
| CPU time | 239.06 seconds |
| Started | Jun 04 12:39:01 PM PDT 24 |
| Finished | Jun 04 12:43:02 PM PDT 24 |
| Peak memory | 200196 kb |
| Host | smart-9b29ff0e-9d7e-4629-97c0-4b8756978c1f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1190671537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.1190671537 |
| Directory | /workspace/27.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/27.uart_rx_start_bit_filter.242134072 |
| Short name | T1087 |
| Test name | |
| Test status | |
| Simulation time | 43430712499 ps |
| CPU time | 11.25 seconds |
| Started | Jun 04 12:39:02 PM PDT 24 |
| Finished | Jun 04 12:39:14 PM PDT 24 |
| Peak memory | 195944 kb |
| Host | smart-976153a9-7062-4155-afd2-0cd9d615f643 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=242134072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.242134072 |
| Directory | /workspace/27.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/27.uart_smoke.1870584468 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 475921415 ps |
| CPU time | 2.19 seconds |
| Started | Jun 04 12:38:54 PM PDT 24 |
| Finished | Jun 04 12:38:58 PM PDT 24 |
| Peak memory | 198768 kb |
| Host | smart-63ae025d-0991-4f29-8ead-69d69de5173a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1870584468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_smoke.1870584468 |
| Directory | /workspace/27.uart_smoke/latest |
| Test location | /workspace/coverage/default/27.uart_stress_all.214951597 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 147002891592 ps |
| CPU time | 347.98 seconds |
| Started | Jun 04 12:39:01 PM PDT 24 |
| Finished | Jun 04 12:44:50 PM PDT 24 |
| Peak memory | 200164 kb |
| Host | smart-02c0fa33-6526-4586-813e-03ab2d8c7ef6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214951597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.214951597 |
| Directory | /workspace/27.uart_stress_all/latest |
| Test location | /workspace/coverage/default/27.uart_stress_all_with_rand_reset.1325453349 |
| Short name | T967 |
| Test name | |
| Test status | |
| Simulation time | 12519679754 ps |
| CPU time | 98.02 seconds |
| Started | Jun 04 12:39:00 PM PDT 24 |
| Finished | Jun 04 12:40:38 PM PDT 24 |
| Peak memory | 208588 kb |
| Host | smart-ccaf46cc-01f4-4a50-b3c9-17ddd5998b99 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325453349 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 27.uart_stress_all_with_rand_reset.1325453349 |
| Directory | /workspace/27.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/27.uart_tx_ovrd.2894903267 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 1764981361 ps |
| CPU time | 3.72 seconds |
| Started | Jun 04 12:39:00 PM PDT 24 |
| Finished | Jun 04 12:39:05 PM PDT 24 |
| Peak memory | 198968 kb |
| Host | smart-9f5b92d4-e538-48b5-bda3-f70375debe86 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2894903267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.2894903267 |
| Directory | /workspace/27.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/27.uart_tx_rx.2769433159 |
| Short name | T956 |
| Test name | |
| Test status | |
| Simulation time | 71664295148 ps |
| CPU time | 34.81 seconds |
| Started | Jun 04 12:38:54 PM PDT 24 |
| Finished | Jun 04 12:39:30 PM PDT 24 |
| Peak memory | 200284 kb |
| Host | smart-b11c4f21-127e-4a96-92ab-38306e1986ae |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2769433159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.2769433159 |
| Directory | /workspace/27.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/270.uart_fifo_reset.3478772260 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 18587790427 ps |
| CPU time | 42.64 seconds |
| Started | Jun 04 12:42:49 PM PDT 24 |
| Finished | Jun 04 12:43:32 PM PDT 24 |
| Peak memory | 200188 kb |
| Host | smart-92230b9d-150d-4e5f-a041-40ddbfe89b9a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3478772260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.3478772260 |
| Directory | /workspace/270.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/271.uart_fifo_reset.180568838 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 18741499949 ps |
| CPU time | 30.02 seconds |
| Started | Jun 04 12:42:53 PM PDT 24 |
| Finished | Jun 04 12:43:23 PM PDT 24 |
| Peak memory | 200264 kb |
| Host | smart-f55680aa-628e-4bae-a4ba-a365f81062e2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=180568838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.180568838 |
| Directory | /workspace/271.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/272.uart_fifo_reset.2352509427 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 159259940058 ps |
| CPU time | 303.73 seconds |
| Started | Jun 04 12:42:51 PM PDT 24 |
| Finished | Jun 04 12:47:56 PM PDT 24 |
| Peak memory | 200220 kb |
| Host | smart-50f2274c-4034-4c65-ad50-6bee4af3e6a9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2352509427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.2352509427 |
| Directory | /workspace/272.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/273.uart_fifo_reset.4093809084 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 12750932277 ps |
| CPU time | 22.02 seconds |
| Started | Jun 04 12:42:50 PM PDT 24 |
| Finished | Jun 04 12:43:13 PM PDT 24 |
| Peak memory | 200324 kb |
| Host | smart-88d72a66-dd4e-4558-b99d-e5907fc19ec6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4093809084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.4093809084 |
| Directory | /workspace/273.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/274.uart_fifo_reset.1098045630 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 17153459204 ps |
| CPU time | 26.84 seconds |
| Started | Jun 04 12:42:50 PM PDT 24 |
| Finished | Jun 04 12:43:17 PM PDT 24 |
| Peak memory | 200108 kb |
| Host | smart-9d1895fa-364a-4ea3-bea3-e11d2049214e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1098045630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.1098045630 |
| Directory | /workspace/274.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/275.uart_fifo_reset.2387668792 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 18136868468 ps |
| CPU time | 9.12 seconds |
| Started | Jun 04 12:42:51 PM PDT 24 |
| Finished | Jun 04 12:43:00 PM PDT 24 |
| Peak memory | 199988 kb |
| Host | smart-9306dfae-c3b5-49c7-b5d9-bec58ee49337 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2387668792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.2387668792 |
| Directory | /workspace/275.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/276.uart_fifo_reset.1908988208 |
| Short name | T1007 |
| Test name | |
| Test status | |
| Simulation time | 36529107462 ps |
| CPU time | 34.94 seconds |
| Started | Jun 04 12:42:50 PM PDT 24 |
| Finished | Jun 04 12:43:26 PM PDT 24 |
| Peak memory | 200144 kb |
| Host | smart-6cfcc2ee-8a67-45b2-9d36-99441b40ad74 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1908988208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.1908988208 |
| Directory | /workspace/276.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/277.uart_fifo_reset.3725431978 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 174451790787 ps |
| CPU time | 65.35 seconds |
| Started | Jun 04 12:42:50 PM PDT 24 |
| Finished | Jun 04 12:43:57 PM PDT 24 |
| Peak memory | 200176 kb |
| Host | smart-859692a6-d5da-432e-b535-6fb176da06b6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3725431978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.3725431978 |
| Directory | /workspace/277.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/278.uart_fifo_reset.2189440585 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 145701728060 ps |
| CPU time | 81.58 seconds |
| Started | Jun 04 12:42:50 PM PDT 24 |
| Finished | Jun 04 12:44:12 PM PDT 24 |
| Peak memory | 200324 kb |
| Host | smart-d35ff54a-bc4f-49af-98d1-e5c1812010f9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2189440585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.2189440585 |
| Directory | /workspace/278.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/279.uart_fifo_reset.3430980623 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 22922423736 ps |
| CPU time | 43.2 seconds |
| Started | Jun 04 12:42:50 PM PDT 24 |
| Finished | Jun 04 12:43:33 PM PDT 24 |
| Peak memory | 200152 kb |
| Host | smart-edf6b07c-9a51-41fd-bc93-f9a7a832c9ec |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3430980623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.3430980623 |
| Directory | /workspace/279.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/28.uart_alert_test.1870949765 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 25207804 ps |
| CPU time | 0.57 seconds |
| Started | Jun 04 12:39:07 PM PDT 24 |
| Finished | Jun 04 12:39:09 PM PDT 24 |
| Peak memory | 195724 kb |
| Host | smart-f998c386-5805-4f39-a499-1d08dddc069f |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870949765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.1870949765 |
| Directory | /workspace/28.uart_alert_test/latest |
| Test location | /workspace/coverage/default/28.uart_fifo_full.2606812202 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 86371781326 ps |
| CPU time | 128.85 seconds |
| Started | Jun 04 12:39:01 PM PDT 24 |
| Finished | Jun 04 12:41:11 PM PDT 24 |
| Peak memory | 200148 kb |
| Host | smart-98b7f750-550c-4f7d-a58f-556edf3701a1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2606812202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.2606812202 |
| Directory | /workspace/28.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/28.uart_fifo_overflow.1323314047 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 113108282426 ps |
| CPU time | 169.44 seconds |
| Started | Jun 04 12:39:00 PM PDT 24 |
| Finished | Jun 04 12:41:50 PM PDT 24 |
| Peak memory | 200108 kb |
| Host | smart-cf765124-0fb3-494a-af2b-030469937d60 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1323314047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.1323314047 |
| Directory | /workspace/28.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/28.uart_fifo_reset.2897575581 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 62877428039 ps |
| CPU time | 58.74 seconds |
| Started | Jun 04 12:39:00 PM PDT 24 |
| Finished | Jun 04 12:40:00 PM PDT 24 |
| Peak memory | 200212 kb |
| Host | smart-af40b6de-8b9c-43de-81a9-3255e1aab9fc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2897575581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.2897575581 |
| Directory | /workspace/28.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/28.uart_intr.2557497461 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 30021437043 ps |
| CPU time | 15.03 seconds |
| Started | Jun 04 12:39:00 PM PDT 24 |
| Finished | Jun 04 12:39:17 PM PDT 24 |
| Peak memory | 200132 kb |
| Host | smart-e51e4ed9-d6f5-484d-9726-a2ba32b49a7b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557497461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.2557497461 |
| Directory | /workspace/28.uart_intr/latest |
| Test location | /workspace/coverage/default/28.uart_long_xfer_wo_dly.630129182 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 157331258442 ps |
| CPU time | 324.52 seconds |
| Started | Jun 04 12:39:01 PM PDT 24 |
| Finished | Jun 04 12:44:28 PM PDT 24 |
| Peak memory | 200180 kb |
| Host | smart-23538416-4d66-498f-afcf-65985c8bda7f |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=630129182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.630129182 |
| Directory | /workspace/28.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/28.uart_loopback.3188778906 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 7670240776 ps |
| CPU time | 7.55 seconds |
| Started | Jun 04 12:39:01 PM PDT 24 |
| Finished | Jun 04 12:39:11 PM PDT 24 |
| Peak memory | 200048 kb |
| Host | smart-c0dc374e-264b-43f2-bfff-ede7fb55b7c2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3188778906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_loopback.3188778906 |
| Directory | /workspace/28.uart_loopback/latest |
| Test location | /workspace/coverage/default/28.uart_noise_filter.107510483 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 68463149281 ps |
| CPU time | 116.09 seconds |
| Started | Jun 04 12:39:05 PM PDT 24 |
| Finished | Jun 04 12:41:02 PM PDT 24 |
| Peak memory | 200332 kb |
| Host | smart-bb66825d-ce9e-4d46-b922-17ed7ac338c1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=107510483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_noise_filter.107510483 |
| Directory | /workspace/28.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/28.uart_perf.2801230613 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 20346232732 ps |
| CPU time | 51.42 seconds |
| Started | Jun 04 12:39:01 PM PDT 24 |
| Finished | Jun 04 12:39:53 PM PDT 24 |
| Peak memory | 200332 kb |
| Host | smart-18391936-7913-4046-8f4c-a5f035cc58e5 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2801230613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.2801230613 |
| Directory | /workspace/28.uart_perf/latest |
| Test location | /workspace/coverage/default/28.uart_rx_oversample.2404099214 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 4166886236 ps |
| CPU time | 4.01 seconds |
| Started | Jun 04 12:39:00 PM PDT 24 |
| Finished | Jun 04 12:39:05 PM PDT 24 |
| Peak memory | 198332 kb |
| Host | smart-b1899ca4-1571-436d-8b0e-4fb77eaa2091 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2404099214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.2404099214 |
| Directory | /workspace/28.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/28.uart_rx_parity_err.2782387897 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 119690188431 ps |
| CPU time | 62.76 seconds |
| Started | Jun 04 12:39:00 PM PDT 24 |
| Finished | Jun 04 12:40:05 PM PDT 24 |
| Peak memory | 200152 kb |
| Host | smart-ea938de8-59ed-46f7-8554-c0718ffe0507 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2782387897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.2782387897 |
| Directory | /workspace/28.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/28.uart_rx_start_bit_filter.2159031421 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 44538639945 ps |
| CPU time | 17.04 seconds |
| Started | Jun 04 12:39:01 PM PDT 24 |
| Finished | Jun 04 12:39:20 PM PDT 24 |
| Peak memory | 196208 kb |
| Host | smart-ca1e2981-3010-41fb-8caa-34c819460331 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2159031421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.2159031421 |
| Directory | /workspace/28.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/28.uart_smoke.4050506965 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 713902678 ps |
| CPU time | 1.91 seconds |
| Started | Jun 04 12:39:06 PM PDT 24 |
| Finished | Jun 04 12:39:09 PM PDT 24 |
| Peak memory | 199124 kb |
| Host | smart-7c0aa2b8-a9b3-4ea2-8906-3f852254f562 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4050506965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_smoke.4050506965 |
| Directory | /workspace/28.uart_smoke/latest |
| Test location | /workspace/coverage/default/28.uart_stress_all.3916082584 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 88573813066 ps |
| CPU time | 198.63 seconds |
| Started | Jun 04 12:39:12 PM PDT 24 |
| Finished | Jun 04 12:42:31 PM PDT 24 |
| Peak memory | 200408 kb |
| Host | smart-e724f9c5-3309-4c0e-be4d-07a113466409 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916082584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.3916082584 |
| Directory | /workspace/28.uart_stress_all/latest |
| Test location | /workspace/coverage/default/28.uart_stress_all_with_rand_reset.1814220543 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 288751337801 ps |
| CPU time | 1104.62 seconds |
| Started | Jun 04 12:39:00 PM PDT 24 |
| Finished | Jun 04 12:57:26 PM PDT 24 |
| Peak memory | 217600 kb |
| Host | smart-6f100f7f-aff5-4f75-aa2e-04ffa107b07e |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814220543 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 28.uart_stress_all_with_rand_reset.1814220543 |
| Directory | /workspace/28.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/28.uart_tx_ovrd.3466401052 |
| Short name | T1161 |
| Test name | |
| Test status | |
| Simulation time | 1241706471 ps |
| CPU time | 3.65 seconds |
| Started | Jun 04 12:39:03 PM PDT 24 |
| Finished | Jun 04 12:39:08 PM PDT 24 |
| Peak memory | 199064 kb |
| Host | smart-62d71e10-5878-4aad-a080-4efed8658ee3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3466401052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.3466401052 |
| Directory | /workspace/28.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/28.uart_tx_rx.3226985155 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 28936433904 ps |
| CPU time | 13.09 seconds |
| Started | Jun 04 12:39:06 PM PDT 24 |
| Finished | Jun 04 12:39:20 PM PDT 24 |
| Peak memory | 200260 kb |
| Host | smart-a8306633-4ad6-4744-89e6-ef7dd93c27cd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3226985155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.3226985155 |
| Directory | /workspace/28.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/280.uart_fifo_reset.421687813 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 28680721372 ps |
| CPU time | 60.63 seconds |
| Started | Jun 04 12:42:48 PM PDT 24 |
| Finished | Jun 04 12:43:50 PM PDT 24 |
| Peak memory | 200196 kb |
| Host | smart-9da8ab1a-ef68-4805-a67c-4909e6cc0adc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=421687813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.421687813 |
| Directory | /workspace/280.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/282.uart_fifo_reset.1249963754 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 20743025960 ps |
| CPU time | 17.98 seconds |
| Started | Jun 04 12:42:51 PM PDT 24 |
| Finished | Jun 04 12:43:10 PM PDT 24 |
| Peak memory | 200224 kb |
| Host | smart-f917e4af-f09b-43e1-9d4c-9508d5ed9bc3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1249963754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.1249963754 |
| Directory | /workspace/282.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/283.uart_fifo_reset.2060884980 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 100489262636 ps |
| CPU time | 184.31 seconds |
| Started | Jun 04 12:42:50 PM PDT 24 |
| Finished | Jun 04 12:45:56 PM PDT 24 |
| Peak memory | 200096 kb |
| Host | smart-880d01ba-b6d3-424f-868d-cf62fa190a2e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2060884980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.2060884980 |
| Directory | /workspace/283.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/284.uart_fifo_reset.789588909 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 52684637429 ps |
| CPU time | 146.23 seconds |
| Started | Jun 04 12:42:50 PM PDT 24 |
| Finished | Jun 04 12:45:17 PM PDT 24 |
| Peak memory | 200320 kb |
| Host | smart-fcf39c2b-ea55-4398-b164-5026a0302a75 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=789588909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.789588909 |
| Directory | /workspace/284.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/285.uart_fifo_reset.1339861278 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 68204054558 ps |
| CPU time | 58.63 seconds |
| Started | Jun 04 12:42:51 PM PDT 24 |
| Finished | Jun 04 12:43:51 PM PDT 24 |
| Peak memory | 200140 kb |
| Host | smart-69136430-c09b-4ec6-b30a-856a5b7b8472 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1339861278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.1339861278 |
| Directory | /workspace/285.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/286.uart_fifo_reset.1714342013 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 51649949148 ps |
| CPU time | 20.77 seconds |
| Started | Jun 04 12:42:49 PM PDT 24 |
| Finished | Jun 04 12:43:11 PM PDT 24 |
| Peak memory | 200280 kb |
| Host | smart-e92091ea-c4f3-489f-aeda-e8ab77572d81 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1714342013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.1714342013 |
| Directory | /workspace/286.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/287.uart_fifo_reset.1171363012 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 17261160785 ps |
| CPU time | 8.15 seconds |
| Started | Jun 04 12:42:48 PM PDT 24 |
| Finished | Jun 04 12:42:57 PM PDT 24 |
| Peak memory | 200012 kb |
| Host | smart-e6a8cdbd-335a-4298-b9c9-cd0a6ebf41a3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1171363012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.1171363012 |
| Directory | /workspace/287.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/288.uart_fifo_reset.819986918 |
| Short name | T1024 |
| Test name | |
| Test status | |
| Simulation time | 108440582088 ps |
| CPU time | 40.53 seconds |
| Started | Jun 04 12:42:50 PM PDT 24 |
| Finished | Jun 04 12:43:32 PM PDT 24 |
| Peak memory | 200244 kb |
| Host | smart-86d1528a-469d-47c6-bc95-b13e7aae0758 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=819986918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.819986918 |
| Directory | /workspace/288.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/289.uart_fifo_reset.3620071946 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 25814452443 ps |
| CPU time | 51.13 seconds |
| Started | Jun 04 12:42:52 PM PDT 24 |
| Finished | Jun 04 12:43:43 PM PDT 24 |
| Peak memory | 200116 kb |
| Host | smart-02138023-e994-46f0-b8b7-82a4e787c6cb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3620071946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.3620071946 |
| Directory | /workspace/289.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/29.uart_alert_test.1017350826 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 13398505 ps |
| CPU time | 0.53 seconds |
| Started | Jun 04 12:39:08 PM PDT 24 |
| Finished | Jun 04 12:39:09 PM PDT 24 |
| Peak memory | 194556 kb |
| Host | smart-dcdc0787-610a-4892-80b3-670432067a68 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017350826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.1017350826 |
| Directory | /workspace/29.uart_alert_test/latest |
| Test location | /workspace/coverage/default/29.uart_fifo_overflow.3489206919 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 123662274467 ps |
| CPU time | 180.07 seconds |
| Started | Jun 04 12:39:11 PM PDT 24 |
| Finished | Jun 04 12:42:12 PM PDT 24 |
| Peak memory | 200096 kb |
| Host | smart-d276cc16-060e-4d01-b81c-574d2cb47ac1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3489206919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.3489206919 |
| Directory | /workspace/29.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/29.uart_intr.2076355355 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 161902769206 ps |
| CPU time | 25.38 seconds |
| Started | Jun 04 12:39:10 PM PDT 24 |
| Finished | Jun 04 12:39:36 PM PDT 24 |
| Peak memory | 196228 kb |
| Host | smart-99f2161c-2b41-4586-a9b8-e72d38a8e077 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076355355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.2076355355 |
| Directory | /workspace/29.uart_intr/latest |
| Test location | /workspace/coverage/default/29.uart_long_xfer_wo_dly.292389873 |
| Short name | T1006 |
| Test name | |
| Test status | |
| Simulation time | 81531180200 ps |
| CPU time | 363.28 seconds |
| Started | Jun 04 12:39:07 PM PDT 24 |
| Finished | Jun 04 12:45:12 PM PDT 24 |
| Peak memory | 200088 kb |
| Host | smart-842148bf-c2d8-4f96-92b2-bb150a962042 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=292389873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.292389873 |
| Directory | /workspace/29.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/29.uart_loopback.2826900517 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 53786228 ps |
| CPU time | 0.57 seconds |
| Started | Jun 04 12:39:09 PM PDT 24 |
| Finished | Jun 04 12:39:10 PM PDT 24 |
| Peak memory | 196188 kb |
| Host | smart-72169fe9-eac4-411a-9557-6131b1384f08 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2826900517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_loopback.2826900517 |
| Directory | /workspace/29.uart_loopback/latest |
| Test location | /workspace/coverage/default/29.uart_noise_filter.2399156365 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 60820158933 ps |
| CPU time | 23.34 seconds |
| Started | Jun 04 12:39:11 PM PDT 24 |
| Finished | Jun 04 12:39:35 PM PDT 24 |
| Peak memory | 198960 kb |
| Host | smart-d089a932-ddaf-423d-b381-34fa43ea446b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2399156365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_noise_filter.2399156365 |
| Directory | /workspace/29.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/29.uart_perf.2202078800 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 4555451417 ps |
| CPU time | 137.53 seconds |
| Started | Jun 04 12:39:09 PM PDT 24 |
| Finished | Jun 04 12:41:27 PM PDT 24 |
| Peak memory | 200232 kb |
| Host | smart-0e0ef6b1-a5d2-48fb-8ce9-e007e70561ab |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2202078800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.2202078800 |
| Directory | /workspace/29.uart_perf/latest |
| Test location | /workspace/coverage/default/29.uart_rx_oversample.1703821462 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 6425174820 ps |
| CPU time | 52.46 seconds |
| Started | Jun 04 12:39:10 PM PDT 24 |
| Finished | Jun 04 12:40:03 PM PDT 24 |
| Peak memory | 198356 kb |
| Host | smart-97daf930-b437-49af-b2f3-c5fadfdaf31e |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1703821462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.1703821462 |
| Directory | /workspace/29.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/29.uart_rx_parity_err.4022491068 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 63319741246 ps |
| CPU time | 19.77 seconds |
| Started | Jun 04 12:39:09 PM PDT 24 |
| Finished | Jun 04 12:39:30 PM PDT 24 |
| Peak memory | 200220 kb |
| Host | smart-4c57c89f-aa72-4836-9454-c3940abfcf20 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4022491068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.4022491068 |
| Directory | /workspace/29.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/29.uart_rx_start_bit_filter.2372433827 |
| Short name | T1009 |
| Test name | |
| Test status | |
| Simulation time | 31357500362 ps |
| CPU time | 55.9 seconds |
| Started | Jun 04 12:39:09 PM PDT 24 |
| Finished | Jun 04 12:40:06 PM PDT 24 |
| Peak memory | 195908 kb |
| Host | smart-47fc94ef-0e13-4752-96ac-f654835dfd4b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2372433827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.2372433827 |
| Directory | /workspace/29.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/29.uart_smoke.881652555 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 11063094760 ps |
| CPU time | 62.91 seconds |
| Started | Jun 04 12:39:09 PM PDT 24 |
| Finished | Jun 04 12:40:13 PM PDT 24 |
| Peak memory | 199776 kb |
| Host | smart-6c9dd836-dd08-4835-8886-cd281df89760 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=881652555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_smoke.881652555 |
| Directory | /workspace/29.uart_smoke/latest |
| Test location | /workspace/coverage/default/29.uart_stress_all_with_rand_reset.3932218119 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 60586630992 ps |
| CPU time | 432.8 seconds |
| Started | Jun 04 12:39:08 PM PDT 24 |
| Finished | Jun 04 12:46:22 PM PDT 24 |
| Peak memory | 216792 kb |
| Host | smart-0cddb808-bc6a-41b3-8e89-d3e8dedfc5ad |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932218119 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 29.uart_stress_all_with_rand_reset.3932218119 |
| Directory | /workspace/29.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/29.uart_tx_ovrd.3729885040 |
| Short name | T1070 |
| Test name | |
| Test status | |
| Simulation time | 7151951940 ps |
| CPU time | 14.17 seconds |
| Started | Jun 04 12:39:09 PM PDT 24 |
| Finished | Jun 04 12:39:24 PM PDT 24 |
| Peak memory | 200072 kb |
| Host | smart-71d5a5d5-77a6-4e04-a7cb-42c9108ab2db |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3729885040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.3729885040 |
| Directory | /workspace/29.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/29.uart_tx_rx.2661162663 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 100352300022 ps |
| CPU time | 17.82 seconds |
| Started | Jun 04 12:39:09 PM PDT 24 |
| Finished | Jun 04 12:39:27 PM PDT 24 |
| Peak memory | 200192 kb |
| Host | smart-3433f094-1a7d-4562-9677-60c7b124bfb5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2661162663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.2661162663 |
| Directory | /workspace/29.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/291.uart_fifo_reset.2387678112 |
| Short name | T993 |
| Test name | |
| Test status | |
| Simulation time | 26785764336 ps |
| CPU time | 44.25 seconds |
| Started | Jun 04 12:42:52 PM PDT 24 |
| Finished | Jun 04 12:43:37 PM PDT 24 |
| Peak memory | 200352 kb |
| Host | smart-c8bcf0a8-adb6-47bf-b451-6ab33f7e145e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2387678112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.2387678112 |
| Directory | /workspace/291.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/292.uart_fifo_reset.1525413973 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 27049226383 ps |
| CPU time | 27.65 seconds |
| Started | Jun 04 12:42:50 PM PDT 24 |
| Finished | Jun 04 12:43:18 PM PDT 24 |
| Peak memory | 200264 kb |
| Host | smart-3410e25d-ccb8-4b27-b4da-2ba8d3c1c94e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1525413973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.1525413973 |
| Directory | /workspace/292.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/293.uart_fifo_reset.3956014588 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 137368566172 ps |
| CPU time | 194.73 seconds |
| Started | Jun 04 12:42:54 PM PDT 24 |
| Finished | Jun 04 12:46:09 PM PDT 24 |
| Peak memory | 200148 kb |
| Host | smart-4ef94b04-0f4f-4bc2-b570-63684ffb0b64 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3956014588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.3956014588 |
| Directory | /workspace/293.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/296.uart_fifo_reset.2229514444 |
| Short name | T1025 |
| Test name | |
| Test status | |
| Simulation time | 14545992629 ps |
| CPU time | 21.42 seconds |
| Started | Jun 04 12:43:00 PM PDT 24 |
| Finished | Jun 04 12:43:23 PM PDT 24 |
| Peak memory | 200276 kb |
| Host | smart-8b39fc4c-a9c6-4ddc-8e51-83bdc1f1e1f3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2229514444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.2229514444 |
| Directory | /workspace/296.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/297.uart_fifo_reset.2961976838 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 136673793310 ps |
| CPU time | 322.34 seconds |
| Started | Jun 04 12:42:58 PM PDT 24 |
| Finished | Jun 04 12:48:21 PM PDT 24 |
| Peak memory | 200336 kb |
| Host | smart-575242bb-bea1-416b-bfb1-4162aae4aa6a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2961976838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.2961976838 |
| Directory | /workspace/297.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/298.uart_fifo_reset.1588969508 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 4386462598 ps |
| CPU time | 8.33 seconds |
| Started | Jun 04 12:43:00 PM PDT 24 |
| Finished | Jun 04 12:43:09 PM PDT 24 |
| Peak memory | 199388 kb |
| Host | smart-4fd06606-5310-4e67-ad10-2be0d99ec5f2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1588969508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.1588969508 |
| Directory | /workspace/298.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/299.uart_fifo_reset.856999182 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 331091507411 ps |
| CPU time | 38.67 seconds |
| Started | Jun 04 12:43:01 PM PDT 24 |
| Finished | Jun 04 12:43:40 PM PDT 24 |
| Peak memory | 200220 kb |
| Host | smart-3b775c60-ca7e-43d6-9053-d6101ef54f17 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=856999182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.856999182 |
| Directory | /workspace/299.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/3.uart_alert_test.3830657277 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 20468452 ps |
| CPU time | 0.59 seconds |
| Started | Jun 04 12:36:58 PM PDT 24 |
| Finished | Jun 04 12:37:00 PM PDT 24 |
| Peak memory | 195600 kb |
| Host | smart-1f5e840c-8621-421c-b237-b4fb46c65535 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830657277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.3830657277 |
| Directory | /workspace/3.uart_alert_test/latest |
| Test location | /workspace/coverage/default/3.uart_fifo_full.748016058 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 268046736775 ps |
| CPU time | 341.9 seconds |
| Started | Jun 04 12:36:51 PM PDT 24 |
| Finished | Jun 04 12:42:34 PM PDT 24 |
| Peak memory | 200156 kb |
| Host | smart-1bc03744-e770-42de-8b9f-21c882d7a87b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=748016058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.748016058 |
| Directory | /workspace/3.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/3.uart_fifo_overflow.3961271483 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 60020212057 ps |
| CPU time | 23.19 seconds |
| Started | Jun 04 12:36:49 PM PDT 24 |
| Finished | Jun 04 12:37:13 PM PDT 24 |
| Peak memory | 200152 kb |
| Host | smart-9b50d0ad-5324-4497-9f84-8cc40db18550 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3961271483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.3961271483 |
| Directory | /workspace/3.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/3.uart_fifo_reset.4235533702 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 98915227919 ps |
| CPU time | 57.26 seconds |
| Started | Jun 04 12:36:51 PM PDT 24 |
| Finished | Jun 04 12:37:50 PM PDT 24 |
| Peak memory | 200232 kb |
| Host | smart-56822b78-cb56-4ff7-ab8d-c50952076cce |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4235533702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.4235533702 |
| Directory | /workspace/3.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/3.uart_intr.3885578782 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 38856425215 ps |
| CPU time | 61.85 seconds |
| Started | Jun 04 12:36:52 PM PDT 24 |
| Finished | Jun 04 12:37:56 PM PDT 24 |
| Peak memory | 200104 kb |
| Host | smart-f48e7ad1-a955-4c28-90d3-d5bd0d360941 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885578782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.3885578782 |
| Directory | /workspace/3.uart_intr/latest |
| Test location | /workspace/coverage/default/3.uart_long_xfer_wo_dly.724473403 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 38720644687 ps |
| CPU time | 52.6 seconds |
| Started | Jun 04 12:36:54 PM PDT 24 |
| Finished | Jun 04 12:37:48 PM PDT 24 |
| Peak memory | 200348 kb |
| Host | smart-450e1234-2e5c-41f3-8bd4-59ee19f64d97 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=724473403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.724473403 |
| Directory | /workspace/3.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/3.uart_loopback.1419949011 |
| Short name | T989 |
| Test name | |
| Test status | |
| Simulation time | 490411612 ps |
| CPU time | 1.21 seconds |
| Started | Jun 04 12:36:54 PM PDT 24 |
| Finished | Jun 04 12:36:56 PM PDT 24 |
| Peak memory | 197408 kb |
| Host | smart-7f22141c-d0a6-4cbe-8d0f-da6b36096b70 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1419949011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_loopback.1419949011 |
| Directory | /workspace/3.uart_loopback/latest |
| Test location | /workspace/coverage/default/3.uart_noise_filter.1373357994 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 55832756752 ps |
| CPU time | 23.91 seconds |
| Started | Jun 04 12:36:51 PM PDT 24 |
| Finished | Jun 04 12:37:17 PM PDT 24 |
| Peak memory | 199256 kb |
| Host | smart-82abc1c6-851c-45d9-8923-63bd3ba9a3ab |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1373357994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_noise_filter.1373357994 |
| Directory | /workspace/3.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/3.uart_perf.4162314584 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 17529169144 ps |
| CPU time | 117.94 seconds |
| Started | Jun 04 12:36:54 PM PDT 24 |
| Finished | Jun 04 12:38:53 PM PDT 24 |
| Peak memory | 200152 kb |
| Host | smart-bc1f3fdf-934f-4ec3-940b-6abc9de3563b |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4162314584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.4162314584 |
| Directory | /workspace/3.uart_perf/latest |
| Test location | /workspace/coverage/default/3.uart_rx_oversample.3745574610 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 2543143363 ps |
| CPU time | 8.17 seconds |
| Started | Jun 04 12:36:52 PM PDT 24 |
| Finished | Jun 04 12:37:02 PM PDT 24 |
| Peak memory | 198388 kb |
| Host | smart-234b0802-8789-4013-887f-88bd3b9b1466 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3745574610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.3745574610 |
| Directory | /workspace/3.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/3.uart_rx_parity_err.1041893980 |
| Short name | T931 |
| Test name | |
| Test status | |
| Simulation time | 216817397713 ps |
| CPU time | 74.34 seconds |
| Started | Jun 04 12:36:51 PM PDT 24 |
| Finished | Jun 04 12:38:07 PM PDT 24 |
| Peak memory | 200224 kb |
| Host | smart-fcd4f29e-3089-4f03-a27a-2dd49a72f081 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1041893980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.1041893980 |
| Directory | /workspace/3.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/3.uart_rx_start_bit_filter.1666693159 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 41134079061 ps |
| CPU time | 19.11 seconds |
| Started | Jun 04 12:36:52 PM PDT 24 |
| Finished | Jun 04 12:37:13 PM PDT 24 |
| Peak memory | 195932 kb |
| Host | smart-791469fa-558f-48dd-9a54-398083c108c0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1666693159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.1666693159 |
| Directory | /workspace/3.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/3.uart_sec_cm.3930763027 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 59115193 ps |
| CPU time | 0.86 seconds |
| Started | Jun 04 12:36:53 PM PDT 24 |
| Finished | Jun 04 12:36:55 PM PDT 24 |
| Peak memory | 218452 kb |
| Host | smart-84b7893f-2ed6-4ac4-bf11-dc1c0254f21c |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930763027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.3930763027 |
| Directory | /workspace/3.uart_sec_cm/latest |
| Test location | /workspace/coverage/default/3.uart_smoke.514779278 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 5643147910 ps |
| CPU time | 20.68 seconds |
| Started | Jun 04 12:36:52 PM PDT 24 |
| Finished | Jun 04 12:37:14 PM PDT 24 |
| Peak memory | 199888 kb |
| Host | smart-e4fc6176-61b7-425a-b0cc-11872ca2d277 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=514779278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_smoke.514779278 |
| Directory | /workspace/3.uart_smoke/latest |
| Test location | /workspace/coverage/default/3.uart_stress_all.4289939965 |
| Short name | T968 |
| Test name | |
| Test status | |
| Simulation time | 160555872877 ps |
| CPU time | 504.26 seconds |
| Started | Jun 04 12:36:53 PM PDT 24 |
| Finished | Jun 04 12:45:18 PM PDT 24 |
| Peak memory | 200232 kb |
| Host | smart-140f05f3-54d2-486e-bec3-89c9f2ca1b4d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289939965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.4289939965 |
| Directory | /workspace/3.uart_stress_all/latest |
| Test location | /workspace/coverage/default/3.uart_stress_all_with_rand_reset.2145847956 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 33245677830 ps |
| CPU time | 394.11 seconds |
| Started | Jun 04 12:36:51 PM PDT 24 |
| Finished | Jun 04 12:43:27 PM PDT 24 |
| Peak memory | 216824 kb |
| Host | smart-860a3519-9079-4cb1-a649-c5555ce88f4d |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145847956 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 3.uart_stress_all_with_rand_reset.2145847956 |
| Directory | /workspace/3.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/3.uart_tx_ovrd.3082735797 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 6739527795 ps |
| CPU time | 24.99 seconds |
| Started | Jun 04 12:36:50 PM PDT 24 |
| Finished | Jun 04 12:37:16 PM PDT 24 |
| Peak memory | 200196 kb |
| Host | smart-80d36495-a203-4c23-b675-d987846b3b4f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3082735797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.3082735797 |
| Directory | /workspace/3.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/3.uart_tx_rx.1184554193 |
| Short name | T932 |
| Test name | |
| Test status | |
| Simulation time | 60488731577 ps |
| CPU time | 54.43 seconds |
| Started | Jun 04 12:36:51 PM PDT 24 |
| Finished | Jun 04 12:37:48 PM PDT 24 |
| Peak memory | 200196 kb |
| Host | smart-e37077df-84c9-4aae-9c16-c393cee50cd3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1184554193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.1184554193 |
| Directory | /workspace/3.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/30.uart_alert_test.855942115 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 48345736 ps |
| CPU time | 0.58 seconds |
| Started | Jun 04 12:39:18 PM PDT 24 |
| Finished | Jun 04 12:39:20 PM PDT 24 |
| Peak memory | 195724 kb |
| Host | smart-43d458b9-458f-4821-a44e-83d29e4814bc |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855942115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.855942115 |
| Directory | /workspace/30.uart_alert_test/latest |
| Test location | /workspace/coverage/default/30.uart_fifo_full.4201112342 |
| Short name | T1119 |
| Test name | |
| Test status | |
| Simulation time | 33908833484 ps |
| CPU time | 28.75 seconds |
| Started | Jun 04 12:39:21 PM PDT 24 |
| Finished | Jun 04 12:39:51 PM PDT 24 |
| Peak memory | 200292 kb |
| Host | smart-20aaeb98-de54-4a3a-85d9-7d5c05aed9ba |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4201112342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.4201112342 |
| Directory | /workspace/30.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/30.uart_fifo_overflow.2753928063 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 192916728443 ps |
| CPU time | 136.37 seconds |
| Started | Jun 04 12:39:18 PM PDT 24 |
| Finished | Jun 04 12:41:36 PM PDT 24 |
| Peak memory | 200160 kb |
| Host | smart-abc14e8f-0542-4fdd-a4dc-be33567c8304 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2753928063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.2753928063 |
| Directory | /workspace/30.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/30.uart_fifo_reset.916511175 |
| Short name | T1003 |
| Test name | |
| Test status | |
| Simulation time | 19642448057 ps |
| CPU time | 10.77 seconds |
| Started | Jun 04 12:39:20 PM PDT 24 |
| Finished | Jun 04 12:39:32 PM PDT 24 |
| Peak memory | 199376 kb |
| Host | smart-aee79d52-829b-4b5f-a3b1-0f63dd3bbfec |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=916511175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.916511175 |
| Directory | /workspace/30.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/30.uart_intr.678843363 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 62740664679 ps |
| CPU time | 56.22 seconds |
| Started | Jun 04 12:39:18 PM PDT 24 |
| Finished | Jun 04 12:40:16 PM PDT 24 |
| Peak memory | 200152 kb |
| Host | smart-e9ac4efb-1d7f-4ded-b601-5734ccbacc16 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678843363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.678843363 |
| Directory | /workspace/30.uart_intr/latest |
| Test location | /workspace/coverage/default/30.uart_long_xfer_wo_dly.3206463261 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 84536586996 ps |
| CPU time | 651.09 seconds |
| Started | Jun 04 12:39:17 PM PDT 24 |
| Finished | Jun 04 12:50:09 PM PDT 24 |
| Peak memory | 200160 kb |
| Host | smart-e35cc3e4-36a3-4caa-9a78-2565052dcba1 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3206463261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.3206463261 |
| Directory | /workspace/30.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/30.uart_loopback.2401285631 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 5167688951 ps |
| CPU time | 5.13 seconds |
| Started | Jun 04 12:39:19 PM PDT 24 |
| Finished | Jun 04 12:39:25 PM PDT 24 |
| Peak memory | 200228 kb |
| Host | smart-8822dda6-d347-4975-a7a5-9eaf113c38c6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2401285631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_loopback.2401285631 |
| Directory | /workspace/30.uart_loopback/latest |
| Test location | /workspace/coverage/default/30.uart_noise_filter.1002209178 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 45966356513 ps |
| CPU time | 78.85 seconds |
| Started | Jun 04 12:39:21 PM PDT 24 |
| Finished | Jun 04 12:40:41 PM PDT 24 |
| Peak memory | 200148 kb |
| Host | smart-d60a0ec1-185d-4eeb-b13e-4122ca570001 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1002209178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_noise_filter.1002209178 |
| Directory | /workspace/30.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/30.uart_perf.225123245 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 4315438667 ps |
| CPU time | 189.86 seconds |
| Started | Jun 04 12:39:20 PM PDT 24 |
| Finished | Jun 04 12:42:31 PM PDT 24 |
| Peak memory | 200252 kb |
| Host | smart-b489aa1f-ab17-4f00-ad92-8a5827628c90 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=225123245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.225123245 |
| Directory | /workspace/30.uart_perf/latest |
| Test location | /workspace/coverage/default/30.uart_rx_oversample.3072312540 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 5271503603 ps |
| CPU time | 49.29 seconds |
| Started | Jun 04 12:39:21 PM PDT 24 |
| Finished | Jun 04 12:40:11 PM PDT 24 |
| Peak memory | 198368 kb |
| Host | smart-3c09e161-bf81-445f-a094-ed5d8b8b6a49 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3072312540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.3072312540 |
| Directory | /workspace/30.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/30.uart_rx_parity_err.2239391754 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 88100408250 ps |
| CPU time | 39.75 seconds |
| Started | Jun 04 12:39:21 PM PDT 24 |
| Finished | Jun 04 12:40:01 PM PDT 24 |
| Peak memory | 200300 kb |
| Host | smart-f12bc093-270d-40c2-8877-5ba388068342 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2239391754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.2239391754 |
| Directory | /workspace/30.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/30.uart_rx_start_bit_filter.1655987908 |
| Short name | T945 |
| Test name | |
| Test status | |
| Simulation time | 1719070733 ps |
| CPU time | 3.2 seconds |
| Started | Jun 04 12:39:19 PM PDT 24 |
| Finished | Jun 04 12:39:24 PM PDT 24 |
| Peak memory | 195564 kb |
| Host | smart-f86f09ea-7bd5-4fa8-90a5-d67544e4c43e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1655987908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.1655987908 |
| Directory | /workspace/30.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/30.uart_smoke.155780554 |
| Short name | T957 |
| Test name | |
| Test status | |
| Simulation time | 592279692 ps |
| CPU time | 0.87 seconds |
| Started | Jun 04 12:39:17 PM PDT 24 |
| Finished | Jun 04 12:39:18 PM PDT 24 |
| Peak memory | 199224 kb |
| Host | smart-63ddbcbe-3bab-4fee-8039-a1626bc79feb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=155780554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_smoke.155780554 |
| Directory | /workspace/30.uart_smoke/latest |
| Test location | /workspace/coverage/default/30.uart_stress_all.2580035140 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 162907805314 ps |
| CPU time | 182.4 seconds |
| Started | Jun 04 12:39:19 PM PDT 24 |
| Finished | Jun 04 12:42:23 PM PDT 24 |
| Peak memory | 208576 kb |
| Host | smart-52339624-1658-4ac0-ab9a-8a61aea1c7d8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580035140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.2580035140 |
| Directory | /workspace/30.uart_stress_all/latest |
| Test location | /workspace/coverage/default/30.uart_stress_all_with_rand_reset.1951751828 |
| Short name | T938 |
| Test name | |
| Test status | |
| Simulation time | 35176354670 ps |
| CPU time | 403.92 seconds |
| Started | Jun 04 12:39:19 PM PDT 24 |
| Finished | Jun 04 12:46:04 PM PDT 24 |
| Peak memory | 215892 kb |
| Host | smart-d539b031-6dbd-48f7-9edb-b7e8047fab78 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951751828 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 30.uart_stress_all_with_rand_reset.1951751828 |
| Directory | /workspace/30.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/30.uart_tx_ovrd.4029020760 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 2928324006 ps |
| CPU time | 2.83 seconds |
| Started | Jun 04 12:39:21 PM PDT 24 |
| Finished | Jun 04 12:39:25 PM PDT 24 |
| Peak memory | 198972 kb |
| Host | smart-36413ad8-7f6a-48d6-8c32-c4f0752e50ee |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4029020760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.4029020760 |
| Directory | /workspace/30.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/30.uart_tx_rx.3037185966 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 43785422626 ps |
| CPU time | 20.61 seconds |
| Started | Jun 04 12:39:19 PM PDT 24 |
| Finished | Jun 04 12:39:41 PM PDT 24 |
| Peak memory | 200252 kb |
| Host | smart-24e1e92f-5199-42c5-b76c-a312cdb3704e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3037185966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.3037185966 |
| Directory | /workspace/30.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/31.uart_alert_test.59221486 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 14453099 ps |
| CPU time | 0.56 seconds |
| Started | Jun 04 12:39:34 PM PDT 24 |
| Finished | Jun 04 12:39:36 PM PDT 24 |
| Peak memory | 195096 kb |
| Host | smart-d89a0362-6f28-433f-8be2-7d67ea8dbfe8 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59221486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.59221486 |
| Directory | /workspace/31.uart_alert_test/latest |
| Test location | /workspace/coverage/default/31.uart_fifo_full.3409389250 |
| Short name | T979 |
| Test name | |
| Test status | |
| Simulation time | 87086692272 ps |
| CPU time | 45.42 seconds |
| Started | Jun 04 12:39:20 PM PDT 24 |
| Finished | Jun 04 12:40:06 PM PDT 24 |
| Peak memory | 200352 kb |
| Host | smart-99c4586d-a34f-40ef-854d-290a9a925fa4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3409389250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.3409389250 |
| Directory | /workspace/31.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/31.uart_fifo_overflow.4133165460 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 51727406319 ps |
| CPU time | 21.75 seconds |
| Started | Jun 04 12:39:18 PM PDT 24 |
| Finished | Jun 04 12:39:41 PM PDT 24 |
| Peak memory | 200276 kb |
| Host | smart-44357451-0851-4667-a405-028449ed6810 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4133165460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.4133165460 |
| Directory | /workspace/31.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/31.uart_fifo_reset.2390403046 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 15018308207 ps |
| CPU time | 35.91 seconds |
| Started | Jun 04 12:39:18 PM PDT 24 |
| Finished | Jun 04 12:39:55 PM PDT 24 |
| Peak memory | 200360 kb |
| Host | smart-813cc1f5-acef-43a2-9174-0f932277e31a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2390403046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.2390403046 |
| Directory | /workspace/31.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/31.uart_intr.246782426 |
| Short name | T1096 |
| Test name | |
| Test status | |
| Simulation time | 19211739473 ps |
| CPU time | 27.78 seconds |
| Started | Jun 04 12:39:18 PM PDT 24 |
| Finished | Jun 04 12:39:47 PM PDT 24 |
| Peak memory | 197048 kb |
| Host | smart-c4f90e91-ea2a-439d-9e0b-526b9bec6a13 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246782426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.246782426 |
| Directory | /workspace/31.uart_intr/latest |
| Test location | /workspace/coverage/default/31.uart_long_xfer_wo_dly.1594423343 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 54467979277 ps |
| CPU time | 323.38 seconds |
| Started | Jun 04 12:39:18 PM PDT 24 |
| Finished | Jun 04 12:44:43 PM PDT 24 |
| Peak memory | 200276 kb |
| Host | smart-f8ea82e0-3c83-40c3-bf6b-25c599cbf402 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1594423343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.1594423343 |
| Directory | /workspace/31.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/31.uart_loopback.398069288 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 61398001 ps |
| CPU time | 0.7 seconds |
| Started | Jun 04 12:39:21 PM PDT 24 |
| Finished | Jun 04 12:39:22 PM PDT 24 |
| Peak memory | 196268 kb |
| Host | smart-1bac8841-c3d1-42e4-9e12-50c782331637 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=398069288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_loopback.398069288 |
| Directory | /workspace/31.uart_loopback/latest |
| Test location | /workspace/coverage/default/31.uart_noise_filter.4052752499 |
| Short name | T1026 |
| Test name | |
| Test status | |
| Simulation time | 54376220998 ps |
| CPU time | 52.98 seconds |
| Started | Jun 04 12:39:21 PM PDT 24 |
| Finished | Jun 04 12:40:15 PM PDT 24 |
| Peak memory | 199304 kb |
| Host | smart-fb2fc9f3-af4f-43a1-b8a2-86aa5b04e6d3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4052752499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_noise_filter.4052752499 |
| Directory | /workspace/31.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/31.uart_perf.1235474795 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 14609993966 ps |
| CPU time | 238.31 seconds |
| Started | Jun 04 12:39:18 PM PDT 24 |
| Finished | Jun 04 12:43:18 PM PDT 24 |
| Peak memory | 200316 kb |
| Host | smart-1dbce972-4884-43b1-b57f-bf0b6dcf60f3 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1235474795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.1235474795 |
| Directory | /workspace/31.uart_perf/latest |
| Test location | /workspace/coverage/default/31.uart_rx_oversample.3392482092 |
| Short name | T966 |
| Test name | |
| Test status | |
| Simulation time | 6792909313 ps |
| CPU time | 51.11 seconds |
| Started | Jun 04 12:39:20 PM PDT 24 |
| Finished | Jun 04 12:40:12 PM PDT 24 |
| Peak memory | 198080 kb |
| Host | smart-3e8957de-3957-430c-a8cd-91e8c6435cea |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3392482092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.3392482092 |
| Directory | /workspace/31.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/31.uart_rx_parity_err.1834565520 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 155862682796 ps |
| CPU time | 306.27 seconds |
| Started | Jun 04 12:39:20 PM PDT 24 |
| Finished | Jun 04 12:44:27 PM PDT 24 |
| Peak memory | 200128 kb |
| Host | smart-0f154da8-ecb7-403b-a492-96fcbbf88b6d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1834565520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.1834565520 |
| Directory | /workspace/31.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/31.uart_rx_start_bit_filter.4014319043 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 3892460347 ps |
| CPU time | 6.93 seconds |
| Started | Jun 04 12:39:20 PM PDT 24 |
| Finished | Jun 04 12:39:27 PM PDT 24 |
| Peak memory | 196228 kb |
| Host | smart-8db511fc-cd2f-4fbf-89dd-cfc55a650984 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4014319043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.4014319043 |
| Directory | /workspace/31.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/31.uart_smoke.3177773636 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 341765971 ps |
| CPU time | 1.29 seconds |
| Started | Jun 04 12:39:20 PM PDT 24 |
| Finished | Jun 04 12:39:23 PM PDT 24 |
| Peak memory | 199892 kb |
| Host | smart-c2d0157c-336d-4d8c-b3de-fa00df37669f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3177773636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_smoke.3177773636 |
| Directory | /workspace/31.uart_smoke/latest |
| Test location | /workspace/coverage/default/31.uart_stress_all.1307465942 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 214283624546 ps |
| CPU time | 601.97 seconds |
| Started | Jun 04 12:39:19 PM PDT 24 |
| Finished | Jun 04 12:49:22 PM PDT 24 |
| Peak memory | 200120 kb |
| Host | smart-29a92e5b-e7ec-4bdb-9566-54445bfb3c13 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307465942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.1307465942 |
| Directory | /workspace/31.uart_stress_all/latest |
| Test location | /workspace/coverage/default/31.uart_stress_all_with_rand_reset.828588778 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 51206995823 ps |
| CPU time | 295.85 seconds |
| Started | Jun 04 12:39:21 PM PDT 24 |
| Finished | Jun 04 12:44:18 PM PDT 24 |
| Peak memory | 216832 kb |
| Host | smart-159740cb-75ab-44b3-8742-f693c81f1e78 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828588778 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 31.uart_stress_all_with_rand_reset.828588778 |
| Directory | /workspace/31.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/31.uart_tx_ovrd.1713248395 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 893935626 ps |
| CPU time | 3.72 seconds |
| Started | Jun 04 12:39:18 PM PDT 24 |
| Finished | Jun 04 12:39:23 PM PDT 24 |
| Peak memory | 198556 kb |
| Host | smart-3b230232-e852-41ae-9cee-1f15adb0628c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1713248395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.1713248395 |
| Directory | /workspace/31.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/31.uart_tx_rx.258912324 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 25690817519 ps |
| CPU time | 14.21 seconds |
| Started | Jun 04 12:39:21 PM PDT 24 |
| Finished | Jun 04 12:39:36 PM PDT 24 |
| Peak memory | 200108 kb |
| Host | smart-fadd791b-1663-4190-93bd-c4b9f296bb47 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=258912324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.258912324 |
| Directory | /workspace/31.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/32.uart_alert_test.939113293 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 34035974 ps |
| CPU time | 0.55 seconds |
| Started | Jun 04 12:39:28 PM PDT 24 |
| Finished | Jun 04 12:39:30 PM PDT 24 |
| Peak memory | 195556 kb |
| Host | smart-79ea20cd-d151-4d6e-b7e5-4d66b23bf4b0 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939113293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.939113293 |
| Directory | /workspace/32.uart_alert_test/latest |
| Test location | /workspace/coverage/default/32.uart_fifo_full.646379164 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 131959203528 ps |
| CPU time | 195.57 seconds |
| Started | Jun 04 12:39:28 PM PDT 24 |
| Finished | Jun 04 12:42:44 PM PDT 24 |
| Peak memory | 200192 kb |
| Host | smart-757247e3-e825-42da-9c84-f3a1c6a68005 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=646379164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.646379164 |
| Directory | /workspace/32.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/32.uart_fifo_overflow.2259705936 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 124414076172 ps |
| CPU time | 29.32 seconds |
| Started | Jun 04 12:39:28 PM PDT 24 |
| Finished | Jun 04 12:39:58 PM PDT 24 |
| Peak memory | 200232 kb |
| Host | smart-ba6e3f9d-4ab8-4299-ae36-499aea176624 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2259705936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.2259705936 |
| Directory | /workspace/32.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/32.uart_fifo_reset.3555290904 |
| Short name | T1151 |
| Test name | |
| Test status | |
| Simulation time | 132320527806 ps |
| CPU time | 56.46 seconds |
| Started | Jun 04 12:39:31 PM PDT 24 |
| Finished | Jun 04 12:40:28 PM PDT 24 |
| Peak memory | 200184 kb |
| Host | smart-ce9cb385-f71b-44b7-a477-fe25c0324f10 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3555290904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.3555290904 |
| Directory | /workspace/32.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/32.uart_intr.3306369133 |
| Short name | T943 |
| Test name | |
| Test status | |
| Simulation time | 14967933370 ps |
| CPU time | 6.9 seconds |
| Started | Jun 04 12:39:32 PM PDT 24 |
| Finished | Jun 04 12:39:40 PM PDT 24 |
| Peak memory | 198300 kb |
| Host | smart-5eee5c17-4e11-4cec-bc4a-e983dc18b271 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306369133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.3306369133 |
| Directory | /workspace/32.uart_intr/latest |
| Test location | /workspace/coverage/default/32.uart_long_xfer_wo_dly.251646100 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 143075012432 ps |
| CPU time | 320.04 seconds |
| Started | Jun 04 12:39:35 PM PDT 24 |
| Finished | Jun 04 12:44:56 PM PDT 24 |
| Peak memory | 200156 kb |
| Host | smart-b0c03cdb-e159-4d49-95f2-24e9a38d2e85 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=251646100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.251646100 |
| Directory | /workspace/32.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/32.uart_loopback.2302855425 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 4550429202 ps |
| CPU time | 3.49 seconds |
| Started | Jun 04 12:39:32 PM PDT 24 |
| Finished | Jun 04 12:39:36 PM PDT 24 |
| Peak memory | 196340 kb |
| Host | smart-ba8cc01f-c53e-4dc6-83eb-0274258f5472 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2302855425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_loopback.2302855425 |
| Directory | /workspace/32.uart_loopback/latest |
| Test location | /workspace/coverage/default/32.uart_noise_filter.3280200226 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 35072073345 ps |
| CPU time | 56.44 seconds |
| Started | Jun 04 12:39:28 PM PDT 24 |
| Finished | Jun 04 12:40:26 PM PDT 24 |
| Peak memory | 198536 kb |
| Host | smart-1dccb332-f630-4c8f-b880-df14f93c38be |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3280200226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_noise_filter.3280200226 |
| Directory | /workspace/32.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/32.uart_perf.3152791199 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 17472575439 ps |
| CPU time | 235.26 seconds |
| Started | Jun 04 12:39:29 PM PDT 24 |
| Finished | Jun 04 12:43:25 PM PDT 24 |
| Peak memory | 200244 kb |
| Host | smart-19bdb4e9-cdf3-4a91-ab64-9fa84ee40b0b |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3152791199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.3152791199 |
| Directory | /workspace/32.uart_perf/latest |
| Test location | /workspace/coverage/default/32.uart_rx_oversample.3725687921 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 6874680760 ps |
| CPU time | 59.82 seconds |
| Started | Jun 04 12:39:28 PM PDT 24 |
| Finished | Jun 04 12:40:29 PM PDT 24 |
| Peak memory | 198528 kb |
| Host | smart-3ed59b13-5280-4e0f-beab-d9eabade8cb4 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3725687921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.3725687921 |
| Directory | /workspace/32.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/32.uart_rx_parity_err.2414964368 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 260572473638 ps |
| CPU time | 24.1 seconds |
| Started | Jun 04 12:39:29 PM PDT 24 |
| Finished | Jun 04 12:39:54 PM PDT 24 |
| Peak memory | 200280 kb |
| Host | smart-3228a731-0355-43f6-9b12-00fd64b1033d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2414964368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.2414964368 |
| Directory | /workspace/32.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/32.uart_rx_start_bit_filter.2137959683 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 80303861984 ps |
| CPU time | 30.78 seconds |
| Started | Jun 04 12:39:31 PM PDT 24 |
| Finished | Jun 04 12:40:02 PM PDT 24 |
| Peak memory | 196352 kb |
| Host | smart-725f0a3a-6633-4fa8-bcf0-0a295b2b66cb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2137959683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.2137959683 |
| Directory | /workspace/32.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/32.uart_smoke.1026097157 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 892856033 ps |
| CPU time | 3.99 seconds |
| Started | Jun 04 12:39:30 PM PDT 24 |
| Finished | Jun 04 12:39:35 PM PDT 24 |
| Peak memory | 199048 kb |
| Host | smart-0b725348-df66-461a-ab2f-5a822e4fe873 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1026097157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_smoke.1026097157 |
| Directory | /workspace/32.uart_smoke/latest |
| Test location | /workspace/coverage/default/32.uart_stress_all.1880577213 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 357765968469 ps |
| CPU time | 329.05 seconds |
| Started | Jun 04 12:39:31 PM PDT 24 |
| Finished | Jun 04 12:45:01 PM PDT 24 |
| Peak memory | 200224 kb |
| Host | smart-c7d0b15e-8e9c-46b8-844f-e02b85726867 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880577213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.1880577213 |
| Directory | /workspace/32.uart_stress_all/latest |
| Test location | /workspace/coverage/default/32.uart_stress_all_with_rand_reset.131149496 |
| Short name | T1081 |
| Test name | |
| Test status | |
| Simulation time | 129686051614 ps |
| CPU time | 904.94 seconds |
| Started | Jun 04 12:39:32 PM PDT 24 |
| Finished | Jun 04 12:54:37 PM PDT 24 |
| Peak memory | 216812 kb |
| Host | smart-0d96ae63-df53-460a-85c2-d7ecc947d228 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131149496 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 32.uart_stress_all_with_rand_reset.131149496 |
| Directory | /workspace/32.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/32.uart_tx_ovrd.1115224490 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 1345650853 ps |
| CPU time | 1.7 seconds |
| Started | Jun 04 12:39:28 PM PDT 24 |
| Finished | Jun 04 12:39:31 PM PDT 24 |
| Peak memory | 198736 kb |
| Host | smart-778d9574-daa9-4965-85b1-6427c4e6ea02 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1115224490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.1115224490 |
| Directory | /workspace/32.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/32.uart_tx_rx.2154676605 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 18279799684 ps |
| CPU time | 30.85 seconds |
| Started | Jun 04 12:39:29 PM PDT 24 |
| Finished | Jun 04 12:40:01 PM PDT 24 |
| Peak memory | 199456 kb |
| Host | smart-7ad04db9-4a85-4e64-b619-2ab57bac19dd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2154676605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.2154676605 |
| Directory | /workspace/32.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/33.uart_alert_test.4068151771 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 10853986 ps |
| CPU time | 0.53 seconds |
| Started | Jun 04 12:39:36 PM PDT 24 |
| Finished | Jun 04 12:39:38 PM PDT 24 |
| Peak memory | 194524 kb |
| Host | smart-bbaf1b28-f533-422b-9b58-90cc0ffff022 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068151771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.4068151771 |
| Directory | /workspace/33.uart_alert_test/latest |
| Test location | /workspace/coverage/default/33.uart_fifo_full.309396709 |
| Short name | T1078 |
| Test name | |
| Test status | |
| Simulation time | 184767615654 ps |
| CPU time | 63.53 seconds |
| Started | Jun 04 12:39:29 PM PDT 24 |
| Finished | Jun 04 12:40:33 PM PDT 24 |
| Peak memory | 200148 kb |
| Host | smart-707495e3-fb84-4795-8fb1-63634952ef7f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=309396709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.309396709 |
| Directory | /workspace/33.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/33.uart_fifo_overflow.3426674132 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 22211780803 ps |
| CPU time | 41.24 seconds |
| Started | Jun 04 12:39:30 PM PDT 24 |
| Finished | Jun 04 12:40:12 PM PDT 24 |
| Peak memory | 200368 kb |
| Host | smart-def07e8d-70eb-4ca4-a8ba-8fe5ca07da73 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3426674132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.3426674132 |
| Directory | /workspace/33.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/33.uart_fifo_reset.2294995492 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 6566275018 ps |
| CPU time | 15.88 seconds |
| Started | Jun 04 12:39:29 PM PDT 24 |
| Finished | Jun 04 12:39:46 PM PDT 24 |
| Peak memory | 200360 kb |
| Host | smart-963b4b77-576a-4c80-83dc-11cd841e82fb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2294995492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.2294995492 |
| Directory | /workspace/33.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/33.uart_intr.3108633164 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 8794924840 ps |
| CPU time | 7.04 seconds |
| Started | Jun 04 12:39:27 PM PDT 24 |
| Finished | Jun 04 12:39:35 PM PDT 24 |
| Peak memory | 196844 kb |
| Host | smart-5028e973-692c-45f7-9657-719d17b35bf4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108633164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.3108633164 |
| Directory | /workspace/33.uart_intr/latest |
| Test location | /workspace/coverage/default/33.uart_long_xfer_wo_dly.3219631122 |
| Short name | T1130 |
| Test name | |
| Test status | |
| Simulation time | 144117191699 ps |
| CPU time | 528.49 seconds |
| Started | Jun 04 12:39:37 PM PDT 24 |
| Finished | Jun 04 12:48:26 PM PDT 24 |
| Peak memory | 200164 kb |
| Host | smart-71715d1a-0861-42bc-a346-3d51428ff1e3 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3219631122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.3219631122 |
| Directory | /workspace/33.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/33.uart_loopback.3361160806 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 2295074313 ps |
| CPU time | 5.99 seconds |
| Started | Jun 04 12:39:40 PM PDT 24 |
| Finished | Jun 04 12:39:47 PM PDT 24 |
| Peak memory | 199068 kb |
| Host | smart-351162b6-4f96-4701-9344-b630ba11f2d8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3361160806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_loopback.3361160806 |
| Directory | /workspace/33.uart_loopback/latest |
| Test location | /workspace/coverage/default/33.uart_noise_filter.400610513 |
| Short name | T1107 |
| Test name | |
| Test status | |
| Simulation time | 80431716562 ps |
| CPU time | 32.25 seconds |
| Started | Jun 04 12:39:28 PM PDT 24 |
| Finished | Jun 04 12:40:02 PM PDT 24 |
| Peak memory | 198468 kb |
| Host | smart-7386cc37-5cea-43c5-9da5-282b4840d625 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=400610513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_noise_filter.400610513 |
| Directory | /workspace/33.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/33.uart_perf.801196992 |
| Short name | T1034 |
| Test name | |
| Test status | |
| Simulation time | 10090144473 ps |
| CPU time | 76.1 seconds |
| Started | Jun 04 12:39:38 PM PDT 24 |
| Finished | Jun 04 12:40:55 PM PDT 24 |
| Peak memory | 200220 kb |
| Host | smart-ee27f1ad-847d-46ac-8568-e801b4a8e3b4 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=801196992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.801196992 |
| Directory | /workspace/33.uart_perf/latest |
| Test location | /workspace/coverage/default/33.uart_rx_oversample.2422629333 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 6546487278 ps |
| CPU time | 31.79 seconds |
| Started | Jun 04 12:39:29 PM PDT 24 |
| Finished | Jun 04 12:40:02 PM PDT 24 |
| Peak memory | 199456 kb |
| Host | smart-033e79ac-9ca5-4d01-8b63-1408d47c91aa |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2422629333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.2422629333 |
| Directory | /workspace/33.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/33.uart_rx_parity_err.251520661 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 18163003971 ps |
| CPU time | 30.11 seconds |
| Started | Jun 04 12:39:41 PM PDT 24 |
| Finished | Jun 04 12:40:12 PM PDT 24 |
| Peak memory | 200204 kb |
| Host | smart-9a94e8e8-486c-4193-ba4a-8283ad9f336d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=251520661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.251520661 |
| Directory | /workspace/33.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/33.uart_rx_start_bit_filter.2738519373 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 45251911057 ps |
| CPU time | 33.33 seconds |
| Started | Jun 04 12:39:28 PM PDT 24 |
| Finished | Jun 04 12:40:02 PM PDT 24 |
| Peak memory | 196028 kb |
| Host | smart-00aac334-844c-4934-8933-1cd4215d8002 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2738519373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.2738519373 |
| Directory | /workspace/33.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/33.uart_smoke.3922571322 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 427786112 ps |
| CPU time | 2.06 seconds |
| Started | Jun 04 12:39:28 PM PDT 24 |
| Finished | Jun 04 12:39:31 PM PDT 24 |
| Peak memory | 200148 kb |
| Host | smart-dd78002c-3304-4a9f-9708-81f306923b9e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3922571322 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_smoke.3922571322 |
| Directory | /workspace/33.uart_smoke/latest |
| Test location | /workspace/coverage/default/33.uart_stress_all.4114339962 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 160717615404 ps |
| CPU time | 263.23 seconds |
| Started | Jun 04 12:39:41 PM PDT 24 |
| Finished | Jun 04 12:44:05 PM PDT 24 |
| Peak memory | 200552 kb |
| Host | smart-729ed745-2c61-4919-a209-0b82cc7b5218 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114339962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.4114339962 |
| Directory | /workspace/33.uart_stress_all/latest |
| Test location | /workspace/coverage/default/33.uart_stress_all_with_rand_reset.3386333522 |
| Short name | T1052 |
| Test name | |
| Test status | |
| Simulation time | 75171760580 ps |
| CPU time | 546.87 seconds |
| Started | Jun 04 12:39:38 PM PDT 24 |
| Finished | Jun 04 12:48:46 PM PDT 24 |
| Peak memory | 225076 kb |
| Host | smart-0641a0fd-2269-4e81-b2a5-1e4f5f469d28 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386333522 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 33.uart_stress_all_with_rand_reset.3386333522 |
| Directory | /workspace/33.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/33.uart_tx_ovrd.712490228 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 3519218387 ps |
| CPU time | 1.83 seconds |
| Started | Jun 04 12:39:37 PM PDT 24 |
| Finished | Jun 04 12:39:40 PM PDT 24 |
| Peak memory | 198396 kb |
| Host | smart-6825023c-1c4c-405e-a335-327354f83316 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=712490228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.712490228 |
| Directory | /workspace/33.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/33.uart_tx_rx.1152995423 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 13298962451 ps |
| CPU time | 12.22 seconds |
| Started | Jun 04 12:39:30 PM PDT 24 |
| Finished | Jun 04 12:39:43 PM PDT 24 |
| Peak memory | 200112 kb |
| Host | smart-9af69d0e-8ae9-4d88-a305-f3aa645c6ef4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1152995423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.1152995423 |
| Directory | /workspace/33.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/34.uart_alert_test.1620313955 |
| Short name | T1020 |
| Test name | |
| Test status | |
| Simulation time | 85001720 ps |
| CPU time | 0.55 seconds |
| Started | Jun 04 12:39:36 PM PDT 24 |
| Finished | Jun 04 12:39:38 PM PDT 24 |
| Peak memory | 195696 kb |
| Host | smart-2a838e08-e75a-4b2d-aca4-84862d65389a |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620313955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.1620313955 |
| Directory | /workspace/34.uart_alert_test/latest |
| Test location | /workspace/coverage/default/34.uart_fifo_full.4206657966 |
| Short name | T952 |
| Test name | |
| Test status | |
| Simulation time | 44143051753 ps |
| CPU time | 65.15 seconds |
| Started | Jun 04 12:39:37 PM PDT 24 |
| Finished | Jun 04 12:40:43 PM PDT 24 |
| Peak memory | 200372 kb |
| Host | smart-0e4d2977-a477-4615-a9f5-31a8c87c1bae |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4206657966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.4206657966 |
| Directory | /workspace/34.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/34.uart_fifo_overflow.2048368677 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 41057420691 ps |
| CPU time | 38.57 seconds |
| Started | Jun 04 12:39:37 PM PDT 24 |
| Finished | Jun 04 12:40:16 PM PDT 24 |
| Peak memory | 200276 kb |
| Host | smart-08113b49-e6bb-4912-80ab-de23f29c2dca |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2048368677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.2048368677 |
| Directory | /workspace/34.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/34.uart_fifo_reset.2264912682 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 134508533477 ps |
| CPU time | 58.43 seconds |
| Started | Jun 04 12:39:37 PM PDT 24 |
| Finished | Jun 04 12:40:37 PM PDT 24 |
| Peak memory | 200352 kb |
| Host | smart-9a017c3f-d932-4574-911b-6701a7a16968 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2264912682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.2264912682 |
| Directory | /workspace/34.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/34.uart_intr.1869592827 |
| Short name | T1120 |
| Test name | |
| Test status | |
| Simulation time | 24023142145 ps |
| CPU time | 5.14 seconds |
| Started | Jun 04 12:39:40 PM PDT 24 |
| Finished | Jun 04 12:39:46 PM PDT 24 |
| Peak memory | 199888 kb |
| Host | smart-86952f1f-2bbe-4b59-a7bd-3ccffc306396 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869592827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.1869592827 |
| Directory | /workspace/34.uart_intr/latest |
| Test location | /workspace/coverage/default/34.uart_long_xfer_wo_dly.2770854313 |
| Short name | T926 |
| Test name | |
| Test status | |
| Simulation time | 127467725850 ps |
| CPU time | 231.05 seconds |
| Started | Jun 04 12:39:39 PM PDT 24 |
| Finished | Jun 04 12:43:31 PM PDT 24 |
| Peak memory | 200168 kb |
| Host | smart-20ba323f-7fb4-4d17-8b87-47307bce5812 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2770854313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.2770854313 |
| Directory | /workspace/34.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/34.uart_loopback.3379753757 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 5238179671 ps |
| CPU time | 5.77 seconds |
| Started | Jun 04 12:39:37 PM PDT 24 |
| Finished | Jun 04 12:39:43 PM PDT 24 |
| Peak memory | 198928 kb |
| Host | smart-5e92fd27-e7ca-47d5-8265-68321ea008df |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3379753757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_loopback.3379753757 |
| Directory | /workspace/34.uart_loopback/latest |
| Test location | /workspace/coverage/default/34.uart_noise_filter.412034816 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 37354722516 ps |
| CPU time | 19 seconds |
| Started | Jun 04 12:39:41 PM PDT 24 |
| Finished | Jun 04 12:40:01 PM PDT 24 |
| Peak memory | 200260 kb |
| Host | smart-25c68a4d-092b-4502-812a-ca5503aaac22 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=412034816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_noise_filter.412034816 |
| Directory | /workspace/34.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/34.uart_perf.1092480229 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 18993400044 ps |
| CPU time | 249.69 seconds |
| Started | Jun 04 12:39:39 PM PDT 24 |
| Finished | Jun 04 12:43:50 PM PDT 24 |
| Peak memory | 200224 kb |
| Host | smart-c53c37bc-d311-43e7-a699-8c672956b38b |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1092480229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.1092480229 |
| Directory | /workspace/34.uart_perf/latest |
| Test location | /workspace/coverage/default/34.uart_rx_oversample.2360183826 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 3571465859 ps |
| CPU time | 25.91 seconds |
| Started | Jun 04 12:39:38 PM PDT 24 |
| Finished | Jun 04 12:40:05 PM PDT 24 |
| Peak memory | 198168 kb |
| Host | smart-e1c2aba2-7647-44c4-9500-8bffe6f17496 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2360183826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.2360183826 |
| Directory | /workspace/34.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/34.uart_rx_parity_err.3655910297 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 32880218906 ps |
| CPU time | 15.12 seconds |
| Started | Jun 04 12:39:38 PM PDT 24 |
| Finished | Jun 04 12:39:54 PM PDT 24 |
| Peak memory | 200240 kb |
| Host | smart-3596c87f-975d-475f-b1db-62b9975c9d87 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3655910297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.3655910297 |
| Directory | /workspace/34.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/34.uart_rx_start_bit_filter.3603454386 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 5235974121 ps |
| CPU time | 2.57 seconds |
| Started | Jun 04 12:39:39 PM PDT 24 |
| Finished | Jun 04 12:39:43 PM PDT 24 |
| Peak memory | 196252 kb |
| Host | smart-d89f55ed-538a-43c0-b4c2-459efa432952 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3603454386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.3603454386 |
| Directory | /workspace/34.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/34.uart_smoke.2610539533 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 297847216 ps |
| CPU time | 1.54 seconds |
| Started | Jun 04 12:39:40 PM PDT 24 |
| Finished | Jun 04 12:39:42 PM PDT 24 |
| Peak memory | 199700 kb |
| Host | smart-7968e72d-1b88-4fc4-8052-f7dde595606a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2610539533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_smoke.2610539533 |
| Directory | /workspace/34.uart_smoke/latest |
| Test location | /workspace/coverage/default/34.uart_tx_ovrd.1884407976 |
| Short name | T1077 |
| Test name | |
| Test status | |
| Simulation time | 1348804690 ps |
| CPU time | 2.56 seconds |
| Started | Jun 04 12:39:39 PM PDT 24 |
| Finished | Jun 04 12:39:43 PM PDT 24 |
| Peak memory | 198896 kb |
| Host | smart-5e40898f-8fbc-44dd-90ca-05df5c9625d6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1884407976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.1884407976 |
| Directory | /workspace/34.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/34.uart_tx_rx.1029454879 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 75824976376 ps |
| CPU time | 188.42 seconds |
| Started | Jun 04 12:39:37 PM PDT 24 |
| Finished | Jun 04 12:42:46 PM PDT 24 |
| Peak memory | 200176 kb |
| Host | smart-1276d9a3-bd0f-4ccd-a117-c7cfd74372a7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1029454879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.1029454879 |
| Directory | /workspace/34.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/35.uart_alert_test.3550442004 |
| Short name | T1092 |
| Test name | |
| Test status | |
| Simulation time | 119714946 ps |
| CPU time | 0.53 seconds |
| Started | Jun 04 12:39:48 PM PDT 24 |
| Finished | Jun 04 12:39:50 PM PDT 24 |
| Peak memory | 194536 kb |
| Host | smart-30902aa0-199b-456b-9edb-76b60e523ef2 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550442004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.3550442004 |
| Directory | /workspace/35.uart_alert_test/latest |
| Test location | /workspace/coverage/default/35.uart_fifo_full.3454227203 |
| Short name | T1125 |
| Test name | |
| Test status | |
| Simulation time | 87244721021 ps |
| CPU time | 43.11 seconds |
| Started | Jun 04 12:39:41 PM PDT 24 |
| Finished | Jun 04 12:40:25 PM PDT 24 |
| Peak memory | 200560 kb |
| Host | smart-14cd7e04-24f5-4863-85be-6b5c1635d1ba |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3454227203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.3454227203 |
| Directory | /workspace/35.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/35.uart_fifo_overflow.2271148458 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 99561324972 ps |
| CPU time | 160.91 seconds |
| Started | Jun 04 12:39:37 PM PDT 24 |
| Finished | Jun 04 12:42:18 PM PDT 24 |
| Peak memory | 200172 kb |
| Host | smart-2b5daa4c-f350-475b-bf07-c21efd716794 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2271148458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.2271148458 |
| Directory | /workspace/35.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/35.uart_fifo_reset.4067077145 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 4579322019 ps |
| CPU time | 7.07 seconds |
| Started | Jun 04 12:39:36 PM PDT 24 |
| Finished | Jun 04 12:39:43 PM PDT 24 |
| Peak memory | 200212 kb |
| Host | smart-afdc46e1-730d-4d68-af19-1cd67ac55cb5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4067077145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.4067077145 |
| Directory | /workspace/35.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/35.uart_intr.2220854899 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 420112070498 ps |
| CPU time | 641.43 seconds |
| Started | Jun 04 12:39:38 PM PDT 24 |
| Finished | Jun 04 12:50:20 PM PDT 24 |
| Peak memory | 199876 kb |
| Host | smart-8773ee81-8706-4549-b214-97b23dfd18bb |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220854899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.2220854899 |
| Directory | /workspace/35.uart_intr/latest |
| Test location | /workspace/coverage/default/35.uart_long_xfer_wo_dly.4159264355 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 126510257958 ps |
| CPU time | 410.05 seconds |
| Started | Jun 04 12:39:36 PM PDT 24 |
| Finished | Jun 04 12:46:27 PM PDT 24 |
| Peak memory | 200296 kb |
| Host | smart-6bec22ae-f6f5-4a4e-bcb5-fe899ed91f61 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4159264355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.4159264355 |
| Directory | /workspace/35.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/35.uart_loopback.1838434614 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 10759053201 ps |
| CPU time | 6.47 seconds |
| Started | Jun 04 12:39:39 PM PDT 24 |
| Finished | Jun 04 12:39:47 PM PDT 24 |
| Peak memory | 199784 kb |
| Host | smart-dd611c65-cbac-4b4a-bf1d-2bd7117b5650 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1838434614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_loopback.1838434614 |
| Directory | /workspace/35.uart_loopback/latest |
| Test location | /workspace/coverage/default/35.uart_noise_filter.1539372495 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 66759217701 ps |
| CPU time | 60.05 seconds |
| Started | Jun 04 12:39:39 PM PDT 24 |
| Finished | Jun 04 12:40:41 PM PDT 24 |
| Peak memory | 200400 kb |
| Host | smart-052c4987-02e8-4c40-b846-cc50f5e7fa60 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1539372495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_noise_filter.1539372495 |
| Directory | /workspace/35.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/35.uart_perf.532979287 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 8894039849 ps |
| CPU time | 458.78 seconds |
| Started | Jun 04 12:39:39 PM PDT 24 |
| Finished | Jun 04 12:47:19 PM PDT 24 |
| Peak memory | 200304 kb |
| Host | smart-6cc4efa1-8ead-4bb8-bfb6-8e02d1916c5d |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=532979287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.532979287 |
| Directory | /workspace/35.uart_perf/latest |
| Test location | /workspace/coverage/default/35.uart_rx_oversample.1250753421 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 7570211569 ps |
| CPU time | 17.69 seconds |
| Started | Jun 04 12:39:40 PM PDT 24 |
| Finished | Jun 04 12:39:59 PM PDT 24 |
| Peak memory | 198404 kb |
| Host | smart-90e5608b-1419-4127-bda7-7ba36a9dadd8 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1250753421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.1250753421 |
| Directory | /workspace/35.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/35.uart_rx_parity_err.1506919628 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 26374573083 ps |
| CPU time | 16.31 seconds |
| Started | Jun 04 12:39:37 PM PDT 24 |
| Finished | Jun 04 12:39:54 PM PDT 24 |
| Peak memory | 200288 kb |
| Host | smart-077a4325-dc1f-43a2-a95a-7917af3567e7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1506919628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.1506919628 |
| Directory | /workspace/35.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/35.uart_rx_start_bit_filter.3755904509 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 3915652988 ps |
| CPU time | 1.07 seconds |
| Started | Jun 04 12:39:38 PM PDT 24 |
| Finished | Jun 04 12:39:40 PM PDT 24 |
| Peak memory | 196228 kb |
| Host | smart-deacf70a-6779-41c3-a614-3557e5f648ec |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3755904509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.3755904509 |
| Directory | /workspace/35.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/35.uart_smoke.2454002825 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 958073414 ps |
| CPU time | 1.66 seconds |
| Started | Jun 04 12:39:39 PM PDT 24 |
| Finished | Jun 04 12:39:41 PM PDT 24 |
| Peak memory | 199948 kb |
| Host | smart-c1404301-1cd6-44c8-87b0-9ba13ddd0cb1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2454002825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_smoke.2454002825 |
| Directory | /workspace/35.uart_smoke/latest |
| Test location | /workspace/coverage/default/35.uart_stress_all.1914945375 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 77189987342 ps |
| CPU time | 131.83 seconds |
| Started | Jun 04 12:39:49 PM PDT 24 |
| Finished | Jun 04 12:42:02 PM PDT 24 |
| Peak memory | 200792 kb |
| Host | smart-48cfbbb1-3ff4-432a-ae54-f2838aed733e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914945375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.1914945375 |
| Directory | /workspace/35.uart_stress_all/latest |
| Test location | /workspace/coverage/default/35.uart_tx_ovrd.403417829 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 6580389751 ps |
| CPU time | 9.97 seconds |
| Started | Jun 04 12:39:37 PM PDT 24 |
| Finished | Jun 04 12:39:48 PM PDT 24 |
| Peak memory | 199488 kb |
| Host | smart-42528d6c-f1ab-475f-80ee-b55c6978eafa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=403417829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.403417829 |
| Directory | /workspace/35.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/35.uart_tx_rx.2620218004 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 101713167527 ps |
| CPU time | 181.88 seconds |
| Started | Jun 04 12:39:39 PM PDT 24 |
| Finished | Jun 04 12:42:42 PM PDT 24 |
| Peak memory | 200068 kb |
| Host | smart-a2bea502-a26f-4a96-a505-85961446ae05 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2620218004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.2620218004 |
| Directory | /workspace/35.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/36.uart_alert_test.879727663 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 35495253 ps |
| CPU time | 0.54 seconds |
| Started | Jun 04 12:39:49 PM PDT 24 |
| Finished | Jun 04 12:39:51 PM PDT 24 |
| Peak memory | 194944 kb |
| Host | smart-65c12abf-1b04-453f-9fa4-8f292a4d3311 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879727663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.879727663 |
| Directory | /workspace/36.uart_alert_test/latest |
| Test location | /workspace/coverage/default/36.uart_fifo_full.1111499338 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 127438693312 ps |
| CPU time | 206.72 seconds |
| Started | Jun 04 12:39:49 PM PDT 24 |
| Finished | Jun 04 12:43:17 PM PDT 24 |
| Peak memory | 200384 kb |
| Host | smart-d1ed66ab-3717-4342-87d2-57cdc18a7de2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1111499338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.1111499338 |
| Directory | /workspace/36.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/36.uart_fifo_overflow.2992829490 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 9039706601 ps |
| CPU time | 15.31 seconds |
| Started | Jun 04 12:39:49 PM PDT 24 |
| Finished | Jun 04 12:40:05 PM PDT 24 |
| Peak memory | 200096 kb |
| Host | smart-0379dcbf-0dd0-4126-9eb0-b5c1b2c6e7b5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2992829490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.2992829490 |
| Directory | /workspace/36.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/36.uart_fifo_reset.1655897498 |
| Short name | T1047 |
| Test name | |
| Test status | |
| Simulation time | 390191265356 ps |
| CPU time | 100.07 seconds |
| Started | Jun 04 12:39:51 PM PDT 24 |
| Finished | Jun 04 12:41:32 PM PDT 24 |
| Peak memory | 200356 kb |
| Host | smart-0e262af1-9331-475e-81ec-34e3528db1a3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1655897498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.1655897498 |
| Directory | /workspace/36.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/36.uart_intr.3522483730 |
| Short name | T1045 |
| Test name | |
| Test status | |
| Simulation time | 67819972801 ps |
| CPU time | 109.9 seconds |
| Started | Jun 04 12:39:49 PM PDT 24 |
| Finished | Jun 04 12:41:40 PM PDT 24 |
| Peak memory | 200040 kb |
| Host | smart-5d9d48ec-3b71-4251-9367-0930c6b6186d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522483730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.3522483730 |
| Directory | /workspace/36.uart_intr/latest |
| Test location | /workspace/coverage/default/36.uart_loopback.733481694 |
| Short name | T1017 |
| Test name | |
| Test status | |
| Simulation time | 5420902416 ps |
| CPU time | 4.35 seconds |
| Started | Jun 04 12:39:48 PM PDT 24 |
| Finished | Jun 04 12:39:54 PM PDT 24 |
| Peak memory | 198648 kb |
| Host | smart-3e3a406f-e1ec-4df6-99a4-d1f2f7027ffc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=733481694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_loopback.733481694 |
| Directory | /workspace/36.uart_loopback/latest |
| Test location | /workspace/coverage/default/36.uart_noise_filter.3871873994 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 18918221894 ps |
| CPU time | 18.41 seconds |
| Started | Jun 04 12:39:47 PM PDT 24 |
| Finished | Jun 04 12:40:07 PM PDT 24 |
| Peak memory | 198576 kb |
| Host | smart-b96038cf-3747-4543-b7de-e0f16d7aa8c2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3871873994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_noise_filter.3871873994 |
| Directory | /workspace/36.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/36.uart_perf.1124262198 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 17866483082 ps |
| CPU time | 512.29 seconds |
| Started | Jun 04 12:39:47 PM PDT 24 |
| Finished | Jun 04 12:48:21 PM PDT 24 |
| Peak memory | 200212 kb |
| Host | smart-b3cfa373-55fe-46b5-8d76-be92a5535bb9 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1124262198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.1124262198 |
| Directory | /workspace/36.uart_perf/latest |
| Test location | /workspace/coverage/default/36.uart_rx_oversample.3400022682 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 6544925224 ps |
| CPU time | 46.53 seconds |
| Started | Jun 04 12:39:49 PM PDT 24 |
| Finished | Jun 04 12:40:37 PM PDT 24 |
| Peak memory | 198440 kb |
| Host | smart-ab2bd2ae-69c2-4cb0-a9ba-c1bcdf17d675 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3400022682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.3400022682 |
| Directory | /workspace/36.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/36.uart_rx_parity_err.2216326819 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 192981758866 ps |
| CPU time | 110.37 seconds |
| Started | Jun 04 12:39:47 PM PDT 24 |
| Finished | Jun 04 12:41:39 PM PDT 24 |
| Peak memory | 200264 kb |
| Host | smart-cbd00a68-1d2a-4be9-b9e4-e2437e478d28 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2216326819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.2216326819 |
| Directory | /workspace/36.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/36.uart_rx_start_bit_filter.1730333819 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 32383701855 ps |
| CPU time | 10.51 seconds |
| Started | Jun 04 12:39:46 PM PDT 24 |
| Finished | Jun 04 12:39:58 PM PDT 24 |
| Peak memory | 196488 kb |
| Host | smart-edbc61c3-ef0f-40aa-85be-5919bf6edb9f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1730333819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.1730333819 |
| Directory | /workspace/36.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/36.uart_smoke.1678784817 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 490233330 ps |
| CPU time | 1.71 seconds |
| Started | Jun 04 12:39:48 PM PDT 24 |
| Finished | Jun 04 12:39:51 PM PDT 24 |
| Peak memory | 199196 kb |
| Host | smart-50d769f2-e7b5-40c7-b6ba-0127745706a0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1678784817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_smoke.1678784817 |
| Directory | /workspace/36.uart_smoke/latest |
| Test location | /workspace/coverage/default/36.uart_stress_all.172976655 |
| Short name | T1134 |
| Test name | |
| Test status | |
| Simulation time | 44286965618 ps |
| CPU time | 7.26 seconds |
| Started | Jun 04 12:39:50 PM PDT 24 |
| Finished | Jun 04 12:39:58 PM PDT 24 |
| Peak memory | 197420 kb |
| Host | smart-db50c07a-9f81-42da-aea9-1e8183ce1696 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172976655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.172976655 |
| Directory | /workspace/36.uart_stress_all/latest |
| Test location | /workspace/coverage/default/36.uart_stress_all_with_rand_reset.1854639250 |
| Short name | T1152 |
| Test name | |
| Test status | |
| Simulation time | 77369533739 ps |
| CPU time | 254.61 seconds |
| Started | Jun 04 12:39:49 PM PDT 24 |
| Finished | Jun 04 12:44:05 PM PDT 24 |
| Peak memory | 217004 kb |
| Host | smart-be4136eb-2703-4016-b185-020e920a9beb |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854639250 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 36.uart_stress_all_with_rand_reset.1854639250 |
| Directory | /workspace/36.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/36.uart_tx_ovrd.28219721 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 895492365 ps |
| CPU time | 4.14 seconds |
| Started | Jun 04 12:39:47 PM PDT 24 |
| Finished | Jun 04 12:39:53 PM PDT 24 |
| Peak memory | 198880 kb |
| Host | smart-f5db34af-5d3a-4809-9a9f-ec7cd748cfcd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=28219721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.28219721 |
| Directory | /workspace/36.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/36.uart_tx_rx.1393852240 |
| Short name | T1171 |
| Test name | |
| Test status | |
| Simulation time | 13714898489 ps |
| CPU time | 24.51 seconds |
| Started | Jun 04 12:39:48 PM PDT 24 |
| Finished | Jun 04 12:40:14 PM PDT 24 |
| Peak memory | 200280 kb |
| Host | smart-b265987f-3cf4-4b03-9254-d45084c5a27f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1393852240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.1393852240 |
| Directory | /workspace/36.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/37.uart_alert_test.3039293637 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 14809961 ps |
| CPU time | 0.59 seconds |
| Started | Jun 04 12:39:59 PM PDT 24 |
| Finished | Jun 04 12:40:00 PM PDT 24 |
| Peak memory | 195664 kb |
| Host | smart-89a73e4b-605d-49ae-a6b3-1f23320bff80 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039293637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.3039293637 |
| Directory | /workspace/37.uart_alert_test/latest |
| Test location | /workspace/coverage/default/37.uart_fifo_full.1164982421 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 24599234648 ps |
| CPU time | 25.73 seconds |
| Started | Jun 04 12:39:47 PM PDT 24 |
| Finished | Jun 04 12:40:15 PM PDT 24 |
| Peak memory | 200212 kb |
| Host | smart-dbbd375c-4765-40df-971c-33320c565dda |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1164982421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.1164982421 |
| Directory | /workspace/37.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/37.uart_fifo_overflow.105089539 |
| Short name | T1126 |
| Test name | |
| Test status | |
| Simulation time | 169195575888 ps |
| CPU time | 81.71 seconds |
| Started | Jun 04 12:39:50 PM PDT 24 |
| Finished | Jun 04 12:41:12 PM PDT 24 |
| Peak memory | 200192 kb |
| Host | smart-bda30c81-6128-4cf1-bdbb-4f2f4ce6af8c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=105089539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.105089539 |
| Directory | /workspace/37.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/37.uart_fifo_reset.181522883 |
| Short name | T1112 |
| Test name | |
| Test status | |
| Simulation time | 87363951084 ps |
| CPU time | 133.73 seconds |
| Started | Jun 04 12:39:48 PM PDT 24 |
| Finished | Jun 04 12:42:03 PM PDT 24 |
| Peak memory | 200204 kb |
| Host | smart-a97972bb-138e-4957-9f26-167d0629ddd8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=181522883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.181522883 |
| Directory | /workspace/37.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/37.uart_long_xfer_wo_dly.3596008004 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 125799637535 ps |
| CPU time | 915.79 seconds |
| Started | Jun 04 12:39:49 PM PDT 24 |
| Finished | Jun 04 12:55:06 PM PDT 24 |
| Peak memory | 200192 kb |
| Host | smart-c9558d56-5cb8-4010-9e13-bec665d0f74f |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3596008004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.3596008004 |
| Directory | /workspace/37.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/37.uart_loopback.1986857519 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 11006689361 ps |
| CPU time | 7.74 seconds |
| Started | Jun 04 12:39:48 PM PDT 24 |
| Finished | Jun 04 12:39:57 PM PDT 24 |
| Peak memory | 200300 kb |
| Host | smart-dbbba81a-5f57-4d3d-a192-4d352057651c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1986857519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_loopback.1986857519 |
| Directory | /workspace/37.uart_loopback/latest |
| Test location | /workspace/coverage/default/37.uart_noise_filter.3798020344 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 15350326076 ps |
| CPU time | 28.67 seconds |
| Started | Jun 04 12:39:48 PM PDT 24 |
| Finished | Jun 04 12:40:18 PM PDT 24 |
| Peak memory | 199972 kb |
| Host | smart-9763659b-78e7-4ef9-b4c9-c2c05714f99f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3798020344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_noise_filter.3798020344 |
| Directory | /workspace/37.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/37.uart_perf.1693360598 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 17212274131 ps |
| CPU time | 223.73 seconds |
| Started | Jun 04 12:39:48 PM PDT 24 |
| Finished | Jun 04 12:43:33 PM PDT 24 |
| Peak memory | 200360 kb |
| Host | smart-6a4fe5ed-a9f8-4963-b370-61a07b45b3dd |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1693360598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.1693360598 |
| Directory | /workspace/37.uart_perf/latest |
| Test location | /workspace/coverage/default/37.uart_rx_oversample.181878634 |
| Short name | T1082 |
| Test name | |
| Test status | |
| Simulation time | 3907594524 ps |
| CPU time | 25.52 seconds |
| Started | Jun 04 12:39:48 PM PDT 24 |
| Finished | Jun 04 12:40:15 PM PDT 24 |
| Peak memory | 198600 kb |
| Host | smart-c41a4fb5-7239-42a9-9db7-04e6cda3ed13 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=181878634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.181878634 |
| Directory | /workspace/37.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/37.uart_rx_parity_err.3425624028 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 49978116315 ps |
| CPU time | 44.54 seconds |
| Started | Jun 04 12:39:47 PM PDT 24 |
| Finished | Jun 04 12:40:34 PM PDT 24 |
| Peak memory | 200192 kb |
| Host | smart-8e5aaeab-1f73-4158-9e3f-d05e64975216 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3425624028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.3425624028 |
| Directory | /workspace/37.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/37.uart_rx_start_bit_filter.102048799 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 37003627943 ps |
| CPU time | 20.48 seconds |
| Started | Jun 04 12:39:50 PM PDT 24 |
| Finished | Jun 04 12:40:12 PM PDT 24 |
| Peak memory | 196332 kb |
| Host | smart-94cedf6e-9b68-416a-b302-cca0abed6a90 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=102048799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.102048799 |
| Directory | /workspace/37.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/37.uart_smoke.604005165 |
| Short name | T965 |
| Test name | |
| Test status | |
| Simulation time | 5568306390 ps |
| CPU time | 36.84 seconds |
| Started | Jun 04 12:39:47 PM PDT 24 |
| Finished | Jun 04 12:40:25 PM PDT 24 |
| Peak memory | 200168 kb |
| Host | smart-732f6021-fc93-4048-9e5f-4af2baef2809 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=604005165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_smoke.604005165 |
| Directory | /workspace/37.uart_smoke/latest |
| Test location | /workspace/coverage/default/37.uart_stress_all.595758627 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 90050225191 ps |
| CPU time | 80.64 seconds |
| Started | Jun 04 12:39:48 PM PDT 24 |
| Finished | Jun 04 12:41:10 PM PDT 24 |
| Peak memory | 200344 kb |
| Host | smart-5e8e7347-21fa-4340-9e6e-65a2e8e7bd8e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595758627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.595758627 |
| Directory | /workspace/37.uart_stress_all/latest |
| Test location | /workspace/coverage/default/37.uart_stress_all_with_rand_reset.2872694552 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 47566606905 ps |
| CPU time | 390.38 seconds |
| Started | Jun 04 12:39:49 PM PDT 24 |
| Finished | Jun 04 12:46:21 PM PDT 24 |
| Peak memory | 216488 kb |
| Host | smart-7dca812a-8119-41d0-b19a-6123de51c179 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872694552 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 37.uart_stress_all_with_rand_reset.2872694552 |
| Directory | /workspace/37.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/37.uart_tx_ovrd.1314763652 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 965109907 ps |
| CPU time | 3.3 seconds |
| Started | Jun 04 12:39:50 PM PDT 24 |
| Finished | Jun 04 12:39:54 PM PDT 24 |
| Peak memory | 199720 kb |
| Host | smart-50d0bd40-b5b8-4d76-8fac-8675a8ecea9a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1314763652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.1314763652 |
| Directory | /workspace/37.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/37.uart_tx_rx.186713116 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 4526541151 ps |
| CPU time | 4.73 seconds |
| Started | Jun 04 12:39:49 PM PDT 24 |
| Finished | Jun 04 12:39:55 PM PDT 24 |
| Peak memory | 200048 kb |
| Host | smart-6d1f582a-a4f0-44c9-be77-bf2612ee6285 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=186713116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.186713116 |
| Directory | /workspace/37.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/38.uart_alert_test.3924137547 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 12450084 ps |
| CPU time | 0.53 seconds |
| Started | Jun 04 12:39:57 PM PDT 24 |
| Finished | Jun 04 12:39:58 PM PDT 24 |
| Peak memory | 195604 kb |
| Host | smart-ceafa179-41b6-40bd-8f4d-44d97c523150 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924137547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.3924137547 |
| Directory | /workspace/38.uart_alert_test/latest |
| Test location | /workspace/coverage/default/38.uart_fifo_full.2622824002 |
| Short name | T1144 |
| Test name | |
| Test status | |
| Simulation time | 29076983273 ps |
| CPU time | 14.83 seconds |
| Started | Jun 04 12:40:00 PM PDT 24 |
| Finished | Jun 04 12:40:16 PM PDT 24 |
| Peak memory | 200320 kb |
| Host | smart-82968b11-b5ec-44bc-9390-b6aac870165c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2622824002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.2622824002 |
| Directory | /workspace/38.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/38.uart_fifo_reset.1167027508 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 121900620393 ps |
| CPU time | 157.4 seconds |
| Started | Jun 04 12:39:58 PM PDT 24 |
| Finished | Jun 04 12:42:36 PM PDT 24 |
| Peak memory | 200296 kb |
| Host | smart-302076c0-82af-4048-8833-8526cd801f1c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1167027508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.1167027508 |
| Directory | /workspace/38.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/38.uart_intr.3732487361 |
| Short name | T1058 |
| Test name | |
| Test status | |
| Simulation time | 21572890553 ps |
| CPU time | 6.35 seconds |
| Started | Jun 04 12:39:59 PM PDT 24 |
| Finished | Jun 04 12:40:06 PM PDT 24 |
| Peak memory | 200208 kb |
| Host | smart-53045cfa-90d7-4654-9e16-054c0f5c1415 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732487361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.3732487361 |
| Directory | /workspace/38.uart_intr/latest |
| Test location | /workspace/coverage/default/38.uart_long_xfer_wo_dly.1579757016 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 94966524852 ps |
| CPU time | 240.61 seconds |
| Started | Jun 04 12:39:58 PM PDT 24 |
| Finished | Jun 04 12:43:59 PM PDT 24 |
| Peak memory | 200168 kb |
| Host | smart-50222da2-1cf6-41f5-95bd-7781cc697539 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1579757016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.1579757016 |
| Directory | /workspace/38.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/38.uart_loopback.4248563252 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 10531278166 ps |
| CPU time | 17.98 seconds |
| Started | Jun 04 12:39:58 PM PDT 24 |
| Finished | Jun 04 12:40:16 PM PDT 24 |
| Peak memory | 198984 kb |
| Host | smart-8d0260a6-f7e2-49b6-afee-b9f408d103bd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4248563252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_loopback.4248563252 |
| Directory | /workspace/38.uart_loopback/latest |
| Test location | /workspace/coverage/default/38.uart_noise_filter.3084755351 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 91984502565 ps |
| CPU time | 13.13 seconds |
| Started | Jun 04 12:39:58 PM PDT 24 |
| Finished | Jun 04 12:40:12 PM PDT 24 |
| Peak memory | 199704 kb |
| Host | smart-26d31bbf-2ae0-4347-a2d0-1b644767c194 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3084755351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_noise_filter.3084755351 |
| Directory | /workspace/38.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/38.uart_perf.2946942780 |
| Short name | T1090 |
| Test name | |
| Test status | |
| Simulation time | 17256877146 ps |
| CPU time | 376.38 seconds |
| Started | Jun 04 12:39:57 PM PDT 24 |
| Finished | Jun 04 12:46:14 PM PDT 24 |
| Peak memory | 200340 kb |
| Host | smart-58412608-b174-4424-8731-c9007d11d2ac |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2946942780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.2946942780 |
| Directory | /workspace/38.uart_perf/latest |
| Test location | /workspace/coverage/default/38.uart_rx_oversample.1910285390 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 3266095830 ps |
| CPU time | 5.84 seconds |
| Started | Jun 04 12:39:57 PM PDT 24 |
| Finished | Jun 04 12:40:03 PM PDT 24 |
| Peak memory | 198600 kb |
| Host | smart-75c288d0-effb-49e0-87f6-a11d639b1a6f |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1910285390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.1910285390 |
| Directory | /workspace/38.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/38.uart_rx_parity_err.3558815018 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 27849474214 ps |
| CPU time | 49.19 seconds |
| Started | Jun 04 12:40:00 PM PDT 24 |
| Finished | Jun 04 12:40:50 PM PDT 24 |
| Peak memory | 200216 kb |
| Host | smart-1b0883c0-6640-4a9f-8c8e-9126bd7ad3dd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3558815018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.3558815018 |
| Directory | /workspace/38.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/38.uart_rx_start_bit_filter.842493549 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 4566392817 ps |
| CPU time | 2.54 seconds |
| Started | Jun 04 12:40:00 PM PDT 24 |
| Finished | Jun 04 12:40:03 PM PDT 24 |
| Peak memory | 196228 kb |
| Host | smart-c9c54dd5-b261-4307-90a9-297bfd69b02c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=842493549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.842493549 |
| Directory | /workspace/38.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/38.uart_smoke.3839772740 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 781196651 ps |
| CPU time | 1.38 seconds |
| Started | Jun 04 12:39:57 PM PDT 24 |
| Finished | Jun 04 12:39:59 PM PDT 24 |
| Peak memory | 198496 kb |
| Host | smart-49f48805-bec1-4aae-badf-140d1b7e1047 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3839772740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_smoke.3839772740 |
| Directory | /workspace/38.uart_smoke/latest |
| Test location | /workspace/coverage/default/38.uart_stress_all.246073881 |
| Short name | T1100 |
| Test name | |
| Test status | |
| Simulation time | 257207874964 ps |
| CPU time | 1371.69 seconds |
| Started | Jun 04 12:39:59 PM PDT 24 |
| Finished | Jun 04 01:02:51 PM PDT 24 |
| Peak memory | 200292 kb |
| Host | smart-07b7ce11-a3eb-47c0-9a43-1b28dd1fd825 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246073881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.246073881 |
| Directory | /workspace/38.uart_stress_all/latest |
| Test location | /workspace/coverage/default/38.uart_stress_all_with_rand_reset.3416834068 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 1444482313875 ps |
| CPU time | 953.03 seconds |
| Started | Jun 04 12:39:57 PM PDT 24 |
| Finished | Jun 04 12:55:50 PM PDT 24 |
| Peak memory | 225056 kb |
| Host | smart-32027002-ee6e-4526-98be-8dc0d3bc20a3 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416834068 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 38.uart_stress_all_with_rand_reset.3416834068 |
| Directory | /workspace/38.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/38.uart_tx_ovrd.2980447358 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 790802621 ps |
| CPU time | 2.58 seconds |
| Started | Jun 04 12:39:57 PM PDT 24 |
| Finished | Jun 04 12:40:00 PM PDT 24 |
| Peak memory | 198384 kb |
| Host | smart-715b352a-905d-4031-8f6f-9b5adeae2a4b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2980447358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.2980447358 |
| Directory | /workspace/38.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/38.uart_tx_rx.1289266937 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 96496847458 ps |
| CPU time | 180.92 seconds |
| Started | Jun 04 12:39:57 PM PDT 24 |
| Finished | Jun 04 12:42:59 PM PDT 24 |
| Peak memory | 200192 kb |
| Host | smart-c8c92cf8-9d66-4094-aa0c-a3a94812f9f9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1289266937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.1289266937 |
| Directory | /workspace/38.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/39.uart_alert_test.166091491 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 16023285 ps |
| CPU time | 0.59 seconds |
| Started | Jun 04 12:40:04 PM PDT 24 |
| Finished | Jun 04 12:40:05 PM PDT 24 |
| Peak memory | 195592 kb |
| Host | smart-57c78ec4-5591-4d45-84db-d2357870fa1e |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166091491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.166091491 |
| Directory | /workspace/39.uart_alert_test/latest |
| Test location | /workspace/coverage/default/39.uart_fifo_full.1704197226 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 85771584042 ps |
| CPU time | 140.65 seconds |
| Started | Jun 04 12:39:57 PM PDT 24 |
| Finished | Jun 04 12:42:18 PM PDT 24 |
| Peak memory | 200120 kb |
| Host | smart-1899141a-a3ed-40af-8e01-4d2f61616157 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1704197226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.1704197226 |
| Directory | /workspace/39.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/39.uart_fifo_overflow.2808505378 |
| Short name | T1051 |
| Test name | |
| Test status | |
| Simulation time | 73903230347 ps |
| CPU time | 35.81 seconds |
| Started | Jun 04 12:39:59 PM PDT 24 |
| Finished | Jun 04 12:40:36 PM PDT 24 |
| Peak memory | 200132 kb |
| Host | smart-774d2e58-a805-4a9c-9c03-2ac2d05c8ed9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2808505378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.2808505378 |
| Directory | /workspace/39.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/39.uart_fifo_reset.2346727455 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 157084885990 ps |
| CPU time | 241.85 seconds |
| Started | Jun 04 12:39:58 PM PDT 24 |
| Finished | Jun 04 12:44:01 PM PDT 24 |
| Peak memory | 200232 kb |
| Host | smart-f4d79dfc-24d7-47b7-8a06-320745e2d981 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2346727455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.2346727455 |
| Directory | /workspace/39.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/39.uart_intr.571522426 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 11054534782 ps |
| CPU time | 9.07 seconds |
| Started | Jun 04 12:39:56 PM PDT 24 |
| Finished | Jun 04 12:40:06 PM PDT 24 |
| Peak memory | 196328 kb |
| Host | smart-121e66f2-7860-47a9-b476-6dcc07420f4e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571522426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.571522426 |
| Directory | /workspace/39.uart_intr/latest |
| Test location | /workspace/coverage/default/39.uart_long_xfer_wo_dly.170350256 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 93156452574 ps |
| CPU time | 871.3 seconds |
| Started | Jun 04 12:40:06 PM PDT 24 |
| Finished | Jun 04 12:54:39 PM PDT 24 |
| Peak memory | 200288 kb |
| Host | smart-507153c5-7d26-41ab-8f5e-f4aa368c0709 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=170350256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.170350256 |
| Directory | /workspace/39.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/39.uart_loopback.2391498307 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 5402575649 ps |
| CPU time | 12.63 seconds |
| Started | Jun 04 12:40:06 PM PDT 24 |
| Finished | Jun 04 12:40:20 PM PDT 24 |
| Peak memory | 199528 kb |
| Host | smart-3349b76c-2261-4742-b15d-da28740a6180 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2391498307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_loopback.2391498307 |
| Directory | /workspace/39.uart_loopback/latest |
| Test location | /workspace/coverage/default/39.uart_noise_filter.3103974479 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 2646802291 ps |
| CPU time | 5.29 seconds |
| Started | Jun 04 12:40:04 PM PDT 24 |
| Finished | Jun 04 12:40:10 PM PDT 24 |
| Peak memory | 194940 kb |
| Host | smart-57d379e7-05da-45c7-81be-95b55f1fab85 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3103974479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_noise_filter.3103974479 |
| Directory | /workspace/39.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/39.uart_perf.2572336081 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 20980457841 ps |
| CPU time | 1193.82 seconds |
| Started | Jun 04 12:40:04 PM PDT 24 |
| Finished | Jun 04 12:59:58 PM PDT 24 |
| Peak memory | 200180 kb |
| Host | smart-76ee68ae-61cf-4755-912a-b318dc4a9a45 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2572336081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.2572336081 |
| Directory | /workspace/39.uart_perf/latest |
| Test location | /workspace/coverage/default/39.uart_rx_oversample.2164409214 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 2231917482 ps |
| CPU time | 3.52 seconds |
| Started | Jun 04 12:39:58 PM PDT 24 |
| Finished | Jun 04 12:40:03 PM PDT 24 |
| Peak memory | 198152 kb |
| Host | smart-a969ab35-3f8c-4e3d-8fbf-1533a688e73d |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2164409214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.2164409214 |
| Directory | /workspace/39.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/39.uart_rx_parity_err.2986394133 |
| Short name | T935 |
| Test name | |
| Test status | |
| Simulation time | 19803140437 ps |
| CPU time | 35.16 seconds |
| Started | Jun 04 12:40:08 PM PDT 24 |
| Finished | Jun 04 12:40:44 PM PDT 24 |
| Peak memory | 200084 kb |
| Host | smart-b88bf0a4-6465-4c2e-bad4-a8dfac75cdbd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2986394133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.2986394133 |
| Directory | /workspace/39.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/39.uart_rx_start_bit_filter.847945800 |
| Short name | T1136 |
| Test name | |
| Test status | |
| Simulation time | 2278835667 ps |
| CPU time | 1.65 seconds |
| Started | Jun 04 12:40:09 PM PDT 24 |
| Finished | Jun 04 12:40:11 PM PDT 24 |
| Peak memory | 195616 kb |
| Host | smart-416d2767-bf6c-4fbf-a08b-50a455910c39 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=847945800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.847945800 |
| Directory | /workspace/39.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/39.uart_smoke.526853536 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 6146073979 ps |
| CPU time | 21 seconds |
| Started | Jun 04 12:39:58 PM PDT 24 |
| Finished | Jun 04 12:40:20 PM PDT 24 |
| Peak memory | 200096 kb |
| Host | smart-ad5e189d-2089-4973-90fb-f4e04b7cd054 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=526853536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_smoke.526853536 |
| Directory | /workspace/39.uart_smoke/latest |
| Test location | /workspace/coverage/default/39.uart_stress_all.428878524 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 151024923574 ps |
| CPU time | 370.16 seconds |
| Started | Jun 04 12:40:06 PM PDT 24 |
| Finished | Jun 04 12:46:18 PM PDT 24 |
| Peak memory | 200196 kb |
| Host | smart-bf3461a7-dfb0-4870-8a56-b3afab3b6f66 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428878524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.428878524 |
| Directory | /workspace/39.uart_stress_all/latest |
| Test location | /workspace/coverage/default/39.uart_stress_all_with_rand_reset.2774385600 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 196043210194 ps |
| CPU time | 241.65 seconds |
| Started | Jun 04 12:40:06 PM PDT 24 |
| Finished | Jun 04 12:44:10 PM PDT 24 |
| Peak memory | 216664 kb |
| Host | smart-5f027499-0bbc-48ef-aa70-64343d14f28d |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774385600 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 39.uart_stress_all_with_rand_reset.2774385600 |
| Directory | /workspace/39.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/39.uart_tx_ovrd.373516777 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 1594202567 ps |
| CPU time | 1.72 seconds |
| Started | Jun 04 12:40:07 PM PDT 24 |
| Finished | Jun 04 12:40:10 PM PDT 24 |
| Peak memory | 198396 kb |
| Host | smart-9c2e9736-1a60-4013-8a95-1122fc27c8b5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=373516777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.373516777 |
| Directory | /workspace/39.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/39.uart_tx_rx.1177690541 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 19490033828 ps |
| CPU time | 9.1 seconds |
| Started | Jun 04 12:40:01 PM PDT 24 |
| Finished | Jun 04 12:40:10 PM PDT 24 |
| Peak memory | 200172 kb |
| Host | smart-2262ebaa-c00a-4094-b725-e659553bf0b0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1177690541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.1177690541 |
| Directory | /workspace/39.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/4.uart_alert_test.904934787 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 29644986 ps |
| CPU time | 0.55 seconds |
| Started | Jun 04 12:36:59 PM PDT 24 |
| Finished | Jun 04 12:37:00 PM PDT 24 |
| Peak memory | 195712 kb |
| Host | smart-80504f2c-0999-4ca2-ab63-a9163e54e9fc |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904934787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.904934787 |
| Directory | /workspace/4.uart_alert_test/latest |
| Test location | /workspace/coverage/default/4.uart_fifo_full.1530593341 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 14640934042 ps |
| CPU time | 10.08 seconds |
| Started | Jun 04 12:37:00 PM PDT 24 |
| Finished | Jun 04 12:37:11 PM PDT 24 |
| Peak memory | 200344 kb |
| Host | smart-06f209a4-27fd-48bd-ae3c-32e02dee07df |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1530593341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.1530593341 |
| Directory | /workspace/4.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/4.uart_fifo_overflow.2654435366 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 26459101313 ps |
| CPU time | 52.65 seconds |
| Started | Jun 04 12:36:57 PM PDT 24 |
| Finished | Jun 04 12:37:51 PM PDT 24 |
| Peak memory | 200324 kb |
| Host | smart-852c0c97-32ab-436f-9734-de190e745449 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2654435366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.2654435366 |
| Directory | /workspace/4.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/4.uart_intr.3852598985 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 19388618393 ps |
| CPU time | 9.09 seconds |
| Started | Jun 04 12:36:58 PM PDT 24 |
| Finished | Jun 04 12:37:08 PM PDT 24 |
| Peak memory | 198464 kb |
| Host | smart-0d966bd8-f475-4871-be1e-be4068399a7b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852598985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.3852598985 |
| Directory | /workspace/4.uart_intr/latest |
| Test location | /workspace/coverage/default/4.uart_long_xfer_wo_dly.196930984 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 78375119243 ps |
| CPU time | 408.61 seconds |
| Started | Jun 04 12:37:04 PM PDT 24 |
| Finished | Jun 04 12:43:53 PM PDT 24 |
| Peak memory | 200232 kb |
| Host | smart-a3de049b-2e10-4eba-8f1d-9d3f697c9dcd |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=196930984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.196930984 |
| Directory | /workspace/4.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/4.uart_loopback.1143926566 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 2453960928 ps |
| CPU time | 5.09 seconds |
| Started | Jun 04 12:36:57 PM PDT 24 |
| Finished | Jun 04 12:37:03 PM PDT 24 |
| Peak memory | 196396 kb |
| Host | smart-637540a7-4a58-4591-ac18-cb9d02219c64 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1143926566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_loopback.1143926566 |
| Directory | /workspace/4.uart_loopback/latest |
| Test location | /workspace/coverage/default/4.uart_noise_filter.853113835 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 56462265944 ps |
| CPU time | 74.78 seconds |
| Started | Jun 04 12:36:58 PM PDT 24 |
| Finished | Jun 04 12:38:14 PM PDT 24 |
| Peak memory | 200304 kb |
| Host | smart-02336341-3f9c-427e-a8e1-2d0601ffeed9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=853113835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_noise_filter.853113835 |
| Directory | /workspace/4.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/4.uart_perf.3939872129 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 14941068911 ps |
| CPU time | 732.9 seconds |
| Started | Jun 04 12:36:58 PM PDT 24 |
| Finished | Jun 04 12:49:13 PM PDT 24 |
| Peak memory | 200324 kb |
| Host | smart-bf00b654-a8e9-4f06-9502-12b31706380d |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3939872129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.3939872129 |
| Directory | /workspace/4.uart_perf/latest |
| Test location | /workspace/coverage/default/4.uart_rx_oversample.3732336465 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 1605567345 ps |
| CPU time | 1.9 seconds |
| Started | Jun 04 12:37:04 PM PDT 24 |
| Finished | Jun 04 12:37:07 PM PDT 24 |
| Peak memory | 199304 kb |
| Host | smart-068345cc-8894-4230-a493-b9e7a69dcb1b |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3732336465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.3732336465 |
| Directory | /workspace/4.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/4.uart_rx_parity_err.2225721296 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 81429203622 ps |
| CPU time | 127.84 seconds |
| Started | Jun 04 12:36:59 PM PDT 24 |
| Finished | Jun 04 12:39:08 PM PDT 24 |
| Peak memory | 200292 kb |
| Host | smart-8cf2e100-be35-4c3f-abf7-945804e29fa0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2225721296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.2225721296 |
| Directory | /workspace/4.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/4.uart_rx_start_bit_filter.4097063312 |
| Short name | T1013 |
| Test name | |
| Test status | |
| Simulation time | 82225212119 ps |
| CPU time | 52.57 seconds |
| Started | Jun 04 12:37:00 PM PDT 24 |
| Finished | Jun 04 12:37:54 PM PDT 24 |
| Peak memory | 195884 kb |
| Host | smart-7320c9ac-5083-4bd8-abfd-4388cbb7090e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4097063312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.4097063312 |
| Directory | /workspace/4.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/4.uart_sec_cm.1301832380 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 69595643 ps |
| CPU time | 0.81 seconds |
| Started | Jun 04 12:36:56 PM PDT 24 |
| Finished | Jun 04 12:36:58 PM PDT 24 |
| Peak memory | 218388 kb |
| Host | smart-4096042a-0922-4b0e-9c15-9ee7c18a9903 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301832380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.1301832380 |
| Directory | /workspace/4.uart_sec_cm/latest |
| Test location | /workspace/coverage/default/4.uart_smoke.1439667961 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 11590784886 ps |
| CPU time | 19.03 seconds |
| Started | Jun 04 12:37:00 PM PDT 24 |
| Finished | Jun 04 12:37:20 PM PDT 24 |
| Peak memory | 200164 kb |
| Host | smart-9b83c031-3f0f-4a73-8103-641c237aebad |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1439667961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_smoke.1439667961 |
| Directory | /workspace/4.uart_smoke/latest |
| Test location | /workspace/coverage/default/4.uart_stress_all.1147532551 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 169501859208 ps |
| CPU time | 337.52 seconds |
| Started | Jun 04 12:36:59 PM PDT 24 |
| Finished | Jun 04 12:42:38 PM PDT 24 |
| Peak memory | 200348 kb |
| Host | smart-2e2c51c2-38ba-4d35-a81d-e59404fdd1e8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147532551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.1147532551 |
| Directory | /workspace/4.uart_stress_all/latest |
| Test location | /workspace/coverage/default/4.uart_stress_all_with_rand_reset.661591662 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 58194650446 ps |
| CPU time | 1990.06 seconds |
| Started | Jun 04 12:36:58 PM PDT 24 |
| Finished | Jun 04 01:10:09 PM PDT 24 |
| Peak memory | 225104 kb |
| Host | smart-420e4bba-55ef-4e37-ba22-ee9285f57419 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661591662 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 4.uart_stress_all_with_rand_reset.661591662 |
| Directory | /workspace/4.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/4.uart_tx_ovrd.1806123748 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 1716746184 ps |
| CPU time | 1.82 seconds |
| Started | Jun 04 12:37:00 PM PDT 24 |
| Finished | Jun 04 12:37:03 PM PDT 24 |
| Peak memory | 198880 kb |
| Host | smart-0f727d6d-20a0-4cab-bedb-67f1287cbd01 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1806123748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.1806123748 |
| Directory | /workspace/4.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/4.uart_tx_rx.3011832101 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 116000734992 ps |
| CPU time | 267.25 seconds |
| Started | Jun 04 12:36:57 PM PDT 24 |
| Finished | Jun 04 12:41:26 PM PDT 24 |
| Peak memory | 200200 kb |
| Host | smart-50907166-176d-47b8-8483-8414501e0766 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3011832101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.3011832101 |
| Directory | /workspace/4.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/40.uart_alert_test.4208220706 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 36259512 ps |
| CPU time | 0.54 seconds |
| Started | Jun 04 12:40:06 PM PDT 24 |
| Finished | Jun 04 12:40:09 PM PDT 24 |
| Peak memory | 195596 kb |
| Host | smart-300f2cc2-0bc8-42b9-a216-3e396286899a |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208220706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.4208220706 |
| Directory | /workspace/40.uart_alert_test/latest |
| Test location | /workspace/coverage/default/40.uart_fifo_full.2877714211 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 58393438987 ps |
| CPU time | 53.19 seconds |
| Started | Jun 04 12:40:06 PM PDT 24 |
| Finished | Jun 04 12:41:01 PM PDT 24 |
| Peak memory | 200252 kb |
| Host | smart-d4df6621-e02b-4977-9b4e-4209deaa3b8f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2877714211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.2877714211 |
| Directory | /workspace/40.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/40.uart_fifo_overflow.4149063265 |
| Short name | T1089 |
| Test name | |
| Test status | |
| Simulation time | 45566911032 ps |
| CPU time | 38.98 seconds |
| Started | Jun 04 12:40:06 PM PDT 24 |
| Finished | Jun 04 12:40:47 PM PDT 24 |
| Peak memory | 198876 kb |
| Host | smart-b9be7ec3-3db4-4118-98ef-2ce73d74633e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4149063265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.4149063265 |
| Directory | /workspace/40.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/40.uart_fifo_reset.519130877 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 167388423445 ps |
| CPU time | 74.39 seconds |
| Started | Jun 04 12:40:05 PM PDT 24 |
| Finished | Jun 04 12:41:21 PM PDT 24 |
| Peak memory | 200148 kb |
| Host | smart-029d053c-113e-4a6c-9b0b-9821991fa95c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=519130877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.519130877 |
| Directory | /workspace/40.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/40.uart_intr.2758076400 |
| Short name | T986 |
| Test name | |
| Test status | |
| Simulation time | 38976697624 ps |
| CPU time | 74.64 seconds |
| Started | Jun 04 12:40:06 PM PDT 24 |
| Finished | Jun 04 12:41:23 PM PDT 24 |
| Peak memory | 200252 kb |
| Host | smart-e4feba0c-8308-4568-9fe5-cf98b0b94e75 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758076400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.2758076400 |
| Directory | /workspace/40.uart_intr/latest |
| Test location | /workspace/coverage/default/40.uart_long_xfer_wo_dly.1008818661 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 82136783353 ps |
| CPU time | 97.13 seconds |
| Started | Jun 04 12:40:04 PM PDT 24 |
| Finished | Jun 04 12:41:42 PM PDT 24 |
| Peak memory | 200232 kb |
| Host | smart-7def122c-ceee-407d-b410-45b6bc7a6314 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1008818661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.1008818661 |
| Directory | /workspace/40.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/40.uart_loopback.2702624708 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 8969152847 ps |
| CPU time | 17.83 seconds |
| Started | Jun 04 12:40:06 PM PDT 24 |
| Finished | Jun 04 12:40:25 PM PDT 24 |
| Peak memory | 198324 kb |
| Host | smart-54c551e1-e8cf-405c-89c7-2ad9bfd4584d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2702624708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_loopback.2702624708 |
| Directory | /workspace/40.uart_loopback/latest |
| Test location | /workspace/coverage/default/40.uart_noise_filter.3411546550 |
| Short name | T1163 |
| Test name | |
| Test status | |
| Simulation time | 15834234566 ps |
| CPU time | 9.04 seconds |
| Started | Jun 04 12:40:08 PM PDT 24 |
| Finished | Jun 04 12:40:18 PM PDT 24 |
| Peak memory | 198884 kb |
| Host | smart-80a3b532-4130-4de7-be93-c3d0e329f024 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3411546550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_noise_filter.3411546550 |
| Directory | /workspace/40.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/40.uart_perf.1265980472 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 21466635507 ps |
| CPU time | 1237.08 seconds |
| Started | Jun 04 12:40:05 PM PDT 24 |
| Finished | Jun 04 01:00:44 PM PDT 24 |
| Peak memory | 200320 kb |
| Host | smart-30ca8e2d-6dc4-4586-833c-d5f34db5dd1a |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1265980472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.1265980472 |
| Directory | /workspace/40.uart_perf/latest |
| Test location | /workspace/coverage/default/40.uart_rx_oversample.243968704 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 4415707234 ps |
| CPU time | 19.45 seconds |
| Started | Jun 04 12:40:06 PM PDT 24 |
| Finished | Jun 04 12:40:27 PM PDT 24 |
| Peak memory | 198432 kb |
| Host | smart-10ba3b5a-3b87-400a-abd0-d646f1e7b7f6 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=243968704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.243968704 |
| Directory | /workspace/40.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/40.uart_rx_parity_err.2162783155 |
| Short name | T1104 |
| Test name | |
| Test status | |
| Simulation time | 110789358275 ps |
| CPU time | 202.3 seconds |
| Started | Jun 04 12:40:06 PM PDT 24 |
| Finished | Jun 04 12:43:30 PM PDT 24 |
| Peak memory | 200120 kb |
| Host | smart-7dd669ef-23af-409f-9b11-a1ae1daa32cb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2162783155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.2162783155 |
| Directory | /workspace/40.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/40.uart_rx_start_bit_filter.2600039142 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 3248127840 ps |
| CPU time | 5.85 seconds |
| Started | Jun 04 12:40:05 PM PDT 24 |
| Finished | Jun 04 12:40:11 PM PDT 24 |
| Peak memory | 196228 kb |
| Host | smart-dfbd47f4-b507-4af6-bdf8-961bf7e14843 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2600039142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.2600039142 |
| Directory | /workspace/40.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/40.uart_smoke.1256745069 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 6215210538 ps |
| CPU time | 10.16 seconds |
| Started | Jun 04 12:40:06 PM PDT 24 |
| Finished | Jun 04 12:40:18 PM PDT 24 |
| Peak memory | 200320 kb |
| Host | smart-d544d93f-6e78-4497-a1b2-a543049f444b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1256745069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_smoke.1256745069 |
| Directory | /workspace/40.uart_smoke/latest |
| Test location | /workspace/coverage/default/40.uart_stress_all.488722633 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 106299500219 ps |
| CPU time | 171.66 seconds |
| Started | Jun 04 12:40:05 PM PDT 24 |
| Finished | Jun 04 12:42:59 PM PDT 24 |
| Peak memory | 208688 kb |
| Host | smart-f2ff4628-2caf-4d06-b5e3-594a4de5b175 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488722633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.488722633 |
| Directory | /workspace/40.uart_stress_all/latest |
| Test location | /workspace/coverage/default/40.uart_stress_all_with_rand_reset.2177031635 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 650759639433 ps |
| CPU time | 1239.82 seconds |
| Started | Jun 04 12:40:06 PM PDT 24 |
| Finished | Jun 04 01:00:47 PM PDT 24 |
| Peak memory | 225276 kb |
| Host | smart-ebd42d46-0cb5-41d2-bc55-58cc7bf971b5 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177031635 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 40.uart_stress_all_with_rand_reset.2177031635 |
| Directory | /workspace/40.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/40.uart_tx_ovrd.2361845118 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 567826902 ps |
| CPU time | 1.95 seconds |
| Started | Jun 04 12:40:06 PM PDT 24 |
| Finished | Jun 04 12:40:10 PM PDT 24 |
| Peak memory | 198544 kb |
| Host | smart-d7ff812a-746f-425a-b428-4e0ffbac4c36 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2361845118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.2361845118 |
| Directory | /workspace/40.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/40.uart_tx_rx.2536384014 |
| Short name | T964 |
| Test name | |
| Test status | |
| Simulation time | 21959331479 ps |
| CPU time | 9.33 seconds |
| Started | Jun 04 12:40:06 PM PDT 24 |
| Finished | Jun 04 12:40:18 PM PDT 24 |
| Peak memory | 200316 kb |
| Host | smart-286eaed9-b689-4155-98f7-81e59b6ac43c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2536384014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.2536384014 |
| Directory | /workspace/40.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/41.uart_alert_test.3858230302 |
| Short name | T1176 |
| Test name | |
| Test status | |
| Simulation time | 14847550 ps |
| CPU time | 0.58 seconds |
| Started | Jun 04 12:40:16 PM PDT 24 |
| Finished | Jun 04 12:40:17 PM PDT 24 |
| Peak memory | 195572 kb |
| Host | smart-a04f7b64-6bed-4086-9877-081abdb2bf9f |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858230302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.3858230302 |
| Directory | /workspace/41.uart_alert_test/latest |
| Test location | /workspace/coverage/default/41.uart_fifo_full.2929641994 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 22752703767 ps |
| CPU time | 26.16 seconds |
| Started | Jun 04 12:40:09 PM PDT 24 |
| Finished | Jun 04 12:40:35 PM PDT 24 |
| Peak memory | 200360 kb |
| Host | smart-de5beb30-514d-41f7-b445-0c9bdcd60783 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2929641994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.2929641994 |
| Directory | /workspace/41.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/41.uart_fifo_overflow.1437042908 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 21926428979 ps |
| CPU time | 35.68 seconds |
| Started | Jun 04 12:40:05 PM PDT 24 |
| Finished | Jun 04 12:40:42 PM PDT 24 |
| Peak memory | 199948 kb |
| Host | smart-6f05273a-a575-4fc3-b020-9cd9dc80a82e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1437042908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.1437042908 |
| Directory | /workspace/41.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/41.uart_fifo_reset.923405132 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 34275275241 ps |
| CPU time | 20.73 seconds |
| Started | Jun 04 12:40:06 PM PDT 24 |
| Finished | Jun 04 12:40:29 PM PDT 24 |
| Peak memory | 200192 kb |
| Host | smart-5d7027fe-664e-4bd7-8f0c-8778a7842270 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=923405132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.923405132 |
| Directory | /workspace/41.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/41.uart_intr.3663284868 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 29830723555 ps |
| CPU time | 27.98 seconds |
| Started | Jun 04 12:40:17 PM PDT 24 |
| Finished | Jun 04 12:40:46 PM PDT 24 |
| Peak memory | 200296 kb |
| Host | smart-a24416d5-a6dc-452a-83c7-7e154620d5b0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663284868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.3663284868 |
| Directory | /workspace/41.uart_intr/latest |
| Test location | /workspace/coverage/default/41.uart_long_xfer_wo_dly.3935347233 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 138025590630 ps |
| CPU time | 904.18 seconds |
| Started | Jun 04 12:40:14 PM PDT 24 |
| Finished | Jun 04 12:55:19 PM PDT 24 |
| Peak memory | 200296 kb |
| Host | smart-9e1b93b5-a361-4aa0-9f4c-72b145b723f0 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3935347233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.3935347233 |
| Directory | /workspace/41.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/41.uart_loopback.772659285 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 9818650668 ps |
| CPU time | 5.86 seconds |
| Started | Jun 04 12:40:16 PM PDT 24 |
| Finished | Jun 04 12:40:22 PM PDT 24 |
| Peak memory | 199016 kb |
| Host | smart-b6975e93-e1a1-4823-87c6-5478f506d5c6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=772659285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_loopback.772659285 |
| Directory | /workspace/41.uart_loopback/latest |
| Test location | /workspace/coverage/default/41.uart_noise_filter.992498929 |
| Short name | T1054 |
| Test name | |
| Test status | |
| Simulation time | 92630192872 ps |
| CPU time | 66.76 seconds |
| Started | Jun 04 12:40:17 PM PDT 24 |
| Finished | Jun 04 12:41:25 PM PDT 24 |
| Peak memory | 199480 kb |
| Host | smart-0977aebb-ab38-4625-aea8-7bbd2ecfbdf7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=992498929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_noise_filter.992498929 |
| Directory | /workspace/41.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/41.uart_perf.2409262571 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 24128498054 ps |
| CPU time | 1170.96 seconds |
| Started | Jun 04 12:40:14 PM PDT 24 |
| Finished | Jun 04 12:59:46 PM PDT 24 |
| Peak memory | 200248 kb |
| Host | smart-1f9dfa15-3d7b-4592-9c50-17cf4b327eb3 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2409262571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.2409262571 |
| Directory | /workspace/41.uart_perf/latest |
| Test location | /workspace/coverage/default/41.uart_rx_oversample.1413521604 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 2429622953 ps |
| CPU time | 4.12 seconds |
| Started | Jun 04 12:40:06 PM PDT 24 |
| Finished | Jun 04 12:40:12 PM PDT 24 |
| Peak memory | 198232 kb |
| Host | smart-579733ad-08af-4bc2-8e65-5fa6abdcd9e8 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1413521604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.1413521604 |
| Directory | /workspace/41.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/41.uart_rx_parity_err.2444404594 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 497318745212 ps |
| CPU time | 127.71 seconds |
| Started | Jun 04 12:40:14 PM PDT 24 |
| Finished | Jun 04 12:42:23 PM PDT 24 |
| Peak memory | 200236 kb |
| Host | smart-d42520dc-0b46-461d-b201-01700dbe84a4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2444404594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.2444404594 |
| Directory | /workspace/41.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/41.uart_rx_start_bit_filter.1761417126 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 6228660495 ps |
| CPU time | 8.88 seconds |
| Started | Jun 04 12:40:16 PM PDT 24 |
| Finished | Jun 04 12:40:25 PM PDT 24 |
| Peak memory | 196488 kb |
| Host | smart-c4c95ad4-2409-40ae-80c2-d25fbb54324b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1761417126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.1761417126 |
| Directory | /workspace/41.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/41.uart_smoke.704820595 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 94398235 ps |
| CPU time | 0.77 seconds |
| Started | Jun 04 12:40:06 PM PDT 24 |
| Finished | Jun 04 12:40:08 PM PDT 24 |
| Peak memory | 197068 kb |
| Host | smart-66594529-ca1a-43ba-9fb0-1b4a8683c5a2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=704820595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_smoke.704820595 |
| Directory | /workspace/41.uart_smoke/latest |
| Test location | /workspace/coverage/default/41.uart_stress_all.3735208583 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 53243868186 ps |
| CPU time | 69.97 seconds |
| Started | Jun 04 12:40:17 PM PDT 24 |
| Finished | Jun 04 12:41:28 PM PDT 24 |
| Peak memory | 200204 kb |
| Host | smart-76307dfb-749f-4612-ac08-1cdcfc3f13a9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735208583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.3735208583 |
| Directory | /workspace/41.uart_stress_all/latest |
| Test location | /workspace/coverage/default/41.uart_stress_all_with_rand_reset.359522103 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 92595112694 ps |
| CPU time | 302.24 seconds |
| Started | Jun 04 12:40:15 PM PDT 24 |
| Finished | Jun 04 12:45:18 PM PDT 24 |
| Peak memory | 216756 kb |
| Host | smart-fef909f9-6057-40f7-aee4-93e5b217628e |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359522103 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 41.uart_stress_all_with_rand_reset.359522103 |
| Directory | /workspace/41.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/41.uart_tx_ovrd.2115692274 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 3719054000 ps |
| CPU time | 1.98 seconds |
| Started | Jun 04 12:40:19 PM PDT 24 |
| Finished | Jun 04 12:40:22 PM PDT 24 |
| Peak memory | 199352 kb |
| Host | smart-d702cded-b4eb-4227-b7d5-5963a2dd3456 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2115692274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.2115692274 |
| Directory | /workspace/41.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/41.uart_tx_rx.3581412064 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 50418210022 ps |
| CPU time | 21.38 seconds |
| Started | Jun 04 12:40:08 PM PDT 24 |
| Finished | Jun 04 12:40:31 PM PDT 24 |
| Peak memory | 200220 kb |
| Host | smart-bc381f7e-ca65-4185-b8ae-1d87b41b9065 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3581412064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.3581412064 |
| Directory | /workspace/41.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/42.uart_alert_test.2460824500 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 14953560 ps |
| CPU time | 0.57 seconds |
| Started | Jun 04 12:40:18 PM PDT 24 |
| Finished | Jun 04 12:40:20 PM PDT 24 |
| Peak memory | 195584 kb |
| Host | smart-d906c9ed-14d1-48c6-9b7e-1699567234c9 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460824500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.2460824500 |
| Directory | /workspace/42.uart_alert_test/latest |
| Test location | /workspace/coverage/default/42.uart_fifo_full.1815545834 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 154430341278 ps |
| CPU time | 30.03 seconds |
| Started | Jun 04 12:40:19 PM PDT 24 |
| Finished | Jun 04 12:40:50 PM PDT 24 |
| Peak memory | 200088 kb |
| Host | smart-7cbf740c-007b-4c9d-b335-97042ccd41e3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1815545834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.1815545834 |
| Directory | /workspace/42.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/42.uart_fifo_overflow.2088466326 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 13600150399 ps |
| CPU time | 21.57 seconds |
| Started | Jun 04 12:40:17 PM PDT 24 |
| Finished | Jun 04 12:40:39 PM PDT 24 |
| Peak memory | 200108 kb |
| Host | smart-82059f37-8992-4c94-bc84-4b11441fb619 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2088466326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.2088466326 |
| Directory | /workspace/42.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/42.uart_fifo_reset.1234773738 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 23884336009 ps |
| CPU time | 25.45 seconds |
| Started | Jun 04 12:40:16 PM PDT 24 |
| Finished | Jun 04 12:40:42 PM PDT 24 |
| Peak memory | 200204 kb |
| Host | smart-f50fe4c7-afa1-4cad-bedf-227469136090 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1234773738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.1234773738 |
| Directory | /workspace/42.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/42.uart_intr.3017134634 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 26149834628 ps |
| CPU time | 9.04 seconds |
| Started | Jun 04 12:40:18 PM PDT 24 |
| Finished | Jun 04 12:40:28 PM PDT 24 |
| Peak memory | 198920 kb |
| Host | smart-d4ffa533-ef32-4780-8b99-da25e46307df |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017134634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.3017134634 |
| Directory | /workspace/42.uart_intr/latest |
| Test location | /workspace/coverage/default/42.uart_long_xfer_wo_dly.4105293943 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 80780918276 ps |
| CPU time | 610.88 seconds |
| Started | Jun 04 12:40:17 PM PDT 24 |
| Finished | Jun 04 12:50:29 PM PDT 24 |
| Peak memory | 200280 kb |
| Host | smart-b1545579-2859-4f01-a887-945d42a1c728 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4105293943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.4105293943 |
| Directory | /workspace/42.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/42.uart_loopback.378141158 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 501460915 ps |
| CPU time | 1.52 seconds |
| Started | Jun 04 12:40:20 PM PDT 24 |
| Finished | Jun 04 12:40:22 PM PDT 24 |
| Peak memory | 197732 kb |
| Host | smart-cfebddc1-357b-4b86-b6b9-2fc1ec8769e5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=378141158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_loopback.378141158 |
| Directory | /workspace/42.uart_loopback/latest |
| Test location | /workspace/coverage/default/42.uart_noise_filter.1609131216 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 15009467894 ps |
| CPU time | 24.9 seconds |
| Started | Jun 04 12:40:20 PM PDT 24 |
| Finished | Jun 04 12:40:45 PM PDT 24 |
| Peak memory | 198856 kb |
| Host | smart-d03946f7-1c96-41a9-adc6-cc5a670ecf0b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1609131216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_noise_filter.1609131216 |
| Directory | /workspace/42.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/42.uart_perf.2741652052 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 17198479156 ps |
| CPU time | 405.03 seconds |
| Started | Jun 04 12:40:15 PM PDT 24 |
| Finished | Jun 04 12:47:01 PM PDT 24 |
| Peak memory | 200248 kb |
| Host | smart-c9401d5e-eea2-440c-94b4-ce2cbc72f1b3 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2741652052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.2741652052 |
| Directory | /workspace/42.uart_perf/latest |
| Test location | /workspace/coverage/default/42.uart_rx_oversample.2886830580 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 2076398716 ps |
| CPU time | 2.17 seconds |
| Started | Jun 04 12:40:17 PM PDT 24 |
| Finished | Jun 04 12:40:21 PM PDT 24 |
| Peak memory | 199216 kb |
| Host | smart-a1cbc8a1-a359-413f-aa25-bb34951116c1 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2886830580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.2886830580 |
| Directory | /workspace/42.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/42.uart_rx_parity_err.3395950568 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 162977480319 ps |
| CPU time | 275.57 seconds |
| Started | Jun 04 12:40:17 PM PDT 24 |
| Finished | Jun 04 12:44:53 PM PDT 24 |
| Peak memory | 200232 kb |
| Host | smart-53938a02-8b1b-4568-8a26-485b0ea4434f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3395950568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.3395950568 |
| Directory | /workspace/42.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/42.uart_rx_start_bit_filter.252879090 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 3741141935 ps |
| CPU time | 7 seconds |
| Started | Jun 04 12:40:15 PM PDT 24 |
| Finished | Jun 04 12:40:22 PM PDT 24 |
| Peak memory | 196220 kb |
| Host | smart-3a52eb93-93a6-4b4e-af95-b4e6cd4bd140 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=252879090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.252879090 |
| Directory | /workspace/42.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/42.uart_smoke.39453454 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 527900388 ps |
| CPU time | 1.39 seconds |
| Started | Jun 04 12:40:16 PM PDT 24 |
| Finished | Jun 04 12:40:18 PM PDT 24 |
| Peak memory | 198856 kb |
| Host | smart-b761ea44-6570-41bf-975d-adc4f3ca2d5e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=39453454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_smoke.39453454 |
| Directory | /workspace/42.uart_smoke/latest |
| Test location | /workspace/coverage/default/42.uart_stress_all_with_rand_reset.416416208 |
| Short name | T1159 |
| Test name | |
| Test status | |
| Simulation time | 75586995745 ps |
| CPU time | 853.02 seconds |
| Started | Jun 04 12:40:20 PM PDT 24 |
| Finished | Jun 04 12:54:33 PM PDT 24 |
| Peak memory | 225156 kb |
| Host | smart-40b26d84-1235-439c-a874-f936291f5947 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416416208 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 42.uart_stress_all_with_rand_reset.416416208 |
| Directory | /workspace/42.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/42.uart_tx_ovrd.2203375724 |
| Short name | T1068 |
| Test name | |
| Test status | |
| Simulation time | 1799814953 ps |
| CPU time | 1.91 seconds |
| Started | Jun 04 12:40:17 PM PDT 24 |
| Finished | Jun 04 12:40:20 PM PDT 24 |
| Peak memory | 199324 kb |
| Host | smart-7eff706c-93c8-4c49-a766-0332215a0015 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2203375724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.2203375724 |
| Directory | /workspace/42.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/42.uart_tx_rx.233180833 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 90430560617 ps |
| CPU time | 200.44 seconds |
| Started | Jun 04 12:40:19 PM PDT 24 |
| Finished | Jun 04 12:43:40 PM PDT 24 |
| Peak memory | 200300 kb |
| Host | smart-75f5e480-b065-49db-bd40-f2d608d3a872 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=233180833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.233180833 |
| Directory | /workspace/42.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/43.uart_alert_test.2662147233 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 21410184 ps |
| CPU time | 0.53 seconds |
| Started | Jun 04 12:40:27 PM PDT 24 |
| Finished | Jun 04 12:40:28 PM PDT 24 |
| Peak memory | 194600 kb |
| Host | smart-c4cc0dc0-462f-4633-9f7c-912100efc392 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662147233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.2662147233 |
| Directory | /workspace/43.uart_alert_test/latest |
| Test location | /workspace/coverage/default/43.uart_fifo_full.3228765076 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 32344956179 ps |
| CPU time | 53.4 seconds |
| Started | Jun 04 12:40:18 PM PDT 24 |
| Finished | Jun 04 12:41:12 PM PDT 24 |
| Peak memory | 200168 kb |
| Host | smart-92cf802a-6ca5-4d93-8203-0205d1b890bf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3228765076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.3228765076 |
| Directory | /workspace/43.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/43.uart_fifo_overflow.332344851 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 42470251111 ps |
| CPU time | 37.48 seconds |
| Started | Jun 04 12:40:27 PM PDT 24 |
| Finished | Jun 04 12:41:06 PM PDT 24 |
| Peak memory | 200096 kb |
| Host | smart-d4dd049d-2ce3-45f5-98e1-9f7e3d4abc50 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=332344851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.332344851 |
| Directory | /workspace/43.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/43.uart_intr.3867763328 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 39778475000 ps |
| CPU time | 31.98 seconds |
| Started | Jun 04 12:40:29 PM PDT 24 |
| Finished | Jun 04 12:41:01 PM PDT 24 |
| Peak memory | 200152 kb |
| Host | smart-8e7b4d29-96dd-4948-a92a-bc06977a9e3e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867763328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.3867763328 |
| Directory | /workspace/43.uart_intr/latest |
| Test location | /workspace/coverage/default/43.uart_long_xfer_wo_dly.4001179783 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 162213155798 ps |
| CPU time | 1378.33 seconds |
| Started | Jun 04 12:40:26 PM PDT 24 |
| Finished | Jun 04 01:03:26 PM PDT 24 |
| Peak memory | 200168 kb |
| Host | smart-d613348a-e7da-4587-8f81-368314df1feb |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4001179783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.4001179783 |
| Directory | /workspace/43.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/43.uart_loopback.2961726694 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 2815584787 ps |
| CPU time | 1.97 seconds |
| Started | Jun 04 12:40:25 PM PDT 24 |
| Finished | Jun 04 12:40:28 PM PDT 24 |
| Peak memory | 197856 kb |
| Host | smart-60637cac-7fa0-4aa3-84d5-01d55f1e47d3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2961726694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_loopback.2961726694 |
| Directory | /workspace/43.uart_loopback/latest |
| Test location | /workspace/coverage/default/43.uart_noise_filter.1038926218 |
| Short name | T1175 |
| Test name | |
| Test status | |
| Simulation time | 31719443341 ps |
| CPU time | 55.99 seconds |
| Started | Jun 04 12:40:25 PM PDT 24 |
| Finished | Jun 04 12:41:22 PM PDT 24 |
| Peak memory | 198216 kb |
| Host | smart-bccc93b7-74d6-4bd0-9fa2-cbacf21dadca |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1038926218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_noise_filter.1038926218 |
| Directory | /workspace/43.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/43.uart_perf.181769038 |
| Short name | T950 |
| Test name | |
| Test status | |
| Simulation time | 10561196707 ps |
| CPU time | 266.3 seconds |
| Started | Jun 04 12:40:25 PM PDT 24 |
| Finished | Jun 04 12:44:53 PM PDT 24 |
| Peak memory | 200228 kb |
| Host | smart-331aa663-0887-40d9-b927-6e9b7aaa1d0d |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=181769038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.181769038 |
| Directory | /workspace/43.uart_perf/latest |
| Test location | /workspace/coverage/default/43.uart_rx_oversample.2647791146 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 3262336048 ps |
| CPU time | 6 seconds |
| Started | Jun 04 12:40:25 PM PDT 24 |
| Finished | Jun 04 12:40:32 PM PDT 24 |
| Peak memory | 198540 kb |
| Host | smart-c4efb3da-ecb0-44ca-a71b-cf98b74f7316 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2647791146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.2647791146 |
| Directory | /workspace/43.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/43.uart_rx_parity_err.3068988075 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 30134357291 ps |
| CPU time | 39.95 seconds |
| Started | Jun 04 12:40:27 PM PDT 24 |
| Finished | Jun 04 12:41:08 PM PDT 24 |
| Peak memory | 200324 kb |
| Host | smart-096a4206-8658-472f-b11a-390deaefdb5b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3068988075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.3068988075 |
| Directory | /workspace/43.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/43.uart_rx_start_bit_filter.311395851 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 1277485151 ps |
| CPU time | 1.15 seconds |
| Started | Jun 04 12:40:25 PM PDT 24 |
| Finished | Jun 04 12:40:27 PM PDT 24 |
| Peak memory | 195648 kb |
| Host | smart-1cb70c41-1059-4190-8af3-e4cc6e77a2db |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=311395851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.311395851 |
| Directory | /workspace/43.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/43.uart_smoke.3013919031 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 699248253 ps |
| CPU time | 2.14 seconds |
| Started | Jun 04 12:40:17 PM PDT 24 |
| Finished | Jun 04 12:40:20 PM PDT 24 |
| Peak memory | 198608 kb |
| Host | smart-e48f7188-ca7d-468f-9a1f-e610fccbc63b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3013919031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_smoke.3013919031 |
| Directory | /workspace/43.uart_smoke/latest |
| Test location | /workspace/coverage/default/43.uart_stress_all.4294927706 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 215016958953 ps |
| CPU time | 72.12 seconds |
| Started | Jun 04 12:40:25 PM PDT 24 |
| Finished | Jun 04 12:41:37 PM PDT 24 |
| Peak memory | 200144 kb |
| Host | smart-16f63b24-b1dc-4afc-b986-b413ddca3bc2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294927706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.4294927706 |
| Directory | /workspace/43.uart_stress_all/latest |
| Test location | /workspace/coverage/default/43.uart_stress_all_with_rand_reset.3944904899 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 237844243042 ps |
| CPU time | 1117.64 seconds |
| Started | Jun 04 12:40:26 PM PDT 24 |
| Finished | Jun 04 12:59:05 PM PDT 24 |
| Peak memory | 225200 kb |
| Host | smart-e1d6da98-759b-4bd3-af9a-6d3d4dc6fdc0 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944904899 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 43.uart_stress_all_with_rand_reset.3944904899 |
| Directory | /workspace/43.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/43.uart_tx_ovrd.2292452409 |
| Short name | T1145 |
| Test name | |
| Test status | |
| Simulation time | 12832803085 ps |
| CPU time | 23.5 seconds |
| Started | Jun 04 12:40:27 PM PDT 24 |
| Finished | Jun 04 12:40:52 PM PDT 24 |
| Peak memory | 199952 kb |
| Host | smart-30dfa883-a92c-4905-83e5-4f81dd211692 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2292452409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.2292452409 |
| Directory | /workspace/43.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/43.uart_tx_rx.1496461996 |
| Short name | T1012 |
| Test name | |
| Test status | |
| Simulation time | 57215724266 ps |
| CPU time | 131.31 seconds |
| Started | Jun 04 12:40:15 PM PDT 24 |
| Finished | Jun 04 12:42:27 PM PDT 24 |
| Peak memory | 200168 kb |
| Host | smart-afeb40dd-69fe-448f-b5de-0824ed75816f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1496461996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.1496461996 |
| Directory | /workspace/43.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/44.uart_alert_test.3659121023 |
| Short name | T1132 |
| Test name | |
| Test status | |
| Simulation time | 54268219 ps |
| CPU time | 0.57 seconds |
| Started | Jun 04 12:40:37 PM PDT 24 |
| Finished | Jun 04 12:40:39 PM PDT 24 |
| Peak memory | 195560 kb |
| Host | smart-10a4115d-219f-48e5-b127-5101294b3ea0 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659121023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.3659121023 |
| Directory | /workspace/44.uart_alert_test/latest |
| Test location | /workspace/coverage/default/44.uart_fifo_full.1614991778 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 50840276068 ps |
| CPU time | 34.29 seconds |
| Started | Jun 04 12:40:27 PM PDT 24 |
| Finished | Jun 04 12:41:02 PM PDT 24 |
| Peak memory | 200216 kb |
| Host | smart-1ec164bd-6ab6-4f1a-9374-37ce01380595 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1614991778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.1614991778 |
| Directory | /workspace/44.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/44.uart_fifo_overflow.3864679758 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 90304868429 ps |
| CPU time | 67.4 seconds |
| Started | Jun 04 12:40:26 PM PDT 24 |
| Finished | Jun 04 12:41:34 PM PDT 24 |
| Peak memory | 200328 kb |
| Host | smart-6cf14289-1ef4-4570-815a-bda1778ce039 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3864679758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.3864679758 |
| Directory | /workspace/44.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/44.uart_fifo_reset.1697282874 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 25842340985 ps |
| CPU time | 38.84 seconds |
| Started | Jun 04 12:40:35 PM PDT 24 |
| Finished | Jun 04 12:41:15 PM PDT 24 |
| Peak memory | 200164 kb |
| Host | smart-ad7c2b74-c075-4f5f-8205-85f0b9fd09c8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1697282874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.1697282874 |
| Directory | /workspace/44.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/44.uart_intr.3748300318 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 60827818116 ps |
| CPU time | 10.74 seconds |
| Started | Jun 04 12:40:37 PM PDT 24 |
| Finished | Jun 04 12:40:48 PM PDT 24 |
| Peak memory | 200252 kb |
| Host | smart-7a3682ff-5e48-4d81-b4d2-043e929ddebd |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748300318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.3748300318 |
| Directory | /workspace/44.uart_intr/latest |
| Test location | /workspace/coverage/default/44.uart_long_xfer_wo_dly.607558417 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 64508436821 ps |
| CPU time | 96.27 seconds |
| Started | Jun 04 12:40:37 PM PDT 24 |
| Finished | Jun 04 12:42:14 PM PDT 24 |
| Peak memory | 200328 kb |
| Host | smart-7a12955a-aed5-4ede-826d-86edfbe38f1a |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=607558417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.607558417 |
| Directory | /workspace/44.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/44.uart_loopback.2561029845 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 10009149666 ps |
| CPU time | 6.53 seconds |
| Started | Jun 04 12:40:39 PM PDT 24 |
| Finished | Jun 04 12:40:46 PM PDT 24 |
| Peak memory | 199668 kb |
| Host | smart-3dc777af-58d4-407e-b60b-a7a98ee9b4ba |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2561029845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_loopback.2561029845 |
| Directory | /workspace/44.uart_loopback/latest |
| Test location | /workspace/coverage/default/44.uart_noise_filter.1529424770 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 77327670147 ps |
| CPU time | 25.62 seconds |
| Started | Jun 04 12:40:36 PM PDT 24 |
| Finished | Jun 04 12:41:03 PM PDT 24 |
| Peak memory | 200296 kb |
| Host | smart-be03c9a4-0258-4333-9d03-9b4d919476da |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1529424770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_noise_filter.1529424770 |
| Directory | /workspace/44.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/44.uart_perf.1134890684 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 11328562552 ps |
| CPU time | 656.13 seconds |
| Started | Jun 04 12:40:37 PM PDT 24 |
| Finished | Jun 04 12:51:34 PM PDT 24 |
| Peak memory | 200188 kb |
| Host | smart-96814b98-476e-49d3-97a9-d1002ca96ee8 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1134890684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.1134890684 |
| Directory | /workspace/44.uart_perf/latest |
| Test location | /workspace/coverage/default/44.uart_rx_oversample.239811723 |
| Short name | T1153 |
| Test name | |
| Test status | |
| Simulation time | 4102399690 ps |
| CPU time | 16.62 seconds |
| Started | Jun 04 12:40:37 PM PDT 24 |
| Finished | Jun 04 12:40:55 PM PDT 24 |
| Peak memory | 198916 kb |
| Host | smart-74115269-533b-4517-a215-b312d92cfd4f |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=239811723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.239811723 |
| Directory | /workspace/44.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/44.uart_rx_parity_err.1995007726 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 162182559367 ps |
| CPU time | 67.06 seconds |
| Started | Jun 04 12:40:36 PM PDT 24 |
| Finished | Jun 04 12:41:45 PM PDT 24 |
| Peak memory | 200104 kb |
| Host | smart-89bf3f8f-07da-4754-8b2f-9bf59a39e063 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1995007726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.1995007726 |
| Directory | /workspace/44.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/44.uart_rx_start_bit_filter.4205105448 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 29331972713 ps |
| CPU time | 8.12 seconds |
| Started | Jun 04 12:40:36 PM PDT 24 |
| Finished | Jun 04 12:40:45 PM PDT 24 |
| Peak memory | 196220 kb |
| Host | smart-77edf0f4-18f6-4132-96b1-30500453e004 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4205105448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.4205105448 |
| Directory | /workspace/44.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/44.uart_smoke.1085653185 |
| Short name | T1099 |
| Test name | |
| Test status | |
| Simulation time | 768911137 ps |
| CPU time | 1.81 seconds |
| Started | Jun 04 12:40:26 PM PDT 24 |
| Finished | Jun 04 12:40:29 PM PDT 24 |
| Peak memory | 199012 kb |
| Host | smart-c9dbf7df-ec8b-4b8e-ae26-20ede67bd9f5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1085653185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_smoke.1085653185 |
| Directory | /workspace/44.uart_smoke/latest |
| Test location | /workspace/coverage/default/44.uart_stress_all.3757119983 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 339796051675 ps |
| CPU time | 159.37 seconds |
| Started | Jun 04 12:40:37 PM PDT 24 |
| Finished | Jun 04 12:43:18 PM PDT 24 |
| Peak memory | 200180 kb |
| Host | smart-87f16695-eb61-4513-80a5-397b92a28e20 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757119983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.3757119983 |
| Directory | /workspace/44.uart_stress_all/latest |
| Test location | /workspace/coverage/default/44.uart_stress_all_with_rand_reset.980060384 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 54641984833 ps |
| CPU time | 981.07 seconds |
| Started | Jun 04 12:40:37 PM PDT 24 |
| Finished | Jun 04 12:56:59 PM PDT 24 |
| Peak memory | 225112 kb |
| Host | smart-50bc15c9-31a0-4c37-84e3-589578f124c9 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980060384 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 44.uart_stress_all_with_rand_reset.980060384 |
| Directory | /workspace/44.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/44.uart_tx_ovrd.2313605522 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 1430475352 ps |
| CPU time | 3.06 seconds |
| Started | Jun 04 12:40:36 PM PDT 24 |
| Finished | Jun 04 12:40:40 PM PDT 24 |
| Peak memory | 199184 kb |
| Host | smart-e0bee550-acfc-4143-a922-30707a826644 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2313605522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.2313605522 |
| Directory | /workspace/44.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/44.uart_tx_rx.2182255420 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 16792968311 ps |
| CPU time | 29.24 seconds |
| Started | Jun 04 12:40:28 PM PDT 24 |
| Finished | Jun 04 12:40:58 PM PDT 24 |
| Peak memory | 200212 kb |
| Host | smart-fd39664d-8636-4996-941d-36be141be1c4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2182255420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.2182255420 |
| Directory | /workspace/44.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/45.uart_alert_test.1774609123 |
| Short name | T1071 |
| Test name | |
| Test status | |
| Simulation time | 17662228 ps |
| CPU time | 0.55 seconds |
| Started | Jun 04 12:40:35 PM PDT 24 |
| Finished | Jun 04 12:40:37 PM PDT 24 |
| Peak memory | 195716 kb |
| Host | smart-93f09f99-31c0-469b-bce0-2fcece388ac8 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774609123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.1774609123 |
| Directory | /workspace/45.uart_alert_test/latest |
| Test location | /workspace/coverage/default/45.uart_fifo_full.1734662766 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 284018903087 ps |
| CPU time | 140.73 seconds |
| Started | Jun 04 12:40:36 PM PDT 24 |
| Finished | Jun 04 12:42:58 PM PDT 24 |
| Peak memory | 200160 kb |
| Host | smart-c2e42bbd-f83b-4a70-b555-6d65018b5905 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1734662766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.1734662766 |
| Directory | /workspace/45.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/45.uart_fifo_overflow.3732983173 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 31172526700 ps |
| CPU time | 13.31 seconds |
| Started | Jun 04 12:40:36 PM PDT 24 |
| Finished | Jun 04 12:40:51 PM PDT 24 |
| Peak memory | 200232 kb |
| Host | smart-0445788a-aca0-4b94-b7cb-57a86bc52dd5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3732983173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.3732983173 |
| Directory | /workspace/45.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/45.uart_fifo_reset.3602484515 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 27377065944 ps |
| CPU time | 8.25 seconds |
| Started | Jun 04 12:40:37 PM PDT 24 |
| Finished | Jun 04 12:40:46 PM PDT 24 |
| Peak memory | 200352 kb |
| Host | smart-67a84687-a06a-4553-9f45-25a60e05911d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3602484515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.3602484515 |
| Directory | /workspace/45.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/45.uart_intr.2741580155 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 30458850484 ps |
| CPU time | 43.89 seconds |
| Started | Jun 04 12:40:35 PM PDT 24 |
| Finished | Jun 04 12:41:20 PM PDT 24 |
| Peak memory | 200060 kb |
| Host | smart-11d29500-5960-4b31-9e5f-45138ce716f1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741580155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.2741580155 |
| Directory | /workspace/45.uart_intr/latest |
| Test location | /workspace/coverage/default/45.uart_long_xfer_wo_dly.3685506785 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 78085324835 ps |
| CPU time | 193.39 seconds |
| Started | Jun 04 12:40:36 PM PDT 24 |
| Finished | Jun 04 12:43:51 PM PDT 24 |
| Peak memory | 200268 kb |
| Host | smart-613cfaee-7c89-44c9-bb84-c3e2638db8c9 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3685506785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.3685506785 |
| Directory | /workspace/45.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/45.uart_loopback.1440495289 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 1020094447 ps |
| CPU time | 1.58 seconds |
| Started | Jun 04 12:40:35 PM PDT 24 |
| Finished | Jun 04 12:40:38 PM PDT 24 |
| Peak memory | 196472 kb |
| Host | smart-bfb2f349-740b-4df9-aef0-adf9020fbdee |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1440495289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_loopback.1440495289 |
| Directory | /workspace/45.uart_loopback/latest |
| Test location | /workspace/coverage/default/45.uart_noise_filter.1913407845 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 159898003379 ps |
| CPU time | 85 seconds |
| Started | Jun 04 12:40:37 PM PDT 24 |
| Finished | Jun 04 12:42:03 PM PDT 24 |
| Peak memory | 215968 kb |
| Host | smart-ac8d48f5-898d-404d-8737-f482620e7a24 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1913407845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_noise_filter.1913407845 |
| Directory | /workspace/45.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/45.uart_perf.974207097 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 10840794672 ps |
| CPU time | 131.55 seconds |
| Started | Jun 04 12:40:36 PM PDT 24 |
| Finished | Jun 04 12:42:48 PM PDT 24 |
| Peak memory | 200276 kb |
| Host | smart-3508c3d1-6f01-4abc-ab86-59cc89f3875b |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=974207097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.974207097 |
| Directory | /workspace/45.uart_perf/latest |
| Test location | /workspace/coverage/default/45.uart_rx_oversample.4147785226 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 5380425751 ps |
| CPU time | 47.19 seconds |
| Started | Jun 04 12:40:36 PM PDT 24 |
| Finished | Jun 04 12:41:25 PM PDT 24 |
| Peak memory | 199032 kb |
| Host | smart-b5c917a4-84a1-4428-96dd-687a451bc7f3 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4147785226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.4147785226 |
| Directory | /workspace/45.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/45.uart_rx_parity_err.3745393482 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 20094739279 ps |
| CPU time | 53.58 seconds |
| Started | Jun 04 12:40:35 PM PDT 24 |
| Finished | Jun 04 12:41:29 PM PDT 24 |
| Peak memory | 200240 kb |
| Host | smart-84bfdb59-213c-494b-9e33-e9508125e327 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3745393482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.3745393482 |
| Directory | /workspace/45.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/45.uart_rx_start_bit_filter.3286349042 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 3005874029 ps |
| CPU time | 6.08 seconds |
| Started | Jun 04 12:40:36 PM PDT 24 |
| Finished | Jun 04 12:40:44 PM PDT 24 |
| Peak memory | 196268 kb |
| Host | smart-dcb58154-7df9-4c45-8e8e-330d4a2fb75d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3286349042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.3286349042 |
| Directory | /workspace/45.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/45.uart_smoke.1945989836 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 307559926 ps |
| CPU time | 1.15 seconds |
| Started | Jun 04 12:40:36 PM PDT 24 |
| Finished | Jun 04 12:40:39 PM PDT 24 |
| Peak memory | 198840 kb |
| Host | smart-cfde385e-1d06-454b-882e-f89ee1d95a63 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1945989836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_smoke.1945989836 |
| Directory | /workspace/45.uart_smoke/latest |
| Test location | /workspace/coverage/default/45.uart_stress_all.3073146545 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 139966222701 ps |
| CPU time | 17.42 seconds |
| Started | Jun 04 12:40:36 PM PDT 24 |
| Finished | Jun 04 12:40:54 PM PDT 24 |
| Peak memory | 200272 kb |
| Host | smart-f0d552fc-441c-4a6e-87cd-53fbca1fe47e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073146545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.3073146545 |
| Directory | /workspace/45.uart_stress_all/latest |
| Test location | /workspace/coverage/default/45.uart_stress_all_with_rand_reset.2999225259 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 148891376589 ps |
| CPU time | 721.92 seconds |
| Started | Jun 04 12:40:35 PM PDT 24 |
| Finished | Jun 04 12:52:38 PM PDT 24 |
| Peak memory | 216984 kb |
| Host | smart-e5d97ae7-9d6c-4cf4-ac70-530c4b3b6a0e |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999225259 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 45.uart_stress_all_with_rand_reset.2999225259 |
| Directory | /workspace/45.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/45.uart_tx_ovrd.1777107161 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 6067577351 ps |
| CPU time | 14.34 seconds |
| Started | Jun 04 12:40:36 PM PDT 24 |
| Finished | Jun 04 12:40:51 PM PDT 24 |
| Peak memory | 199916 kb |
| Host | smart-46f378a3-ab6d-413b-8474-5e5998741810 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1777107161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.1777107161 |
| Directory | /workspace/45.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/45.uart_tx_rx.1402032339 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 198638071373 ps |
| CPU time | 59.8 seconds |
| Started | Jun 04 12:40:36 PM PDT 24 |
| Finished | Jun 04 12:41:37 PM PDT 24 |
| Peak memory | 200308 kb |
| Host | smart-a35b0435-a925-40ea-a1c5-5c48e60ee410 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1402032339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.1402032339 |
| Directory | /workspace/45.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/46.uart_alert_test.3089371072 |
| Short name | T1149 |
| Test name | |
| Test status | |
| Simulation time | 36583996 ps |
| CPU time | 0.56 seconds |
| Started | Jun 04 12:40:48 PM PDT 24 |
| Finished | Jun 04 12:40:50 PM PDT 24 |
| Peak memory | 194692 kb |
| Host | smart-3c4ac46b-3855-47bc-a095-d8aa4e04f04b |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089371072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.3089371072 |
| Directory | /workspace/46.uart_alert_test/latest |
| Test location | /workspace/coverage/default/46.uart_fifo_full.687383564 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 145674581437 ps |
| CPU time | 334.86 seconds |
| Started | Jun 04 12:40:48 PM PDT 24 |
| Finished | Jun 04 12:46:24 PM PDT 24 |
| Peak memory | 200300 kb |
| Host | smart-b4f4a598-6284-47b9-8ee9-3e08b17b1dca |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=687383564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.687383564 |
| Directory | /workspace/46.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/46.uart_fifo_overflow.3910396326 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 52802236915 ps |
| CPU time | 25.29 seconds |
| Started | Jun 04 12:40:45 PM PDT 24 |
| Finished | Jun 04 12:41:12 PM PDT 24 |
| Peak memory | 200244 kb |
| Host | smart-fa89ac32-8b17-467a-a090-1782563abac2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3910396326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.3910396326 |
| Directory | /workspace/46.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/46.uart_fifo_reset.4040915497 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 14152507941 ps |
| CPU time | 12.23 seconds |
| Started | Jun 04 12:40:47 PM PDT 24 |
| Finished | Jun 04 12:41:00 PM PDT 24 |
| Peak memory | 199960 kb |
| Host | smart-e98355bf-76ca-4c40-bf79-6fa0758b4b16 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4040915497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.4040915497 |
| Directory | /workspace/46.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/46.uart_intr.1395004485 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 59372597485 ps |
| CPU time | 51.58 seconds |
| Started | Jun 04 12:40:46 PM PDT 24 |
| Finished | Jun 04 12:41:39 PM PDT 24 |
| Peak memory | 200088 kb |
| Host | smart-05e826fe-5878-482a-afdf-518d6a11f322 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395004485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.1395004485 |
| Directory | /workspace/46.uart_intr/latest |
| Test location | /workspace/coverage/default/46.uart_long_xfer_wo_dly.3180062528 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 296331829261 ps |
| CPU time | 181.48 seconds |
| Started | Jun 04 12:40:48 PM PDT 24 |
| Finished | Jun 04 12:43:50 PM PDT 24 |
| Peak memory | 200152 kb |
| Host | smart-c464bab1-38fd-46ff-9c0d-b0f7f72b8f2e |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3180062528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.3180062528 |
| Directory | /workspace/46.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/46.uart_loopback.1224405025 |
| Short name | T981 |
| Test name | |
| Test status | |
| Simulation time | 1307667770 ps |
| CPU time | 5.77 seconds |
| Started | Jun 04 12:40:46 PM PDT 24 |
| Finished | Jun 04 12:40:53 PM PDT 24 |
| Peak memory | 198688 kb |
| Host | smart-8954321f-1bf7-45af-8de7-b4ddb2806985 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1224405025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_loopback.1224405025 |
| Directory | /workspace/46.uart_loopback/latest |
| Test location | /workspace/coverage/default/46.uart_noise_filter.2165362619 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 174088481044 ps |
| CPU time | 71.67 seconds |
| Started | Jun 04 12:40:46 PM PDT 24 |
| Finished | Jun 04 12:41:59 PM PDT 24 |
| Peak memory | 208144 kb |
| Host | smart-cac2be82-d0a3-4917-af74-dada3bac638d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2165362619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_noise_filter.2165362619 |
| Directory | /workspace/46.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/46.uart_perf.2165183341 |
| Short name | T1141 |
| Test name | |
| Test status | |
| Simulation time | 11575956683 ps |
| CPU time | 139.44 seconds |
| Started | Jun 04 12:40:48 PM PDT 24 |
| Finished | Jun 04 12:43:09 PM PDT 24 |
| Peak memory | 200140 kb |
| Host | smart-6780e003-c469-45c4-90e4-c3e2ac392412 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2165183341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.2165183341 |
| Directory | /workspace/46.uart_perf/latest |
| Test location | /workspace/coverage/default/46.uart_rx_oversample.4048795250 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 3994668836 ps |
| CPU time | 11.6 seconds |
| Started | Jun 04 12:40:45 PM PDT 24 |
| Finished | Jun 04 12:40:58 PM PDT 24 |
| Peak memory | 199488 kb |
| Host | smart-f197b14e-ebd0-4908-a5ce-fcda6a19a4f0 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4048795250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.4048795250 |
| Directory | /workspace/46.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/46.uart_rx_parity_err.635549713 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 135616982090 ps |
| CPU time | 234.34 seconds |
| Started | Jun 04 12:40:48 PM PDT 24 |
| Finished | Jun 04 12:44:44 PM PDT 24 |
| Peak memory | 200108 kb |
| Host | smart-561ced6d-7724-4299-b1c0-f8c273b7e694 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=635549713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.635549713 |
| Directory | /workspace/46.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/46.uart_rx_start_bit_filter.3413384463 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 1472322593 ps |
| CPU time | 1.68 seconds |
| Started | Jun 04 12:40:48 PM PDT 24 |
| Finished | Jun 04 12:40:50 PM PDT 24 |
| Peak memory | 195560 kb |
| Host | smart-808dcb7e-1d87-41c7-b758-802ae4cf8662 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3413384463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.3413384463 |
| Directory | /workspace/46.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/46.uart_smoke.1197285557 |
| Short name | T1067 |
| Test name | |
| Test status | |
| Simulation time | 302377369 ps |
| CPU time | 0.99 seconds |
| Started | Jun 04 12:40:43 PM PDT 24 |
| Finished | Jun 04 12:40:44 PM PDT 24 |
| Peak memory | 199864 kb |
| Host | smart-0f940176-e0e7-42a3-8517-3247aee1c619 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1197285557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_smoke.1197285557 |
| Directory | /workspace/46.uart_smoke/latest |
| Test location | /workspace/coverage/default/46.uart_stress_all.3544850263 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 479736830080 ps |
| CPU time | 109.43 seconds |
| Started | Jun 04 12:40:47 PM PDT 24 |
| Finished | Jun 04 12:42:37 PM PDT 24 |
| Peak memory | 216808 kb |
| Host | smart-5e4b944d-b2ee-45a6-a342-13733a964961 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544850263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.3544850263 |
| Directory | /workspace/46.uart_stress_all/latest |
| Test location | /workspace/coverage/default/46.uart_stress_all_with_rand_reset.1413808441 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 79382288008 ps |
| CPU time | 235.54 seconds |
| Started | Jun 04 12:40:48 PM PDT 24 |
| Finished | Jun 04 12:44:45 PM PDT 24 |
| Peak memory | 216900 kb |
| Host | smart-78ec5dfe-f062-4c11-9da1-c59bb9c1cbae |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413808441 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 46.uart_stress_all_with_rand_reset.1413808441 |
| Directory | /workspace/46.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/46.uart_tx_ovrd.2744067725 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 1814216354 ps |
| CPU time | 1.81 seconds |
| Started | Jun 04 12:40:48 PM PDT 24 |
| Finished | Jun 04 12:40:51 PM PDT 24 |
| Peak memory | 198820 kb |
| Host | smart-023dd2e6-aefc-47a6-acb5-c8fe01015e25 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2744067725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.2744067725 |
| Directory | /workspace/46.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/46.uart_tx_rx.3443732065 |
| Short name | T1088 |
| Test name | |
| Test status | |
| Simulation time | 13757646897 ps |
| CPU time | 39.06 seconds |
| Started | Jun 04 12:40:44 PM PDT 24 |
| Finished | Jun 04 12:41:24 PM PDT 24 |
| Peak memory | 200276 kb |
| Host | smart-a70d471a-92ff-4ab1-94d3-ab831cca43f6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3443732065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.3443732065 |
| Directory | /workspace/46.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/47.uart_alert_test.2342582020 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 42689523 ps |
| CPU time | 0.55 seconds |
| Started | Jun 04 12:40:51 PM PDT 24 |
| Finished | Jun 04 12:40:52 PM PDT 24 |
| Peak memory | 195624 kb |
| Host | smart-2ce6fb3a-889d-423c-8fd1-326a23c046f9 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342582020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.2342582020 |
| Directory | /workspace/47.uart_alert_test/latest |
| Test location | /workspace/coverage/default/47.uart_fifo_full.2366041913 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 54603690289 ps |
| CPU time | 10.22 seconds |
| Started | Jun 04 12:40:47 PM PDT 24 |
| Finished | Jun 04 12:40:58 PM PDT 24 |
| Peak memory | 200164 kb |
| Host | smart-c9678cde-29b4-4a9f-986e-0e8c6add0347 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2366041913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.2366041913 |
| Directory | /workspace/47.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/47.uart_fifo_overflow.3042923510 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 12852911994 ps |
| CPU time | 21.36 seconds |
| Started | Jun 04 12:40:46 PM PDT 24 |
| Finished | Jun 04 12:41:08 PM PDT 24 |
| Peak memory | 200124 kb |
| Host | smart-4a9cd734-a506-4ff2-b9d0-83914b144afb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3042923510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.3042923510 |
| Directory | /workspace/47.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/47.uart_fifo_reset.3966541084 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 27813794726 ps |
| CPU time | 26.41 seconds |
| Started | Jun 04 12:40:46 PM PDT 24 |
| Finished | Jun 04 12:41:13 PM PDT 24 |
| Peak memory | 200220 kb |
| Host | smart-ee38e07e-1c0b-415e-998f-97deae527dc8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3966541084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.3966541084 |
| Directory | /workspace/47.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/47.uart_intr.4002014165 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 394269508414 ps |
| CPU time | 1222.91 seconds |
| Started | Jun 04 12:40:48 PM PDT 24 |
| Finished | Jun 04 01:01:12 PM PDT 24 |
| Peak memory | 200248 kb |
| Host | smart-498eb4c8-b2a3-4314-b420-ec6fd2046f32 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002014165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.4002014165 |
| Directory | /workspace/47.uart_intr/latest |
| Test location | /workspace/coverage/default/47.uart_long_xfer_wo_dly.2674466768 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 77579300638 ps |
| CPU time | 331.8 seconds |
| Started | Jun 04 12:40:45 PM PDT 24 |
| Finished | Jun 04 12:46:18 PM PDT 24 |
| Peak memory | 200108 kb |
| Host | smart-464d16c9-2ccf-40bc-8aa9-400d6f007466 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2674466768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.2674466768 |
| Directory | /workspace/47.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/47.uart_loopback.1121400293 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 5260231758 ps |
| CPU time | 7.4 seconds |
| Started | Jun 04 12:40:45 PM PDT 24 |
| Finished | Jun 04 12:40:53 PM PDT 24 |
| Peak memory | 198880 kb |
| Host | smart-b016c6a5-c986-483e-bb1c-0b0b503ce210 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1121400293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_loopback.1121400293 |
| Directory | /workspace/47.uart_loopback/latest |
| Test location | /workspace/coverage/default/47.uart_noise_filter.284907851 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 87103960189 ps |
| CPU time | 78.75 seconds |
| Started | Jun 04 12:40:47 PM PDT 24 |
| Finished | Jun 04 12:42:06 PM PDT 24 |
| Peak memory | 200504 kb |
| Host | smart-605cc521-4842-414b-a75c-9e571f0b01b3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=284907851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_noise_filter.284907851 |
| Directory | /workspace/47.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/47.uart_perf.1433038325 |
| Short name | T1076 |
| Test name | |
| Test status | |
| Simulation time | 8858623411 ps |
| CPU time | 361.93 seconds |
| Started | Jun 04 12:40:44 PM PDT 24 |
| Finished | Jun 04 12:46:47 PM PDT 24 |
| Peak memory | 200120 kb |
| Host | smart-a7dad7f6-ffc8-4510-b45b-374980fe1f87 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1433038325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.1433038325 |
| Directory | /workspace/47.uart_perf/latest |
| Test location | /workspace/coverage/default/47.uart_rx_oversample.3628278505 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 1584718041 ps |
| CPU time | 6.34 seconds |
| Started | Jun 04 12:40:46 PM PDT 24 |
| Finished | Jun 04 12:40:53 PM PDT 24 |
| Peak memory | 198308 kb |
| Host | smart-a9c4dedf-b7b9-4f73-8ebf-526c7cd53d08 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3628278505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.3628278505 |
| Directory | /workspace/47.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/47.uart_rx_parity_err.847871742 |
| Short name | T1060 |
| Test name | |
| Test status | |
| Simulation time | 68347687446 ps |
| CPU time | 57.12 seconds |
| Started | Jun 04 12:40:47 PM PDT 24 |
| Finished | Jun 04 12:41:45 PM PDT 24 |
| Peak memory | 199800 kb |
| Host | smart-c24054e7-6a14-4c9b-90db-aa153f848c6e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=847871742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.847871742 |
| Directory | /workspace/47.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/47.uart_rx_start_bit_filter.2056487502 |
| Short name | T1035 |
| Test name | |
| Test status | |
| Simulation time | 6149860828 ps |
| CPU time | 5.26 seconds |
| Started | Jun 04 12:40:47 PM PDT 24 |
| Finished | Jun 04 12:40:53 PM PDT 24 |
| Peak memory | 195928 kb |
| Host | smart-afe105fc-76c1-4145-8c00-dc18185d9ca0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2056487502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.2056487502 |
| Directory | /workspace/47.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/47.uart_smoke.808836144 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 894890054 ps |
| CPU time | 2.24 seconds |
| Started | Jun 04 12:40:46 PM PDT 24 |
| Finished | Jun 04 12:40:49 PM PDT 24 |
| Peak memory | 198444 kb |
| Host | smart-a7e8cc0a-7e36-4eaf-8c86-8cdcc269b79c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=808836144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_smoke.808836144 |
| Directory | /workspace/47.uart_smoke/latest |
| Test location | /workspace/coverage/default/47.uart_stress_all.2264904996 |
| Short name | T972 |
| Test name | |
| Test status | |
| Simulation time | 913197718286 ps |
| CPU time | 358.17 seconds |
| Started | Jun 04 12:40:46 PM PDT 24 |
| Finished | Jun 04 12:46:45 PM PDT 24 |
| Peak memory | 200160 kb |
| Host | smart-5565e8e8-6d8b-459e-9b8a-1625f94957fd |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264904996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.2264904996 |
| Directory | /workspace/47.uart_stress_all/latest |
| Test location | /workspace/coverage/default/47.uart_tx_ovrd.2038450637 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 3474211580 ps |
| CPU time | 2.04 seconds |
| Started | Jun 04 12:40:47 PM PDT 24 |
| Finished | Jun 04 12:40:50 PM PDT 24 |
| Peak memory | 199428 kb |
| Host | smart-4200dcac-5ef9-49f8-a2c4-cec1c6cb5d4d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2038450637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.2038450637 |
| Directory | /workspace/47.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/47.uart_tx_rx.4048932922 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 8942942220 ps |
| CPU time | 7.36 seconds |
| Started | Jun 04 12:40:46 PM PDT 24 |
| Finished | Jun 04 12:40:54 PM PDT 24 |
| Peak memory | 200196 kb |
| Host | smart-e32937d6-366f-4a51-a628-8317a02656d1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4048932922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.4048932922 |
| Directory | /workspace/47.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/48.uart_alert_test.599214870 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 45911861 ps |
| CPU time | 0.56 seconds |
| Started | Jun 04 12:40:57 PM PDT 24 |
| Finished | Jun 04 12:40:59 PM PDT 24 |
| Peak memory | 195728 kb |
| Host | smart-63a4f3ab-5e8d-4adb-bf0b-d676aa6d4e74 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599214870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.599214870 |
| Directory | /workspace/48.uart_alert_test/latest |
| Test location | /workspace/coverage/default/48.uart_fifo_full.1020050187 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 87845637324 ps |
| CPU time | 253.33 seconds |
| Started | Jun 04 12:40:47 PM PDT 24 |
| Finished | Jun 04 12:45:02 PM PDT 24 |
| Peak memory | 199944 kb |
| Host | smart-ef975def-5a57-49eb-8bb7-0edc1eedbebd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1020050187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.1020050187 |
| Directory | /workspace/48.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/48.uart_fifo_overflow.1076012670 |
| Short name | T1004 |
| Test name | |
| Test status | |
| Simulation time | 100257940152 ps |
| CPU time | 108.46 seconds |
| Started | Jun 04 12:40:51 PM PDT 24 |
| Finished | Jun 04 12:42:40 PM PDT 24 |
| Peak memory | 199672 kb |
| Host | smart-4b5fba32-9109-48db-9d94-c0127dbbe438 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1076012670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.1076012670 |
| Directory | /workspace/48.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/48.uart_fifo_reset.2374154342 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 83673583083 ps |
| CPU time | 41 seconds |
| Started | Jun 04 12:40:45 PM PDT 24 |
| Finished | Jun 04 12:41:27 PM PDT 24 |
| Peak memory | 200232 kb |
| Host | smart-f7a9e7c0-f41d-401b-aeed-8bf8a5088ed8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2374154342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.2374154342 |
| Directory | /workspace/48.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/48.uart_intr.3943228748 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 31571376764 ps |
| CPU time | 50.9 seconds |
| Started | Jun 04 12:40:51 PM PDT 24 |
| Finished | Jun 04 12:41:43 PM PDT 24 |
| Peak memory | 199224 kb |
| Host | smart-5310f409-9269-4ce9-bdd0-22e73db313fc |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943228748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.3943228748 |
| Directory | /workspace/48.uart_intr/latest |
| Test location | /workspace/coverage/default/48.uart_long_xfer_wo_dly.3185830367 |
| Short name | T1128 |
| Test name | |
| Test status | |
| Simulation time | 70891893593 ps |
| CPU time | 301.67 seconds |
| Started | Jun 04 12:40:56 PM PDT 24 |
| Finished | Jun 04 12:45:59 PM PDT 24 |
| Peak memory | 200252 kb |
| Host | smart-20bcebab-af06-47be-b9d1-eedf4d371e2c |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3185830367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.3185830367 |
| Directory | /workspace/48.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/48.uart_loopback.801996078 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 6766353857 ps |
| CPU time | 4.5 seconds |
| Started | Jun 04 12:40:57 PM PDT 24 |
| Finished | Jun 04 12:41:03 PM PDT 24 |
| Peak memory | 199716 kb |
| Host | smart-821bec80-2368-42b8-bc1a-82893dece194 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=801996078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_loopback.801996078 |
| Directory | /workspace/48.uart_loopback/latest |
| Test location | /workspace/coverage/default/48.uart_noise_filter.494157201 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 315159229749 ps |
| CPU time | 58.26 seconds |
| Started | Jun 04 12:40:46 PM PDT 24 |
| Finished | Jun 04 12:41:45 PM PDT 24 |
| Peak memory | 200464 kb |
| Host | smart-2a2690f8-55df-4d5d-8fab-697dfc2ddeee |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=494157201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_noise_filter.494157201 |
| Directory | /workspace/48.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/48.uart_perf.3863391649 |
| Short name | T1143 |
| Test name | |
| Test status | |
| Simulation time | 7467052152 ps |
| CPU time | 378.1 seconds |
| Started | Jun 04 12:40:56 PM PDT 24 |
| Finished | Jun 04 12:47:15 PM PDT 24 |
| Peak memory | 200180 kb |
| Host | smart-0000e895-6dfa-40fc-83eb-b88eab054573 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3863391649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.3863391649 |
| Directory | /workspace/48.uart_perf/latest |
| Test location | /workspace/coverage/default/48.uart_rx_oversample.2844564678 |
| Short name | T1101 |
| Test name | |
| Test status | |
| Simulation time | 3568195362 ps |
| CPU time | 7.63 seconds |
| Started | Jun 04 12:40:47 PM PDT 24 |
| Finished | Jun 04 12:40:56 PM PDT 24 |
| Peak memory | 198220 kb |
| Host | smart-758145f9-d55c-49e0-be65-9d7a768f950f |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2844564678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.2844564678 |
| Directory | /workspace/48.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/48.uart_rx_parity_err.2637306472 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 19997743706 ps |
| CPU time | 17.56 seconds |
| Started | Jun 04 12:40:49 PM PDT 24 |
| Finished | Jun 04 12:41:08 PM PDT 24 |
| Peak memory | 199952 kb |
| Host | smart-9a540247-45da-4384-b0c6-0b9fa8b82999 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2637306472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.2637306472 |
| Directory | /workspace/48.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/48.uart_rx_start_bit_filter.3327177034 |
| Short name | T959 |
| Test name | |
| Test status | |
| Simulation time | 3075129034 ps |
| CPU time | 1.07 seconds |
| Started | Jun 04 12:40:46 PM PDT 24 |
| Finished | Jun 04 12:40:48 PM PDT 24 |
| Peak memory | 196144 kb |
| Host | smart-ec280ef5-158a-4c46-a57d-71adb11b16f7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3327177034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.3327177034 |
| Directory | /workspace/48.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/48.uart_smoke.3557122719 |
| Short name | T920 |
| Test name | |
| Test status | |
| Simulation time | 5808593439 ps |
| CPU time | 3.63 seconds |
| Started | Jun 04 12:40:48 PM PDT 24 |
| Finished | Jun 04 12:40:53 PM PDT 24 |
| Peak memory | 199388 kb |
| Host | smart-284532c2-e43d-4d22-aaac-98af1262fa15 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3557122719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_smoke.3557122719 |
| Directory | /workspace/48.uart_smoke/latest |
| Test location | /workspace/coverage/default/48.uart_stress_all.2205155410 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 307865866583 ps |
| CPU time | 343.07 seconds |
| Started | Jun 04 12:40:58 PM PDT 24 |
| Finished | Jun 04 12:46:42 PM PDT 24 |
| Peak memory | 200364 kb |
| Host | smart-09307490-3391-4399-a5dd-d275e915e493 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205155410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.2205155410 |
| Directory | /workspace/48.uart_stress_all/latest |
| Test location | /workspace/coverage/default/48.uart_stress_all_with_rand_reset.3742547412 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 138346900550 ps |
| CPU time | 672.33 seconds |
| Started | Jun 04 12:40:57 PM PDT 24 |
| Finished | Jun 04 12:52:11 PM PDT 24 |
| Peak memory | 211704 kb |
| Host | smart-e96b3d3e-f713-44a5-ac35-1b8938ef0e7d |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742547412 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 48.uart_stress_all_with_rand_reset.3742547412 |
| Directory | /workspace/48.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/48.uart_tx_ovrd.3715820616 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 1263315436 ps |
| CPU time | 2.06 seconds |
| Started | Jun 04 12:40:58 PM PDT 24 |
| Finished | Jun 04 12:41:01 PM PDT 24 |
| Peak memory | 200204 kb |
| Host | smart-0bad186f-4f39-4570-9d7d-f6f29b3203bc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3715820616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.3715820616 |
| Directory | /workspace/48.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/48.uart_tx_rx.2912304616 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 16069492157 ps |
| CPU time | 12.37 seconds |
| Started | Jun 04 12:40:48 PM PDT 24 |
| Finished | Jun 04 12:41:01 PM PDT 24 |
| Peak memory | 197976 kb |
| Host | smart-ca53bded-6fcb-4c11-9e7f-cde354d83016 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2912304616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.2912304616 |
| Directory | /workspace/48.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/49.uart_alert_test.2044980880 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 12207772 ps |
| CPU time | 0.56 seconds |
| Started | Jun 04 12:40:56 PM PDT 24 |
| Finished | Jun 04 12:40:58 PM PDT 24 |
| Peak memory | 195048 kb |
| Host | smart-77b48d60-8d6d-4d19-b529-b92ac5c804fa |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044980880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.2044980880 |
| Directory | /workspace/49.uart_alert_test/latest |
| Test location | /workspace/coverage/default/49.uart_fifo_full.796441855 |
| Short name | T918 |
| Test name | |
| Test status | |
| Simulation time | 66101327027 ps |
| CPU time | 30.17 seconds |
| Started | Jun 04 12:40:58 PM PDT 24 |
| Finished | Jun 04 12:41:29 PM PDT 24 |
| Peak memory | 200108 kb |
| Host | smart-0a40c7d0-e472-4883-8797-e8d58d2e4e25 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=796441855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.796441855 |
| Directory | /workspace/49.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/49.uart_fifo_overflow.2139389246 |
| Short name | T1033 |
| Test name | |
| Test status | |
| Simulation time | 34549016511 ps |
| CPU time | 32.25 seconds |
| Started | Jun 04 12:40:56 PM PDT 24 |
| Finished | Jun 04 12:41:29 PM PDT 24 |
| Peak memory | 200320 kb |
| Host | smart-898d08c3-4b70-449f-9af6-04ff2c3b49bc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2139389246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.2139389246 |
| Directory | /workspace/49.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/49.uart_fifo_reset.2906649711 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 47044962945 ps |
| CPU time | 18.54 seconds |
| Started | Jun 04 12:40:56 PM PDT 24 |
| Finished | Jun 04 12:41:15 PM PDT 24 |
| Peak memory | 200148 kb |
| Host | smart-eb27210e-d6e2-4bc5-bbdf-9434b8894b83 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2906649711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.2906649711 |
| Directory | /workspace/49.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/49.uart_intr.1991659312 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 38937556469 ps |
| CPU time | 9.03 seconds |
| Started | Jun 04 12:40:57 PM PDT 24 |
| Finished | Jun 04 12:41:07 PM PDT 24 |
| Peak memory | 200268 kb |
| Host | smart-85ff02b2-e621-4fae-a3ab-a500562025cf |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991659312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.1991659312 |
| Directory | /workspace/49.uart_intr/latest |
| Test location | /workspace/coverage/default/49.uart_long_xfer_wo_dly.2608507349 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 110879669846 ps |
| CPU time | 980.68 seconds |
| Started | Jun 04 12:40:57 PM PDT 24 |
| Finished | Jun 04 12:57:19 PM PDT 24 |
| Peak memory | 200204 kb |
| Host | smart-36828a7e-5af9-4a3d-bab3-05cac56c2286 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2608507349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.2608507349 |
| Directory | /workspace/49.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/49.uart_loopback.660937352 |
| Short name | T1140 |
| Test name | |
| Test status | |
| Simulation time | 5126327224 ps |
| CPU time | 3.84 seconds |
| Started | Jun 04 12:40:56 PM PDT 24 |
| Finished | Jun 04 12:41:01 PM PDT 24 |
| Peak memory | 199472 kb |
| Host | smart-7ee6ded2-5fb9-4c21-ab28-cd5adb76fe8f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=660937352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_loopback.660937352 |
| Directory | /workspace/49.uart_loopback/latest |
| Test location | /workspace/coverage/default/49.uart_noise_filter.3680255839 |
| Short name | T1023 |
| Test name | |
| Test status | |
| Simulation time | 193114417145 ps |
| CPU time | 94.19 seconds |
| Started | Jun 04 12:40:56 PM PDT 24 |
| Finished | Jun 04 12:42:32 PM PDT 24 |
| Peak memory | 216280 kb |
| Host | smart-2b0b30c1-8c69-4a0e-8eb6-874bd67849a6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3680255839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_noise_filter.3680255839 |
| Directory | /workspace/49.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/49.uart_perf.1632199387 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 12070482933 ps |
| CPU time | 704.14 seconds |
| Started | Jun 04 12:40:56 PM PDT 24 |
| Finished | Jun 04 12:52:41 PM PDT 24 |
| Peak memory | 200224 kb |
| Host | smart-7079fbfa-2cbe-444a-b65f-cc2f2b7fd9aa |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1632199387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.1632199387 |
| Directory | /workspace/49.uart_perf/latest |
| Test location | /workspace/coverage/default/49.uart_rx_oversample.3398614148 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 6599638684 ps |
| CPU time | 16.48 seconds |
| Started | Jun 04 12:40:56 PM PDT 24 |
| Finished | Jun 04 12:41:14 PM PDT 24 |
| Peak memory | 199408 kb |
| Host | smart-70530fb6-502d-4eb2-bcec-2865331aeedf |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3398614148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.3398614148 |
| Directory | /workspace/49.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/49.uart_rx_parity_err.3088298880 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 32578031670 ps |
| CPU time | 57.01 seconds |
| Started | Jun 04 12:40:57 PM PDT 24 |
| Finished | Jun 04 12:41:55 PM PDT 24 |
| Peak memory | 200116 kb |
| Host | smart-a87d28db-8130-4fdd-98ff-3e16fb162ad5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3088298880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.3088298880 |
| Directory | /workspace/49.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/49.uart_rx_start_bit_filter.3952493091 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 5050844994 ps |
| CPU time | 2.69 seconds |
| Started | Jun 04 12:40:58 PM PDT 24 |
| Finished | Jun 04 12:41:01 PM PDT 24 |
| Peak memory | 196480 kb |
| Host | smart-c54ad8c0-9f6c-4cd0-9070-1d0178e8a0bc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3952493091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.3952493091 |
| Directory | /workspace/49.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/49.uart_smoke.123897239 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 111216226 ps |
| CPU time | 1.16 seconds |
| Started | Jun 04 12:40:59 PM PDT 24 |
| Finished | Jun 04 12:41:01 PM PDT 24 |
| Peak memory | 199748 kb |
| Host | smart-ac4b4993-2266-4492-b0f0-841c81a93d1f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=123897239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_smoke.123897239 |
| Directory | /workspace/49.uart_smoke/latest |
| Test location | /workspace/coverage/default/49.uart_stress_all.2747700363 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 417180630117 ps |
| CPU time | 1936.71 seconds |
| Started | Jun 04 12:40:57 PM PDT 24 |
| Finished | Jun 04 01:13:15 PM PDT 24 |
| Peak memory | 200240 kb |
| Host | smart-1bca593a-2893-4074-bbfd-20ac94e99a86 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747700363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.2747700363 |
| Directory | /workspace/49.uart_stress_all/latest |
| Test location | /workspace/coverage/default/49.uart_stress_all_with_rand_reset.2180064910 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 191863697112 ps |
| CPU time | 1075.57 seconds |
| Started | Jun 04 12:40:58 PM PDT 24 |
| Finished | Jun 04 12:58:55 PM PDT 24 |
| Peak memory | 226104 kb |
| Host | smart-5f060996-d1bb-4494-8fc8-88f1a13bcebd |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180064910 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 49.uart_stress_all_with_rand_reset.2180064910 |
| Directory | /workspace/49.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/49.uart_tx_ovrd.4047398916 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 354724770 ps |
| CPU time | 1.46 seconds |
| Started | Jun 04 12:40:56 PM PDT 24 |
| Finished | Jun 04 12:40:58 PM PDT 24 |
| Peak memory | 197344 kb |
| Host | smart-11cbdac4-f1f2-43ff-985d-3aa30860ed4b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4047398916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.4047398916 |
| Directory | /workspace/49.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/49.uart_tx_rx.418063136 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 21723034120 ps |
| CPU time | 15.76 seconds |
| Started | Jun 04 12:40:57 PM PDT 24 |
| Finished | Jun 04 12:41:14 PM PDT 24 |
| Peak memory | 197872 kb |
| Host | smart-b59b1e71-dea5-4d90-a9ce-6f3e36cea5fc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=418063136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.418063136 |
| Directory | /workspace/49.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/5.uart_alert_test.402055367 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 61843959 ps |
| CPU time | 0.53 seconds |
| Started | Jun 04 12:37:06 PM PDT 24 |
| Finished | Jun 04 12:37:07 PM PDT 24 |
| Peak memory | 195708 kb |
| Host | smart-dff551ab-3b42-4650-a283-0a51789f6e0c |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402055367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.402055367 |
| Directory | /workspace/5.uart_alert_test/latest |
| Test location | /workspace/coverage/default/5.uart_fifo_full.3136141865 |
| Short name | T1065 |
| Test name | |
| Test status | |
| Simulation time | 16748546577 ps |
| CPU time | 18.14 seconds |
| Started | Jun 04 12:37:10 PM PDT 24 |
| Finished | Jun 04 12:37:29 PM PDT 24 |
| Peak memory | 200196 kb |
| Host | smart-742d1208-d87c-476e-b84b-d5f15c7dc3fc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3136141865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.3136141865 |
| Directory | /workspace/5.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/5.uart_fifo_overflow.2124495401 |
| Short name | T929 |
| Test name | |
| Test status | |
| Simulation time | 80394498129 ps |
| CPU time | 111.16 seconds |
| Started | Jun 04 12:36:59 PM PDT 24 |
| Finished | Jun 04 12:38:52 PM PDT 24 |
| Peak memory | 200200 kb |
| Host | smart-743b20f8-9023-4d16-9d4c-e93b40adf16b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2124495401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.2124495401 |
| Directory | /workspace/5.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/5.uart_fifo_reset.876598073 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 54997724087 ps |
| CPU time | 47.29 seconds |
| Started | Jun 04 12:37:04 PM PDT 24 |
| Finished | Jun 04 12:37:52 PM PDT 24 |
| Peak memory | 200248 kb |
| Host | smart-6f608ab5-03fb-4a62-8f0a-d2f2375306e4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=876598073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.876598073 |
| Directory | /workspace/5.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/5.uart_intr.1017418428 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 15648661341 ps |
| CPU time | 24.71 seconds |
| Started | Jun 04 12:37:07 PM PDT 24 |
| Finished | Jun 04 12:37:33 PM PDT 24 |
| Peak memory | 199724 kb |
| Host | smart-3bcbec64-527b-4d21-a30f-e6652bf37ba2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017418428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.1017418428 |
| Directory | /workspace/5.uart_intr/latest |
| Test location | /workspace/coverage/default/5.uart_long_xfer_wo_dly.2383967106 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 140150663685 ps |
| CPU time | 1158.86 seconds |
| Started | Jun 04 12:37:07 PM PDT 24 |
| Finished | Jun 04 12:56:27 PM PDT 24 |
| Peak memory | 200208 kb |
| Host | smart-3f2b0483-48b4-4f3b-b9fb-288705794138 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2383967106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.2383967106 |
| Directory | /workspace/5.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/5.uart_loopback.4014660483 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 122585323 ps |
| CPU time | 1.45 seconds |
| Started | Jun 04 12:37:09 PM PDT 24 |
| Finished | Jun 04 12:37:11 PM PDT 24 |
| Peak memory | 198876 kb |
| Host | smart-3b54dd5a-3a85-4cb5-874a-018ee80c3f96 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4014660483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_loopback.4014660483 |
| Directory | /workspace/5.uart_loopback/latest |
| Test location | /workspace/coverage/default/5.uart_noise_filter.295549321 |
| Short name | T1139 |
| Test name | |
| Test status | |
| Simulation time | 73172750063 ps |
| CPU time | 28.76 seconds |
| Started | Jun 04 12:37:09 PM PDT 24 |
| Finished | Jun 04 12:37:39 PM PDT 24 |
| Peak memory | 200176 kb |
| Host | smart-afa47e95-9222-4047-94a9-00239b75c923 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=295549321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_noise_filter.295549321 |
| Directory | /workspace/5.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/5.uart_perf.827339201 |
| Short name | T994 |
| Test name | |
| Test status | |
| Simulation time | 17286333830 ps |
| CPU time | 110.72 seconds |
| Started | Jun 04 12:37:09 PM PDT 24 |
| Finished | Jun 04 12:39:01 PM PDT 24 |
| Peak memory | 200240 kb |
| Host | smart-20a92d4b-9607-4cc8-91a1-6443920e2faa |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=827339201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.827339201 |
| Directory | /workspace/5.uart_perf/latest |
| Test location | /workspace/coverage/default/5.uart_rx_oversample.2470600182 |
| Short name | T941 |
| Test name | |
| Test status | |
| Simulation time | 2462607282 ps |
| CPU time | 4 seconds |
| Started | Jun 04 12:37:09 PM PDT 24 |
| Finished | Jun 04 12:37:14 PM PDT 24 |
| Peak memory | 198596 kb |
| Host | smart-7e05f44e-d96b-4642-b946-2a96c0087254 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2470600182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.2470600182 |
| Directory | /workspace/5.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/5.uart_rx_parity_err.714073925 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 38205848841 ps |
| CPU time | 16.88 seconds |
| Started | Jun 04 12:37:07 PM PDT 24 |
| Finished | Jun 04 12:37:24 PM PDT 24 |
| Peak memory | 199692 kb |
| Host | smart-4c1355fd-00a0-4ad5-a6cc-6f4c09af489f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=714073925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.714073925 |
| Directory | /workspace/5.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/5.uart_rx_start_bit_filter.2802394310 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 43939032871 ps |
| CPU time | 72.17 seconds |
| Started | Jun 04 12:37:09 PM PDT 24 |
| Finished | Jun 04 12:38:23 PM PDT 24 |
| Peak memory | 195912 kb |
| Host | smart-7cf7371e-83b5-4539-8096-018544a68633 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2802394310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.2802394310 |
| Directory | /workspace/5.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/5.uart_smoke.2364086238 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 5948489240 ps |
| CPU time | 12.77 seconds |
| Started | Jun 04 12:37:00 PM PDT 24 |
| Finished | Jun 04 12:37:14 PM PDT 24 |
| Peak memory | 200160 kb |
| Host | smart-156ba3d8-d5c2-4e85-a27f-cb9169506953 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2364086238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_smoke.2364086238 |
| Directory | /workspace/5.uart_smoke/latest |
| Test location | /workspace/coverage/default/5.uart_stress_all_with_rand_reset.3136557268 |
| Short name | T949 |
| Test name | |
| Test status | |
| Simulation time | 25417946740 ps |
| CPU time | 656.93 seconds |
| Started | Jun 04 12:37:08 PM PDT 24 |
| Finished | Jun 04 12:48:06 PM PDT 24 |
| Peak memory | 212228 kb |
| Host | smart-78924b83-81c6-4213-96f3-00378cbe7cd7 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136557268 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 5.uart_stress_all_with_rand_reset.3136557268 |
| Directory | /workspace/5.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/5.uart_tx_ovrd.2848608560 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 1345193844 ps |
| CPU time | 1.66 seconds |
| Started | Jun 04 12:37:08 PM PDT 24 |
| Finished | Jun 04 12:37:11 PM PDT 24 |
| Peak memory | 198948 kb |
| Host | smart-79f6ffeb-0051-4c58-9280-b96d9041f232 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2848608560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.2848608560 |
| Directory | /workspace/5.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/5.uart_tx_rx.1183113591 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 138513092409 ps |
| CPU time | 145.35 seconds |
| Started | Jun 04 12:36:58 PM PDT 24 |
| Finished | Jun 04 12:39:25 PM PDT 24 |
| Peak memory | 200168 kb |
| Host | smart-06a43e49-e3d7-49d0-94f5-93c6884dd72b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1183113591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.1183113591 |
| Directory | /workspace/5.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/50.uart_fifo_reset.1575567099 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 99448025367 ps |
| CPU time | 151.17 seconds |
| Started | Jun 04 12:40:56 PM PDT 24 |
| Finished | Jun 04 12:43:28 PM PDT 24 |
| Peak memory | 200260 kb |
| Host | smart-8db69511-6332-4bdf-bfa6-ef48aa79c9bb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1575567099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.1575567099 |
| Directory | /workspace/50.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/50.uart_stress_all_with_rand_reset.2738032795 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 53062249009 ps |
| CPU time | 327.29 seconds |
| Started | Jun 04 12:40:58 PM PDT 24 |
| Finished | Jun 04 12:46:26 PM PDT 24 |
| Peak memory | 216732 kb |
| Host | smart-e8e40269-ec94-48a5-97be-a6d8c9d3a4e6 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738032795 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 50.uart_stress_all_with_rand_reset.2738032795 |
| Directory | /workspace/50.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/51.uart_fifo_reset.1504094054 |
| Short name | T1116 |
| Test name | |
| Test status | |
| Simulation time | 133276794048 ps |
| CPU time | 23.54 seconds |
| Started | Jun 04 12:40:58 PM PDT 24 |
| Finished | Jun 04 12:41:23 PM PDT 24 |
| Peak memory | 200160 kb |
| Host | smart-bf1fa62b-aa4d-402a-9264-724cb55ffb5f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1504094054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.1504094054 |
| Directory | /workspace/51.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/51.uart_stress_all_with_rand_reset.234437950 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 73722942538 ps |
| CPU time | 1595.5 seconds |
| Started | Jun 04 12:40:56 PM PDT 24 |
| Finished | Jun 04 01:07:33 PM PDT 24 |
| Peak memory | 225136 kb |
| Host | smart-f9c6c683-1b2d-4294-ac36-ef88c6ae6090 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234437950 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 51.uart_stress_all_with_rand_reset.234437950 |
| Directory | /workspace/51.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/52.uart_fifo_reset.765182272 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 11322362510 ps |
| CPU time | 12.58 seconds |
| Started | Jun 04 12:40:57 PM PDT 24 |
| Finished | Jun 04 12:41:11 PM PDT 24 |
| Peak memory | 200360 kb |
| Host | smart-9ec5c348-ab10-43d9-bd4b-5fa990a3a7e1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=765182272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.765182272 |
| Directory | /workspace/52.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/52.uart_stress_all_with_rand_reset.3432024391 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 276581774676 ps |
| CPU time | 752.22 seconds |
| Started | Jun 04 12:40:57 PM PDT 24 |
| Finished | Jun 04 12:53:30 PM PDT 24 |
| Peak memory | 216668 kb |
| Host | smart-e2df2dae-7a91-4d0f-b002-e567e8e4c8b9 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432024391 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 52.uart_stress_all_with_rand_reset.3432024391 |
| Directory | /workspace/52.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/53.uart_fifo_reset.693013 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 40187046132 ps |
| CPU time | 66.85 seconds |
| Started | Jun 04 12:40:57 PM PDT 24 |
| Finished | Jun 04 12:42:05 PM PDT 24 |
| Peak memory | 199980 kb |
| Host | smart-5c450e9d-523c-4b83-94e6-1509fb9b0bf9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=693013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.693013 |
| Directory | /workspace/53.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/53.uart_stress_all_with_rand_reset.3464804726 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 76230425822 ps |
| CPU time | 1013.15 seconds |
| Started | Jun 04 12:40:55 PM PDT 24 |
| Finished | Jun 04 12:57:49 PM PDT 24 |
| Peak memory | 216684 kb |
| Host | smart-1639edf9-bc16-41da-afe1-7e1c62524b36 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464804726 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 53.uart_stress_all_with_rand_reset.3464804726 |
| Directory | /workspace/53.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/54.uart_stress_all_with_rand_reset.339275998 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 51921714568 ps |
| CPU time | 260.55 seconds |
| Started | Jun 04 12:40:57 PM PDT 24 |
| Finished | Jun 04 12:45:18 PM PDT 24 |
| Peak memory | 215856 kb |
| Host | smart-ced79697-b596-4fed-a093-a15316044b19 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339275998 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 54.uart_stress_all_with_rand_reset.339275998 |
| Directory | /workspace/54.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/55.uart_fifo_reset.617584676 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 11320968156 ps |
| CPU time | 19.91 seconds |
| Started | Jun 04 12:40:57 PM PDT 24 |
| Finished | Jun 04 12:41:18 PM PDT 24 |
| Peak memory | 199972 kb |
| Host | smart-171ade1c-8f48-487f-bfe4-7a7a0051b64a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=617584676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.617584676 |
| Directory | /workspace/55.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/55.uart_stress_all_with_rand_reset.268982560 |
| Short name | T1079 |
| Test name | |
| Test status | |
| Simulation time | 345188815533 ps |
| CPU time | 366.56 seconds |
| Started | Jun 04 12:41:07 PM PDT 24 |
| Finished | Jun 04 12:47:15 PM PDT 24 |
| Peak memory | 210304 kb |
| Host | smart-8d90f5e3-40bb-4e18-8d00-187620a2e337 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268982560 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 55.uart_stress_all_with_rand_reset.268982560 |
| Directory | /workspace/55.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/56.uart_fifo_reset.2843451313 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 23933509116 ps |
| CPU time | 11.24 seconds |
| Started | Jun 04 12:41:16 PM PDT 24 |
| Finished | Jun 04 12:41:28 PM PDT 24 |
| Peak memory | 200192 kb |
| Host | smart-93622b79-9b5c-4f3d-ab92-d8f5bb837cd1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2843451313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.2843451313 |
| Directory | /workspace/56.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/56.uart_stress_all_with_rand_reset.3523357376 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 87473377408 ps |
| CPU time | 445.95 seconds |
| Started | Jun 04 12:41:05 PM PDT 24 |
| Finished | Jun 04 12:48:32 PM PDT 24 |
| Peak memory | 216816 kb |
| Host | smart-daef7b1c-1d91-4df6-95f0-2b6355783b29 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523357376 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 56.uart_stress_all_with_rand_reset.3523357376 |
| Directory | /workspace/56.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/57.uart_fifo_reset.1416870148 |
| Short name | T1074 |
| Test name | |
| Test status | |
| Simulation time | 116857666885 ps |
| CPU time | 178.24 seconds |
| Started | Jun 04 12:41:08 PM PDT 24 |
| Finished | Jun 04 12:44:07 PM PDT 24 |
| Peak memory | 200320 kb |
| Host | smart-8e13c8de-5773-4366-a75b-fcf33ecc9cca |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1416870148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.1416870148 |
| Directory | /workspace/57.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/57.uart_stress_all_with_rand_reset.1758119381 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 29346127199 ps |
| CPU time | 359.17 seconds |
| Started | Jun 04 12:41:06 PM PDT 24 |
| Finished | Jun 04 12:47:06 PM PDT 24 |
| Peak memory | 216656 kb |
| Host | smart-d9b233d3-d462-4cc7-b0b7-fb178894dade |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758119381 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 57.uart_stress_all_with_rand_reset.1758119381 |
| Directory | /workspace/57.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/58.uart_fifo_reset.711672388 |
| Short name | T1154 |
| Test name | |
| Test status | |
| Simulation time | 22234754452 ps |
| CPU time | 37.29 seconds |
| Started | Jun 04 12:41:06 PM PDT 24 |
| Finished | Jun 04 12:41:44 PM PDT 24 |
| Peak memory | 200172 kb |
| Host | smart-db46c5a2-037e-4592-a4c8-e97621d4e4dd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=711672388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.711672388 |
| Directory | /workspace/58.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/58.uart_stress_all_with_rand_reset.3686750932 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 60474627713 ps |
| CPU time | 383.99 seconds |
| Started | Jun 04 12:41:05 PM PDT 24 |
| Finished | Jun 04 12:47:30 PM PDT 24 |
| Peak memory | 215888 kb |
| Host | smart-d18735fe-03ef-48a4-a027-273ea12e2f88 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686750932 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 58.uart_stress_all_with_rand_reset.3686750932 |
| Directory | /workspace/58.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/59.uart_fifo_reset.1961436456 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 172909278548 ps |
| CPU time | 182.85 seconds |
| Started | Jun 04 12:41:07 PM PDT 24 |
| Finished | Jun 04 12:44:11 PM PDT 24 |
| Peak memory | 200252 kb |
| Host | smart-a619a1f9-03a0-484b-860d-d5a0e26396f0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1961436456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.1961436456 |
| Directory | /workspace/59.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/59.uart_stress_all_with_rand_reset.3604563513 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 22880375283 ps |
| CPU time | 101.12 seconds |
| Started | Jun 04 12:41:07 PM PDT 24 |
| Finished | Jun 04 12:42:49 PM PDT 24 |
| Peak memory | 215900 kb |
| Host | smart-c4378acc-d6c1-4d65-8a4d-b1caa63ab273 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604563513 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 59.uart_stress_all_with_rand_reset.3604563513 |
| Directory | /workspace/59.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/6.uart_alert_test.1982325733 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 21737797 ps |
| CPU time | 0.56 seconds |
| Started | Jun 04 12:37:07 PM PDT 24 |
| Finished | Jun 04 12:37:08 PM PDT 24 |
| Peak memory | 195592 kb |
| Host | smart-532273de-98d7-4d54-9f7b-f2d97397fa8c |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982325733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.1982325733 |
| Directory | /workspace/6.uart_alert_test/latest |
| Test location | /workspace/coverage/default/6.uart_fifo_full.2493028941 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 39932664858 ps |
| CPU time | 64.03 seconds |
| Started | Jun 04 12:37:09 PM PDT 24 |
| Finished | Jun 04 12:38:14 PM PDT 24 |
| Peak memory | 200296 kb |
| Host | smart-664614a2-cb75-4867-b878-63f12b7aa2f1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2493028941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.2493028941 |
| Directory | /workspace/6.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/6.uart_fifo_overflow.1802472472 |
| Short name | T1167 |
| Test name | |
| Test status | |
| Simulation time | 34656288411 ps |
| CPU time | 52.2 seconds |
| Started | Jun 04 12:37:05 PM PDT 24 |
| Finished | Jun 04 12:37:58 PM PDT 24 |
| Peak memory | 200208 kb |
| Host | smart-9d978809-2ef9-405b-9b02-c0402ee8fd09 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1802472472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.1802472472 |
| Directory | /workspace/6.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/6.uart_fifo_reset.3438566467 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 98192462114 ps |
| CPU time | 30.59 seconds |
| Started | Jun 04 12:37:08 PM PDT 24 |
| Finished | Jun 04 12:37:40 PM PDT 24 |
| Peak memory | 200244 kb |
| Host | smart-c2d66688-2546-4969-a023-8464fc893a4e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3438566467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.3438566467 |
| Directory | /workspace/6.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/6.uart_intr.2477178072 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 55375028901 ps |
| CPU time | 27.94 seconds |
| Started | Jun 04 12:37:09 PM PDT 24 |
| Finished | Jun 04 12:37:38 PM PDT 24 |
| Peak memory | 200220 kb |
| Host | smart-69c95f0c-4816-42eb-be9f-455a1d0198b5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477178072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.2477178072 |
| Directory | /workspace/6.uart_intr/latest |
| Test location | /workspace/coverage/default/6.uart_long_xfer_wo_dly.1135123344 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 133536825091 ps |
| CPU time | 121.75 seconds |
| Started | Jun 04 12:37:08 PM PDT 24 |
| Finished | Jun 04 12:39:11 PM PDT 24 |
| Peak memory | 200184 kb |
| Host | smart-e3e8f651-ac85-49c4-85c9-3b6aa7fc5af7 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1135123344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.1135123344 |
| Directory | /workspace/6.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/6.uart_loopback.1237685753 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 1338402913 ps |
| CPU time | 1.68 seconds |
| Started | Jun 04 12:37:10 PM PDT 24 |
| Finished | Jun 04 12:37:12 PM PDT 24 |
| Peak memory | 197140 kb |
| Host | smart-992a45a3-f3c2-4205-98f5-505e45b49ad1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1237685753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_loopback.1237685753 |
| Directory | /workspace/6.uart_loopback/latest |
| Test location | /workspace/coverage/default/6.uart_noise_filter.3208005976 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 90651326042 ps |
| CPU time | 146.52 seconds |
| Started | Jun 04 12:37:11 PM PDT 24 |
| Finished | Jun 04 12:39:38 PM PDT 24 |
| Peak memory | 200308 kb |
| Host | smart-24f4d550-43e8-4c48-b9a0-7584b51aaf03 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3208005976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_noise_filter.3208005976 |
| Directory | /workspace/6.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/6.uart_perf.1277333372 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 18841794616 ps |
| CPU time | 60.42 seconds |
| Started | Jun 04 12:37:06 PM PDT 24 |
| Finished | Jun 04 12:38:07 PM PDT 24 |
| Peak memory | 200336 kb |
| Host | smart-99c1ffe9-2bf9-4044-ab53-9f002dbc1128 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1277333372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.1277333372 |
| Directory | /workspace/6.uart_perf/latest |
| Test location | /workspace/coverage/default/6.uart_rx_oversample.82529107 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 6335211742 ps |
| CPU time | 26.73 seconds |
| Started | Jun 04 12:37:07 PM PDT 24 |
| Finished | Jun 04 12:37:35 PM PDT 24 |
| Peak memory | 198372 kb |
| Host | smart-8f082417-e4a8-4e9a-aa29-5efdb5be580e |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=82529107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.82529107 |
| Directory | /workspace/6.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/6.uart_rx_parity_err.1637329613 |
| Short name | T1094 |
| Test name | |
| Test status | |
| Simulation time | 26470040737 ps |
| CPU time | 20.42 seconds |
| Started | Jun 04 12:37:06 PM PDT 24 |
| Finished | Jun 04 12:37:27 PM PDT 24 |
| Peak memory | 200264 kb |
| Host | smart-255bd008-1363-427c-88ef-6bf6016d4b2b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1637329613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.1637329613 |
| Directory | /workspace/6.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/6.uart_rx_start_bit_filter.1804301694 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 653803575 ps |
| CPU time | 1.79 seconds |
| Started | Jun 04 12:37:08 PM PDT 24 |
| Finished | Jun 04 12:37:11 PM PDT 24 |
| Peak memory | 195656 kb |
| Host | smart-f11a0a35-b1d5-4faf-99a8-364673fe0bed |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1804301694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.1804301694 |
| Directory | /workspace/6.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/6.uart_smoke.4029468578 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 720217266 ps |
| CPU time | 1.53 seconds |
| Started | Jun 04 12:37:07 PM PDT 24 |
| Finished | Jun 04 12:37:09 PM PDT 24 |
| Peak memory | 198496 kb |
| Host | smart-2b8ec15a-dc0d-4e16-a2e8-c3fcb3e0d20a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4029468578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_smoke.4029468578 |
| Directory | /workspace/6.uart_smoke/latest |
| Test location | /workspace/coverage/default/6.uart_stress_all.2961658668 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 447633610572 ps |
| CPU time | 351.09 seconds |
| Started | Jun 04 12:37:09 PM PDT 24 |
| Finished | Jun 04 12:43:01 PM PDT 24 |
| Peak memory | 200172 kb |
| Host | smart-bf650068-3f03-4b53-9f5c-c8cd93bfe6aa |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961658668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.2961658668 |
| Directory | /workspace/6.uart_stress_all/latest |
| Test location | /workspace/coverage/default/6.uart_stress_all_with_rand_reset.1147428036 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 58434187958 ps |
| CPU time | 189.05 seconds |
| Started | Jun 04 12:37:08 PM PDT 24 |
| Finished | Jun 04 12:40:18 PM PDT 24 |
| Peak memory | 208512 kb |
| Host | smart-25c79b9d-9c77-4c41-888d-9ee709f2cf63 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147428036 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 6.uart_stress_all_with_rand_reset.1147428036 |
| Directory | /workspace/6.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/6.uart_tx_ovrd.24138446 |
| Short name | T977 |
| Test name | |
| Test status | |
| Simulation time | 897157086 ps |
| CPU time | 2.59 seconds |
| Started | Jun 04 12:37:06 PM PDT 24 |
| Finished | Jun 04 12:37:10 PM PDT 24 |
| Peak memory | 199824 kb |
| Host | smart-a8e33a90-9a38-4716-9ed9-a3463725d1fc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=24138446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.24138446 |
| Directory | /workspace/6.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/6.uart_tx_rx.912087717 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 173428746976 ps |
| CPU time | 78.74 seconds |
| Started | Jun 04 12:37:08 PM PDT 24 |
| Finished | Jun 04 12:38:27 PM PDT 24 |
| Peak memory | 200336 kb |
| Host | smart-1dfc0959-b748-4c45-889e-f3c5496da136 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=912087717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.912087717 |
| Directory | /workspace/6.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/60.uart_fifo_reset.2679521164 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 174563167491 ps |
| CPU time | 38.91 seconds |
| Started | Jun 04 12:41:06 PM PDT 24 |
| Finished | Jun 04 12:41:46 PM PDT 24 |
| Peak memory | 200076 kb |
| Host | smart-cdaeb990-ef61-4f5c-9745-e4dac33f2965 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2679521164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.2679521164 |
| Directory | /workspace/60.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/60.uart_stress_all_with_rand_reset.3935182381 |
| Short name | T1131 |
| Test name | |
| Test status | |
| Simulation time | 7565489839 ps |
| CPU time | 104.84 seconds |
| Started | Jun 04 12:41:15 PM PDT 24 |
| Finished | Jun 04 12:43:01 PM PDT 24 |
| Peak memory | 208436 kb |
| Host | smart-d4f39771-3fd0-4fb5-be7e-138c2aafb7fd |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935182381 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 60.uart_stress_all_with_rand_reset.3935182381 |
| Directory | /workspace/60.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/61.uart_fifo_reset.1044884097 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 51439618818 ps |
| CPU time | 287.76 seconds |
| Started | Jun 04 12:41:07 PM PDT 24 |
| Finished | Jun 04 12:45:56 PM PDT 24 |
| Peak memory | 200224 kb |
| Host | smart-1f89945c-94a6-41c5-a6b4-dfa31d3f180e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1044884097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.1044884097 |
| Directory | /workspace/61.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/61.uart_stress_all_with_rand_reset.1480453443 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 38188424834 ps |
| CPU time | 233.55 seconds |
| Started | Jun 04 12:41:06 PM PDT 24 |
| Finished | Jun 04 12:45:01 PM PDT 24 |
| Peak memory | 212072 kb |
| Host | smart-9f1f15ad-c439-40c1-9c65-5e02f8fd8604 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480453443 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 61.uart_stress_all_with_rand_reset.1480453443 |
| Directory | /workspace/61.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/62.uart_fifo_reset.4097620235 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 79903657889 ps |
| CPU time | 95.2 seconds |
| Started | Jun 04 12:41:07 PM PDT 24 |
| Finished | Jun 04 12:42:44 PM PDT 24 |
| Peak memory | 200124 kb |
| Host | smart-0ddf673f-76de-4dfe-b699-470e52839042 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4097620235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.4097620235 |
| Directory | /workspace/62.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/62.uart_stress_all_with_rand_reset.4178875441 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 104108744247 ps |
| CPU time | 788.31 seconds |
| Started | Jun 04 12:41:10 PM PDT 24 |
| Finished | Jun 04 12:54:19 PM PDT 24 |
| Peak memory | 216836 kb |
| Host | smart-e356f186-75ef-48fb-adfc-f119561164e6 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178875441 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 62.uart_stress_all_with_rand_reset.4178875441 |
| Directory | /workspace/62.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/63.uart_fifo_reset.208902960 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 17971615461 ps |
| CPU time | 40.2 seconds |
| Started | Jun 04 12:41:14 PM PDT 24 |
| Finished | Jun 04 12:41:55 PM PDT 24 |
| Peak memory | 200220 kb |
| Host | smart-d3bac0e0-48c5-441b-ba63-faa14322ff11 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=208902960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.208902960 |
| Directory | /workspace/63.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/63.uart_stress_all_with_rand_reset.2800316182 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 4543175564 ps |
| CPU time | 47.14 seconds |
| Started | Jun 04 12:41:09 PM PDT 24 |
| Finished | Jun 04 12:41:56 PM PDT 24 |
| Peak memory | 215872 kb |
| Host | smart-43238167-d1d4-48aa-ad30-9df9409bfddc |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800316182 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 63.uart_stress_all_with_rand_reset.2800316182 |
| Directory | /workspace/63.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/64.uart_fifo_reset.3886774509 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 166195490456 ps |
| CPU time | 251.86 seconds |
| Started | Jun 04 12:41:06 PM PDT 24 |
| Finished | Jun 04 12:45:19 PM PDT 24 |
| Peak memory | 200168 kb |
| Host | smart-7ae15f33-e121-4772-871e-9135786976bf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3886774509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.3886774509 |
| Directory | /workspace/64.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/64.uart_stress_all_with_rand_reset.2636613181 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 54946032902 ps |
| CPU time | 371.35 seconds |
| Started | Jun 04 12:41:08 PM PDT 24 |
| Finished | Jun 04 12:47:21 PM PDT 24 |
| Peak memory | 216908 kb |
| Host | smart-25822d96-71e7-4063-9b3b-52e24fe0f5c0 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636613181 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 64.uart_stress_all_with_rand_reset.2636613181 |
| Directory | /workspace/64.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/65.uart_fifo_reset.3776827438 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 79376376492 ps |
| CPU time | 36.03 seconds |
| Started | Jun 04 12:41:06 PM PDT 24 |
| Finished | Jun 04 12:41:43 PM PDT 24 |
| Peak memory | 200224 kb |
| Host | smart-73497e5a-65df-45b9-bf1f-082a99d8b706 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3776827438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.3776827438 |
| Directory | /workspace/65.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/65.uart_stress_all_with_rand_reset.2275209881 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 22248976187 ps |
| CPU time | 256.04 seconds |
| Started | Jun 04 12:41:06 PM PDT 24 |
| Finished | Jun 04 12:45:23 PM PDT 24 |
| Peak memory | 216704 kb |
| Host | smart-62114fc8-0736-42ed-9272-382737eb2e1c |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275209881 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 65.uart_stress_all_with_rand_reset.2275209881 |
| Directory | /workspace/65.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/66.uart_fifo_reset.444154641 |
| Short name | T998 |
| Test name | |
| Test status | |
| Simulation time | 164095763975 ps |
| CPU time | 25.64 seconds |
| Started | Jun 04 12:41:10 PM PDT 24 |
| Finished | Jun 04 12:41:36 PM PDT 24 |
| Peak memory | 200088 kb |
| Host | smart-32a8e52b-e395-4612-a2b1-2600e50a3139 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=444154641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.444154641 |
| Directory | /workspace/66.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/66.uart_stress_all_with_rand_reset.1280963690 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 140719331364 ps |
| CPU time | 931.35 seconds |
| Started | Jun 04 12:41:07 PM PDT 24 |
| Finished | Jun 04 12:56:40 PM PDT 24 |
| Peak memory | 224976 kb |
| Host | smart-234347eb-68d7-470f-9990-5990338af77f |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280963690 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 66.uart_stress_all_with_rand_reset.1280963690 |
| Directory | /workspace/66.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/67.uart_fifo_reset.4180221089 |
| Short name | T1057 |
| Test name | |
| Test status | |
| Simulation time | 20735669588 ps |
| CPU time | 39.9 seconds |
| Started | Jun 04 12:41:05 PM PDT 24 |
| Finished | Jun 04 12:41:46 PM PDT 24 |
| Peak memory | 200368 kb |
| Host | smart-09b430d9-4305-4ec4-8f8b-598f67e1413e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4180221089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.4180221089 |
| Directory | /workspace/67.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/67.uart_stress_all_with_rand_reset.2847917790 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 81970327041 ps |
| CPU time | 362.49 seconds |
| Started | Jun 04 12:41:06 PM PDT 24 |
| Finished | Jun 04 12:47:10 PM PDT 24 |
| Peak memory | 216616 kb |
| Host | smart-03175903-94fc-4dce-8098-252646928b0a |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847917790 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 67.uart_stress_all_with_rand_reset.2847917790 |
| Directory | /workspace/67.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/68.uart_fifo_reset.4127091204 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 108963191987 ps |
| CPU time | 124.82 seconds |
| Started | Jun 04 12:41:05 PM PDT 24 |
| Finished | Jun 04 12:43:11 PM PDT 24 |
| Peak memory | 200172 kb |
| Host | smart-f23985c7-c768-4aaa-84ac-8159595e503a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4127091204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.4127091204 |
| Directory | /workspace/68.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/68.uart_stress_all_with_rand_reset.669086625 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 165792361293 ps |
| CPU time | 508.13 seconds |
| Started | Jun 04 12:41:16 PM PDT 24 |
| Finished | Jun 04 12:49:45 PM PDT 24 |
| Peak memory | 225016 kb |
| Host | smart-51b29dba-2fc7-47dc-820c-c3577a68239f |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669086625 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 68.uart_stress_all_with_rand_reset.669086625 |
| Directory | /workspace/68.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/69.uart_fifo_reset.1796302621 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 119231893446 ps |
| CPU time | 183.66 seconds |
| Started | Jun 04 12:41:07 PM PDT 24 |
| Finished | Jun 04 12:44:12 PM PDT 24 |
| Peak memory | 200292 kb |
| Host | smart-f651a62e-e6db-47ba-a721-e40ea1163013 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1796302621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.1796302621 |
| Directory | /workspace/69.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/69.uart_stress_all_with_rand_reset.2334816660 |
| Short name | T1042 |
| Test name | |
| Test status | |
| Simulation time | 286230008882 ps |
| CPU time | 339.86 seconds |
| Started | Jun 04 12:41:14 PM PDT 24 |
| Finished | Jun 04 12:46:55 PM PDT 24 |
| Peak memory | 208588 kb |
| Host | smart-8e4f6243-542d-4e90-b915-5b3812a902e7 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334816660 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 69.uart_stress_all_with_rand_reset.2334816660 |
| Directory | /workspace/69.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/7.uart_alert_test.1234770714 |
| Short name | T1123 |
| Test name | |
| Test status | |
| Simulation time | 20051694 ps |
| CPU time | 0.57 seconds |
| Started | Jun 04 12:37:17 PM PDT 24 |
| Finished | Jun 04 12:37:19 PM PDT 24 |
| Peak memory | 195600 kb |
| Host | smart-a8873a8b-0a19-42a5-82b0-393c3556a720 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234770714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.1234770714 |
| Directory | /workspace/7.uart_alert_test/latest |
| Test location | /workspace/coverage/default/7.uart_fifo_full.3857114791 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 152092171544 ps |
| CPU time | 70.95 seconds |
| Started | Jun 04 12:37:09 PM PDT 24 |
| Finished | Jun 04 12:38:21 PM PDT 24 |
| Peak memory | 200188 kb |
| Host | smart-207cecba-a7d7-47b3-bfae-69f2905d6c42 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3857114791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.3857114791 |
| Directory | /workspace/7.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/7.uart_fifo_overflow.1367242181 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 29357957073 ps |
| CPU time | 15.7 seconds |
| Started | Jun 04 12:37:16 PM PDT 24 |
| Finished | Jun 04 12:37:33 PM PDT 24 |
| Peak memory | 200196 kb |
| Host | smart-58c5642a-5f03-4b60-a109-5a69ba647f7c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1367242181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.1367242181 |
| Directory | /workspace/7.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/7.uart_fifo_reset.2729076412 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 14982759113 ps |
| CPU time | 23.36 seconds |
| Started | Jun 04 12:37:17 PM PDT 24 |
| Finished | Jun 04 12:37:42 PM PDT 24 |
| Peak memory | 200256 kb |
| Host | smart-3419352c-aa31-46bf-bead-06d543f87aea |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2729076412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.2729076412 |
| Directory | /workspace/7.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/7.uart_intr.2924044222 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 27320825745 ps |
| CPU time | 11.75 seconds |
| Started | Jun 04 12:37:17 PM PDT 24 |
| Finished | Jun 04 12:37:30 PM PDT 24 |
| Peak memory | 200208 kb |
| Host | smart-d0aca91c-9acb-44bf-ac2b-fec2a7187a0b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924044222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.2924044222 |
| Directory | /workspace/7.uart_intr/latest |
| Test location | /workspace/coverage/default/7.uart_long_xfer_wo_dly.791715304 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 369529094509 ps |
| CPU time | 403.56 seconds |
| Started | Jun 04 12:37:17 PM PDT 24 |
| Finished | Jun 04 12:44:01 PM PDT 24 |
| Peak memory | 200368 kb |
| Host | smart-d92ff5e5-33d2-4cf9-8de8-3ff3ffb61272 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=791715304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.791715304 |
| Directory | /workspace/7.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/7.uart_loopback.2040696692 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 7263735334 ps |
| CPU time | 18.95 seconds |
| Started | Jun 04 12:37:17 PM PDT 24 |
| Finished | Jun 04 12:37:37 PM PDT 24 |
| Peak memory | 199400 kb |
| Host | smart-85d18df5-c0fe-494b-a23d-35c96f7fcc25 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2040696692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_loopback.2040696692 |
| Directory | /workspace/7.uart_loopback/latest |
| Test location | /workspace/coverage/default/7.uart_noise_filter.3279625082 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 125844913403 ps |
| CPU time | 156.46 seconds |
| Started | Jun 04 12:37:18 PM PDT 24 |
| Finished | Jun 04 12:39:55 PM PDT 24 |
| Peak memory | 208576 kb |
| Host | smart-92fe649a-e6ff-41e0-b105-e102c9e92d99 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3279625082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_noise_filter.3279625082 |
| Directory | /workspace/7.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/7.uart_perf.187788806 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 22137642990 ps |
| CPU time | 250.86 seconds |
| Started | Jun 04 12:37:13 PM PDT 24 |
| Finished | Jun 04 12:41:25 PM PDT 24 |
| Peak memory | 200208 kb |
| Host | smart-604ec0e2-fc0d-49c1-8698-56e9db4aa2ec |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=187788806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.187788806 |
| Directory | /workspace/7.uart_perf/latest |
| Test location | /workspace/coverage/default/7.uart_rx_oversample.3007649875 |
| Short name | T1095 |
| Test name | |
| Test status | |
| Simulation time | 1782830261 ps |
| CPU time | 6.24 seconds |
| Started | Jun 04 12:37:16 PM PDT 24 |
| Finished | Jun 04 12:37:24 PM PDT 24 |
| Peak memory | 198396 kb |
| Host | smart-33ccc962-e258-40e9-95ff-f1476329a581 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3007649875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.3007649875 |
| Directory | /workspace/7.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/7.uart_rx_parity_err.4070362878 |
| Short name | T1050 |
| Test name | |
| Test status | |
| Simulation time | 45093555249 ps |
| CPU time | 104.41 seconds |
| Started | Jun 04 12:37:16 PM PDT 24 |
| Finished | Jun 04 12:39:01 PM PDT 24 |
| Peak memory | 200208 kb |
| Host | smart-db8360fd-5b22-4749-8f8a-5edde239f466 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4070362878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.4070362878 |
| Directory | /workspace/7.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/7.uart_rx_start_bit_filter.3485776445 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 6131825530 ps |
| CPU time | 10.89 seconds |
| Started | Jun 04 12:37:18 PM PDT 24 |
| Finished | Jun 04 12:37:30 PM PDT 24 |
| Peak memory | 196500 kb |
| Host | smart-1fc3def6-504d-4251-bcf0-928a97f10b7d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3485776445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.3485776445 |
| Directory | /workspace/7.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/7.uart_smoke.2809555236 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 848925488 ps |
| CPU time | 2.26 seconds |
| Started | Jun 04 12:37:08 PM PDT 24 |
| Finished | Jun 04 12:37:12 PM PDT 24 |
| Peak memory | 198868 kb |
| Host | smart-fb1db01c-4590-4be7-9e2f-471293f11ed1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2809555236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_smoke.2809555236 |
| Directory | /workspace/7.uart_smoke/latest |
| Test location | /workspace/coverage/default/7.uart_stress_all.600515181 |
| Short name | T1121 |
| Test name | |
| Test status | |
| Simulation time | 146363691507 ps |
| CPU time | 139.69 seconds |
| Started | Jun 04 12:37:13 PM PDT 24 |
| Finished | Jun 04 12:39:34 PM PDT 24 |
| Peak memory | 200236 kb |
| Host | smart-03cb09b4-8fb5-46d7-b843-18594a48a50e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600515181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.600515181 |
| Directory | /workspace/7.uart_stress_all/latest |
| Test location | /workspace/coverage/default/7.uart_stress_all_with_rand_reset.3105596100 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 517658518465 ps |
| CPU time | 681.68 seconds |
| Started | Jun 04 12:37:17 PM PDT 24 |
| Finished | Jun 04 12:48:40 PM PDT 24 |
| Peak memory | 216632 kb |
| Host | smart-5cee2c44-317d-43f3-a9c2-e419074f48db |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105596100 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 7.uart_stress_all_with_rand_reset.3105596100 |
| Directory | /workspace/7.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/7.uart_tx_ovrd.2492608990 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 2164834900 ps |
| CPU time | 2.36 seconds |
| Started | Jun 04 12:37:17 PM PDT 24 |
| Finished | Jun 04 12:37:20 PM PDT 24 |
| Peak memory | 198620 kb |
| Host | smart-64166162-9052-4453-b8ba-5e411b548f64 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2492608990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.2492608990 |
| Directory | /workspace/7.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/7.uart_tx_rx.299636983 |
| Short name | T922 |
| Test name | |
| Test status | |
| Simulation time | 45148174066 ps |
| CPU time | 125.57 seconds |
| Started | Jun 04 12:37:07 PM PDT 24 |
| Finished | Jun 04 12:39:13 PM PDT 24 |
| Peak memory | 200176 kb |
| Host | smart-aaef4cc1-06d0-4426-a442-ebbf50205ca9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=299636983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.299636983 |
| Directory | /workspace/7.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/70.uart_fifo_reset.1649961877 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 77307385481 ps |
| CPU time | 56.41 seconds |
| Started | Jun 04 12:41:07 PM PDT 24 |
| Finished | Jun 04 12:42:05 PM PDT 24 |
| Peak memory | 200148 kb |
| Host | smart-1bbcef5d-5779-4052-a512-10ada0e84ab8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1649961877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.1649961877 |
| Directory | /workspace/70.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/71.uart_fifo_reset.301110921 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 167859705637 ps |
| CPU time | 19.48 seconds |
| Started | Jun 04 12:41:08 PM PDT 24 |
| Finished | Jun 04 12:41:28 PM PDT 24 |
| Peak memory | 200244 kb |
| Host | smart-89d83730-9385-44ca-af25-ca8cce78845d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=301110921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.301110921 |
| Directory | /workspace/71.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/71.uart_stress_all_with_rand_reset.774294039 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 103151332844 ps |
| CPU time | 586.37 seconds |
| Started | Jun 04 12:41:15 PM PDT 24 |
| Finished | Jun 04 12:51:02 PM PDT 24 |
| Peak memory | 216568 kb |
| Host | smart-5c121e00-2140-4d33-8089-dd7a6c8795e9 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774294039 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 71.uart_stress_all_with_rand_reset.774294039 |
| Directory | /workspace/71.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/72.uart_fifo_reset.1301459358 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 50216842567 ps |
| CPU time | 29.18 seconds |
| Started | Jun 04 12:41:06 PM PDT 24 |
| Finished | Jun 04 12:41:36 PM PDT 24 |
| Peak memory | 200168 kb |
| Host | smart-f998d8d1-aaf5-4784-80c7-cd6651ec4afe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1301459358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.1301459358 |
| Directory | /workspace/72.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/72.uart_stress_all_with_rand_reset.1765206594 |
| Short name | T1084 |
| Test name | |
| Test status | |
| Simulation time | 89362677314 ps |
| CPU time | 279.89 seconds |
| Started | Jun 04 12:41:13 PM PDT 24 |
| Finished | Jun 04 12:45:54 PM PDT 24 |
| Peak memory | 216660 kb |
| Host | smart-f09d627e-5b46-40f9-ba56-f52b9bafbc9b |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765206594 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 72.uart_stress_all_with_rand_reset.1765206594 |
| Directory | /workspace/72.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/73.uart_fifo_reset.2877895447 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 27897591478 ps |
| CPU time | 20.97 seconds |
| Started | Jun 04 12:41:08 PM PDT 24 |
| Finished | Jun 04 12:41:30 PM PDT 24 |
| Peak memory | 200264 kb |
| Host | smart-3e5ed794-2188-43c3-a859-ad61c290369c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2877895447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.2877895447 |
| Directory | /workspace/73.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/73.uart_stress_all_with_rand_reset.3104947075 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 261991937849 ps |
| CPU time | 768.59 seconds |
| Started | Jun 04 12:41:14 PM PDT 24 |
| Finished | Jun 04 12:54:04 PM PDT 24 |
| Peak memory | 224000 kb |
| Host | smart-198c9f40-70e0-4b7e-9812-e67f701c5c4b |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104947075 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 73.uart_stress_all_with_rand_reset.3104947075 |
| Directory | /workspace/73.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/74.uart_fifo_reset.3244243844 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 108480712975 ps |
| CPU time | 36.19 seconds |
| Started | Jun 04 12:41:14 PM PDT 24 |
| Finished | Jun 04 12:41:50 PM PDT 24 |
| Peak memory | 200200 kb |
| Host | smart-a679e2a3-b0c0-4cc6-a8ef-ce696818b03a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3244243844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.3244243844 |
| Directory | /workspace/74.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/75.uart_fifo_reset.243053886 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 170576327512 ps |
| CPU time | 428.13 seconds |
| Started | Jun 04 12:41:17 PM PDT 24 |
| Finished | Jun 04 12:48:26 PM PDT 24 |
| Peak memory | 200244 kb |
| Host | smart-a28d8b95-9ee9-4932-9384-fbdc5b68d794 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=243053886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.243053886 |
| Directory | /workspace/75.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/75.uart_stress_all_with_rand_reset.2739483251 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 93405694905 ps |
| CPU time | 508.77 seconds |
| Started | Jun 04 12:41:17 PM PDT 24 |
| Finished | Jun 04 12:49:47 PM PDT 24 |
| Peak memory | 217012 kb |
| Host | smart-fe6bb976-4f8d-4360-ae16-aecdf6fc428c |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739483251 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 75.uart_stress_all_with_rand_reset.2739483251 |
| Directory | /workspace/75.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/76.uart_fifo_reset.3906260326 |
| Short name | T1011 |
| Test name | |
| Test status | |
| Simulation time | 59782211635 ps |
| CPU time | 25.31 seconds |
| Started | Jun 04 12:41:17 PM PDT 24 |
| Finished | Jun 04 12:41:43 PM PDT 24 |
| Peak memory | 200232 kb |
| Host | smart-e0fce4a8-96f6-44ed-8c59-b3f5161e52c8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3906260326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.3906260326 |
| Directory | /workspace/76.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/76.uart_stress_all_with_rand_reset.3760825895 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 139490751145 ps |
| CPU time | 1571.04 seconds |
| Started | Jun 04 12:41:17 PM PDT 24 |
| Finished | Jun 04 01:07:29 PM PDT 24 |
| Peak memory | 228784 kb |
| Host | smart-bc6d45ee-c470-4834-bae1-f91bac333dbf |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760825895 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 76.uart_stress_all_with_rand_reset.3760825895 |
| Directory | /workspace/76.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/77.uart_fifo_reset.2077871265 |
| Short name | T1030 |
| Test name | |
| Test status | |
| Simulation time | 24392779005 ps |
| CPU time | 20.26 seconds |
| Started | Jun 04 12:41:19 PM PDT 24 |
| Finished | Jun 04 12:41:40 PM PDT 24 |
| Peak memory | 200344 kb |
| Host | smart-d6982666-3937-45f1-b9f3-e889bf3ad605 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2077871265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.2077871265 |
| Directory | /workspace/77.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/77.uart_stress_all_with_rand_reset.1185540283 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 108419055735 ps |
| CPU time | 1007.97 seconds |
| Started | Jun 04 12:41:17 PM PDT 24 |
| Finished | Jun 04 12:58:06 PM PDT 24 |
| Peak memory | 227132 kb |
| Host | smart-f4634b31-9099-4688-afbe-0d3798e548cf |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185540283 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 77.uart_stress_all_with_rand_reset.1185540283 |
| Directory | /workspace/77.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/78.uart_fifo_reset.3443274103 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 85696571122 ps |
| CPU time | 76.76 seconds |
| Started | Jun 04 12:41:20 PM PDT 24 |
| Finished | Jun 04 12:42:37 PM PDT 24 |
| Peak memory | 200188 kb |
| Host | smart-3ce6b055-cafa-4a2c-a46a-2727d2b6c742 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3443274103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.3443274103 |
| Directory | /workspace/78.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/78.uart_stress_all_with_rand_reset.924541360 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 35812292381 ps |
| CPU time | 480.71 seconds |
| Started | Jun 04 12:41:18 PM PDT 24 |
| Finished | Jun 04 12:49:19 PM PDT 24 |
| Peak memory | 216876 kb |
| Host | smart-271dc139-9d43-4e81-8c49-967f7fecfa74 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924541360 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 78.uart_stress_all_with_rand_reset.924541360 |
| Directory | /workspace/78.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/79.uart_fifo_reset.1977260363 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 25175082508 ps |
| CPU time | 20.13 seconds |
| Started | Jun 04 12:41:18 PM PDT 24 |
| Finished | Jun 04 12:41:39 PM PDT 24 |
| Peak memory | 199784 kb |
| Host | smart-431d510e-6b3c-44a5-b292-8133c5dd8954 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1977260363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.1977260363 |
| Directory | /workspace/79.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/79.uart_stress_all_with_rand_reset.825854419 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 132185626010 ps |
| CPU time | 831.96 seconds |
| Started | Jun 04 12:41:17 PM PDT 24 |
| Finished | Jun 04 12:55:09 PM PDT 24 |
| Peak memory | 215908 kb |
| Host | smart-c0ffaab6-9d08-46db-97d4-aa39ed6380d5 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825854419 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 79.uart_stress_all_with_rand_reset.825854419 |
| Directory | /workspace/79.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/8.uart_alert_test.2269360080 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 34126130 ps |
| CPU time | 0.54 seconds |
| Started | Jun 04 12:37:25 PM PDT 24 |
| Finished | Jun 04 12:37:26 PM PDT 24 |
| Peak memory | 195680 kb |
| Host | smart-0a254a09-ca29-420d-89d1-31a1ef528bb6 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269360080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.2269360080 |
| Directory | /workspace/8.uart_alert_test/latest |
| Test location | /workspace/coverage/default/8.uart_fifo_full.724916829 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 48541695078 ps |
| CPU time | 34.72 seconds |
| Started | Jun 04 12:37:17 PM PDT 24 |
| Finished | Jun 04 12:37:53 PM PDT 24 |
| Peak memory | 200172 kb |
| Host | smart-c3cadc4d-5175-43ff-9223-f40e702eafa4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=724916829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.724916829 |
| Directory | /workspace/8.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/8.uart_fifo_overflow.2956888638 |
| Short name | T1072 |
| Test name | |
| Test status | |
| Simulation time | 121372415434 ps |
| CPU time | 29.2 seconds |
| Started | Jun 04 12:37:18 PM PDT 24 |
| Finished | Jun 04 12:37:48 PM PDT 24 |
| Peak memory | 200240 kb |
| Host | smart-2760b067-82db-43da-9fc8-02920250d109 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2956888638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.2956888638 |
| Directory | /workspace/8.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/8.uart_fifo_reset.2645562797 |
| Short name | T974 |
| Test name | |
| Test status | |
| Simulation time | 12626627539 ps |
| CPU time | 4.21 seconds |
| Started | Jun 04 12:37:18 PM PDT 24 |
| Finished | Jun 04 12:37:23 PM PDT 24 |
| Peak memory | 199208 kb |
| Host | smart-c6995bc8-fd87-498e-a768-f09b04f1366c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2645562797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.2645562797 |
| Directory | /workspace/8.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/8.uart_intr.386967487 |
| Short name | T1172 |
| Test name | |
| Test status | |
| Simulation time | 10182503228 ps |
| CPU time | 4.87 seconds |
| Started | Jun 04 12:37:16 PM PDT 24 |
| Finished | Jun 04 12:37:22 PM PDT 24 |
| Peak memory | 197344 kb |
| Host | smart-59fe8c05-fcee-4adb-9085-8e78e2f46a8a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386967487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.386967487 |
| Directory | /workspace/8.uart_intr/latest |
| Test location | /workspace/coverage/default/8.uart_long_xfer_wo_dly.2285148030 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 88252860151 ps |
| CPU time | 303.11 seconds |
| Started | Jun 04 12:37:14 PM PDT 24 |
| Finished | Jun 04 12:42:18 PM PDT 24 |
| Peak memory | 200176 kb |
| Host | smart-2bbf14eb-49e2-4c12-b7e8-9e24a1950d9d |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2285148030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.2285148030 |
| Directory | /workspace/8.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/8.uart_loopback.2095581434 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 3687455647 ps |
| CPU time | 6.68 seconds |
| Started | Jun 04 12:37:17 PM PDT 24 |
| Finished | Jun 04 12:37:24 PM PDT 24 |
| Peak memory | 199352 kb |
| Host | smart-1bbce8d0-25d0-4f59-8b15-c5c1956b35a1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2095581434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_loopback.2095581434 |
| Directory | /workspace/8.uart_loopback/latest |
| Test location | /workspace/coverage/default/8.uart_noise_filter.25409792 |
| Short name | T927 |
| Test name | |
| Test status | |
| Simulation time | 71708857995 ps |
| CPU time | 33.73 seconds |
| Started | Jun 04 12:37:16 PM PDT 24 |
| Finished | Jun 04 12:37:51 PM PDT 24 |
| Peak memory | 208632 kb |
| Host | smart-260defd3-f391-4669-ade0-2fa28ec4a24a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=25409792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_noise_filter.25409792 |
| Directory | /workspace/8.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/8.uart_perf.292047315 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 17522234964 ps |
| CPU time | 169.13 seconds |
| Started | Jun 04 12:37:16 PM PDT 24 |
| Finished | Jun 04 12:40:07 PM PDT 24 |
| Peak memory | 200216 kb |
| Host | smart-8d5f800e-5015-4b44-9d3a-dfe67dbc66c5 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=292047315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.292047315 |
| Directory | /workspace/8.uart_perf/latest |
| Test location | /workspace/coverage/default/8.uart_rx_oversample.2063146127 |
| Short name | T1147 |
| Test name | |
| Test status | |
| Simulation time | 5899389447 ps |
| CPU time | 59.13 seconds |
| Started | Jun 04 12:37:16 PM PDT 24 |
| Finished | Jun 04 12:38:15 PM PDT 24 |
| Peak memory | 198440 kb |
| Host | smart-08563757-8da2-404d-8bee-826d005f1f14 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2063146127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.2063146127 |
| Directory | /workspace/8.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/8.uart_rx_parity_err.2524987289 |
| Short name | T1148 |
| Test name | |
| Test status | |
| Simulation time | 24883505558 ps |
| CPU time | 38.09 seconds |
| Started | Jun 04 12:37:15 PM PDT 24 |
| Finished | Jun 04 12:37:54 PM PDT 24 |
| Peak memory | 200164 kb |
| Host | smart-4f152d48-08a7-4fc9-8fd0-881794c8901f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2524987289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.2524987289 |
| Directory | /workspace/8.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/8.uart_rx_start_bit_filter.1487210844 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 3250608386 ps |
| CPU time | 6.35 seconds |
| Started | Jun 04 12:37:16 PM PDT 24 |
| Finished | Jun 04 12:37:23 PM PDT 24 |
| Peak memory | 196192 kb |
| Host | smart-bee2dca1-51ab-4514-9077-19bcd2d4c58a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1487210844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.1487210844 |
| Directory | /workspace/8.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/8.uart_smoke.4241069349 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 850026990 ps |
| CPU time | 2.11 seconds |
| Started | Jun 04 12:37:18 PM PDT 24 |
| Finished | Jun 04 12:37:21 PM PDT 24 |
| Peak memory | 198620 kb |
| Host | smart-3acb4c07-ccfb-42ae-957a-7e2dbac530cc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4241069349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_smoke.4241069349 |
| Directory | /workspace/8.uart_smoke/latest |
| Test location | /workspace/coverage/default/8.uart_stress_all.2681319296 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 4050365411 ps |
| CPU time | 12.36 seconds |
| Started | Jun 04 12:37:25 PM PDT 24 |
| Finished | Jun 04 12:37:38 PM PDT 24 |
| Peak memory | 200208 kb |
| Host | smart-adcd7469-b50c-46a5-93f4-89260d5fd608 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681319296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.2681319296 |
| Directory | /workspace/8.uart_stress_all/latest |
| Test location | /workspace/coverage/default/8.uart_stress_all_with_rand_reset.1291535584 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 132309171426 ps |
| CPU time | 336.28 seconds |
| Started | Jun 04 12:37:17 PM PDT 24 |
| Finished | Jun 04 12:42:55 PM PDT 24 |
| Peak memory | 216584 kb |
| Host | smart-0e221c95-d5f6-44fb-853a-849b774f8f4a |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291535584 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 8.uart_stress_all_with_rand_reset.1291535584 |
| Directory | /workspace/8.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/8.uart_tx_ovrd.4040929581 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 1246049851 ps |
| CPU time | 4.53 seconds |
| Started | Jun 04 12:37:16 PM PDT 24 |
| Finished | Jun 04 12:37:21 PM PDT 24 |
| Peak memory | 198496 kb |
| Host | smart-c4eba49d-4762-4fbc-a7d6-1fec79ce65db |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4040929581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.4040929581 |
| Directory | /workspace/8.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/8.uart_tx_rx.1582777726 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 49353791789 ps |
| CPU time | 18.63 seconds |
| Started | Jun 04 12:37:17 PM PDT 24 |
| Finished | Jun 04 12:37:37 PM PDT 24 |
| Peak memory | 200208 kb |
| Host | smart-a6ff8f04-8078-437e-b06f-59b8fd843a93 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1582777726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.1582777726 |
| Directory | /workspace/8.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/80.uart_fifo_reset.3689827968 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 95626202248 ps |
| CPU time | 15.25 seconds |
| Started | Jun 04 12:41:15 PM PDT 24 |
| Finished | Jun 04 12:41:31 PM PDT 24 |
| Peak memory | 200336 kb |
| Host | smart-dc6bbd81-17ef-4a06-969f-564e9b9677fe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3689827968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.3689827968 |
| Directory | /workspace/80.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/80.uart_stress_all_with_rand_reset.1178506686 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 152145427965 ps |
| CPU time | 456.08 seconds |
| Started | Jun 04 12:41:16 PM PDT 24 |
| Finished | Jun 04 12:48:53 PM PDT 24 |
| Peak memory | 227020 kb |
| Host | smart-51bed99c-5b54-4986-adb9-1be017829b00 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178506686 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 80.uart_stress_all_with_rand_reset.1178506686 |
| Directory | /workspace/80.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/81.uart_fifo_reset.2490699514 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 11479317672 ps |
| CPU time | 18.2 seconds |
| Started | Jun 04 12:41:17 PM PDT 24 |
| Finished | Jun 04 12:41:36 PM PDT 24 |
| Peak memory | 199732 kb |
| Host | smart-fb5de555-9347-45a1-92ff-67a6c1490848 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2490699514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.2490699514 |
| Directory | /workspace/81.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/82.uart_fifo_reset.1979892863 |
| Short name | T954 |
| Test name | |
| Test status | |
| Simulation time | 117130644596 ps |
| CPU time | 43.97 seconds |
| Started | Jun 04 12:41:17 PM PDT 24 |
| Finished | Jun 04 12:42:01 PM PDT 24 |
| Peak memory | 200328 kb |
| Host | smart-43d5a213-79f3-48d9-9d78-c9f0cad8893b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1979892863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.1979892863 |
| Directory | /workspace/82.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/82.uart_stress_all_with_rand_reset.3384530246 |
| Short name | T1049 |
| Test name | |
| Test status | |
| Simulation time | 181707418360 ps |
| CPU time | 160.68 seconds |
| Started | Jun 04 12:41:16 PM PDT 24 |
| Finished | Jun 04 12:43:57 PM PDT 24 |
| Peak memory | 216032 kb |
| Host | smart-e84090df-cd14-47c1-9aaa-b99c93e80c50 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384530246 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 82.uart_stress_all_with_rand_reset.3384530246 |
| Directory | /workspace/82.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/83.uart_fifo_reset.4268394592 |
| Short name | T1056 |
| Test name | |
| Test status | |
| Simulation time | 22553458003 ps |
| CPU time | 38.37 seconds |
| Started | Jun 04 12:41:17 PM PDT 24 |
| Finished | Jun 04 12:41:56 PM PDT 24 |
| Peak memory | 200152 kb |
| Host | smart-c2d07668-49fc-4595-af94-223d05368d37 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4268394592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.4268394592 |
| Directory | /workspace/83.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/83.uart_stress_all_with_rand_reset.2847147369 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 37105072287 ps |
| CPU time | 300.86 seconds |
| Started | Jun 04 12:41:19 PM PDT 24 |
| Finished | Jun 04 12:46:20 PM PDT 24 |
| Peak memory | 208480 kb |
| Host | smart-fc0b84b5-6bd4-462e-a953-50a79adb3477 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847147369 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 83.uart_stress_all_with_rand_reset.2847147369 |
| Directory | /workspace/83.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/84.uart_stress_all_with_rand_reset.3038670484 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 833915827060 ps |
| CPU time | 1021.04 seconds |
| Started | Jun 04 12:41:16 PM PDT 24 |
| Finished | Jun 04 12:58:18 PM PDT 24 |
| Peak memory | 225152 kb |
| Host | smart-c7da7e36-ebfc-482f-b248-37d6a85d95d3 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038670484 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 84.uart_stress_all_with_rand_reset.3038670484 |
| Directory | /workspace/84.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/85.uart_fifo_reset.1830745501 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 106168581352 ps |
| CPU time | 178.27 seconds |
| Started | Jun 04 12:41:17 PM PDT 24 |
| Finished | Jun 04 12:44:16 PM PDT 24 |
| Peak memory | 200208 kb |
| Host | smart-f7f10c15-ba28-48c2-9e53-876fae8e4c73 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1830745501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.1830745501 |
| Directory | /workspace/85.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/86.uart_fifo_reset.2679372732 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 111735772912 ps |
| CPU time | 88.02 seconds |
| Started | Jun 04 12:41:24 PM PDT 24 |
| Finished | Jun 04 12:42:53 PM PDT 24 |
| Peak memory | 200324 kb |
| Host | smart-4194e4fa-7454-485e-9a01-a2d93c43bec6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2679372732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.2679372732 |
| Directory | /workspace/86.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/86.uart_stress_all_with_rand_reset.1787798492 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 195025146117 ps |
| CPU time | 608.24 seconds |
| Started | Jun 04 12:41:26 PM PDT 24 |
| Finished | Jun 04 12:51:35 PM PDT 24 |
| Peak memory | 225160 kb |
| Host | smart-b877dea3-2850-4dd9-b516-958b36462c4e |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787798492 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 86.uart_stress_all_with_rand_reset.1787798492 |
| Directory | /workspace/86.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/87.uart_stress_all_with_rand_reset.2907363799 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 12684561608 ps |
| CPU time | 121.99 seconds |
| Started | Jun 04 12:41:24 PM PDT 24 |
| Finished | Jun 04 12:43:27 PM PDT 24 |
| Peak memory | 216568 kb |
| Host | smart-c2f34e93-d265-4b98-946b-152bc268f2f0 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907363799 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 87.uart_stress_all_with_rand_reset.2907363799 |
| Directory | /workspace/87.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/88.uart_fifo_reset.433499185 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 88499831992 ps |
| CPU time | 20.99 seconds |
| Started | Jun 04 12:41:32 PM PDT 24 |
| Finished | Jun 04 12:41:54 PM PDT 24 |
| Peak memory | 200140 kb |
| Host | smart-324bce16-5635-4d47-98a3-4f739dbfbc3b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=433499185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.433499185 |
| Directory | /workspace/88.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/88.uart_stress_all_with_rand_reset.975518633 |
| Short name | T980 |
| Test name | |
| Test status | |
| Simulation time | 291350829715 ps |
| CPU time | 1740.51 seconds |
| Started | Jun 04 12:41:25 PM PDT 24 |
| Finished | Jun 04 01:10:26 PM PDT 24 |
| Peak memory | 244836 kb |
| Host | smart-e30aed7c-cc04-4eda-b05e-d87b83d5592d |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975518633 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 88.uart_stress_all_with_rand_reset.975518633 |
| Directory | /workspace/88.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/89.uart_fifo_reset.2837316460 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 17465646847 ps |
| CPU time | 13.94 seconds |
| Started | Jun 04 12:41:27 PM PDT 24 |
| Finished | Jun 04 12:41:42 PM PDT 24 |
| Peak memory | 200204 kb |
| Host | smart-8a7f4f4f-81e0-477b-b5d2-405bedf7a02d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2837316460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.2837316460 |
| Directory | /workspace/89.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/9.uart_alert_test.2072278145 |
| Short name | T1174 |
| Test name | |
| Test status | |
| Simulation time | 15862724 ps |
| CPU time | 0.56 seconds |
| Started | Jun 04 12:37:25 PM PDT 24 |
| Finished | Jun 04 12:37:27 PM PDT 24 |
| Peak memory | 195708 kb |
| Host | smart-73accd5a-0042-446b-8591-b6a61989ba31 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072278145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.2072278145 |
| Directory | /workspace/9.uart_alert_test/latest |
| Test location | /workspace/coverage/default/9.uart_fifo_full.3140760637 |
| Short name | T1015 |
| Test name | |
| Test status | |
| Simulation time | 39467173989 ps |
| CPU time | 82.75 seconds |
| Started | Jun 04 12:37:25 PM PDT 24 |
| Finished | Jun 04 12:38:49 PM PDT 24 |
| Peak memory | 200160 kb |
| Host | smart-cb72a3c9-7197-48f6-805c-5c45f173199b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3140760637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.3140760637 |
| Directory | /workspace/9.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/9.uart_fifo_overflow.888785402 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 68691033844 ps |
| CPU time | 25.11 seconds |
| Started | Jun 04 12:37:26 PM PDT 24 |
| Finished | Jun 04 12:37:52 PM PDT 24 |
| Peak memory | 199572 kb |
| Host | smart-02b76c07-855a-430d-96e5-f85284fe4e17 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=888785402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.888785402 |
| Directory | /workspace/9.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/9.uart_intr.2752294107 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 23202428281 ps |
| CPU time | 35.96 seconds |
| Started | Jun 04 12:37:25 PM PDT 24 |
| Finished | Jun 04 12:38:02 PM PDT 24 |
| Peak memory | 199836 kb |
| Host | smart-edb27d89-3bbc-4627-ba32-9136f532b966 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752294107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.2752294107 |
| Directory | /workspace/9.uart_intr/latest |
| Test location | /workspace/coverage/default/9.uart_long_xfer_wo_dly.1288220021 |
| Short name | T947 |
| Test name | |
| Test status | |
| Simulation time | 42845617938 ps |
| CPU time | 195.22 seconds |
| Started | Jun 04 12:37:25 PM PDT 24 |
| Finished | Jun 04 12:40:41 PM PDT 24 |
| Peak memory | 200208 kb |
| Host | smart-7dc053c3-52d2-498a-9700-6d52aa13acc0 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1288220021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.1288220021 |
| Directory | /workspace/9.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/9.uart_loopback.2924274624 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 8816641481 ps |
| CPU time | 6.47 seconds |
| Started | Jun 04 12:37:25 PM PDT 24 |
| Finished | Jun 04 12:37:33 PM PDT 24 |
| Peak memory | 199924 kb |
| Host | smart-65382a9b-e71d-4a47-8b63-34eee15ca6b4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2924274624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_loopback.2924274624 |
| Directory | /workspace/9.uart_loopback/latest |
| Test location | /workspace/coverage/default/9.uart_noise_filter.497711012 |
| Short name | T1111 |
| Test name | |
| Test status | |
| Simulation time | 14077279510 ps |
| CPU time | 7.72 seconds |
| Started | Jun 04 12:37:26 PM PDT 24 |
| Finished | Jun 04 12:37:35 PM PDT 24 |
| Peak memory | 198512 kb |
| Host | smart-35ebfd85-1dc5-4a2b-86f6-682ad75e3491 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=497711012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.497711012 |
| Directory | /workspace/9.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/9.uart_perf.880234182 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 22871675637 ps |
| CPU time | 1330.78 seconds |
| Started | Jun 04 12:37:25 PM PDT 24 |
| Finished | Jun 04 12:59:38 PM PDT 24 |
| Peak memory | 200128 kb |
| Host | smart-d51f0a12-a065-488a-a12d-fa9989bf4656 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=880234182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.880234182 |
| Directory | /workspace/9.uart_perf/latest |
| Test location | /workspace/coverage/default/9.uart_rx_oversample.2431483094 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 1190079268 ps |
| CPU time | 1.09 seconds |
| Started | Jun 04 12:37:25 PM PDT 24 |
| Finished | Jun 04 12:37:28 PM PDT 24 |
| Peak memory | 195776 kb |
| Host | smart-c1069913-9cca-4f15-9752-d4d13bae2b69 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2431483094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.2431483094 |
| Directory | /workspace/9.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/9.uart_rx_parity_err.1826251509 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 129074938784 ps |
| CPU time | 211.23 seconds |
| Started | Jun 04 12:37:26 PM PDT 24 |
| Finished | Jun 04 12:40:59 PM PDT 24 |
| Peak memory | 200076 kb |
| Host | smart-ece180b0-45e5-4fa1-ae21-ef21bf9f6151 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1826251509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.1826251509 |
| Directory | /workspace/9.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/9.uart_rx_start_bit_filter.2005435485 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 2879837354 ps |
| CPU time | 5.48 seconds |
| Started | Jun 04 12:37:25 PM PDT 24 |
| Finished | Jun 04 12:37:32 PM PDT 24 |
| Peak memory | 195940 kb |
| Host | smart-fbc530fe-b3d7-42b3-9e2e-5708f41bc08a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2005435485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.2005435485 |
| Directory | /workspace/9.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/9.uart_smoke.3306149400 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 677616740 ps |
| CPU time | 2.43 seconds |
| Started | Jun 04 12:37:27 PM PDT 24 |
| Finished | Jun 04 12:37:31 PM PDT 24 |
| Peak memory | 198972 kb |
| Host | smart-aceae9ac-e602-4e0d-b4b7-800dfd83e0f4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3306149400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_smoke.3306149400 |
| Directory | /workspace/9.uart_smoke/latest |
| Test location | /workspace/coverage/default/9.uart_stress_all.1058519634 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 464696117953 ps |
| CPU time | 991.39 seconds |
| Started | Jun 04 12:37:24 PM PDT 24 |
| Finished | Jun 04 12:53:57 PM PDT 24 |
| Peak memory | 200244 kb |
| Host | smart-142e6094-3578-490d-9234-814059784ad8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058519634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.1058519634 |
| Directory | /workspace/9.uart_stress_all/latest |
| Test location | /workspace/coverage/default/9.uart_stress_all_with_rand_reset.1342696088 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 52900158288 ps |
| CPU time | 501.17 seconds |
| Started | Jun 04 12:37:24 PM PDT 24 |
| Finished | Jun 04 12:45:45 PM PDT 24 |
| Peak memory | 225192 kb |
| Host | smart-7d8bf0a2-eff6-46d0-ad10-22e0283f6824 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342696088 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 9.uart_stress_all_with_rand_reset.1342696088 |
| Directory | /workspace/9.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/9.uart_tx_ovrd.781867286 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 7085994740 ps |
| CPU time | 23.7 seconds |
| Started | Jun 04 12:37:24 PM PDT 24 |
| Finished | Jun 04 12:37:48 PM PDT 24 |
| Peak memory | 199456 kb |
| Host | smart-fd6b48e4-23fb-421c-a59c-3f882720f9a4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=781867286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.781867286 |
| Directory | /workspace/9.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/9.uart_tx_rx.2122365665 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 30370698591 ps |
| CPU time | 15.09 seconds |
| Started | Jun 04 12:37:26 PM PDT 24 |
| Finished | Jun 04 12:37:43 PM PDT 24 |
| Peak memory | 200208 kb |
| Host | smart-2bf8a21f-9e05-41c5-ade9-da71113b6a8d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2122365665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.2122365665 |
| Directory | /workspace/9.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/90.uart_stress_all_with_rand_reset.1821654232 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 70094021424 ps |
| CPU time | 251.81 seconds |
| Started | Jun 04 12:41:23 PM PDT 24 |
| Finished | Jun 04 12:45:35 PM PDT 24 |
| Peak memory | 213652 kb |
| Host | smart-dfb78321-b192-4c36-b574-5a72015e9229 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821654232 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 90.uart_stress_all_with_rand_reset.1821654232 |
| Directory | /workspace/90.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/91.uart_fifo_reset.1033621608 |
| Short name | T1066 |
| Test name | |
| Test status | |
| Simulation time | 22179004908 ps |
| CPU time | 35.6 seconds |
| Started | Jun 04 12:41:26 PM PDT 24 |
| Finished | Jun 04 12:42:03 PM PDT 24 |
| Peak memory | 200172 kb |
| Host | smart-5853386f-1fab-40e3-9ec4-adbde5b72e87 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1033621608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.1033621608 |
| Directory | /workspace/91.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/92.uart_fifo_reset.3627202296 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 55274855039 ps |
| CPU time | 29.25 seconds |
| Started | Jun 04 12:41:25 PM PDT 24 |
| Finished | Jun 04 12:41:55 PM PDT 24 |
| Peak memory | 200192 kb |
| Host | smart-8c2ed360-01df-40aa-a00d-54afdec8bb47 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3627202296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.3627202296 |
| Directory | /workspace/92.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/92.uart_stress_all_with_rand_reset.784121899 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 68477279278 ps |
| CPU time | 386.63 seconds |
| Started | Jun 04 12:41:25 PM PDT 24 |
| Finished | Jun 04 12:47:53 PM PDT 24 |
| Peak memory | 216216 kb |
| Host | smart-fa083a78-b8da-4d64-acc0-2a6059d01f20 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784121899 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 92.uart_stress_all_with_rand_reset.784121899 |
| Directory | /workspace/92.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/93.uart_fifo_reset.2999850902 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 155121673630 ps |
| CPU time | 61.5 seconds |
| Started | Jun 04 12:41:25 PM PDT 24 |
| Finished | Jun 04 12:42:28 PM PDT 24 |
| Peak memory | 200224 kb |
| Host | smart-69288eff-b860-4891-852f-2271e6617e13 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2999850902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.2999850902 |
| Directory | /workspace/93.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/93.uart_stress_all_with_rand_reset.3217404922 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 514102905070 ps |
| CPU time | 1215.39 seconds |
| Started | Jun 04 12:41:23 PM PDT 24 |
| Finished | Jun 04 01:01:39 PM PDT 24 |
| Peak memory | 225192 kb |
| Host | smart-06342368-9916-4934-95c4-30875417db4c |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217404922 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 93.uart_stress_all_with_rand_reset.3217404922 |
| Directory | /workspace/93.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/94.uart_fifo_reset.503314945 |
| Short name | T1064 |
| Test name | |
| Test status | |
| Simulation time | 36542869217 ps |
| CPU time | 59.31 seconds |
| Started | Jun 04 12:41:31 PM PDT 24 |
| Finished | Jun 04 12:42:31 PM PDT 24 |
| Peak memory | 200168 kb |
| Host | smart-246c758b-a5e9-4f87-9404-6179722dfae2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=503314945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.503314945 |
| Directory | /workspace/94.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/94.uart_stress_all_with_rand_reset.3920168324 |
| Short name | T924 |
| Test name | |
| Test status | |
| Simulation time | 184269186744 ps |
| CPU time | 928.03 seconds |
| Started | Jun 04 12:41:25 PM PDT 24 |
| Finished | Jun 04 12:56:54 PM PDT 24 |
| Peak memory | 225112 kb |
| Host | smart-2346e9dd-5964-43cd-9f09-cbce6f90a5a3 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920168324 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 94.uart_stress_all_with_rand_reset.3920168324 |
| Directory | /workspace/94.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/95.uart_fifo_reset.2446683018 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 71848539514 ps |
| CPU time | 34.87 seconds |
| Started | Jun 04 12:41:25 PM PDT 24 |
| Finished | Jun 04 12:42:01 PM PDT 24 |
| Peak memory | 200184 kb |
| Host | smart-867d3cbe-86e7-4b5d-a76d-0367d53c093c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2446683018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.2446683018 |
| Directory | /workspace/95.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/95.uart_stress_all_with_rand_reset.4055616222 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 171757471630 ps |
| CPU time | 266.7 seconds |
| Started | Jun 04 12:41:25 PM PDT 24 |
| Finished | Jun 04 12:45:52 PM PDT 24 |
| Peak memory | 216436 kb |
| Host | smart-c54c2a6b-aa01-41b6-a527-cfb3044cfba2 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055616222 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 95.uart_stress_all_with_rand_reset.4055616222 |
| Directory | /workspace/95.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/96.uart_fifo_reset.1892182987 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 58161897490 ps |
| CPU time | 113.82 seconds |
| Started | Jun 04 12:41:27 PM PDT 24 |
| Finished | Jun 04 12:43:21 PM PDT 24 |
| Peak memory | 200260 kb |
| Host | smart-e19e2119-cc7c-4902-bce5-50f4fccdd77a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1892182987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.1892182987 |
| Directory | /workspace/96.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/96.uart_stress_all_with_rand_reset.4122356095 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 252236575429 ps |
| CPU time | 205.99 seconds |
| Started | Jun 04 12:41:32 PM PDT 24 |
| Finished | Jun 04 12:44:59 PM PDT 24 |
| Peak memory | 216656 kb |
| Host | smart-45c9a0fa-f497-4eb7-b5c7-0eca148e1ce4 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122356095 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 96.uart_stress_all_with_rand_reset.4122356095 |
| Directory | /workspace/96.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/97.uart_fifo_reset.342013269 |
| Short name | T1041 |
| Test name | |
| Test status | |
| Simulation time | 58942153103 ps |
| CPU time | 94.37 seconds |
| Started | Jun 04 12:41:32 PM PDT 24 |
| Finished | Jun 04 12:43:07 PM PDT 24 |
| Peak memory | 200164 kb |
| Host | smart-ad3513a8-abde-4ab7-938e-6facce8372fb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=342013269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.342013269 |
| Directory | /workspace/97.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/97.uart_stress_all_with_rand_reset.2992855161 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 76411343984 ps |
| CPU time | 1504.83 seconds |
| Started | Jun 04 12:41:27 PM PDT 24 |
| Finished | Jun 04 01:06:33 PM PDT 24 |
| Peak memory | 224984 kb |
| Host | smart-28898600-fcfd-40fe-ba24-162abcf5124e |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992855161 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 97.uart_stress_all_with_rand_reset.2992855161 |
| Directory | /workspace/97.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/98.uart_fifo_reset.2342060552 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 44733362110 ps |
| CPU time | 17.22 seconds |
| Started | Jun 04 12:41:23 PM PDT 24 |
| Finished | Jun 04 12:41:41 PM PDT 24 |
| Peak memory | 200172 kb |
| Host | smart-882fa518-8fe2-4cf6-b350-d7498bcceb8b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2342060552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.2342060552 |
| Directory | /workspace/98.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/98.uart_stress_all_with_rand_reset.4065823526 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 136560467350 ps |
| CPU time | 328.74 seconds |
| Started | Jun 04 12:41:24 PM PDT 24 |
| Finished | Jun 04 12:46:54 PM PDT 24 |
| Peak memory | 216680 kb |
| Host | smart-66057c0d-0fff-44fb-90f2-c7e85e52a12c |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065823526 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 98.uart_stress_all_with_rand_reset.4065823526 |
| Directory | /workspace/98.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/99.uart_fifo_reset.253562315 |
| Short name | T1027 |
| Test name | |
| Test status | |
| Simulation time | 24063844202 ps |
| CPU time | 36.37 seconds |
| Started | Jun 04 12:41:27 PM PDT 24 |
| Finished | Jun 04 12:42:04 PM PDT 24 |
| Peak memory | 200172 kb |
| Host | smart-7ebd02ed-925f-4981-bcf3-6b7156241120 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=253562315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.253562315 |
| Directory | /workspace/99.uart_fifo_reset/latest |
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