Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	114589	1			T1	10		T2	23		T3	14
all_values[1]	114589	1			T1	10		T2	23		T3	14
all_values[2]	114589	1			T1	10		T2	23		T3	14
all_values[3]	114589	1			T1	10		T2	23		T3	14
all_values[4]	114589	1			T1	10		T2	23		T3	14
all_values[5]	114589	1			T1	10		T2	23		T3	14
all_values[6]	114589	1			T1	10		T2	23		T3	14
all_values[7]	114589	1			T1	10		T2	23		T3	14

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

464031

1

T1

41

T2

94

T3

53

auto[1]

452681

1

T1

39

T2

90

T3

59

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

857079

1

T1

66

T2

163

T3

103

auto[1]

59633

1

T1

14

T2

21

T3

9

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	34922	1			T2	12		T3	6		T4	127
all_values[0]	auto[0]	auto[1]	23056	1			T1	5		T2	2		T4	27
all_values[0]	auto[1]	auto[0]	32575	1			T1	1		T3	4		T4	32
all_values[0]	auto[1]	auto[1]	24036	1			T1	4		T2	9		T3	4
all_values[1]	auto[0]	auto[0]	58274	1			T1	5		T2	2		T3	3
all_values[1]	auto[0]	auto[1]	1605	1			T1	1		T8	31		T13	3
all_values[1]	auto[1]	auto[0]	52558	1			T1	4		T2	12		T3	11
all_values[1]	auto[1]	auto[1]	2152	1			T2	9		T5	5		T120	11
all_values[2]	auto[0]	auto[0]	54111	1			T3	4		T4	145		T5	16
all_values[2]	auto[0]	auto[1]	2811	1			T3	4		T4	6		T5	2
all_values[2]	auto[1]	auto[0]	54973	1			T1	6		T2	22		T3	5
all_values[2]	auto[1]	auto[1]	2694	1			T1	4		T2	1		T3	1
all_values[3]	auto[0]	auto[0]	56560	1			T1	9		T2	21		T3	9
all_values[3]	auto[0]	auto[1]	351	1			T8	1		T12	1		T15	2
all_values[3]	auto[1]	auto[0]	57310	1			T1	1		T2	2		T3	5
all_values[3]	auto[1]	auto[1]	368	1			T10	1		T13	7		T15	2
all_values[4]	auto[0]	auto[0]	57052	1			T1	6		T2	23		T3	5
all_values[4]	auto[0]	auto[1]	471	1			T13	4		T15	11		T28	1
all_values[4]	auto[1]	auto[0]	56568	1			T1	4		T3	9		T4	35
all_values[4]	auto[1]	auto[1]	498	1			T13	7		T12	4		T14	4
all_values[5]	auto[0]	auto[0]	56339	1			T1	8		T2	11		T3	6
all_values[5]	auto[0]	auto[1]	225	1			T13	6		T15	6		T28	4
all_values[5]	auto[1]	auto[0]	57842	1			T1	2		T2	12		T3	8
all_values[5]	auto[1]	auto[1]	183	1			T13	3		T15	1		T28	1
all_values[6]	auto[0]	auto[0]	58046	1			T1	2		T2	2		T3	5
all_values[6]	auto[0]	auto[1]	213	1			T13	6		T15	7		T28	4
all_values[6]	auto[1]	auto[0]	56143	1			T1	8		T2	21		T3	9
all_values[6]	auto[1]	auto[1]	187	1			T13	1		T15	2		T42	1
all_values[7]	auto[0]	auto[0]	59616	1			T1	5		T2	21		T3	11
all_values[7]	auto[0]	auto[1]	379	1			T13	3		T16	1		T12	2
all_values[7]	auto[1]	auto[0]	54190	1			T1	5		T2	2		T3	3
all_values[7]	auto[1]	auto[1]	404	1			T13	3		T16	1		T15	3