Summary for Variable cp_dir
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_dir
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[UartTx] |
2549 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
auto[UartRx] |
2549 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_rst_pos
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
11 |
0 |
11 |
100.00 |
User Defined Bins for cp_rst_pos
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0] |
4481 |
1 |
|
|
T1 |
2 |
|
T2 |
2 |
|
T3 |
2 |
values[1] |
53 |
1 |
|
|
T16 |
1 |
|
T28 |
1 |
|
T32 |
1 |
values[2] |
45 |
1 |
|
|
T29 |
1 |
|
T110 |
1 |
|
T319 |
2 |
values[3] |
56 |
1 |
|
|
T13 |
2 |
|
T16 |
1 |
|
T15 |
2 |
values[4] |
44 |
1 |
|
|
T13 |
1 |
|
T16 |
1 |
|
T27 |
1 |
values[5] |
51 |
1 |
|
|
T33 |
1 |
|
T122 |
2 |
|
T152 |
1 |
values[6] |
57 |
1 |
|
|
T13 |
2 |
|
T16 |
1 |
|
T15 |
1 |
values[7] |
70 |
1 |
|
|
T13 |
1 |
|
T16 |
1 |
|
T28 |
1 |
values[8] |
77 |
1 |
|
|
T13 |
1 |
|
T16 |
1 |
|
T28 |
4 |
values[9] |
71 |
1 |
|
|
T16 |
1 |
|
T15 |
2 |
|
T27 |
1 |
values[10] |
61 |
1 |
|
|
T16 |
2 |
|
T15 |
1 |
|
T27 |
1 |
Summary for Cross uart_reset_cg_cc
Samples crossed: cp_dir cp_rst_pos
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
22 |
0 |
22 |
100.00 |
|
Automatically Generated Cross Bins for uart_reset_cg_cc
Bins
cp_dir | cp_rst_pos | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[UartTx] |
values[0] |
2341 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
auto[UartTx] |
values[1] |
17 |
1 |
|
|
T16 |
1 |
|
T32 |
1 |
|
T33 |
1 |
auto[UartTx] |
values[2] |
11 |
1 |
|
|
T319 |
1 |
|
T56 |
1 |
|
T115 |
1 |
auto[UartTx] |
values[3] |
19 |
1 |
|
|
T13 |
1 |
|
T15 |
1 |
|
T110 |
1 |
auto[UartTx] |
values[4] |
17 |
1 |
|
|
T13 |
1 |
|
T267 |
1 |
|
T122 |
1 |
auto[UartTx] |
values[5] |
18 |
1 |
|
|
T33 |
1 |
|
T152 |
1 |
|
T58 |
1 |
auto[UartTx] |
values[6] |
17 |
1 |
|
|
T28 |
1 |
|
T33 |
1 |
|
T320 |
1 |
auto[UartTx] |
values[7] |
17 |
1 |
|
|
T112 |
1 |
|
T321 |
1 |
|
T322 |
1 |
auto[UartTx] |
values[8] |
27 |
1 |
|
|
T13 |
1 |
|
T16 |
1 |
|
T28 |
2 |
auto[UartTx] |
values[9] |
29 |
1 |
|
|
T15 |
1 |
|
T30 |
1 |
|
T31 |
1 |
auto[UartTx] |
values[10] |
25 |
1 |
|
|
T16 |
2 |
|
T15 |
1 |
|
T27 |
1 |
auto[UartRx] |
values[0] |
2140 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
auto[UartRx] |
values[1] |
36 |
1 |
|
|
T28 |
1 |
|
T55 |
1 |
|
T319 |
1 |
auto[UartRx] |
values[2] |
34 |
1 |
|
|
T29 |
1 |
|
T110 |
1 |
|
T319 |
1 |
auto[UartRx] |
values[3] |
37 |
1 |
|
|
T13 |
1 |
|
T16 |
1 |
|
T15 |
1 |
auto[UartRx] |
values[4] |
27 |
1 |
|
|
T16 |
1 |
|
T27 |
1 |
|
T28 |
1 |
auto[UartRx] |
values[5] |
33 |
1 |
|
|
T122 |
2 |
|
T299 |
1 |
|
T169 |
1 |
auto[UartRx] |
values[6] |
40 |
1 |
|
|
T13 |
2 |
|
T16 |
1 |
|
T15 |
1 |
auto[UartRx] |
values[7] |
53 |
1 |
|
|
T13 |
1 |
|
T16 |
1 |
|
T28 |
1 |
auto[UartRx] |
values[8] |
50 |
1 |
|
|
T28 |
2 |
|
T32 |
2 |
|
T33 |
2 |
auto[UartRx] |
values[9] |
42 |
1 |
|
|
T16 |
1 |
|
T15 |
1 |
|
T27 |
1 |
auto[UartRx] |
values[10] |
36 |
1 |
|
|
T28 |
1 |
|
T30 |
1 |
|
T32 |
1 |