Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	2241	1			T2	2		T5	4		T6	12
auto[BaudRate115200]	1929	1			T1	1		T2	2		T3	4
auto[BaudRate230400]	1890	1			T1	2		T2	1		T4	3
auto[BaudRate128Kbps]	1918	1			T1	1		T2	2		T4	1
auto[BaudRate256Kbps]	2248	1			T2	3		T3	2		T4	1
auto[BaudRate1Mbps]	1795	1			T1	1		T3	1		T8	3
auto[BaudRate1p5Mbps]	1323	1			T7	1		T10	1		T11	3

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Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	1637	1			T3	7		T89	9		T35	8
freqs[25]	997	1			T8	8		T90	7		T15	80
freqs[48]	342	1			T19	15		T274	2		T135	9
freqs[50]	520	1			T6	12		T10	7		T34	7
freqs[100]	1450	1			T120	8		T118	8		T29	26

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Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	242	1			T89	1		T30	2		T265	1
auto[BaudRate9600]	freqs[25]	189	1			T8	1		T15	5		T175	1
auto[BaudRate9600]	freqs[48]	50	1			T274	1		T135	1		T119	2
auto[BaudRate9600]	freqs[50]	84	1			T6	12		T34	1		T41	1
auto[BaudRate9600]	freqs[100]	219	1			T120	1		T118	1		T29	2
auto[BaudRate115200]	freqs[24]	244	1			T3	4		T35	2		T40	1
auto[BaudRate115200]	freqs[25]	152	1			T8	1		T90	1		T15	12
auto[BaudRate115200]	freqs[48]	40	1			T19	3		T135	2		T119	2
auto[BaudRate115200]	freqs[50]	69	1			T10	1		T12	1		T323	3
auto[BaudRate115200]	freqs[100]	195	1			T120	2		T29	6		T54	1
auto[BaudRate230400]	freqs[24]	283	1			T89	2		T35	1		T14	2
auto[BaudRate230400]	freqs[25]	156	1			T8	1		T90	1		T15	12
auto[BaudRate230400]	freqs[48]	53	1			T135	1		T119	5		T192	2
auto[BaudRate230400]	freqs[50]	65	1			T10	1		T34	1		T12	2
auto[BaudRate230400]	freqs[100]	194	1			T120	3		T118	2		T281	5
auto[BaudRate128Kbps]	freqs[24]	276	1			T89	2		T35	2		T14	1
auto[BaudRate128Kbps]	freqs[25]	116	1			T8	1		T15	12		T175	1
auto[BaudRate128Kbps]	freqs[48]	37	1			T119	1		T324	1		T292	1
auto[BaudRate128Kbps]	freqs[50]	61	1			T34	1		T41	1		T323	3
auto[BaudRate128Kbps]	freqs[100]	171	1			T118	2		T29	3		T54	2
auto[BaudRate256Kbps]	freqs[24]	229	1			T3	2		T89	1		T35	1
auto[BaudRate256Kbps]	freqs[25]	184	1			T8	1		T90	3		T15	17
auto[BaudRate256Kbps]	freqs[48]	47	1			T19	3		T135	3		T119	4
auto[BaudRate256Kbps]	freqs[50]	82	1			T10	2		T34	2		T323	3
auto[BaudRate256Kbps]	freqs[100]	252	1			T120	1		T118	2		T29	6
auto[BaudRate1Mbps]	freqs[24]	245	1			T3	1		T89	2		T35	2
auto[BaudRate1Mbps]	freqs[25]	139	1			T8	3		T90	2		T15	14
auto[BaudRate1Mbps]	freqs[48]	53	1			T19	3		T135	2		T119	4
auto[BaudRate1Mbps]	freqs[50]	78	1			T10	2		T34	1		T136	1
auto[BaudRate1Mbps]	freqs[100]	216	1			T118	1		T29	7		T54	2
auto[BaudRate1p5Mbps]	freqs[25]	61	1			T15	8		T175	1		T256	1
auto[BaudRate1p5Mbps]	freqs[48]	62	1			T19	6		T274	1		T119	5
auto[BaudRate1p5Mbps]	freqs[50]	81	1			T10	1		T34	1		T136	1
auto[BaudRate1p5Mbps]	freqs[100]	203	1			T120	1		T29	2		T54	1

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded