Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	114589	1			T1	10		T2	23		T3	14
all_pins[1]	114589	1			T1	10		T2	23		T3	14
all_pins[2]	114589	1			T1	10		T2	23		T3	14
all_pins[3]	114589	1			T1	10		T2	23		T3	14
all_pins[4]	114589	1			T1	10		T2	23		T3	14
all_pins[5]	114589	1			T1	10		T2	23		T3	14
all_pins[6]	114589	1			T1	10		T2	23		T3	14
all_pins[7]	114589	1			T1	10		T2	23		T3	14

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	885233	1			T1	72		T2	165		T3	107
values[0x1]	31479	1			T1	8		T2	19		T3	5
transitions[0x0=>0x1]	30147	1			T1	8		T2	10		T3	5
transitions[0x1=>0x0]	29695	1			T1	7		T2	10		T3	4

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	90479	1			T1	6		T2	14		T3	10
all_pins[0]	values[0x1]	24110	1			T1	4		T2	9		T3	4
all_pins[0]	transitions[0x0=>0x1]	23372	1			T1	4		T3	4		T4	31
all_pins[0]	transitions[0x1=>0x0]	1412	1			T5	5		T120	11		T13	1
all_pins[1]	values[0x0]	112439	1			T1	10		T2	14		T3	14
all_pins[1]	values[0x1]	2150	1			T2	9		T5	5		T120	11
all_pins[1]	transitions[0x0=>0x1]	2019	1			T2	9		T5	5		T120	11
all_pins[1]	transitions[0x1=>0x0]	2625	1			T1	4		T2	1		T3	1
all_pins[2]	values[0x0]	111833	1			T1	6		T2	22		T3	13
all_pins[2]	values[0x1]	2756	1			T1	4		T2	1		T3	1
all_pins[2]	transitions[0x0=>0x1]	2674	1			T1	4		T2	1		T3	1
all_pins[2]	transitions[0x1=>0x0]	286	1			T13	6		T15	1		T42	1
all_pins[3]	values[0x0]	114221	1			T1	10		T2	23		T3	14
all_pins[3]	values[0x1]	368	1			T10	1		T13	7		T15	2
all_pins[3]	transitions[0x0=>0x1]	316	1			T10	1		T13	3		T15	1
all_pins[3]	transitions[0x1=>0x0]	446	1			T13	3		T12	4		T14	4
all_pins[4]	values[0x0]	114091	1			T1	10		T2	23		T3	14
all_pins[4]	values[0x1]	498	1			T13	7		T12	4		T14	4
all_pins[4]	transitions[0x0=>0x1]	419	1			T13	5		T12	4		T14	4
all_pins[4]	transitions[0x1=>0x0]	165	1			T13	1		T15	2		T28	1
all_pins[5]	values[0x0]	114345	1			T1	10		T2	23		T3	14
all_pins[5]	values[0x1]	244	1			T13	3		T15	2		T28	1
all_pins[5]	transitions[0x0=>0x1]	200	1			T13	2		T15	1		T28	1
all_pins[5]	transitions[0x1=>0x0]	905	1			T8	1		T10	2		T90	1
all_pins[6]	values[0x0]	113640	1			T1	10		T2	23		T3	14
all_pins[6]	values[0x1]	949	1			T8	1		T10	2		T90	1
all_pins[6]	transitions[0x0=>0x1]	904	1			T8	1		T10	2		T90	1
all_pins[6]	transitions[0x1=>0x0]	359	1			T13	3		T16	1		T15	2
all_pins[7]	values[0x0]	114185	1			T1	10		T2	23		T3	14
all_pins[7]	values[0x1]	404	1			T13	3		T16	1		T15	3
all_pins[7]	transitions[0x0=>0x1]	243	1			T13	3		T16	1		T15	1
all_pins[7]	transitions[0x1=>0x0]	23497	1			T1	3		T2	9		T3	3