Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::tx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::tx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	35	0	35	100.00
Crosses	66	0	66	100.00

Variables for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	33	0	33	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tx_fifo_level_cg_cc	66	0	66	100.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	7955628	1			T1	29		T2	4		T3	14
all_levels[1]	1858816	1			T2	38		T4	942		T5	14
all_levels[2]	584823	1			T4	947		T90	1		T257	40
all_levels[3]	232325	1			T1	1		T4	947		T5	13
all_levels[4]	390236	1			T4	950		T5	1		T257	31
all_levels[5]	226308	1			T4	928		T5	7		T11	1
all_levels[6]	599956	1			T1	3		T4	940		T5	4
all_levels[7]	526534	1			T2	2		T4	952		T5	5
all_levels[8]	296367	1			T4	1074		T5	1		T257	20
all_levels[9]	220130	1			T2	2		T4	786		T5	3
all_levels[10]	234312	1			T2	4		T4	787		T5	6
all_levels[11]	397157	1			T4	780		T5	5		T257	35
all_levels[12]	248481	1			T4	812		T5	6		T257	20
all_levels[13]	380491	1			T4	1079		T5	15		T257	28
all_levels[14]	240729	1			T4	1081		T5	10		T90	5
all_levels[15]	201357	1			T4	1079		T5	10		T257	26
all_levels[16]	263027	1			T4	1061		T5	21		T257	36
all_levels[17]	256897	1			T2	3		T4	1079		T90	2
all_levels[18]	189893	1			T4	1080		T257	32		T13	693
all_levels[19]	280206	1			T4	1078		T10	4		T90	4
all_levels[20]	253487	1			T4	1054		T5	2		T90	7
all_levels[21]	202497	1			T4	1078		T5	9		T11	2
all_levels[22]	408578	1			T4	1324		T5	7		T257	30
all_levels[23]	196296	1			T4	585		T5	1		T89	2
all_levels[24]	245359	1			T4	589		T5	1		T89	1
all_levels[25]	232672	1			T4	567		T5	4		T257	26
all_levels[26]	236206	1			T4	589		T5	20		T257	36
all_levels[27]	239197	1			T4	589		T257	36		T13	683
all_levels[28]	331528	1			T4	584		T5	6		T257	30
all_levels[29]	314097	1			T4	589		T5	1		T257	36
all_levels[30]	176323	1			T4	589		T5	2		T257	43
all_levels[31]	683066	1			T4	2908		T5	2		T257	819
all_levels[32]	13280482	1			T2	6		T3	2		T4	17816

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32379358

1

T1

28

T2

50

T3

10

auto[1]

4103

1

T1

5

T2

9

T3

6

---

Summary for Cross tx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	66	0	66	100.00

Automatically Generated Cross Bins for tx_fifo_level_cg_cc

Bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	7953501	1			T1	25		T2	1		T3	9
all_levels[0]	auto[1]	2127	1			T1	4		T2	3		T3	5
all_levels[1]	auto[0]	1858428	1			T2	37		T4	942		T5	14
all_levels[1]	auto[1]	388	1			T2	1		T8	1		T10	4
all_levels[2]	auto[0]	584784	1			T4	947		T90	1		T257	40
all_levels[2]	auto[1]	39	1			T42	3		T43	2		T106	1
all_levels[3]	auto[0]	232182	1			T1	1		T4	947		T5	13
all_levels[3]	auto[1]	143	1			T154	1		T140	1		T313	1
all_levels[4]	auto[0]	390211	1			T4	950		T5	1		T257	31
all_levels[4]	auto[1]	25	1			T50	1		T253	2		T32	2
all_levels[5]	auto[0]	226273	1			T4	928		T5	7		T11	1
all_levels[5]	auto[1]	35	1			T42	1		T205	1		T149	3
all_levels[6]	auto[0]	599924	1			T1	2		T4	940		T5	4
all_levels[6]	auto[1]	32	1			T1	1		T214	1		T310	1
all_levels[7]	auto[0]	526429	1			T2	2		T4	952		T5	5
all_levels[7]	auto[1]	105	1			T154	1		T325	5		T305	1
all_levels[8]	auto[0]	296335	1			T4	1074		T5	1		T257	20
all_levels[8]	auto[1]	32	1			T262	2		T135	2		T194	1
all_levels[9]	auto[0]	220107	1			T2	2		T4	786		T5	3
all_levels[9]	auto[1]	23	1			T40	1		T190	1		T245	1
all_levels[10]	auto[0]	234282	1			T2	2		T4	787		T5	6
all_levels[10]	auto[1]	30	1			T2	2		T36	2		T15	2
all_levels[11]	auto[0]	397131	1			T4	780		T5	5		T257	35
all_levels[11]	auto[1]	26	1			T195	2		T214	1		T302	1
all_levels[12]	auto[0]	248451	1			T4	812		T5	6		T257	20
all_levels[12]	auto[1]	30	1			T140	1		T108	3		T327	1
all_levels[13]	auto[0]	380454	1			T4	1079		T5	15		T257	28
all_levels[13]	auto[1]	37	1			T36	3		T30	5		T328	1
all_levels[14]	auto[0]	240711	1			T4	1081		T5	10		T90	4
all_levels[14]	auto[1]	18	1			T90	1		T13	1		T42	1
all_levels[15]	auto[0]	201167	1			T4	1079		T5	10		T257	26
all_levels[15]	auto[1]	190	1			T12	7		T15	12		T42	2
all_levels[16]	auto[0]	263003	1			T4	1061		T5	21		T257	36
all_levels[16]	auto[1]	24	1			T38	1		T43	1		T154	2
all_levels[17]	auto[0]	256866	1			T2	1		T4	1079		T90	2
all_levels[17]	auto[1]	31	1			T2	2		T30	1		T130	2
all_levels[18]	auto[0]	189876	1			T4	1080		T257	32		T13	693
all_levels[18]	auto[1]	17	1			T324	1		T207	2		T329	1
all_levels[19]	auto[0]	280191	1			T4	1078		T10	3		T90	4
all_levels[19]	auto[1]	15	1			T10	1		T294	2		T330	1
all_levels[20]	auto[0]	253461	1			T4	1054		T5	2		T90	7
all_levels[20]	auto[1]	26	1			T28	1		T189	1		T134	1
all_levels[21]	auto[0]	202481	1			T4	1078		T5	9		T11	2
all_levels[21]	auto[1]	16	1			T38	1		T205	2		T331	1
all_levels[22]	auto[0]	408560	1			T4	1324		T5	7		T257	30
all_levels[22]	auto[1]	18	1			T129	1		T146	2		T279	1
all_levels[23]	auto[0]	196285	1			T4	585		T5	1		T89	2
all_levels[23]	auto[1]	11	1			T227	1		T332	1		T333	1
all_levels[24]	auto[0]	245347	1			T4	589		T5	1		T89	1
all_levels[24]	auto[1]	12	1			T264	2		T334	1		T335	1
all_levels[25]	auto[0]	232658	1			T4	567		T5	4		T257	26
all_levels[25]	auto[1]	14	1			T36	1		T128	1		T214	2
all_levels[26]	auto[0]	236173	1			T4	589		T5	20		T257	36
all_levels[26]	auto[1]	33	1			T132	3		T227	1		T331	2
all_levels[27]	auto[0]	239187	1			T4	589		T257	36		T13	683
all_levels[27]	auto[1]	10	1			T202	1		T279	1		T336	1
all_levels[28]	auto[0]	331504	1			T4	584		T5	6		T257	30
all_levels[28]	auto[1]	24	1			T138	1		T128	1		T130	1
all_levels[29]	auto[0]	314076	1			T4	589		T5	1		T257	36
all_levels[29]	auto[1]	21	1			T13	1		T42	1		T130	1
all_levels[30]	auto[0]	176314	1			T4	589		T5	2		T257	43
all_levels[30]	auto[1]	9	1			T28	1		T121	1		T337	1
all_levels[31]	auto[0]	683045	1			T4	2908		T5	2		T257	819
all_levels[31]	auto[1]	21	1			T146	1		T338	1		T303	3
all_levels[32]	auto[0]	13279961	1			T2	5		T3	1		T4	17815
all_levels[32]	auto[1]	521	1			T2	1		T3	1		T4	1