Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.55	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	4	44	91.67

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	4	44	91.67	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	861	1			T13	11		T15	11		T42	4
all_values[1]	861	1			T13	11		T15	11		T42	4
all_values[2]	861	1			T13	11		T15	11		T42	4
all_values[3]	861	1			T13	11		T15	11		T42	4
all_values[4]	861	1			T13	11		T15	11		T42	4
all_values[5]	861	1			T13	11		T15	11		T42	4
all_values[6]	861	1			T13	11		T15	11		T42	4
all_values[7]	861	1			T13	11		T15	11		T42	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3720

1

T13

42

T15

48

T42

21

auto[1]

3168

1

T13

46

T15

40

T42

11

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2485

1

T13

19

T15

23

T42

15

auto[1]

4403

1

T13

69

T15

65

T42

17

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4056

1

T13

43

T15

50

T42

19

auto[1]

2832

1

T13

45

T15

38

T42

13

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	4	44	91.67	4
Automatically Generated Cross Bins	48	4	44	91.67	4
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	*	[auto[0]]	--	--	2
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	275	1			T13	1		T15	2		T42	1
all_values[0]	auto[0]	auto[1]	auto[1]	224	1			T13	7		T15	5		T42	1
all_values[0]	auto[1]	auto[0]	auto[1]	186	1			T15	2		T28	1		T30	1
all_values[0]	auto[1]	auto[1]	auto[1]	176	1			T13	3		T15	2		T42	2
all_values[1]	auto[0]	auto[0]	auto[0]	267	1			T13	4		T15	4		T42	2
all_values[1]	auto[0]	auto[1]	auto[0]	251	1			T13	1		T15	3		T28	2
all_values[1]	auto[1]	auto[0]	auto[1]	187	1			T13	5		T15	4		T42	2
all_values[1]	auto[1]	auto[1]	auto[1]	156	1			T13	1		T28	1		T30	2
all_values[2]	auto[0]	auto[0]	auto[0]	171	1			T13	1		T42	3		T55	1
all_values[2]	auto[0]	auto[0]	auto[1]	96	1			T13	1		T15	3		T128	1
all_values[2]	auto[0]	auto[1]	auto[0]	175	1			T13	1		T15	2		T28	1
all_values[2]	auto[0]	auto[1]	auto[1]	68	1			T13	1		T15	1		T28	3
all_values[2]	auto[1]	auto[0]	auto[1]	187	1			T13	5		T15	2		T42	1
all_values[2]	auto[1]	auto[1]	auto[1]	164	1			T13	2		T15	3		T28	2
all_values[3]	auto[0]	auto[0]	auto[0]	155	1			T13	1		T15	1		T42	2
all_values[3]	auto[0]	auto[0]	auto[1]	113	1			T15	1		T128	4		T33	2
all_values[3]	auto[0]	auto[1]	auto[0]	141	1			T13	1		T15	4		T28	3
all_values[3]	auto[0]	auto[1]	auto[1]	82	1			T13	2		T30	1		T128	1
all_values[3]	auto[1]	auto[0]	auto[1]	207	1			T13	1		T15	3		T42	2
all_values[3]	auto[1]	auto[1]	auto[1]	163	1			T13	6		T15	2		T28	2
all_values[4]	auto[0]	auto[0]	auto[0]	176	1			T15	2		T28	4		T32	4
all_values[4]	auto[0]	auto[0]	auto[1]	95	1			T15	1		T128	1		T33	1
all_values[4]	auto[0]	auto[1]	auto[0]	136	1			T15	2		T42	1		T28	2
all_values[4]	auto[0]	auto[1]	auto[1]	105	1			T13	4		T42	1		T119	1
all_values[4]	auto[1]	auto[0]	auto[1]	196	1			T13	3		T15	3		T42	1
all_values[4]	auto[1]	auto[1]	auto[1]	153	1			T13	4		T15	3		T42	1
all_values[5]	auto[0]	auto[0]	auto[0]	169	1			T13	1		T42	1		T28	1
all_values[5]	auto[0]	auto[0]	auto[1]	102	1			T13	3		T15	4		T28	2
all_values[5]	auto[0]	auto[1]	auto[0]	156	1			T15	4		T42	2		T28	2
all_values[5]	auto[0]	auto[1]	auto[1]	71	1			T119	1		T33	1		T55	1
all_values[5]	auto[1]	auto[0]	auto[1]	200	1			T13	4		T15	2		T28	2
all_values[5]	auto[1]	auto[1]	auto[1]	163	1			T13	3		T15	1		T42	1
all_values[6]	auto[0]	auto[0]	auto[0]	175	1			T13	1		T42	1		T28	2
all_values[6]	auto[0]	auto[0]	auto[1]	99	1			T13	2		T15	4		T28	1
all_values[6]	auto[0]	auto[1]	auto[0]	154	1			T13	2		T42	1		T30	1
all_values[6]	auto[0]	auto[1]	auto[1]	78	1			T15	1		T28	2		T30	1
all_values[6]	auto[1]	auto[0]	auto[1]	197	1			T13	5		T15	5		T42	1
all_values[6]	auto[1]	auto[1]	auto[1]	158	1			T13	1		T15	1		T42	1
all_values[7]	auto[0]	auto[0]	auto[0]	206	1			T13	2		T42	2		T28	1
all_values[7]	auto[0]	auto[0]	auto[1]	83	1			T13	2		T15	2		T42	1
all_values[7]	auto[0]	auto[1]	auto[0]	153	1			T13	4		T15	1		T128	4
all_values[7]	auto[0]	auto[1]	auto[1]	80	1			T13	1		T15	3		T28	1
all_values[7]	auto[1]	auto[0]	auto[1]	178	1			T15	3		T42	1		T28	3
all_values[7]	auto[1]	auto[1]	auto[1]	161	1			T13	2		T15	2		T28	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal