Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.27 99.27 97.95 100.00 98.80 100.00 99.61


Total test records in report: 1319
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T97 /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.2138936351 Jun 05 04:11:51 PM PDT 24 Jun 05 04:11:52 PM PDT 24 92361657 ps
T1254 /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.4212416294 Jun 05 04:11:46 PM PDT 24 Jun 05 04:11:49 PM PDT 24 318502825 ps
T1255 /workspace/coverage/cover_reg_top/1.uart_tl_errors.3180289818 Jun 05 04:11:37 PM PDT 24 Jun 05 04:11:40 PM PDT 24 100134598 ps
T1256 /workspace/coverage/cover_reg_top/46.uart_intr_test.2270892399 Jun 05 04:11:56 PM PDT 24 Jun 05 04:11:58 PM PDT 24 11931848 ps
T1257 /workspace/coverage/cover_reg_top/33.uart_intr_test.664413215 Jun 05 04:11:52 PM PDT 24 Jun 05 04:11:54 PM PDT 24 33895183 ps
T1258 /workspace/coverage/cover_reg_top/15.uart_csr_rw.3839359195 Jun 05 04:11:49 PM PDT 24 Jun 05 04:11:50 PM PDT 24 13770808 ps
T1259 /workspace/coverage/cover_reg_top/15.uart_intr_test.3577193247 Jun 05 04:11:51 PM PDT 24 Jun 05 04:11:52 PM PDT 24 42427923 ps
T1260 /workspace/coverage/cover_reg_top/19.uart_tl_errors.2412970095 Jun 05 04:11:53 PM PDT 24 Jun 05 04:11:55 PM PDT 24 246800338 ps
T1261 /workspace/coverage/cover_reg_top/8.uart_intr_test.2378167253 Jun 05 04:11:46 PM PDT 24 Jun 05 04:11:48 PM PDT 24 67488910 ps
T1262 /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.845747365 Jun 05 04:11:34 PM PDT 24 Jun 05 04:11:36 PM PDT 24 108151640 ps
T1263 /workspace/coverage/cover_reg_top/48.uart_intr_test.2860987063 Jun 05 04:11:53 PM PDT 24 Jun 05 04:11:55 PM PDT 24 16049324 ps
T1264 /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.203829604 Jun 05 04:11:37 PM PDT 24 Jun 05 04:11:39 PM PDT 24 28187284 ps
T1265 /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.3536127977 Jun 05 04:11:47 PM PDT 24 Jun 05 04:11:49 PM PDT 24 190147299 ps
T1266 /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.2696156852 Jun 05 04:11:46 PM PDT 24 Jun 05 04:11:48 PM PDT 24 124089749 ps
T1267 /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.465391314 Jun 05 04:11:36 PM PDT 24 Jun 05 04:11:38 PM PDT 24 133915194 ps
T1268 /workspace/coverage/cover_reg_top/10.uart_tl_errors.2534108187 Jun 05 04:11:46 PM PDT 24 Jun 05 04:11:47 PM PDT 24 89798367 ps
T1269 /workspace/coverage/cover_reg_top/18.uart_tl_errors.3350325365 Jun 05 04:11:46 PM PDT 24 Jun 05 04:11:48 PM PDT 24 356444910 ps
T1270 /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.4040809155 Jun 05 04:11:38 PM PDT 24 Jun 05 04:11:40 PM PDT 24 18426765 ps
T1271 /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.3743955082 Jun 05 04:11:40 PM PDT 24 Jun 05 04:11:42 PM PDT 24 89464217 ps
T1272 /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.1300481820 Jun 05 04:11:58 PM PDT 24 Jun 05 04:12:00 PM PDT 24 117192447 ps
T1273 /workspace/coverage/cover_reg_top/8.uart_csr_rw.3488033590 Jun 05 04:11:47 PM PDT 24 Jun 05 04:11:49 PM PDT 24 131601310 ps
T1274 /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.2140335957 Jun 05 04:11:35 PM PDT 24 Jun 05 04:11:37 PM PDT 24 126325552 ps
T1275 /workspace/coverage/cover_reg_top/3.uart_csr_rw.4219044554 Jun 05 04:11:37 PM PDT 24 Jun 05 04:11:39 PM PDT 24 14996237 ps
T1276 /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.1218483218 Jun 05 04:11:34 PM PDT 24 Jun 05 04:11:35 PM PDT 24 152830427 ps
T1277 /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.59609107 Jun 05 04:11:37 PM PDT 24 Jun 05 04:11:40 PM PDT 24 71618261 ps
T1278 /workspace/coverage/cover_reg_top/0.uart_tl_errors.2742666481 Jun 05 04:11:34 PM PDT 24 Jun 05 04:11:37 PM PDT 24 147787349 ps
T1279 /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.3605063821 Jun 05 04:11:36 PM PDT 24 Jun 05 04:11:38 PM PDT 24 85288807 ps
T1280 /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.3273384323 Jun 05 04:11:41 PM PDT 24 Jun 05 04:11:43 PM PDT 24 71217020 ps
T1281 /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.3913742907 Jun 05 04:11:37 PM PDT 24 Jun 05 04:11:38 PM PDT 24 14346768 ps
T1282 /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.2246920984 Jun 05 04:11:38 PM PDT 24 Jun 05 04:11:40 PM PDT 24 48284423 ps
T1283 /workspace/coverage/cover_reg_top/14.uart_intr_test.3905294582 Jun 05 04:11:46 PM PDT 24 Jun 05 04:11:48 PM PDT 24 20846102 ps
T80 /workspace/coverage/cover_reg_top/16.uart_csr_rw.599432237 Jun 05 04:11:51 PM PDT 24 Jun 05 04:11:52 PM PDT 24 42207331 ps
T1284 /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.3071165952 Jun 05 04:11:54 PM PDT 24 Jun 05 04:11:56 PM PDT 24 20342629 ps
T1285 /workspace/coverage/cover_reg_top/2.uart_tl_errors.2638507140 Jun 05 04:11:38 PM PDT 24 Jun 05 04:11:41 PM PDT 24 94424345 ps
T1286 /workspace/coverage/cover_reg_top/16.uart_intr_test.2082832240 Jun 05 04:11:47 PM PDT 24 Jun 05 04:11:49 PM PDT 24 19142266 ps
T1287 /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.1909052501 Jun 05 04:11:45 PM PDT 24 Jun 05 04:11:47 PM PDT 24 53318504 ps
T1288 /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.889649208 Jun 05 04:11:46 PM PDT 24 Jun 05 04:11:48 PM PDT 24 34911182 ps
T1289 /workspace/coverage/cover_reg_top/36.uart_intr_test.1979513851 Jun 05 04:11:52 PM PDT 24 Jun 05 04:11:53 PM PDT 24 119148998 ps
T1290 /workspace/coverage/cover_reg_top/25.uart_intr_test.1258416400 Jun 05 04:11:57 PM PDT 24 Jun 05 04:11:58 PM PDT 24 15261430 ps
T1291 /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.472317731 Jun 05 04:11:50 PM PDT 24 Jun 05 04:11:52 PM PDT 24 28021043 ps
T1292 /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.3666431000 Jun 05 04:11:36 PM PDT 24 Jun 05 04:11:39 PM PDT 24 56978425 ps
T1293 /workspace/coverage/cover_reg_top/49.uart_intr_test.2495903886 Jun 05 04:11:54 PM PDT 24 Jun 05 04:11:56 PM PDT 24 45235418 ps
T1294 /workspace/coverage/cover_reg_top/37.uart_intr_test.972210217 Jun 05 04:11:55 PM PDT 24 Jun 05 04:11:57 PM PDT 24 33498961 ps
T1295 /workspace/coverage/cover_reg_top/19.uart_csr_rw.2130832777 Jun 05 04:11:54 PM PDT 24 Jun 05 04:11:55 PM PDT 24 71366439 ps
T1296 /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.200839602 Jun 05 04:11:46 PM PDT 24 Jun 05 04:11:48 PM PDT 24 33975832 ps
T1297 /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.4162801666 Jun 05 04:11:53 PM PDT 24 Jun 05 04:11:54 PM PDT 24 75752487 ps
T98 /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.1353895351 Jun 05 04:11:46 PM PDT 24 Jun 05 04:11:48 PM PDT 24 120555082 ps
T1298 /workspace/coverage/cover_reg_top/22.uart_intr_test.3020006999 Jun 05 04:11:57 PM PDT 24 Jun 05 04:11:59 PM PDT 24 14966471 ps
T1299 /workspace/coverage/cover_reg_top/5.uart_csr_rw.1329583210 Jun 05 04:11:42 PM PDT 24 Jun 05 04:11:43 PM PDT 24 23961219 ps
T1300 /workspace/coverage/cover_reg_top/28.uart_intr_test.1550513865 Jun 05 04:11:53 PM PDT 24 Jun 05 04:11:54 PM PDT 24 49889823 ps
T1301 /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.380728890 Jun 05 04:11:47 PM PDT 24 Jun 05 04:11:49 PM PDT 24 22658123 ps
T1302 /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.3292440984 Jun 05 04:11:38 PM PDT 24 Jun 05 04:11:40 PM PDT 24 39754315 ps
T1303 /workspace/coverage/cover_reg_top/11.uart_tl_errors.1907876672 Jun 05 04:11:45 PM PDT 24 Jun 05 04:11:48 PM PDT 24 174187644 ps
T1304 /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.3811729689 Jun 05 04:11:39 PM PDT 24 Jun 05 04:11:40 PM PDT 24 35704002 ps
T1305 /workspace/coverage/cover_reg_top/2.uart_csr_rw.1759687860 Jun 05 04:11:37 PM PDT 24 Jun 05 04:11:39 PM PDT 24 39576372 ps
T1306 /workspace/coverage/cover_reg_top/39.uart_intr_test.1351509748 Jun 05 04:11:55 PM PDT 24 Jun 05 04:11:57 PM PDT 24 13983733 ps
T1307 /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.887842006 Jun 05 04:11:46 PM PDT 24 Jun 05 04:11:47 PM PDT 24 46433457 ps
T1308 /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.1030287240 Jun 05 04:11:43 PM PDT 24 Jun 05 04:11:44 PM PDT 24 27929017 ps
T1309 /workspace/coverage/cover_reg_top/2.uart_intr_test.1880362452 Jun 05 04:11:39 PM PDT 24 Jun 05 04:11:40 PM PDT 24 18141948 ps
T1310 /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.3929907666 Jun 05 04:11:49 PM PDT 24 Jun 05 04:11:51 PM PDT 24 42293112 ps
T1311 /workspace/coverage/cover_reg_top/30.uart_intr_test.1141477611 Jun 05 04:11:50 PM PDT 24 Jun 05 04:11:51 PM PDT 24 44786641 ps
T1312 /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.3210287250 Jun 05 04:11:37 PM PDT 24 Jun 05 04:11:39 PM PDT 24 98901358 ps
T1313 /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.2656008170 Jun 05 04:11:54 PM PDT 24 Jun 05 04:11:55 PM PDT 24 13413138 ps
T1314 /workspace/coverage/cover_reg_top/13.uart_intr_test.4248977633 Jun 05 04:11:45 PM PDT 24 Jun 05 04:11:47 PM PDT 24 27962338 ps
T1315 /workspace/coverage/cover_reg_top/14.uart_tl_errors.2983984904 Jun 05 04:11:48 PM PDT 24 Jun 05 04:11:51 PM PDT 24 394618058 ps
T1316 /workspace/coverage/cover_reg_top/17.uart_intr_test.3658846175 Jun 05 04:11:53 PM PDT 24 Jun 05 04:11:55 PM PDT 24 36995043 ps
T1317 /workspace/coverage/cover_reg_top/6.uart_csr_rw.700496008 Jun 05 04:11:46 PM PDT 24 Jun 05 04:11:48 PM PDT 24 64018913 ps
T1318 /workspace/coverage/cover_reg_top/5.uart_intr_test.360036095 Jun 05 04:11:40 PM PDT 24 Jun 05 04:11:41 PM PDT 24 42175588 ps
T1319 /workspace/coverage/cover_reg_top/7.uart_intr_test.3526192482 Jun 05 04:11:43 PM PDT 24 Jun 05 04:11:44 PM PDT 24 43068217 ps

Test location /workspace/coverage/default/180.uart_fifo_reset.3020192405
Short name T8
Test name
Test status
Simulation time 91203377960 ps
CPU time 42.5 seconds
Started Jun 05 04:18:27 PM PDT 24
Finished Jun 05 04:19:10 PM PDT 24
Peak memory 200444 kb
Host smart-f7c9378e-e6ff-4a5d-81d7-54849c301cc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020192405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.3020192405
Directory /workspace/180.uart_fifo_reset/latest

Test location /workspace/coverage/default/4.uart_stress_all_with_rand_reset.2865443903
Short name T15
Test name
Test status
Simulation time 230080119760 ps
CPU time 854.76 seconds
Started Jun 05 04:15:06 PM PDT 24
Finished Jun 05 04:29:22 PM PDT 24
Peak memory 216928 kb
Host smart-850d2dc9-ddb0-409b-9e01-30cb16f00f08
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865443903 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.uart_stress_all_with_rand_reset.2865443903
Directory /workspace/4.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.uart_stress_all_with_rand_reset.3806147803
Short name T28
Test name
Test status
Simulation time 503527892819 ps
CPU time 994.41 seconds
Started Jun 05 04:16:53 PM PDT 24
Finished Jun 05 04:33:28 PM PDT 24
Peak memory 225420 kb
Host smart-4f963143-9c2c-4cf7-925c-7ca7eb088d1e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806147803 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 41.uart_stress_all_with_rand_reset.3806147803
Directory /workspace/41.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.uart_stress_all.791083401
Short name T128
Test name
Test status
Simulation time 172705762399 ps
CPU time 361.1 seconds
Started Jun 05 04:14:57 PM PDT 24
Finished Jun 05 04:20:59 PM PDT 24
Peak memory 208776 kb
Host smart-b757790a-4911-42ba-a0fe-6560b2843d0d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791083401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.791083401
Directory /workspace/10.uart_stress_all/latest

Test location /workspace/coverage/default/33.uart_stress_all_with_rand_reset.1862093145
Short name T55
Test name
Test status
Simulation time 279435997858 ps
CPU time 920.87 seconds
Started Jun 05 04:16:18 PM PDT 24
Finished Jun 05 04:31:40 PM PDT 24
Peak memory 214492 kb
Host smart-836d8788-20a4-41b2-9149-61a37313b620
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862093145 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 33.uart_stress_all_with_rand_reset.1862093145
Directory /workspace/33.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.uart_stress_all.1179547334
Short name T144
Test name
Test status
Simulation time 430422378107 ps
CPU time 299.53 seconds
Started Jun 05 04:16:16 PM PDT 24
Finished Jun 05 04:21:16 PM PDT 24
Peak memory 200656 kb
Host smart-8d1a7e17-5d0a-4d39-a879-8477bb89290a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179547334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.1179547334
Directory /workspace/34.uart_stress_all/latest

Test location /workspace/coverage/default/27.uart_long_xfer_wo_dly.2001067019
Short name T257
Test name
Test status
Simulation time 95542558327 ps
CPU time 301.06 seconds
Started Jun 05 04:15:58 PM PDT 24
Finished Jun 05 04:21:00 PM PDT 24
Peak memory 200448 kb
Host smart-558b3851-d0d7-435f-9c5d-770d03af3a7d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2001067019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.2001067019
Directory /workspace/27.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/1.uart_sec_cm.1727248400
Short name T24
Test name
Test status
Simulation time 87911643 ps
CPU time 0.83 seconds
Started Jun 05 04:14:45 PM PDT 24
Finished Jun 05 04:14:46 PM PDT 24
Peak memory 218688 kb
Host smart-0e8b1bec-911a-469d-8b4d-5599f231a5af
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727248400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.1727248400
Directory /workspace/1.uart_sec_cm/latest

Test location /workspace/coverage/default/12.uart_stress_all_with_rand_reset.2786063165
Short name T31
Test name
Test status
Simulation time 577105950590 ps
CPU time 761.69 seconds
Started Jun 05 04:15:10 PM PDT 24
Finished Jun 05 04:27:53 PM PDT 24
Peak memory 225196 kb
Host smart-1b92704e-7377-4c16-bd6f-e78067c1ee7b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786063165 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 12.uart_stress_all_with_rand_reset.2786063165
Directory /workspace/12.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.uart_fifo_reset.1191222715
Short name T2
Test name
Test status
Simulation time 166413804265 ps
CPU time 30.53 seconds
Started Jun 05 04:18:25 PM PDT 24
Finished Jun 05 04:18:56 PM PDT 24
Peak memory 200436 kb
Host smart-75b21778-e970-431b-ad19-b9e4099496c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191222715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.1191222715
Directory /workspace/170.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_stress_all.661707264
Short name T151
Test name
Test status
Simulation time 346626799566 ps
CPU time 161.54 seconds
Started Jun 05 04:14:46 PM PDT 24
Finished Jun 05 04:17:28 PM PDT 24
Peak memory 200316 kb
Host smart-ebc4dd10-a45c-4256-8665-ca7cc8856726
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661707264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.661707264
Directory /workspace/6.uart_stress_all/latest

Test location /workspace/coverage/default/11.uart_stress_all.2869092194
Short name T281
Test name
Test status
Simulation time 74360687957 ps
CPU time 783.45 seconds
Started Jun 05 04:15:11 PM PDT 24
Finished Jun 05 04:28:16 PM PDT 24
Peak memory 200416 kb
Host smart-08aee129-ed00-44fe-ad3b-b7f977737736
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869092194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.2869092194
Directory /workspace/11.uart_stress_all/latest

Test location /workspace/coverage/default/76.uart_stress_all_with_rand_reset.3291775164
Short name T13
Test name
Test status
Simulation time 291468317841 ps
CPU time 454.2 seconds
Started Jun 05 04:17:44 PM PDT 24
Finished Jun 05 04:25:18 PM PDT 24
Peak memory 225232 kb
Host smart-10262409-ebe8-40ec-ab9d-b405f9cfb6d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291775164 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 76.uart_stress_all_with_rand_reset.3291775164
Directory /workspace/76.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/296.uart_fifo_reset.1494531091
Short name T140
Test name
Test status
Simulation time 91137236954 ps
CPU time 101.25 seconds
Started Jun 05 04:19:21 PM PDT 24
Finished Jun 05 04:21:03 PM PDT 24
Peak memory 200340 kb
Host smart-fbdc7e71-d936-47d2-bd71-a21f4fe9f1bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494531091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.1494531091
Directory /workspace/296.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.791203552
Short name T93
Test name
Test status
Simulation time 72431925 ps
CPU time 1.36 seconds
Started Jun 05 04:11:57 PM PDT 24
Finished Jun 05 04:11:59 PM PDT 24
Peak memory 199640 kb
Host smart-05f2b5f5-3082-4c3a-9669-2dade59056bf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791203552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.791203552
Directory /workspace/17.uart_tl_intg_err/latest

Test location /workspace/coverage/default/15.uart_stress_all_with_rand_reset.4282603200
Short name T32
Test name
Test status
Simulation time 20774805922 ps
CPU time 376.92 seconds
Started Jun 05 04:15:19 PM PDT 24
Finished Jun 05 04:21:36 PM PDT 24
Peak memory 216796 kb
Host smart-c97309be-4735-45ce-bec4-9d8c4f4caa32
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282603200 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 15.uart_stress_all_with_rand_reset.4282603200
Directory /workspace/15.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.uart_stress_all.3429517602
Short name T42
Test name
Test status
Simulation time 397819388039 ps
CPU time 702.79 seconds
Started Jun 05 04:15:52 PM PDT 24
Finished Jun 05 04:27:35 PM PDT 24
Peak memory 200476 kb
Host smart-a81c2093-500f-4690-a413-ef60e253ceb9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429517602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.3429517602
Directory /workspace/26.uart_stress_all/latest

Test location /workspace/coverage/default/20.uart_alert_test.3560744206
Short name T370
Test name
Test status
Simulation time 53585332 ps
CPU time 0.55 seconds
Started Jun 05 04:15:20 PM PDT 24
Finished Jun 05 04:15:21 PM PDT 24
Peak memory 195788 kb
Host smart-9b99358f-5606-4943-9859-66bee9973997
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560744206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.3560744206
Directory /workspace/20.uart_alert_test/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_rw.1852476978
Short name T64
Test name
Test status
Simulation time 68025209 ps
CPU time 0.61 seconds
Started Jun 05 04:11:53 PM PDT 24
Finished Jun 05 04:11:55 PM PDT 24
Peak memory 195744 kb
Host smart-39bb10bf-c6ef-40d6-9101-51fc69306495
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852476978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.1852476978
Directory /workspace/18.uart_csr_rw/latest

Test location /workspace/coverage/default/36.uart_fifo_overflow.3373514239
Short name T269
Test name
Test status
Simulation time 133678445525 ps
CPU time 93.85 seconds
Started Jun 05 04:16:25 PM PDT 24
Finished Jun 05 04:18:00 PM PDT 24
Peak memory 200368 kb
Host smart-37d6fa29-a70b-4556-bec8-7ee0a345b37a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373514239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.3373514239
Directory /workspace/36.uart_fifo_overflow/latest

Test location /workspace/coverage/default/15.uart_stress_all.1056763814
Short name T297
Test name
Test status
Simulation time 410171554195 ps
CPU time 450.42 seconds
Started Jun 05 04:15:06 PM PDT 24
Finished Jun 05 04:22:38 PM PDT 24
Peak memory 200300 kb
Host smart-8d12c01b-6fc7-44c9-b889-8d588aa2bb2e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056763814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.1056763814
Directory /workspace/15.uart_stress_all/latest

Test location /workspace/coverage/default/87.uart_stress_all_with_rand_reset.718691949
Short name T58
Test name
Test status
Simulation time 51290461134 ps
CPU time 522.95 seconds
Started Jun 05 04:17:50 PM PDT 24
Finished Jun 05 04:26:34 PM PDT 24
Peak memory 217196 kb
Host smart-652cad20-f5ef-45d4-ac0c-2a4348ba26ed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718691949 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 87.uart_stress_all_with_rand_reset.718691949
Directory /workspace/87.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.uart_stress_all.1288225646
Short name T124
Test name
Test status
Simulation time 178913107377 ps
CPU time 297.25 seconds
Started Jun 05 04:16:46 PM PDT 24
Finished Jun 05 04:21:44 PM PDT 24
Peak memory 200400 kb
Host smart-8f5e8921-4dc5-49dc-afeb-084ece821a72
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288225646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.1288225646
Directory /workspace/38.uart_stress_all/latest

Test location /workspace/coverage/default/11.uart_fifo_reset.2136171470
Short name T135
Test name
Test status
Simulation time 113555169109 ps
CPU time 108.64 seconds
Started Jun 05 04:15:10 PM PDT 24
Finished Jun 05 04:17:01 PM PDT 24
Peak memory 200400 kb
Host smart-9507b5ae-5c48-4a73-bae7-1a043c34db39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136171470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.2136171470
Directory /workspace/11.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_stress_all_with_rand_reset.974862915
Short name T122
Test name
Test status
Simulation time 135848767108 ps
CPU time 1219.26 seconds
Started Jun 05 04:15:30 PM PDT 24
Finished Jun 05 04:35:50 PM PDT 24
Peak memory 225232 kb
Host smart-bef78a10-5e5d-4592-8bc9-33144ce5da3d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974862915 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 22.uart_stress_all_with_rand_reset.974862915
Directory /workspace/22.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.uart_stress_all_with_rand_reset.2481053428
Short name T177
Test name
Test status
Simulation time 1712322170644 ps
CPU time 2053.72 seconds
Started Jun 05 04:16:46 PM PDT 24
Finished Jun 05 04:51:00 PM PDT 24
Peak memory 225080 kb
Host smart-18d480fd-8ccf-4b56-8e96-205da26d18f1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481053428 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 40.uart_stress_all_with_rand_reset.2481053428
Directory /workspace/40.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.uart_stress_all.3625624516
Short name T141
Test name
Test status
Simulation time 106547792547 ps
CPU time 204.8 seconds
Started Jun 05 04:15:14 PM PDT 24
Finished Jun 05 04:18:39 PM PDT 24
Peak memory 200420 kb
Host smart-869bffb9-8019-4cd7-8ea4-215d2198a893
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625624516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.3625624516
Directory /workspace/16.uart_stress_all/latest

Test location /workspace/coverage/default/108.uart_fifo_reset.407988390
Short name T132
Test name
Test status
Simulation time 45760559438 ps
CPU time 24.27 seconds
Started Jun 05 04:18:04 PM PDT 24
Finished Jun 05 04:18:29 PM PDT 24
Peak memory 200440 kb
Host smart-bec75cf5-a623-4b1c-a5f7-fdf399227b1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407988390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.407988390
Directory /workspace/108.uart_fifo_reset/latest

Test location /workspace/coverage/default/163.uart_fifo_reset.3475982950
Short name T279
Test name
Test status
Simulation time 187844868072 ps
CPU time 116.8 seconds
Started Jun 05 04:18:19 PM PDT 24
Finished Jun 05 04:20:17 PM PDT 24
Peak memory 200384 kb
Host smart-499a1806-e775-4d0a-abe6-eeaf3ceec5c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475982950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.3475982950
Directory /workspace/163.uart_fifo_reset/latest

Test location /workspace/coverage/default/223.uart_fifo_reset.1322253696
Short name T174
Test name
Test status
Simulation time 107823589914 ps
CPU time 45.72 seconds
Started Jun 05 04:18:45 PM PDT 24
Finished Jun 05 04:19:32 PM PDT 24
Peak memory 200392 kb
Host smart-ee9f2410-51eb-480d-9799-a3db68de23eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322253696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.1322253696
Directory /workspace/223.uart_fifo_reset/latest

Test location /workspace/coverage/default/235.uart_fifo_reset.1702642482
Short name T38
Test name
Test status
Simulation time 41501758887 ps
CPU time 70.09 seconds
Started Jun 05 04:18:52 PM PDT 24
Finished Jun 05 04:20:03 PM PDT 24
Peak memory 200428 kb
Host smart-842c1715-a5b6-41cf-9937-558abc3ff123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702642482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.1702642482
Directory /workspace/235.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.1353895351
Short name T98
Test name
Test status
Simulation time 120555082 ps
CPU time 1.2 seconds
Started Jun 05 04:11:46 PM PDT 24
Finished Jun 05 04:11:48 PM PDT 24
Peak memory 199608 kb
Host smart-9d16047b-0f74-4c50-90d5-e858bd651387
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353895351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.1353895351
Directory /workspace/13.uart_tl_intg_err/latest

Test location /workspace/coverage/default/211.uart_fifo_reset.3766694505
Short name T193
Test name
Test status
Simulation time 225472548677 ps
CPU time 26.59 seconds
Started Jun 05 04:18:45 PM PDT 24
Finished Jun 05 04:19:12 PM PDT 24
Peak memory 200464 kb
Host smart-92a9fd82-39e6-4f06-8a1d-95c555b9f4f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766694505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.3766694505
Directory /workspace/211.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_stress_all.2497526458
Short name T119
Test name
Test status
Simulation time 108359125732 ps
CPU time 84.06 seconds
Started Jun 05 04:16:00 PM PDT 24
Finished Jun 05 04:17:25 PM PDT 24
Peak memory 200456 kb
Host smart-3f3421ee-cb2e-4b9c-9b9a-a3ead65cef5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497526458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.2497526458
Directory /workspace/30.uart_stress_all/latest

Test location /workspace/coverage/default/122.uart_fifo_reset.2592411257
Short name T804
Test name
Test status
Simulation time 63543443844 ps
CPU time 58.57 seconds
Started Jun 05 04:18:11 PM PDT 24
Finished Jun 05 04:19:10 PM PDT 24
Peak memory 200436 kb
Host smart-5a54f10f-1c08-458e-bf21-cdf8f7ba8820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592411257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.2592411257
Directory /workspace/122.uart_fifo_reset/latest

Test location /workspace/coverage/default/133.uart_fifo_reset.2066358843
Short name T236
Test name
Test status
Simulation time 151047495243 ps
CPU time 64.31 seconds
Started Jun 05 04:18:12 PM PDT 24
Finished Jun 05 04:19:17 PM PDT 24
Peak memory 200364 kb
Host smart-f1f7bec4-1102-41b7-9d6f-e3c3c9518ef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066358843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.2066358843
Directory /workspace/133.uart_fifo_reset/latest

Test location /workspace/coverage/default/148.uart_fifo_reset.3915600103
Short name T258
Test name
Test status
Simulation time 93650039026 ps
CPU time 83.37 seconds
Started Jun 05 04:18:19 PM PDT 24
Finished Jun 05 04:19:43 PM PDT 24
Peak memory 200368 kb
Host smart-799b6c91-f482-4fac-addc-25e7d106198b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915600103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.3915600103
Directory /workspace/148.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_stress_all_with_rand_reset.2645347287
Short name T267
Test name
Test status
Simulation time 214313952763 ps
CPU time 508.51 seconds
Started Jun 05 04:15:40 PM PDT 24
Finished Jun 05 04:24:10 PM PDT 24
Peak memory 225308 kb
Host smart-6f9bb4b9-682b-4a27-bcc8-bbf26515799b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645347287 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 17.uart_stress_all_with_rand_reset.2645347287
Directory /workspace/17.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/172.uart_fifo_reset.393929286
Short name T164
Test name
Test status
Simulation time 19814090551 ps
CPU time 14.35 seconds
Started Jun 05 04:18:28 PM PDT 24
Finished Jun 05 04:18:43 PM PDT 24
Peak memory 200160 kb
Host smart-e95fd16a-0df1-4e47-829a-e33db77acc6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393929286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.393929286
Directory /workspace/172.uart_fifo_reset/latest

Test location /workspace/coverage/default/238.uart_fifo_reset.2570265920
Short name T36
Test name
Test status
Simulation time 65839165551 ps
CPU time 149.88 seconds
Started Jun 05 04:18:50 PM PDT 24
Finished Jun 05 04:21:20 PM PDT 24
Peak memory 200360 kb
Host smart-3e36988e-8a22-485a-be8e-4914731706b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570265920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.2570265920
Directory /workspace/238.uart_fifo_reset/latest

Test location /workspace/coverage/default/49.uart_stress_all_with_rand_reset.2518843107
Short name T561
Test name
Test status
Simulation time 453572213338 ps
CPU time 1168.49 seconds
Started Jun 05 04:17:26 PM PDT 24
Finished Jun 05 04:36:55 PM PDT 24
Peak memory 216716 kb
Host smart-4ddc2124-4933-4240-a1fd-3f6233f4ff5b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518843107 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 49.uart_stress_all_with_rand_reset.2518843107
Directory /workspace/49.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.uart_fifo_reset.1918287886
Short name T170
Test name
Test status
Simulation time 80800214164 ps
CPU time 39 seconds
Started Jun 05 04:14:57 PM PDT 24
Finished Jun 05 04:15:36 PM PDT 24
Peak memory 200432 kb
Host smart-1f91afa1-0cf3-42ae-93dd-341bb39443b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918287886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.1918287886
Directory /workspace/1.uart_fifo_reset/latest

Test location /workspace/coverage/default/110.uart_fifo_reset.1126788757
Short name T187
Test name
Test status
Simulation time 97643993407 ps
CPU time 143.34 seconds
Started Jun 05 04:18:03 PM PDT 24
Finished Jun 05 04:20:27 PM PDT 24
Peak memory 200464 kb
Host smart-f606afcb-8276-4b12-bade-38f7a3132f22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126788757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.1126788757
Directory /workspace/110.uart_fifo_reset/latest

Test location /workspace/coverage/default/174.uart_fifo_reset.2100587145
Short name T130
Test name
Test status
Simulation time 40506197779 ps
CPU time 63.69 seconds
Started Jun 05 04:18:26 PM PDT 24
Finished Jun 05 04:19:30 PM PDT 24
Peak memory 200444 kb
Host smart-04490936-9236-400a-bf6d-d2eda3410413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100587145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.2100587145
Directory /workspace/174.uart_fifo_reset/latest

Test location /workspace/coverage/default/247.uart_fifo_reset.1625575026
Short name T200
Test name
Test status
Simulation time 257545593168 ps
CPU time 143.52 seconds
Started Jun 05 04:18:53 PM PDT 24
Finished Jun 05 04:21:18 PM PDT 24
Peak memory 200376 kb
Host smart-8a0c5bb0-1879-4d22-9c5d-aa5b23d069de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625575026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.1625575026
Directory /workspace/247.uart_fifo_reset/latest

Test location /workspace/coverage/default/273.uart_fifo_reset.989530191
Short name T180
Test name
Test status
Simulation time 91235901913 ps
CPU time 75.93 seconds
Started Jun 05 04:19:19 PM PDT 24
Finished Jun 05 04:20:36 PM PDT 24
Peak memory 200464 kb
Host smart-0970aab1-2fae-491d-a2fa-8cf088427dcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989530191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.989530191
Directory /workspace/273.uart_fifo_reset/latest

Test location /workspace/coverage/default/287.uart_fifo_reset.3642895125
Short name T172
Test name
Test status
Simulation time 41226744730 ps
CPU time 27.79 seconds
Started Jun 05 04:19:11 PM PDT 24
Finished Jun 05 04:19:39 PM PDT 24
Peak memory 200376 kb
Host smart-e362c298-ee6f-4296-81d9-758bd5b284e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642895125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.3642895125
Directory /workspace/287.uart_fifo_reset/latest

Test location /workspace/coverage/default/121.uart_fifo_reset.3867445338
Short name T264
Test name
Test status
Simulation time 28049631015 ps
CPU time 38.12 seconds
Started Jun 05 04:18:13 PM PDT 24
Finished Jun 05 04:18:52 PM PDT 24
Peak memory 200576 kb
Host smart-3bf5fd46-2890-44ba-b25f-2a0f44cec0fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867445338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.3867445338
Directory /workspace/121.uart_fifo_reset/latest

Test location /workspace/coverage/default/129.uart_fifo_reset.517413887
Short name T245
Test name
Test status
Simulation time 60610755206 ps
CPU time 104.22 seconds
Started Jun 05 04:18:10 PM PDT 24
Finished Jun 05 04:19:55 PM PDT 24
Peak memory 200448 kb
Host smart-9c3583e6-a94a-4322-8317-5f16ce6f6f35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517413887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.517413887
Directory /workspace/129.uart_fifo_reset/latest

Test location /workspace/coverage/default/132.uart_fifo_reset.3765452949
Short name T3
Test name
Test status
Simulation time 21843341865 ps
CPU time 10.86 seconds
Started Jun 05 04:18:09 PM PDT 24
Finished Jun 05 04:18:21 PM PDT 24
Peak memory 200408 kb
Host smart-39d2949c-d949-46bb-8d8f-5b68c51ae77d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765452949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.3765452949
Directory /workspace/132.uart_fifo_reset/latest

Test location /workspace/coverage/default/179.uart_fifo_reset.4015463402
Short name T224
Test name
Test status
Simulation time 133386447821 ps
CPU time 70.16 seconds
Started Jun 05 04:18:26 PM PDT 24
Finished Jun 05 04:19:37 PM PDT 24
Peak memory 200332 kb
Host smart-5b5a8ea4-967d-40e9-9e6d-679522e51949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015463402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.4015463402
Directory /workspace/179.uart_fifo_reset/latest

Test location /workspace/coverage/default/215.uart_fifo_reset.3438821199
Short name T189
Test name
Test status
Simulation time 15980997595 ps
CPU time 28.29 seconds
Started Jun 05 04:18:46 PM PDT 24
Finished Jun 05 04:19:16 PM PDT 24
Peak memory 200464 kb
Host smart-d4979ea9-e028-4e72-85f2-a06e187394b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438821199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.3438821199
Directory /workspace/215.uart_fifo_reset/latest

Test location /workspace/coverage/default/240.uart_fifo_reset.3381668746
Short name T244
Test name
Test status
Simulation time 29510282829 ps
CPU time 12.61 seconds
Started Jun 05 04:18:51 PM PDT 24
Finished Jun 05 04:19:05 PM PDT 24
Peak memory 200468 kb
Host smart-8df356b3-a2c7-48c3-a3e0-4f219e1b92b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381668746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.3381668746
Directory /workspace/240.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_fifo_reset.3061499927
Short name T129
Test name
Test status
Simulation time 21818774956 ps
CPU time 21.71 seconds
Started Jun 05 04:15:52 PM PDT 24
Finished Jun 05 04:16:14 PM PDT 24
Peak memory 200428 kb
Host smart-7d319606-14a9-4aa6-929d-e8a0d1c65083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061499927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.3061499927
Directory /workspace/25.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.768549316
Short name T127
Test name
Test status
Simulation time 94254861 ps
CPU time 0.95 seconds
Started Jun 05 04:11:51 PM PDT 24
Finished Jun 05 04:11:53 PM PDT 24
Peak memory 199240 kb
Host smart-981036f3-85cb-4229-9a35-e27797b0f07c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768549316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.768549316
Directory /workspace/14.uart_tl_intg_err/latest

Test location /workspace/coverage/default/107.uart_fifo_reset.1022150923
Short name T230
Test name
Test status
Simulation time 21884956640 ps
CPU time 7.11 seconds
Started Jun 05 04:18:02 PM PDT 24
Finished Jun 05 04:18:10 PM PDT 24
Peak memory 200380 kb
Host smart-22ed0e98-95f6-4e23-9764-577ebb986ea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022150923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.1022150923
Directory /workspace/107.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_fifo_overflow.255984105
Short name T282
Test name
Test status
Simulation time 158501831028 ps
CPU time 95.18 seconds
Started Jun 05 04:15:06 PM PDT 24
Finished Jun 05 04:16:42 PM PDT 24
Peak memory 200304 kb
Host smart-d31ba845-4b8f-4af5-955c-4ef49abfc890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255984105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.255984105
Directory /workspace/12.uart_fifo_overflow/latest

Test location /workspace/coverage/default/12.uart_fifo_reset.1603763826
Short name T138
Test name
Test status
Simulation time 31004734042 ps
CPU time 43.97 seconds
Started Jun 05 04:15:05 PM PDT 24
Finished Jun 05 04:15:50 PM PDT 24
Peak memory 200288 kb
Host smart-5ac408f9-02c7-43a7-ac64-2739a7ecb57a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603763826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.1603763826
Directory /workspace/12.uart_fifo_reset/latest

Test location /workspace/coverage/default/124.uart_fifo_reset.3957943803
Short name T229
Test name
Test status
Simulation time 143884630146 ps
CPU time 57.07 seconds
Started Jun 05 04:18:10 PM PDT 24
Finished Jun 05 04:19:08 PM PDT 24
Peak memory 200368 kb
Host smart-dd25aee6-c507-45ec-8efa-1b44e1c6fd20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957943803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.3957943803
Directory /workspace/124.uart_fifo_reset/latest

Test location /workspace/coverage/default/125.uart_fifo_reset.1683414327
Short name T221
Test name
Test status
Simulation time 85924370585 ps
CPU time 45.4 seconds
Started Jun 05 04:18:10 PM PDT 24
Finished Jun 05 04:18:56 PM PDT 24
Peak memory 200404 kb
Host smart-90a39cd9-6b54-4a5b-8a30-7bff61dd8c46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683414327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.1683414327
Directory /workspace/125.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_smoke.3276419147
Short name T104
Test name
Test status
Simulation time 5555967077 ps
CPU time 18.87 seconds
Started Jun 05 04:15:27 PM PDT 24
Finished Jun 05 04:15:46 PM PDT 24
Peak memory 200352 kb
Host smart-91b35976-7947-41ef-9474-c7f3deaff916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276419147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_smoke.3276419147
Directory /workspace/13.uart_smoke/latest

Test location /workspace/coverage/default/13.uart_stress_all.3943437071
Short name T858
Test name
Test status
Simulation time 745402787435 ps
CPU time 648.73 seconds
Started Jun 05 04:15:11 PM PDT 24
Finished Jun 05 04:26:01 PM PDT 24
Peak memory 200460 kb
Host smart-7c305a20-246f-4305-bc2a-4bcca548454e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943437071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.3943437071
Directory /workspace/13.uart_stress_all/latest

Test location /workspace/coverage/default/140.uart_fifo_reset.2909829462
Short name T251
Test name
Test status
Simulation time 37383642189 ps
CPU time 19.51 seconds
Started Jun 05 04:18:10 PM PDT 24
Finished Jun 05 04:18:31 PM PDT 24
Peak memory 200364 kb
Host smart-87b049ec-fa77-4201-875c-80ae9f8fba82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909829462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.2909829462
Directory /workspace/140.uart_fifo_reset/latest

Test location /workspace/coverage/default/143.uart_fifo_reset.453894689
Short name T239
Test name
Test status
Simulation time 69236576841 ps
CPU time 48.15 seconds
Started Jun 05 04:18:10 PM PDT 24
Finished Jun 05 04:18:59 PM PDT 24
Peak memory 200376 kb
Host smart-22dc22d2-ad60-40ac-8e43-02ac15450e43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453894689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.453894689
Directory /workspace/143.uart_fifo_reset/latest

Test location /workspace/coverage/default/205.uart_fifo_reset.3651564864
Short name T235
Test name
Test status
Simulation time 17691958502 ps
CPU time 30.43 seconds
Started Jun 05 04:18:39 PM PDT 24
Finished Jun 05 04:19:10 PM PDT 24
Peak memory 200468 kb
Host smart-f3f19eae-bdfa-43aa-86e3-e47537fa71a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651564864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.3651564864
Directory /workspace/205.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_fifo_reset.2299318372
Short name T248
Test name
Test status
Simulation time 134296388308 ps
CPU time 360.33 seconds
Started Jun 05 04:15:27 PM PDT 24
Finished Jun 05 04:21:28 PM PDT 24
Peak memory 200360 kb
Host smart-536e382f-3851-4bc8-b05e-6345f21e3987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299318372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.2299318372
Directory /workspace/21.uart_fifo_reset/latest

Test location /workspace/coverage/default/231.uart_fifo_reset.2765484089
Short name T207
Test name
Test status
Simulation time 112925089395 ps
CPU time 176.18 seconds
Started Jun 05 04:18:48 PM PDT 24
Finished Jun 05 04:21:45 PM PDT 24
Peak memory 200468 kb
Host smart-f52ba271-fed2-4691-a9fd-c778870febee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765484089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.2765484089
Directory /workspace/231.uart_fifo_reset/latest

Test location /workspace/coverage/default/239.uart_fifo_reset.4024759380
Short name T216
Test name
Test status
Simulation time 55867458829 ps
CPU time 64.58 seconds
Started Jun 05 04:18:51 PM PDT 24
Finished Jun 05 04:19:56 PM PDT 24
Peak memory 200408 kb
Host smart-46e30a79-fcff-459b-af06-5729428878b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024759380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.4024759380
Directory /workspace/239.uart_fifo_reset/latest

Test location /workspace/coverage/default/272.uart_fifo_reset.3226307349
Short name T252
Test name
Test status
Simulation time 169640571159 ps
CPU time 23.52 seconds
Started Jun 05 04:19:10 PM PDT 24
Finished Jun 05 04:19:34 PM PDT 24
Peak memory 200520 kb
Host smart-5657af92-0eaf-4ec8-80e5-3ea8443004b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226307349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.3226307349
Directory /workspace/272.uart_fifo_reset/latest

Test location /workspace/coverage/default/47.uart_fifo_reset.3969192678
Short name T223
Test name
Test status
Simulation time 47748530949 ps
CPU time 19.75 seconds
Started Jun 05 04:17:16 PM PDT 24
Finished Jun 05 04:17:37 PM PDT 24
Peak memory 200396 kb
Host smart-a28c2bf5-d314-49b4-9bb1-c164a977a8f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969192678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.3969192678
Directory /workspace/47.uart_fifo_reset/latest

Test location /workspace/coverage/default/90.uart_fifo_reset.3454419025
Short name T242
Test name
Test status
Simulation time 15786694395 ps
CPU time 14.15 seconds
Started Jun 05 04:17:51 PM PDT 24
Finished Jun 05 04:18:06 PM PDT 24
Peak memory 200448 kb
Host smart-a599d4c3-8923-4f8b-affb-85359f785cae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454419025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.3454419025
Directory /workspace/90.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.4091126687
Short name T1208
Test name
Test status
Simulation time 52202581 ps
CPU time 0.75 seconds
Started Jun 05 04:11:34 PM PDT 24
Finished Jun 05 04:11:35 PM PDT 24
Peak memory 196708 kb
Host smart-b9bd2bf6-874a-4a32-9574-e120e32cda12
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091126687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.4091126687
Directory /workspace/0.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.465391314
Short name T1267
Test name
Test status
Simulation time 133915194 ps
CPU time 1.57 seconds
Started Jun 05 04:11:36 PM PDT 24
Finished Jun 05 04:11:38 PM PDT 24
Peak memory 197740 kb
Host smart-35a6bfaf-4e01-4e5b-9eff-3589154fb4a2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465391314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.465391314
Directory /workspace/0.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.188698243
Short name T1206
Test name
Test status
Simulation time 34677151 ps
CPU time 0.58 seconds
Started Jun 05 04:11:36 PM PDT 24
Finished Jun 05 04:11:37 PM PDT 24
Peak memory 195600 kb
Host smart-94b6b1ed-4cc4-4122-a801-c4d1998ad834
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188698243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.188698243
Directory /workspace/0.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.103664996
Short name T1209
Test name
Test status
Simulation time 70826933 ps
CPU time 0.96 seconds
Started Jun 05 04:11:36 PM PDT 24
Finished Jun 05 04:11:39 PM PDT 24
Peak memory 200128 kb
Host smart-42b96e90-4581-43d7-9795-514d94733201
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103664996 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.103664996
Directory /workspace/0.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_rw.2239274359
Short name T1226
Test name
Test status
Simulation time 29442802 ps
CPU time 0.55 seconds
Started Jun 05 04:11:36 PM PDT 24
Finished Jun 05 04:11:37 PM PDT 24
Peak memory 195716 kb
Host smart-c1c31d11-f764-49fd-bed1-3c52631c3a70
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239274359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.2239274359
Directory /workspace/0.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.uart_intr_test.3064143514
Short name T1199
Test name
Test status
Simulation time 54424221 ps
CPU time 0.59 seconds
Started Jun 05 04:11:35 PM PDT 24
Finished Jun 05 04:11:36 PM PDT 24
Peak memory 194680 kb
Host smart-8f328189-5906-4afe-9e42-f3624928f7ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064143514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.3064143514
Directory /workspace/0.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.4281419891
Short name T84
Test name
Test status
Simulation time 54457509 ps
CPU time 0.75 seconds
Started Jun 05 04:11:37 PM PDT 24
Finished Jun 05 04:11:39 PM PDT 24
Peak memory 196808 kb
Host smart-9ab95427-5b87-4a31-bfc5-a42bde0c3e50
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281419891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr
_outstanding.4281419891
Directory /workspace/0.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_errors.2742666481
Short name T1278
Test name
Test status
Simulation time 147787349 ps
CPU time 2.01 seconds
Started Jun 05 04:11:34 PM PDT 24
Finished Jun 05 04:11:37 PM PDT 24
Peak memory 200372 kb
Host smart-badfc41c-2096-442b-b687-d2626dc00252
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742666481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.2742666481
Directory /workspace/0.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.845747365
Short name T1262
Test name
Test status
Simulation time 108151640 ps
CPU time 0.93 seconds
Started Jun 05 04:11:34 PM PDT 24
Finished Jun 05 04:11:36 PM PDT 24
Peak memory 199176 kb
Host smart-95bd96be-d148-4c07-ab96-d5b0ad118ab3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845747365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.845747365
Directory /workspace/0.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.2887177911
Short name T1186
Test name
Test status
Simulation time 62714664 ps
CPU time 0.78 seconds
Started Jun 05 04:11:34 PM PDT 24
Finished Jun 05 04:11:36 PM PDT 24
Peak memory 196680 kb
Host smart-2755900e-7a10-4f8a-833a-f9b7a80a230b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887177911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.2887177911
Directory /workspace/1.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.3210287250
Short name T1312
Test name
Test status
Simulation time 98901358 ps
CPU time 1.56 seconds
Started Jun 05 04:11:37 PM PDT 24
Finished Jun 05 04:11:39 PM PDT 24
Peak memory 198208 kb
Host smart-1e1234e7-c0f0-485d-a378-f7be9395f099
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210287250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.3210287250
Directory /workspace/1.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.9533927
Short name T1249
Test name
Test status
Simulation time 32511439 ps
CPU time 0.56 seconds
Started Jun 05 04:11:37 PM PDT 24
Finished Jun 05 04:11:38 PM PDT 24
Peak memory 195720 kb
Host smart-78a63eb1-2b9e-457a-afca-a938949e749a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9533927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.9533927
Directory /workspace/1.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.2140335957
Short name T1274
Test name
Test status
Simulation time 126325552 ps
CPU time 1.45 seconds
Started Jun 05 04:11:35 PM PDT 24
Finished Jun 05 04:11:37 PM PDT 24
Peak memory 200268 kb
Host smart-653398d1-d1cd-4734-b5ba-48d8dff3c31d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140335957 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.2140335957
Directory /workspace/1.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_rw.2407722953
Short name T1229
Test name
Test status
Simulation time 42170325 ps
CPU time 0.62 seconds
Started Jun 05 04:11:34 PM PDT 24
Finished Jun 05 04:11:36 PM PDT 24
Peak memory 195888 kb
Host smart-a15f03c7-6ada-4587-9146-e5a466a869c3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407722953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.2407722953
Directory /workspace/1.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.uart_intr_test.1780151289
Short name T1179
Test name
Test status
Simulation time 15088031 ps
CPU time 0.59 seconds
Started Jun 05 04:11:37 PM PDT 24
Finished Jun 05 04:11:39 PM PDT 24
Peak memory 194924 kb
Host smart-f52207db-22c8-4e75-b6c8-3e9093eea55d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780151289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.1780151289
Directory /workspace/1.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.2246920984
Short name T1282
Test name
Test status
Simulation time 48284423 ps
CPU time 0.66 seconds
Started Jun 05 04:11:38 PM PDT 24
Finished Jun 05 04:11:40 PM PDT 24
Peak memory 196168 kb
Host smart-a347381e-788f-4e33-b972-3306ebf4b798
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246920984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr
_outstanding.2246920984
Directory /workspace/1.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_errors.3180289818
Short name T1255
Test name
Test status
Simulation time 100134598 ps
CPU time 1.33 seconds
Started Jun 05 04:11:37 PM PDT 24
Finished Jun 05 04:11:40 PM PDT 24
Peak memory 200372 kb
Host smart-5f9b59fe-33cf-429e-b013-d23bd18f55d3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180289818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.3180289818
Directory /workspace/1.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.3605063821
Short name T1279
Test name
Test status
Simulation time 85288807 ps
CPU time 0.92 seconds
Started Jun 05 04:11:36 PM PDT 24
Finished Jun 05 04:11:38 PM PDT 24
Peak memory 199300 kb
Host smart-d8911374-84c5-46f9-a20a-4156d54897c4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605063821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.3605063821
Directory /workspace/1.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.1030287240
Short name T1308
Test name
Test status
Simulation time 27929017 ps
CPU time 0.79 seconds
Started Jun 05 04:11:43 PM PDT 24
Finished Jun 05 04:11:44 PM PDT 24
Peak memory 200140 kb
Host smart-ab55e9be-8001-44d0-9a7b-3516e5a333a7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030287240 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.1030287240
Directory /workspace/10.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_rw.1661461303
Short name T1223
Test name
Test status
Simulation time 32902583 ps
CPU time 0.58 seconds
Started Jun 05 04:11:44 PM PDT 24
Finished Jun 05 04:11:45 PM PDT 24
Peak memory 195704 kb
Host smart-5413297c-759e-43fa-b255-afc045e9ca6f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661461303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.1661461303
Directory /workspace/10.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.uart_intr_test.2656561608
Short name T1241
Test name
Test status
Simulation time 17350586 ps
CPU time 0.57 seconds
Started Jun 05 04:11:46 PM PDT 24
Finished Jun 05 04:11:48 PM PDT 24
Peak memory 194688 kb
Host smart-5aecc52a-48ae-46cf-af93-02d4766b007b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656561608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.2656561608
Directory /workspace/10.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.4222268355
Short name T1231
Test name
Test status
Simulation time 27679650 ps
CPU time 0.69 seconds
Started Jun 05 04:11:47 PM PDT 24
Finished Jun 05 04:11:48 PM PDT 24
Peak memory 197172 kb
Host smart-fe25b1f8-9bc0-4e25-b2b7-7e2bbcdcdbcf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222268355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_cs
r_outstanding.4222268355
Directory /workspace/10.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_errors.2534108187
Short name T1268
Test name
Test status
Simulation time 89798367 ps
CPU time 1.19 seconds
Started Jun 05 04:11:46 PM PDT 24
Finished Jun 05 04:11:47 PM PDT 24
Peak memory 200388 kb
Host smart-25712aae-bb91-48d5-bccb-a9cbdc298b26
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534108187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.2534108187
Directory /workspace/10.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.2257959699
Short name T91
Test name
Test status
Simulation time 426686837 ps
CPU time 1.29 seconds
Started Jun 05 04:11:47 PM PDT 24
Finished Jun 05 04:11:50 PM PDT 24
Peak memory 199312 kb
Host smart-8f46929b-9ae7-4c4b-a0a5-5ce5822ff8db
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257959699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.2257959699
Directory /workspace/10.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.889649208
Short name T1288
Test name
Test status
Simulation time 34911182 ps
CPU time 0.64 seconds
Started Jun 05 04:11:46 PM PDT 24
Finished Jun 05 04:11:48 PM PDT 24
Peak memory 197604 kb
Host smart-69b43fbf-68c6-4d44-897c-13bd1ab0058c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889649208 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.889649208
Directory /workspace/11.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_rw.2303273379
Short name T1218
Test name
Test status
Simulation time 31247111 ps
CPU time 0.63 seconds
Started Jun 05 04:11:45 PM PDT 24
Finished Jun 05 04:11:46 PM PDT 24
Peak memory 195816 kb
Host smart-b5847637-6e9b-4f0c-9e13-de746fbcb359
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303273379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.2303273379
Directory /workspace/11.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.uart_intr_test.1092436584
Short name T1233
Test name
Test status
Simulation time 15230546 ps
CPU time 0.59 seconds
Started Jun 05 04:11:49 PM PDT 24
Finished Jun 05 04:11:50 PM PDT 24
Peak memory 194676 kb
Host smart-41593bd2-6c51-436d-a17a-ef10919f65e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092436584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.1092436584
Directory /workspace/11.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.103944914
Short name T83
Test name
Test status
Simulation time 29288574 ps
CPU time 0.78 seconds
Started Jun 05 04:11:46 PM PDT 24
Finished Jun 05 04:11:48 PM PDT 24
Peak memory 197496 kb
Host smart-c737893e-f978-4313-9d5a-9d4ef33c7031
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103944914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_csr
_outstanding.103944914
Directory /workspace/11.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_errors.1907876672
Short name T1303
Test name
Test status
Simulation time 174187644 ps
CPU time 2.25 seconds
Started Jun 05 04:11:45 PM PDT 24
Finished Jun 05 04:11:48 PM PDT 24
Peak memory 200340 kb
Host smart-eaf5c57e-0859-4794-8de1-33d02e874293
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907876672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.1907876672
Directory /workspace/11.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.4212416294
Short name T1254
Test name
Test status
Simulation time 318502825 ps
CPU time 1.28 seconds
Started Jun 05 04:11:46 PM PDT 24
Finished Jun 05 04:11:49 PM PDT 24
Peak memory 199572 kb
Host smart-d175e87a-8f99-46c2-952e-e02b0a734f22
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212416294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.4212416294
Directory /workspace/11.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.1909052501
Short name T1287
Test name
Test status
Simulation time 53318504 ps
CPU time 0.84 seconds
Started Jun 05 04:11:45 PM PDT 24
Finished Jun 05 04:11:47 PM PDT 24
Peak memory 200164 kb
Host smart-f9e79a21-e0dd-4704-9e32-8be5cca7e980
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909052501 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.1909052501
Directory /workspace/12.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_rw.1039881208
Short name T87
Test name
Test status
Simulation time 34979961 ps
CPU time 0.68 seconds
Started Jun 05 04:11:49 PM PDT 24
Finished Jun 05 04:11:50 PM PDT 24
Peak memory 195768 kb
Host smart-d3919ab0-a940-4c2b-aa09-6edeaa881edf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039881208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.1039881208
Directory /workspace/12.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.uart_intr_test.1705151653
Short name T1189
Test name
Test status
Simulation time 33231410 ps
CPU time 0.57 seconds
Started Jun 05 04:11:46 PM PDT 24
Finished Jun 05 04:11:48 PM PDT 24
Peak memory 194688 kb
Host smart-445ed8c7-b1d4-4831-827b-584d80d2e1b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705151653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.1705151653
Directory /workspace/12.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.3484922562
Short name T86
Test name
Test status
Simulation time 39717115 ps
CPU time 0.72 seconds
Started Jun 05 04:11:49 PM PDT 24
Finished Jun 05 04:11:50 PM PDT 24
Peak memory 196100 kb
Host smart-a5db94ed-ecfc-430c-bb87-badb194673af
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484922562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_cs
r_outstanding.3484922562
Directory /workspace/12.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_errors.3768563624
Short name T1215
Test name
Test status
Simulation time 128789330 ps
CPU time 2.23 seconds
Started Jun 05 04:11:45 PM PDT 24
Finished Jun 05 04:11:48 PM PDT 24
Peak memory 200388 kb
Host smart-821b6c37-95ac-4bfc-8c6a-06a70f2e0f15
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768563624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.3768563624
Directory /workspace/12.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.887842006
Short name T1307
Test name
Test status
Simulation time 46433457 ps
CPU time 0.98 seconds
Started Jun 05 04:11:46 PM PDT 24
Finished Jun 05 04:11:47 PM PDT 24
Peak memory 199656 kb
Host smart-0ed7fc73-d716-4b54-9f8f-1aa0d71fd241
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887842006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.887842006
Directory /workspace/12.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.2012472638
Short name T1201
Test name
Test status
Simulation time 96748392 ps
CPU time 0.73 seconds
Started Jun 05 04:11:53 PM PDT 24
Finished Jun 05 04:11:54 PM PDT 24
Peak memory 198396 kb
Host smart-08ca5305-376c-471e-ae0d-89e2c626925d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012472638 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.2012472638
Directory /workspace/13.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_rw.3993022292
Short name T1237
Test name
Test status
Simulation time 18142845 ps
CPU time 0.55 seconds
Started Jun 05 04:11:47 PM PDT 24
Finished Jun 05 04:11:49 PM PDT 24
Peak memory 195728 kb
Host smart-5642eccb-bc59-4889-a032-b3a305066376
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993022292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.3993022292
Directory /workspace/13.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.uart_intr_test.4248977633
Short name T1314
Test name
Test status
Simulation time 27962338 ps
CPU time 0.61 seconds
Started Jun 05 04:11:45 PM PDT 24
Finished Jun 05 04:11:47 PM PDT 24
Peak memory 194856 kb
Host smart-b3cb5b97-a91c-48b1-a94b-978e97c5d820
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248977633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.4248977633
Directory /workspace/13.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.3971734495
Short name T1236
Test name
Test status
Simulation time 21439600 ps
CPU time 0.65 seconds
Started Jun 05 04:11:50 PM PDT 24
Finished Jun 05 04:11:52 PM PDT 24
Peak memory 196856 kb
Host smart-739f9ac2-5561-4aaa-96be-61a1efa6b045
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971734495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_cs
r_outstanding.3971734495
Directory /workspace/13.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_errors.1111435672
Short name T1183
Test name
Test status
Simulation time 84205567 ps
CPU time 1.26 seconds
Started Jun 05 04:11:47 PM PDT 24
Finished Jun 05 04:11:49 PM PDT 24
Peak memory 200388 kb
Host smart-c396f073-6926-4d4b-9521-d74f52d38bd4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111435672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.1111435672
Directory /workspace/13.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.3929907666
Short name T1310
Test name
Test status
Simulation time 42293112 ps
CPU time 1.09 seconds
Started Jun 05 04:11:49 PM PDT 24
Finished Jun 05 04:11:51 PM PDT 24
Peak memory 200216 kb
Host smart-83792ae1-6d06-405a-a525-c99f5bec92fc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929907666 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.3929907666
Directory /workspace/14.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_rw.3678173483
Short name T1238
Test name
Test status
Simulation time 25275042 ps
CPU time 0.62 seconds
Started Jun 05 04:11:49 PM PDT 24
Finished Jun 05 04:11:50 PM PDT 24
Peak memory 195724 kb
Host smart-ff78ac17-2570-4543-a848-1afcb2b5c868
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678173483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.3678173483
Directory /workspace/14.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.uart_intr_test.3905294582
Short name T1283
Test name
Test status
Simulation time 20846102 ps
CPU time 0.57 seconds
Started Jun 05 04:11:46 PM PDT 24
Finished Jun 05 04:11:48 PM PDT 24
Peak memory 194692 kb
Host smart-32cd2dae-4f7f-4a39-b897-59828b5d2732
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905294582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.3905294582
Directory /workspace/14.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.1922031732
Short name T81
Test name
Test status
Simulation time 17421075 ps
CPU time 0.72 seconds
Started Jun 05 04:11:53 PM PDT 24
Finished Jun 05 04:11:54 PM PDT 24
Peak memory 197492 kb
Host smart-136a22ef-daf7-4e2e-a141-352b0edbfc76
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922031732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_cs
r_outstanding.1922031732
Directory /workspace/14.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_errors.2983984904
Short name T1315
Test name
Test status
Simulation time 394618058 ps
CPU time 1.66 seconds
Started Jun 05 04:11:48 PM PDT 24
Finished Jun 05 04:11:51 PM PDT 24
Peak memory 200396 kb
Host smart-4c83c87b-853b-4019-a22d-e076ce39286e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983984904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.2983984904
Directory /workspace/14.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.3008566236
Short name T1178
Test name
Test status
Simulation time 40598109 ps
CPU time 0.96 seconds
Started Jun 05 04:11:47 PM PDT 24
Finished Jun 05 04:11:50 PM PDT 24
Peak memory 200220 kb
Host smart-34ef7fa8-69a4-4258-a7b9-b0892f3f31a0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008566236 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.3008566236
Directory /workspace/15.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_rw.3839359195
Short name T1258
Test name
Test status
Simulation time 13770808 ps
CPU time 0.59 seconds
Started Jun 05 04:11:49 PM PDT 24
Finished Jun 05 04:11:50 PM PDT 24
Peak memory 195572 kb
Host smart-5df3df37-16a3-4fbf-a6da-8e87fccee9b0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839359195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.3839359195
Directory /workspace/15.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.uart_intr_test.3577193247
Short name T1259
Test name
Test status
Simulation time 42427923 ps
CPU time 0.57 seconds
Started Jun 05 04:11:51 PM PDT 24
Finished Jun 05 04:11:52 PM PDT 24
Peak memory 194704 kb
Host smart-2aaf1bec-efd6-493e-a700-2680485bce46
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577193247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.3577193247
Directory /workspace/15.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.380728890
Short name T1301
Test name
Test status
Simulation time 22658123 ps
CPU time 0.67 seconds
Started Jun 05 04:11:47 PM PDT 24
Finished Jun 05 04:11:49 PM PDT 24
Peak memory 195964 kb
Host smart-6fbb8bcf-ee37-4e58-805d-afb88acf1352
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380728890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_csr
_outstanding.380728890
Directory /workspace/15.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_errors.2329628479
Short name T1213
Test name
Test status
Simulation time 42347523 ps
CPU time 2.17 seconds
Started Jun 05 04:11:49 PM PDT 24
Finished Jun 05 04:11:52 PM PDT 24
Peak memory 200400 kb
Host smart-0c1c075d-534d-4234-9479-851c84df1ff9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329628479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.2329628479
Directory /workspace/15.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.2138936351
Short name T97
Test name
Test status
Simulation time 92361657 ps
CPU time 1.04 seconds
Started Jun 05 04:11:51 PM PDT 24
Finished Jun 05 04:11:52 PM PDT 24
Peak memory 199424 kb
Host smart-1460a2e1-928e-4327-866b-4a1f968b165d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138936351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.2138936351
Directory /workspace/15.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.472317731
Short name T1291
Test name
Test status
Simulation time 28021043 ps
CPU time 0.83 seconds
Started Jun 05 04:11:50 PM PDT 24
Finished Jun 05 04:11:52 PM PDT 24
Peak memory 199980 kb
Host smart-03b15f16-ec57-4e40-b717-f55a2e45ed02
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472317731 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.472317731
Directory /workspace/16.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_rw.599432237
Short name T80
Test name
Test status
Simulation time 42207331 ps
CPU time 0.59 seconds
Started Jun 05 04:11:51 PM PDT 24
Finished Jun 05 04:11:52 PM PDT 24
Peak memory 195720 kb
Host smart-1cfe4aae-59be-47ef-91b1-ce2b3f36ee25
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599432237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.599432237
Directory /workspace/16.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.uart_intr_test.2082832240
Short name T1286
Test name
Test status
Simulation time 19142266 ps
CPU time 0.59 seconds
Started Jun 05 04:11:47 PM PDT 24
Finished Jun 05 04:11:49 PM PDT 24
Peak memory 194700 kb
Host smart-03b7855c-98bd-4077-ba9f-099fcef3fa8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082832240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.2082832240
Directory /workspace/16.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.634290908
Short name T1252
Test name
Test status
Simulation time 86797652 ps
CPU time 0.72 seconds
Started Jun 05 04:11:57 PM PDT 24
Finished Jun 05 04:11:58 PM PDT 24
Peak memory 196072 kb
Host smart-a28060c7-1795-4a1f-81c1-d8c79fa7debb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634290908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_csr
_outstanding.634290908
Directory /workspace/16.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_errors.84312852
Short name T1187
Test name
Test status
Simulation time 211932059 ps
CPU time 2.37 seconds
Started Jun 05 04:11:51 PM PDT 24
Finished Jun 05 04:11:54 PM PDT 24
Peak memory 200384 kb
Host smart-e5017862-2e42-44f6-86ab-84cc6c8e9e5b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84312852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.84312852
Directory /workspace/16.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.4090791810
Short name T1242
Test name
Test status
Simulation time 238464043 ps
CPU time 0.98 seconds
Started Jun 05 04:11:50 PM PDT 24
Finished Jun 05 04:11:51 PM PDT 24
Peak memory 199516 kb
Host smart-af262c13-3cf3-4c44-bc77-db87588b35f7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090791810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.4090791810
Directory /workspace/16.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.2086651395
Short name T1207
Test name
Test status
Simulation time 60285752 ps
CPU time 0.65 seconds
Started Jun 05 04:11:49 PM PDT 24
Finished Jun 05 04:11:50 PM PDT 24
Peak memory 197708 kb
Host smart-45748174-9059-4f92-9472-321093831a07
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086651395 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.2086651395
Directory /workspace/17.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_rw.80967408
Short name T82
Test name
Test status
Simulation time 16199079 ps
CPU time 0.64 seconds
Started Jun 05 04:11:57 PM PDT 24
Finished Jun 05 04:11:58 PM PDT 24
Peak memory 196068 kb
Host smart-0d7c4937-1e67-42bc-b54e-99626082792c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80967408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.80967408
Directory /workspace/17.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.uart_intr_test.3658846175
Short name T1316
Test name
Test status
Simulation time 36995043 ps
CPU time 0.59 seconds
Started Jun 05 04:11:53 PM PDT 24
Finished Jun 05 04:11:55 PM PDT 24
Peak memory 194736 kb
Host smart-e5992659-7cc9-411e-983d-ec9748478e9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658846175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.3658846175
Directory /workspace/17.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.2485052636
Short name T88
Test name
Test status
Simulation time 18187765 ps
CPU time 0.72 seconds
Started Jun 05 04:11:52 PM PDT 24
Finished Jun 05 04:11:54 PM PDT 24
Peak memory 197392 kb
Host smart-cd82e63c-ae10-42ad-8d9f-b0e39864b0b1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485052636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_cs
r_outstanding.2485052636
Directory /workspace/17.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_errors.1135062268
Short name T1180
Test name
Test status
Simulation time 73634152 ps
CPU time 1.97 seconds
Started Jun 05 04:11:58 PM PDT 24
Finished Jun 05 04:12:01 PM PDT 24
Peak memory 200368 kb
Host smart-841bdacd-5251-446e-bb40-c0b7e55e3801
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135062268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.1135062268
Directory /workspace/17.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.4162801666
Short name T1297
Test name
Test status
Simulation time 75752487 ps
CPU time 0.73 seconds
Started Jun 05 04:11:53 PM PDT 24
Finished Jun 05 04:11:54 PM PDT 24
Peak memory 198576 kb
Host smart-d3bfa313-3fea-46c8-a7e0-e2f8f0e44999
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162801666 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.4162801666
Directory /workspace/18.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.uart_intr_test.3736780199
Short name T1222
Test name
Test status
Simulation time 13836736 ps
CPU time 0.56 seconds
Started Jun 05 04:11:53 PM PDT 24
Finished Jun 05 04:11:54 PM PDT 24
Peak memory 194696 kb
Host smart-093d9bae-a2ab-414e-93a9-a52b148cf372
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736780199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.3736780199
Directory /workspace/18.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.3071165952
Short name T1284
Test name
Test status
Simulation time 20342629 ps
CPU time 0.71 seconds
Started Jun 05 04:11:54 PM PDT 24
Finished Jun 05 04:11:56 PM PDT 24
Peak memory 197300 kb
Host smart-43a8c9d7-11fa-4762-ba3f-486d3949664f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071165952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_cs
r_outstanding.3071165952
Directory /workspace/18.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_errors.3350325365
Short name T1269
Test name
Test status
Simulation time 356444910 ps
CPU time 1.15 seconds
Started Jun 05 04:11:46 PM PDT 24
Finished Jun 05 04:11:48 PM PDT 24
Peak memory 200184 kb
Host smart-25b7c8e0-9ed8-4770-9f4c-c15f6f71a3c3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350325365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.3350325365
Directory /workspace/18.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.122084313
Short name T92
Test name
Test status
Simulation time 124924583 ps
CPU time 1.32 seconds
Started Jun 05 04:11:46 PM PDT 24
Finished Jun 05 04:11:48 PM PDT 24
Peak memory 199648 kb
Host smart-b4dff72c-7617-42bb-b4a6-f14131b95319
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122084313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.122084313
Directory /workspace/18.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.56703898
Short name T1247
Test name
Test status
Simulation time 221843557 ps
CPU time 0.81 seconds
Started Jun 05 04:11:53 PM PDT 24
Finished Jun 05 04:11:55 PM PDT 24
Peak memory 199892 kb
Host smart-82790d41-4360-4bed-b658-85e3aaba059b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56703898 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.56703898
Directory /workspace/19.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_rw.2130832777
Short name T1295
Test name
Test status
Simulation time 71366439 ps
CPU time 0.61 seconds
Started Jun 05 04:11:54 PM PDT 24
Finished Jun 05 04:11:55 PM PDT 24
Peak memory 195720 kb
Host smart-b667ab84-7380-43bf-83f7-553f94741063
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130832777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.2130832777
Directory /workspace/19.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.uart_intr_test.1494071339
Short name T1184
Test name
Test status
Simulation time 35507705 ps
CPU time 0.56 seconds
Started Jun 05 04:11:53 PM PDT 24
Finished Jun 05 04:11:55 PM PDT 24
Peak memory 194728 kb
Host smart-c404eb71-be3c-4150-ba8f-6e093039afaa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494071339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.1494071339
Directory /workspace/19.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.2656008170
Short name T1313
Test name
Test status
Simulation time 13413138 ps
CPU time 0.68 seconds
Started Jun 05 04:11:54 PM PDT 24
Finished Jun 05 04:11:55 PM PDT 24
Peak memory 196020 kb
Host smart-00f3dca5-949f-4c27-80d0-fd2e92020dd5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656008170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_cs
r_outstanding.2656008170
Directory /workspace/19.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_errors.2412970095
Short name T1260
Test name
Test status
Simulation time 246800338 ps
CPU time 1.87 seconds
Started Jun 05 04:11:53 PM PDT 24
Finished Jun 05 04:11:55 PM PDT 24
Peak memory 200532 kb
Host smart-e3428c32-cc18-4045-8d4a-66eaec85199d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412970095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.2412970095
Directory /workspace/19.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.1300481820
Short name T1272
Test name
Test status
Simulation time 117192447 ps
CPU time 1.32 seconds
Started Jun 05 04:11:58 PM PDT 24
Finished Jun 05 04:12:00 PM PDT 24
Peak memory 198780 kb
Host smart-f1d00bef-040d-4d61-969b-87b02ed02ad5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300481820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.1300481820
Directory /workspace/19.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.1775438677
Short name T79
Test name
Test status
Simulation time 22761302 ps
CPU time 0.69 seconds
Started Jun 05 04:11:38 PM PDT 24
Finished Jun 05 04:11:40 PM PDT 24
Peak memory 195616 kb
Host smart-dc48e8e8-9edd-4f71-897a-abf10218aa55
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775438677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.1775438677
Directory /workspace/2.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.4065965229
Short name T1250
Test name
Test status
Simulation time 182666412 ps
CPU time 2.48 seconds
Started Jun 05 04:11:37 PM PDT 24
Finished Jun 05 04:11:41 PM PDT 24
Peak memory 198200 kb
Host smart-9f04848b-72a0-4812-b63a-45c7eb313867
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065965229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.4065965229
Directory /workspace/2.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.1218483218
Short name T1276
Test name
Test status
Simulation time 152830427 ps
CPU time 0.59 seconds
Started Jun 05 04:11:34 PM PDT 24
Finished Jun 05 04:11:35 PM PDT 24
Peak memory 195716 kb
Host smart-d8cc9b18-37ce-4a3f-a95a-fd54d697bcda
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218483218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.1218483218
Directory /workspace/2.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.4040809155
Short name T1270
Test name
Test status
Simulation time 18426765 ps
CPU time 0.74 seconds
Started Jun 05 04:11:38 PM PDT 24
Finished Jun 05 04:11:40 PM PDT 24
Peak memory 197948 kb
Host smart-a54da102-3f71-493d-9691-49789009d434
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040809155 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.4040809155
Directory /workspace/2.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_rw.1759687860
Short name T1305
Test name
Test status
Simulation time 39576372 ps
CPU time 0.61 seconds
Started Jun 05 04:11:37 PM PDT 24
Finished Jun 05 04:11:39 PM PDT 24
Peak memory 195712 kb
Host smart-18990687-15b8-46f0-a257-259f97c630f4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759687860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.1759687860
Directory /workspace/2.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.uart_intr_test.1880362452
Short name T1309
Test name
Test status
Simulation time 18141948 ps
CPU time 0.59 seconds
Started Jun 05 04:11:39 PM PDT 24
Finished Jun 05 04:11:40 PM PDT 24
Peak memory 194664 kb
Host smart-00df6367-ada8-467d-9aea-42a1daeedadd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880362452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.1880362452
Directory /workspace/2.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.203829604
Short name T1264
Test name
Test status
Simulation time 28187284 ps
CPU time 0.74 seconds
Started Jun 05 04:11:37 PM PDT 24
Finished Jun 05 04:11:39 PM PDT 24
Peak memory 196340 kb
Host smart-d4883cf6-0715-4021-a6b2-2d27500b9298
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203829604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr_
outstanding.203829604
Directory /workspace/2.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_errors.2638507140
Short name T1285
Test name
Test status
Simulation time 94424345 ps
CPU time 1.53 seconds
Started Jun 05 04:11:38 PM PDT 24
Finished Jun 05 04:11:41 PM PDT 24
Peak memory 200272 kb
Host smart-b03d3d68-61b6-4389-a446-30705486d9f2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638507140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.2638507140
Directory /workspace/2.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.4255039611
Short name T95
Test name
Test status
Simulation time 42328408 ps
CPU time 0.91 seconds
Started Jun 05 04:11:37 PM PDT 24
Finished Jun 05 04:11:38 PM PDT 24
Peak memory 199072 kb
Host smart-32884601-89fd-42f7-9e65-74f091a3a045
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255039611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.4255039611
Directory /workspace/2.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.uart_intr_test.1218877118
Short name T1194
Test name
Test status
Simulation time 45309133 ps
CPU time 0.59 seconds
Started Jun 05 04:11:59 PM PDT 24
Finished Jun 05 04:12:00 PM PDT 24
Peak memory 194688 kb
Host smart-3a2f641c-5f75-48ec-b99e-b1bd934405f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218877118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.1218877118
Directory /workspace/20.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.uart_intr_test.1938397230
Short name T1217
Test name
Test status
Simulation time 43875333 ps
CPU time 0.55 seconds
Started Jun 05 04:11:58 PM PDT 24
Finished Jun 05 04:11:59 PM PDT 24
Peak memory 194148 kb
Host smart-2da595eb-241e-4c60-8f77-886ff3e73c69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938397230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.1938397230
Directory /workspace/21.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.uart_intr_test.3020006999
Short name T1298
Test name
Test status
Simulation time 14966471 ps
CPU time 0.58 seconds
Started Jun 05 04:11:57 PM PDT 24
Finished Jun 05 04:11:59 PM PDT 24
Peak memory 194716 kb
Host smart-9f2cad65-9bb1-4f4d-91e2-4358a6cde970
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020006999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.3020006999
Directory /workspace/22.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.uart_intr_test.2029458349
Short name T1227
Test name
Test status
Simulation time 63974818 ps
CPU time 0.66 seconds
Started Jun 05 04:11:54 PM PDT 24
Finished Jun 05 04:11:55 PM PDT 24
Peak memory 194760 kb
Host smart-695a440b-2de2-42d2-a49d-50bc7bc0ebd0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029458349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.2029458349
Directory /workspace/23.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.uart_intr_test.2267481069
Short name T1240
Test name
Test status
Simulation time 15704941 ps
CPU time 0.6 seconds
Started Jun 05 04:11:56 PM PDT 24
Finished Jun 05 04:11:58 PM PDT 24
Peak memory 194692 kb
Host smart-b8bd95df-2593-46bc-bf5b-6998acd689b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267481069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.2267481069
Directory /workspace/24.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.uart_intr_test.1258416400
Short name T1290
Test name
Test status
Simulation time 15261430 ps
CPU time 0.59 seconds
Started Jun 05 04:11:57 PM PDT 24
Finished Jun 05 04:11:58 PM PDT 24
Peak memory 194760 kb
Host smart-c4664842-147c-47de-a69f-0a50d2e97468
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258416400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.1258416400
Directory /workspace/25.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.uart_intr_test.3381794654
Short name T1251
Test name
Test status
Simulation time 30811041 ps
CPU time 0.55 seconds
Started Jun 05 04:11:52 PM PDT 24
Finished Jun 05 04:11:53 PM PDT 24
Peak memory 194692 kb
Host smart-17346f51-cab8-4918-9332-ea0cb1886e00
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381794654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.3381794654
Directory /workspace/26.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.uart_intr_test.3511983153
Short name T1243
Test name
Test status
Simulation time 28031299 ps
CPU time 0.58 seconds
Started Jun 05 04:11:55 PM PDT 24
Finished Jun 05 04:11:56 PM PDT 24
Peak memory 194592 kb
Host smart-1ce81569-78e2-4484-bdab-b0b74f95f1a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511983153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.3511983153
Directory /workspace/27.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.uart_intr_test.1550513865
Short name T1300
Test name
Test status
Simulation time 49889823 ps
CPU time 0.61 seconds
Started Jun 05 04:11:53 PM PDT 24
Finished Jun 05 04:11:54 PM PDT 24
Peak memory 194868 kb
Host smart-ebf56282-6963-4198-a159-0216262eefe5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550513865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.1550513865
Directory /workspace/28.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.uart_intr_test.3492865200
Short name T1197
Test name
Test status
Simulation time 19585533 ps
CPU time 0.56 seconds
Started Jun 05 04:11:52 PM PDT 24
Finished Jun 05 04:11:54 PM PDT 24
Peak memory 194756 kb
Host smart-24540a46-9132-4076-b2f8-c57dcc969709
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492865200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.3492865200
Directory /workspace/29.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.406722898
Short name T1202
Test name
Test status
Simulation time 21957215 ps
CPU time 0.63 seconds
Started Jun 05 04:11:37 PM PDT 24
Finished Jun 05 04:11:39 PM PDT 24
Peak memory 195292 kb
Host smart-e02d1d84-cdd0-4951-adaa-6773f7c627e4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406722898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.406722898
Directory /workspace/3.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.3795862708
Short name T1205
Test name
Test status
Simulation time 340511177 ps
CPU time 1.61 seconds
Started Jun 05 04:11:37 PM PDT 24
Finished Jun 05 04:11:40 PM PDT 24
Peak memory 198280 kb
Host smart-5266a94f-6503-4712-8362-945b14544c5e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795862708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.3795862708
Directory /workspace/3.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.1087753912
Short name T1198
Test name
Test status
Simulation time 15007097 ps
CPU time 0.62 seconds
Started Jun 05 04:11:38 PM PDT 24
Finished Jun 05 04:11:40 PM PDT 24
Peak memory 195716 kb
Host smart-efd54717-b289-4611-a27a-15f928052245
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087753912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.1087753912
Directory /workspace/3.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.59609107
Short name T1277
Test name
Test status
Simulation time 71618261 ps
CPU time 1.33 seconds
Started Jun 05 04:11:37 PM PDT 24
Finished Jun 05 04:11:40 PM PDT 24
Peak memory 200384 kb
Host smart-dc86958a-d2e1-4637-8691-8883ceb7a5b7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59609107 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.59609107
Directory /workspace/3.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_rw.4219044554
Short name T1275
Test name
Test status
Simulation time 14996237 ps
CPU time 0.6 seconds
Started Jun 05 04:11:37 PM PDT 24
Finished Jun 05 04:11:39 PM PDT 24
Peak memory 195880 kb
Host smart-27e1bc39-a287-487a-90a1-c0d55fb557d6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219044554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.4219044554
Directory /workspace/3.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.uart_intr_test.4042396937
Short name T1216
Test name
Test status
Simulation time 36326122 ps
CPU time 0.6 seconds
Started Jun 05 04:11:37 PM PDT 24
Finished Jun 05 04:11:39 PM PDT 24
Peak memory 194604 kb
Host smart-a9ca3848-d19b-416f-aa6a-b59521353c19
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042396937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.4042396937
Directory /workspace/3.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.4123773126
Short name T1220
Test name
Test status
Simulation time 22670744 ps
CPU time 0.64 seconds
Started Jun 05 04:11:41 PM PDT 24
Finished Jun 05 04:11:42 PM PDT 24
Peak memory 195860 kb
Host smart-79c0c8cd-eb16-4dd2-8648-8fcd4cda9984
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123773126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr
_outstanding.4123773126
Directory /workspace/3.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_errors.4150527848
Short name T1195
Test name
Test status
Simulation time 231056545 ps
CPU time 2.07 seconds
Started Jun 05 04:11:41 PM PDT 24
Finished Jun 05 04:11:44 PM PDT 24
Peak memory 200372 kb
Host smart-388de5d1-87da-460e-900c-eb9232483dda
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150527848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.4150527848
Directory /workspace/3.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.1825445956
Short name T96
Test name
Test status
Simulation time 93127742 ps
CPU time 1.25 seconds
Started Jun 05 04:11:41 PM PDT 24
Finished Jun 05 04:11:43 PM PDT 24
Peak memory 199580 kb
Host smart-de9d6bb5-5a72-4d69-b08a-f225e508669f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825445956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.1825445956
Directory /workspace/3.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.uart_intr_test.1141477611
Short name T1311
Test name
Test status
Simulation time 44786641 ps
CPU time 0.57 seconds
Started Jun 05 04:11:50 PM PDT 24
Finished Jun 05 04:11:51 PM PDT 24
Peak memory 194684 kb
Host smart-aa64c1d0-b44c-47b2-b437-0d879cc03236
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141477611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.1141477611
Directory /workspace/30.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.uart_intr_test.510694481
Short name T1192
Test name
Test status
Simulation time 22488863 ps
CPU time 0.63 seconds
Started Jun 05 04:11:56 PM PDT 24
Finished Jun 05 04:11:57 PM PDT 24
Peak memory 194736 kb
Host smart-44193c7a-bf3b-43b4-9a35-b6959f6a43c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510694481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.510694481
Directory /workspace/31.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.uart_intr_test.4076826455
Short name T1204
Test name
Test status
Simulation time 19903151 ps
CPU time 0.53 seconds
Started Jun 05 04:11:54 PM PDT 24
Finished Jun 05 04:11:56 PM PDT 24
Peak memory 194668 kb
Host smart-aa7c3cf8-3c91-433c-b2da-be4baba140e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076826455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.4076826455
Directory /workspace/32.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.uart_intr_test.664413215
Short name T1257
Test name
Test status
Simulation time 33895183 ps
CPU time 0.56 seconds
Started Jun 05 04:11:52 PM PDT 24
Finished Jun 05 04:11:54 PM PDT 24
Peak memory 194740 kb
Host smart-86bfa91b-13f0-498a-8a06-2199fb5a0e88
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664413215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.664413215
Directory /workspace/33.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.uart_intr_test.4016160938
Short name T1177
Test name
Test status
Simulation time 97871568 ps
CPU time 0.58 seconds
Started Jun 05 04:11:53 PM PDT 24
Finished Jun 05 04:11:54 PM PDT 24
Peak memory 194668 kb
Host smart-5bf6ebf6-f457-4bd2-ad4e-c20220cd4b41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016160938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.4016160938
Directory /workspace/34.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.uart_intr_test.726336376
Short name T1188
Test name
Test status
Simulation time 37348688 ps
CPU time 0.57 seconds
Started Jun 05 04:11:53 PM PDT 24
Finished Jun 05 04:11:54 PM PDT 24
Peak memory 194656 kb
Host smart-9dea4955-db7e-4ef6-952a-78fb0a7b71c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726336376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.726336376
Directory /workspace/35.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.uart_intr_test.1979513851
Short name T1289
Test name
Test status
Simulation time 119148998 ps
CPU time 0.58 seconds
Started Jun 05 04:11:52 PM PDT 24
Finished Jun 05 04:11:53 PM PDT 24
Peak memory 194740 kb
Host smart-d3ba379c-9c5c-450a-989e-da56ae7e1530
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979513851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.1979513851
Directory /workspace/36.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.uart_intr_test.972210217
Short name T1294
Test name
Test status
Simulation time 33498961 ps
CPU time 0.56 seconds
Started Jun 05 04:11:55 PM PDT 24
Finished Jun 05 04:11:57 PM PDT 24
Peak memory 194524 kb
Host smart-389c725f-3b30-4c8d-95bd-d613370774a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972210217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.972210217
Directory /workspace/37.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.uart_intr_test.1857099117
Short name T1228
Test name
Test status
Simulation time 12739680 ps
CPU time 0.58 seconds
Started Jun 05 04:11:52 PM PDT 24
Finished Jun 05 04:11:53 PM PDT 24
Peak memory 194736 kb
Host smart-20fc7416-b92c-4224-b6f1-4d57b6b846a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857099117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.1857099117
Directory /workspace/38.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.uart_intr_test.1351509748
Short name T1306
Test name
Test status
Simulation time 13983733 ps
CPU time 0.64 seconds
Started Jun 05 04:11:55 PM PDT 24
Finished Jun 05 04:11:57 PM PDT 24
Peak memory 194588 kb
Host smart-6055b767-29a8-4e87-bf8e-15d84dfb9dda
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351509748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.1351509748
Directory /workspace/39.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.2317736073
Short name T65
Test name
Test status
Simulation time 15863939 ps
CPU time 0.69 seconds
Started Jun 05 04:11:38 PM PDT 24
Finished Jun 05 04:11:40 PM PDT 24
Peak memory 195648 kb
Host smart-778d1d4d-5602-45e3-be96-84a354ac8927
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317736073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.2317736073
Directory /workspace/4.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.3666431000
Short name T1292
Test name
Test status
Simulation time 56978425 ps
CPU time 2.3 seconds
Started Jun 05 04:11:36 PM PDT 24
Finished Jun 05 04:11:39 PM PDT 24
Peak memory 197820 kb
Host smart-562227b4-39bd-4c7f-a52f-5707bd054eac
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666431000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.3666431000
Directory /workspace/4.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.3913742907
Short name T1281
Test name
Test status
Simulation time 14346768 ps
CPU time 0.58 seconds
Started Jun 05 04:11:37 PM PDT 24
Finished Jun 05 04:11:38 PM PDT 24
Peak memory 195716 kb
Host smart-90dc2044-1228-424b-a12d-a6501939700d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913742907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.3913742907
Directory /workspace/4.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.1505770761
Short name T1232
Test name
Test status
Simulation time 25532044 ps
CPU time 1.12 seconds
Started Jun 05 04:11:39 PM PDT 24
Finished Jun 05 04:11:41 PM PDT 24
Peak memory 200380 kb
Host smart-eade8399-1c6f-4af3-9d08-07e6791990df
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505770761 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.1505770761
Directory /workspace/4.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_rw.2479953226
Short name T66
Test name
Test status
Simulation time 38141051 ps
CPU time 0.65 seconds
Started Jun 05 04:11:41 PM PDT 24
Finished Jun 05 04:11:42 PM PDT 24
Peak memory 195716 kb
Host smart-3487ff0b-5546-4d3b-974b-a813b83ca431
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479953226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.2479953226
Directory /workspace/4.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.uart_intr_test.2025142537
Short name T1245
Test name
Test status
Simulation time 12753150 ps
CPU time 0.59 seconds
Started Jun 05 04:11:37 PM PDT 24
Finished Jun 05 04:11:39 PM PDT 24
Peak memory 194740 kb
Host smart-13a5c09d-da0e-437f-882b-b2462da3dec9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025142537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.2025142537
Directory /workspace/4.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.2970537699
Short name T1246
Test name
Test status
Simulation time 48358346 ps
CPU time 0.64 seconds
Started Jun 05 04:11:40 PM PDT 24
Finished Jun 05 04:11:42 PM PDT 24
Peak memory 196076 kb
Host smart-f07c360d-23ef-4028-a516-1a8afb4be551
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970537699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr
_outstanding.2970537699
Directory /workspace/4.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_errors.1098260649
Short name T1235
Test name
Test status
Simulation time 266638101 ps
CPU time 1.57 seconds
Started Jun 05 04:11:41 PM PDT 24
Finished Jun 05 04:11:43 PM PDT 24
Peak memory 200360 kb
Host smart-3d011179-e4d7-415c-be2b-457c45762e8a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098260649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.1098260649
Directory /workspace/4.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.3273384323
Short name T1280
Test name
Test status
Simulation time 71217020 ps
CPU time 0.94 seconds
Started Jun 05 04:11:41 PM PDT 24
Finished Jun 05 04:11:43 PM PDT 24
Peak memory 199384 kb
Host smart-d116a1a9-3aa1-48c1-9a61-b7bc7c9ff695
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273384323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.3273384323
Directory /workspace/4.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.uart_intr_test.2712337173
Short name T1196
Test name
Test status
Simulation time 39445120 ps
CPU time 0.58 seconds
Started Jun 05 04:11:55 PM PDT 24
Finished Jun 05 04:11:56 PM PDT 24
Peak memory 194700 kb
Host smart-02053ca4-819b-4c52-84a5-4686a23a5e2d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712337173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.2712337173
Directory /workspace/40.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.uart_intr_test.1521325780
Short name T1185
Test name
Test status
Simulation time 43307357 ps
CPU time 0.57 seconds
Started Jun 05 04:11:55 PM PDT 24
Finished Jun 05 04:11:56 PM PDT 24
Peak memory 194756 kb
Host smart-a91bdef9-0070-4fc7-9511-90ff58eab575
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521325780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.1521325780
Directory /workspace/41.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.uart_intr_test.3491800013
Short name T1181
Test name
Test status
Simulation time 17298758 ps
CPU time 0.59 seconds
Started Jun 05 04:11:54 PM PDT 24
Finished Jun 05 04:11:55 PM PDT 24
Peak memory 194692 kb
Host smart-1622fe4b-8f84-4027-9aed-4207a3bb7b60
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491800013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.3491800013
Directory /workspace/42.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.uart_intr_test.4049020274
Short name T1182
Test name
Test status
Simulation time 14871233 ps
CPU time 0.61 seconds
Started Jun 05 04:11:57 PM PDT 24
Finished Jun 05 04:11:58 PM PDT 24
Peak memory 194696 kb
Host smart-d7b4a092-5742-4c96-aafc-3b06c9c6e1cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049020274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.4049020274
Directory /workspace/43.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.uart_intr_test.2637058148
Short name T1210
Test name
Test status
Simulation time 11762284 ps
CPU time 0.59 seconds
Started Jun 05 04:11:55 PM PDT 24
Finished Jun 05 04:11:57 PM PDT 24
Peak memory 194688 kb
Host smart-b410c2a1-3d00-4a68-841d-24700be995be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637058148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.2637058148
Directory /workspace/44.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.uart_intr_test.3696793934
Short name T1191
Test name
Test status
Simulation time 16595362 ps
CPU time 0.58 seconds
Started Jun 05 04:11:54 PM PDT 24
Finished Jun 05 04:11:56 PM PDT 24
Peak memory 194688 kb
Host smart-4a55b6ac-45a2-4f6d-a5b9-1f85f77ae89e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696793934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.3696793934
Directory /workspace/45.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.uart_intr_test.2270892399
Short name T1256
Test name
Test status
Simulation time 11931848 ps
CPU time 0.56 seconds
Started Jun 05 04:11:56 PM PDT 24
Finished Jun 05 04:11:58 PM PDT 24
Peak memory 194540 kb
Host smart-631de56a-01bd-4aba-ad35-491eee9f1b7a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270892399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.2270892399
Directory /workspace/46.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.uart_intr_test.1771351195
Short name T1244
Test name
Test status
Simulation time 13288311 ps
CPU time 0.57 seconds
Started Jun 05 04:11:56 PM PDT 24
Finished Jun 05 04:11:57 PM PDT 24
Peak memory 194696 kb
Host smart-d895c7e5-cc9a-49d6-87f9-6bdf1f8cad05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771351195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.1771351195
Directory /workspace/47.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.uart_intr_test.2860987063
Short name T1263
Test name
Test status
Simulation time 16049324 ps
CPU time 0.59 seconds
Started Jun 05 04:11:53 PM PDT 24
Finished Jun 05 04:11:55 PM PDT 24
Peak memory 194700 kb
Host smart-5240e1cf-89c0-4b8a-83ba-d9d64238feea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860987063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.2860987063
Directory /workspace/48.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.uart_intr_test.2495903886
Short name T1293
Test name
Test status
Simulation time 45235418 ps
CPU time 0.59 seconds
Started Jun 05 04:11:54 PM PDT 24
Finished Jun 05 04:11:56 PM PDT 24
Peak memory 194760 kb
Host smart-f93e1a20-960f-4df3-9b39-b10674157502
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495903886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.2495903886
Directory /workspace/49.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.3292440984
Short name T1302
Test name
Test status
Simulation time 39754315 ps
CPU time 0.77 seconds
Started Jun 05 04:11:38 PM PDT 24
Finished Jun 05 04:11:40 PM PDT 24
Peak memory 198824 kb
Host smart-02dc6452-79a1-43b0-a3aa-622050bce8dc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292440984 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.3292440984
Directory /workspace/5.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_rw.1329583210
Short name T1299
Test name
Test status
Simulation time 23961219 ps
CPU time 0.62 seconds
Started Jun 05 04:11:42 PM PDT 24
Finished Jun 05 04:11:43 PM PDT 24
Peak memory 195928 kb
Host smart-4ba5ed62-d017-4c1a-bde5-070139e5d492
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329583210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.1329583210
Directory /workspace/5.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.uart_intr_test.360036095
Short name T1318
Test name
Test status
Simulation time 42175588 ps
CPU time 0.56 seconds
Started Jun 05 04:11:40 PM PDT 24
Finished Jun 05 04:11:41 PM PDT 24
Peak memory 194700 kb
Host smart-35b67581-215f-4881-b78d-86ca4da40d27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360036095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.360036095
Directory /workspace/5.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.3811729689
Short name T1304
Test name
Test status
Simulation time 35704002 ps
CPU time 0.7 seconds
Started Jun 05 04:11:39 PM PDT 24
Finished Jun 05 04:11:40 PM PDT 24
Peak memory 196208 kb
Host smart-d76d9e61-5c24-4a3f-a1ea-e92ccf394874
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811729689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr
_outstanding.3811729689
Directory /workspace/5.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_errors.2356514780
Short name T1211
Test name
Test status
Simulation time 64888937 ps
CPU time 1.5 seconds
Started Jun 05 04:11:39 PM PDT 24
Finished Jun 05 04:11:41 PM PDT 24
Peak memory 200316 kb
Host smart-b7a41b52-a84e-4170-8fd6-8d1a7cca4edd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356514780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.2356514780
Directory /workspace/5.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.3743955082
Short name T1271
Test name
Test status
Simulation time 89464217 ps
CPU time 1.29 seconds
Started Jun 05 04:11:40 PM PDT 24
Finished Jun 05 04:11:42 PM PDT 24
Peak memory 199624 kb
Host smart-b6687af3-c9a9-4bc1-879b-3c02438e416b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743955082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.3743955082
Directory /workspace/5.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.200839602
Short name T1296
Test name
Test status
Simulation time 33975832 ps
CPU time 0.67 seconds
Started Jun 05 04:11:46 PM PDT 24
Finished Jun 05 04:11:48 PM PDT 24
Peak memory 197524 kb
Host smart-0194d0e1-8994-4329-a6f1-dc4c7f7465fc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200839602 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.200839602
Directory /workspace/6.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_rw.700496008
Short name T1317
Test name
Test status
Simulation time 64018913 ps
CPU time 0.64 seconds
Started Jun 05 04:11:46 PM PDT 24
Finished Jun 05 04:11:48 PM PDT 24
Peak memory 195744 kb
Host smart-a4ed2143-0cf4-4fc9-a439-e2cca631b109
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700496008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.700496008
Directory /workspace/6.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.uart_intr_test.3352271568
Short name T1239
Test name
Test status
Simulation time 23206283 ps
CPU time 0.58 seconds
Started Jun 05 04:11:46 PM PDT 24
Finished Jun 05 04:11:47 PM PDT 24
Peak memory 194736 kb
Host smart-16d0a1d1-dc8c-459e-a60b-a78e554751da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352271568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.3352271568
Directory /workspace/6.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.2894746596
Short name T1212
Test name
Test status
Simulation time 114116063 ps
CPU time 0.74 seconds
Started Jun 05 04:11:43 PM PDT 24
Finished Jun 05 04:11:44 PM PDT 24
Peak memory 197304 kb
Host smart-f4d03bec-a08a-493f-b775-cfa03d0bc2f9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894746596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr
_outstanding.2894746596
Directory /workspace/6.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_errors.1820486797
Short name T1200
Test name
Test status
Simulation time 358632061 ps
CPU time 1.93 seconds
Started Jun 05 04:11:41 PM PDT 24
Finished Jun 05 04:11:43 PM PDT 24
Peak memory 200372 kb
Host smart-77b064e8-9d3d-4bcd-8200-ce579b78230f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820486797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.1820486797
Directory /workspace/6.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.2823956509
Short name T1253
Test name
Test status
Simulation time 151689956 ps
CPU time 0.94 seconds
Started Jun 05 04:11:45 PM PDT 24
Finished Jun 05 04:11:46 PM PDT 24
Peak memory 199036 kb
Host smart-03d4cb2b-a064-48d4-ac7c-942365e57171
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823956509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.2823956509
Directory /workspace/6.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.2115712240
Short name T1225
Test name
Test status
Simulation time 68572235 ps
CPU time 1 seconds
Started Jun 05 04:11:46 PM PDT 24
Finished Jun 05 04:11:48 PM PDT 24
Peak memory 200176 kb
Host smart-561d0a3c-8463-4148-a15d-f9713c34a071
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115712240 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.2115712240
Directory /workspace/7.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_rw.1233744404
Short name T1221
Test name
Test status
Simulation time 12990196 ps
CPU time 0.6 seconds
Started Jun 05 04:11:44 PM PDT 24
Finished Jun 05 04:11:45 PM PDT 24
Peak memory 195692 kb
Host smart-c27eb484-bf18-47d9-aa62-c16d88e847f0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233744404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.1233744404
Directory /workspace/7.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.uart_intr_test.3526192482
Short name T1319
Test name
Test status
Simulation time 43068217 ps
CPU time 0.57 seconds
Started Jun 05 04:11:43 PM PDT 24
Finished Jun 05 04:11:44 PM PDT 24
Peak memory 194664 kb
Host smart-d74744b1-e155-4aa0-b3df-286daf95a8e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526192482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.3526192482
Directory /workspace/7.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.2957987529
Short name T1234
Test name
Test status
Simulation time 148637886 ps
CPU time 0.75 seconds
Started Jun 05 04:11:47 PM PDT 24
Finished Jun 05 04:11:49 PM PDT 24
Peak memory 197356 kb
Host smart-525206b3-292b-44f2-95bd-7e70a3fd84ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957987529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr
_outstanding.2957987529
Directory /workspace/7.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_errors.2062449086
Short name T1203
Test name
Test status
Simulation time 27269313 ps
CPU time 1.36 seconds
Started Jun 05 04:11:44 PM PDT 24
Finished Jun 05 04:11:46 PM PDT 24
Peak memory 200380 kb
Host smart-b217b30d-cbdf-4ab3-9c1a-ec2ffe19d36e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062449086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.2062449086
Directory /workspace/7.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.3412842666
Short name T1214
Test name
Test status
Simulation time 329172879 ps
CPU time 1.29 seconds
Started Jun 05 04:11:45 PM PDT 24
Finished Jun 05 04:11:47 PM PDT 24
Peak memory 199824 kb
Host smart-05d50cbe-e3b6-49e4-98f3-e87880c70586
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412842666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.3412842666
Directory /workspace/7.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.1354548072
Short name T1224
Test name
Test status
Simulation time 79579577 ps
CPU time 0.83 seconds
Started Jun 05 04:11:48 PM PDT 24
Finished Jun 05 04:11:50 PM PDT 24
Peak memory 199696 kb
Host smart-5cf4c7ab-549a-4ebd-8b9e-638a2bb3c3d1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354548072 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.1354548072
Directory /workspace/8.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_rw.3488033590
Short name T1273
Test name
Test status
Simulation time 131601310 ps
CPU time 0.57 seconds
Started Jun 05 04:11:47 PM PDT 24
Finished Jun 05 04:11:49 PM PDT 24
Peak memory 195712 kb
Host smart-59a0c4f8-83ab-4fff-82c0-31ae227a09f4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488033590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.3488033590
Directory /workspace/8.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.uart_intr_test.2378167253
Short name T1261
Test name
Test status
Simulation time 67488910 ps
CPU time 0.64 seconds
Started Jun 05 04:11:46 PM PDT 24
Finished Jun 05 04:11:48 PM PDT 24
Peak memory 194740 kb
Host smart-0a1cb9d4-058b-4cab-8f84-143d3bc5c985
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378167253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.2378167253
Directory /workspace/8.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.1134523843
Short name T1219
Test name
Test status
Simulation time 29718652 ps
CPU time 0.66 seconds
Started Jun 05 04:11:44 PM PDT 24
Finished Jun 05 04:11:45 PM PDT 24
Peak memory 195856 kb
Host smart-73b97065-5161-4120-9515-7323a6366925
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134523843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr
_outstanding.1134523843
Directory /workspace/8.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_errors.3121868207
Short name T1190
Test name
Test status
Simulation time 795399462 ps
CPU time 1.84 seconds
Started Jun 05 04:11:45 PM PDT 24
Finished Jun 05 04:11:48 PM PDT 24
Peak memory 200200 kb
Host smart-99ebe684-b344-41ea-a9db-875a4189cd88
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121868207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.3121868207
Directory /workspace/8.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.2696156852
Short name T1266
Test name
Test status
Simulation time 124089749 ps
CPU time 0.97 seconds
Started Jun 05 04:11:46 PM PDT 24
Finished Jun 05 04:11:48 PM PDT 24
Peak memory 199236 kb
Host smart-d4f96218-6960-4f67-8679-669d3cbc3586
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696156852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.2696156852
Directory /workspace/8.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.456930162
Short name T1248
Test name
Test status
Simulation time 93676073 ps
CPU time 0.86 seconds
Started Jun 05 04:11:47 PM PDT 24
Finished Jun 05 04:11:49 PM PDT 24
Peak memory 200120 kb
Host smart-b3b1bd08-13c1-4850-b13d-746efc8ba8e8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456930162 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.456930162
Directory /workspace/9.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_rw.779479264
Short name T85
Test name
Test status
Simulation time 14536248 ps
CPU time 0.62 seconds
Started Jun 05 04:11:46 PM PDT 24
Finished Jun 05 04:11:47 PM PDT 24
Peak memory 195712 kb
Host smart-a9522376-d79c-4696-9431-69823229162a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779479264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.779479264
Directory /workspace/9.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.uart_intr_test.3375655348
Short name T1230
Test name
Test status
Simulation time 39519737 ps
CPU time 0.58 seconds
Started Jun 05 04:11:47 PM PDT 24
Finished Jun 05 04:11:48 PM PDT 24
Peak memory 194692 kb
Host smart-e0fd7d67-bb65-4588-b816-0f5ae0ae3a9c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375655348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.3375655348
Directory /workspace/9.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.3536127977
Short name T1265
Test name
Test status
Simulation time 190147299 ps
CPU time 0.72 seconds
Started Jun 05 04:11:47 PM PDT 24
Finished Jun 05 04:11:49 PM PDT 24
Peak memory 197220 kb
Host smart-135d6a1b-3f81-49b1-87ca-15c1ba53ae10
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536127977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr
_outstanding.3536127977
Directory /workspace/9.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_errors.543274773
Short name T1193
Test name
Test status
Simulation time 45264930 ps
CPU time 1.29 seconds
Started Jun 05 04:11:44 PM PDT 24
Finished Jun 05 04:11:46 PM PDT 24
Peak memory 200388 kb
Host smart-0d7374a6-82c9-48fd-9476-8e6ac8c7d28c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543274773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.543274773
Directory /workspace/9.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.2599846620
Short name T94
Test name
Test status
Simulation time 104390570 ps
CPU time 1 seconds
Started Jun 05 04:11:47 PM PDT 24
Finished Jun 05 04:11:49 PM PDT 24
Peak memory 199388 kb
Host smart-cba31110-b4db-4595-b8a7-066804a32067
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599846620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.2599846620
Directory /workspace/9.uart_tl_intg_err/latest

Test location /workspace/coverage/default/0.uart_alert_test.141243734
Short name T1125
Test name
Test status
Simulation time 25477896 ps
CPU time 0.53 seconds
Started Jun 05 04:15:00 PM PDT 24
Finished Jun 05 04:15:01 PM PDT 24
Peak memory 194720 kb
Host smart-02be44b0-9e3e-43d8-b20e-d9a82b96ff2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141243734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.141243734
Directory /workspace/0.uart_alert_test/latest

Test location /workspace/coverage/default/0.uart_fifo_full.68122951
Short name T644
Test name
Test status
Simulation time 22819430663 ps
CPU time 40.7 seconds
Started Jun 05 04:14:58 PM PDT 24
Finished Jun 05 04:15:39 PM PDT 24
Peak memory 200388 kb
Host smart-e5f11bf6-6ebe-4927-a6b1-79ce5e14eb18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68122951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.68122951
Directory /workspace/0.uart_fifo_full/latest

Test location /workspace/coverage/default/0.uart_fifo_overflow.3488165110
Short name T979
Test name
Test status
Simulation time 144329154932 ps
CPU time 461.53 seconds
Started Jun 05 04:14:51 PM PDT 24
Finished Jun 05 04:22:34 PM PDT 24
Peak memory 200360 kb
Host smart-36aaac23-06ef-45ec-9c86-b369b25583b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488165110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.3488165110
Directory /workspace/0.uart_fifo_overflow/latest

Test location /workspace/coverage/default/0.uart_fifo_reset.2883756473
Short name T685
Test name
Test status
Simulation time 223702961579 ps
CPU time 122.41 seconds
Started Jun 05 04:14:47 PM PDT 24
Finished Jun 05 04:16:50 PM PDT 24
Peak memory 200432 kb
Host smart-01fb7c9c-2abe-4cda-a84a-b2c08ce0bd34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883756473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.2883756473
Directory /workspace/0.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_intr.1278113236
Short name T1047
Test name
Test status
Simulation time 205040576256 ps
CPU time 84.69 seconds
Started Jun 05 04:14:31 PM PDT 24
Finished Jun 05 04:15:57 PM PDT 24
Peak memory 197632 kb
Host smart-0e0a192b-d1df-4d50-aed5-daf76ae7bfb5
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278113236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.1278113236
Directory /workspace/0.uart_intr/latest

Test location /workspace/coverage/default/0.uart_long_xfer_wo_dly.3527850509
Short name T391
Test name
Test status
Simulation time 98281573189 ps
CPU time 769.05 seconds
Started Jun 05 04:14:35 PM PDT 24
Finished Jun 05 04:27:24 PM PDT 24
Peak memory 200452 kb
Host smart-d92bf2ee-813d-474d-b6d7-f53269497c11
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3527850509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.3527850509
Directory /workspace/0.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/0.uart_loopback.1081802592
Short name T342
Test name
Test status
Simulation time 11657137012 ps
CPU time 11.18 seconds
Started Jun 05 04:14:52 PM PDT 24
Finished Jun 05 04:15:04 PM PDT 24
Peak memory 200308 kb
Host smart-1954417b-9a50-464e-b289-cf79dc197a40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081802592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_loopback.1081802592
Directory /workspace/0.uart_loopback/latest

Test location /workspace/coverage/default/0.uart_noise_filter.3303460519
Short name T820
Test name
Test status
Simulation time 45503171496 ps
CPU time 96.52 seconds
Started Jun 05 04:14:55 PM PDT 24
Finished Jun 05 04:16:32 PM PDT 24
Peak memory 199520 kb
Host smart-b45b5fea-5bbe-4033-aef7-f6753b6fb456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303460519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_noise_filter.3303460519
Directory /workspace/0.uart_noise_filter/latest

Test location /workspace/coverage/default/0.uart_perf.3529284621
Short name T727
Test name
Test status
Simulation time 10670420366 ps
CPU time 531.91 seconds
Started Jun 05 04:14:51 PM PDT 24
Finished Jun 05 04:23:44 PM PDT 24
Peak memory 200600 kb
Host smart-dcf837e4-75e7-43dd-b1c5-d61a14e6d21e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3529284621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.3529284621
Directory /workspace/0.uart_perf/latest

Test location /workspace/coverage/default/0.uart_rx_oversample.1321993317
Short name T626
Test name
Test status
Simulation time 1174643649 ps
CPU time 2.02 seconds
Started Jun 05 04:14:47 PM PDT 24
Finished Jun 05 04:14:50 PM PDT 24
Peak memory 197292 kb
Host smart-a8976da4-3980-458f-8d31-ab640d7fdc34
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1321993317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.1321993317
Directory /workspace/0.uart_rx_oversample/latest

Test location /workspace/coverage/default/0.uart_rx_parity_err.688633512
Short name T163
Test name
Test status
Simulation time 31543265549 ps
CPU time 26.89 seconds
Started Jun 05 04:14:34 PM PDT 24
Finished Jun 05 04:15:02 PM PDT 24
Peak memory 200220 kb
Host smart-148c37f9-a24f-4d07-8969-5e7cc1d6607a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688633512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.688633512
Directory /workspace/0.uart_rx_parity_err/latest

Test location /workspace/coverage/default/0.uart_rx_start_bit_filter.2923867460
Short name T293
Test name
Test status
Simulation time 5103531214 ps
CPU time 2.73 seconds
Started Jun 05 04:15:05 PM PDT 24
Finished Jun 05 04:15:08 PM PDT 24
Peak memory 196416 kb
Host smart-352bf871-cd7a-4167-9374-e1d17a8cd7aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923867460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.2923867460
Directory /workspace/0.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/0.uart_sec_cm.2621809765
Short name T100
Test name
Test status
Simulation time 71060783 ps
CPU time 0.76 seconds
Started Jun 05 04:14:56 PM PDT 24
Finished Jun 05 04:14:57 PM PDT 24
Peak memory 218616 kb
Host smart-ece20c16-bf88-4f4f-acdc-79a527ed645b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621809765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.2621809765
Directory /workspace/0.uart_sec_cm/latest

Test location /workspace/coverage/default/0.uart_smoke.1676636978
Short name T372
Test name
Test status
Simulation time 753638867 ps
CPU time 1.38 seconds
Started Jun 05 04:14:32 PM PDT 24
Finished Jun 05 04:14:34 PM PDT 24
Peak memory 199068 kb
Host smart-11c33300-d0c8-482d-9e32-5228f25ecb47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676636978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_smoke.1676636978
Directory /workspace/0.uart_smoke/latest

Test location /workspace/coverage/default/0.uart_stress_all.1609585404
Short name T333
Test name
Test status
Simulation time 49334511396 ps
CPU time 98.25 seconds
Started Jun 05 04:14:51 PM PDT 24
Finished Jun 05 04:16:30 PM PDT 24
Peak memory 208796 kb
Host smart-161a2ece-6675-4b61-b23b-63c1a39a104d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609585404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.1609585404
Directory /workspace/0.uart_stress_all/latest

Test location /workspace/coverage/default/0.uart_stress_all_with_rand_reset.1612559957
Short name T741
Test name
Test status
Simulation time 196129267486 ps
CPU time 711.97 seconds
Started Jun 05 04:14:31 PM PDT 24
Finished Jun 05 04:26:24 PM PDT 24
Peak memory 225216 kb
Host smart-771de108-5fe2-4099-8c7b-7e07a0fee0c1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612559957 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.uart_stress_all_with_rand_reset.1612559957
Directory /workspace/0.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.uart_tx_ovrd.790752852
Short name T1021
Test name
Test status
Simulation time 769509096 ps
CPU time 2.83 seconds
Started Jun 05 04:14:30 PM PDT 24
Finished Jun 05 04:14:34 PM PDT 24
Peak memory 200248 kb
Host smart-54ef6cfc-545e-48e0-98dd-c66508077b8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790752852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.790752852
Directory /workspace/0.uart_tx_ovrd/latest

Test location /workspace/coverage/default/0.uart_tx_rx.2517201815
Short name T1127
Test name
Test status
Simulation time 35609261898 ps
CPU time 14.56 seconds
Started Jun 05 04:14:49 PM PDT 24
Finished Jun 05 04:15:04 PM PDT 24
Peak memory 200576 kb
Host smart-810de0ab-357f-4740-888b-8087b3deec97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517201815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.2517201815
Directory /workspace/0.uart_tx_rx/latest

Test location /workspace/coverage/default/1.uart_alert_test.3428426892
Short name T1166
Test name
Test status
Simulation time 13383935 ps
CPU time 0.59 seconds
Started Jun 05 04:14:40 PM PDT 24
Finished Jun 05 04:14:41 PM PDT 24
Peak memory 195928 kb
Host smart-ffb1f1f3-5dbd-4c62-9fd1-3dde2b0756c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428426892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.3428426892
Directory /workspace/1.uart_alert_test/latest

Test location /workspace/coverage/default/1.uart_fifo_full.1461345484
Short name T742
Test name
Test status
Simulation time 131126668860 ps
CPU time 52.69 seconds
Started Jun 05 04:14:34 PM PDT 24
Finished Jun 05 04:15:27 PM PDT 24
Peak memory 200376 kb
Host smart-a4c7d4e0-8cef-4c09-a80e-c4932e1a6c62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461345484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.1461345484
Directory /workspace/1.uart_fifo_full/latest

Test location /workspace/coverage/default/1.uart_fifo_overflow.1350264617
Short name T660
Test name
Test status
Simulation time 163103720409 ps
CPU time 37.96 seconds
Started Jun 05 04:14:53 PM PDT 24
Finished Jun 05 04:15:32 PM PDT 24
Peak memory 200424 kb
Host smart-7c587a86-8a5b-4e48-98a0-4d4560dfdcaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350264617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.1350264617
Directory /workspace/1.uart_fifo_overflow/latest

Test location /workspace/coverage/default/1.uart_long_xfer_wo_dly.3291581698
Short name T387
Test name
Test status
Simulation time 89408479920 ps
CPU time 798.78 seconds
Started Jun 05 04:15:07 PM PDT 24
Finished Jun 05 04:28:27 PM PDT 24
Peak memory 200372 kb
Host smart-ed97a32f-2483-42b1-9ab5-f25d769f1008
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3291581698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.3291581698
Directory /workspace/1.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/1.uart_loopback.3525362212
Short name T584
Test name
Test status
Simulation time 9170148990 ps
CPU time 20 seconds
Started Jun 05 04:14:41 PM PDT 24
Finished Jun 05 04:15:02 PM PDT 24
Peak memory 200344 kb
Host smart-42402b37-25a3-4645-9181-cbe0ae2bbeb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525362212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_loopback.3525362212
Directory /workspace/1.uart_loopback/latest

Test location /workspace/coverage/default/1.uart_noise_filter.3222104205
Short name T304
Test name
Test status
Simulation time 102855067604 ps
CPU time 68.06 seconds
Started Jun 05 04:14:50 PM PDT 24
Finished Jun 05 04:15:59 PM PDT 24
Peak memory 200208 kb
Host smart-1faa8d9e-8b61-48d0-ba02-d94fc1b4e695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222104205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_noise_filter.3222104205
Directory /workspace/1.uart_noise_filter/latest

Test location /workspace/coverage/default/1.uart_perf.526309045
Short name T815
Test name
Test status
Simulation time 7095404075 ps
CPU time 371.34 seconds
Started Jun 05 04:15:01 PM PDT 24
Finished Jun 05 04:21:13 PM PDT 24
Peak memory 200452 kb
Host smart-f3acc7fc-2623-4590-967d-db3a8fce6965
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=526309045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.526309045
Directory /workspace/1.uart_perf/latest

Test location /workspace/coverage/default/1.uart_rx_oversample.2609341469
Short name T998
Test name
Test status
Simulation time 4364648670 ps
CPU time 19.8 seconds
Started Jun 05 04:14:39 PM PDT 24
Finished Jun 05 04:14:59 PM PDT 24
Peak memory 198976 kb
Host smart-522a2ce3-1c38-4b27-a83d-c51436844a3e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2609341469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.2609341469
Directory /workspace/1.uart_rx_oversample/latest

Test location /workspace/coverage/default/1.uart_rx_parity_err.1098095102
Short name T722
Test name
Test status
Simulation time 75743911362 ps
CPU time 122.41 seconds
Started Jun 05 04:14:39 PM PDT 24
Finished Jun 05 04:16:42 PM PDT 24
Peak memory 200372 kb
Host smart-0cd52c6f-e2e2-41b2-a99d-a6f14e8afd22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098095102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.1098095102
Directory /workspace/1.uart_rx_parity_err/latest

Test location /workspace/coverage/default/1.uart_rx_start_bit_filter.3495579926
Short name T546
Test name
Test status
Simulation time 27817769838 ps
CPU time 49.02 seconds
Started Jun 05 04:15:03 PM PDT 24
Finished Jun 05 04:15:53 PM PDT 24
Peak memory 196104 kb
Host smart-e38f1038-7e7d-4be8-9877-335499551c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495579926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.3495579926
Directory /workspace/1.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/1.uart_smoke.4111519535
Short name T350
Test name
Test status
Simulation time 532714412 ps
CPU time 1.47 seconds
Started Jun 05 04:14:48 PM PDT 24
Finished Jun 05 04:14:50 PM PDT 24
Peak memory 200224 kb
Host smart-55068ba3-619b-4a83-8c65-8b9d67c1867f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111519535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_smoke.4111519535
Directory /workspace/1.uart_smoke/latest

Test location /workspace/coverage/default/1.uart_stress_all.1258832638
Short name T1145
Test name
Test status
Simulation time 488406383105 ps
CPU time 183.67 seconds
Started Jun 05 04:14:43 PM PDT 24
Finished Jun 05 04:17:48 PM PDT 24
Peak memory 200420 kb
Host smart-069c0658-acb6-42ec-a7f7-7243347db041
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258832638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.1258832638
Directory /workspace/1.uart_stress_all/latest

Test location /workspace/coverage/default/1.uart_stress_all_with_rand_reset.3303100466
Short name T152
Test name
Test status
Simulation time 304011975456 ps
CPU time 294.25 seconds
Started Jun 05 04:14:40 PM PDT 24
Finished Jun 05 04:19:35 PM PDT 24
Peak memory 217176 kb
Host smart-4a58d980-3929-4517-8e14-0865d7723409
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303100466 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.uart_stress_all_with_rand_reset.3303100466
Directory /workspace/1.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.uart_tx_ovrd.2090906129
Short name T358
Test name
Test status
Simulation time 978734341 ps
CPU time 3.74 seconds
Started Jun 05 04:15:00 PM PDT 24
Finished Jun 05 04:15:04 PM PDT 24
Peak memory 198796 kb
Host smart-1116f482-99d5-4547-aa62-dee584df8d00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090906129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.2090906129
Directory /workspace/1.uart_tx_ovrd/latest

Test location /workspace/coverage/default/1.uart_tx_rx.2461003783
Short name T643
Test name
Test status
Simulation time 39932841058 ps
CPU time 74.38 seconds
Started Jun 05 04:14:48 PM PDT 24
Finished Jun 05 04:16:03 PM PDT 24
Peak memory 200388 kb
Host smart-7c9dcff0-e84e-4140-9477-963fb5d8da1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461003783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.2461003783
Directory /workspace/1.uart_tx_rx/latest

Test location /workspace/coverage/default/10.uart_alert_test.2999747466
Short name T960
Test name
Test status
Simulation time 26234114 ps
CPU time 0.59 seconds
Started Jun 05 04:15:08 PM PDT 24
Finished Jun 05 04:15:10 PM PDT 24
Peak memory 195808 kb
Host smart-566c2aa4-a7fa-4cf3-8ccc-619c91d94653
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999747466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.2999747466
Directory /workspace/10.uart_alert_test/latest

Test location /workspace/coverage/default/10.uart_fifo_full.393898836
Short name T806
Test name
Test status
Simulation time 95436502271 ps
CPU time 43.11 seconds
Started Jun 05 04:15:10 PM PDT 24
Finished Jun 05 04:15:54 PM PDT 24
Peak memory 200444 kb
Host smart-7929cbb6-deb5-4261-94be-c0fc72d0709e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393898836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.393898836
Directory /workspace/10.uart_fifo_full/latest

Test location /workspace/coverage/default/10.uart_fifo_overflow.3182756899
Short name T1148
Test name
Test status
Simulation time 155227094597 ps
CPU time 12.98 seconds
Started Jun 05 04:14:56 PM PDT 24
Finished Jun 05 04:15:09 PM PDT 24
Peak memory 200360 kb
Host smart-4a16b25a-e50d-4f3b-b071-771f23da3f9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182756899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.3182756899
Directory /workspace/10.uart_fifo_overflow/latest

Test location /workspace/coverage/default/10.uart_fifo_reset.959615212
Short name T562
Test name
Test status
Simulation time 63913681201 ps
CPU time 91.39 seconds
Started Jun 05 04:14:59 PM PDT 24
Finished Jun 05 04:16:31 PM PDT 24
Peak memory 200488 kb
Host smart-64fca407-4da7-4efb-8acd-e63be9dc86d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959615212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.959615212
Directory /workspace/10.uart_fifo_reset/latest

Test location /workspace/coverage/default/10.uart_intr.2118573320
Short name T573
Test name
Test status
Simulation time 9959705191 ps
CPU time 16.42 seconds
Started Jun 05 04:14:59 PM PDT 24
Finished Jun 05 04:15:16 PM PDT 24
Peak memory 198124 kb
Host smart-08152090-6023-4998-b8ab-f9052e0e6626
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118573320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.2118573320
Directory /workspace/10.uart_intr/latest

Test location /workspace/coverage/default/10.uart_long_xfer_wo_dly.2261374036
Short name T710
Test name
Test status
Simulation time 132223479614 ps
CPU time 346.36 seconds
Started Jun 05 04:14:58 PM PDT 24
Finished Jun 05 04:20:45 PM PDT 24
Peak memory 200440 kb
Host smart-2842889c-be38-4136-bc12-47e10084305e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2261374036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.2261374036
Directory /workspace/10.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/10.uart_loopback.3988546952
Short name T603
Test name
Test status
Simulation time 6034997969 ps
CPU time 14.23 seconds
Started Jun 05 04:14:57 PM PDT 24
Finished Jun 05 04:15:12 PM PDT 24
Peak memory 199272 kb
Host smart-6831e5ac-342f-4817-bd8a-73921a8f6d14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988546952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_loopback.3988546952
Directory /workspace/10.uart_loopback/latest

Test location /workspace/coverage/default/10.uart_noise_filter.1727041995
Short name T1011
Test name
Test status
Simulation time 110033606151 ps
CPU time 53.57 seconds
Started Jun 05 04:14:56 PM PDT 24
Finished Jun 05 04:15:51 PM PDT 24
Peak memory 199876 kb
Host smart-4dffad41-e37c-4ee6-88d4-448ae04b1361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727041995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_noise_filter.1727041995
Directory /workspace/10.uart_noise_filter/latest

Test location /workspace/coverage/default/10.uart_perf.2028132746
Short name T365
Test name
Test status
Simulation time 18516704944 ps
CPU time 200.42 seconds
Started Jun 05 04:15:11 PM PDT 24
Finished Jun 05 04:18:33 PM PDT 24
Peak memory 200412 kb
Host smart-7840d5a1-8959-479a-80f2-a84febd5652c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2028132746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.2028132746
Directory /workspace/10.uart_perf/latest

Test location /workspace/coverage/default/10.uart_rx_oversample.2458965760
Short name T6
Test name
Test status
Simulation time 4346862760 ps
CPU time 18.41 seconds
Started Jun 05 04:15:09 PM PDT 24
Finished Jun 05 04:15:29 PM PDT 24
Peak memory 198544 kb
Host smart-9c98ccaf-5219-44f4-ad99-b046dd6acdd6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2458965760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.2458965760
Directory /workspace/10.uart_rx_oversample/latest

Test location /workspace/coverage/default/10.uart_rx_parity_err.3041396735
Short name T529
Test name
Test status
Simulation time 23642944847 ps
CPU time 38.8 seconds
Started Jun 05 04:15:07 PM PDT 24
Finished Jun 05 04:15:47 PM PDT 24
Peak memory 200116 kb
Host smart-8034fe3e-9794-4eea-a2a6-f682994212fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041396735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.3041396735
Directory /workspace/10.uart_rx_parity_err/latest

Test location /workspace/coverage/default/10.uart_rx_start_bit_filter.1350556212
Short name T265
Test name
Test status
Simulation time 40042885491 ps
CPU time 15.86 seconds
Started Jun 05 04:14:55 PM PDT 24
Finished Jun 05 04:15:12 PM PDT 24
Peak memory 196448 kb
Host smart-8047774f-51d5-4732-b9ee-087c873bf9db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350556212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.1350556212
Directory /workspace/10.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/10.uart_smoke.3571899490
Short name T726
Test name
Test status
Simulation time 487456199 ps
CPU time 1.59 seconds
Started Jun 05 04:15:06 PM PDT 24
Finished Jun 05 04:15:09 PM PDT 24
Peak memory 200308 kb
Host smart-977c5573-0254-4069-9d54-2afac12f2073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571899490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_smoke.3571899490
Directory /workspace/10.uart_smoke/latest

Test location /workspace/coverage/default/10.uart_stress_all_with_rand_reset.830139700
Short name T299
Test name
Test status
Simulation time 26922728240 ps
CPU time 287.68 seconds
Started Jun 05 04:15:04 PM PDT 24
Finished Jun 05 04:19:53 PM PDT 24
Peak memory 216872 kb
Host smart-da2735d0-ad28-430b-b265-af8a2d35709c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830139700 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 10.uart_stress_all_with_rand_reset.830139700
Directory /workspace/10.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.uart_tx_ovrd.754185422
Short name T900
Test name
Test status
Simulation time 1236360576 ps
CPU time 2.74 seconds
Started Jun 05 04:15:06 PM PDT 24
Finished Jun 05 04:15:10 PM PDT 24
Peak memory 200064 kb
Host smart-85d8d8e6-07bf-4453-85e1-e2021e21efab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754185422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.754185422
Directory /workspace/10.uart_tx_ovrd/latest

Test location /workspace/coverage/default/10.uart_tx_rx.2463576715
Short name T329
Test name
Test status
Simulation time 51485608388 ps
CPU time 18 seconds
Started Jun 05 04:15:11 PM PDT 24
Finished Jun 05 04:15:30 PM PDT 24
Peak memory 200360 kb
Host smart-bbb1531c-c51a-47a8-a6d2-47b796500a87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463576715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.2463576715
Directory /workspace/10.uart_tx_rx/latest

Test location /workspace/coverage/default/100.uart_fifo_reset.1533729966
Short name T237
Test name
Test status
Simulation time 26699064218 ps
CPU time 22.2 seconds
Started Jun 05 04:18:04 PM PDT 24
Finished Jun 05 04:18:26 PM PDT 24
Peak memory 200460 kb
Host smart-ffd1e742-ad7e-4e90-97ff-51c8c4b7a262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533729966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.1533729966
Directory /workspace/100.uart_fifo_reset/latest

Test location /workspace/coverage/default/101.uart_fifo_reset.508725043
Short name T1135
Test name
Test status
Simulation time 27314985528 ps
CPU time 48.21 seconds
Started Jun 05 04:18:01 PM PDT 24
Finished Jun 05 04:18:50 PM PDT 24
Peak memory 200460 kb
Host smart-b6033a9f-2306-42e8-bb4b-32f8742c41ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508725043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.508725043
Directory /workspace/101.uart_fifo_reset/latest

Test location /workspace/coverage/default/102.uart_fifo_reset.2858473265
Short name T533
Test name
Test status
Simulation time 28209375407 ps
CPU time 58.06 seconds
Started Jun 05 04:18:00 PM PDT 24
Finished Jun 05 04:18:59 PM PDT 24
Peak memory 200388 kb
Host smart-0c9a5700-2505-4590-934c-b7a35d631e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858473265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.2858473265
Directory /workspace/102.uart_fifo_reset/latest

Test location /workspace/coverage/default/103.uart_fifo_reset.4241494213
Short name T1078
Test name
Test status
Simulation time 160999337686 ps
CPU time 179.09 seconds
Started Jun 05 04:18:02 PM PDT 24
Finished Jun 05 04:21:02 PM PDT 24
Peak memory 200332 kb
Host smart-66f3e332-73b0-4888-8e07-57d0982a6e0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241494213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.4241494213
Directory /workspace/103.uart_fifo_reset/latest

Test location /workspace/coverage/default/104.uart_fifo_reset.1697027812
Short name T1067
Test name
Test status
Simulation time 294709874429 ps
CPU time 35.82 seconds
Started Jun 05 04:18:01 PM PDT 24
Finished Jun 05 04:18:38 PM PDT 24
Peak memory 200380 kb
Host smart-a9dfba76-b097-4b81-a42a-769456832090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697027812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.1697027812
Directory /workspace/104.uart_fifo_reset/latest

Test location /workspace/coverage/default/105.uart_fifo_reset.2759319166
Short name T34
Test name
Test status
Simulation time 18665213174 ps
CPU time 23.23 seconds
Started Jun 05 04:18:01 PM PDT 24
Finished Jun 05 04:18:25 PM PDT 24
Peak memory 200132 kb
Host smart-1601ccb7-84c3-46fc-8954-281e50abbf4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759319166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.2759319166
Directory /workspace/105.uart_fifo_reset/latest

Test location /workspace/coverage/default/106.uart_fifo_reset.986592321
Short name T523
Test name
Test status
Simulation time 110198389145 ps
CPU time 70.78 seconds
Started Jun 05 04:18:00 PM PDT 24
Finished Jun 05 04:19:11 PM PDT 24
Peak memory 200432 kb
Host smart-b0bc8845-2ae3-49a1-8282-dbf658bdf171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986592321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.986592321
Directory /workspace/106.uart_fifo_reset/latest

Test location /workspace/coverage/default/109.uart_fifo_reset.1235524368
Short name T600
Test name
Test status
Simulation time 209633609418 ps
CPU time 127.36 seconds
Started Jun 05 04:18:04 PM PDT 24
Finished Jun 05 04:20:11 PM PDT 24
Peak memory 200460 kb
Host smart-91dbaf94-652e-42fd-a22d-fe02f504c2e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235524368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.1235524368
Directory /workspace/109.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_alert_test.126869647
Short name T574
Test name
Test status
Simulation time 12371916 ps
CPU time 0.54 seconds
Started Jun 05 04:15:09 PM PDT 24
Finished Jun 05 04:15:11 PM PDT 24
Peak memory 195820 kb
Host smart-ee6017f3-640a-4564-bf4c-e161a3661a0d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126869647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.126869647
Directory /workspace/11.uart_alert_test/latest

Test location /workspace/coverage/default/11.uart_fifo_full.2257757111
Short name T823
Test name
Test status
Simulation time 35880650913 ps
CPU time 132.22 seconds
Started Jun 05 04:14:59 PM PDT 24
Finished Jun 05 04:17:12 PM PDT 24
Peak memory 200392 kb
Host smart-1bab7d8d-cd87-4d8a-8229-3884f916453a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257757111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.2257757111
Directory /workspace/11.uart_fifo_full/latest

Test location /workspace/coverage/default/11.uart_fifo_overflow.4188139354
Short name T516
Test name
Test status
Simulation time 52802265036 ps
CPU time 25.06 seconds
Started Jun 05 04:15:10 PM PDT 24
Finished Jun 05 04:15:37 PM PDT 24
Peak memory 200280 kb
Host smart-d4bb1070-80a7-4887-a2e3-722ad678f030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188139354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.4188139354
Directory /workspace/11.uart_fifo_overflow/latest

Test location /workspace/coverage/default/11.uart_intr.4207947860
Short name T663
Test name
Test status
Simulation time 3617383467 ps
CPU time 5.86 seconds
Started Jun 05 04:15:10 PM PDT 24
Finished Jun 05 04:15:17 PM PDT 24
Peak memory 196892 kb
Host smart-873c48be-3060-43b3-b493-c3e8d48119a9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207947860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.4207947860
Directory /workspace/11.uart_intr/latest

Test location /workspace/coverage/default/11.uart_long_xfer_wo_dly.4242915630
Short name T421
Test name
Test status
Simulation time 78482153450 ps
CPU time 421 seconds
Started Jun 05 04:15:00 PM PDT 24
Finished Jun 05 04:22:01 PM PDT 24
Peak memory 200384 kb
Host smart-e6d5e710-3d91-4a33-8049-ab50ff2075f1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4242915630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.4242915630
Directory /workspace/11.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/11.uart_loopback.956789503
Short name T536
Test name
Test status
Simulation time 8121916555 ps
CPU time 2.96 seconds
Started Jun 05 04:15:09 PM PDT 24
Finished Jun 05 04:15:13 PM PDT 24
Peak memory 199632 kb
Host smart-6d9d1c66-185c-457e-80f8-8ae0574acd3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956789503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_loopback.956789503
Directory /workspace/11.uart_loopback/latest

Test location /workspace/coverage/default/11.uart_noise_filter.2294543438
Short name T572
Test name
Test status
Simulation time 80436508686 ps
CPU time 163.7 seconds
Started Jun 05 04:15:03 PM PDT 24
Finished Jun 05 04:17:48 PM PDT 24
Peak memory 200588 kb
Host smart-9906e1d8-362e-4732-8d69-16c0c079f535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294543438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_noise_filter.2294543438
Directory /workspace/11.uart_noise_filter/latest

Test location /workspace/coverage/default/11.uart_perf.739139524
Short name T769
Test name
Test status
Simulation time 18341309154 ps
CPU time 585.67 seconds
Started Jun 05 04:15:08 PM PDT 24
Finished Jun 05 04:24:55 PM PDT 24
Peak memory 200364 kb
Host smart-0675e517-838b-463d-9bd6-32fb6f6e5fb3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=739139524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.739139524
Directory /workspace/11.uart_perf/latest

Test location /workspace/coverage/default/11.uart_rx_oversample.3194685667
Short name T463
Test name
Test status
Simulation time 5088740438 ps
CPU time 9.14 seconds
Started Jun 05 04:15:10 PM PDT 24
Finished Jun 05 04:15:20 PM PDT 24
Peak memory 198500 kb
Host smart-85d064ae-941e-49f5-a2fa-38825e1b6632
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3194685667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.3194685667
Directory /workspace/11.uart_rx_oversample/latest

Test location /workspace/coverage/default/11.uart_rx_parity_err.3626757300
Short name T559
Test name
Test status
Simulation time 234793992104 ps
CPU time 359.58 seconds
Started Jun 05 04:15:11 PM PDT 24
Finished Jun 05 04:21:12 PM PDT 24
Peak memory 200364 kb
Host smart-d50d704e-bdef-4cf1-994e-f35de81fe843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626757300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.3626757300
Directory /workspace/11.uart_rx_parity_err/latest

Test location /workspace/coverage/default/11.uart_rx_start_bit_filter.753406290
Short name T364
Test name
Test status
Simulation time 554411283 ps
CPU time 1.12 seconds
Started Jun 05 04:15:07 PM PDT 24
Finished Jun 05 04:15:10 PM PDT 24
Peak memory 195808 kb
Host smart-5b6b704f-9ad9-4090-b296-386931ceba3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753406290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.753406290
Directory /workspace/11.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/11.uart_smoke.1469074058
Short name T669
Test name
Test status
Simulation time 6079770118 ps
CPU time 17.74 seconds
Started Jun 05 04:14:55 PM PDT 24
Finished Jun 05 04:15:14 PM PDT 24
Peak memory 200392 kb
Host smart-7bacd4e9-5bed-4804-83fb-2b27a64725e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469074058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_smoke.1469074058
Directory /workspace/11.uart_smoke/latest

Test location /workspace/coverage/default/11.uart_stress_all_with_rand_reset.2931484070
Short name T59
Test name
Test status
Simulation time 29262456103 ps
CPU time 262.27 seconds
Started Jun 05 04:15:12 PM PDT 24
Finished Jun 05 04:19:35 PM PDT 24
Peak memory 216212 kb
Host smart-dbec7e92-c7cf-4769-8dae-0bdb2c2102e5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931484070 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 11.uart_stress_all_with_rand_reset.2931484070
Directory /workspace/11.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.uart_tx_ovrd.1729963922
Short name T883
Test name
Test status
Simulation time 7973423052 ps
CPU time 8.66 seconds
Started Jun 05 04:15:11 PM PDT 24
Finished Jun 05 04:15:21 PM PDT 24
Peak memory 200228 kb
Host smart-aabfcc34-d209-4d2a-af5c-03269215e213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729963922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.1729963922
Directory /workspace/11.uart_tx_ovrd/latest

Test location /workspace/coverage/default/11.uart_tx_rx.2219027392
Short name T397
Test name
Test status
Simulation time 47711458250 ps
CPU time 81.87 seconds
Started Jun 05 04:15:12 PM PDT 24
Finished Jun 05 04:16:35 PM PDT 24
Peak memory 200360 kb
Host smart-06c91d75-995b-45fb-aa28-c930d8fcacb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219027392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.2219027392
Directory /workspace/11.uart_tx_rx/latest

Test location /workspace/coverage/default/111.uart_fifo_reset.2571666059
Short name T120
Test name
Test status
Simulation time 68255765091 ps
CPU time 149.12 seconds
Started Jun 05 04:18:02 PM PDT 24
Finished Jun 05 04:20:32 PM PDT 24
Peak memory 200444 kb
Host smart-b6907e19-a83f-49e4-98a8-bad4150139e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571666059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.2571666059
Directory /workspace/111.uart_fifo_reset/latest

Test location /workspace/coverage/default/112.uart_fifo_reset.1687201916
Short name T313
Test name
Test status
Simulation time 27749565059 ps
CPU time 50.69 seconds
Started Jun 05 04:18:02 PM PDT 24
Finished Jun 05 04:18:53 PM PDT 24
Peak memory 200420 kb
Host smart-145e2ede-20e2-44ed-a792-6e8bd30aac5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687201916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.1687201916
Directory /workspace/112.uart_fifo_reset/latest

Test location /workspace/coverage/default/113.uart_fifo_reset.382673148
Short name T1113
Test name
Test status
Simulation time 33247217433 ps
CPU time 56.76 seconds
Started Jun 05 04:18:01 PM PDT 24
Finished Jun 05 04:18:59 PM PDT 24
Peak memory 200316 kb
Host smart-f0ee152a-a7cb-46f5-99ef-a702e84bc7c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382673148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.382673148
Directory /workspace/113.uart_fifo_reset/latest

Test location /workspace/coverage/default/114.uart_fifo_reset.3679854012
Short name T215
Test name
Test status
Simulation time 32524333167 ps
CPU time 42.16 seconds
Started Jun 05 04:18:11 PM PDT 24
Finished Jun 05 04:18:54 PM PDT 24
Peak memory 200460 kb
Host smart-9e203a7a-4d25-476a-b834-acd251b65ad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679854012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.3679854012
Directory /workspace/114.uart_fifo_reset/latest

Test location /workspace/coverage/default/115.uart_fifo_reset.2098432801
Short name T528
Test name
Test status
Simulation time 117480937465 ps
CPU time 241.69 seconds
Started Jun 05 04:18:10 PM PDT 24
Finished Jun 05 04:22:12 PM PDT 24
Peak memory 200332 kb
Host smart-4a480bc5-0733-44f6-add1-a453a2b109cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098432801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.2098432801
Directory /workspace/115.uart_fifo_reset/latest

Test location /workspace/coverage/default/116.uart_fifo_reset.4047677770
Short name T964
Test name
Test status
Simulation time 26800002268 ps
CPU time 22.68 seconds
Started Jun 05 04:18:14 PM PDT 24
Finished Jun 05 04:18:37 PM PDT 24
Peak memory 200384 kb
Host smart-964ebef1-5247-4cea-84bc-d27eda2f2ae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047677770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.4047677770
Directory /workspace/116.uart_fifo_reset/latest

Test location /workspace/coverage/default/117.uart_fifo_reset.415054210
Short name T233
Test name
Test status
Simulation time 99701218972 ps
CPU time 171.59 seconds
Started Jun 05 04:18:11 PM PDT 24
Finished Jun 05 04:21:03 PM PDT 24
Peak memory 200428 kb
Host smart-7aba1927-98a0-4199-a5d6-30d2af4c1c88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415054210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.415054210
Directory /workspace/117.uart_fifo_reset/latest

Test location /workspace/coverage/default/118.uart_fifo_reset.3140840517
Short name T578
Test name
Test status
Simulation time 172230353137 ps
CPU time 282.06 seconds
Started Jun 05 04:18:10 PM PDT 24
Finished Jun 05 04:22:53 PM PDT 24
Peak memory 200476 kb
Host smart-a09300b1-6fb1-4509-899f-5bdc29c10e73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140840517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.3140840517
Directory /workspace/118.uart_fifo_reset/latest

Test location /workspace/coverage/default/119.uart_fifo_reset.1030333242
Short name T918
Test name
Test status
Simulation time 113915858593 ps
CPU time 37.23 seconds
Started Jun 05 04:18:11 PM PDT 24
Finished Jun 05 04:18:49 PM PDT 24
Peak memory 200440 kb
Host smart-787f27a8-ba80-4358-9e09-926b5625dad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030333242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.1030333242
Directory /workspace/119.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_alert_test.3677560506
Short name T550
Test name
Test status
Simulation time 71827468 ps
CPU time 0.55 seconds
Started Jun 05 04:15:07 PM PDT 24
Finished Jun 05 04:15:08 PM PDT 24
Peak memory 195836 kb
Host smart-b2feaa4d-6cd5-4d77-9f21-da92e310bdc6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677560506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.3677560506
Directory /workspace/12.uart_alert_test/latest

Test location /workspace/coverage/default/12.uart_fifo_full.1018634222
Short name T314
Test name
Test status
Simulation time 34896527158 ps
CPU time 18.97 seconds
Started Jun 05 04:15:04 PM PDT 24
Finished Jun 05 04:15:23 PM PDT 24
Peak memory 200368 kb
Host smart-1ccce01e-04b8-4dc0-a0e0-a33e5096e552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018634222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.1018634222
Directory /workspace/12.uart_fifo_full/latest

Test location /workspace/coverage/default/12.uart_intr.2130213883
Short name T388
Test name
Test status
Simulation time 3118733600 ps
CPU time 1.02 seconds
Started Jun 05 04:15:07 PM PDT 24
Finished Jun 05 04:15:09 PM PDT 24
Peak memory 197208 kb
Host smart-4ff4ec7f-17ec-4356-8fea-4f8a35aa0914
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130213883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.2130213883
Directory /workspace/12.uart_intr/latest

Test location /workspace/coverage/default/12.uart_long_xfer_wo_dly.958019292
Short name T865
Test name
Test status
Simulation time 146154738011 ps
CPU time 973.23 seconds
Started Jun 05 04:15:17 PM PDT 24
Finished Jun 05 04:31:31 PM PDT 24
Peak memory 200332 kb
Host smart-ae9a1084-970e-4e1f-aed6-c020cdd43c27
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=958019292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.958019292
Directory /workspace/12.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/12.uart_loopback.912280497
Short name T349
Test name
Test status
Simulation time 2893882190 ps
CPU time 1.09 seconds
Started Jun 05 04:15:16 PM PDT 24
Finished Jun 05 04:15:18 PM PDT 24
Peak memory 196784 kb
Host smart-955f995d-074a-460e-b3a9-ea96e9762c03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912280497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_loopback.912280497
Directory /workspace/12.uart_loopback/latest

Test location /workspace/coverage/default/12.uart_noise_filter.2854673579
Short name T41
Test name
Test status
Simulation time 32674120590 ps
CPU time 27.5 seconds
Started Jun 05 04:15:26 PM PDT 24
Finished Jun 05 04:15:59 PM PDT 24
Peak memory 200576 kb
Host smart-dc859afa-3534-45c9-9137-febbc3fad1d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854673579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_noise_filter.2854673579
Directory /workspace/12.uart_noise_filter/latest

Test location /workspace/coverage/default/12.uart_perf.1947561087
Short name T356
Test name
Test status
Simulation time 10076875284 ps
CPU time 92.56 seconds
Started Jun 05 04:15:11 PM PDT 24
Finished Jun 05 04:16:45 PM PDT 24
Peak memory 200408 kb
Host smart-f192df17-560d-44eb-a452-145b510c8846
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1947561087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.1947561087
Directory /workspace/12.uart_perf/latest

Test location /workspace/coverage/default/12.uart_rx_oversample.2446428745
Short name T788
Test name
Test status
Simulation time 2411506415 ps
CPU time 7.71 seconds
Started Jun 05 04:15:05 PM PDT 24
Finished Jun 05 04:15:14 PM PDT 24
Peak memory 199524 kb
Host smart-1a07b6ba-2dbd-4708-a266-730c82d691d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2446428745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.2446428745
Directory /workspace/12.uart_rx_oversample/latest

Test location /workspace/coverage/default/12.uart_rx_parity_err.3890394168
Short name T1027
Test name
Test status
Simulation time 77475101806 ps
CPU time 37.05 seconds
Started Jun 05 04:15:14 PM PDT 24
Finished Jun 05 04:15:52 PM PDT 24
Peak memory 200400 kb
Host smart-4df2cbb9-0462-4c90-beb3-073c20e381cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890394168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.3890394168
Directory /workspace/12.uart_rx_parity_err/latest

Test location /workspace/coverage/default/12.uart_rx_start_bit_filter.3737547946
Short name T1005
Test name
Test status
Simulation time 5378077640 ps
CPU time 8.53 seconds
Started Jun 05 04:15:15 PM PDT 24
Finished Jun 05 04:15:25 PM PDT 24
Peak memory 196440 kb
Host smart-d82024a2-c951-47c5-8583-855f7e8d5436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737547946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.3737547946
Directory /workspace/12.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/12.uart_smoke.3019609331
Short name T298
Test name
Test status
Simulation time 5797210159 ps
CPU time 14.38 seconds
Started Jun 05 04:15:09 PM PDT 24
Finished Jun 05 04:15:25 PM PDT 24
Peak memory 200236 kb
Host smart-c2540fa4-fce9-473e-afa9-d886aae1e971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019609331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_smoke.3019609331
Directory /workspace/12.uart_smoke/latest

Test location /workspace/coverage/default/12.uart_stress_all.3739292890
Short name T1046
Test name
Test status
Simulation time 86090710664 ps
CPU time 151 seconds
Started Jun 05 04:15:08 PM PDT 24
Finished Jun 05 04:17:41 PM PDT 24
Peak memory 200656 kb
Host smart-6dd02a40-1d92-4940-b434-dd48ba7e47c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739292890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.3739292890
Directory /workspace/12.uart_stress_all/latest

Test location /workspace/coverage/default/12.uart_tx_ovrd.58396166
Short name T1036
Test name
Test status
Simulation time 6558337705 ps
CPU time 6.67 seconds
Started Jun 05 04:15:08 PM PDT 24
Finished Jun 05 04:15:16 PM PDT 24
Peak memory 200228 kb
Host smart-3b6d15bd-07b3-43e0-9c9e-55ad87608f2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58396166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.58396166
Directory /workspace/12.uart_tx_ovrd/latest

Test location /workspace/coverage/default/12.uart_tx_rx.159543297
Short name T454
Test name
Test status
Simulation time 12316801151 ps
CPU time 20.2 seconds
Started Jun 05 04:15:10 PM PDT 24
Finished Jun 05 04:15:32 PM PDT 24
Peak memory 200324 kb
Host smart-867ca9ab-13a8-429f-a23f-f8ffe64a4b73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159543297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.159543297
Directory /workspace/12.uart_tx_rx/latest

Test location /workspace/coverage/default/120.uart_fifo_reset.1000787331
Short name T765
Test name
Test status
Simulation time 125166886159 ps
CPU time 174.5 seconds
Started Jun 05 04:18:13 PM PDT 24
Finished Jun 05 04:21:08 PM PDT 24
Peak memory 200408 kb
Host smart-1813f436-8122-4e95-8e02-86d827c24143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000787331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.1000787331
Directory /workspace/120.uart_fifo_reset/latest

Test location /workspace/coverage/default/123.uart_fifo_reset.21329330
Short name T1157
Test name
Test status
Simulation time 46825269265 ps
CPU time 21.8 seconds
Started Jun 05 04:18:12 PM PDT 24
Finished Jun 05 04:18:34 PM PDT 24
Peak memory 200236 kb
Host smart-2132d570-0cd1-4ad0-8b02-708ad0f35bcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21329330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.21329330
Directory /workspace/123.uart_fifo_reset/latest

Test location /workspace/coverage/default/126.uart_fifo_reset.321740234
Short name T732
Test name
Test status
Simulation time 22532095984 ps
CPU time 23.15 seconds
Started Jun 05 04:18:12 PM PDT 24
Finished Jun 05 04:18:35 PM PDT 24
Peak memory 200292 kb
Host smart-39d53f1c-059d-4798-b7dd-d88808d639fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321740234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.321740234
Directory /workspace/126.uart_fifo_reset/latest

Test location /workspace/coverage/default/127.uart_fifo_reset.2621630544
Short name T143
Test name
Test status
Simulation time 140931328699 ps
CPU time 128.82 seconds
Started Jun 05 04:18:14 PM PDT 24
Finished Jun 05 04:20:23 PM PDT 24
Peak memory 200380 kb
Host smart-9a57559d-c536-4e0b-9179-013d6cb58682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621630544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.2621630544
Directory /workspace/127.uart_fifo_reset/latest

Test location /workspace/coverage/default/128.uart_fifo_reset.4258681834
Short name T305
Test name
Test status
Simulation time 28985783563 ps
CPU time 143.68 seconds
Started Jun 05 04:18:09 PM PDT 24
Finished Jun 05 04:20:33 PM PDT 24
Peak memory 200364 kb
Host smart-00dc7497-6012-45f0-959f-51ab776216d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258681834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.4258681834
Directory /workspace/128.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_alert_test.72938409
Short name T844
Test name
Test status
Simulation time 40840977 ps
CPU time 0.55 seconds
Started Jun 05 04:15:35 PM PDT 24
Finished Jun 05 04:15:36 PM PDT 24
Peak memory 195136 kb
Host smart-6e771e55-35ac-4afa-9c9b-8187cf4e484f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72938409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.72938409
Directory /workspace/13.uart_alert_test/latest

Test location /workspace/coverage/default/13.uart_fifo_full.2448145051
Short name T640
Test name
Test status
Simulation time 29916583906 ps
CPU time 27.71 seconds
Started Jun 05 04:15:10 PM PDT 24
Finished Jun 05 04:15:39 PM PDT 24
Peak memory 200600 kb
Host smart-a9c7d740-4ac9-4083-9d2a-a8d8b24908cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448145051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.2448145051
Directory /workspace/13.uart_fifo_full/latest

Test location /workspace/coverage/default/13.uart_fifo_overflow.1673778031
Short name T1131
Test name
Test status
Simulation time 62446888264 ps
CPU time 60.03 seconds
Started Jun 05 04:15:09 PM PDT 24
Finished Jun 05 04:16:10 PM PDT 24
Peak memory 200108 kb
Host smart-20090dd8-35d4-47d7-959d-91025b86de4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673778031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.1673778031
Directory /workspace/13.uart_fifo_overflow/latest

Test location /workspace/coverage/default/13.uart_fifo_reset.1052487102
Short name T713
Test name
Test status
Simulation time 99454022942 ps
CPU time 236.95 seconds
Started Jun 05 04:15:09 PM PDT 24
Finished Jun 05 04:19:07 PM PDT 24
Peak memory 200440 kb
Host smart-1b1befc3-958b-4993-8868-54c5d5dea360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052487102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.1052487102
Directory /workspace/13.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_intr.2667546343
Short name T647
Test name
Test status
Simulation time 262757918676 ps
CPU time 86.77 seconds
Started Jun 05 04:15:14 PM PDT 24
Finished Jun 05 04:16:42 PM PDT 24
Peak memory 197504 kb
Host smart-88cef7de-c740-4140-a0e1-dea5c70b0607
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667546343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.2667546343
Directory /workspace/13.uart_intr/latest

Test location /workspace/coverage/default/13.uart_long_xfer_wo_dly.3679424986
Short name T352
Test name
Test status
Simulation time 129999656507 ps
CPU time 1215.02 seconds
Started Jun 05 04:15:09 PM PDT 24
Finished Jun 05 04:35:26 PM PDT 24
Peak memory 200444 kb
Host smart-e662a9d8-e082-4581-9f72-91ae40b66216
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3679424986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.3679424986
Directory /workspace/13.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/13.uart_loopback.767976871
Short name T861
Test name
Test status
Simulation time 6119733333 ps
CPU time 1.46 seconds
Started Jun 05 04:15:08 PM PDT 24
Finished Jun 05 04:15:11 PM PDT 24
Peak memory 198604 kb
Host smart-c5b7491c-b227-49ca-ad71-ce1f1edce9c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767976871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_loopback.767976871
Directory /workspace/13.uart_loopback/latest

Test location /workspace/coverage/default/13.uart_noise_filter.3690641639
Short name T509
Test name
Test status
Simulation time 97504586458 ps
CPU time 212.7 seconds
Started Jun 05 04:15:14 PM PDT 24
Finished Jun 05 04:18:48 PM PDT 24
Peak memory 200592 kb
Host smart-1c4a58b2-bd70-4751-beb6-c8098972cc67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690641639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_noise_filter.3690641639
Directory /workspace/13.uart_noise_filter/latest

Test location /workspace/coverage/default/13.uart_perf.3702840116
Short name T542
Test name
Test status
Simulation time 24193289840 ps
CPU time 1327.41 seconds
Started Jun 05 04:15:10 PM PDT 24
Finished Jun 05 04:37:19 PM PDT 24
Peak memory 200412 kb
Host smart-fcaa96de-8be1-452f-ab40-9d1c9745926c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3702840116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.3702840116
Directory /workspace/13.uart_perf/latest

Test location /workspace/coverage/default/13.uart_rx_oversample.4246396247
Short name T401
Test name
Test status
Simulation time 7491413562 ps
CPU time 66.62 seconds
Started Jun 05 04:15:06 PM PDT 24
Finished Jun 05 04:16:13 PM PDT 24
Peak memory 199732 kb
Host smart-e7c29595-ee6f-4a90-ac26-f2b10d4bfc4b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4246396247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.4246396247
Directory /workspace/13.uart_rx_oversample/latest

Test location /workspace/coverage/default/13.uart_rx_parity_err.1555532719
Short name T1163
Test name
Test status
Simulation time 21724787399 ps
CPU time 18.71 seconds
Started Jun 05 04:15:16 PM PDT 24
Finished Jun 05 04:15:36 PM PDT 24
Peak memory 200208 kb
Host smart-94190329-df17-4d50-8887-5884177fdb1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555532719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.1555532719
Directory /workspace/13.uart_rx_parity_err/latest

Test location /workspace/coverage/default/13.uart_rx_start_bit_filter.1226466689
Short name T288
Test name
Test status
Simulation time 3301299023 ps
CPU time 6.1 seconds
Started Jun 05 04:15:06 PM PDT 24
Finished Jun 05 04:15:13 PM PDT 24
Peak memory 196320 kb
Host smart-2191d86d-6e55-4419-9855-2520f2c9e3d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226466689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.1226466689
Directory /workspace/13.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/13.uart_stress_all_with_rand_reset.1498752383
Short name T111
Test name
Test status
Simulation time 65510866617 ps
CPU time 741.72 seconds
Started Jun 05 04:15:07 PM PDT 24
Finished Jun 05 04:27:29 PM PDT 24
Peak memory 217064 kb
Host smart-04a3435b-2c6d-4b99-b77b-6d733142b724
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498752383 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 13.uart_stress_all_with_rand_reset.1498752383
Directory /workspace/13.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.uart_tx_ovrd.1350675001
Short name T783
Test name
Test status
Simulation time 1601355084 ps
CPU time 3.21 seconds
Started Jun 05 04:15:11 PM PDT 24
Finished Jun 05 04:15:15 PM PDT 24
Peak memory 198700 kb
Host smart-61ea64c4-8585-48a5-ae25-34c48d67bf16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350675001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.1350675001
Directory /workspace/13.uart_tx_ovrd/latest

Test location /workspace/coverage/default/13.uart_tx_rx.2423667876
Short name T1065
Test name
Test status
Simulation time 77239026890 ps
CPU time 21.13 seconds
Started Jun 05 04:15:10 PM PDT 24
Finished Jun 05 04:15:33 PM PDT 24
Peak memory 200388 kb
Host smart-4296aa6d-7947-4a86-ad94-16de2ad901ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423667876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.2423667876
Directory /workspace/13.uart_tx_rx/latest

Test location /workspace/coverage/default/130.uart_fifo_reset.3261884127
Short name T655
Test name
Test status
Simulation time 14141849575 ps
CPU time 12.02 seconds
Started Jun 05 04:18:10 PM PDT 24
Finished Jun 05 04:18:23 PM PDT 24
Peak memory 199072 kb
Host smart-28f3ffee-a781-4e48-bf03-57e031248367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261884127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.3261884127
Directory /workspace/130.uart_fifo_reset/latest

Test location /workspace/coverage/default/131.uart_fifo_reset.4276243941
Short name T757
Test name
Test status
Simulation time 18569768621 ps
CPU time 32 seconds
Started Jun 05 04:18:11 PM PDT 24
Finished Jun 05 04:18:44 PM PDT 24
Peak memory 200316 kb
Host smart-1c1b2252-d043-4b25-a227-c76380627865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276243941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.4276243941
Directory /workspace/131.uart_fifo_reset/latest

Test location /workspace/coverage/default/134.uart_fifo_reset.1839680198
Short name T601
Test name
Test status
Simulation time 24601894240 ps
CPU time 37.29 seconds
Started Jun 05 04:18:14 PM PDT 24
Finished Jun 05 04:18:52 PM PDT 24
Peak memory 200468 kb
Host smart-c9550540-6962-4862-8e89-a3ce6031cf74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839680198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.1839680198
Directory /workspace/134.uart_fifo_reset/latest

Test location /workspace/coverage/default/135.uart_fifo_reset.1274594746
Short name T866
Test name
Test status
Simulation time 106478338858 ps
CPU time 141.21 seconds
Started Jun 05 04:18:09 PM PDT 24
Finished Jun 05 04:20:32 PM PDT 24
Peak memory 200380 kb
Host smart-ba4b12d7-1680-48c3-8cff-3c5e663524b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274594746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.1274594746
Directory /workspace/135.uart_fifo_reset/latest

Test location /workspace/coverage/default/136.uart_fifo_reset.4038958395
Short name T456
Test name
Test status
Simulation time 77339508979 ps
CPU time 130.35 seconds
Started Jun 05 04:18:14 PM PDT 24
Finished Jun 05 04:20:25 PM PDT 24
Peak memory 200408 kb
Host smart-aff58048-ca0a-4994-a5b1-7e0168aceedf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038958395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.4038958395
Directory /workspace/136.uart_fifo_reset/latest

Test location /workspace/coverage/default/137.uart_fifo_reset.2152043657
Short name T139
Test name
Test status
Simulation time 31350942540 ps
CPU time 16.3 seconds
Started Jun 05 04:18:12 PM PDT 24
Finished Jun 05 04:18:29 PM PDT 24
Peak memory 200520 kb
Host smart-d637fc83-217e-4ce4-afdb-b2d2b49790f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152043657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.2152043657
Directory /workspace/137.uart_fifo_reset/latest

Test location /workspace/coverage/default/138.uart_fifo_reset.2025250409
Short name T162
Test name
Test status
Simulation time 192025182501 ps
CPU time 133.48 seconds
Started Jun 05 04:18:14 PM PDT 24
Finished Jun 05 04:20:28 PM PDT 24
Peak memory 200432 kb
Host smart-6e472417-36ec-48c3-9028-895e566f1e69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025250409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.2025250409
Directory /workspace/138.uart_fifo_reset/latest

Test location /workspace/coverage/default/139.uart_fifo_reset.2390000921
Short name T1003
Test name
Test status
Simulation time 138424953132 ps
CPU time 210.69 seconds
Started Jun 05 04:18:10 PM PDT 24
Finished Jun 05 04:21:41 PM PDT 24
Peak memory 200444 kb
Host smart-c8379cdf-43e8-4d11-bba4-fa20431e3d6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390000921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.2390000921
Directory /workspace/139.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_alert_test.998496152
Short name T642
Test name
Test status
Simulation time 38676589 ps
CPU time 0.54 seconds
Started Jun 05 04:15:14 PM PDT 24
Finished Jun 05 04:15:15 PM PDT 24
Peak memory 195828 kb
Host smart-0eceb392-f150-4222-89e7-ff77ea799e85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998496152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.998496152
Directory /workspace/14.uart_alert_test/latest

Test location /workspace/coverage/default/14.uart_fifo_full.761838083
Short name T136
Test name
Test status
Simulation time 47827108733 ps
CPU time 38.87 seconds
Started Jun 05 04:15:09 PM PDT 24
Finished Jun 05 04:15:49 PM PDT 24
Peak memory 200472 kb
Host smart-08716c76-bc05-463d-afe3-c501c687eb14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761838083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.761838083
Directory /workspace/14.uart_fifo_full/latest

Test location /workspace/coverage/default/14.uart_fifo_overflow.4217046053
Short name T743
Test name
Test status
Simulation time 45280023385 ps
CPU time 81 seconds
Started Jun 05 04:15:23 PM PDT 24
Finished Jun 05 04:16:44 PM PDT 24
Peak memory 200332 kb
Host smart-9cdc550f-e047-4625-8c9a-49d9a1484c18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217046053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.4217046053
Directory /workspace/14.uart_fifo_overflow/latest

Test location /workspace/coverage/default/14.uart_fifo_reset.1409277069
Short name T220
Test name
Test status
Simulation time 112680453402 ps
CPU time 54.45 seconds
Started Jun 05 04:15:11 PM PDT 24
Finished Jun 05 04:16:07 PM PDT 24
Peak memory 200440 kb
Host smart-d85a3031-a8f0-469f-a462-ff047f144ec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409277069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.1409277069
Directory /workspace/14.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_intr.534855318
Short name T326
Test name
Test status
Simulation time 20834270958 ps
CPU time 21.08 seconds
Started Jun 05 04:15:10 PM PDT 24
Finished Jun 05 04:15:33 PM PDT 24
Peak memory 200384 kb
Host smart-dd3def67-86b2-4d75-890d-7b3c61c2e30e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534855318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.534855318
Directory /workspace/14.uart_intr/latest

Test location /workspace/coverage/default/14.uart_long_xfer_wo_dly.1847216636
Short name T503
Test name
Test status
Simulation time 211795312169 ps
CPU time 2041.04 seconds
Started Jun 05 04:15:09 PM PDT 24
Finished Jun 05 04:49:11 PM PDT 24
Peak memory 200492 kb
Host smart-20f09fce-dc68-4026-b126-a6e42a0bbb09
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1847216636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.1847216636
Directory /workspace/14.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/14.uart_loopback.3496749400
Short name T805
Test name
Test status
Simulation time 10248023759 ps
CPU time 13.05 seconds
Started Jun 05 04:15:07 PM PDT 24
Finished Jun 05 04:15:21 PM PDT 24
Peak memory 200072 kb
Host smart-0a62fa5e-4818-4de7-9f50-28b076c6c53c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496749400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_loopback.3496749400
Directory /workspace/14.uart_loopback/latest

Test location /workspace/coverage/default/14.uart_noise_filter.1073239398
Short name T444
Test name
Test status
Simulation time 27022190753 ps
CPU time 15.72 seconds
Started Jun 05 04:15:09 PM PDT 24
Finished Jun 05 04:15:26 PM PDT 24
Peak memory 208744 kb
Host smart-7540b235-3ce8-4042-ab2d-9ef036426d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073239398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_noise_filter.1073239398
Directory /workspace/14.uart_noise_filter/latest

Test location /workspace/coverage/default/14.uart_perf.3874146802
Short name T4
Test name
Test status
Simulation time 13251877799 ps
CPU time 103.34 seconds
Started Jun 05 04:15:15 PM PDT 24
Finished Jun 05 04:16:59 PM PDT 24
Peak memory 200432 kb
Host smart-1b95bf5a-073c-45a5-b3cc-3b428d3b4ea2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3874146802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.3874146802
Directory /workspace/14.uart_perf/latest

Test location /workspace/coverage/default/14.uart_rx_oversample.3413784340
Short name T767
Test name
Test status
Simulation time 5562863352 ps
CPU time 44.3 seconds
Started Jun 05 04:15:01 PM PDT 24
Finished Jun 05 04:15:46 PM PDT 24
Peak memory 199564 kb
Host smart-4902a754-fc72-4e37-a494-3e3a16964613
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3413784340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.3413784340
Directory /workspace/14.uart_rx_oversample/latest

Test location /workspace/coverage/default/14.uart_rx_parity_err.605191960
Short name T355
Test name
Test status
Simulation time 10705158881 ps
CPU time 20.04 seconds
Started Jun 05 04:15:06 PM PDT 24
Finished Jun 05 04:15:26 PM PDT 24
Peak memory 200360 kb
Host smart-e749cff6-39c8-45c7-b290-786dfa0aa547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605191960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.605191960
Directory /workspace/14.uart_rx_parity_err/latest

Test location /workspace/coverage/default/14.uart_rx_start_bit_filter.18063336
Short name T539
Test name
Test status
Simulation time 4206173557 ps
CPU time 3.31 seconds
Started Jun 05 04:15:10 PM PDT 24
Finished Jun 05 04:15:15 PM PDT 24
Peak memory 196712 kb
Host smart-8b1c8f3f-c28f-4306-ad31-2f0e5805efdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18063336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.18063336
Directory /workspace/14.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/14.uart_smoke.955685745
Short name T286
Test name
Test status
Simulation time 697750295 ps
CPU time 1.83 seconds
Started Jun 05 04:15:07 PM PDT 24
Finished Jun 05 04:15:09 PM PDT 24
Peak memory 199288 kb
Host smart-b04a011e-1260-4777-94f4-48ffe551a2d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955685745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_smoke.955685745
Directory /workspace/14.uart_smoke/latest

Test location /workspace/coverage/default/14.uart_stress_all.2386011207
Short name T1064
Test name
Test status
Simulation time 121669051912 ps
CPU time 678.78 seconds
Started Jun 05 04:15:46 PM PDT 24
Finished Jun 05 04:27:06 PM PDT 24
Peak memory 200436 kb
Host smart-5a600481-4207-4898-9fb2-28e5a848c10f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386011207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.2386011207
Directory /workspace/14.uart_stress_all/latest

Test location /workspace/coverage/default/14.uart_stress_all_with_rand_reset.3577590845
Short name T613
Test name
Test status
Simulation time 139122301114 ps
CPU time 446.79 seconds
Started Jun 05 04:15:10 PM PDT 24
Finished Jun 05 04:22:39 PM PDT 24
Peak memory 225268 kb
Host smart-a723b79c-2f82-4571-b3a0-ea014366dc32
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577590845 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 14.uart_stress_all_with_rand_reset.3577590845
Directory /workspace/14.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.uart_tx_ovrd.3521095787
Short name T1066
Test name
Test status
Simulation time 1156052200 ps
CPU time 4.49 seconds
Started Jun 05 04:15:11 PM PDT 24
Finished Jun 05 04:15:17 PM PDT 24
Peak memory 200124 kb
Host smart-24bed454-70e3-4d4a-9722-47acd15131a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521095787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.3521095787
Directory /workspace/14.uart_tx_ovrd/latest

Test location /workspace/coverage/default/14.uart_tx_rx.2669328894
Short name T695
Test name
Test status
Simulation time 154427454051 ps
CPU time 99.56 seconds
Started Jun 05 04:15:05 PM PDT 24
Finished Jun 05 04:16:45 PM PDT 24
Peak memory 200388 kb
Host smart-d55ca859-2dc3-43fc-b517-194516565409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669328894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.2669328894
Directory /workspace/14.uart_tx_rx/latest

Test location /workspace/coverage/default/141.uart_fifo_reset.1374387377
Short name T134
Test name
Test status
Simulation time 110799744297 ps
CPU time 46.23 seconds
Started Jun 05 04:18:10 PM PDT 24
Finished Jun 05 04:18:57 PM PDT 24
Peak memory 200416 kb
Host smart-9bf6c648-4c39-4e8e-8c67-6974e668e5d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374387377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.1374387377
Directory /workspace/141.uart_fifo_reset/latest

Test location /workspace/coverage/default/142.uart_fifo_reset.2545237559
Short name T204
Test name
Test status
Simulation time 63988831938 ps
CPU time 99.6 seconds
Started Jun 05 04:18:12 PM PDT 24
Finished Jun 05 04:19:52 PM PDT 24
Peak memory 200516 kb
Host smart-a03ae437-1f45-4af6-8d5f-8a178882ccd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545237559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.2545237559
Directory /workspace/142.uart_fifo_reset/latest

Test location /workspace/coverage/default/144.uart_fifo_reset.320002498
Short name T188
Test name
Test status
Simulation time 141975938806 ps
CPU time 57.72 seconds
Started Jun 05 04:18:10 PM PDT 24
Finished Jun 05 04:19:08 PM PDT 24
Peak memory 200376 kb
Host smart-b9b22541-8c2b-47f4-81e9-c5bd7e02556f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320002498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.320002498
Directory /workspace/144.uart_fifo_reset/latest

Test location /workspace/coverage/default/145.uart_fifo_reset.3654628516
Short name T179
Test name
Test status
Simulation time 201303374640 ps
CPU time 395.19 seconds
Started Jun 05 04:18:12 PM PDT 24
Finished Jun 05 04:24:48 PM PDT 24
Peak memory 200336 kb
Host smart-db58d388-11de-4094-9626-434dacbf5863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654628516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.3654628516
Directory /workspace/145.uart_fifo_reset/latest

Test location /workspace/coverage/default/146.uart_fifo_reset.1768092234
Short name T558
Test name
Test status
Simulation time 29687029242 ps
CPU time 44.78 seconds
Started Jun 05 04:18:10 PM PDT 24
Finished Jun 05 04:18:56 PM PDT 24
Peak memory 200368 kb
Host smart-5ec7d08c-68db-4923-8f22-33b5a6a2ce06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768092234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.1768092234
Directory /workspace/146.uart_fifo_reset/latest

Test location /workspace/coverage/default/147.uart_fifo_reset.3600789599
Short name T240
Test name
Test status
Simulation time 116947086135 ps
CPU time 167.21 seconds
Started Jun 05 04:18:13 PM PDT 24
Finished Jun 05 04:21:01 PM PDT 24
Peak memory 200404 kb
Host smart-86d0c20c-da9e-4152-85b5-84d39c77e57c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600789599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.3600789599
Directory /workspace/147.uart_fifo_reset/latest

Test location /workspace/coverage/default/149.uart_fifo_reset.4067300709
Short name T497
Test name
Test status
Simulation time 70741844644 ps
CPU time 34.02 seconds
Started Jun 05 04:18:18 PM PDT 24
Finished Jun 05 04:18:52 PM PDT 24
Peak memory 200372 kb
Host smart-b2b352a5-87c4-4a23-9ff0-b092dd117e88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067300709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.4067300709
Directory /workspace/149.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_alert_test.3364485053
Short name T873
Test name
Test status
Simulation time 44584041 ps
CPU time 0.55 seconds
Started Jun 05 04:15:16 PM PDT 24
Finished Jun 05 04:15:17 PM PDT 24
Peak memory 195816 kb
Host smart-8b5dfb0a-accd-463a-b645-e2f89afb9be4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364485053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.3364485053
Directory /workspace/15.uart_alert_test/latest

Test location /workspace/coverage/default/15.uart_fifo_full.3194074908
Short name T1016
Test name
Test status
Simulation time 66335371647 ps
CPU time 26.64 seconds
Started Jun 05 04:15:19 PM PDT 24
Finished Jun 05 04:15:47 PM PDT 24
Peak memory 200408 kb
Host smart-2b5cecc5-ac17-4ab4-be7c-df3e80158421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194074908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.3194074908
Directory /workspace/15.uart_fifo_full/latest

Test location /workspace/coverage/default/15.uart_fifo_overflow.1954259692
Short name T1068
Test name
Test status
Simulation time 99342774938 ps
CPU time 175.04 seconds
Started Jun 05 04:15:08 PM PDT 24
Finished Jun 05 04:18:04 PM PDT 24
Peak memory 200464 kb
Host smart-8f969502-2bc7-475d-9efe-ff6d2c185cfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954259692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.1954259692
Directory /workspace/15.uart_fifo_overflow/latest

Test location /workspace/coverage/default/15.uart_fifo_reset.280264999
Short name T1110
Test name
Test status
Simulation time 185520264979 ps
CPU time 260.05 seconds
Started Jun 05 04:15:13 PM PDT 24
Finished Jun 05 04:19:34 PM PDT 24
Peak memory 200364 kb
Host smart-fb5ee61d-96ee-4ddd-a3be-124f1893b34e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280264999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.280264999
Directory /workspace/15.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_intr.3817906679
Short name T14
Test name
Test status
Simulation time 23294827429 ps
CPU time 13.04 seconds
Started Jun 05 04:15:09 PM PDT 24
Finished Jun 05 04:15:24 PM PDT 24
Peak memory 200168 kb
Host smart-b102c0fc-1a4a-437b-9770-e332d3af18f4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817906679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.3817906679
Directory /workspace/15.uart_intr/latest

Test location /workspace/coverage/default/15.uart_long_xfer_wo_dly.3249865373
Short name T571
Test name
Test status
Simulation time 255066875995 ps
CPU time 517.48 seconds
Started Jun 05 04:15:12 PM PDT 24
Finished Jun 05 04:23:50 PM PDT 24
Peak memory 200444 kb
Host smart-7735eaae-43e1-4a9d-b6d3-c110b65c9f70
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3249865373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.3249865373
Directory /workspace/15.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/15.uart_loopback.753516393
Short name T596
Test name
Test status
Simulation time 4093133960 ps
CPU time 3.76 seconds
Started Jun 05 04:15:09 PM PDT 24
Finished Jun 05 04:15:15 PM PDT 24
Peak memory 200332 kb
Host smart-202b6a80-e482-468d-8585-4816a6ac9df9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753516393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_loopback.753516393
Directory /workspace/15.uart_loopback/latest

Test location /workspace/coverage/default/15.uart_noise_filter.2107021026
Short name T699
Test name
Test status
Simulation time 146384078302 ps
CPU time 107.11 seconds
Started Jun 05 04:15:14 PM PDT 24
Finished Jun 05 04:17:06 PM PDT 24
Peak memory 200648 kb
Host smart-3f9693d3-9574-46a1-95b5-b1c56d79e1f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107021026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_noise_filter.2107021026
Directory /workspace/15.uart_noise_filter/latest

Test location /workspace/coverage/default/15.uart_perf.1020743071
Short name T35
Test name
Test status
Simulation time 17246717974 ps
CPU time 241.59 seconds
Started Jun 05 04:15:09 PM PDT 24
Finished Jun 05 04:19:13 PM PDT 24
Peak memory 200336 kb
Host smart-59645259-00bb-468b-bea5-a0984d0a0d7b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1020743071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.1020743071
Directory /workspace/15.uart_perf/latest

Test location /workspace/coverage/default/15.uart_rx_oversample.3094826158
Short name T1098
Test name
Test status
Simulation time 6279611179 ps
CPU time 63.88 seconds
Started Jun 05 04:15:30 PM PDT 24
Finished Jun 05 04:16:34 PM PDT 24
Peak memory 199748 kb
Host smart-be37ba98-3312-446d-8d62-93d0eb1761b7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3094826158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.3094826158
Directory /workspace/15.uart_rx_oversample/latest

Test location /workspace/coverage/default/15.uart_rx_parity_err.427781773
Short name T1102
Test name
Test status
Simulation time 36845007126 ps
CPU time 58.79 seconds
Started Jun 05 04:15:09 PM PDT 24
Finished Jun 05 04:16:09 PM PDT 24
Peak memory 200440 kb
Host smart-b54f2533-0c18-4fe5-8fe4-8e0cfa07e1ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427781773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.427781773
Directory /workspace/15.uart_rx_parity_err/latest

Test location /workspace/coverage/default/15.uart_rx_start_bit_filter.192865623
Short name T500
Test name
Test status
Simulation time 4110360395 ps
CPU time 4.03 seconds
Started Jun 05 04:15:08 PM PDT 24
Finished Jun 05 04:15:13 PM PDT 24
Peak memory 196432 kb
Host smart-23e429f5-ecc3-4be1-a105-7ece0b2ed2bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192865623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.192865623
Directory /workspace/15.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/15.uart_smoke.1601921199
Short name T933
Test name
Test status
Simulation time 485479349 ps
CPU time 1.17 seconds
Started Jun 05 04:15:10 PM PDT 24
Finished Jun 05 04:15:17 PM PDT 24
Peak memory 199228 kb
Host smart-61b68f8f-1178-4a73-ba89-b9ddddf91446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601921199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_smoke.1601921199
Directory /workspace/15.uart_smoke/latest

Test location /workspace/coverage/default/15.uart_tx_ovrd.666810304
Short name T843
Test name
Test status
Simulation time 676916526 ps
CPU time 2.03 seconds
Started Jun 05 04:15:25 PM PDT 24
Finished Jun 05 04:15:28 PM PDT 24
Peak memory 199000 kb
Host smart-06cb6de4-9fac-4aa7-acf8-7d419a4946d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666810304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.666810304
Directory /workspace/15.uart_tx_ovrd/latest

Test location /workspace/coverage/default/15.uart_tx_rx.2365024666
Short name T289
Test name
Test status
Simulation time 14646770614 ps
CPU time 24.27 seconds
Started Jun 05 04:15:07 PM PDT 24
Finished Jun 05 04:15:32 PM PDT 24
Peak memory 200416 kb
Host smart-28cda124-d177-462d-9d01-672e87509021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365024666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.2365024666
Directory /workspace/15.uart_tx_rx/latest

Test location /workspace/coverage/default/150.uart_fifo_reset.1050640012
Short name T214
Test name
Test status
Simulation time 73203275480 ps
CPU time 32.02 seconds
Started Jun 05 04:18:17 PM PDT 24
Finished Jun 05 04:18:50 PM PDT 24
Peak memory 200392 kb
Host smart-6a411566-bbc4-4a13-997a-8489bf0b9ded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050640012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.1050640012
Directory /workspace/150.uart_fifo_reset/latest

Test location /workspace/coverage/default/151.uart_fifo_reset.3060468672
Short name T636
Test name
Test status
Simulation time 155127575600 ps
CPU time 83.77 seconds
Started Jun 05 04:18:17 PM PDT 24
Finished Jun 05 04:19:41 PM PDT 24
Peak memory 200324 kb
Host smart-7c433457-8ace-438d-b25c-ecebc47c6caa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060468672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.3060468672
Directory /workspace/151.uart_fifo_reset/latest

Test location /workspace/coverage/default/152.uart_fifo_reset.2143616262
Short name T219
Test name
Test status
Simulation time 73844646043 ps
CPU time 30.26 seconds
Started Jun 05 04:18:18 PM PDT 24
Finished Jun 05 04:18:49 PM PDT 24
Peak memory 200340 kb
Host smart-b5a4741f-773e-4494-a2c1-dba09befa41a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143616262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.2143616262
Directory /workspace/152.uart_fifo_reset/latest

Test location /workspace/coverage/default/153.uart_fifo_reset.1709563579
Short name T476
Test name
Test status
Simulation time 169420732749 ps
CPU time 44.18 seconds
Started Jun 05 04:18:18 PM PDT 24
Finished Jun 05 04:19:04 PM PDT 24
Peak memory 200412 kb
Host smart-b78ddd1a-daf3-4f51-88be-daeeebb91dc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709563579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.1709563579
Directory /workspace/153.uart_fifo_reset/latest

Test location /workspace/coverage/default/154.uart_fifo_reset.2514923905
Short name T1022
Test name
Test status
Simulation time 27306521340 ps
CPU time 41.13 seconds
Started Jun 05 04:18:18 PM PDT 24
Finished Jun 05 04:19:00 PM PDT 24
Peak memory 200208 kb
Host smart-ca5a4684-9226-4b2e-ae23-0bb8c6d2a1d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514923905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.2514923905
Directory /workspace/154.uart_fifo_reset/latest

Test location /workspace/coverage/default/155.uart_fifo_reset.3669847475
Short name T185
Test name
Test status
Simulation time 20960508038 ps
CPU time 34.61 seconds
Started Jun 05 04:18:18 PM PDT 24
Finished Jun 05 04:18:54 PM PDT 24
Peak memory 200432 kb
Host smart-f73f0b64-5194-4987-af0a-f2ddf7c23d7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669847475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.3669847475
Directory /workspace/155.uart_fifo_reset/latest

Test location /workspace/coverage/default/156.uart_fifo_reset.1352412458
Short name T49
Test name
Test status
Simulation time 6191783519 ps
CPU time 10.31 seconds
Started Jun 05 04:18:23 PM PDT 24
Finished Jun 05 04:18:34 PM PDT 24
Peak memory 200200 kb
Host smart-a22c5d7d-3828-4638-9fb3-0847acadc574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352412458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.1352412458
Directory /workspace/156.uart_fifo_reset/latest

Test location /workspace/coverage/default/157.uart_fifo_reset.2396440539
Short name T1150
Test name
Test status
Simulation time 88997764038 ps
CPU time 37.04 seconds
Started Jun 05 04:18:19 PM PDT 24
Finished Jun 05 04:18:57 PM PDT 24
Peak memory 200448 kb
Host smart-2422a11f-f4f6-4393-9ace-0593e062b5ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396440539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.2396440539
Directory /workspace/157.uart_fifo_reset/latest

Test location /workspace/coverage/default/158.uart_fifo_reset.3511685001
Short name T192
Test name
Test status
Simulation time 28792602883 ps
CPU time 24.46 seconds
Started Jun 05 04:18:15 PM PDT 24
Finished Jun 05 04:18:40 PM PDT 24
Peak memory 200112 kb
Host smart-fc8c1c81-5637-4752-b264-50cf4feb5e80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511685001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.3511685001
Directory /workspace/158.uart_fifo_reset/latest

Test location /workspace/coverage/default/159.uart_fifo_reset.885583578
Short name T51
Test name
Test status
Simulation time 10727841648 ps
CPU time 17.09 seconds
Started Jun 05 04:18:23 PM PDT 24
Finished Jun 05 04:18:41 PM PDT 24
Peak memory 200080 kb
Host smart-dfce0bce-a3ec-4d5b-87a4-dbd100e2819d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885583578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.885583578
Directory /workspace/159.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_alert_test.1681413371
Short name T697
Test name
Test status
Simulation time 14599106 ps
CPU time 0.55 seconds
Started Jun 05 04:15:08 PM PDT 24
Finished Jun 05 04:15:09 PM PDT 24
Peak memory 195836 kb
Host smart-dda18915-c350-4fd4-b31a-87b5342331d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681413371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.1681413371
Directory /workspace/16.uart_alert_test/latest

Test location /workspace/coverage/default/16.uart_fifo_full.4132876294
Short name T876
Test name
Test status
Simulation time 255566031957 ps
CPU time 455.72 seconds
Started Jun 05 04:15:12 PM PDT 24
Finished Jun 05 04:22:49 PM PDT 24
Peak memory 200392 kb
Host smart-5248d700-8045-47cf-a74f-30e8e8603210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132876294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.4132876294
Directory /workspace/16.uart_fifo_full/latest

Test location /workspace/coverage/default/16.uart_fifo_overflow.3110205522
Short name T1149
Test name
Test status
Simulation time 25377506771 ps
CPU time 42.87 seconds
Started Jun 05 04:15:10 PM PDT 24
Finished Jun 05 04:15:55 PM PDT 24
Peak memory 200424 kb
Host smart-438ef15b-07d5-44e5-b00a-5a052292d29d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110205522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.3110205522
Directory /workspace/16.uart_fifo_overflow/latest

Test location /workspace/coverage/default/16.uart_fifo_reset.3492722436
Short name T462
Test name
Test status
Simulation time 142045986354 ps
CPU time 220.2 seconds
Started Jun 05 04:15:10 PM PDT 24
Finished Jun 05 04:18:52 PM PDT 24
Peak memory 200376 kb
Host smart-9cf08660-1d24-4d10-a2a1-ece67aa4f98a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492722436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.3492722436
Directory /workspace/16.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_intr.1549456961
Short name T902
Test name
Test status
Simulation time 29766897569 ps
CPU time 13.52 seconds
Started Jun 05 04:15:11 PM PDT 24
Finished Jun 05 04:15:26 PM PDT 24
Peak memory 200444 kb
Host smart-4caf2f94-34da-42d7-ba82-4be24e446cd6
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549456961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.1549456961
Directory /workspace/16.uart_intr/latest

Test location /workspace/coverage/default/16.uart_long_xfer_wo_dly.667618693
Short name T101
Test name
Test status
Simulation time 136020723989 ps
CPU time 913.8 seconds
Started Jun 05 04:15:12 PM PDT 24
Finished Jun 05 04:30:27 PM PDT 24
Peak memory 200420 kb
Host smart-d554595d-e231-450c-b86e-ab2f51e9337a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=667618693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.667618693
Directory /workspace/16.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/16.uart_loopback.1234150706
Short name T20
Test name
Test status
Simulation time 8758616351 ps
CPU time 4.44 seconds
Started Jun 05 04:15:11 PM PDT 24
Finished Jun 05 04:15:17 PM PDT 24
Peak memory 200100 kb
Host smart-568527a9-2ca6-46a7-9931-71c040b4a01d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234150706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_loopback.1234150706
Directory /workspace/16.uart_loopback/latest

Test location /workspace/coverage/default/16.uart_noise_filter.2025552288
Short name T775
Test name
Test status
Simulation time 121947498772 ps
CPU time 138.1 seconds
Started Jun 05 04:15:12 PM PDT 24
Finished Jun 05 04:17:31 PM PDT 24
Peak memory 200620 kb
Host smart-7ddfd5c0-314e-4255-b666-217a67cbce69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025552288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_noise_filter.2025552288
Directory /workspace/16.uart_noise_filter/latest

Test location /workspace/coverage/default/16.uart_perf.1655357853
Short name T385
Test name
Test status
Simulation time 12932816084 ps
CPU time 170.56 seconds
Started Jun 05 04:15:09 PM PDT 24
Finished Jun 05 04:18:01 PM PDT 24
Peak memory 200584 kb
Host smart-bd8f4b66-0fb4-4ae6-afad-e0c0f057ef09
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1655357853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.1655357853
Directory /workspace/16.uart_perf/latest

Test location /workspace/coverage/default/16.uart_rx_oversample.2706200382
Short name T357
Test name
Test status
Simulation time 2397440963 ps
CPU time 7.57 seconds
Started Jun 05 04:15:22 PM PDT 24
Finished Jun 05 04:15:30 PM PDT 24
Peak memory 198508 kb
Host smart-dfc0b053-493b-4ea6-aa5c-b9a074a3259b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2706200382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.2706200382
Directory /workspace/16.uart_rx_oversample/latest

Test location /workspace/coverage/default/16.uart_rx_parity_err.336443483
Short name T389
Test name
Test status
Simulation time 15302417752 ps
CPU time 20.73 seconds
Started Jun 05 04:15:12 PM PDT 24
Finished Jun 05 04:15:34 PM PDT 24
Peak memory 200428 kb
Host smart-8a452943-a4e9-411c-9389-43bc79b33af2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336443483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.336443483
Directory /workspace/16.uart_rx_parity_err/latest

Test location /workspace/coverage/default/16.uart_rx_start_bit_filter.3550963909
Short name T410
Test name
Test status
Simulation time 39929783921 ps
CPU time 23.24 seconds
Started Jun 05 04:15:13 PM PDT 24
Finished Jun 05 04:15:37 PM PDT 24
Peak memory 196148 kb
Host smart-c1f4fcc1-77c3-4d39-9e16-3c9062262998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550963909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.3550963909
Directory /workspace/16.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/16.uart_smoke.3007091866
Short name T468
Test name
Test status
Simulation time 444687077 ps
CPU time 1.92 seconds
Started Jun 05 04:15:42 PM PDT 24
Finished Jun 05 04:15:45 PM PDT 24
Peak memory 199968 kb
Host smart-55b72159-636f-4227-bb2e-1ad1a27aaf09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007091866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_smoke.3007091866
Directory /workspace/16.uart_smoke/latest

Test location /workspace/coverage/default/16.uart_stress_all_with_rand_reset.1800954251
Short name T810
Test name
Test status
Simulation time 64044531101 ps
CPU time 465.96 seconds
Started Jun 05 04:15:13 PM PDT 24
Finished Jun 05 04:23:00 PM PDT 24
Peak memory 217052 kb
Host smart-fc0b505b-9d72-4c20-b341-3d17da5d6ba4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800954251 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 16.uart_stress_all_with_rand_reset.1800954251
Directory /workspace/16.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.uart_tx_ovrd.2781562411
Short name T557
Test name
Test status
Simulation time 1305852273 ps
CPU time 1.77 seconds
Started Jun 05 04:15:13 PM PDT 24
Finished Jun 05 04:15:16 PM PDT 24
Peak memory 199444 kb
Host smart-89db2174-f91c-49af-aeba-f0fe4cb5af66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781562411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.2781562411
Directory /workspace/16.uart_tx_ovrd/latest

Test location /workspace/coverage/default/16.uart_tx_rx.2100579532
Short name T1038
Test name
Test status
Simulation time 7518025829 ps
CPU time 18.82 seconds
Started Jun 05 04:15:15 PM PDT 24
Finished Jun 05 04:15:35 PM PDT 24
Peak memory 200444 kb
Host smart-c9762b15-916a-4eb3-a635-451c43c7ea25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100579532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.2100579532
Directory /workspace/16.uart_tx_rx/latest

Test location /workspace/coverage/default/160.uart_fifo_reset.3521436488
Short name T39
Test name
Test status
Simulation time 135600236638 ps
CPU time 210.88 seconds
Started Jun 05 04:18:18 PM PDT 24
Finished Jun 05 04:21:50 PM PDT 24
Peak memory 200108 kb
Host smart-498271d6-eaa6-4960-956e-d9d43cc1f3ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521436488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.3521436488
Directory /workspace/160.uart_fifo_reset/latest

Test location /workspace/coverage/default/161.uart_fifo_reset.3986569927
Short name T253
Test name
Test status
Simulation time 16397910307 ps
CPU time 41.32 seconds
Started Jun 05 04:18:19 PM PDT 24
Finished Jun 05 04:19:01 PM PDT 24
Peak memory 200420 kb
Host smart-2edaf6d2-1bcd-4d85-8dfb-c024ae9b974a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986569927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.3986569927
Directory /workspace/161.uart_fifo_reset/latest

Test location /workspace/coverage/default/162.uart_fifo_reset.1631093447
Short name T700
Test name
Test status
Simulation time 163338209070 ps
CPU time 72.05 seconds
Started Jun 05 04:18:18 PM PDT 24
Finished Jun 05 04:19:32 PM PDT 24
Peak memory 200124 kb
Host smart-851411b6-c29b-4e0a-91ab-f99009e62495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631093447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.1631093447
Directory /workspace/162.uart_fifo_reset/latest

Test location /workspace/coverage/default/164.uart_fifo_reset.1495776013
Short name T894
Test name
Test status
Simulation time 38828996786 ps
CPU time 68.62 seconds
Started Jun 05 04:18:18 PM PDT 24
Finished Jun 05 04:19:28 PM PDT 24
Peak memory 200376 kb
Host smart-054858d1-f532-4f80-922c-4fdac84a79a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495776013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.1495776013
Directory /workspace/164.uart_fifo_reset/latest

Test location /workspace/coverage/default/165.uart_fifo_reset.2661880230
Short name T667
Test name
Test status
Simulation time 19518832482 ps
CPU time 11.98 seconds
Started Jun 05 04:18:23 PM PDT 24
Finished Jun 05 04:18:36 PM PDT 24
Peak memory 200360 kb
Host smart-32720890-13b1-426f-8ada-7c98d4ee1380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661880230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.2661880230
Directory /workspace/165.uart_fifo_reset/latest

Test location /workspace/coverage/default/166.uart_fifo_reset.3360786405
Short name T452
Test name
Test status
Simulation time 74422552646 ps
CPU time 36.32 seconds
Started Jun 05 04:18:19 PM PDT 24
Finished Jun 05 04:18:56 PM PDT 24
Peak memory 200444 kb
Host smart-85646343-462d-47a1-a9f9-30979aaecf76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360786405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.3360786405
Directory /workspace/166.uart_fifo_reset/latest

Test location /workspace/coverage/default/167.uart_fifo_reset.4218274185
Short name T149
Test name
Test status
Simulation time 51849037597 ps
CPU time 23.88 seconds
Started Jun 05 04:18:18 PM PDT 24
Finished Jun 05 04:18:43 PM PDT 24
Peak memory 200464 kb
Host smart-549898cf-554e-4fda-b109-ed8af2e13606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218274185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.4218274185
Directory /workspace/167.uart_fifo_reset/latest

Test location /workspace/coverage/default/168.uart_fifo_reset.1677416065
Short name T133
Test name
Test status
Simulation time 32707780943 ps
CPU time 25.63 seconds
Started Jun 05 04:18:19 PM PDT 24
Finished Jun 05 04:18:45 PM PDT 24
Peak memory 200436 kb
Host smart-eced5444-3249-45fd-b3bc-099fbb0a383f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677416065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.1677416065
Directory /workspace/168.uart_fifo_reset/latest

Test location /workspace/coverage/default/169.uart_fifo_reset.280321829
Short name T632
Test name
Test status
Simulation time 79785114312 ps
CPU time 129.37 seconds
Started Jun 05 04:18:26 PM PDT 24
Finished Jun 05 04:20:37 PM PDT 24
Peak memory 200464 kb
Host smart-ae6f8a26-1d50-4d1f-81eb-fa71d9ec3514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280321829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.280321829
Directory /workspace/169.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_alert_test.1081955183
Short name T648
Test name
Test status
Simulation time 13066416 ps
CPU time 0.54 seconds
Started Jun 05 04:15:12 PM PDT 24
Finished Jun 05 04:15:13 PM PDT 24
Peak memory 195808 kb
Host smart-6772a50c-20ef-4de5-ac98-5063a51ff8a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081955183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.1081955183
Directory /workspace/17.uart_alert_test/latest

Test location /workspace/coverage/default/17.uart_fifo_full.2171627049
Short name T435
Test name
Test status
Simulation time 19606744744 ps
CPU time 28.58 seconds
Started Jun 05 04:15:34 PM PDT 24
Finished Jun 05 04:16:03 PM PDT 24
Peak memory 200460 kb
Host smart-c3626530-043d-4fc6-8ef0-ff9fd5209c94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171627049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.2171627049
Directory /workspace/17.uart_fifo_full/latest

Test location /workspace/coverage/default/17.uart_fifo_overflow.4126072986
Short name T618
Test name
Test status
Simulation time 127703877963 ps
CPU time 55.87 seconds
Started Jun 05 04:15:14 PM PDT 24
Finished Jun 05 04:16:11 PM PDT 24
Peak memory 200424 kb
Host smart-c4889e58-6728-4c21-b8f6-8d88d04716ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126072986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.4126072986
Directory /workspace/17.uart_fifo_overflow/latest

Test location /workspace/coverage/default/17.uart_fifo_reset.1188263995
Short name T395
Test name
Test status
Simulation time 18161994910 ps
CPU time 51.49 seconds
Started Jun 05 04:15:15 PM PDT 24
Finished Jun 05 04:16:08 PM PDT 24
Peak memory 200476 kb
Host smart-572a99f2-d149-401c-9114-d29add26f755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188263995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.1188263995
Directory /workspace/17.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_intr.1998099275
Short name T1082
Test name
Test status
Simulation time 47360152439 ps
CPU time 84.24 seconds
Started Jun 05 04:15:08 PM PDT 24
Finished Jun 05 04:16:33 PM PDT 24
Peak memory 200400 kb
Host smart-2b196244-103e-4759-88d3-0b31e89e6d99
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998099275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.1998099275
Directory /workspace/17.uart_intr/latest

Test location /workspace/coverage/default/17.uart_long_xfer_wo_dly.1376885454
Short name T1109
Test name
Test status
Simulation time 256722913323 ps
CPU time 219.25 seconds
Started Jun 05 04:15:16 PM PDT 24
Finished Jun 05 04:18:56 PM PDT 24
Peak memory 200444 kb
Host smart-82c05267-d669-484d-9851-a7857fa07a4e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1376885454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.1376885454
Directory /workspace/17.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/17.uart_loopback.2537187487
Short name T396
Test name
Test status
Simulation time 7655773142 ps
CPU time 5.28 seconds
Started Jun 05 04:15:12 PM PDT 24
Finished Jun 05 04:15:19 PM PDT 24
Peak memory 200004 kb
Host smart-c9befbc9-8732-4064-864b-534b32026e43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537187487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_loopback.2537187487
Directory /workspace/17.uart_loopback/latest

Test location /workspace/coverage/default/17.uart_noise_filter.2673864975
Short name T676
Test name
Test status
Simulation time 90164045680 ps
CPU time 194.41 seconds
Started Jun 05 04:15:12 PM PDT 24
Finished Jun 05 04:18:28 PM PDT 24
Peak memory 208748 kb
Host smart-c12f5832-fec2-4bac-905e-aa2bf6e4c48c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673864975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_noise_filter.2673864975
Directory /workspace/17.uart_noise_filter/latest

Test location /workspace/coverage/default/17.uart_perf.711728330
Short name T263
Test name
Test status
Simulation time 16948809617 ps
CPU time 241.22 seconds
Started Jun 05 04:15:16 PM PDT 24
Finished Jun 05 04:19:18 PM PDT 24
Peak memory 200372 kb
Host smart-84a8712a-e139-41b6-82d9-0a618fd06d96
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=711728330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.711728330
Directory /workspace/17.uart_perf/latest

Test location /workspace/coverage/default/17.uart_rx_oversample.2019689341
Short name T971
Test name
Test status
Simulation time 4962150955 ps
CPU time 48.33 seconds
Started Jun 05 04:15:19 PM PDT 24
Finished Jun 05 04:16:07 PM PDT 24
Peak memory 198716 kb
Host smart-def18ea7-d527-49d5-bcb7-06368a4b9ee1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2019689341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.2019689341
Directory /workspace/17.uart_rx_oversample/latest

Test location /workspace/coverage/default/17.uart_rx_parity_err.963875974
Short name T978
Test name
Test status
Simulation time 50380920524 ps
CPU time 77.38 seconds
Started Jun 05 04:15:12 PM PDT 24
Finished Jun 05 04:16:30 PM PDT 24
Peak memory 200360 kb
Host smart-b62eedd3-b740-4a1e-8368-59c850c39716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963875974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.963875974
Directory /workspace/17.uart_rx_parity_err/latest

Test location /workspace/coverage/default/17.uart_rx_start_bit_filter.1767718240
Short name T1063
Test name
Test status
Simulation time 2585930049 ps
CPU time 3.38 seconds
Started Jun 05 04:15:13 PM PDT 24
Finished Jun 05 04:15:17 PM PDT 24
Peak memory 196396 kb
Host smart-1646be31-a611-4b86-a530-23fd5591bcb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767718240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.1767718240
Directory /workspace/17.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/17.uart_smoke.3971618605
Short name T477
Test name
Test status
Simulation time 5910817688 ps
CPU time 17.91 seconds
Started Jun 05 04:15:06 PM PDT 24
Finished Jun 05 04:15:25 PM PDT 24
Peak memory 200312 kb
Host smart-0fdb92b1-7a91-452d-9b5a-7172c717e23c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971618605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_smoke.3971618605
Directory /workspace/17.uart_smoke/latest

Test location /workspace/coverage/default/17.uart_stress_all.116638054
Short name T399
Test name
Test status
Simulation time 93775144347 ps
CPU time 547.33 seconds
Started Jun 05 04:15:11 PM PDT 24
Finished Jun 05 04:24:20 PM PDT 24
Peak memory 200396 kb
Host smart-bbe5c1a8-dae8-43bc-b803-1bd7ff7f4d8d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116638054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.116638054
Directory /workspace/17.uart_stress_all/latest

Test location /workspace/coverage/default/17.uart_tx_ovrd.2506899327
Short name T948
Test name
Test status
Simulation time 1070900709 ps
CPU time 3.86 seconds
Started Jun 05 04:15:13 PM PDT 24
Finished Jun 05 04:15:18 PM PDT 24
Peak memory 199444 kb
Host smart-7f2b803c-1244-4d06-bb06-f07768812873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506899327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.2506899327
Directory /workspace/17.uart_tx_ovrd/latest

Test location /workspace/coverage/default/17.uart_tx_rx.2626955954
Short name T556
Test name
Test status
Simulation time 85080695820 ps
CPU time 197.48 seconds
Started Jun 05 04:15:10 PM PDT 24
Finished Jun 05 04:18:30 PM PDT 24
Peak memory 200440 kb
Host smart-dbee1b33-493c-4b5a-bd28-1c2f2fa37f30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626955954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.2626955954
Directory /workspace/17.uart_tx_rx/latest

Test location /workspace/coverage/default/171.uart_fifo_reset.3185960280
Short name T418
Test name
Test status
Simulation time 64988800576 ps
CPU time 106.54 seconds
Started Jun 05 04:18:27 PM PDT 24
Finished Jun 05 04:20:14 PM PDT 24
Peak memory 200384 kb
Host smart-83c6bd12-8a1d-4385-842d-8468f6080fc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185960280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.3185960280
Directory /workspace/171.uart_fifo_reset/latest

Test location /workspace/coverage/default/173.uart_fifo_reset.4229517169
Short name T448
Test name
Test status
Simulation time 30644286397 ps
CPU time 17.44 seconds
Started Jun 05 04:18:26 PM PDT 24
Finished Jun 05 04:18:44 PM PDT 24
Peak memory 200444 kb
Host smart-8416f069-4ea5-4594-8bf5-5b303fc70dd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229517169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.4229517169
Directory /workspace/173.uart_fifo_reset/latest

Test location /workspace/coverage/default/175.uart_fifo_reset.2112753162
Short name T1106
Test name
Test status
Simulation time 14505744963 ps
CPU time 19.45 seconds
Started Jun 05 04:18:26 PM PDT 24
Finished Jun 05 04:18:45 PM PDT 24
Peak memory 200436 kb
Host smart-d59b9a03-e459-4756-911f-f13a04d40470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112753162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.2112753162
Directory /workspace/175.uart_fifo_reset/latest

Test location /workspace/coverage/default/176.uart_fifo_reset.3796097856
Short name T953
Test name
Test status
Simulation time 93914818156 ps
CPU time 188.63 seconds
Started Jun 05 04:18:25 PM PDT 24
Finished Jun 05 04:21:34 PM PDT 24
Peak memory 200380 kb
Host smart-cb6b9389-6ab0-4ff5-8caa-7a0bad0ae987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796097856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.3796097856
Directory /workspace/176.uart_fifo_reset/latest

Test location /workspace/coverage/default/177.uart_fifo_reset.2490993778
Short name T178
Test name
Test status
Simulation time 56161604863 ps
CPU time 17.54 seconds
Started Jun 05 04:18:24 PM PDT 24
Finished Jun 05 04:18:42 PM PDT 24
Peak memory 200424 kb
Host smart-282256ad-f895-452d-b498-4231587508e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490993778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.2490993778
Directory /workspace/177.uart_fifo_reset/latest

Test location /workspace/coverage/default/178.uart_fifo_reset.1005667015
Short name T338
Test name
Test status
Simulation time 69516184120 ps
CPU time 39.25 seconds
Started Jun 05 04:18:26 PM PDT 24
Finished Jun 05 04:19:06 PM PDT 24
Peak memory 200376 kb
Host smart-01f91c60-a6cb-40c6-8b3e-6cc875d0edd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005667015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.1005667015
Directory /workspace/178.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_alert_test.4262336521
Short name T1161
Test name
Test status
Simulation time 15306934 ps
CPU time 0.56 seconds
Started Jun 05 04:15:25 PM PDT 24
Finished Jun 05 04:15:26 PM PDT 24
Peak memory 195812 kb
Host smart-090a692f-f76a-4bf0-8ade-c7dfa3e4cd81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262336521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.4262336521
Directory /workspace/18.uart_alert_test/latest

Test location /workspace/coverage/default/18.uart_fifo_full.3520793099
Short name T981
Test name
Test status
Simulation time 136816978608 ps
CPU time 57.13 seconds
Started Jun 05 04:15:16 PM PDT 24
Finished Jun 05 04:16:14 PM PDT 24
Peak memory 200456 kb
Host smart-e85c08bb-3ff1-4c0a-a29d-1887c92035d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520793099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.3520793099
Directory /workspace/18.uart_fifo_full/latest

Test location /workspace/coverage/default/18.uart_fifo_overflow.2800851824
Short name T780
Test name
Test status
Simulation time 117340535660 ps
CPU time 54.76 seconds
Started Jun 05 04:15:17 PM PDT 24
Finished Jun 05 04:16:13 PM PDT 24
Peak memory 200404 kb
Host smart-f12d5d2a-e09d-4521-bdf5-306e515336bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800851824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.2800851824
Directory /workspace/18.uart_fifo_overflow/latest

Test location /workspace/coverage/default/18.uart_fifo_reset.2728897065
Short name T1152
Test name
Test status
Simulation time 37496262459 ps
CPU time 25.53 seconds
Started Jun 05 04:15:16 PM PDT 24
Finished Jun 05 04:15:42 PM PDT 24
Peak memory 200332 kb
Host smart-39e60a73-93c3-4a6b-9416-2ff181a23da5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728897065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.2728897065
Directory /workspace/18.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_intr.921582909
Short name T1124
Test name
Test status
Simulation time 41977599716 ps
CPU time 36.87 seconds
Started Jun 05 04:15:16 PM PDT 24
Finished Jun 05 04:15:54 PM PDT 24
Peak memory 200404 kb
Host smart-48b35d1c-d9f7-47df-8cf7-ccac92b5bc30
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921582909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.921582909
Directory /workspace/18.uart_intr/latest

Test location /workspace/coverage/default/18.uart_long_xfer_wo_dly.3734844589
Short name T377
Test name
Test status
Simulation time 243184130790 ps
CPU time 376.01 seconds
Started Jun 05 04:15:28 PM PDT 24
Finished Jun 05 04:21:45 PM PDT 24
Peak memory 200448 kb
Host smart-1533ddbe-0fb6-4fdd-baab-44fdf979e3b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3734844589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.3734844589
Directory /workspace/18.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/18.uart_loopback.2152438093
Short name T940
Test name
Test status
Simulation time 14038814010 ps
CPU time 4.19 seconds
Started Jun 05 04:15:21 PM PDT 24
Finished Jun 05 04:15:26 PM PDT 24
Peak memory 200196 kb
Host smart-bf0d566c-c76e-4808-8b96-10e303f07ef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152438093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_loopback.2152438093
Directory /workspace/18.uart_loopback/latest

Test location /workspace/coverage/default/18.uart_noise_filter.2798157054
Short name T475
Test name
Test status
Simulation time 5335601516 ps
CPU time 9.64 seconds
Started Jun 05 04:15:27 PM PDT 24
Finished Jun 05 04:15:38 PM PDT 24
Peak memory 200372 kb
Host smart-11b53d99-a304-4dc4-aca3-428504bd8ca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798157054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_noise_filter.2798157054
Directory /workspace/18.uart_noise_filter/latest

Test location /workspace/coverage/default/18.uart_perf.947685693
Short name T797
Test name
Test status
Simulation time 6260841241 ps
CPU time 343.35 seconds
Started Jun 05 04:15:21 PM PDT 24
Finished Jun 05 04:21:05 PM PDT 24
Peak memory 200356 kb
Host smart-b12a81ca-013d-4789-aa95-7fa4a8398070
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=947685693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.947685693
Directory /workspace/18.uart_perf/latest

Test location /workspace/coverage/default/18.uart_rx_oversample.374381059
Short name T908
Test name
Test status
Simulation time 2547182477 ps
CPU time 4.64 seconds
Started Jun 05 04:15:13 PM PDT 24
Finished Jun 05 04:15:19 PM PDT 24
Peak memory 199768 kb
Host smart-33e0e816-732e-4d78-b593-70bbf5d93df4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=374381059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.374381059
Directory /workspace/18.uart_rx_oversample/latest

Test location /workspace/coverage/default/18.uart_rx_parity_err.928681587
Short name T160
Test name
Test status
Simulation time 155647853496 ps
CPU time 32.85 seconds
Started Jun 05 04:15:12 PM PDT 24
Finished Jun 05 04:15:46 PM PDT 24
Peak memory 200424 kb
Host smart-2a61697b-572c-4d06-95e7-fe10e08ee77d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928681587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.928681587
Directory /workspace/18.uart_rx_parity_err/latest

Test location /workspace/coverage/default/18.uart_rx_start_bit_filter.557898841
Short name T693
Test name
Test status
Simulation time 1792572296 ps
CPU time 3.78 seconds
Started Jun 05 04:15:12 PM PDT 24
Finished Jun 05 04:15:17 PM PDT 24
Peak memory 195792 kb
Host smart-76a96f20-d2b6-4af0-a370-ba794be6ab42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557898841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.557898841
Directory /workspace/18.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/18.uart_smoke.3832633255
Short name T374
Test name
Test status
Simulation time 733410581 ps
CPU time 2.77 seconds
Started Jun 05 04:15:13 PM PDT 24
Finished Jun 05 04:15:16 PM PDT 24
Peak memory 199664 kb
Host smart-87c2dd8e-09eb-43b1-be6b-d9178d87b74a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832633255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_smoke.3832633255
Directory /workspace/18.uart_smoke/latest

Test location /workspace/coverage/default/18.uart_stress_all.914927641
Short name T137
Test name
Test status
Simulation time 308361739307 ps
CPU time 278.9 seconds
Started Jun 05 04:15:24 PM PDT 24
Finished Jun 05 04:20:03 PM PDT 24
Peak memory 200360 kb
Host smart-ccc8fc12-e8ef-4b5d-8f9a-3db8f98daaa5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914927641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.914927641
Directory /workspace/18.uart_stress_all/latest

Test location /workspace/coverage/default/18.uart_stress_all_with_rand_reset.3487741638
Short name T991
Test name
Test status
Simulation time 29197098193 ps
CPU time 353.95 seconds
Started Jun 05 04:15:34 PM PDT 24
Finished Jun 05 04:21:29 PM PDT 24
Peak memory 216084 kb
Host smart-2ea406c0-5f5e-4b52-b4bb-7b44ea4421ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487741638 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 18.uart_stress_all_with_rand_reset.3487741638
Directory /workspace/18.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.uart_tx_ovrd.282884058
Short name T819
Test name
Test status
Simulation time 484052821 ps
CPU time 1.33 seconds
Started Jun 05 04:15:23 PM PDT 24
Finished Jun 05 04:15:25 PM PDT 24
Peak memory 198944 kb
Host smart-bf50d7b1-af80-42dc-b27a-9320c3a0081f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282884058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.282884058
Directory /workspace/18.uart_tx_ovrd/latest

Test location /workspace/coverage/default/18.uart_tx_rx.569843831
Short name T1107
Test name
Test status
Simulation time 302973531718 ps
CPU time 116.04 seconds
Started Jun 05 04:15:16 PM PDT 24
Finished Jun 05 04:17:13 PM PDT 24
Peak memory 200380 kb
Host smart-d3cf9174-fdaf-4d97-9c03-23760e0507a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569843831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.569843831
Directory /workspace/18.uart_tx_rx/latest

Test location /workspace/coverage/default/181.uart_fifo_reset.2201980326
Short name T261
Test name
Test status
Simulation time 65661944752 ps
CPU time 271.91 seconds
Started Jun 05 04:18:29 PM PDT 24
Finished Jun 05 04:23:01 PM PDT 24
Peak memory 200404 kb
Host smart-9a1d6357-a0a9-4022-9014-4abcf28a56cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201980326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.2201980326
Directory /workspace/181.uart_fifo_reset/latest

Test location /workspace/coverage/default/182.uart_fifo_reset.2599645003
Short name T441
Test name
Test status
Simulation time 137884642537 ps
CPU time 58.85 seconds
Started Jun 05 04:18:26 PM PDT 24
Finished Jun 05 04:19:25 PM PDT 24
Peak memory 200476 kb
Host smart-32c63077-d9e6-421d-9f9b-89b3a0a6d791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599645003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.2599645003
Directory /workspace/182.uart_fifo_reset/latest

Test location /workspace/coverage/default/183.uart_fifo_reset.2037753433
Short name T1142
Test name
Test status
Simulation time 46025860897 ps
CPU time 25.13 seconds
Started Jun 05 04:18:25 PM PDT 24
Finished Jun 05 04:18:51 PM PDT 24
Peak memory 200516 kb
Host smart-11ad0ba3-0c2c-43b1-ba58-ac5fbc512e46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037753433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.2037753433
Directory /workspace/183.uart_fifo_reset/latest

Test location /workspace/coverage/default/184.uart_fifo_reset.3778388847
Short name T226
Test name
Test status
Simulation time 238904305927 ps
CPU time 77.17 seconds
Started Jun 05 04:18:26 PM PDT 24
Finished Jun 05 04:19:44 PM PDT 24
Peak memory 200396 kb
Host smart-4d9fdcb6-8de9-4607-bc05-141059f5dc2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778388847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.3778388847
Directory /workspace/184.uart_fifo_reset/latest

Test location /workspace/coverage/default/185.uart_fifo_reset.3946380088
Short name T875
Test name
Test status
Simulation time 47556142136 ps
CPU time 37.6 seconds
Started Jun 05 04:18:28 PM PDT 24
Finished Jun 05 04:19:06 PM PDT 24
Peak memory 200440 kb
Host smart-7e079314-7a04-4d8f-b4fa-80efc56f247e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946380088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.3946380088
Directory /workspace/185.uart_fifo_reset/latest

Test location /workspace/coverage/default/186.uart_fifo_reset.1589245039
Short name T145
Test name
Test status
Simulation time 10139495232 ps
CPU time 17.14 seconds
Started Jun 05 04:18:26 PM PDT 24
Finished Jun 05 04:18:44 PM PDT 24
Peak memory 200180 kb
Host smart-c3b82ea4-51c2-4846-be56-38ab9e09b984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589245039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.1589245039
Directory /workspace/186.uart_fifo_reset/latest

Test location /workspace/coverage/default/187.uart_fifo_reset.2378074975
Short name T850
Test name
Test status
Simulation time 51121808377 ps
CPU time 47.89 seconds
Started Jun 05 04:18:28 PM PDT 24
Finished Jun 05 04:19:16 PM PDT 24
Peak memory 200472 kb
Host smart-72f65a11-1e40-4321-bd08-be15579a5d9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378074975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.2378074975
Directory /workspace/187.uart_fifo_reset/latest

Test location /workspace/coverage/default/188.uart_fifo_reset.3766875142
Short name T1013
Test name
Test status
Simulation time 91689131638 ps
CPU time 147.36 seconds
Started Jun 05 04:18:27 PM PDT 24
Finished Jun 05 04:20:55 PM PDT 24
Peak memory 200416 kb
Host smart-89241bb5-9972-4cc8-9d13-7d0d042bea51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766875142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.3766875142
Directory /workspace/188.uart_fifo_reset/latest

Test location /workspace/coverage/default/189.uart_fifo_reset.2139256196
Short name T770
Test name
Test status
Simulation time 24593647384 ps
CPU time 40.39 seconds
Started Jun 05 04:18:28 PM PDT 24
Finished Jun 05 04:19:09 PM PDT 24
Peak memory 200196 kb
Host smart-a6037504-4f05-4bab-939f-b91f308bc218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139256196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.2139256196
Directory /workspace/189.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_alert_test.1242112877
Short name T1029
Test name
Test status
Simulation time 11975750 ps
CPU time 0.56 seconds
Started Jun 05 04:15:23 PM PDT 24
Finished Jun 05 04:15:25 PM PDT 24
Peak memory 195756 kb
Host smart-aaadf64e-2dea-4953-b6b7-33fd00f1add7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242112877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.1242112877
Directory /workspace/19.uart_alert_test/latest

Test location /workspace/coverage/default/19.uart_fifo_full.2497038684
Short name T165
Test name
Test status
Simulation time 32623668789 ps
CPU time 10.24 seconds
Started Jun 05 04:15:13 PM PDT 24
Finished Jun 05 04:15:24 PM PDT 24
Peak memory 200360 kb
Host smart-d80eb5cb-0d85-41b4-a157-aa2248dee142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497038684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.2497038684
Directory /workspace/19.uart_fifo_full/latest

Test location /workspace/coverage/default/19.uart_fifo_overflow.3337854885
Short name T464
Test name
Test status
Simulation time 32529175570 ps
CPU time 60.69 seconds
Started Jun 05 04:15:16 PM PDT 24
Finished Jun 05 04:16:17 PM PDT 24
Peak memory 200364 kb
Host smart-f6dd7a96-379a-43c2-8c0f-26ce48b9c2ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337854885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.3337854885
Directory /workspace/19.uart_fifo_overflow/latest

Test location /workspace/coverage/default/19.uart_fifo_reset.1420971379
Short name T753
Test name
Test status
Simulation time 13566433859 ps
CPU time 23.42 seconds
Started Jun 05 04:15:14 PM PDT 24
Finished Jun 05 04:15:38 PM PDT 24
Peak memory 200448 kb
Host smart-99215d5a-f0d9-4e12-83a6-7efd36d6f102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420971379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.1420971379
Directory /workspace/19.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_intr.649723486
Short name T491
Test name
Test status
Simulation time 254794454647 ps
CPU time 105.03 seconds
Started Jun 05 04:15:24 PM PDT 24
Finished Jun 05 04:17:10 PM PDT 24
Peak memory 199860 kb
Host smart-0a08a755-2da4-41f6-a4da-23e44f18b791
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649723486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.649723486
Directory /workspace/19.uart_intr/latest

Test location /workspace/coverage/default/19.uart_long_xfer_wo_dly.2987264502
Short name T807
Test name
Test status
Simulation time 223879168844 ps
CPU time 340.94 seconds
Started Jun 05 04:15:24 PM PDT 24
Finished Jun 05 04:21:06 PM PDT 24
Peak memory 200388 kb
Host smart-7803dff6-91e8-4b88-bb28-bd5fbff33751
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2987264502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.2987264502
Directory /workspace/19.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/19.uart_loopback.4220364196
Short name T744
Test name
Test status
Simulation time 803611217 ps
CPU time 0.96 seconds
Started Jun 05 04:15:12 PM PDT 24
Finished Jun 05 04:15:14 PM PDT 24
Peak memory 196472 kb
Host smart-6d9823e4-baf7-4b9e-b218-8d3b05b61b0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220364196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_loopback.4220364196
Directory /workspace/19.uart_loopback/latest

Test location /workspace/coverage/default/19.uart_noise_filter.2991940833
Short name T622
Test name
Test status
Simulation time 215033061829 ps
CPU time 417.46 seconds
Started Jun 05 04:15:15 PM PDT 24
Finished Jun 05 04:22:13 PM PDT 24
Peak memory 200380 kb
Host smart-181cff0b-a13e-4099-a77e-50c4a0a71938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991940833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_noise_filter.2991940833
Directory /workspace/19.uart_noise_filter/latest

Test location /workspace/coverage/default/19.uart_perf.1448435993
Short name T46
Test name
Test status
Simulation time 7713957028 ps
CPU time 391.55 seconds
Started Jun 05 04:15:16 PM PDT 24
Finished Jun 05 04:21:49 PM PDT 24
Peak memory 200420 kb
Host smart-16de8814-e782-428d-ad51-4e4cb6939fa5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1448435993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.1448435993
Directory /workspace/19.uart_perf/latest

Test location /workspace/coverage/default/19.uart_rx_oversample.3961394553
Short name T967
Test name
Test status
Simulation time 2974925539 ps
CPU time 10.39 seconds
Started Jun 05 04:15:35 PM PDT 24
Finished Jun 05 04:15:46 PM PDT 24
Peak memory 198564 kb
Host smart-4010f0bb-de9f-42f6-b56a-2751549b4785
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3961394553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.3961394553
Directory /workspace/19.uart_rx_oversample/latest

Test location /workspace/coverage/default/19.uart_rx_parity_err.1693794803
Short name T674
Test name
Test status
Simulation time 263224850174 ps
CPU time 357.43 seconds
Started Jun 05 04:15:27 PM PDT 24
Finished Jun 05 04:21:25 PM PDT 24
Peak memory 200424 kb
Host smart-c6b739ad-c85f-4771-a913-aeb79a3276ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693794803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.1693794803
Directory /workspace/19.uart_rx_parity_err/latest

Test location /workspace/coverage/default/19.uart_rx_start_bit_filter.533569528
Short name T897
Test name
Test status
Simulation time 46812430209 ps
CPU time 81.13 seconds
Started Jun 05 04:15:24 PM PDT 24
Finished Jun 05 04:16:46 PM PDT 24
Peak memory 196640 kb
Host smart-be124a83-58b0-4a58-b6ef-1166a0532676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533569528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.533569528
Directory /workspace/19.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/19.uart_smoke.4039044301
Short name T1144
Test name
Test status
Simulation time 447107134 ps
CPU time 2.2 seconds
Started Jun 05 04:15:13 PM PDT 24
Finished Jun 05 04:15:16 PM PDT 24
Peak memory 199648 kb
Host smart-42e283e0-5e2a-422f-bfcb-28948209bea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039044301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_smoke.4039044301
Directory /workspace/19.uart_smoke/latest

Test location /workspace/coverage/default/19.uart_stress_all.2244647321
Short name T922
Test name
Test status
Simulation time 13204573268 ps
CPU time 45.04 seconds
Started Jun 05 04:15:15 PM PDT 24
Finished Jun 05 04:16:01 PM PDT 24
Peak memory 200184 kb
Host smart-325382d1-b214-41d1-878c-33cb4f133f0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244647321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.2244647321
Directory /workspace/19.uart_stress_all/latest

Test location /workspace/coverage/default/19.uart_stress_all_with_rand_reset.1420409482
Short name T1012
Test name
Test status
Simulation time 228428158948 ps
CPU time 689.07 seconds
Started Jun 05 04:15:24 PM PDT 24
Finished Jun 05 04:26:54 PM PDT 24
Peak memory 217128 kb
Host smart-e0d0b414-001c-483f-81cd-9ec4ddfba2cf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420409482 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 19.uart_stress_all_with_rand_reset.1420409482
Directory /workspace/19.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.uart_tx_ovrd.2317589274
Short name T646
Test name
Test status
Simulation time 1246314507 ps
CPU time 1.84 seconds
Started Jun 05 04:15:24 PM PDT 24
Finished Jun 05 04:15:27 PM PDT 24
Peak memory 198616 kb
Host smart-7fbe400a-606e-4a70-8a26-e206c9ef8519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317589274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.2317589274
Directory /workspace/19.uart_tx_ovrd/latest

Test location /workspace/coverage/default/19.uart_tx_rx.4173560998
Short name T408
Test name
Test status
Simulation time 112954036364 ps
CPU time 71.19 seconds
Started Jun 05 04:15:11 PM PDT 24
Finished Jun 05 04:16:24 PM PDT 24
Peak memory 200376 kb
Host smart-bee56719-c907-4b7a-8b98-b7470dba2c48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173560998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.4173560998
Directory /workspace/19.uart_tx_rx/latest

Test location /workspace/coverage/default/190.uart_fifo_reset.3016356087
Short name T1088
Test name
Test status
Simulation time 28834101751 ps
CPU time 8.44 seconds
Started Jun 05 04:18:35 PM PDT 24
Finished Jun 05 04:18:44 PM PDT 24
Peak memory 200436 kb
Host smart-7cb8509c-d8ab-4b0e-a102-8cb36a190727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016356087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.3016356087
Directory /workspace/190.uart_fifo_reset/latest

Test location /workspace/coverage/default/191.uart_fifo_reset.1341445329
Short name T294
Test name
Test status
Simulation time 60016960104 ps
CPU time 22.19 seconds
Started Jun 05 04:18:34 PM PDT 24
Finished Jun 05 04:18:56 PM PDT 24
Peak memory 200368 kb
Host smart-94af45db-075f-4670-91e9-8b8fc534ebd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341445329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.1341445329
Directory /workspace/191.uart_fifo_reset/latest

Test location /workspace/coverage/default/192.uart_fifo_reset.4117727826
Short name T195
Test name
Test status
Simulation time 77319971540 ps
CPU time 25.29 seconds
Started Jun 05 04:18:36 PM PDT 24
Finished Jun 05 04:19:02 PM PDT 24
Peak memory 200348 kb
Host smart-1b943ebd-a929-458e-bf4f-0edce76f1f7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117727826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.4117727826
Directory /workspace/192.uart_fifo_reset/latest

Test location /workspace/coverage/default/193.uart_fifo_reset.2631476968
Short name T197
Test name
Test status
Simulation time 18383231733 ps
CPU time 42.36 seconds
Started Jun 05 04:18:40 PM PDT 24
Finished Jun 05 04:19:23 PM PDT 24
Peak memory 200404 kb
Host smart-ac448f01-a758-426e-9791-7afb49ccf01b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631476968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.2631476968
Directory /workspace/193.uart_fifo_reset/latest

Test location /workspace/coverage/default/194.uart_fifo_reset.704939798
Short name T1116
Test name
Test status
Simulation time 78857320517 ps
CPU time 46.28 seconds
Started Jun 05 04:18:39 PM PDT 24
Finished Jun 05 04:19:26 PM PDT 24
Peak memory 200464 kb
Host smart-61383fa7-f097-4ab2-8eae-db729286f909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704939798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.704939798
Directory /workspace/194.uart_fifo_reset/latest

Test location /workspace/coverage/default/195.uart_fifo_reset.2192649066
Short name T469
Test name
Test status
Simulation time 66275391463 ps
CPU time 115.05 seconds
Started Jun 05 04:18:35 PM PDT 24
Finished Jun 05 04:20:30 PM PDT 24
Peak memory 200444 kb
Host smart-1ac1fb40-e0dd-44a2-bd7d-a1eae0d6e94b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192649066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.2192649066
Directory /workspace/195.uart_fifo_reset/latest

Test location /workspace/coverage/default/196.uart_fifo_reset.2738562453
Short name T602
Test name
Test status
Simulation time 25922941851 ps
CPU time 44.85 seconds
Started Jun 05 04:18:35 PM PDT 24
Finished Jun 05 04:19:21 PM PDT 24
Peak memory 200412 kb
Host smart-38df4338-a33d-4e14-8f55-becd5f4eed38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738562453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.2738562453
Directory /workspace/196.uart_fifo_reset/latest

Test location /workspace/coverage/default/197.uart_fifo_reset.3025850183
Short name T225
Test name
Test status
Simulation time 222570069436 ps
CPU time 250.77 seconds
Started Jun 05 04:18:36 PM PDT 24
Finished Jun 05 04:22:48 PM PDT 24
Peak memory 200332 kb
Host smart-53a49dab-3076-46c5-8888-100404f07f0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025850183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.3025850183
Directory /workspace/197.uart_fifo_reset/latest

Test location /workspace/coverage/default/198.uart_fifo_reset.3610056612
Short name T331
Test name
Test status
Simulation time 11617503755 ps
CPU time 21.05 seconds
Started Jun 05 04:18:36 PM PDT 24
Finished Jun 05 04:18:57 PM PDT 24
Peak memory 200464 kb
Host smart-d3532eb1-05dc-49be-86e3-e74be00e6b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610056612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.3610056612
Directory /workspace/198.uart_fifo_reset/latest

Test location /workspace/coverage/default/199.uart_fifo_reset.170454516
Short name T392
Test name
Test status
Simulation time 41197766928 ps
CPU time 10.18 seconds
Started Jun 05 04:18:36 PM PDT 24
Finished Jun 05 04:18:47 PM PDT 24
Peak memory 200168 kb
Host smart-8ca7973f-1be7-4b76-9cf8-85da711361fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170454516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.170454516
Directory /workspace/199.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_alert_test.477837241
Short name T440
Test name
Test status
Simulation time 108036858 ps
CPU time 0.56 seconds
Started Jun 05 04:14:41 PM PDT 24
Finished Jun 05 04:14:42 PM PDT 24
Peak memory 195792 kb
Host smart-577ee472-2630-4cde-b5a7-c0658f3026e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477837241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.477837241
Directory /workspace/2.uart_alert_test/latest

Test location /workspace/coverage/default/2.uart_fifo_full.1760134259
Short name T309
Test name
Test status
Simulation time 41089822512 ps
CPU time 72.71 seconds
Started Jun 05 04:14:41 PM PDT 24
Finished Jun 05 04:15:54 PM PDT 24
Peak memory 200352 kb
Host smart-0f845f7c-f468-4aef-97c7-59cc11e4aecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760134259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.1760134259
Directory /workspace/2.uart_fifo_full/latest

Test location /workspace/coverage/default/2.uart_fifo_overflow.4287998044
Short name T938
Test name
Test status
Simulation time 32994565525 ps
CPU time 64.68 seconds
Started Jun 05 04:14:50 PM PDT 24
Finished Jun 05 04:15:56 PM PDT 24
Peak memory 200380 kb
Host smart-10ab1564-4652-4ecb-97b9-c679c47f9dce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287998044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.4287998044
Directory /workspace/2.uart_fifo_overflow/latest

Test location /workspace/coverage/default/2.uart_fifo_reset.2608741345
Short name T945
Test name
Test status
Simulation time 126264849210 ps
CPU time 181.58 seconds
Started Jun 05 04:14:43 PM PDT 24
Finished Jun 05 04:17:45 PM PDT 24
Peak memory 200392 kb
Host smart-3128a5fe-7a12-4d0e-9c5b-b4382a8025af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608741345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.2608741345
Directory /workspace/2.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_intr.4102237792
Short name T575
Test name
Test status
Simulation time 72217886636 ps
CPU time 52.33 seconds
Started Jun 05 04:14:46 PM PDT 24
Finished Jun 05 04:15:40 PM PDT 24
Peak memory 200400 kb
Host smart-81719a33-51f6-4f97-88aa-9f413f7bb277
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102237792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.4102237792
Directory /workspace/2.uart_intr/latest

Test location /workspace/coverage/default/2.uart_long_xfer_wo_dly.609574807
Short name T103
Test name
Test status
Simulation time 108734175464 ps
CPU time 214.77 seconds
Started Jun 05 04:14:51 PM PDT 24
Finished Jun 05 04:18:27 PM PDT 24
Peak memory 200368 kb
Host smart-96746647-3aad-4476-b406-c303f1612c09
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=609574807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.609574807
Directory /workspace/2.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/2.uart_loopback.298463848
Short name T566
Test name
Test status
Simulation time 5679802819 ps
CPU time 5.83 seconds
Started Jun 05 04:14:39 PM PDT 24
Finished Jun 05 04:14:45 PM PDT 24
Peak memory 200312 kb
Host smart-7d43ca74-3e7f-412a-8680-0c03daa4590a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298463848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_loopback.298463848
Directory /workspace/2.uart_loopback/latest

Test location /workspace/coverage/default/2.uart_noise_filter.3620963958
Short name T651
Test name
Test status
Simulation time 22802575498 ps
CPU time 35.73 seconds
Started Jun 05 04:15:01 PM PDT 24
Finished Jun 05 04:15:37 PM PDT 24
Peak memory 199364 kb
Host smart-a124d03c-2b54-4a6f-9592-fe8f34b1dfdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620963958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_noise_filter.3620963958
Directory /workspace/2.uart_noise_filter/latest

Test location /workspace/coverage/default/2.uart_perf.1549348985
Short name T701
Test name
Test status
Simulation time 15410001375 ps
CPU time 899.58 seconds
Started Jun 05 04:14:46 PM PDT 24
Finished Jun 05 04:29:47 PM PDT 24
Peak memory 200432 kb
Host smart-c4cee174-6327-4757-a2bb-d51f3b2b0521
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1549348985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.1549348985
Directory /workspace/2.uart_perf/latest

Test location /workspace/coverage/default/2.uart_rx_oversample.1191208843
Short name T1119
Test name
Test status
Simulation time 4287796118 ps
CPU time 35.94 seconds
Started Jun 05 04:14:40 PM PDT 24
Finished Jun 05 04:15:16 PM PDT 24
Peak memory 199784 kb
Host smart-f527e668-bf92-47d2-88b0-5e3a0bcc7252
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1191208843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.1191208843
Directory /workspace/2.uart_rx_oversample/latest

Test location /workspace/coverage/default/2.uart_rx_parity_err.3211149764
Short name T455
Test name
Test status
Simulation time 32136476886 ps
CPU time 57.39 seconds
Started Jun 05 04:14:53 PM PDT 24
Finished Jun 05 04:15:51 PM PDT 24
Peak memory 200336 kb
Host smart-acc4a9b3-9dc7-464e-8137-a6b6e0b29f02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211149764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.3211149764
Directory /workspace/2.uart_rx_parity_err/latest

Test location /workspace/coverage/default/2.uart_rx_start_bit_filter.1148603704
Short name T1084
Test name
Test status
Simulation time 2588485507 ps
CPU time 1.71 seconds
Started Jun 05 04:14:41 PM PDT 24
Finished Jun 05 04:14:43 PM PDT 24
Peak memory 196144 kb
Host smart-3c9c665f-8238-43a1-8a57-726ec657f3fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148603704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.1148603704
Directory /workspace/2.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/2.uart_sec_cm.2303860327
Short name T25
Test name
Test status
Simulation time 151243989 ps
CPU time 0.79 seconds
Started Jun 05 04:14:41 PM PDT 24
Finished Jun 05 04:14:42 PM PDT 24
Peak memory 218636 kb
Host smart-38bedbf5-b915-4a35-a4ff-352470d6e002
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303860327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.2303860327
Directory /workspace/2.uart_sec_cm/latest

Test location /workspace/coverage/default/2.uart_smoke.100051657
Short name T1058
Test name
Test status
Simulation time 6219752498 ps
CPU time 20.12 seconds
Started Jun 05 04:14:39 PM PDT 24
Finished Jun 05 04:15:00 PM PDT 24
Peak memory 200224 kb
Host smart-aced3f03-5898-4439-8629-e3c1c9cc029c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100051657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_smoke.100051657
Directory /workspace/2.uart_smoke/latest

Test location /workspace/coverage/default/2.uart_stress_all.1258824346
Short name T1099
Test name
Test status
Simulation time 44276788333 ps
CPU time 92.98 seconds
Started Jun 05 04:15:03 PM PDT 24
Finished Jun 05 04:16:37 PM PDT 24
Peak memory 200404 kb
Host smart-1224f29e-0ad8-48ad-aad8-306750a082e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258824346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.1258824346
Directory /workspace/2.uart_stress_all/latest

Test location /workspace/coverage/default/2.uart_stress_all_with_rand_reset.319015798
Short name T76
Test name
Test status
Simulation time 35735660151 ps
CPU time 282.98 seconds
Started Jun 05 04:15:04 PM PDT 24
Finished Jun 05 04:19:47 PM PDT 24
Peak memory 208696 kb
Host smart-daf15f35-17f1-4d86-b24e-19a6d3ed681d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319015798 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 2.uart_stress_all_with_rand_reset.319015798
Directory /workspace/2.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.uart_tx_ovrd.1521017901
Short name T1159
Test name
Test status
Simulation time 747338117 ps
CPU time 2.8 seconds
Started Jun 05 04:14:39 PM PDT 24
Finished Jun 05 04:14:42 PM PDT 24
Peak memory 199308 kb
Host smart-4968b606-0faa-422f-a33b-8b68b96dcc28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521017901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.1521017901
Directory /workspace/2.uart_tx_ovrd/latest

Test location /workspace/coverage/default/2.uart_tx_rx.611644013
Short name T607
Test name
Test status
Simulation time 8371579771 ps
CPU time 4.13 seconds
Started Jun 05 04:14:59 PM PDT 24
Finished Jun 05 04:15:04 PM PDT 24
Peak memory 199936 kb
Host smart-c1b05542-6aeb-4807-b755-7a57f756849f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611644013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.611644013
Directory /workspace/2.uart_tx_rx/latest

Test location /workspace/coverage/default/20.uart_fifo_full.3719578807
Short name T725
Test name
Test status
Simulation time 179286209961 ps
CPU time 78.8 seconds
Started Jun 05 04:15:37 PM PDT 24
Finished Jun 05 04:16:56 PM PDT 24
Peak memory 200372 kb
Host smart-f0198494-4790-4127-a22f-35ec5842d1f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719578807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.3719578807
Directory /workspace/20.uart_fifo_full/latest

Test location /workspace/coverage/default/20.uart_fifo_overflow.3891917025
Short name T451
Test name
Test status
Simulation time 35795253776 ps
CPU time 18.53 seconds
Started Jun 05 04:15:23 PM PDT 24
Finished Jun 05 04:15:42 PM PDT 24
Peak memory 200092 kb
Host smart-053c4a96-9845-4f1a-8500-2ab11eaf2491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891917025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.3891917025
Directory /workspace/20.uart_fifo_overflow/latest

Test location /workspace/coverage/default/20.uart_fifo_reset.3645939343
Short name T390
Test name
Test status
Simulation time 15690029964 ps
CPU time 16.6 seconds
Started Jun 05 04:15:13 PM PDT 24
Finished Jun 05 04:15:30 PM PDT 24
Peak memory 200312 kb
Host smart-b0edbddb-d0e1-4c7b-833d-db6a587303fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645939343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.3645939343
Directory /workspace/20.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_intr.1496355979
Short name T341
Test name
Test status
Simulation time 5884716138 ps
CPU time 9.52 seconds
Started Jun 05 04:15:24 PM PDT 24
Finished Jun 05 04:15:34 PM PDT 24
Peak memory 197024 kb
Host smart-49c6f9a7-bdb0-4452-abd6-6f4fd4fbb1ff
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496355979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.1496355979
Directory /workspace/20.uart_intr/latest

Test location /workspace/coverage/default/20.uart_long_xfer_wo_dly.2522217131
Short name T949
Test name
Test status
Simulation time 91136280006 ps
CPU time 370.94 seconds
Started Jun 05 04:15:21 PM PDT 24
Finished Jun 05 04:21:33 PM PDT 24
Peak memory 200416 kb
Host smart-16f57e0a-d0ff-4fe1-8a35-4c2957234e39
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2522217131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.2522217131
Directory /workspace/20.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/20.uart_loopback.2138810557
Short name T739
Test name
Test status
Simulation time 7975419802 ps
CPU time 7.5 seconds
Started Jun 05 04:15:27 PM PDT 24
Finished Jun 05 04:15:35 PM PDT 24
Peak memory 200360 kb
Host smart-b75b48bf-d5ef-4876-bb15-58b55e33cdc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138810557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_loopback.2138810557
Directory /workspace/20.uart_loopback/latest

Test location /workspace/coverage/default/20.uart_noise_filter.3484284684
Short name T939
Test name
Test status
Simulation time 126451468690 ps
CPU time 34.19 seconds
Started Jun 05 04:15:25 PM PDT 24
Finished Jun 05 04:16:00 PM PDT 24
Peak memory 200604 kb
Host smart-724abe34-2401-4512-bb14-0c9d221e3a4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484284684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_noise_filter.3484284684
Directory /workspace/20.uart_noise_filter/latest

Test location /workspace/coverage/default/20.uart_perf.1580828866
Short name T489
Test name
Test status
Simulation time 19467956790 ps
CPU time 483.34 seconds
Started Jun 05 04:15:15 PM PDT 24
Finished Jun 05 04:23:20 PM PDT 24
Peak memory 200412 kb
Host smart-8a181d32-25d3-4ce6-ae93-ed7b41ff1946
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1580828866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.1580828866
Directory /workspace/20.uart_perf/latest

Test location /workspace/coverage/default/20.uart_rx_oversample.1590985037
Short name T696
Test name
Test status
Simulation time 1479915486 ps
CPU time 5.79 seconds
Started Jun 05 04:15:15 PM PDT 24
Finished Jun 05 04:15:22 PM PDT 24
Peak memory 198572 kb
Host smart-4e970682-ed2f-4b3a-8925-7fd47bb13d62
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1590985037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.1590985037
Directory /workspace/20.uart_rx_oversample/latest

Test location /workspace/coverage/default/20.uart_rx_parity_err.2322043845
Short name T740
Test name
Test status
Simulation time 77464590668 ps
CPU time 136.62 seconds
Started Jun 05 04:15:37 PM PDT 24
Finished Jun 05 04:17:55 PM PDT 24
Peak memory 200436 kb
Host smart-f964d0a9-40c8-4572-83ba-8d9ab758e214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322043845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.2322043845
Directory /workspace/20.uart_rx_parity_err/latest

Test location /workspace/coverage/default/20.uart_rx_start_bit_filter.2622334095
Short name T635
Test name
Test status
Simulation time 38405621935 ps
CPU time 32.07 seconds
Started Jun 05 04:15:26 PM PDT 24
Finished Jun 05 04:15:59 PM PDT 24
Peak memory 196732 kb
Host smart-7dbe39aa-cdf1-41af-bea5-f9020c0fa55f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622334095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.2622334095
Directory /workspace/20.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/20.uart_smoke.689650101
Short name T677
Test name
Test status
Simulation time 880892076 ps
CPU time 4.36 seconds
Started Jun 05 04:15:17 PM PDT 24
Finished Jun 05 04:15:22 PM PDT 24
Peak memory 198780 kb
Host smart-1f61115b-feb9-4de0-ac99-6544acbb1c63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689650101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_smoke.689650101
Directory /workspace/20.uart_smoke/latest

Test location /workspace/coverage/default/20.uart_stress_all.2497874912
Short name T1025
Test name
Test status
Simulation time 301048343823 ps
CPU time 1220.65 seconds
Started Jun 05 04:15:20 PM PDT 24
Finished Jun 05 04:35:41 PM PDT 24
Peak memory 200368 kb
Host smart-9130837c-b55c-494c-9057-8be631a3f849
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497874912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.2497874912
Directory /workspace/20.uart_stress_all/latest

Test location /workspace/coverage/default/20.uart_stress_all_with_rand_reset.745369041
Short name T720
Test name
Test status
Simulation time 444166395545 ps
CPU time 1808.51 seconds
Started Jun 05 04:15:32 PM PDT 24
Finished Jun 05 04:45:42 PM PDT 24
Peak memory 216924 kb
Host smart-ff8bb988-2161-4b2c-82ff-c6157560e14b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745369041 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 20.uart_stress_all_with_rand_reset.745369041
Directory /workspace/20.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.uart_tx_ovrd.3349927790
Short name T608
Test name
Test status
Simulation time 870948035 ps
CPU time 3.1 seconds
Started Jun 05 04:15:41 PM PDT 24
Finished Jun 05 04:15:45 PM PDT 24
Peak memory 200256 kb
Host smart-c4949a46-ac9a-403b-8260-f662d9017df3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349927790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.3349927790
Directory /workspace/20.uart_tx_ovrd/latest

Test location /workspace/coverage/default/20.uart_tx_rx.3611425539
Short name T482
Test name
Test status
Simulation time 74596002363 ps
CPU time 187.4 seconds
Started Jun 05 04:15:15 PM PDT 24
Finished Jun 05 04:18:23 PM PDT 24
Peak memory 200124 kb
Host smart-fb818287-219a-41da-89ff-50d8dd527d3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611425539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.3611425539
Directory /workspace/20.uart_tx_rx/latest

Test location /workspace/coverage/default/200.uart_fifo_reset.144013258
Short name T856
Test name
Test status
Simulation time 45307208770 ps
CPU time 18.55 seconds
Started Jun 05 04:18:38 PM PDT 24
Finished Jun 05 04:18:57 PM PDT 24
Peak memory 200248 kb
Host smart-4e11e3c1-d6a6-4dec-90b6-769f8cf68962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144013258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.144013258
Directory /workspace/200.uart_fifo_reset/latest

Test location /workspace/coverage/default/201.uart_fifo_reset.3782160514
Short name T965
Test name
Test status
Simulation time 102206913021 ps
CPU time 45.18 seconds
Started Jun 05 04:18:34 PM PDT 24
Finished Jun 05 04:19:20 PM PDT 24
Peak memory 200420 kb
Host smart-08702c66-27d7-4f93-a051-b17039051dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782160514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.3782160514
Directory /workspace/201.uart_fifo_reset/latest

Test location /workspace/coverage/default/202.uart_fifo_reset.703360194
Short name T154
Test name
Test status
Simulation time 85241337100 ps
CPU time 174.65 seconds
Started Jun 05 04:18:34 PM PDT 24
Finished Jun 05 04:21:30 PM PDT 24
Peak memory 200464 kb
Host smart-2023b421-abe6-4d0c-a100-94bf71ca4e2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703360194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.703360194
Directory /workspace/202.uart_fifo_reset/latest

Test location /workspace/coverage/default/203.uart_fifo_reset.559488650
Short name T186
Test name
Test status
Simulation time 150681195476 ps
CPU time 234.1 seconds
Started Jun 05 04:18:36 PM PDT 24
Finished Jun 05 04:22:31 PM PDT 24
Peak memory 200488 kb
Host smart-991d969c-1da7-4e23-8603-ed49914aae64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559488650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.559488650
Directory /workspace/203.uart_fifo_reset/latest

Test location /workspace/coverage/default/204.uart_fifo_reset.532930925
Short name T54
Test name
Test status
Simulation time 21495032486 ps
CPU time 33.2 seconds
Started Jun 05 04:18:35 PM PDT 24
Finished Jun 05 04:19:09 PM PDT 24
Peak memory 200364 kb
Host smart-031eb785-055e-4ae6-8c4e-013957a13133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532930925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.532930925
Directory /workspace/204.uart_fifo_reset/latest

Test location /workspace/coverage/default/206.uart_fifo_reset.54839695
Short name T398
Test name
Test status
Simulation time 142284787429 ps
CPU time 60.99 seconds
Started Jun 05 04:18:33 PM PDT 24
Finished Jun 05 04:19:35 PM PDT 24
Peak memory 199180 kb
Host smart-076c537b-45e7-432c-8342-d4272a614899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54839695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.54839695
Directory /workspace/206.uart_fifo_reset/latest

Test location /workspace/coverage/default/207.uart_fifo_reset.1775647762
Short name T1024
Test name
Test status
Simulation time 47119172708 ps
CPU time 19.89 seconds
Started Jun 05 04:18:36 PM PDT 24
Finished Jun 05 04:18:56 PM PDT 24
Peak memory 200340 kb
Host smart-43f28713-fe75-497a-91a4-fb67c7266eb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775647762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.1775647762
Directory /workspace/207.uart_fifo_reset/latest

Test location /workspace/coverage/default/208.uart_fifo_reset.1137806705
Short name T1103
Test name
Test status
Simulation time 29089315895 ps
CPU time 13.81 seconds
Started Jun 05 04:18:36 PM PDT 24
Finished Jun 05 04:18:50 PM PDT 24
Peak memory 200376 kb
Host smart-4ed1b8e4-8d3a-49b5-a846-25c288b5ab27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137806705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.1137806705
Directory /workspace/208.uart_fifo_reset/latest

Test location /workspace/coverage/default/209.uart_fifo_reset.2985233698
Short name T708
Test name
Test status
Simulation time 21055140213 ps
CPU time 17.49 seconds
Started Jun 05 04:18:40 PM PDT 24
Finished Jun 05 04:18:58 PM PDT 24
Peak memory 200188 kb
Host smart-233a97da-2db1-45a8-b42f-c4638fecd437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985233698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.2985233698
Directory /workspace/209.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_alert_test.90491401
Short name T1071
Test name
Test status
Simulation time 15091289 ps
CPU time 0.57 seconds
Started Jun 05 04:15:43 PM PDT 24
Finished Jun 05 04:15:44 PM PDT 24
Peak memory 195756 kb
Host smart-d4ce1abf-4db9-4c4f-b38c-8487eef82b88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90491401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.90491401
Directory /workspace/21.uart_alert_test/latest

Test location /workspace/coverage/default/21.uart_fifo_full.754305708
Short name T166
Test name
Test status
Simulation time 257873568265 ps
CPU time 622.98 seconds
Started Jun 05 04:15:22 PM PDT 24
Finished Jun 05 04:25:46 PM PDT 24
Peak memory 200440 kb
Host smart-18d542f6-729f-48e6-8602-ab0793d5e686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754305708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.754305708
Directory /workspace/21.uart_fifo_full/latest

Test location /workspace/coverage/default/21.uart_fifo_overflow.3605331175
Short name T1030
Test name
Test status
Simulation time 33747310868 ps
CPU time 35.29 seconds
Started Jun 05 04:15:27 PM PDT 24
Finished Jun 05 04:16:03 PM PDT 24
Peak memory 200376 kb
Host smart-365ffdc0-ed81-4862-879b-e90e6436d193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605331175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.3605331175
Directory /workspace/21.uart_fifo_overflow/latest

Test location /workspace/coverage/default/21.uart_intr.2540561415
Short name T17
Test name
Test status
Simulation time 56686554840 ps
CPU time 30.34 seconds
Started Jun 05 04:15:43 PM PDT 24
Finished Jun 05 04:16:14 PM PDT 24
Peak memory 200404 kb
Host smart-b1a236c5-7ae4-489f-9abe-61889c742128
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540561415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.2540561415
Directory /workspace/21.uart_intr/latest

Test location /workspace/coverage/default/21.uart_long_xfer_wo_dly.923676940
Short name T1032
Test name
Test status
Simulation time 236537929360 ps
CPU time 1837.15 seconds
Started Jun 05 04:15:35 PM PDT 24
Finished Jun 05 04:46:13 PM PDT 24
Peak memory 200360 kb
Host smart-b58b83f8-951c-4c36-9adc-26bfca39393c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=923676940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.923676940
Directory /workspace/21.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/21.uart_loopback.76956485
Short name T920
Test name
Test status
Simulation time 11067305262 ps
CPU time 5.85 seconds
Started Jun 05 04:15:32 PM PDT 24
Finished Jun 05 04:15:38 PM PDT 24
Peak memory 199336 kb
Host smart-51514cb5-4479-448d-a136-ab955fbbd85e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76956485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_loopback.76956485
Directory /workspace/21.uart_loopback/latest

Test location /workspace/coverage/default/21.uart_noise_filter.540319718
Short name T505
Test name
Test status
Simulation time 128467694651 ps
CPU time 271.16 seconds
Started Jun 05 04:15:42 PM PDT 24
Finished Jun 05 04:20:14 PM PDT 24
Peak memory 208784 kb
Host smart-823db421-7be1-4c3f-b7e3-fb188cbc62a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540319718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_noise_filter.540319718
Directory /workspace/21.uart_noise_filter/latest

Test location /workspace/coverage/default/21.uart_perf.3429268843
Short name T1091
Test name
Test status
Simulation time 29464468288 ps
CPU time 380.93 seconds
Started Jun 05 04:15:27 PM PDT 24
Finished Jun 05 04:21:49 PM PDT 24
Peak memory 200412 kb
Host smart-f61a52c0-3cf5-447f-a739-cab52c4136c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3429268843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.3429268843
Directory /workspace/21.uart_perf/latest

Test location /workspace/coverage/default/21.uart_rx_oversample.1685394317
Short name T1120
Test name
Test status
Simulation time 5958507173 ps
CPU time 7.62 seconds
Started Jun 05 04:15:32 PM PDT 24
Finished Jun 05 04:15:40 PM PDT 24
Peak memory 198516 kb
Host smart-6ab8ae8b-adb0-4167-a3ff-ea75003d0d42
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1685394317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.1685394317
Directory /workspace/21.uart_rx_oversample/latest

Test location /workspace/coverage/default/21.uart_rx_parity_err.998969912
Short name T884
Test name
Test status
Simulation time 142552011369 ps
CPU time 24.05 seconds
Started Jun 05 04:15:34 PM PDT 24
Finished Jun 05 04:15:58 PM PDT 24
Peak memory 200168 kb
Host smart-13835961-333b-4ddf-b238-a49530fd09c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998969912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.998969912
Directory /workspace/21.uart_rx_parity_err/latest

Test location /workspace/coverage/default/21.uart_rx_start_bit_filter.2495874030
Short name T969
Test name
Test status
Simulation time 3953752244 ps
CPU time 2.67 seconds
Started Jun 05 04:15:22 PM PDT 24
Finished Jun 05 04:15:26 PM PDT 24
Peak memory 196452 kb
Host smart-b1b6e15d-7c25-4606-8800-6ad1473375f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495874030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.2495874030
Directory /workspace/21.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/21.uart_smoke.433352595
Short name T1095
Test name
Test status
Simulation time 477631499 ps
CPU time 1.86 seconds
Started Jun 05 04:15:21 PM PDT 24
Finished Jun 05 04:15:23 PM PDT 24
Peak memory 198948 kb
Host smart-16ef0689-b78b-4bd9-bbd9-c5b29368e59c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433352595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_smoke.433352595
Directory /workspace/21.uart_smoke/latest

Test location /workspace/coverage/default/21.uart_stress_all.2217226448
Short name T631
Test name
Test status
Simulation time 160385944223 ps
CPU time 826.87 seconds
Started Jun 05 04:15:21 PM PDT 24
Finished Jun 05 04:29:09 PM PDT 24
Peak memory 200440 kb
Host smart-5226a15c-53de-44d1-9b07-750b498f1ca4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217226448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.2217226448
Directory /workspace/21.uart_stress_all/latest

Test location /workspace/coverage/default/21.uart_stress_all_with_rand_reset.2501832563
Short name T1051
Test name
Test status
Simulation time 45458366204 ps
CPU time 643 seconds
Started Jun 05 04:15:22 PM PDT 24
Finished Jun 05 04:26:06 PM PDT 24
Peak memory 216892 kb
Host smart-0291f773-99e8-4563-9f4a-023f635cef85
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501832563 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 21.uart_stress_all_with_rand_reset.2501832563
Directory /workspace/21.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.uart_tx_ovrd.500427867
Short name T369
Test name
Test status
Simulation time 6626482656 ps
CPU time 25.86 seconds
Started Jun 05 04:15:31 PM PDT 24
Finished Jun 05 04:15:57 PM PDT 24
Peak memory 199680 kb
Host smart-6c6a7deb-87a2-4d50-8714-29a311caaf12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500427867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.500427867
Directory /workspace/21.uart_tx_ovrd/latest

Test location /workspace/coverage/default/21.uart_tx_rx.2029569257
Short name T460
Test name
Test status
Simulation time 114210588363 ps
CPU time 39.54 seconds
Started Jun 05 04:15:21 PM PDT 24
Finished Jun 05 04:16:01 PM PDT 24
Peak memory 200440 kb
Host smart-dd5ec062-b44d-4243-949c-29568ed8b522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029569257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.2029569257
Directory /workspace/21.uart_tx_rx/latest

Test location /workspace/coverage/default/210.uart_fifo_reset.745880616
Short name T231
Test name
Test status
Simulation time 133659643314 ps
CPU time 178.94 seconds
Started Jun 05 04:18:40 PM PDT 24
Finished Jun 05 04:21:39 PM PDT 24
Peak memory 200436 kb
Host smart-d2531d6c-f4f1-4e0c-8d4d-fa3c89f15701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745880616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.745880616
Directory /workspace/210.uart_fifo_reset/latest

Test location /workspace/coverage/default/212.uart_fifo_reset.480794355
Short name T202
Test name
Test status
Simulation time 34548339155 ps
CPU time 22.47 seconds
Started Jun 05 04:18:44 PM PDT 24
Finished Jun 05 04:19:08 PM PDT 24
Peak memory 200260 kb
Host smart-ed212610-d95c-4564-a15a-b60859da29d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480794355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.480794355
Directory /workspace/212.uart_fifo_reset/latest

Test location /workspace/coverage/default/213.uart_fifo_reset.2633129551
Short name T1121
Test name
Test status
Simulation time 23660546974 ps
CPU time 41.23 seconds
Started Jun 05 04:18:44 PM PDT 24
Finished Jun 05 04:19:26 PM PDT 24
Peak memory 200492 kb
Host smart-bfbcd919-515f-445a-9aef-a84aad4bb7fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633129551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.2633129551
Directory /workspace/213.uart_fifo_reset/latest

Test location /workspace/coverage/default/214.uart_fifo_reset.845691159
Short name T211
Test name
Test status
Simulation time 53500869396 ps
CPU time 26.57 seconds
Started Jun 05 04:18:45 PM PDT 24
Finished Jun 05 04:19:12 PM PDT 24
Peak memory 200380 kb
Host smart-9e32d5a5-7108-4346-99d5-7b377ffc9b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845691159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.845691159
Directory /workspace/214.uart_fifo_reset/latest

Test location /workspace/coverage/default/216.uart_fifo_reset.2663108183
Short name T1070
Test name
Test status
Simulation time 26882910656 ps
CPU time 11.49 seconds
Started Jun 05 04:18:45 PM PDT 24
Finished Jun 05 04:18:57 PM PDT 24
Peak memory 199956 kb
Host smart-f63b7d9e-0270-42ca-ac6c-0855bb615fa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663108183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.2663108183
Directory /workspace/216.uart_fifo_reset/latest

Test location /workspace/coverage/default/217.uart_fifo_reset.969684134
Short name T194
Test name
Test status
Simulation time 90679771877 ps
CPU time 23.71 seconds
Started Jun 05 04:18:44 PM PDT 24
Finished Jun 05 04:19:09 PM PDT 24
Peak memory 200500 kb
Host smart-67b4f415-c07c-479a-bdd4-74309e0b06c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969684134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.969684134
Directory /workspace/217.uart_fifo_reset/latest

Test location /workspace/coverage/default/218.uart_fifo_reset.2544252819
Short name T268
Test name
Test status
Simulation time 74116144726 ps
CPU time 42.19 seconds
Started Jun 05 04:18:46 PM PDT 24
Finished Jun 05 04:19:29 PM PDT 24
Peak memory 200356 kb
Host smart-9b444748-73c0-4556-b811-592ee42e29c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544252819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.2544252819
Directory /workspace/218.uart_fifo_reset/latest

Test location /workspace/coverage/default/219.uart_fifo_reset.3877541043
Short name T809
Test name
Test status
Simulation time 74459841328 ps
CPU time 36.22 seconds
Started Jun 05 04:18:46 PM PDT 24
Finished Jun 05 04:19:23 PM PDT 24
Peak memory 200416 kb
Host smart-cd1f20a0-72ad-4dbc-b43f-354cc1512ede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877541043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.3877541043
Directory /workspace/219.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_alert_test.90699460
Short name T67
Test name
Test status
Simulation time 69548197 ps
CPU time 0.6 seconds
Started Jun 05 04:15:42 PM PDT 24
Finished Jun 05 04:15:43 PM PDT 24
Peak memory 194760 kb
Host smart-f6052dcb-55ef-47eb-9448-be572ccda620
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90699460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.90699460
Directory /workspace/22.uart_alert_test/latest

Test location /workspace/coverage/default/22.uart_fifo_full.1673910082
Short name T1034
Test name
Test status
Simulation time 123821235782 ps
CPU time 55.24 seconds
Started Jun 05 04:15:39 PM PDT 24
Finished Jun 05 04:16:35 PM PDT 24
Peak memory 200424 kb
Host smart-9503824d-6b39-43f3-950f-b01e66fdf241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673910082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.1673910082
Directory /workspace/22.uart_fifo_full/latest

Test location /workspace/coverage/default/22.uart_fifo_overflow.2087036835
Short name T407
Test name
Test status
Simulation time 161431667636 ps
CPU time 24.8 seconds
Started Jun 05 04:15:27 PM PDT 24
Finished Jun 05 04:15:53 PM PDT 24
Peak memory 200428 kb
Host smart-b86db18c-8629-4bb7-9c8e-289749fffe8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087036835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.2087036835
Directory /workspace/22.uart_fifo_overflow/latest

Test location /workspace/coverage/default/22.uart_fifo_reset.2309708575
Short name T191
Test name
Test status
Simulation time 37607774470 ps
CPU time 19.3 seconds
Started Jun 05 04:15:39 PM PDT 24
Finished Jun 05 04:15:59 PM PDT 24
Peak memory 200412 kb
Host smart-20027919-3856-4283-9637-b733147e2fee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309708575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.2309708575
Directory /workspace/22.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_intr.2493772356
Short name T724
Test name
Test status
Simulation time 33875320519 ps
CPU time 19.54 seconds
Started Jun 05 04:15:19 PM PDT 24
Finished Jun 05 04:15:40 PM PDT 24
Peak memory 200248 kb
Host smart-edafbabb-382e-4e85-83df-979b0e2de261
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493772356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.2493772356
Directory /workspace/22.uart_intr/latest

Test location /workspace/coverage/default/22.uart_long_xfer_wo_dly.1223160274
Short name T1001
Test name
Test status
Simulation time 49837420823 ps
CPU time 177.85 seconds
Started Jun 05 04:15:41 PM PDT 24
Finished Jun 05 04:18:39 PM PDT 24
Peak memory 200316 kb
Host smart-437f46f5-8d60-48c9-93d0-5153eb0715fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1223160274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.1223160274
Directory /workspace/22.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/22.uart_loopback.1993351908
Short name T914
Test name
Test status
Simulation time 1683443423 ps
CPU time 3.34 seconds
Started Jun 05 04:15:46 PM PDT 24
Finished Jun 05 04:15:50 PM PDT 24
Peak memory 198944 kb
Host smart-bff46aff-ea3a-49ac-9bdd-a8331db728da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993351908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_loopback.1993351908
Directory /workspace/22.uart_loopback/latest

Test location /workspace/coverage/default/22.uart_noise_filter.1105089868
Short name T684
Test name
Test status
Simulation time 215550733041 ps
CPU time 39.67 seconds
Started Jun 05 04:15:42 PM PDT 24
Finished Jun 05 04:16:23 PM PDT 24
Peak memory 216836 kb
Host smart-80780983-617e-47fc-be8b-d750d5ee902a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105089868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_noise_filter.1105089868
Directory /workspace/22.uart_noise_filter/latest

Test location /workspace/coverage/default/22.uart_perf.1632756865
Short name T781
Test name
Test status
Simulation time 9764771981 ps
CPU time 449.66 seconds
Started Jun 05 04:15:44 PM PDT 24
Finished Jun 05 04:23:15 PM PDT 24
Peak memory 200308 kb
Host smart-c7ad54f2-67b0-4851-baf8-dab4c04c6992
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1632756865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.1632756865
Directory /workspace/22.uart_perf/latest

Test location /workspace/coverage/default/22.uart_rx_oversample.3728614205
Short name T771
Test name
Test status
Simulation time 2224873532 ps
CPU time 11.86 seconds
Started Jun 05 04:15:21 PM PDT 24
Finished Jun 05 04:15:34 PM PDT 24
Peak memory 198956 kb
Host smart-4cd3c364-834f-407f-913b-1745c2224bce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3728614205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.3728614205
Directory /workspace/22.uart_rx_oversample/latest

Test location /workspace/coverage/default/22.uart_rx_parity_err.1485122276
Short name T45
Test name
Test status
Simulation time 310762093379 ps
CPU time 146.35 seconds
Started Jun 05 04:15:20 PM PDT 24
Finished Jun 05 04:17:47 PM PDT 24
Peak memory 200388 kb
Host smart-c352115d-fc93-4498-93dd-39299e156529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485122276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.1485122276
Directory /workspace/22.uart_rx_parity_err/latest

Test location /workspace/coverage/default/22.uart_rx_start_bit_filter.4030711134
Short name T472
Test name
Test status
Simulation time 1521566555 ps
CPU time 3.56 seconds
Started Jun 05 04:15:29 PM PDT 24
Finished Jun 05 04:15:33 PM PDT 24
Peak memory 195800 kb
Host smart-51fc09f3-5e73-480b-85af-ae07b053dd49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030711134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.4030711134
Directory /workspace/22.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/22.uart_smoke.2885303125
Short name T909
Test name
Test status
Simulation time 652158540 ps
CPU time 3.33 seconds
Started Jun 05 04:15:33 PM PDT 24
Finished Jun 05 04:15:37 PM PDT 24
Peak memory 200288 kb
Host smart-43d92192-19f5-4db9-8e87-908f226cf8ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885303125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_smoke.2885303125
Directory /workspace/22.uart_smoke/latest

Test location /workspace/coverage/default/22.uart_stress_all.2433277693
Short name T658
Test name
Test status
Simulation time 533324859874 ps
CPU time 373.61 seconds
Started Jun 05 04:15:41 PM PDT 24
Finished Jun 05 04:21:55 PM PDT 24
Peak memory 200552 kb
Host smart-f5c033a7-e4b7-41e1-88bf-bfa36cdf3568
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433277693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.2433277693
Directory /workspace/22.uart_stress_all/latest

Test location /workspace/coverage/default/22.uart_tx_ovrd.2875311736
Short name T910
Test name
Test status
Simulation time 598902331 ps
CPU time 2.36 seconds
Started Jun 05 04:15:30 PM PDT 24
Finished Jun 05 04:15:33 PM PDT 24
Peak memory 198728 kb
Host smart-984dd56b-c77d-4c25-8bd5-a363f231ee1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875311736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.2875311736
Directory /workspace/22.uart_tx_ovrd/latest

Test location /workspace/coverage/default/22.uart_tx_rx.2332960567
Short name T745
Test name
Test status
Simulation time 85841000682 ps
CPU time 33.88 seconds
Started Jun 05 04:15:22 PM PDT 24
Finished Jun 05 04:15:57 PM PDT 24
Peak memory 200544 kb
Host smart-94d39322-4962-4fbe-b3c8-1a85922af588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332960567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.2332960567
Directory /workspace/22.uart_tx_rx/latest

Test location /workspace/coverage/default/220.uart_fifo_reset.3547482513
Short name T895
Test name
Test status
Simulation time 49636389315 ps
CPU time 92.44 seconds
Started Jun 05 04:18:47 PM PDT 24
Finished Jun 05 04:20:21 PM PDT 24
Peak memory 200384 kb
Host smart-b47084ae-6f4e-4232-bdd7-b3aa6f3d5219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547482513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.3547482513
Directory /workspace/220.uart_fifo_reset/latest

Test location /workspace/coverage/default/221.uart_fifo_reset.2121614890
Short name T891
Test name
Test status
Simulation time 45511450259 ps
CPU time 20.13 seconds
Started Jun 05 04:18:46 PM PDT 24
Finished Jun 05 04:19:07 PM PDT 24
Peak memory 200392 kb
Host smart-52c07e07-184b-4ec1-907a-665ff173618a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121614890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.2121614890
Directory /workspace/221.uart_fifo_reset/latest

Test location /workspace/coverage/default/222.uart_fifo_reset.923476569
Short name T654
Test name
Test status
Simulation time 172186176435 ps
CPU time 301.93 seconds
Started Jun 05 04:18:48 PM PDT 24
Finished Jun 05 04:23:51 PM PDT 24
Peak memory 200428 kb
Host smart-de290d9e-ef70-4c1e-a153-5258cc204d34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923476569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.923476569
Directory /workspace/222.uart_fifo_reset/latest

Test location /workspace/coverage/default/224.uart_fifo_reset.2675395164
Short name T986
Test name
Test status
Simulation time 22705252498 ps
CPU time 10.25 seconds
Started Jun 05 04:18:47 PM PDT 24
Finished Jun 05 04:18:58 PM PDT 24
Peak memory 200356 kb
Host smart-2c6d9a81-51a9-4c4e-a054-e18a18fd9a52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675395164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.2675395164
Directory /workspace/224.uart_fifo_reset/latest

Test location /workspace/coverage/default/225.uart_fifo_reset.2980153282
Short name T518
Test name
Test status
Simulation time 15364754761 ps
CPU time 35.54 seconds
Started Jun 05 04:18:45 PM PDT 24
Finished Jun 05 04:19:22 PM PDT 24
Peak memory 200452 kb
Host smart-145faa4c-d825-420e-ba1c-a7c65b2f667d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980153282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.2980153282
Directory /workspace/225.uart_fifo_reset/latest

Test location /workspace/coverage/default/226.uart_fifo_reset.1506246154
Short name T952
Test name
Test status
Simulation time 10980739081 ps
CPU time 10.62 seconds
Started Jun 05 04:18:44 PM PDT 24
Finished Jun 05 04:18:56 PM PDT 24
Peak memory 200380 kb
Host smart-c1c8dd17-869e-40e4-a74f-26606bae7a9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506246154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.1506246154
Directory /workspace/226.uart_fifo_reset/latest

Test location /workspace/coverage/default/227.uart_fifo_reset.3424929807
Short name T50
Test name
Test status
Simulation time 113748475809 ps
CPU time 165.46 seconds
Started Jun 05 04:18:46 PM PDT 24
Finished Jun 05 04:21:32 PM PDT 24
Peak memory 200372 kb
Host smart-18d1f217-1e4e-403b-a01e-23d30f7f84c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424929807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.3424929807
Directory /workspace/227.uart_fifo_reset/latest

Test location /workspace/coverage/default/228.uart_fifo_reset.1580695923
Short name T10
Test name
Test status
Simulation time 19119844455 ps
CPU time 15.61 seconds
Started Jun 05 04:18:44 PM PDT 24
Finished Jun 05 04:19:01 PM PDT 24
Peak memory 200376 kb
Host smart-190182a0-9c46-46ac-bc11-b49954c23f48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580695923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.1580695923
Directory /workspace/228.uart_fifo_reset/latest

Test location /workspace/coverage/default/229.uart_fifo_reset.2451878161
Short name T790
Test name
Test status
Simulation time 160900804312 ps
CPU time 19.08 seconds
Started Jun 05 04:18:47 PM PDT 24
Finished Jun 05 04:19:07 PM PDT 24
Peak memory 200424 kb
Host smart-85c845cc-6aba-4982-97fe-dea1f8bf1867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451878161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.2451878161
Directory /workspace/229.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_alert_test.3295181008
Short name T1172
Test name
Test status
Simulation time 147521113 ps
CPU time 0.57 seconds
Started Jun 05 04:15:46 PM PDT 24
Finished Jun 05 04:15:47 PM PDT 24
Peak memory 195808 kb
Host smart-76097273-085f-47a1-8c48-5476ed9bf3df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295181008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.3295181008
Directory /workspace/23.uart_alert_test/latest

Test location /workspace/coverage/default/23.uart_fifo_full.195211646
Short name T835
Test name
Test status
Simulation time 162010150208 ps
CPU time 144.07 seconds
Started Jun 05 04:15:29 PM PDT 24
Finished Jun 05 04:17:53 PM PDT 24
Peak memory 200344 kb
Host smart-fe2bc871-02a0-4b83-882a-6f57a4c4043e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195211646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.195211646
Directory /workspace/23.uart_fifo_full/latest

Test location /workspace/coverage/default/23.uart_fifo_overflow.3008297523
Short name T1090
Test name
Test status
Simulation time 26755094333 ps
CPU time 49.82 seconds
Started Jun 05 04:15:47 PM PDT 24
Finished Jun 05 04:16:38 PM PDT 24
Peak memory 200364 kb
Host smart-092c3635-43b6-4f4d-96ad-dc58a4e9e39f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008297523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.3008297523
Directory /workspace/23.uart_fifo_overflow/latest

Test location /workspace/coverage/default/23.uart_fifo_reset.1985862263
Short name T210
Test name
Test status
Simulation time 35973615694 ps
CPU time 28.95 seconds
Started Jun 05 04:15:31 PM PDT 24
Finished Jun 05 04:16:01 PM PDT 24
Peak memory 200460 kb
Host smart-7f175002-b103-4a38-a143-be4e265243ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985862263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.1985862263
Directory /workspace/23.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_intr.1945855159
Short name T754
Test name
Test status
Simulation time 30657147510 ps
CPU time 15.87 seconds
Started Jun 05 04:15:42 PM PDT 24
Finished Jun 05 04:15:59 PM PDT 24
Peak memory 200336 kb
Host smart-0fb5d2cd-bdaa-4146-84dc-f9fe5aff3745
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945855159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.1945855159
Directory /workspace/23.uart_intr/latest

Test location /workspace/coverage/default/23.uart_long_xfer_wo_dly.4006094277
Short name T903
Test name
Test status
Simulation time 55897644265 ps
CPU time 339.62 seconds
Started Jun 05 04:15:45 PM PDT 24
Finished Jun 05 04:21:26 PM PDT 24
Peak memory 200448 kb
Host smart-ff64bf5a-9588-44e3-af72-e1d083c6f303
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4006094277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.4006094277
Directory /workspace/23.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/23.uart_loopback.1975584131
Short name T1041
Test name
Test status
Simulation time 2887989737 ps
CPU time 2.7 seconds
Started Jun 05 04:15:44 PM PDT 24
Finished Jun 05 04:15:47 PM PDT 24
Peak memory 199416 kb
Host smart-deb318a4-9e61-47dd-8a20-ed95c9c68876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975584131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_loopback.1975584131
Directory /workspace/23.uart_loopback/latest

Test location /workspace/coverage/default/23.uart_noise_filter.2331235442
Short name T1167
Test name
Test status
Simulation time 142854567706 ps
CPU time 20.42 seconds
Started Jun 05 04:15:44 PM PDT 24
Finished Jun 05 04:16:05 PM PDT 24
Peak memory 198376 kb
Host smart-3063333d-167e-42c4-aa58-b26d6bcd59fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331235442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_noise_filter.2331235442
Directory /workspace/23.uart_noise_filter/latest

Test location /workspace/coverage/default/23.uart_perf.2653405226
Short name T795
Test name
Test status
Simulation time 27633881164 ps
CPU time 1166.5 seconds
Started Jun 05 04:15:41 PM PDT 24
Finished Jun 05 04:35:09 PM PDT 24
Peak memory 200392 kb
Host smart-45750678-31e0-4d0d-8e50-861f85f4fdc4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2653405226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.2653405226
Directory /workspace/23.uart_perf/latest

Test location /workspace/coverage/default/23.uart_rx_oversample.1517998403
Short name T675
Test name
Test status
Simulation time 5621145521 ps
CPU time 13.55 seconds
Started Jun 05 04:15:44 PM PDT 24
Finished Jun 05 04:15:58 PM PDT 24
Peak memory 198796 kb
Host smart-2f50dd77-9ea1-4086-8b42-9add6890f07e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1517998403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.1517998403
Directory /workspace/23.uart_rx_oversample/latest

Test location /workspace/coverage/default/23.uart_rx_parity_err.3947195281
Short name T526
Test name
Test status
Simulation time 201639688761 ps
CPU time 299.05 seconds
Started Jun 05 04:15:29 PM PDT 24
Finished Jun 05 04:20:29 PM PDT 24
Peak memory 200400 kb
Host smart-6b17626c-fe11-49e0-aeda-2ba39232b0a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947195281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.3947195281
Directory /workspace/23.uart_rx_parity_err/latest

Test location /workspace/coverage/default/23.uart_rx_start_bit_filter.1766436591
Short name T935
Test name
Test status
Simulation time 2792200316 ps
CPU time 1.74 seconds
Started Jun 05 04:15:44 PM PDT 24
Finished Jun 05 04:15:47 PM PDT 24
Peak memory 196164 kb
Host smart-e5ff5997-37d7-4cd5-8762-d67e78791b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766436591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.1766436591
Directory /workspace/23.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/23.uart_smoke.126865947
Short name T841
Test name
Test status
Simulation time 496837988 ps
CPU time 1.33 seconds
Started Jun 05 04:15:44 PM PDT 24
Finished Jun 05 04:15:46 PM PDT 24
Peak memory 199164 kb
Host smart-e6e865ae-2f78-4970-85de-d36386e00b5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126865947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_smoke.126865947
Directory /workspace/23.uart_smoke/latest

Test location /workspace/coverage/default/23.uart_stress_all.4285290898
Short name T1122
Test name
Test status
Simulation time 112284322251 ps
CPU time 448.38 seconds
Started Jun 05 04:15:29 PM PDT 24
Finished Jun 05 04:22:58 PM PDT 24
Peak memory 200564 kb
Host smart-491e10c4-06b7-4685-a0cf-429e3bbd7ebc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285290898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.4285290898
Directory /workspace/23.uart_stress_all/latest

Test location /workspace/coverage/default/23.uart_stress_all_with_rand_reset.2948586264
Short name T733
Test name
Test status
Simulation time 89416811280 ps
CPU time 137.18 seconds
Started Jun 05 04:15:40 PM PDT 24
Finished Jun 05 04:17:58 PM PDT 24
Peak memory 217276 kb
Host smart-489598b9-0dcc-4f1a-8ce5-ef7dd169ae96
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948586264 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 23.uart_stress_all_with_rand_reset.2948586264
Directory /workspace/23.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.uart_tx_ovrd.3945113428
Short name T551
Test name
Test status
Simulation time 6733766386 ps
CPU time 9.71 seconds
Started Jun 05 04:15:43 PM PDT 24
Finished Jun 05 04:15:53 PM PDT 24
Peak memory 199776 kb
Host smart-949064cd-72c9-4e07-bbca-755c801d1302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945113428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.3945113428
Directory /workspace/23.uart_tx_ovrd/latest

Test location /workspace/coverage/default/23.uart_tx_rx.3483719174
Short name T1112
Test name
Test status
Simulation time 36653949897 ps
CPU time 17.39 seconds
Started Jun 05 04:15:30 PM PDT 24
Finished Jun 05 04:15:48 PM PDT 24
Peak memory 200380 kb
Host smart-facf3ea2-a3bb-441f-8d4f-1307855f1a09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483719174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.3483719174
Directory /workspace/23.uart_tx_rx/latest

Test location /workspace/coverage/default/230.uart_fifo_reset.1501638872
Short name T921
Test name
Test status
Simulation time 19320847375 ps
CPU time 30.58 seconds
Started Jun 05 04:18:48 PM PDT 24
Finished Jun 05 04:19:20 PM PDT 24
Peak memory 200448 kb
Host smart-d0e166b0-6691-4bc0-acc5-4366bb63a6ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501638872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.1501638872
Directory /workspace/230.uart_fifo_reset/latest

Test location /workspace/coverage/default/232.uart_fifo_reset.3640832909
Short name T1137
Test name
Test status
Simulation time 170192544675 ps
CPU time 345.76 seconds
Started Jun 05 04:18:52 PM PDT 24
Finished Jun 05 04:24:38 PM PDT 24
Peak memory 200480 kb
Host smart-4dd86309-ae80-4116-8f26-d26b5c433bbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640832909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.3640832909
Directory /workspace/232.uart_fifo_reset/latest

Test location /workspace/coverage/default/233.uart_fifo_reset.1005039846
Short name T1081
Test name
Test status
Simulation time 218493554700 ps
CPU time 168.94 seconds
Started Jun 05 04:18:51 PM PDT 24
Finished Jun 05 04:21:41 PM PDT 24
Peak memory 200340 kb
Host smart-ddc95960-21b2-4ca9-bd77-1a849f6ac3e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005039846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.1005039846
Directory /workspace/233.uart_fifo_reset/latest

Test location /workspace/coverage/default/234.uart_fifo_reset.2387755754
Short name T958
Test name
Test status
Simulation time 164509115209 ps
CPU time 96.61 seconds
Started Jun 05 04:18:51 PM PDT 24
Finished Jun 05 04:20:29 PM PDT 24
Peak memory 200416 kb
Host smart-4abda4fe-b129-4f6c-af64-be6d3318ca21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387755754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.2387755754
Directory /workspace/234.uart_fifo_reset/latest

Test location /workspace/coverage/default/236.uart_fifo_reset.566890199
Short name T796
Test name
Test status
Simulation time 66184779701 ps
CPU time 37.85 seconds
Started Jun 05 04:18:52 PM PDT 24
Finished Jun 05 04:19:30 PM PDT 24
Peak memory 199988 kb
Host smart-8d6a5f46-6cf3-40fa-83ff-e91ae62b2a2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566890199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.566890199
Directory /workspace/236.uart_fifo_reset/latest

Test location /workspace/coverage/default/237.uart_fifo_reset.1720419123
Short name T723
Test name
Test status
Simulation time 67663025172 ps
CPU time 29.13 seconds
Started Jun 05 04:18:51 PM PDT 24
Finished Jun 05 04:19:21 PM PDT 24
Peak memory 199040 kb
Host smart-72159db8-f9e7-46c6-ae5d-42446c58abe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720419123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.1720419123
Directory /workspace/237.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_alert_test.713982704
Short name T577
Test name
Test status
Simulation time 14070080 ps
CPU time 0.57 seconds
Started Jun 05 04:15:42 PM PDT 24
Finished Jun 05 04:15:43 PM PDT 24
Peak memory 195488 kb
Host smart-48918b9f-8ec1-4fd8-8683-cc9718851259
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713982704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.713982704
Directory /workspace/24.uart_alert_test/latest

Test location /workspace/coverage/default/24.uart_fifo_full.3134640423
Short name T168
Test name
Test status
Simulation time 404395968274 ps
CPU time 250.99 seconds
Started Jun 05 04:15:46 PM PDT 24
Finished Jun 05 04:19:58 PM PDT 24
Peak memory 200376 kb
Host smart-4bbdce76-1f77-44fd-bfee-6c30af659282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134640423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.3134640423
Directory /workspace/24.uart_fifo_full/latest

Test location /workspace/coverage/default/24.uart_fifo_overflow.370405991
Short name T1004
Test name
Test status
Simulation time 143492797603 ps
CPU time 17.56 seconds
Started Jun 05 04:15:49 PM PDT 24
Finished Jun 05 04:16:07 PM PDT 24
Peak memory 200184 kb
Host smart-a86ffa4e-ccc6-47ed-8dd7-762fcdb628da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370405991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.370405991
Directory /workspace/24.uart_fifo_overflow/latest

Test location /workspace/coverage/default/24.uart_fifo_reset.1612186906
Short name T1048
Test name
Test status
Simulation time 89439646169 ps
CPU time 46.82 seconds
Started Jun 05 04:15:37 PM PDT 24
Finished Jun 05 04:16:24 PM PDT 24
Peak memory 200396 kb
Host smart-13eb6625-b83a-4d88-acdf-a1f15a66f501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612186906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.1612186906
Directory /workspace/24.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_intr.3530957962
Short name T913
Test name
Test status
Simulation time 15126381189 ps
CPU time 4.8 seconds
Started Jun 05 04:15:40 PM PDT 24
Finished Jun 05 04:15:46 PM PDT 24
Peak memory 200316 kb
Host smart-9b25360e-9e5d-4bbb-81aa-ac39e2411aca
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530957962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.3530957962
Directory /workspace/24.uart_intr/latest

Test location /workspace/coverage/default/24.uart_long_xfer_wo_dly.4250279588
Short name T1169
Test name
Test status
Simulation time 216804304955 ps
CPU time 252.3 seconds
Started Jun 05 04:15:54 PM PDT 24
Finished Jun 05 04:20:07 PM PDT 24
Peak memory 200440 kb
Host smart-63f4f5d7-3d4d-4eec-a4c4-8e77c443947e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4250279588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.4250279588
Directory /workspace/24.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/24.uart_loopback.3468741080
Short name T427
Test name
Test status
Simulation time 3619038946 ps
CPU time 2.27 seconds
Started Jun 05 04:15:39 PM PDT 24
Finished Jun 05 04:15:43 PM PDT 24
Peak memory 196216 kb
Host smart-7f02bfdb-2436-4914-811d-9d410c4c2c7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468741080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_loopback.3468741080
Directory /workspace/24.uart_loopback/latest

Test location /workspace/coverage/default/24.uart_noise_filter.3630473935
Short name T619
Test name
Test status
Simulation time 128132391886 ps
CPU time 203.36 seconds
Started Jun 05 04:15:42 PM PDT 24
Finished Jun 05 04:19:07 PM PDT 24
Peak memory 215896 kb
Host smart-53da610e-7c67-4c84-9c4c-eb99164c0095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630473935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_noise_filter.3630473935
Directory /workspace/24.uart_noise_filter/latest

Test location /workspace/coverage/default/24.uart_perf.194424215
Short name T554
Test name
Test status
Simulation time 12694623377 ps
CPU time 744.13 seconds
Started Jun 05 04:15:40 PM PDT 24
Finished Jun 05 04:28:05 PM PDT 24
Peak memory 200416 kb
Host smart-5e612262-8c61-4108-b1ae-5359450d6747
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=194424215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.194424215
Directory /workspace/24.uart_perf/latest

Test location /workspace/coverage/default/24.uart_rx_oversample.1870333178
Short name T419
Test name
Test status
Simulation time 5341545825 ps
CPU time 24 seconds
Started Jun 05 04:15:37 PM PDT 24
Finished Jun 05 04:16:02 PM PDT 24
Peak memory 199444 kb
Host smart-2deaa3fa-5075-4f54-99c9-1f48a292583d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1870333178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.1870333178
Directory /workspace/24.uart_rx_oversample/latest

Test location /workspace/coverage/default/24.uart_rx_parity_err.1920292424
Short name T690
Test name
Test status
Simulation time 164780933476 ps
CPU time 117.19 seconds
Started Jun 05 04:15:39 PM PDT 24
Finished Jun 05 04:17:37 PM PDT 24
Peak memory 200388 kb
Host smart-c4ba2ce4-f022-4a67-9e81-321327a02699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920292424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.1920292424
Directory /workspace/24.uart_rx_parity_err/latest

Test location /workspace/coverage/default/24.uart_rx_start_bit_filter.1554331841
Short name T549
Test name
Test status
Simulation time 37506685790 ps
CPU time 59.41 seconds
Started Jun 05 04:15:53 PM PDT 24
Finished Jun 05 04:16:53 PM PDT 24
Peak memory 196200 kb
Host smart-e642f772-ff3f-4f74-9c96-8ec52e594f70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554331841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.1554331841
Directory /workspace/24.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/24.uart_smoke.3284858160
Short name T1097
Test name
Test status
Simulation time 561114466 ps
CPU time 1.99 seconds
Started Jun 05 04:15:48 PM PDT 24
Finished Jun 05 04:15:50 PM PDT 24
Peak memory 200356 kb
Host smart-313ec9a7-7a7e-4e58-827b-85e527fed708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284858160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_smoke.3284858160
Directory /workspace/24.uart_smoke/latest

Test location /workspace/coverage/default/24.uart_stress_all.2971710411
Short name T465
Test name
Test status
Simulation time 1407801552 ps
CPU time 3.64 seconds
Started Jun 05 04:15:54 PM PDT 24
Finished Jun 05 04:15:58 PM PDT 24
Peak memory 200420 kb
Host smart-7d94e216-b6bc-4c99-aa60-3556c4aff22c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971710411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.2971710411
Directory /workspace/24.uart_stress_all/latest

Test location /workspace/coverage/default/24.uart_stress_all_with_rand_reset.3101656821
Short name T778
Test name
Test status
Simulation time 46602037060 ps
CPU time 589.42 seconds
Started Jun 05 04:15:37 PM PDT 24
Finished Jun 05 04:25:28 PM PDT 24
Peak memory 225240 kb
Host smart-31d7a20b-0df1-4f6d-828f-4207119c89c3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101656821 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 24.uart_stress_all_with_rand_reset.3101656821
Directory /workspace/24.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.uart_tx_ovrd.3537754063
Short name T1154
Test name
Test status
Simulation time 191743570 ps
CPU time 0.83 seconds
Started Jun 05 04:15:39 PM PDT 24
Finished Jun 05 04:15:41 PM PDT 24
Peak memory 197500 kb
Host smart-06213f60-5271-4948-9e13-af5b65ecc932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537754063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.3537754063
Directory /workspace/24.uart_tx_ovrd/latest

Test location /workspace/coverage/default/24.uart_tx_rx.2701429641
Short name T869
Test name
Test status
Simulation time 144828672792 ps
CPU time 43.51 seconds
Started Jun 05 04:15:46 PM PDT 24
Finished Jun 05 04:16:30 PM PDT 24
Peak memory 200404 kb
Host smart-6dd4cdaa-0235-4572-978a-de08358f3806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701429641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.2701429641
Directory /workspace/24.uart_tx_rx/latest

Test location /workspace/coverage/default/241.uart_fifo_reset.2142767097
Short name T201
Test name
Test status
Simulation time 31443378711 ps
CPU time 11.26 seconds
Started Jun 05 04:18:54 PM PDT 24
Finished Jun 05 04:19:06 PM PDT 24
Peak memory 200324 kb
Host smart-b7e80385-0d45-426b-8b27-8f4c18736fbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142767097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.2142767097
Directory /workspace/241.uart_fifo_reset/latest

Test location /workspace/coverage/default/242.uart_fifo_reset.2867472465
Short name T182
Test name
Test status
Simulation time 89483055681 ps
CPU time 165.38 seconds
Started Jun 05 04:18:54 PM PDT 24
Finished Jun 05 04:21:40 PM PDT 24
Peak memory 200420 kb
Host smart-53ae4089-e1c6-4f38-8bfd-7e920e14e2e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867472465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.2867472465
Directory /workspace/242.uart_fifo_reset/latest

Test location /workspace/coverage/default/243.uart_fifo_reset.3889512296
Short name T247
Test name
Test status
Simulation time 23474854354 ps
CPU time 40.6 seconds
Started Jun 05 04:18:52 PM PDT 24
Finished Jun 05 04:19:33 PM PDT 24
Peak memory 200416 kb
Host smart-46b0f597-8a30-47fb-abe2-d3b4c7a3f868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889512296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.3889512296
Directory /workspace/243.uart_fifo_reset/latest

Test location /workspace/coverage/default/244.uart_fifo_reset.1574496852
Short name T241
Test name
Test status
Simulation time 23235144651 ps
CPU time 9.72 seconds
Started Jun 05 04:18:50 PM PDT 24
Finished Jun 05 04:19:01 PM PDT 24
Peak memory 200392 kb
Host smart-27ac4107-6c14-4ced-95c0-2659621dc686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574496852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.1574496852
Directory /workspace/244.uart_fifo_reset/latest

Test location /workspace/coverage/default/245.uart_fifo_reset.1262554939
Short name T234
Test name
Test status
Simulation time 79735422375 ps
CPU time 55.92 seconds
Started Jun 05 04:18:52 PM PDT 24
Finished Jun 05 04:19:48 PM PDT 24
Peak memory 200312 kb
Host smart-224c6e96-5098-4011-b82a-e5a2c76daaee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262554939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.1262554939
Directory /workspace/245.uart_fifo_reset/latest

Test location /workspace/coverage/default/246.uart_fifo_reset.4173540491
Short name T801
Test name
Test status
Simulation time 116177591631 ps
CPU time 103.93 seconds
Started Jun 05 04:18:52 PM PDT 24
Finished Jun 05 04:20:37 PM PDT 24
Peak memory 200408 kb
Host smart-17ae8714-d72f-40c0-beda-a7e17bb85e73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173540491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.4173540491
Directory /workspace/246.uart_fifo_reset/latest

Test location /workspace/coverage/default/248.uart_fifo_reset.3837106174
Short name T878
Test name
Test status
Simulation time 33127217394 ps
CPU time 31.06 seconds
Started Jun 05 04:18:51 PM PDT 24
Finished Jun 05 04:19:23 PM PDT 24
Peak memory 200412 kb
Host smart-58771514-8a37-49fb-91e0-d41c56bcf519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837106174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.3837106174
Directory /workspace/248.uart_fifo_reset/latest

Test location /workspace/coverage/default/249.uart_fifo_reset.2973878082
Short name T905
Test name
Test status
Simulation time 10932890987 ps
CPU time 13.09 seconds
Started Jun 05 04:18:51 PM PDT 24
Finished Jun 05 04:19:05 PM PDT 24
Peak memory 200276 kb
Host smart-94e89aa2-c347-41b1-bccd-f14f559cff5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973878082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.2973878082
Directory /workspace/249.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_alert_test.2513215190
Short name T721
Test name
Test status
Simulation time 13335633 ps
CPU time 0.57 seconds
Started Jun 05 04:15:49 PM PDT 24
Finished Jun 05 04:15:50 PM PDT 24
Peak memory 195808 kb
Host smart-2d32faf5-b126-41d1-970e-a5d3e0869141
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513215190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.2513215190
Directory /workspace/25.uart_alert_test/latest

Test location /workspace/coverage/default/25.uart_fifo_full.726222567
Short name T848
Test name
Test status
Simulation time 38380618633 ps
CPU time 18.75 seconds
Started Jun 05 04:15:47 PM PDT 24
Finished Jun 05 04:16:06 PM PDT 24
Peak memory 200440 kb
Host smart-229eb7a6-a546-4e7b-a302-334187093e6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726222567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.726222567
Directory /workspace/25.uart_fifo_full/latest

Test location /workspace/coverage/default/25.uart_fifo_overflow.4265209485
Short name T785
Test name
Test status
Simulation time 71617374390 ps
CPU time 110.81 seconds
Started Jun 05 04:15:49 PM PDT 24
Finished Jun 05 04:17:41 PM PDT 24
Peak memory 200392 kb
Host smart-59fd9324-79c1-44b4-941e-4a3ba569134d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265209485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.4265209485
Directory /workspace/25.uart_fifo_overflow/latest

Test location /workspace/coverage/default/25.uart_intr.4280322369
Short name T125
Test name
Test status
Simulation time 54879189466 ps
CPU time 95.53 seconds
Started Jun 05 04:15:38 PM PDT 24
Finished Jun 05 04:17:14 PM PDT 24
Peak memory 199492 kb
Host smart-d7a449ad-e1ee-4432-ac8d-e14e0f67300b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280322369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.4280322369
Directory /workspace/25.uart_intr/latest

Test location /workspace/coverage/default/25.uart_long_xfer_wo_dly.2748677063
Short name T260
Test name
Test status
Simulation time 163377228627 ps
CPU time 1099.66 seconds
Started Jun 05 04:15:38 PM PDT 24
Finished Jun 05 04:33:58 PM PDT 24
Peak memory 200380 kb
Host smart-e79b30d3-82b2-4260-834d-5c89d8a2c6fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2748677063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.2748677063
Directory /workspace/25.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/25.uart_loopback.1854723219
Short name T712
Test name
Test status
Simulation time 7967740184 ps
CPU time 4.19 seconds
Started Jun 05 04:15:42 PM PDT 24
Finished Jun 05 04:15:46 PM PDT 24
Peak memory 200016 kb
Host smart-16dd02f2-e7e1-47db-ad61-6bfa44c2565e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854723219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_loopback.1854723219
Directory /workspace/25.uart_loopback/latest

Test location /workspace/coverage/default/25.uart_noise_filter.2391720210
Short name T361
Test name
Test status
Simulation time 35557880270 ps
CPU time 28.14 seconds
Started Jun 05 04:15:40 PM PDT 24
Finished Jun 05 04:16:09 PM PDT 24
Peak memory 200596 kb
Host smart-404cd2c5-bcc4-4a0f-9d4a-4229aa6b4ba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391720210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_noise_filter.2391720210
Directory /workspace/25.uart_noise_filter/latest

Test location /workspace/coverage/default/25.uart_perf.89097013
Short name T591
Test name
Test status
Simulation time 24593532518 ps
CPU time 655.16 seconds
Started Jun 05 04:15:37 PM PDT 24
Finished Jun 05 04:26:33 PM PDT 24
Peak memory 200432 kb
Host smart-16d2967b-af31-480c-a69b-6786dca4abc9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=89097013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.89097013
Directory /workspace/25.uart_perf/latest

Test location /workspace/coverage/default/25.uart_rx_oversample.1256211213
Short name T483
Test name
Test status
Simulation time 4542777514 ps
CPU time 6.24 seconds
Started Jun 05 04:15:46 PM PDT 24
Finished Jun 05 04:15:53 PM PDT 24
Peak memory 199816 kb
Host smart-b5042748-a9d0-43d3-9c81-1aa63b5f07ed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1256211213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.1256211213
Directory /workspace/25.uart_rx_oversample/latest

Test location /workspace/coverage/default/25.uart_rx_parity_err.771766326
Short name T105
Test name
Test status
Simulation time 128748115260 ps
CPU time 191.88 seconds
Started Jun 05 04:15:43 PM PDT 24
Finished Jun 05 04:18:55 PM PDT 24
Peak memory 200284 kb
Host smart-aa1ec5d1-0551-4c51-b6bc-b83c81779cae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771766326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.771766326
Directory /workspace/25.uart_rx_parity_err/latest

Test location /workspace/coverage/default/25.uart_rx_start_bit_filter.826436982
Short name T830
Test name
Test status
Simulation time 66009042916 ps
CPU time 10.67 seconds
Started Jun 05 04:15:38 PM PDT 24
Finished Jun 05 04:15:49 PM PDT 24
Peak memory 196128 kb
Host smart-59963bba-e11c-49b7-b348-909a07460b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826436982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.826436982
Directory /workspace/25.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/25.uart_smoke.3527512470
Short name T490
Test name
Test status
Simulation time 894061086 ps
CPU time 2.33 seconds
Started Jun 05 04:15:57 PM PDT 24
Finished Jun 05 04:16:00 PM PDT 24
Peak memory 199148 kb
Host smart-7cc3a622-d719-4a88-8a62-95c2d34cc882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527512470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_smoke.3527512470
Directory /workspace/25.uart_smoke/latest

Test location /workspace/coverage/default/25.uart_stress_all.3304116522
Short name T610
Test name
Test status
Simulation time 245229562045 ps
CPU time 1454.05 seconds
Started Jun 05 04:15:48 PM PDT 24
Finished Jun 05 04:40:03 PM PDT 24
Peak memory 200472 kb
Host smart-bd27edac-bc18-422e-aeb2-12fb0fbf3436
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304116522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.3304116522
Directory /workspace/25.uart_stress_all/latest

Test location /workspace/coverage/default/25.uart_stress_all_with_rand_reset.3117518712
Short name T56
Test name
Test status
Simulation time 41292913860 ps
CPU time 453.48 seconds
Started Jun 05 04:15:41 PM PDT 24
Finished Jun 05 04:23:15 PM PDT 24
Peak memory 208624 kb
Host smart-ae1635bd-9138-48bc-9b1e-00d6526f3931
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117518712 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 25.uart_stress_all_with_rand_reset.3117518712
Directory /workspace/25.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.uart_tx_ovrd.2245478590
Short name T367
Test name
Test status
Simulation time 1390837991 ps
CPU time 3.13 seconds
Started Jun 05 04:15:48 PM PDT 24
Finished Jun 05 04:15:51 PM PDT 24
Peak memory 199056 kb
Host smart-74409f32-53c2-4a7e-be30-817644418dc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245478590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.2245478590
Directory /workspace/25.uart_tx_ovrd/latest

Test location /workspace/coverage/default/25.uart_tx_rx.2298130785
Short name T1153
Test name
Test status
Simulation time 74398741082 ps
CPU time 19.59 seconds
Started Jun 05 04:15:39 PM PDT 24
Finished Jun 05 04:15:59 PM PDT 24
Peak memory 200448 kb
Host smart-c1724517-14d1-4b0c-b403-8bd202c0975c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298130785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.2298130785
Directory /workspace/25.uart_tx_rx/latest

Test location /workspace/coverage/default/250.uart_fifo_reset.980222804
Short name T860
Test name
Test status
Simulation time 146103424673 ps
CPU time 68.06 seconds
Started Jun 05 04:18:52 PM PDT 24
Finished Jun 05 04:20:01 PM PDT 24
Peak memory 200508 kb
Host smart-0e4cd2c0-61fb-4857-ba24-98a09ce6f113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980222804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.980222804
Directory /workspace/250.uart_fifo_reset/latest

Test location /workspace/coverage/default/251.uart_fifo_reset.3552827213
Short name T1042
Test name
Test status
Simulation time 129857979233 ps
CPU time 70.48 seconds
Started Jun 05 04:18:59 PM PDT 24
Finished Jun 05 04:20:11 PM PDT 24
Peak memory 200380 kb
Host smart-aefb2d81-38b3-4c24-b145-42d06db75a4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552827213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.3552827213
Directory /workspace/251.uart_fifo_reset/latest

Test location /workspace/coverage/default/252.uart_fifo_reset.1783494857
Short name T150
Test name
Test status
Simulation time 14452340994 ps
CPU time 18.65 seconds
Started Jun 05 04:19:01 PM PDT 24
Finished Jun 05 04:19:20 PM PDT 24
Peak memory 200384 kb
Host smart-1c122b8f-974b-4df5-b7d2-24b2e644e323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783494857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.1783494857
Directory /workspace/252.uart_fifo_reset/latest

Test location /workspace/coverage/default/253.uart_fifo_reset.1927867972
Short name T175
Test name
Test status
Simulation time 51561511750 ps
CPU time 25.16 seconds
Started Jun 05 04:18:59 PM PDT 24
Finished Jun 05 04:19:25 PM PDT 24
Peak memory 200412 kb
Host smart-3c1723de-9706-46bd-a0a4-995ec4c822d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927867972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.1927867972
Directory /workspace/253.uart_fifo_reset/latest

Test location /workspace/coverage/default/254.uart_fifo_reset.2164593544
Short name T336
Test name
Test status
Simulation time 39980421421 ps
CPU time 25.66 seconds
Started Jun 05 04:19:00 PM PDT 24
Finished Jun 05 04:19:26 PM PDT 24
Peak memory 200392 kb
Host smart-adb76215-b8da-4029-887e-de66ec2b703a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164593544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.2164593544
Directory /workspace/254.uart_fifo_reset/latest

Test location /workspace/coverage/default/255.uart_fifo_reset.1883482423
Short name T155
Test name
Test status
Simulation time 15699964372 ps
CPU time 27.23 seconds
Started Jun 05 04:19:01 PM PDT 24
Finished Jun 05 04:19:29 PM PDT 24
Peak memory 200404 kb
Host smart-00a279c7-629b-40f1-9043-aa96bed26c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883482423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.1883482423
Directory /workspace/255.uart_fifo_reset/latest

Test location /workspace/coverage/default/256.uart_fifo_reset.5639811
Short name T839
Test name
Test status
Simulation time 42849982956 ps
CPU time 10.07 seconds
Started Jun 05 04:19:00 PM PDT 24
Finished Jun 05 04:19:11 PM PDT 24
Peak memory 200520 kb
Host smart-918629a5-d119-4184-ae26-ef8c4bc44305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5639811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.5639811
Directory /workspace/256.uart_fifo_reset/latest

Test location /workspace/coverage/default/257.uart_fifo_reset.1471126010
Short name T218
Test name
Test status
Simulation time 119205954136 ps
CPU time 59.68 seconds
Started Jun 05 04:19:02 PM PDT 24
Finished Jun 05 04:20:02 PM PDT 24
Peak memory 200372 kb
Host smart-5f70fd83-3bc5-4365-a701-cc2b2af4b326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471126010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.1471126010
Directory /workspace/257.uart_fifo_reset/latest

Test location /workspace/coverage/default/258.uart_fifo_reset.3512876018
Short name T458
Test name
Test status
Simulation time 17930527357 ps
CPU time 16.34 seconds
Started Jun 05 04:19:01 PM PDT 24
Finished Jun 05 04:19:17 PM PDT 24
Peak memory 200456 kb
Host smart-b6f76e34-e612-4026-bd64-44f487678f9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512876018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.3512876018
Directory /workspace/258.uart_fifo_reset/latest

Test location /workspace/coverage/default/259.uart_fifo_reset.2931143475
Short name T840
Test name
Test status
Simulation time 7158623138 ps
CPU time 17.04 seconds
Started Jun 05 04:19:01 PM PDT 24
Finished Jun 05 04:19:18 PM PDT 24
Peak memory 200444 kb
Host smart-386f41ff-0364-4601-ab2a-887d1b17f3f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931143475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.2931143475
Directory /workspace/259.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_alert_test.468613568
Short name T985
Test name
Test status
Simulation time 11904720 ps
CPU time 0.56 seconds
Started Jun 05 04:15:53 PM PDT 24
Finished Jun 05 04:15:55 PM PDT 24
Peak memory 195808 kb
Host smart-f0067c62-0c81-4b64-a9ec-5b49a470b045
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468613568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.468613568
Directory /workspace/26.uart_alert_test/latest

Test location /workspace/coverage/default/26.uart_fifo_full.3060966211
Short name T442
Test name
Test status
Simulation time 66893617860 ps
CPU time 108.57 seconds
Started Jun 05 04:15:48 PM PDT 24
Finished Jun 05 04:17:38 PM PDT 24
Peak memory 200436 kb
Host smart-2f8cec1d-5b7b-42a2-b443-fad0ac898a3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060966211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.3060966211
Directory /workspace/26.uart_fifo_full/latest

Test location /workspace/coverage/default/26.uart_fifo_overflow.850564728
Short name T1060
Test name
Test status
Simulation time 19831784919 ps
CPU time 18.21 seconds
Started Jun 05 04:15:50 PM PDT 24
Finished Jun 05 04:16:09 PM PDT 24
Peak memory 200416 kb
Host smart-04aac305-70c6-44e2-a8d1-4971e5f3424a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850564728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.850564728
Directory /workspace/26.uart_fifo_overflow/latest

Test location /workspace/coverage/default/26.uart_fifo_reset.2086307990
Short name T156
Test name
Test status
Simulation time 225250351960 ps
CPU time 42.59 seconds
Started Jun 05 04:15:49 PM PDT 24
Finished Jun 05 04:16:33 PM PDT 24
Peak memory 200380 kb
Host smart-0e69678e-3ab9-47f2-a951-065f7528ff5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086307990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.2086307990
Directory /workspace/26.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_intr.1732832408
Short name T813
Test name
Test status
Simulation time 42160106167 ps
CPU time 52.44 seconds
Started Jun 05 04:15:49 PM PDT 24
Finished Jun 05 04:16:42 PM PDT 24
Peak memory 200364 kb
Host smart-212755dc-37c0-41eb-91e2-6555864ba5a4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732832408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.1732832408
Directory /workspace/26.uart_intr/latest

Test location /workspace/coverage/default/26.uart_long_xfer_wo_dly.1966064858
Short name T515
Test name
Test status
Simulation time 99380331524 ps
CPU time 1041.1 seconds
Started Jun 05 04:15:55 PM PDT 24
Finished Jun 05 04:33:17 PM PDT 24
Peak memory 200580 kb
Host smart-79ce50c5-67a9-482d-a52d-8d9b3cf24a28
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1966064858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.1966064858
Directory /workspace/26.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/26.uart_loopback.3275360462
Short name T937
Test name
Test status
Simulation time 10644986747 ps
CPU time 25.75 seconds
Started Jun 05 04:15:50 PM PDT 24
Finished Jun 05 04:16:16 PM PDT 24
Peak memory 198916 kb
Host smart-3eff6255-b990-4ae7-9514-d2851362d805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275360462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_loopback.3275360462
Directory /workspace/26.uart_loopback/latest

Test location /workspace/coverage/default/26.uart_noise_filter.658942782
Short name T595
Test name
Test status
Simulation time 110390378021 ps
CPU time 336.01 seconds
Started Jun 05 04:15:50 PM PDT 24
Finished Jun 05 04:21:27 PM PDT 24
Peak memory 200688 kb
Host smart-f7e782e5-937a-4d31-addc-a15aaffa781b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658942782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_noise_filter.658942782
Directory /workspace/26.uart_noise_filter/latest

Test location /workspace/coverage/default/26.uart_perf.3178793869
Short name T621
Test name
Test status
Simulation time 7974157378 ps
CPU time 300.82 seconds
Started Jun 05 04:15:47 PM PDT 24
Finished Jun 05 04:20:49 PM PDT 24
Peak memory 200368 kb
Host smart-a2bb6917-644a-419b-875d-3e5677fe8cba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3178793869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.3178793869
Directory /workspace/26.uart_perf/latest

Test location /workspace/coverage/default/26.uart_rx_oversample.522498371
Short name T1173
Test name
Test status
Simulation time 3869440693 ps
CPU time 15.25 seconds
Started Jun 05 04:15:49 PM PDT 24
Finished Jun 05 04:16:05 PM PDT 24
Peak memory 198480 kb
Host smart-6d7f555d-b49e-4b17-a978-868fcb259b90
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=522498371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.522498371
Directory /workspace/26.uart_rx_oversample/latest

Test location /workspace/coverage/default/26.uart_rx_parity_err.3133073462
Short name T1075
Test name
Test status
Simulation time 22827939223 ps
CPU time 9.55 seconds
Started Jun 05 04:15:51 PM PDT 24
Finished Jun 05 04:16:01 PM PDT 24
Peak memory 200100 kb
Host smart-ff49d4c7-3c77-444c-a82b-ed77dbab1705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133073462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.3133073462
Directory /workspace/26.uart_rx_parity_err/latest

Test location /workspace/coverage/default/26.uart_rx_start_bit_filter.719413308
Short name T1055
Test name
Test status
Simulation time 2436111376 ps
CPU time 4.04 seconds
Started Jun 05 04:15:49 PM PDT 24
Finished Jun 05 04:15:54 PM PDT 24
Peak memory 196148 kb
Host smart-f8b96606-1ee9-4002-86f9-5b574ea5a444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719413308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.719413308
Directory /workspace/26.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/26.uart_smoke.2636156171
Short name T1037
Test name
Test status
Simulation time 434835747 ps
CPU time 1.47 seconds
Started Jun 05 04:15:48 PM PDT 24
Finished Jun 05 04:15:50 PM PDT 24
Peak memory 199076 kb
Host smart-285ed68b-3172-4a50-be11-081f8fb833c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636156171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_smoke.2636156171
Directory /workspace/26.uart_smoke/latest

Test location /workspace/coverage/default/26.uart_stress_all_with_rand_reset.2002923521
Short name T27
Test name
Test status
Simulation time 34739510537 ps
CPU time 419.88 seconds
Started Jun 05 04:15:54 PM PDT 24
Finished Jun 05 04:22:54 PM PDT 24
Peak memory 216848 kb
Host smart-ef9fc621-7858-4c92-b865-c4c986362232
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002923521 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 26.uart_stress_all_with_rand_reset.2002923521
Directory /workspace/26.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.uart_tx_ovrd.2943435927
Short name T957
Test name
Test status
Simulation time 1078672370 ps
CPU time 3.83 seconds
Started Jun 05 04:15:49 PM PDT 24
Finished Jun 05 04:15:54 PM PDT 24
Peak memory 198860 kb
Host smart-183dd78c-3879-4b14-a50d-bd7f6ce9252a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943435927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.2943435927
Directory /workspace/26.uart_tx_ovrd/latest

Test location /workspace/coverage/default/26.uart_tx_rx.2854690220
Short name T1134
Test name
Test status
Simulation time 36799896278 ps
CPU time 18.61 seconds
Started Jun 05 04:15:47 PM PDT 24
Finished Jun 05 04:16:06 PM PDT 24
Peak memory 200388 kb
Host smart-aa44b0d4-cc4a-4ca3-9528-8db963666583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854690220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.2854690220
Directory /workspace/26.uart_tx_rx/latest

Test location /workspace/coverage/default/260.uart_fifo_reset.496174
Short name T659
Test name
Test status
Simulation time 19341982202 ps
CPU time 9.96 seconds
Started Jun 05 04:19:02 PM PDT 24
Finished Jun 05 04:19:12 PM PDT 24
Peak memory 200376 kb
Host smart-f9aef986-12b5-4b27-b80d-787c96bdd046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.496174
Directory /workspace/260.uart_fifo_reset/latest

Test location /workspace/coverage/default/261.uart_fifo_reset.920447636
Short name T936
Test name
Test status
Simulation time 32402993768 ps
CPU time 29.04 seconds
Started Jun 05 04:19:00 PM PDT 24
Finished Jun 05 04:19:29 PM PDT 24
Peak memory 200388 kb
Host smart-685d9416-0fbe-469d-b43f-6c6dd2443dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920447636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.920447636
Directory /workspace/261.uart_fifo_reset/latest

Test location /workspace/coverage/default/262.uart_fifo_reset.536962701
Short name T924
Test name
Test status
Simulation time 11821004586 ps
CPU time 22.27 seconds
Started Jun 05 04:18:59 PM PDT 24
Finished Jun 05 04:19:22 PM PDT 24
Peak memory 200404 kb
Host smart-9f125df3-8c79-468a-85f0-42f8a33bc561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536962701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.536962701
Directory /workspace/262.uart_fifo_reset/latest

Test location /workspace/coverage/default/263.uart_fifo_reset.3724136495
Short name T664
Test name
Test status
Simulation time 47216352122 ps
CPU time 32.79 seconds
Started Jun 05 04:19:03 PM PDT 24
Finished Jun 05 04:19:37 PM PDT 24
Peak memory 200356 kb
Host smart-352cfbee-ee26-4c78-9f08-07b7c8effb39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724136495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.3724136495
Directory /workspace/263.uart_fifo_reset/latest

Test location /workspace/coverage/default/264.uart_fifo_reset.3265906191
Short name T1151
Test name
Test status
Simulation time 73003075008 ps
CPU time 32.52 seconds
Started Jun 05 04:19:01 PM PDT 24
Finished Jun 05 04:19:35 PM PDT 24
Peak memory 200404 kb
Host smart-90c5c1bb-5a4a-4b58-a4b1-afa118b5dcf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265906191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.3265906191
Directory /workspace/264.uart_fifo_reset/latest

Test location /workspace/coverage/default/265.uart_fifo_reset.1788858426
Short name T457
Test name
Test status
Simulation time 112155551369 ps
CPU time 48.84 seconds
Started Jun 05 04:19:01 PM PDT 24
Finished Jun 05 04:19:51 PM PDT 24
Peak memory 200188 kb
Host smart-f8222839-3d55-4236-99d2-364c55c34b3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788858426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.1788858426
Directory /workspace/265.uart_fifo_reset/latest

Test location /workspace/coverage/default/266.uart_fifo_reset.4248252839
Short name T203
Test name
Test status
Simulation time 69932982680 ps
CPU time 33.59 seconds
Started Jun 05 04:19:00 PM PDT 24
Finished Jun 05 04:19:34 PM PDT 24
Peak memory 200408 kb
Host smart-509212b9-091b-4600-908f-10075e60e7d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248252839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.4248252839
Directory /workspace/266.uart_fifo_reset/latest

Test location /workspace/coverage/default/267.uart_fifo_reset.786187892
Short name T443
Test name
Test status
Simulation time 18066512359 ps
CPU time 36.27 seconds
Started Jun 05 04:19:00 PM PDT 24
Finished Jun 05 04:19:37 PM PDT 24
Peak memory 200468 kb
Host smart-da230075-a6a3-4e98-92a0-21410a1f40f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786187892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.786187892
Directory /workspace/267.uart_fifo_reset/latest

Test location /workspace/coverage/default/268.uart_fifo_reset.1299648998
Short name T276
Test name
Test status
Simulation time 220340069984 ps
CPU time 172.48 seconds
Started Jun 05 04:19:01 PM PDT 24
Finished Jun 05 04:21:54 PM PDT 24
Peak memory 200356 kb
Host smart-9ad362cd-ec0f-4dd8-bd25-695862d68ae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299648998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.1299648998
Directory /workspace/268.uart_fifo_reset/latest

Test location /workspace/coverage/default/269.uart_fifo_reset.1669444154
Short name T228
Test name
Test status
Simulation time 51290728536 ps
CPU time 89.21 seconds
Started Jun 05 04:18:59 PM PDT 24
Finished Jun 05 04:20:29 PM PDT 24
Peak memory 200368 kb
Host smart-1731868c-73cb-4355-8df6-dedca0146d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669444154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.1669444154
Directory /workspace/269.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_alert_test.77804688
Short name T946
Test name
Test status
Simulation time 17980660 ps
CPU time 0.56 seconds
Started Jun 05 04:16:01 PM PDT 24
Finished Jun 05 04:16:03 PM PDT 24
Peak memory 195796 kb
Host smart-14c5014e-aa3b-49ed-a681-456bbeebb250
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77804688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.77804688
Directory /workspace/27.uart_alert_test/latest

Test location /workspace/coverage/default/27.uart_fifo_full.3082560674
Short name T434
Test name
Test status
Simulation time 112711918505 ps
CPU time 185.07 seconds
Started Jun 05 04:15:50 PM PDT 24
Finished Jun 05 04:18:56 PM PDT 24
Peak memory 200416 kb
Host smart-7196efd5-27ca-4a6b-aa59-01fe4cd016ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082560674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.3082560674
Directory /workspace/27.uart_fifo_full/latest

Test location /workspace/coverage/default/27.uart_fifo_overflow.774103401
Short name T855
Test name
Test status
Simulation time 104350071526 ps
CPU time 93.66 seconds
Started Jun 05 04:15:48 PM PDT 24
Finished Jun 05 04:17:22 PM PDT 24
Peak memory 200392 kb
Host smart-3b1d6576-43ef-49ff-b054-27da1844b9f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774103401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.774103401
Directory /workspace/27.uart_fifo_overflow/latest

Test location /workspace/coverage/default/27.uart_fifo_reset.732352118
Short name T146
Test name
Test status
Simulation time 74629166438 ps
CPU time 204.37 seconds
Started Jun 05 04:15:47 PM PDT 24
Finished Jun 05 04:19:13 PM PDT 24
Peak memory 200464 kb
Host smart-300f8bf4-af97-499c-b9b6-3173e9fe9351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732352118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.732352118
Directory /workspace/27.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_intr.2252582640
Short name T393
Test name
Test status
Simulation time 27478640993 ps
CPU time 11.05 seconds
Started Jun 05 04:15:49 PM PDT 24
Finished Jun 05 04:16:01 PM PDT 24
Peak memory 200260 kb
Host smart-58fc0515-e500-4e52-a3eb-f895948b6a83
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252582640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.2252582640
Directory /workspace/27.uart_intr/latest

Test location /workspace/coverage/default/27.uart_loopback.1810068058
Short name T761
Test name
Test status
Simulation time 4343710401 ps
CPU time 3.02 seconds
Started Jun 05 04:15:59 PM PDT 24
Finished Jun 05 04:16:03 PM PDT 24
Peak memory 198348 kb
Host smart-3056c06e-fb90-4f5a-a875-4a4b0d30b930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810068058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_loopback.1810068058
Directory /workspace/27.uart_loopback/latest

Test location /workspace/coverage/default/27.uart_noise_filter.2464317204
Short name T273
Test name
Test status
Simulation time 148610547312 ps
CPU time 59.78 seconds
Started Jun 05 04:15:56 PM PDT 24
Finished Jun 05 04:16:56 PM PDT 24
Peak memory 198964 kb
Host smart-f3e758d5-b974-48b8-be4d-cc38c13b556a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464317204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_noise_filter.2464317204
Directory /workspace/27.uart_noise_filter/latest

Test location /workspace/coverage/default/27.uart_perf.3827028562
Short name T478
Test name
Test status
Simulation time 16635875852 ps
CPU time 187.54 seconds
Started Jun 05 04:15:58 PM PDT 24
Finished Jun 05 04:19:07 PM PDT 24
Peak memory 200556 kb
Host smart-49af9f21-1382-4146-86c6-df6f6e1d103c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3827028562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.3827028562
Directory /workspace/27.uart_perf/latest

Test location /workspace/coverage/default/27.uart_rx_oversample.562846722
Short name T413
Test name
Test status
Simulation time 7258866445 ps
CPU time 40.6 seconds
Started Jun 05 04:15:50 PM PDT 24
Finished Jun 05 04:16:31 PM PDT 24
Peak memory 200336 kb
Host smart-8f1ea6f3-5fe3-497a-a321-4122031084b5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=562846722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.562846722
Directory /workspace/27.uart_rx_oversample/latest

Test location /workspace/coverage/default/27.uart_rx_parity_err.2791363029
Short name T569
Test name
Test status
Simulation time 97073642188 ps
CPU time 144.64 seconds
Started Jun 05 04:15:56 PM PDT 24
Finished Jun 05 04:18:21 PM PDT 24
Peak memory 200252 kb
Host smart-c184b2a2-9300-4267-9fa2-6b775c863c1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791363029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.2791363029
Directory /workspace/27.uart_rx_parity_err/latest

Test location /workspace/coverage/default/27.uart_rx_start_bit_filter.2885779415
Short name T439
Test name
Test status
Simulation time 2069984606 ps
CPU time 3.92 seconds
Started Jun 05 04:15:56 PM PDT 24
Finished Jun 05 04:16:00 PM PDT 24
Peak memory 196072 kb
Host smart-16c8d4b6-c1ef-40df-b416-1ce8865ac850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885779415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.2885779415
Directory /workspace/27.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/27.uart_smoke.3105786067
Short name T485
Test name
Test status
Simulation time 6031671452 ps
CPU time 22.3 seconds
Started Jun 05 04:15:55 PM PDT 24
Finished Jun 05 04:16:18 PM PDT 24
Peak memory 199648 kb
Host smart-606cc955-c9e4-490b-9f0c-2a049fb7f9c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105786067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_smoke.3105786067
Directory /workspace/27.uart_smoke/latest

Test location /workspace/coverage/default/27.uart_stress_all.1023499580
Short name T555
Test name
Test status
Simulation time 636888514294 ps
CPU time 347.38 seconds
Started Jun 05 04:15:57 PM PDT 24
Finished Jun 05 04:21:45 PM PDT 24
Peak memory 200400 kb
Host smart-ee692218-10f7-48c6-ab8e-23ab2ce1f77d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023499580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.1023499580
Directory /workspace/27.uart_stress_all/latest

Test location /workspace/coverage/default/27.uart_stress_all_with_rand_reset.2945601074
Short name T459
Test name
Test status
Simulation time 151382307308 ps
CPU time 366.52 seconds
Started Jun 05 04:16:02 PM PDT 24
Finished Jun 05 04:22:10 PM PDT 24
Peak memory 215588 kb
Host smart-0c4dece8-d0f1-4db9-8bc2-450659dee280
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945601074 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 27.uart_stress_all_with_rand_reset.2945601074
Directory /workspace/27.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.uart_tx_ovrd.2924999477
Short name T885
Test name
Test status
Simulation time 1025281798 ps
CPU time 3.01 seconds
Started Jun 05 04:15:59 PM PDT 24
Finished Jun 05 04:16:04 PM PDT 24
Peak memory 199804 kb
Host smart-a94575e6-99b1-4c20-8651-ed4c29c1a59e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924999477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.2924999477
Directory /workspace/27.uart_tx_ovrd/latest

Test location /workspace/coverage/default/27.uart_tx_rx.1813281442
Short name T705
Test name
Test status
Simulation time 65444113993 ps
CPU time 29.38 seconds
Started Jun 05 04:15:51 PM PDT 24
Finished Jun 05 04:16:21 PM PDT 24
Peak memory 200408 kb
Host smart-9f45efc6-4e8a-4426-9c84-980e17ecedf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813281442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.1813281442
Directory /workspace/27.uart_tx_rx/latest

Test location /workspace/coverage/default/270.uart_fifo_reset.637942043
Short name T1105
Test name
Test status
Simulation time 23074705352 ps
CPU time 11.64 seconds
Started Jun 05 04:19:09 PM PDT 24
Finished Jun 05 04:19:22 PM PDT 24
Peak memory 200396 kb
Host smart-56875f0e-beac-426b-af71-fa3bf5fa63d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637942043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.637942043
Directory /workspace/270.uart_fifo_reset/latest

Test location /workspace/coverage/default/271.uart_fifo_reset.4263614393
Short name T232
Test name
Test status
Simulation time 61529358092 ps
CPU time 8.14 seconds
Started Jun 05 04:19:10 PM PDT 24
Finished Jun 05 04:19:19 PM PDT 24
Peak memory 199192 kb
Host smart-cb536a32-1b70-4db6-a704-1e10b32caad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263614393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.4263614393
Directory /workspace/271.uart_fifo_reset/latest

Test location /workspace/coverage/default/274.uart_fifo_reset.2096383116
Short name T334
Test name
Test status
Simulation time 120790825878 ps
CPU time 138.57 seconds
Started Jun 05 04:19:10 PM PDT 24
Finished Jun 05 04:21:29 PM PDT 24
Peak memory 200380 kb
Host smart-15ae7e54-fe1b-45ed-b28d-08b6d1ca1ce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096383116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.2096383116
Directory /workspace/274.uart_fifo_reset/latest

Test location /workspace/coverage/default/275.uart_fifo_reset.3564252806
Short name T1015
Test name
Test status
Simulation time 25095892129 ps
CPU time 49.73 seconds
Started Jun 05 04:19:09 PM PDT 24
Finished Jun 05 04:20:00 PM PDT 24
Peak memory 200412 kb
Host smart-60b37bf2-cf39-4eb3-86e5-2b72cc2fa942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564252806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.3564252806
Directory /workspace/275.uart_fifo_reset/latest

Test location /workspace/coverage/default/276.uart_fifo_reset.2385971684
Short name T513
Test name
Test status
Simulation time 10025620917 ps
CPU time 16.08 seconds
Started Jun 05 04:19:11 PM PDT 24
Finished Jun 05 04:19:28 PM PDT 24
Peak memory 199072 kb
Host smart-5f447745-c187-4dfc-a041-4c825a808cf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385971684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.2385971684
Directory /workspace/276.uart_fifo_reset/latest

Test location /workspace/coverage/default/277.uart_fifo_reset.1156138297
Short name T968
Test name
Test status
Simulation time 106432134399 ps
CPU time 161.63 seconds
Started Jun 05 04:19:19 PM PDT 24
Finished Jun 05 04:22:02 PM PDT 24
Peak memory 200404 kb
Host smart-b2c7e06f-053b-460a-9a95-dc76634fe2eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156138297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.1156138297
Directory /workspace/277.uart_fifo_reset/latest

Test location /workspace/coverage/default/278.uart_fifo_reset.1857337034
Short name T302
Test name
Test status
Simulation time 120802071355 ps
CPU time 55.52 seconds
Started Jun 05 04:19:10 PM PDT 24
Finished Jun 05 04:20:07 PM PDT 24
Peak memory 200288 kb
Host smart-8f730f79-6be2-46ed-8ed3-0db980e14297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857337034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.1857337034
Directory /workspace/278.uart_fifo_reset/latest

Test location /workspace/coverage/default/279.uart_fifo_reset.1341212854
Short name T316
Test name
Test status
Simulation time 101455764990 ps
CPU time 175.93 seconds
Started Jun 05 04:19:11 PM PDT 24
Finished Jun 05 04:22:07 PM PDT 24
Peak memory 200336 kb
Host smart-a98186b6-c7f9-401b-ab60-85bacbed94cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341212854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.1341212854
Directory /workspace/279.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_alert_test.2356234901
Short name T540
Test name
Test status
Simulation time 46360143 ps
CPU time 0.58 seconds
Started Jun 05 04:16:00 PM PDT 24
Finished Jun 05 04:16:02 PM PDT 24
Peak memory 195812 kb
Host smart-5fc3225e-f07d-4a38-b545-46ac91fd3a7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356234901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.2356234901
Directory /workspace/28.uart_alert_test/latest

Test location /workspace/coverage/default/28.uart_fifo_full.1513250450
Short name T912
Test name
Test status
Simulation time 19123056837 ps
CPU time 31.36 seconds
Started Jun 05 04:16:00 PM PDT 24
Finished Jun 05 04:16:33 PM PDT 24
Peak memory 200416 kb
Host smart-59f4cd9e-7661-408b-897e-3479f815837d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513250450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.1513250450
Directory /workspace/28.uart_fifo_full/latest

Test location /workspace/coverage/default/28.uart_fifo_overflow.2321531830
Short name T438
Test name
Test status
Simulation time 69050461712 ps
CPU time 34.59 seconds
Started Jun 05 04:16:00 PM PDT 24
Finished Jun 05 04:16:36 PM PDT 24
Peak memory 200328 kb
Host smart-2b6b497e-e1cc-4e5f-ac32-5cbd9e31a0ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321531830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.2321531830
Directory /workspace/28.uart_fifo_overflow/latest

Test location /workspace/coverage/default/28.uart_fifo_reset.1013077071
Short name T190
Test name
Test status
Simulation time 45086362953 ps
CPU time 32.2 seconds
Started Jun 05 04:16:08 PM PDT 24
Finished Jun 05 04:16:42 PM PDT 24
Peak memory 200324 kb
Host smart-93fca03b-a679-4269-b6b0-ff63f820c597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013077071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.1013077071
Directory /workspace/28.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_intr.2528921297
Short name T829
Test name
Test status
Simulation time 42491374673 ps
CPU time 74.05 seconds
Started Jun 05 04:16:02 PM PDT 24
Finished Jun 05 04:17:17 PM PDT 24
Peak memory 200360 kb
Host smart-67690ef1-0f50-40ce-ae9f-99a43a49d552
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528921297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.2528921297
Directory /workspace/28.uart_intr/latest

Test location /workspace/coverage/default/28.uart_long_xfer_wo_dly.3073864402
Short name T1155
Test name
Test status
Simulation time 43309029926 ps
CPU time 163.33 seconds
Started Jun 05 04:16:01 PM PDT 24
Finished Jun 05 04:18:45 PM PDT 24
Peak memory 200352 kb
Host smart-bbb6081d-060d-436e-95ac-316dcb15876f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3073864402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.3073864402
Directory /workspace/28.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/28.uart_loopback.3418542219
Short name T340
Test name
Test status
Simulation time 17858445144 ps
CPU time 5.65 seconds
Started Jun 05 04:16:00 PM PDT 24
Finished Jun 05 04:16:06 PM PDT 24
Peak memory 200328 kb
Host smart-73225de4-84d5-46f9-b824-4e4c00bc93d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418542219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_loopback.3418542219
Directory /workspace/28.uart_loopback/latest

Test location /workspace/coverage/default/28.uart_noise_filter.2465155071
Short name T1170
Test name
Test status
Simulation time 104950465078 ps
CPU time 102.33 seconds
Started Jun 05 04:15:58 PM PDT 24
Finished Jun 05 04:17:41 PM PDT 24
Peak memory 200228 kb
Host smart-3a56c2aa-3d75-41a1-95e4-b8d49e02602e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465155071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_noise_filter.2465155071
Directory /workspace/28.uart_noise_filter/latest

Test location /workspace/coverage/default/28.uart_perf.864652771
Short name T786
Test name
Test status
Simulation time 18268144173 ps
CPU time 794.96 seconds
Started Jun 05 04:15:58 PM PDT 24
Finished Jun 05 04:29:14 PM PDT 24
Peak memory 200360 kb
Host smart-b8be0d7c-0654-4d1b-95f7-072d72142606
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=864652771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.864652771
Directory /workspace/28.uart_perf/latest

Test location /workspace/coverage/default/28.uart_rx_oversample.852845007
Short name T1164
Test name
Test status
Simulation time 5717520069 ps
CPU time 5.5 seconds
Started Jun 05 04:16:00 PM PDT 24
Finished Jun 05 04:16:07 PM PDT 24
Peak memory 198684 kb
Host smart-aa0bd6d4-a7e6-437a-9bc7-2397364a74db
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=852845007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.852845007
Directory /workspace/28.uart_rx_oversample/latest

Test location /workspace/coverage/default/28.uart_rx_parity_err.4035308419
Short name T255
Test name
Test status
Simulation time 42222404209 ps
CPU time 16.8 seconds
Started Jun 05 04:16:00 PM PDT 24
Finished Jun 05 04:16:18 PM PDT 24
Peak memory 200336 kb
Host smart-60c3235b-d4a5-4817-b8bc-7df0bf6d65d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035308419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.4035308419
Directory /workspace/28.uart_rx_parity_err/latest

Test location /workspace/coverage/default/28.uart_rx_start_bit_filter.3151200474
Short name T296
Test name
Test status
Simulation time 34114607507 ps
CPU time 26.39 seconds
Started Jun 05 04:16:01 PM PDT 24
Finished Jun 05 04:16:28 PM PDT 24
Peak memory 196408 kb
Host smart-e5053f12-4fc3-4b8d-8707-dd7c5761f16d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151200474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.3151200474
Directory /workspace/28.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/28.uart_smoke.67210015
Short name T274
Test name
Test status
Simulation time 5266574412 ps
CPU time 9.81 seconds
Started Jun 05 04:16:04 PM PDT 24
Finished Jun 05 04:16:14 PM PDT 24
Peak memory 200396 kb
Host smart-c5e27308-6585-4c93-ba43-af436034da61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67210015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_smoke.67210015
Directory /workspace/28.uart_smoke/latest

Test location /workspace/coverage/default/28.uart_stress_all.3570953070
Short name T1087
Test name
Test status
Simulation time 176211771871 ps
CPU time 422.86 seconds
Started Jun 05 04:16:00 PM PDT 24
Finished Jun 05 04:23:04 PM PDT 24
Peak memory 200412 kb
Host smart-f2b92542-e5ce-4ea5-905e-3f681ed5bd06
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570953070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.3570953070
Directory /workspace/28.uart_stress_all/latest

Test location /workspace/coverage/default/28.uart_stress_all_with_rand_reset.2975043079
Short name T77
Test name
Test status
Simulation time 65290651742 ps
CPU time 781.02 seconds
Started Jun 05 04:16:02 PM PDT 24
Finished Jun 05 04:29:04 PM PDT 24
Peak memory 225144 kb
Host smart-55c2a151-3297-4b47-9bc4-ee3366c186e2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975043079 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 28.uart_stress_all_with_rand_reset.2975043079
Directory /workspace/28.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.uart_tx_ovrd.751643404
Short name T380
Test name
Test status
Simulation time 1447593255 ps
CPU time 1.22 seconds
Started Jun 05 04:15:58 PM PDT 24
Finished Jun 05 04:16:00 PM PDT 24
Peak memory 199516 kb
Host smart-fdf9b2e3-9e28-4f24-b9f5-af491f2f0cb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751643404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.751643404
Directory /workspace/28.uart_tx_ovrd/latest

Test location /workspace/coverage/default/28.uart_tx_rx.4084370017
Short name T665
Test name
Test status
Simulation time 59447241041 ps
CPU time 149.12 seconds
Started Jun 05 04:16:00 PM PDT 24
Finished Jun 05 04:18:30 PM PDT 24
Peak memory 200388 kb
Host smart-2098817e-7a3a-49b1-9b7a-2fc50ef65804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084370017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.4084370017
Directory /workspace/28.uart_tx_rx/latest

Test location /workspace/coverage/default/280.uart_fifo_reset.1558111488
Short name T108
Test name
Test status
Simulation time 86196577671 ps
CPU time 35.19 seconds
Started Jun 05 04:19:08 PM PDT 24
Finished Jun 05 04:19:43 PM PDT 24
Peak memory 200328 kb
Host smart-0a2663bf-c358-4ad9-985b-609c4b2d689e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558111488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.1558111488
Directory /workspace/280.uart_fifo_reset/latest

Test location /workspace/coverage/default/281.uart_fifo_reset.2612423540
Short name T262
Test name
Test status
Simulation time 11612553792 ps
CPU time 15.17 seconds
Started Jun 05 04:19:10 PM PDT 24
Finished Jun 05 04:19:26 PM PDT 24
Peak memory 200376 kb
Host smart-4aa0892a-c9cb-46fb-871a-465ec246aaac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612423540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.2612423540
Directory /workspace/281.uart_fifo_reset/latest

Test location /workspace/coverage/default/282.uart_fifo_reset.2934863666
Short name T818
Test name
Test status
Simulation time 38294487511 ps
CPU time 67.13 seconds
Started Jun 05 04:19:09 PM PDT 24
Finished Jun 05 04:20:17 PM PDT 24
Peak memory 200360 kb
Host smart-07bb2ce7-f987-43fb-bc2b-2ed6db925d0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934863666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.2934863666
Directory /workspace/282.uart_fifo_reset/latest

Test location /workspace/coverage/default/283.uart_fifo_reset.1414193101
Short name T522
Test name
Test status
Simulation time 43381248640 ps
CPU time 72.34 seconds
Started Jun 05 04:19:10 PM PDT 24
Finished Jun 05 04:20:24 PM PDT 24
Peak memory 200440 kb
Host smart-ca797ffa-f077-4aef-9a5d-f0c4c5a64ebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414193101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.1414193101
Directory /workspace/283.uart_fifo_reset/latest

Test location /workspace/coverage/default/284.uart_fifo_reset.955611351
Short name T698
Test name
Test status
Simulation time 5582900654 ps
CPU time 11.6 seconds
Started Jun 05 04:19:09 PM PDT 24
Finished Jun 05 04:19:21 PM PDT 24
Peak memory 200460 kb
Host smart-f7be934a-1b2b-4449-b084-c735f2a4d43f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955611351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.955611351
Directory /workspace/284.uart_fifo_reset/latest

Test location /workspace/coverage/default/285.uart_fifo_reset.2848745677
Short name T543
Test name
Test status
Simulation time 84626822237 ps
CPU time 74.96 seconds
Started Jun 05 04:19:10 PM PDT 24
Finished Jun 05 04:20:25 PM PDT 24
Peak memory 200572 kb
Host smart-b2f3bef0-fcd8-45f0-a828-00c99ab67996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848745677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.2848745677
Directory /workspace/285.uart_fifo_reset/latest

Test location /workspace/coverage/default/286.uart_fifo_reset.1114953286
Short name T466
Test name
Test status
Simulation time 50327368234 ps
CPU time 45.94 seconds
Started Jun 05 04:19:19 PM PDT 24
Finished Jun 05 04:20:06 PM PDT 24
Peak memory 200372 kb
Host smart-e7b924ad-5f81-46bc-9be3-4e3b8fabe136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114953286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.1114953286
Directory /workspace/286.uart_fifo_reset/latest

Test location /workspace/coverage/default/288.uart_fifo_reset.368892067
Short name T847
Test name
Test status
Simulation time 6954321662 ps
CPU time 14.87 seconds
Started Jun 05 04:19:12 PM PDT 24
Finished Jun 05 04:19:28 PM PDT 24
Peak memory 200344 kb
Host smart-cd1ce863-67f9-498f-afc6-7369dcec6fa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368892067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.368892067
Directory /workspace/288.uart_fifo_reset/latest

Test location /workspace/coverage/default/289.uart_fifo_reset.1265390054
Short name T303
Test name
Test status
Simulation time 62259773854 ps
CPU time 182.55 seconds
Started Jun 05 04:19:12 PM PDT 24
Finished Jun 05 04:22:15 PM PDT 24
Peak memory 200448 kb
Host smart-c4996dd8-43ae-471c-95f2-e892e2c55888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265390054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.1265390054
Directory /workspace/289.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_alert_test.2445121659
Short name T378
Test name
Test status
Simulation time 12015564 ps
CPU time 0.52 seconds
Started Jun 05 04:15:57 PM PDT 24
Finished Jun 05 04:15:58 PM PDT 24
Peak memory 194788 kb
Host smart-885a51f1-bed8-44c0-9904-03b1f236008c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445121659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.2445121659
Directory /workspace/29.uart_alert_test/latest

Test location /workspace/coverage/default/29.uart_fifo_full.2828549252
Short name T629
Test name
Test status
Simulation time 141898828524 ps
CPU time 56.6 seconds
Started Jun 05 04:16:01 PM PDT 24
Finished Jun 05 04:16:59 PM PDT 24
Peak memory 200384 kb
Host smart-3d1a82bd-5e81-4421-8820-bd2909c49413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828549252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.2828549252
Directory /workspace/29.uart_fifo_full/latest

Test location /workspace/coverage/default/29.uart_fifo_overflow.3510460348
Short name T605
Test name
Test status
Simulation time 49752005558 ps
CPU time 21.71 seconds
Started Jun 05 04:16:01 PM PDT 24
Finished Jun 05 04:16:24 PM PDT 24
Peak memory 200416 kb
Host smart-3b48d0cc-1981-4e23-98ba-7bca350aa2be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510460348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.3510460348
Directory /workspace/29.uart_fifo_overflow/latest

Test location /workspace/coverage/default/29.uart_fifo_reset.775916795
Short name T666
Test name
Test status
Simulation time 149887089830 ps
CPU time 75.32 seconds
Started Jun 05 04:16:00 PM PDT 24
Finished Jun 05 04:17:17 PM PDT 24
Peak memory 200456 kb
Host smart-3a279260-b29d-4cf7-a105-930a5f65ed65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775916795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.775916795
Directory /workspace/29.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_intr.3230577115
Short name T956
Test name
Test status
Simulation time 50742283422 ps
CPU time 39.64 seconds
Started Jun 05 04:15:58 PM PDT 24
Finished Jun 05 04:16:39 PM PDT 24
Peak memory 200192 kb
Host smart-e9015c46-9f68-4a45-a031-851438b9ae44
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230577115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.3230577115
Directory /workspace/29.uart_intr/latest

Test location /workspace/coverage/default/29.uart_long_xfer_wo_dly.2093577994
Short name T678
Test name
Test status
Simulation time 142307179918 ps
CPU time 932.71 seconds
Started Jun 05 04:16:03 PM PDT 24
Finished Jun 05 04:31:37 PM PDT 24
Peak memory 200336 kb
Host smart-9f58c67f-a6a8-40fc-841d-36bb08eeae84
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2093577994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.2093577994
Directory /workspace/29.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/29.uart_loopback.841375839
Short name T359
Test name
Test status
Simulation time 1085690641 ps
CPU time 3.32 seconds
Started Jun 05 04:16:02 PM PDT 24
Finished Jun 05 04:16:07 PM PDT 24
Peak memory 198972 kb
Host smart-737c3806-4169-4eed-80a4-3a20eed5576b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841375839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_loopback.841375839
Directory /workspace/29.uart_loopback/latest

Test location /workspace/coverage/default/29.uart_noise_filter.1820131705
Short name T671
Test name
Test status
Simulation time 16753140666 ps
CPU time 42.21 seconds
Started Jun 05 04:15:58 PM PDT 24
Finished Jun 05 04:16:41 PM PDT 24
Peak memory 200536 kb
Host smart-014e3d5a-f034-4ff8-b587-40319f10aacb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820131705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_noise_filter.1820131705
Directory /workspace/29.uart_noise_filter/latest

Test location /workspace/coverage/default/29.uart_perf.2434400732
Short name T461
Test name
Test status
Simulation time 13920201447 ps
CPU time 152.03 seconds
Started Jun 05 04:16:00 PM PDT 24
Finished Jun 05 04:18:34 PM PDT 24
Peak memory 200376 kb
Host smart-dc14766f-447e-416f-b9cd-6fbd7c9db395
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2434400732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.2434400732
Directory /workspace/29.uart_perf/latest

Test location /workspace/coverage/default/29.uart_rx_oversample.3750414384
Short name T386
Test name
Test status
Simulation time 1490484778 ps
CPU time 3.45 seconds
Started Jun 05 04:16:02 PM PDT 24
Finished Jun 05 04:16:06 PM PDT 24
Peak memory 198608 kb
Host smart-ac46db0d-14a7-433f-be30-34544f879f2c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3750414384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.3750414384
Directory /workspace/29.uart_rx_oversample/latest

Test location /workspace/coverage/default/29.uart_rx_parity_err.1503699929
Short name T495
Test name
Test status
Simulation time 3366007425 ps
CPU time 6.45 seconds
Started Jun 05 04:15:59 PM PDT 24
Finished Jun 05 04:16:06 PM PDT 24
Peak memory 199308 kb
Host smart-0da974ee-d401-47fe-a23b-af2e2334960d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503699929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.1503699929
Directory /workspace/29.uart_rx_parity_err/latest

Test location /workspace/coverage/default/29.uart_rx_start_bit_filter.2016266833
Short name T988
Test name
Test status
Simulation time 34998628174 ps
CPU time 12.95 seconds
Started Jun 05 04:15:58 PM PDT 24
Finished Jun 05 04:16:12 PM PDT 24
Peak memory 196448 kb
Host smart-a8794d41-b093-4b98-b0ae-1af94036af8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016266833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.2016266833
Directory /workspace/29.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/29.uart_smoke.933632183
Short name T730
Test name
Test status
Simulation time 571768360 ps
CPU time 1.39 seconds
Started Jun 05 04:16:03 PM PDT 24
Finished Jun 05 04:16:06 PM PDT 24
Peak memory 199676 kb
Host smart-d9eb8f15-c5e2-47b5-b985-5058c6df7c29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933632183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_smoke.933632183
Directory /workspace/29.uart_smoke/latest

Test location /workspace/coverage/default/29.uart_stress_all.50595600
Short name T650
Test name
Test status
Simulation time 373613892828 ps
CPU time 2507.88 seconds
Started Jun 05 04:16:02 PM PDT 24
Finished Jun 05 04:57:51 PM PDT 24
Peak memory 200596 kb
Host smart-58b7c14d-6f1e-4d04-b5ab-3af09d3adfd3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50595600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.50595600
Directory /workspace/29.uart_stress_all/latest

Test location /workspace/coverage/default/29.uart_stress_all_with_rand_reset.2038409171
Short name T29
Test name
Test status
Simulation time 29706325101 ps
CPU time 462.47 seconds
Started Jun 05 04:16:00 PM PDT 24
Finished Jun 05 04:23:44 PM PDT 24
Peak memory 216652 kb
Host smart-4d735b5c-03e7-4c13-a4cd-b59fe46438b4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038409171 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 29.uart_stress_all_with_rand_reset.2038409171
Directory /workspace/29.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.uart_tx_ovrd.4269091964
Short name T846
Test name
Test status
Simulation time 718725957 ps
CPU time 2.6 seconds
Started Jun 05 04:15:58 PM PDT 24
Finished Jun 05 04:16:02 PM PDT 24
Peak memory 199064 kb
Host smart-758c71e4-0c17-4d0f-ba4e-c56f7952a684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269091964 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.4269091964
Directory /workspace/29.uart_tx_ovrd/latest

Test location /workspace/coverage/default/29.uart_tx_rx.3903042922
Short name T638
Test name
Test status
Simulation time 45002621689 ps
CPU time 131.68 seconds
Started Jun 05 04:16:00 PM PDT 24
Finished Jun 05 04:18:13 PM PDT 24
Peak memory 200436 kb
Host smart-0fa61196-6b16-4637-b51c-9b91e83cb86f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903042922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.3903042922
Directory /workspace/29.uart_tx_rx/latest

Test location /workspace/coverage/default/290.uart_fifo_reset.907071288
Short name T445
Test name
Test status
Simulation time 391811191719 ps
CPU time 36.32 seconds
Started Jun 05 04:19:09 PM PDT 24
Finished Jun 05 04:19:46 PM PDT 24
Peak memory 200400 kb
Host smart-6ecb261c-582c-4b14-826a-0519a3712496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907071288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.907071288
Directory /workspace/290.uart_fifo_reset/latest

Test location /workspace/coverage/default/291.uart_fifo_reset.834285877
Short name T199
Test name
Test status
Simulation time 18033926071 ps
CPU time 51.02 seconds
Started Jun 05 04:19:09 PM PDT 24
Finished Jun 05 04:20:01 PM PDT 24
Peak memory 200468 kb
Host smart-14c65cf9-dd5a-4fad-b3cb-e1b1a417437b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834285877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.834285877
Directory /workspace/291.uart_fifo_reset/latest

Test location /workspace/coverage/default/292.uart_fifo_reset.1992187966
Short name T394
Test name
Test status
Simulation time 42783027719 ps
CPU time 19.86 seconds
Started Jun 05 04:19:08 PM PDT 24
Finished Jun 05 04:19:28 PM PDT 24
Peak memory 200360 kb
Host smart-69377e34-cad8-4936-b4b2-361a89164917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992187966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.1992187966
Directory /workspace/292.uart_fifo_reset/latest

Test location /workspace/coverage/default/293.uart_fifo_reset.826588367
Short name T857
Test name
Test status
Simulation time 75322324118 ps
CPU time 153.78 seconds
Started Jun 05 04:19:17 PM PDT 24
Finished Jun 05 04:21:52 PM PDT 24
Peak memory 200464 kb
Host smart-9b593771-9ab1-4e36-9177-4b2db7210a81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826588367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.826588367
Directory /workspace/293.uart_fifo_reset/latest

Test location /workspace/coverage/default/294.uart_fifo_reset.2710303767
Short name T327
Test name
Test status
Simulation time 30105956792 ps
CPU time 28.2 seconds
Started Jun 05 04:19:18 PM PDT 24
Finished Jun 05 04:19:46 PM PDT 24
Peak memory 200436 kb
Host smart-322c702d-98a6-4955-b015-8d32eed0268c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710303767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.2710303767
Directory /workspace/294.uart_fifo_reset/latest

Test location /workspace/coverage/default/295.uart_fifo_reset.2333437177
Short name T1080
Test name
Test status
Simulation time 34629517092 ps
CPU time 15.97 seconds
Started Jun 05 04:19:18 PM PDT 24
Finished Jun 05 04:19:35 PM PDT 24
Peak memory 200456 kb
Host smart-783d04ef-d8f3-4ae3-806c-e92e2c31a8f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333437177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.2333437177
Directory /workspace/295.uart_fifo_reset/latest

Test location /workspace/coverage/default/297.uart_fifo_reset.3428420498
Short name T1077
Test name
Test status
Simulation time 41448267264 ps
CPU time 69.17 seconds
Started Jun 05 04:19:17 PM PDT 24
Finished Jun 05 04:20:26 PM PDT 24
Peak memory 200148 kb
Host smart-c0cb5561-0041-4873-bc75-c455c6c97e1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428420498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.3428420498
Directory /workspace/297.uart_fifo_reset/latest

Test location /workspace/coverage/default/298.uart_fifo_reset.1860493657
Short name T212
Test name
Test status
Simulation time 57013197911 ps
CPU time 29.44 seconds
Started Jun 05 04:19:22 PM PDT 24
Finished Jun 05 04:19:52 PM PDT 24
Peak memory 200436 kb
Host smart-99ff8c63-67ae-4287-a8c8-3ba62fb4f7d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860493657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.1860493657
Directory /workspace/298.uart_fifo_reset/latest

Test location /workspace/coverage/default/299.uart_fifo_reset.3967163997
Short name T40
Test name
Test status
Simulation time 48540705984 ps
CPU time 33.22 seconds
Started Jun 05 04:19:21 PM PDT 24
Finished Jun 05 04:19:55 PM PDT 24
Peak memory 200436 kb
Host smart-bace6b8e-6d86-4584-8fa2-27756ab57d58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967163997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.3967163997
Directory /workspace/299.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_alert_test.2785039098
Short name T21
Test name
Test status
Simulation time 39114794 ps
CPU time 0.56 seconds
Started Jun 05 04:14:40 PM PDT 24
Finished Jun 05 04:14:41 PM PDT 24
Peak memory 195812 kb
Host smart-d2e4f768-9d6a-4a8e-82b4-be9c38ce7ad9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785039098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.2785039098
Directory /workspace/3.uart_alert_test/latest

Test location /workspace/coverage/default/3.uart_fifo_full.3895013
Short name T123
Test name
Test status
Simulation time 218810581697 ps
CPU time 181.01 seconds
Started Jun 05 04:14:55 PM PDT 24
Finished Jun 05 04:17:57 PM PDT 24
Peak memory 200444 kb
Host smart-a922aaaa-fec4-42ac-9646-47f0114c9392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.3895013
Directory /workspace/3.uart_fifo_full/latest

Test location /workspace/coverage/default/3.uart_fifo_overflow.1634112717
Short name T158
Test name
Test status
Simulation time 37764603882 ps
CPU time 32.12 seconds
Started Jun 05 04:14:39 PM PDT 24
Finished Jun 05 04:15:12 PM PDT 24
Peak memory 200308 kb
Host smart-d39e8764-16f9-42e2-adbf-a8974d6eb4cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634112717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.1634112717
Directory /workspace/3.uart_fifo_overflow/latest

Test location /workspace/coverage/default/3.uart_fifo_reset.4048476665
Short name T525
Test name
Test status
Simulation time 22014468060 ps
CPU time 40.42 seconds
Started Jun 05 04:14:45 PM PDT 24
Finished Jun 05 04:15:26 PM PDT 24
Peak memory 200476 kb
Host smart-4d6cb759-46b5-4bf2-9f8a-1b4b59a44d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048476665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.4048476665
Directory /workspace/3.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_intr.1895781285
Short name T126
Test name
Test status
Simulation time 52054758337 ps
CPU time 23.81 seconds
Started Jun 05 04:14:40 PM PDT 24
Finished Jun 05 04:15:04 PM PDT 24
Peak memory 199592 kb
Host smart-0f91ba54-2019-4cb8-b8d3-67a67a466410
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895781285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.1895781285
Directory /workspace/3.uart_intr/latest

Test location /workspace/coverage/default/3.uart_long_xfer_wo_dly.3903541839
Short name T842
Test name
Test status
Simulation time 123868619631 ps
CPU time 204.55 seconds
Started Jun 05 04:14:52 PM PDT 24
Finished Jun 05 04:18:17 PM PDT 24
Peak memory 200564 kb
Host smart-7400649c-efa9-4b1e-8e12-18b5ab4305c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3903541839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.3903541839
Directory /workspace/3.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/3.uart_loopback.647591694
Short name T52
Test name
Test status
Simulation time 1646553575 ps
CPU time 1.74 seconds
Started Jun 05 04:15:01 PM PDT 24
Finished Jun 05 04:15:04 PM PDT 24
Peak memory 197716 kb
Host smart-bc1eb3aa-15e6-447a-89c1-5b9d60b6460a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647591694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_loopback.647591694
Directory /workspace/3.uart_loopback/latest

Test location /workspace/coverage/default/3.uart_noise_filter.1031723923
Short name T328
Test name
Test status
Simulation time 24978950599 ps
CPU time 10.66 seconds
Started Jun 05 04:14:54 PM PDT 24
Finished Jun 05 04:15:06 PM PDT 24
Peak memory 195120 kb
Host smart-3fc78607-69de-49cb-8487-15ec57bb839c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031723923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_noise_filter.1031723923
Directory /workspace/3.uart_noise_filter/latest

Test location /workspace/coverage/default/3.uart_perf.2800904268
Short name T625
Test name
Test status
Simulation time 23850021366 ps
CPU time 167.42 seconds
Started Jun 05 04:15:01 PM PDT 24
Finished Jun 05 04:17:49 PM PDT 24
Peak memory 200512 kb
Host smart-064c9a99-fe88-41a4-af2d-7e5559c34af7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2800904268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.2800904268
Directory /workspace/3.uart_perf/latest

Test location /workspace/coverage/default/3.uart_rx_oversample.1043277412
Short name T759
Test name
Test status
Simulation time 7940270352 ps
CPU time 20.07 seconds
Started Jun 05 04:14:46 PM PDT 24
Finished Jun 05 04:15:07 PM PDT 24
Peak memory 199768 kb
Host smart-704d9c63-2094-4559-8b2d-894674a6b13d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1043277412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.1043277412
Directory /workspace/3.uart_rx_oversample/latest

Test location /workspace/coverage/default/3.uart_rx_parity_err.1626340069
Short name T811
Test name
Test status
Simulation time 25239813805 ps
CPU time 46.01 seconds
Started Jun 05 04:14:39 PM PDT 24
Finished Jun 05 04:15:25 PM PDT 24
Peak memory 200420 kb
Host smart-fb157e00-4af6-4d00-9daa-4fdaa4a2d27a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626340069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.1626340069
Directory /workspace/3.uart_rx_parity_err/latest

Test location /workspace/coverage/default/3.uart_rx_start_bit_filter.3376244092
Short name T498
Test name
Test status
Simulation time 4585824360 ps
CPU time 1.9 seconds
Started Jun 05 04:14:47 PM PDT 24
Finished Jun 05 04:14:50 PM PDT 24
Peak memory 196412 kb
Host smart-eb8090cd-b426-49be-92bd-907cebba94ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376244092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.3376244092
Directory /workspace/3.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/3.uart_sec_cm.234001529
Short name T26
Test name
Test status
Simulation time 59423440 ps
CPU time 0.85 seconds
Started Jun 05 04:15:02 PM PDT 24
Finished Jun 05 04:15:04 PM PDT 24
Peak memory 218756 kb
Host smart-3f32a79b-e52c-4874-bfba-588a0d4bc169
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234001529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.234001529
Directory /workspace/3.uart_sec_cm/latest

Test location /workspace/coverage/default/3.uart_smoke.3732282435
Short name T620
Test name
Test status
Simulation time 302252643 ps
CPU time 1.43 seconds
Started Jun 05 04:14:41 PM PDT 24
Finished Jun 05 04:14:43 PM PDT 24
Peak memory 198648 kb
Host smart-f8a349d4-ca82-416b-8a9e-0ff7f28eff37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732282435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_smoke.3732282435
Directory /workspace/3.uart_smoke/latest

Test location /workspace/coverage/default/3.uart_stress_all.1032706352
Short name T1020
Test name
Test status
Simulation time 59083335491 ps
CPU time 66.81 seconds
Started Jun 05 04:14:43 PM PDT 24
Finished Jun 05 04:15:50 PM PDT 24
Peak memory 200448 kb
Host smart-9082f04a-99ae-482a-a0ca-387b41368019
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032706352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.1032706352
Directory /workspace/3.uart_stress_all/latest

Test location /workspace/coverage/default/3.uart_stress_all_with_rand_reset.2234565536
Short name T33
Test name
Test status
Simulation time 247283878503 ps
CPU time 1277.65 seconds
Started Jun 05 04:15:08 PM PDT 24
Finished Jun 05 04:36:27 PM PDT 24
Peak memory 233496 kb
Host smart-d2c6c285-6d1b-438f-b52e-1a1d213ed458
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234565536 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.uart_stress_all_with_rand_reset.2234565536
Directory /workspace/3.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.uart_tx_ovrd.3641662855
Short name T746
Test name
Test status
Simulation time 6571887677 ps
CPU time 15.71 seconds
Started Jun 05 04:14:39 PM PDT 24
Finished Jun 05 04:14:56 PM PDT 24
Peak memory 200316 kb
Host smart-b8336898-f985-45d8-9777-3524881012bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641662855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.3641662855
Directory /workspace/3.uart_tx_ovrd/latest

Test location /workspace/coverage/default/3.uart_tx_rx.2491443011
Short name T798
Test name
Test status
Simulation time 41653486628 ps
CPU time 39.5 seconds
Started Jun 05 04:14:44 PM PDT 24
Finished Jun 05 04:15:23 PM PDT 24
Peak memory 200436 kb
Host smart-9876af35-bb1c-469d-a7ec-3c2745e721db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491443011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.2491443011
Directory /workspace/3.uart_tx_rx/latest

Test location /workspace/coverage/default/30.uart_alert_test.4089138134
Short name T934
Test name
Test status
Simulation time 25664514 ps
CPU time 0.56 seconds
Started Jun 05 04:16:01 PM PDT 24
Finished Jun 05 04:16:03 PM PDT 24
Peak memory 195768 kb
Host smart-e0ac628f-ae98-46a9-a680-8e0c34b8f58d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089138134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.4089138134
Directory /workspace/30.uart_alert_test/latest

Test location /workspace/coverage/default/30.uart_fifo_full.1961040942
Short name T1160
Test name
Test status
Simulation time 19491718256 ps
CPU time 36.22 seconds
Started Jun 05 04:16:00 PM PDT 24
Finished Jun 05 04:16:38 PM PDT 24
Peak memory 200452 kb
Host smart-94fedfa0-9f4a-44a3-b6fa-2315509914b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961040942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.1961040942
Directory /workspace/30.uart_fifo_full/latest

Test location /workspace/coverage/default/30.uart_fifo_overflow.3866378727
Short name T1043
Test name
Test status
Simulation time 153200064456 ps
CPU time 139.21 seconds
Started Jun 05 04:16:02 PM PDT 24
Finished Jun 05 04:18:23 PM PDT 24
Peak memory 200404 kb
Host smart-abeddd67-c4a7-4b30-9b4e-cc069501141b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866378727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.3866378727
Directory /workspace/30.uart_fifo_overflow/latest

Test location /workspace/coverage/default/30.uart_fifo_reset.2304106486
Short name T157
Test name
Test status
Simulation time 70169085067 ps
CPU time 60.7 seconds
Started Jun 05 04:16:02 PM PDT 24
Finished Jun 05 04:17:04 PM PDT 24
Peak memory 200420 kb
Host smart-66c9db13-430b-41b3-88db-391f30f45758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304106486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.2304106486
Directory /workspace/30.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_intr.1064564457
Short name T1171
Test name
Test status
Simulation time 51971903385 ps
CPU time 53.77 seconds
Started Jun 05 04:16:00 PM PDT 24
Finished Jun 05 04:16:55 PM PDT 24
Peak memory 200360 kb
Host smart-64d5afb0-cd5c-419b-8a55-d17ed490cd4c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064564457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.1064564457
Directory /workspace/30.uart_intr/latest

Test location /workspace/coverage/default/30.uart_long_xfer_wo_dly.1722978713
Short name T544
Test name
Test status
Simulation time 30494714692 ps
CPU time 203.1 seconds
Started Jun 05 04:16:00 PM PDT 24
Finished Jun 05 04:19:24 PM PDT 24
Peak memory 200344 kb
Host smart-5c36e459-f52a-4758-bb20-e4865101f797
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1722978713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.1722978713
Directory /workspace/30.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/30.uart_loopback.2608809437
Short name T436
Test name
Test status
Simulation time 102353825 ps
CPU time 1.01 seconds
Started Jun 05 04:15:59 PM PDT 24
Finished Jun 05 04:16:01 PM PDT 24
Peak memory 199172 kb
Host smart-0d044e8a-e68d-4d8f-a940-63ff03659573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608809437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_loopback.2608809437
Directory /workspace/30.uart_loopback/latest

Test location /workspace/coverage/default/30.uart_noise_filter.2980285804
Short name T501
Test name
Test status
Simulation time 139896529591 ps
CPU time 63.13 seconds
Started Jun 05 04:16:01 PM PDT 24
Finished Jun 05 04:17:06 PM PDT 24
Peak memory 216992 kb
Host smart-50b98ba6-dab7-40c6-99c1-761fb40cb039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980285804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_noise_filter.2980285804
Directory /workspace/30.uart_noise_filter/latest

Test location /workspace/coverage/default/30.uart_perf.3682920548
Short name T382
Test name
Test status
Simulation time 8799248484 ps
CPU time 130.58 seconds
Started Jun 05 04:16:00 PM PDT 24
Finished Jun 05 04:18:12 PM PDT 24
Peak memory 200424 kb
Host smart-1181414a-5ad1-4bfa-83b8-907d5bdfb0b0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3682920548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.3682920548
Directory /workspace/30.uart_perf/latest

Test location /workspace/coverage/default/30.uart_rx_oversample.2877815755
Short name T383
Test name
Test status
Simulation time 2339552156 ps
CPU time 3.53 seconds
Started Jun 05 04:16:02 PM PDT 24
Finished Jun 05 04:16:07 PM PDT 24
Peak memory 198312 kb
Host smart-3e4f13cb-e01e-4a6f-9828-b9a0cff1b364
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2877815755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.2877815755
Directory /workspace/30.uart_rx_oversample/latest

Test location /workspace/coverage/default/30.uart_rx_parity_err.3152973243
Short name T641
Test name
Test status
Simulation time 125896252727 ps
CPU time 175.73 seconds
Started Jun 05 04:16:00 PM PDT 24
Finished Jun 05 04:18:57 PM PDT 24
Peak memory 200356 kb
Host smart-0d2a040f-13eb-4cfc-9883-9b3cdb832b95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152973243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.3152973243
Directory /workspace/30.uart_rx_parity_err/latest

Test location /workspace/coverage/default/30.uart_rx_start_bit_filter.1056577772
Short name T874
Test name
Test status
Simulation time 4738749990 ps
CPU time 5.16 seconds
Started Jun 05 04:16:02 PM PDT 24
Finished Jun 05 04:16:08 PM PDT 24
Peak memory 196888 kb
Host smart-1d1e80aa-6b42-4070-92bf-c2b947336819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056577772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.1056577772
Directory /workspace/30.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/30.uart_smoke.2558061369
Short name T729
Test name
Test status
Simulation time 537321112 ps
CPU time 2.4 seconds
Started Jun 05 04:15:59 PM PDT 24
Finished Jun 05 04:16:03 PM PDT 24
Peak memory 198980 kb
Host smart-b12dfff7-f05c-4e26-88d3-05d430680c66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558061369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_smoke.2558061369
Directory /workspace/30.uart_smoke/latest

Test location /workspace/coverage/default/30.uart_stress_all_with_rand_reset.891381226
Short name T1129
Test name
Test status
Simulation time 24640728481 ps
CPU time 292.79 seconds
Started Jun 05 04:15:59 PM PDT 24
Finished Jun 05 04:20:52 PM PDT 24
Peak memory 208716 kb
Host smart-cb8faf00-78a9-40c2-9ee4-9e88a9a09c92
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891381226 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 30.uart_stress_all_with_rand_reset.891381226
Directory /workspace/30.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.uart_tx_ovrd.2730254588
Short name T889
Test name
Test status
Simulation time 12235126671 ps
CPU time 30.95 seconds
Started Jun 05 04:16:04 PM PDT 24
Finished Jun 05 04:16:35 PM PDT 24
Peak memory 200332 kb
Host smart-0a0bff9a-63ad-4db4-83f6-994a97cb15da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730254588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.2730254588
Directory /workspace/30.uart_tx_ovrd/latest

Test location /workspace/coverage/default/30.uart_tx_rx.185983785
Short name T579
Test name
Test status
Simulation time 14312749101 ps
CPU time 12.28 seconds
Started Jun 05 04:16:01 PM PDT 24
Finished Jun 05 04:16:14 PM PDT 24
Peak memory 200152 kb
Host smart-f7bd596c-2573-4412-8d8f-19eebe2d5006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185983785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.185983785
Directory /workspace/30.uart_tx_rx/latest

Test location /workspace/coverage/default/31.uart_alert_test.2515556855
Short name T530
Test name
Test status
Simulation time 17820988 ps
CPU time 0.57 seconds
Started Jun 05 04:16:10 PM PDT 24
Finished Jun 05 04:16:12 PM PDT 24
Peak memory 195812 kb
Host smart-6cb5cd60-f144-4f39-8f69-cf1edd394d54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515556855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.2515556855
Directory /workspace/31.uart_alert_test/latest

Test location /workspace/coverage/default/31.uart_fifo_full.4084344013
Short name T714
Test name
Test status
Simulation time 15632804027 ps
CPU time 6.5 seconds
Started Jun 05 04:16:07 PM PDT 24
Finished Jun 05 04:16:15 PM PDT 24
Peak memory 200404 kb
Host smart-7ffb53f3-0ce3-4bf8-a5ca-668f53f863bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084344013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.4084344013
Directory /workspace/31.uart_fifo_full/latest

Test location /workspace/coverage/default/31.uart_fifo_overflow.2031470739
Short name T161
Test name
Test status
Simulation time 154324433187 ps
CPU time 65.07 seconds
Started Jun 05 04:16:08 PM PDT 24
Finished Jun 05 04:17:15 PM PDT 24
Peak memory 200408 kb
Host smart-d9bccded-edbc-455a-8531-e88c5bb8f8f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031470739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.2031470739
Directory /workspace/31.uart_fifo_overflow/latest

Test location /workspace/coverage/default/31.uart_fifo_reset.1495373747
Short name T1008
Test name
Test status
Simulation time 38310437382 ps
CPU time 71.65 seconds
Started Jun 05 04:16:06 PM PDT 24
Finished Jun 05 04:17:19 PM PDT 24
Peak memory 200416 kb
Host smart-6e8ec310-a3b6-408d-a127-0f356a8ca44f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495373747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.1495373747
Directory /workspace/31.uart_fifo_reset/latest

Test location /workspace/coverage/default/31.uart_intr.3576487162
Short name T487
Test name
Test status
Simulation time 252220651882 ps
CPU time 447.14 seconds
Started Jun 05 04:16:09 PM PDT 24
Finished Jun 05 04:23:37 PM PDT 24
Peak memory 199700 kb
Host smart-0c8fc422-468f-436a-a227-877cd31d1ed3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576487162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.3576487162
Directory /workspace/31.uart_intr/latest

Test location /workspace/coverage/default/31.uart_long_xfer_wo_dly.2074137720
Short name T863
Test name
Test status
Simulation time 142287633646 ps
CPU time 1082.86 seconds
Started Jun 05 04:16:06 PM PDT 24
Finished Jun 05 04:34:10 PM PDT 24
Peak memory 200452 kb
Host smart-dfac35ca-5b56-4199-b5bc-c819578cef10
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2074137720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.2074137720
Directory /workspace/31.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/31.uart_loopback.3789061995
Short name T428
Test name
Test status
Simulation time 8678588477 ps
CPU time 15.2 seconds
Started Jun 05 04:16:06 PM PDT 24
Finished Jun 05 04:16:23 PM PDT 24
Peak memory 198880 kb
Host smart-e2af65f3-148a-4486-847f-b2e1a436c8d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789061995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_loopback.3789061995
Directory /workspace/31.uart_loopback/latest

Test location /workspace/coverage/default/31.uart_noise_filter.1771476490
Short name T1006
Test name
Test status
Simulation time 45076213348 ps
CPU time 81.49 seconds
Started Jun 05 04:16:07 PM PDT 24
Finished Jun 05 04:17:30 PM PDT 24
Peak memory 200612 kb
Host smart-1af4ace6-e40f-444f-834e-b07e4007d3f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771476490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_noise_filter.1771476490
Directory /workspace/31.uart_noise_filter/latest

Test location /workspace/coverage/default/31.uart_perf.2857161404
Short name T1100
Test name
Test status
Simulation time 21345576781 ps
CPU time 493.49 seconds
Started Jun 05 04:16:08 PM PDT 24
Finished Jun 05 04:24:23 PM PDT 24
Peak memory 200588 kb
Host smart-fc2161bc-eff4-4ecd-bc3d-7e1a047a9d99
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2857161404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.2857161404
Directory /workspace/31.uart_perf/latest

Test location /workspace/coverage/default/31.uart_rx_oversample.1627391771
Short name T990
Test name
Test status
Simulation time 7104043971 ps
CPU time 69.54 seconds
Started Jun 05 04:16:08 PM PDT 24
Finished Jun 05 04:17:19 PM PDT 24
Peak memory 199952 kb
Host smart-0023cedd-ac39-45d5-b02a-838a955e9128
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1627391771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.1627391771
Directory /workspace/31.uart_rx_oversample/latest

Test location /workspace/coverage/default/31.uart_rx_parity_err.1287039435
Short name T118
Test name
Test status
Simulation time 113364610439 ps
CPU time 209.98 seconds
Started Jun 05 04:16:07 PM PDT 24
Finished Jun 05 04:19:38 PM PDT 24
Peak memory 200424 kb
Host smart-7e9da01e-e33c-48f5-8347-68a20011dd31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287039435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.1287039435
Directory /workspace/31.uart_rx_parity_err/latest

Test location /workspace/coverage/default/31.uart_rx_start_bit_filter.739980761
Short name T1140
Test name
Test status
Simulation time 31036875470 ps
CPU time 24.9 seconds
Started Jun 05 04:16:08 PM PDT 24
Finished Jun 05 04:16:34 PM PDT 24
Peak memory 196376 kb
Host smart-8a69685a-0ba6-4f60-91f1-cecf97f60b12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739980761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.739980761
Directory /workspace/31.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/31.uart_smoke.1275590941
Short name T504
Test name
Test status
Simulation time 5635485241 ps
CPU time 10.44 seconds
Started Jun 05 04:16:00 PM PDT 24
Finished Jun 05 04:16:12 PM PDT 24
Peak memory 200100 kb
Host smart-2e59f4de-05c4-481c-b385-d1cfb0aae83b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275590941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_smoke.1275590941
Directory /workspace/31.uart_smoke/latest

Test location /workspace/coverage/default/31.uart_stress_all.1152759721
Short name T792
Test name
Test status
Simulation time 138029087455 ps
CPU time 237.83 seconds
Started Jun 05 04:16:11 PM PDT 24
Finished Jun 05 04:20:09 PM PDT 24
Peak memory 200472 kb
Host smart-ec36607a-c183-4d37-931a-bff84b7313ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152759721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.1152759721
Directory /workspace/31.uart_stress_all/latest

Test location /workspace/coverage/default/31.uart_stress_all_with_rand_reset.1265476620
Short name T673
Test name
Test status
Simulation time 31971783769 ps
CPU time 190.48 seconds
Started Jun 05 04:16:06 PM PDT 24
Finished Jun 05 04:19:17 PM PDT 24
Peak memory 208696 kb
Host smart-ee6ff0a1-c5ec-4da0-8fd1-42cd93d4f3d9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265476620 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 31.uart_stress_all_with_rand_reset.1265476620
Directory /workspace/31.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.uart_tx_ovrd.1515028816
Short name T563
Test name
Test status
Simulation time 1900042836 ps
CPU time 2.11 seconds
Started Jun 05 04:16:08 PM PDT 24
Finished Jun 05 04:16:11 PM PDT 24
Peak memory 199324 kb
Host smart-79f16d1f-8015-42ae-9469-9b63727b3119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515028816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.1515028816
Directory /workspace/31.uart_tx_ovrd/latest

Test location /workspace/coverage/default/31.uart_tx_rx.3353792290
Short name T737
Test name
Test status
Simulation time 85057939394 ps
CPU time 42.75 seconds
Started Jun 05 04:16:07 PM PDT 24
Finished Jun 05 04:16:51 PM PDT 24
Peak memory 200376 kb
Host smart-fa50ef87-0324-4107-9ea7-255b41102ec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353792290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.3353792290
Directory /workspace/31.uart_tx_rx/latest

Test location /workspace/coverage/default/32.uart_alert_test.3615603090
Short name T429
Test name
Test status
Simulation time 18381613 ps
CPU time 0.63 seconds
Started Jun 05 04:16:09 PM PDT 24
Finished Jun 05 04:16:11 PM PDT 24
Peak memory 195756 kb
Host smart-47bf3cb9-bd6b-4786-b8e3-e668472da93f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615603090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.3615603090
Directory /workspace/32.uart_alert_test/latest

Test location /workspace/coverage/default/32.uart_fifo_full.2915108825
Short name T1079
Test name
Test status
Simulation time 37778787987 ps
CPU time 54.38 seconds
Started Jun 05 04:16:08 PM PDT 24
Finished Jun 05 04:17:04 PM PDT 24
Peak memory 200452 kb
Host smart-92db4212-00a6-4106-9b21-69c5906a6070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915108825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.2915108825
Directory /workspace/32.uart_fifo_full/latest

Test location /workspace/coverage/default/32.uart_fifo_overflow.4279614916
Short name T1073
Test name
Test status
Simulation time 115682137946 ps
CPU time 210.67 seconds
Started Jun 05 04:16:07 PM PDT 24
Finished Jun 05 04:19:38 PM PDT 24
Peak memory 200436 kb
Host smart-b72ee5d3-9fea-42a9-b544-46b2e2a7904d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279614916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.4279614916
Directory /workspace/32.uart_fifo_overflow/latest

Test location /workspace/coverage/default/32.uart_fifo_reset.3715175787
Short name T831
Test name
Test status
Simulation time 31527776111 ps
CPU time 15.4 seconds
Started Jun 05 04:16:07 PM PDT 24
Finished Jun 05 04:16:24 PM PDT 24
Peak memory 200236 kb
Host smart-e9d57cd4-6c9d-46bd-8fdb-1a74a9f974af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715175787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.3715175787
Directory /workspace/32.uart_fifo_reset/latest

Test location /workspace/coverage/default/32.uart_intr.2828210332
Short name T325
Test name
Test status
Simulation time 2320546694 ps
CPU time 4.52 seconds
Started Jun 05 04:16:10 PM PDT 24
Finished Jun 05 04:16:16 PM PDT 24
Peak memory 200392 kb
Host smart-94082321-a304-4219-b43e-404b978ea6da
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828210332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.2828210332
Directory /workspace/32.uart_intr/latest

Test location /workspace/coverage/default/32.uart_long_xfer_wo_dly.28654975
Short name T617
Test name
Test status
Simulation time 99135561520 ps
CPU time 583.23 seconds
Started Jun 05 04:16:07 PM PDT 24
Finished Jun 05 04:25:52 PM PDT 24
Peak memory 200392 kb
Host smart-b8d44977-4631-49c1-ad12-f8f8fcfee8d8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=28654975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.28654975
Directory /workspace/32.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/32.uart_loopback.880122765
Short name T993
Test name
Test status
Simulation time 2460966490 ps
CPU time 2.64 seconds
Started Jun 05 04:16:05 PM PDT 24
Finished Jun 05 04:16:08 PM PDT 24
Peak memory 199284 kb
Host smart-ba607f1c-e807-473e-a4ff-c281d614efee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880122765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_loopback.880122765
Directory /workspace/32.uart_loopback/latest

Test location /workspace/coverage/default/32.uart_noise_filter.2619294808
Short name T537
Test name
Test status
Simulation time 96306108479 ps
CPU time 239.84 seconds
Started Jun 05 04:16:08 PM PDT 24
Finished Jun 05 04:20:10 PM PDT 24
Peak memory 200540 kb
Host smart-8ffedbe5-3c63-491a-8107-043270b80676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619294808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_noise_filter.2619294808
Directory /workspace/32.uart_noise_filter/latest

Test location /workspace/coverage/default/32.uart_perf.2925709518
Short name T467
Test name
Test status
Simulation time 5526002798 ps
CPU time 125.04 seconds
Started Jun 05 04:16:07 PM PDT 24
Finished Jun 05 04:18:14 PM PDT 24
Peak memory 200432 kb
Host smart-0ad1ba06-e650-4164-b0c9-ea5ea8743d24
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2925709518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.2925709518
Directory /workspace/32.uart_perf/latest

Test location /workspace/coverage/default/32.uart_rx_oversample.377432565
Short name T18
Test name
Test status
Simulation time 2668862243 ps
CPU time 2.57 seconds
Started Jun 05 04:16:06 PM PDT 24
Finished Jun 05 04:16:10 PM PDT 24
Peak memory 198444 kb
Host smart-e105e0c4-dfd2-4c0f-b2d6-a26f63ab6baf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=377432565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.377432565
Directory /workspace/32.uart_rx_oversample/latest

Test location /workspace/coverage/default/32.uart_rx_parity_err.2285130646
Short name T511
Test name
Test status
Simulation time 35654661362 ps
CPU time 57.21 seconds
Started Jun 05 04:16:07 PM PDT 24
Finished Jun 05 04:17:05 PM PDT 24
Peak memory 200316 kb
Host smart-4d0bcbc8-2cc4-4a9c-9022-acffef52a2a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285130646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.2285130646
Directory /workspace/32.uart_rx_parity_err/latest

Test location /workspace/coverage/default/32.uart_rx_start_bit_filter.4000159774
Short name T9
Test name
Test status
Simulation time 42307751931 ps
CPU time 64.34 seconds
Started Jun 05 04:16:06 PM PDT 24
Finished Jun 05 04:17:11 PM PDT 24
Peak memory 196440 kb
Host smart-d656c9f1-71ad-4173-956b-2fae66897d26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000159774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.4000159774
Directory /workspace/32.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/32.uart_smoke.3674897616
Short name T706
Test name
Test status
Simulation time 937157451 ps
CPU time 3.28 seconds
Started Jun 05 04:16:06 PM PDT 24
Finished Jun 05 04:16:10 PM PDT 24
Peak memory 199988 kb
Host smart-ad825620-8337-40f6-8414-ce4724c2afee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674897616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_smoke.3674897616
Directory /workspace/32.uart_smoke/latest

Test location /workspace/coverage/default/32.uart_stress_all.3150743078
Short name T633
Test name
Test status
Simulation time 146503536427 ps
CPU time 236.13 seconds
Started Jun 05 04:16:09 PM PDT 24
Finished Jun 05 04:20:06 PM PDT 24
Peak memory 200400 kb
Host smart-efb1bdd5-0f71-42bb-a959-f3f99c2b2073
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150743078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.3150743078
Directory /workspace/32.uart_stress_all/latest

Test location /workspace/coverage/default/32.uart_stress_all_with_rand_reset.2597420518
Short name T1093
Test name
Test status
Simulation time 44859663453 ps
CPU time 752.9 seconds
Started Jun 05 04:16:08 PM PDT 24
Finished Jun 05 04:28:43 PM PDT 24
Peak memory 225276 kb
Host smart-178a53df-eed5-4334-911c-b828980ebd1d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597420518 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 32.uart_stress_all_with_rand_reset.2597420518
Directory /workspace/32.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.uart_tx_ovrd.1879896705
Short name T1014
Test name
Test status
Simulation time 919913651 ps
CPU time 3.16 seconds
Started Jun 05 04:16:07 PM PDT 24
Finished Jun 05 04:16:11 PM PDT 24
Peak memory 199164 kb
Host smart-342a23dc-4d0d-49f1-bcde-cd2cdebca6b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879896705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.1879896705
Directory /workspace/32.uart_tx_ovrd/latest

Test location /workspace/coverage/default/32.uart_tx_rx.3009994346
Short name T567
Test name
Test status
Simulation time 49070059184 ps
CPU time 102.61 seconds
Started Jun 05 04:16:07 PM PDT 24
Finished Jun 05 04:17:51 PM PDT 24
Peak memory 200460 kb
Host smart-08d242bb-79c3-4239-84fe-39571c6798e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009994346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.3009994346
Directory /workspace/32.uart_tx_rx/latest

Test location /workspace/coverage/default/33.uart_alert_test.1831981776
Short name T470
Test name
Test status
Simulation time 27377860 ps
CPU time 0.54 seconds
Started Jun 05 04:16:15 PM PDT 24
Finished Jun 05 04:16:16 PM PDT 24
Peak memory 195812 kb
Host smart-14d641ff-77a6-4639-8b0a-e52c17d78dd3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831981776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.1831981776
Directory /workspace/33.uart_alert_test/latest

Test location /workspace/coverage/default/33.uart_fifo_full.3388004188
Short name T259
Test name
Test status
Simulation time 26370066535 ps
CPU time 49.43 seconds
Started Jun 05 04:16:06 PM PDT 24
Finished Jun 05 04:16:57 PM PDT 24
Peak memory 200356 kb
Host smart-02b160b0-0388-43d2-bb96-bdd5072e339e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388004188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.3388004188
Directory /workspace/33.uart_fifo_full/latest

Test location /workspace/coverage/default/33.uart_fifo_overflow.3649615473
Short name T381
Test name
Test status
Simulation time 103591602285 ps
CPU time 83.49 seconds
Started Jun 05 04:16:07 PM PDT 24
Finished Jun 05 04:17:32 PM PDT 24
Peak memory 200308 kb
Host smart-19283960-4f7f-4459-acf0-c6d5dd32a967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649615473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.3649615473
Directory /workspace/33.uart_fifo_overflow/latest

Test location /workspace/coverage/default/33.uart_fifo_reset.591839810
Short name T616
Test name
Test status
Simulation time 27933049886 ps
CPU time 44.32 seconds
Started Jun 05 04:16:11 PM PDT 24
Finished Jun 05 04:16:56 PM PDT 24
Peak memory 200476 kb
Host smart-8460e6bd-4cd9-4332-998b-533d0a46b695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591839810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.591839810
Directory /workspace/33.uart_fifo_reset/latest

Test location /workspace/coverage/default/33.uart_intr.1825719493
Short name T657
Test name
Test status
Simulation time 38529714865 ps
CPU time 35.67 seconds
Started Jun 05 04:16:09 PM PDT 24
Finished Jun 05 04:16:46 PM PDT 24
Peak memory 200096 kb
Host smart-6eaa8a39-7388-4c56-9bd9-e2dd1e9410aa
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825719493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.1825719493
Directory /workspace/33.uart_intr/latest

Test location /workspace/coverage/default/33.uart_long_xfer_wo_dly.3705102616
Short name T704
Test name
Test status
Simulation time 103790496231 ps
CPU time 759.7 seconds
Started Jun 05 04:16:13 PM PDT 24
Finished Jun 05 04:28:54 PM PDT 24
Peak memory 200368 kb
Host smart-c79c82de-b8e7-4923-91c4-79fe26f4449c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3705102616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.3705102616
Directory /workspace/33.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/33.uart_loopback.2725510862
Short name T346
Test name
Test status
Simulation time 8862951753 ps
CPU time 7.77 seconds
Started Jun 05 04:16:10 PM PDT 24
Finished Jun 05 04:16:19 PM PDT 24
Peak memory 200344 kb
Host smart-3b5e6da7-aebd-4ec6-a6b6-fa9e49d16a41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725510862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_loopback.2725510862
Directory /workspace/33.uart_loopback/latest

Test location /workspace/coverage/default/33.uart_noise_filter.4196805014
Short name T716
Test name
Test status
Simulation time 177247878181 ps
CPU time 187.37 seconds
Started Jun 05 04:16:07 PM PDT 24
Finished Jun 05 04:19:16 PM PDT 24
Peak memory 200544 kb
Host smart-fbe44cd5-b338-4dc3-b099-1f2c3c2db5d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196805014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_noise_filter.4196805014
Directory /workspace/33.uart_noise_filter/latest

Test location /workspace/coverage/default/33.uart_perf.2376490324
Short name T719
Test name
Test status
Simulation time 5285005733 ps
CPU time 250.68 seconds
Started Jun 05 04:16:25 PM PDT 24
Finished Jun 05 04:20:36 PM PDT 24
Peak memory 200348 kb
Host smart-88eee1a5-6cde-47df-9988-99a147aab78e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2376490324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.2376490324
Directory /workspace/33.uart_perf/latest

Test location /workspace/coverage/default/33.uart_rx_oversample.4052310503
Short name T1017
Test name
Test status
Simulation time 2635234205 ps
CPU time 16.09 seconds
Started Jun 05 04:16:10 PM PDT 24
Finished Jun 05 04:16:27 PM PDT 24
Peak memory 198724 kb
Host smart-55266d43-0bd8-4eaf-bd43-aa28871b6a6d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4052310503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.4052310503
Directory /workspace/33.uart_rx_oversample/latest

Test location /workspace/coverage/default/33.uart_rx_parity_err.2205384542
Short name T176
Test name
Test status
Simulation time 133616200767 ps
CPU time 657.63 seconds
Started Jun 05 04:16:07 PM PDT 24
Finished Jun 05 04:27:06 PM PDT 24
Peak memory 200412 kb
Host smart-78a7db93-c1c9-4d62-9831-0dffe354c516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205384542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.2205384542
Directory /workspace/33.uart_rx_parity_err/latest

Test location /workspace/coverage/default/33.uart_rx_start_bit_filter.863839754
Short name T758
Test name
Test status
Simulation time 3281138808 ps
CPU time 1.43 seconds
Started Jun 05 04:16:07 PM PDT 24
Finished Jun 05 04:16:10 PM PDT 24
Peak memory 196452 kb
Host smart-5a674840-ad99-4445-bbd5-a6474ebe744f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863839754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.863839754
Directory /workspace/33.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/33.uart_smoke.2213139797
Short name T545
Test name
Test status
Simulation time 886907504 ps
CPU time 3.12 seconds
Started Jun 05 04:16:06 PM PDT 24
Finished Jun 05 04:16:10 PM PDT 24
Peak memory 198708 kb
Host smart-297635db-4a2a-4bfe-bbee-0ed7d44beec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213139797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_smoke.2213139797
Directory /workspace/33.uart_smoke/latest

Test location /workspace/coverage/default/33.uart_stress_all.621889100
Short name T1118
Test name
Test status
Simulation time 102861447182 ps
CPU time 824.8 seconds
Started Jun 05 04:16:27 PM PDT 24
Finished Jun 05 04:30:12 PM PDT 24
Peak memory 200476 kb
Host smart-4263e6d0-68f5-4000-981e-f0f69c165ce4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621889100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.621889100
Directory /workspace/33.uart_stress_all/latest

Test location /workspace/coverage/default/33.uart_tx_ovrd.3046485579
Short name T587
Test name
Test status
Simulation time 7060802993 ps
CPU time 9.31 seconds
Started Jun 05 04:16:07 PM PDT 24
Finished Jun 05 04:16:18 PM PDT 24
Peak memory 200356 kb
Host smart-bbf1418a-ba91-4637-89ce-a56e78ef4bb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046485579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.3046485579
Directory /workspace/33.uart_tx_ovrd/latest

Test location /workspace/coverage/default/33.uart_tx_rx.274291165
Short name T686
Test name
Test status
Simulation time 20614222940 ps
CPU time 12.85 seconds
Started Jun 05 04:16:08 PM PDT 24
Finished Jun 05 04:16:22 PM PDT 24
Peak memory 197372 kb
Host smart-2f1dc773-edc2-480e-a66f-f505e27cdb1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274291165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.274291165
Directory /workspace/33.uart_tx_rx/latest

Test location /workspace/coverage/default/34.uart_alert_test.1250879411
Short name T23
Test name
Test status
Simulation time 14639345 ps
CPU time 0.59 seconds
Started Jun 05 04:16:19 PM PDT 24
Finished Jun 05 04:16:21 PM PDT 24
Peak memory 195756 kb
Host smart-151ce8f1-5c9b-4c1c-ae2b-a3f12c7b6acd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250879411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.1250879411
Directory /workspace/34.uart_alert_test/latest

Test location /workspace/coverage/default/34.uart_fifo_full.2245428850
Short name T793
Test name
Test status
Simulation time 38228445965 ps
CPU time 31.9 seconds
Started Jun 05 04:16:17 PM PDT 24
Finished Jun 05 04:16:50 PM PDT 24
Peak memory 200424 kb
Host smart-47303529-8611-4e04-b789-5be62e9e8fed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245428850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.2245428850
Directory /workspace/34.uart_fifo_full/latest

Test location /workspace/coverage/default/34.uart_fifo_overflow.1674629181
Short name T531
Test name
Test status
Simulation time 9905139744 ps
CPU time 16.07 seconds
Started Jun 05 04:16:25 PM PDT 24
Finished Jun 05 04:16:42 PM PDT 24
Peak memory 200328 kb
Host smart-ef92f0a5-1f55-4587-a6d8-eb7bf55ea37e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674629181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.1674629181
Directory /workspace/34.uart_fifo_overflow/latest

Test location /workspace/coverage/default/34.uart_fifo_reset.264071424
Short name T507
Test name
Test status
Simulation time 15422448584 ps
CPU time 27.25 seconds
Started Jun 05 04:16:16 PM PDT 24
Finished Jun 05 04:16:44 PM PDT 24
Peak memory 200484 kb
Host smart-07f6a5db-7b94-4912-961c-c52b4daa2e23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264071424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.264071424
Directory /workspace/34.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_intr.3595098440
Short name T899
Test name
Test status
Simulation time 29602173498 ps
CPU time 47.01 seconds
Started Jun 05 04:16:18 PM PDT 24
Finished Jun 05 04:17:06 PM PDT 24
Peak memory 199388 kb
Host smart-2b1cf8a7-556d-4998-9284-24d88565656a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595098440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.3595098440
Directory /workspace/34.uart_intr/latest

Test location /workspace/coverage/default/34.uart_long_xfer_wo_dly.937809155
Short name T402
Test name
Test status
Simulation time 158352897286 ps
CPU time 259.88 seconds
Started Jun 05 04:16:16 PM PDT 24
Finished Jun 05 04:20:37 PM PDT 24
Peak memory 200416 kb
Host smart-4c7569a0-876e-4468-94af-cf2c4e0b96a8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=937809155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.937809155
Directory /workspace/34.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/34.uart_loopback.2930761060
Short name T747
Test name
Test status
Simulation time 173756808 ps
CPU time 0.75 seconds
Started Jun 05 04:16:15 PM PDT 24
Finished Jun 05 04:16:16 PM PDT 24
Peak memory 197244 kb
Host smart-b1e06da5-4695-4668-b015-d750e88e658a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930761060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_loopback.2930761060
Directory /workspace/34.uart_loopback/latest

Test location /workspace/coverage/default/34.uart_noise_filter.1264913192
Short name T803
Test name
Test status
Simulation time 34891779120 ps
CPU time 78.72 seconds
Started Jun 05 04:16:19 PM PDT 24
Finished Jun 05 04:17:39 PM PDT 24
Peak memory 200588 kb
Host smart-faa9935e-b518-48f4-b476-c94b77213475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264913192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_noise_filter.1264913192
Directory /workspace/34.uart_noise_filter/latest

Test location /workspace/coverage/default/34.uart_perf.1751813623
Short name T1039
Test name
Test status
Simulation time 25283276845 ps
CPU time 1286.45 seconds
Started Jun 05 04:16:17 PM PDT 24
Finished Jun 05 04:37:45 PM PDT 24
Peak memory 200344 kb
Host smart-0eb0c1ad-ade4-4c33-8c82-96bf824b862d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1751813623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.1751813623
Directory /workspace/34.uart_perf/latest

Test location /workspace/coverage/default/34.uart_rx_oversample.87308707
Short name T599
Test name
Test status
Simulation time 4965805571 ps
CPU time 46.76 seconds
Started Jun 05 04:16:27 PM PDT 24
Finished Jun 05 04:17:14 PM PDT 24
Peak memory 199860 kb
Host smart-abdb543a-6dee-484c-b500-6a100ef2d8f3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=87308707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.87308707
Directory /workspace/34.uart_rx_oversample/latest

Test location /workspace/coverage/default/34.uart_rx_parity_err.2519717876
Short name T1141
Test name
Test status
Simulation time 161061442052 ps
CPU time 76.97 seconds
Started Jun 05 04:16:17 PM PDT 24
Finished Jun 05 04:17:34 PM PDT 24
Peak memory 200384 kb
Host smart-dcf4abf3-21c8-48cb-bd56-016a3a79bbc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519717876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.2519717876
Directory /workspace/34.uart_rx_parity_err/latest

Test location /workspace/coverage/default/34.uart_rx_start_bit_filter.2291000550
Short name T1062
Test name
Test status
Simulation time 4380859084 ps
CPU time 7.17 seconds
Started Jun 05 04:16:14 PM PDT 24
Finished Jun 05 04:16:22 PM PDT 24
Peak memory 196732 kb
Host smart-2018bb96-1134-436a-9b62-ce990c6e34ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291000550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.2291000550
Directory /workspace/34.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/34.uart_smoke.4068407850
Short name T887
Test name
Test status
Simulation time 887566310 ps
CPU time 2.78 seconds
Started Jun 05 04:16:15 PM PDT 24
Finished Jun 05 04:16:19 PM PDT 24
Peak memory 199940 kb
Host smart-c962a570-32ef-4e03-b796-64289b9cb5aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068407850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_smoke.4068407850
Directory /workspace/34.uart_smoke/latest

Test location /workspace/coverage/default/34.uart_stress_all_with_rand_reset.40182029
Short name T760
Test name
Test status
Simulation time 364018724361 ps
CPU time 1273.19 seconds
Started Jun 05 04:16:15 PM PDT 24
Finished Jun 05 04:37:29 PM PDT 24
Peak memory 225108 kb
Host smart-d2469d1a-876a-41d0-851a-71ca9a01a880
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40182029 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 34.uart_stress_all_with_rand_reset.40182029
Directory /workspace/34.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.uart_tx_ovrd.1828430632
Short name T709
Test name
Test status
Simulation time 3455772795 ps
CPU time 2.22 seconds
Started Jun 05 04:16:24 PM PDT 24
Finished Jun 05 04:16:27 PM PDT 24
Peak memory 199480 kb
Host smart-575c2480-545b-46e1-aadd-93ebcb1960f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828430632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.1828430632
Directory /workspace/34.uart_tx_ovrd/latest

Test location /workspace/coverage/default/34.uart_tx_rx.2876735594
Short name T816
Test name
Test status
Simulation time 128441646000 ps
CPU time 52.02 seconds
Started Jun 05 04:16:15 PM PDT 24
Finished Jun 05 04:17:08 PM PDT 24
Peak memory 200388 kb
Host smart-a2489311-e82e-4854-86f2-e009767ee696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876735594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.2876735594
Directory /workspace/34.uart_tx_rx/latest

Test location /workspace/coverage/default/35.uart_alert_test.1263132907
Short name T1174
Test name
Test status
Simulation time 65969902 ps
CPU time 0.54 seconds
Started Jun 05 04:16:24 PM PDT 24
Finished Jun 05 04:16:25 PM PDT 24
Peak memory 195816 kb
Host smart-b205727b-9924-4cc9-bfc3-6e2502d62ced
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263132907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.1263132907
Directory /workspace/35.uart_alert_test/latest

Test location /workspace/coverage/default/35.uart_fifo_full.1934315235
Short name T983
Test name
Test status
Simulation time 21285984035 ps
CPU time 37.85 seconds
Started Jun 05 04:16:25 PM PDT 24
Finished Jun 05 04:17:04 PM PDT 24
Peak memory 200260 kb
Host smart-ba34fe72-cd97-4a35-b331-b8c027a6c299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934315235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.1934315235
Directory /workspace/35.uart_fifo_full/latest

Test location /workspace/coverage/default/35.uart_fifo_overflow.4036919296
Short name T142
Test name
Test status
Simulation time 184985386862 ps
CPU time 152.78 seconds
Started Jun 05 04:16:25 PM PDT 24
Finished Jun 05 04:18:58 PM PDT 24
Peak memory 200416 kb
Host smart-9e9ca4e6-f14a-4d2c-be27-f1c300d50b65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036919296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.4036919296
Directory /workspace/35.uart_fifo_overflow/latest

Test location /workspace/coverage/default/35.uart_fifo_reset.2738945711
Short name T928
Test name
Test status
Simulation time 62504216864 ps
CPU time 100.7 seconds
Started Jun 05 04:16:27 PM PDT 24
Finished Jun 05 04:18:08 PM PDT 24
Peak memory 200436 kb
Host smart-67dd7e7e-1d45-408b-96b1-909d31a6a9f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738945711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.2738945711
Directory /workspace/35.uart_fifo_reset/latest

Test location /workspace/coverage/default/35.uart_intr.630749063
Short name T941
Test name
Test status
Simulation time 13476840529 ps
CPU time 33.32 seconds
Started Jun 05 04:16:16 PM PDT 24
Finished Jun 05 04:16:50 PM PDT 24
Peak memory 200536 kb
Host smart-02fa0af4-d609-473f-8af3-69ad20a2d659
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630749063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.630749063
Directory /workspace/35.uart_intr/latest

Test location /workspace/coverage/default/35.uart_long_xfer_wo_dly.400463098
Short name T662
Test name
Test status
Simulation time 114576787145 ps
CPU time 1057.34 seconds
Started Jun 05 04:16:25 PM PDT 24
Finished Jun 05 04:34:03 PM PDT 24
Peak memory 200456 kb
Host smart-ba37ffc4-6238-40dc-bcfb-6a25656a1fae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=400463098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.400463098
Directory /workspace/35.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/35.uart_loopback.4263251800
Short name T777
Test name
Test status
Simulation time 1300769913 ps
CPU time 1.17 seconds
Started Jun 05 04:16:26 PM PDT 24
Finished Jun 05 04:16:27 PM PDT 24
Peak memory 195896 kb
Host smart-b1df4bea-48e6-4c34-b5c1-d19c29a6acf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263251800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_loopback.4263251800
Directory /workspace/35.uart_loopback/latest

Test location /workspace/coverage/default/35.uart_noise_filter.1004656655
Short name T1162
Test name
Test status
Simulation time 150931106561 ps
CPU time 67.53 seconds
Started Jun 05 04:16:17 PM PDT 24
Finished Jun 05 04:17:26 PM PDT 24
Peak memory 200616 kb
Host smart-86912f44-5b71-4655-b9b8-402456f9ddcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004656655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_noise_filter.1004656655
Directory /workspace/35.uart_noise_filter/latest

Test location /workspace/coverage/default/35.uart_perf.3822468526
Short name T827
Test name
Test status
Simulation time 20193215677 ps
CPU time 998.56 seconds
Started Jun 05 04:16:25 PM PDT 24
Finished Jun 05 04:33:04 PM PDT 24
Peak memory 200456 kb
Host smart-0b45ea18-1a3c-420d-b39d-7f90410e6cb6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3822468526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.3822468526
Directory /workspace/35.uart_perf/latest

Test location /workspace/coverage/default/35.uart_rx_oversample.1960848326
Short name T69
Test name
Test status
Simulation time 3700715321 ps
CPU time 11.92 seconds
Started Jun 05 04:16:17 PM PDT 24
Finished Jun 05 04:16:30 PM PDT 24
Peak memory 199472 kb
Host smart-3adaee6b-d652-49bb-b6de-d93a5b476469
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1960848326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.1960848326
Directory /workspace/35.uart_rx_oversample/latest

Test location /workspace/coverage/default/35.uart_rx_parity_err.1973761339
Short name T749
Test name
Test status
Simulation time 28579780242 ps
CPU time 26.12 seconds
Started Jun 05 04:16:25 PM PDT 24
Finished Jun 05 04:16:52 PM PDT 24
Peak memory 200352 kb
Host smart-52d42560-6ab5-4c2f-b7eb-5d8e829b9721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973761339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.1973761339
Directory /workspace/35.uart_rx_parity_err/latest

Test location /workspace/coverage/default/35.uart_rx_start_bit_filter.1424229543
Short name T409
Test name
Test status
Simulation time 41620532755 ps
CPU time 18.76 seconds
Started Jun 05 04:16:25 PM PDT 24
Finished Jun 05 04:16:44 PM PDT 24
Peak memory 196728 kb
Host smart-f1a1440a-5096-408d-b371-c79f883daeda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424229543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.1424229543
Directory /workspace/35.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/35.uart_smoke.1947798735
Short name T837
Test name
Test status
Simulation time 896378926 ps
CPU time 3.23 seconds
Started Jun 05 04:16:17 PM PDT 24
Finished Jun 05 04:16:20 PM PDT 24
Peak memory 199252 kb
Host smart-3dfb282f-ba01-4122-b09f-3e9aa4183fe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947798735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_smoke.1947798735
Directory /workspace/35.uart_smoke/latest

Test location /workspace/coverage/default/35.uart_stress_all.3617765042
Short name T275
Test name
Test status
Simulation time 85121256693 ps
CPU time 32.95 seconds
Started Jun 05 04:16:25 PM PDT 24
Finished Jun 05 04:16:59 PM PDT 24
Peak memory 200300 kb
Host smart-ebeb0f27-ccec-4daf-9d3e-271eaf7f3395
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617765042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.3617765042
Directory /workspace/35.uart_stress_all/latest

Test location /workspace/coverage/default/35.uart_stress_all_with_rand_reset.3351586079
Short name T480
Test name
Test status
Simulation time 41671096534 ps
CPU time 310.14 seconds
Started Jun 05 04:16:24 PM PDT 24
Finished Jun 05 04:21:35 PM PDT 24
Peak memory 214940 kb
Host smart-fa5bacdb-1583-4c9b-ba78-673910415d38
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351586079 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 35.uart_stress_all_with_rand_reset.3351586079
Directory /workspace/35.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.uart_tx_ovrd.224118618
Short name T471
Test name
Test status
Simulation time 969585599 ps
CPU time 1.42 seconds
Started Jun 05 04:16:26 PM PDT 24
Finished Jun 05 04:16:28 PM PDT 24
Peak memory 198608 kb
Host smart-4dc13ab6-c523-4be0-9f22-5b058c31a944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224118618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.224118618
Directory /workspace/35.uart_tx_ovrd/latest

Test location /workspace/coverage/default/35.uart_tx_rx.1991098312
Short name T47
Test name
Test status
Simulation time 185300404722 ps
CPU time 49 seconds
Started Jun 05 04:16:25 PM PDT 24
Finished Jun 05 04:17:15 PM PDT 24
Peak memory 200260 kb
Host smart-b430506b-7e57-4bf7-9909-81297d33b393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991098312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.1991098312
Directory /workspace/35.uart_tx_rx/latest

Test location /workspace/coverage/default/36.uart_alert_test.483072708
Short name T416
Test name
Test status
Simulation time 41855984 ps
CPU time 0.56 seconds
Started Jun 05 04:16:23 PM PDT 24
Finished Jun 05 04:16:24 PM PDT 24
Peak memory 195812 kb
Host smart-a53fcbc1-f88a-4b53-9b31-e6669a8e6b85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483072708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.483072708
Directory /workspace/36.uart_alert_test/latest

Test location /workspace/coverage/default/36.uart_fifo_full.229524728
Short name T159
Test name
Test status
Simulation time 148572523641 ps
CPU time 117.82 seconds
Started Jun 05 04:16:26 PM PDT 24
Finished Jun 05 04:18:25 PM PDT 24
Peak memory 200392 kb
Host smart-d7e187c0-1f76-455a-b7b9-74a801bb91c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229524728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.229524728
Directory /workspace/36.uart_fifo_full/latest

Test location /workspace/coverage/default/36.uart_fifo_reset.1023553083
Short name T184
Test name
Test status
Simulation time 116495797453 ps
CPU time 130.31 seconds
Started Jun 05 04:16:27 PM PDT 24
Finished Jun 05 04:18:37 PM PDT 24
Peak memory 200444 kb
Host smart-e157db2f-24b0-425e-9e2a-57ba6cc5ccd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023553083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.1023553083
Directory /workspace/36.uart_fifo_reset/latest

Test location /workspace/coverage/default/36.uart_intr.3896595678
Short name T853
Test name
Test status
Simulation time 238596285630 ps
CPU time 261.04 seconds
Started Jun 05 04:16:24 PM PDT 24
Finished Jun 05 04:20:46 PM PDT 24
Peak memory 200328 kb
Host smart-9ce35adf-8c45-4fa7-9ab9-b0655c7cb515
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896595678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.3896595678
Directory /workspace/36.uart_intr/latest

Test location /workspace/coverage/default/36.uart_long_xfer_wo_dly.1355436719
Short name T552
Test name
Test status
Simulation time 101263866604 ps
CPU time 752.84 seconds
Started Jun 05 04:16:24 PM PDT 24
Finished Jun 05 04:28:57 PM PDT 24
Peak memory 200444 kb
Host smart-ef1348fa-1599-47a8-96fa-aa6b3370ada4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1355436719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.1355436719
Directory /workspace/36.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/36.uart_loopback.2740423531
Short name T353
Test name
Test status
Simulation time 1508647726 ps
CPU time 0.75 seconds
Started Jun 05 04:16:24 PM PDT 24
Finished Jun 05 04:16:25 PM PDT 24
Peak memory 196492 kb
Host smart-f883948c-2960-405f-bcf6-6748bf01d5c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740423531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_loopback.2740423531
Directory /workspace/36.uart_loopback/latest

Test location /workspace/coverage/default/36.uart_noise_filter.855542406
Short name T287
Test name
Test status
Simulation time 121738871766 ps
CPU time 104.93 seconds
Started Jun 05 04:16:25 PM PDT 24
Finished Jun 05 04:18:11 PM PDT 24
Peak memory 208560 kb
Host smart-b6f4d3c1-796d-4642-93b8-44d9ebc6bd26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855542406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_noise_filter.855542406
Directory /workspace/36.uart_noise_filter/latest

Test location /workspace/coverage/default/36.uart_perf.3946087008
Short name T70
Test name
Test status
Simulation time 13431393939 ps
CPU time 190.5 seconds
Started Jun 05 04:16:28 PM PDT 24
Finished Jun 05 04:19:39 PM PDT 24
Peak memory 200372 kb
Host smart-5bb07e4c-c27b-46b1-8d6e-da95f9f05edc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3946087008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.3946087008
Directory /workspace/36.uart_perf/latest

Test location /workspace/coverage/default/36.uart_rx_oversample.1097404980
Short name T836
Test name
Test status
Simulation time 5279251101 ps
CPU time 44.09 seconds
Started Jun 05 04:16:26 PM PDT 24
Finished Jun 05 04:17:11 PM PDT 24
Peak memory 199528 kb
Host smart-bfc6cc5d-3b71-425b-95af-a1876680c770
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1097404980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.1097404980
Directory /workspace/36.uart_rx_oversample/latest

Test location /workspace/coverage/default/36.uart_rx_parity_err.3848195700
Short name T332
Test name
Test status
Simulation time 125126237382 ps
CPU time 103.75 seconds
Started Jun 05 04:16:25 PM PDT 24
Finished Jun 05 04:18:10 PM PDT 24
Peak memory 200244 kb
Host smart-f0b7ec6e-2827-4a07-8aa7-4748bd3ea7dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848195700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.3848195700
Directory /workspace/36.uart_rx_parity_err/latest

Test location /workspace/coverage/default/36.uart_rx_start_bit_filter.1629354128
Short name T520
Test name
Test status
Simulation time 5071979414 ps
CPU time 3.71 seconds
Started Jun 05 04:16:28 PM PDT 24
Finished Jun 05 04:16:32 PM PDT 24
Peak memory 196436 kb
Host smart-0d8db1f9-6fcd-4a51-b0e0-b5ee2fa9bfc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629354128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.1629354128
Directory /workspace/36.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/36.uart_smoke.1995431579
Short name T681
Test name
Test status
Simulation time 910335965 ps
CPU time 2.14 seconds
Started Jun 05 04:16:26 PM PDT 24
Finished Jun 05 04:16:28 PM PDT 24
Peak memory 200296 kb
Host smart-8eab6d9f-9420-4e2e-918a-61c96718b919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995431579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_smoke.1995431579
Directory /workspace/36.uart_smoke/latest

Test location /workspace/coverage/default/36.uart_stress_all.2839552833
Short name T266
Test name
Test status
Simulation time 355895092427 ps
CPU time 641.33 seconds
Started Jun 05 04:16:25 PM PDT 24
Finished Jun 05 04:27:08 PM PDT 24
Peak memory 200476 kb
Host smart-a788881f-b730-4691-bb75-6863998a7324
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839552833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.2839552833
Directory /workspace/36.uart_stress_all/latest

Test location /workspace/coverage/default/36.uart_stress_all_with_rand_reset.203551060
Short name T604
Test name
Test status
Simulation time 36343942130 ps
CPU time 516.03 seconds
Started Jun 05 04:16:25 PM PDT 24
Finished Jun 05 04:25:02 PM PDT 24
Peak memory 216456 kb
Host smart-c3db0b53-3550-4366-8886-0adcddc8c74f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203551060 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 36.uart_stress_all_with_rand_reset.203551060
Directory /workspace/36.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.uart_tx_ovrd.2773996465
Short name T683
Test name
Test status
Simulation time 7061839625 ps
CPU time 19.31 seconds
Started Jun 05 04:16:26 PM PDT 24
Finished Jun 05 04:16:46 PM PDT 24
Peak memory 200320 kb
Host smart-5da7a3bb-b1ae-44bd-99f8-ba0617f25136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773996465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.2773996465
Directory /workspace/36.uart_tx_ovrd/latest

Test location /workspace/coverage/default/36.uart_tx_rx.1655743628
Short name T426
Test name
Test status
Simulation time 76941337764 ps
CPU time 33.25 seconds
Started Jun 05 04:16:25 PM PDT 24
Finished Jun 05 04:16:59 PM PDT 24
Peak memory 200432 kb
Host smart-f70df4e9-f3b5-43c3-b7ec-a7d154aa1e90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655743628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.1655743628
Directory /workspace/36.uart_tx_rx/latest

Test location /workspace/coverage/default/37.uart_alert_test.312910000
Short name T1156
Test name
Test status
Simulation time 38291669 ps
CPU time 0.53 seconds
Started Jun 05 04:16:36 PM PDT 24
Finished Jun 05 04:16:38 PM PDT 24
Peak memory 195800 kb
Host smart-a8f3ef4a-7a19-4806-88fe-ec1e1115ad5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312910000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.312910000
Directory /workspace/37.uart_alert_test/latest

Test location /workspace/coverage/default/37.uart_fifo_full.3700193957
Short name T845
Test name
Test status
Simulation time 182166511311 ps
CPU time 82.13 seconds
Started Jun 05 04:16:26 PM PDT 24
Finished Jun 05 04:17:49 PM PDT 24
Peak memory 200464 kb
Host smart-bffd2aa4-2cf2-4baf-be25-9797add05a9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700193957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.3700193957
Directory /workspace/37.uart_fifo_full/latest

Test location /workspace/coverage/default/37.uart_fifo_overflow.424273022
Short name T560
Test name
Test status
Simulation time 108890185555 ps
CPU time 174.81 seconds
Started Jun 05 04:16:33 PM PDT 24
Finished Jun 05 04:19:28 PM PDT 24
Peak memory 200360 kb
Host smart-8b855b21-c855-4a67-b5de-054eb88e68d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424273022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.424273022
Directory /workspace/37.uart_fifo_overflow/latest

Test location /workspace/coverage/default/37.uart_fifo_reset.4124356722
Short name T973
Test name
Test status
Simulation time 112854848344 ps
CPU time 188.91 seconds
Started Jun 05 04:16:36 PM PDT 24
Finished Jun 05 04:19:46 PM PDT 24
Peak memory 200320 kb
Host smart-4c104d3f-3810-4e6e-961f-99815c6f3f01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124356722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.4124356722
Directory /workspace/37.uart_fifo_reset/latest

Test location /workspace/coverage/default/37.uart_intr.1720634475
Short name T12
Test name
Test status
Simulation time 54960153434 ps
CPU time 51.68 seconds
Started Jun 05 04:16:37 PM PDT 24
Finished Jun 05 04:17:30 PM PDT 24
Peak memory 200460 kb
Host smart-15cbdd82-9da1-4b25-bd36-e70b11fe4e1b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720634475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.1720634475
Directory /workspace/37.uart_intr/latest

Test location /workspace/coverage/default/37.uart_long_xfer_wo_dly.4002012995
Short name T859
Test name
Test status
Simulation time 176970605027 ps
CPU time 76.8 seconds
Started Jun 05 04:16:34 PM PDT 24
Finished Jun 05 04:17:52 PM PDT 24
Peak memory 200444 kb
Host smart-b1cfd356-5bd1-4519-ae76-df9576ce5212
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4002012995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.4002012995
Directory /workspace/37.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/37.uart_loopback.208939275
Short name T1010
Test name
Test status
Simulation time 2626908249 ps
CPU time 4.6 seconds
Started Jun 05 04:16:34 PM PDT 24
Finished Jun 05 04:16:40 PM PDT 24
Peak memory 196824 kb
Host smart-938e4e69-6459-4b2b-8375-40ec5282c41f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208939275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_loopback.208939275
Directory /workspace/37.uart_loopback/latest

Test location /workspace/coverage/default/37.uart_noise_filter.1472993717
Short name T927
Test name
Test status
Simulation time 59015028723 ps
CPU time 107.1 seconds
Started Jun 05 04:16:34 PM PDT 24
Finished Jun 05 04:18:22 PM PDT 24
Peak memory 199856 kb
Host smart-127f89e5-60e5-439c-b47f-6b147a70e71f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472993717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_noise_filter.1472993717
Directory /workspace/37.uart_noise_filter/latest

Test location /workspace/coverage/default/37.uart_perf.2535481254
Short name T106
Test name
Test status
Simulation time 14810549364 ps
CPU time 213.19 seconds
Started Jun 05 04:16:35 PM PDT 24
Finished Jun 05 04:20:09 PM PDT 24
Peak memory 200380 kb
Host smart-0af8d6f1-a6d3-4c04-b9dc-d94ae43738ae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2535481254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.2535481254
Directory /workspace/37.uart_perf/latest

Test location /workspace/coverage/default/37.uart_rx_oversample.524452652
Short name T731
Test name
Test status
Simulation time 7863663275 ps
CPU time 69.54 seconds
Started Jun 05 04:16:35 PM PDT 24
Finished Jun 05 04:17:45 PM PDT 24
Peak memory 199212 kb
Host smart-f734b4af-06ae-4a0e-a5cd-8d0e88fcf5f5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=524452652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.524452652
Directory /workspace/37.uart_rx_oversample/latest

Test location /workspace/coverage/default/37.uart_rx_parity_err.1956106459
Short name T1045
Test name
Test status
Simulation time 38805291638 ps
CPU time 42.95 seconds
Started Jun 05 04:16:41 PM PDT 24
Finished Jun 05 04:17:25 PM PDT 24
Peak memory 200440 kb
Host smart-8df259ad-15d8-41f7-a9fc-e56b79340bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956106459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.1956106459
Directory /workspace/37.uart_rx_parity_err/latest

Test location /workspace/coverage/default/37.uart_rx_start_bit_filter.720214370
Short name T412
Test name
Test status
Simulation time 3228293243 ps
CPU time 2.03 seconds
Started Jun 05 04:16:36 PM PDT 24
Finished Jun 05 04:16:39 PM PDT 24
Peak memory 196716 kb
Host smart-496abe13-82d5-471a-a859-65fc645cb6a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720214370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.720214370
Directory /workspace/37.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/37.uart_smoke.404260333
Short name T437
Test name
Test status
Simulation time 942190212 ps
CPU time 2.58 seconds
Started Jun 05 04:16:25 PM PDT 24
Finished Jun 05 04:16:28 PM PDT 24
Peak memory 199984 kb
Host smart-3a01939f-104a-4ef0-80f0-ef0074d2ef43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404260333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_smoke.404260333
Directory /workspace/37.uart_smoke/latest

Test location /workspace/coverage/default/37.uart_stress_all.1132499041
Short name T1061
Test name
Test status
Simulation time 297065986930 ps
CPU time 279.06 seconds
Started Jun 05 04:16:35 PM PDT 24
Finished Jun 05 04:21:15 PM PDT 24
Peak memory 200448 kb
Host smart-a7577a3b-8afc-49f4-a526-36221a8bff54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132499041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.1132499041
Directory /workspace/37.uart_stress_all/latest

Test location /workspace/coverage/default/37.uart_stress_all_with_rand_reset.1086880245
Short name T169
Test name
Test status
Simulation time 47719279803 ps
CPU time 140.76 seconds
Started Jun 05 04:16:33 PM PDT 24
Finished Jun 05 04:18:55 PM PDT 24
Peak memory 208848 kb
Host smart-84a02011-5717-4957-9f12-7de1a48d9d22
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086880245 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 37.uart_stress_all_with_rand_reset.1086880245
Directory /workspace/37.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.uart_tx_ovrd.344860101
Short name T535
Test name
Test status
Simulation time 1800110587 ps
CPU time 4.07 seconds
Started Jun 05 04:16:34 PM PDT 24
Finished Jun 05 04:16:39 PM PDT 24
Peak memory 198228 kb
Host smart-93931553-0b22-4515-bf4f-90068cf023b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344860101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.344860101
Directory /workspace/37.uart_tx_ovrd/latest

Test location /workspace/coverage/default/37.uart_tx_rx.946674129
Short name T450
Test name
Test status
Simulation time 35286844874 ps
CPU time 35.4 seconds
Started Jun 05 04:16:28 PM PDT 24
Finished Jun 05 04:17:04 PM PDT 24
Peak memory 200376 kb
Host smart-dea07059-bc10-4dc8-a5f8-af36cda22130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946674129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.946674129
Directory /workspace/37.uart_tx_rx/latest

Test location /workspace/coverage/default/38.uart_alert_test.831993033
Short name T817
Test name
Test status
Simulation time 15943422 ps
CPU time 0.56 seconds
Started Jun 05 04:16:44 PM PDT 24
Finished Jun 05 04:16:46 PM PDT 24
Peak memory 195812 kb
Host smart-54dad1d0-1b9d-409e-b953-4ba88f81c8bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831993033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.831993033
Directory /workspace/38.uart_alert_test/latest

Test location /workspace/coverage/default/38.uart_fifo_full.558303697
Short name T1130
Test name
Test status
Simulation time 15106108233 ps
CPU time 13.82 seconds
Started Jun 05 04:16:37 PM PDT 24
Finished Jun 05 04:16:52 PM PDT 24
Peak memory 200368 kb
Host smart-c89dcbcd-4c5d-4711-91e0-e69c82af3136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558303697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.558303697
Directory /workspace/38.uart_fifo_full/latest

Test location /workspace/coverage/default/38.uart_fifo_overflow.3089782139
Short name T1175
Test name
Test status
Simulation time 47658636422 ps
CPU time 22.65 seconds
Started Jun 05 04:16:34 PM PDT 24
Finished Jun 05 04:16:58 PM PDT 24
Peak memory 200396 kb
Host smart-73ac30df-9a3b-4c8e-aeca-a9f270ff05bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089782139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.3089782139
Directory /workspace/38.uart_fifo_overflow/latest

Test location /workspace/coverage/default/38.uart_fifo_reset.4172140158
Short name T324
Test name
Test status
Simulation time 104201182908 ps
CPU time 72.67 seconds
Started Jun 05 04:16:35 PM PDT 24
Finished Jun 05 04:17:49 PM PDT 24
Peak memory 200120 kb
Host smart-8adf4a48-9b2a-4123-af45-98252d9da913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172140158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.4172140158
Directory /workspace/38.uart_fifo_reset/latest

Test location /workspace/coverage/default/38.uart_intr.10388729
Short name T750
Test name
Test status
Simulation time 185511295875 ps
CPU time 390.51 seconds
Started Jun 05 04:16:36 PM PDT 24
Finished Jun 05 04:23:07 PM PDT 24
Peak memory 200132 kb
Host smart-1adb8599-94ad-4511-a1fc-b2672ae8e0cb
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10388729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.10388729
Directory /workspace/38.uart_intr/latest

Test location /workspace/coverage/default/38.uart_long_xfer_wo_dly.185514752
Short name T808
Test name
Test status
Simulation time 34229374354 ps
CPU time 160 seconds
Started Jun 05 04:16:34 PM PDT 24
Finished Jun 05 04:19:15 PM PDT 24
Peak memory 200420 kb
Host smart-349c05db-4195-4bef-8562-fc868237bbe5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=185514752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.185514752
Directory /workspace/38.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/38.uart_loopback.1779950503
Short name T977
Test name
Test status
Simulation time 2288221053 ps
CPU time 4.1 seconds
Started Jun 05 04:16:37 PM PDT 24
Finished Jun 05 04:16:42 PM PDT 24
Peak memory 198992 kb
Host smart-2e0f5d1b-97e0-41bf-8b4c-1f81841b5388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779950503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_loopback.1779950503
Directory /workspace/38.uart_loopback/latest

Test location /workspace/coverage/default/38.uart_noise_filter.2964549791
Short name T1133
Test name
Test status
Simulation time 53205201580 ps
CPU time 119.3 seconds
Started Jun 05 04:16:38 PM PDT 24
Finished Jun 05 04:18:38 PM PDT 24
Peak memory 200568 kb
Host smart-f9e1a141-022f-4875-b439-530b93e4789b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964549791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_noise_filter.2964549791
Directory /workspace/38.uart_noise_filter/latest

Test location /workspace/coverage/default/38.uart_perf.1296816024
Short name T802
Test name
Test status
Simulation time 3391507241 ps
CPU time 198.68 seconds
Started Jun 05 04:16:34 PM PDT 24
Finished Jun 05 04:19:53 PM PDT 24
Peak memory 200404 kb
Host smart-bc4dcd03-163e-4383-93ca-89264e17b905
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1296816024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.1296816024
Directory /workspace/38.uart_perf/latest

Test location /workspace/coverage/default/38.uart_rx_oversample.4184602150
Short name T109
Test name
Test status
Simulation time 7100593154 ps
CPU time 10.83 seconds
Started Jun 05 04:16:33 PM PDT 24
Finished Jun 05 04:16:45 PM PDT 24
Peak memory 199848 kb
Host smart-bdc49ccd-151a-4fa7-9e52-511c91cddbc6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4184602150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.4184602150
Directory /workspace/38.uart_rx_oversample/latest

Test location /workspace/coverage/default/38.uart_rx_parity_err.725634860
Short name T183
Test name
Test status
Simulation time 34968519651 ps
CPU time 59.35 seconds
Started Jun 05 04:16:35 PM PDT 24
Finished Jun 05 04:17:35 PM PDT 24
Peak memory 200344 kb
Host smart-ddd94a07-273a-4db4-a984-bba5b362fd59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725634860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.725634860
Directory /workspace/38.uart_rx_parity_err/latest

Test location /workspace/coverage/default/38.uart_rx_start_bit_filter.3447858236
Short name T68
Test name
Test status
Simulation time 4906413785 ps
CPU time 2.41 seconds
Started Jun 05 04:16:41 PM PDT 24
Finished Jun 05 04:16:44 PM PDT 24
Peak memory 196724 kb
Host smart-57bc023b-378e-4bae-82ee-c8c5426cb98f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447858236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.3447858236
Directory /workspace/38.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/38.uart_smoke.404033087
Short name T791
Test name
Test status
Simulation time 11569472476 ps
CPU time 25.3 seconds
Started Jun 05 04:16:33 PM PDT 24
Finished Jun 05 04:16:59 PM PDT 24
Peak memory 199992 kb
Host smart-8afa74a5-2325-45b1-8e66-6eee3d813bac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404033087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_smoke.404033087
Directory /workspace/38.uart_smoke/latest

Test location /workspace/coverage/default/38.uart_stress_all_with_rand_reset.1369465361
Short name T363
Test name
Test status
Simulation time 29571082630 ps
CPU time 755.83 seconds
Started Jun 05 04:16:35 PM PDT 24
Finished Jun 05 04:29:12 PM PDT 24
Peak memory 215004 kb
Host smart-477b238c-1ada-4161-a85c-f6e26c89cbed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369465361 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 38.uart_stress_all_with_rand_reset.1369465361
Directory /workspace/38.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.uart_tx_ovrd.1200400977
Short name T415
Test name
Test status
Simulation time 2140346484 ps
CPU time 1.64 seconds
Started Jun 05 04:16:35 PM PDT 24
Finished Jun 05 04:16:37 PM PDT 24
Peak memory 198608 kb
Host smart-7f63ff83-8ae4-4c7a-88e1-d5b713a2a515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200400977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.1200400977
Directory /workspace/38.uart_tx_ovrd/latest

Test location /workspace/coverage/default/38.uart_tx_rx.595212915
Short name T776
Test name
Test status
Simulation time 6900427185 ps
CPU time 11.84 seconds
Started Jun 05 04:16:34 PM PDT 24
Finished Jun 05 04:16:47 PM PDT 24
Peak memory 200180 kb
Host smart-cfd1cdee-a99b-4de7-9fb1-55846ccb18fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595212915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.595212915
Directory /workspace/38.uart_tx_rx/latest

Test location /workspace/coverage/default/39.uart_alert_test.1913067352
Short name T728
Test name
Test status
Simulation time 39811329 ps
CPU time 0.57 seconds
Started Jun 05 04:16:44 PM PDT 24
Finished Jun 05 04:16:45 PM PDT 24
Peak memory 195812 kb
Host smart-139384c2-4b82-4bce-b9e3-36e4ce8316d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913067352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.1913067352
Directory /workspace/39.uart_alert_test/latest

Test location /workspace/coverage/default/39.uart_fifo_full.1542587013
Short name T871
Test name
Test status
Simulation time 21459815748 ps
CPU time 44.09 seconds
Started Jun 05 04:16:42 PM PDT 24
Finished Jun 05 04:17:27 PM PDT 24
Peak memory 200456 kb
Host smart-d48717b1-186e-4597-b2a9-60eb3005becd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542587013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.1542587013
Directory /workspace/39.uart_fifo_full/latest

Test location /workspace/coverage/default/39.uart_fifo_overflow.2035751151
Short name T48
Test name
Test status
Simulation time 45477379650 ps
CPU time 24.34 seconds
Started Jun 05 04:16:44 PM PDT 24
Finished Jun 05 04:17:09 PM PDT 24
Peak memory 198684 kb
Host smart-e3ae21cc-2b7e-4245-8eb2-504c2fdab49d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035751151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.2035751151
Directory /workspace/39.uart_fifo_overflow/latest

Test location /workspace/coverage/default/39.uart_fifo_reset.3979099107
Short name T1056
Test name
Test status
Simulation time 45359062956 ps
CPU time 76.11 seconds
Started Jun 05 04:16:42 PM PDT 24
Finished Jun 05 04:17:59 PM PDT 24
Peak memory 200360 kb
Host smart-75fcdb13-1d1b-47b0-871c-29eb466bf615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979099107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.3979099107
Directory /workspace/39.uart_fifo_reset/latest

Test location /workspace/coverage/default/39.uart_intr.2987733606
Short name T717
Test name
Test status
Simulation time 6504647570 ps
CPU time 14.85 seconds
Started Jun 05 04:16:42 PM PDT 24
Finished Jun 05 04:16:58 PM PDT 24
Peak memory 200040 kb
Host smart-21dbcc2e-b32e-4789-b071-5d17ebef009e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987733606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.2987733606
Directory /workspace/39.uart_intr/latest

Test location /workspace/coverage/default/39.uart_long_xfer_wo_dly.3285351928
Short name T944
Test name
Test status
Simulation time 59107332481 ps
CPU time 166.37 seconds
Started Jun 05 04:16:40 PM PDT 24
Finished Jun 05 04:19:27 PM PDT 24
Peak memory 200484 kb
Host smart-6fc508db-5d1c-4d2f-b168-033bdcb62acc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3285351928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.3285351928
Directory /workspace/39.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/39.uart_loopback.1212183827
Short name T368
Test name
Test status
Simulation time 1146645125 ps
CPU time 2.36 seconds
Started Jun 05 04:16:44 PM PDT 24
Finished Jun 05 04:16:48 PM PDT 24
Peak memory 196504 kb
Host smart-0a782b87-d1d4-40df-bac6-5dce51e0adb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212183827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_loopback.1212183827
Directory /workspace/39.uart_loopback/latest

Test location /workspace/coverage/default/39.uart_noise_filter.3959047099
Short name T735
Test name
Test status
Simulation time 86485051418 ps
CPU time 54.24 seconds
Started Jun 05 04:16:44 PM PDT 24
Finished Jun 05 04:17:39 PM PDT 24
Peak memory 208584 kb
Host smart-9c4becc8-cad9-4dfc-bb02-0cce4b9c8af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959047099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_noise_filter.3959047099
Directory /workspace/39.uart_noise_filter/latest

Test location /workspace/coverage/default/39.uart_perf.4058839120
Short name T502
Test name
Test status
Simulation time 30239683943 ps
CPU time 363.58 seconds
Started Jun 05 04:16:43 PM PDT 24
Finished Jun 05 04:22:48 PM PDT 24
Peak memory 200384 kb
Host smart-586dafc4-a25b-4725-a02e-851daa2b8b8b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4058839120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.4058839120
Directory /workspace/39.uart_perf/latest

Test location /workspace/coverage/default/39.uart_rx_oversample.1096595916
Short name T44
Test name
Test status
Simulation time 4504887093 ps
CPU time 17 seconds
Started Jun 05 04:16:43 PM PDT 24
Finished Jun 05 04:17:01 PM PDT 24
Peak memory 199756 kb
Host smart-353436fe-46e4-4628-95fc-3a7d949aa576
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1096595916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.1096595916
Directory /workspace/39.uart_rx_oversample/latest

Test location /workspace/coverage/default/39.uart_rx_parity_err.2363733829
Short name T824
Test name
Test status
Simulation time 8540224150 ps
CPU time 6.66 seconds
Started Jun 05 04:16:42 PM PDT 24
Finished Jun 05 04:16:49 PM PDT 24
Peak memory 199920 kb
Host smart-d191d625-26f6-4fb4-962f-8544b8118dd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363733829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.2363733829
Directory /workspace/39.uart_rx_parity_err/latest

Test location /workspace/coverage/default/39.uart_rx_start_bit_filter.1074466699
Short name T652
Test name
Test status
Simulation time 3753912844 ps
CPU time 6.2 seconds
Started Jun 05 04:16:42 PM PDT 24
Finished Jun 05 04:16:50 PM PDT 24
Peak memory 196448 kb
Host smart-5530505a-6ccf-4f34-a5d4-afc2cbee1364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074466699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.1074466699
Directory /workspace/39.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/39.uart_smoke.2174887908
Short name T400
Test name
Test status
Simulation time 104708060 ps
CPU time 0.98 seconds
Started Jun 05 04:16:43 PM PDT 24
Finished Jun 05 04:16:45 PM PDT 24
Peak memory 198528 kb
Host smart-da599b93-a3ce-4df8-8f95-e47ad4f1ae4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174887908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_smoke.2174887908
Directory /workspace/39.uart_smoke/latest

Test location /workspace/coverage/default/39.uart_stress_all.3729402282
Short name T1132
Test name
Test status
Simulation time 208341460328 ps
CPU time 266.45 seconds
Started Jun 05 04:16:42 PM PDT 24
Finished Jun 05 04:21:10 PM PDT 24
Peak memory 200448 kb
Host smart-3cf769a3-2114-4a2b-9076-4264d43fd613
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729402282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.3729402282
Directory /workspace/39.uart_stress_all/latest

Test location /workspace/coverage/default/39.uart_stress_all_with_rand_reset.778680811
Short name T689
Test name
Test status
Simulation time 14058877249 ps
CPU time 212.07 seconds
Started Jun 05 04:16:47 PM PDT 24
Finished Jun 05 04:20:20 PM PDT 24
Peak memory 215960 kb
Host smart-501eb78c-5dc9-42f9-93fd-65073eda9c05
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778680811 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 39.uart_stress_all_with_rand_reset.778680811
Directory /workspace/39.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.uart_tx_ovrd.122188818
Short name T564
Test name
Test status
Simulation time 1257056603 ps
CPU time 2.18 seconds
Started Jun 05 04:16:41 PM PDT 24
Finished Jun 05 04:16:45 PM PDT 24
Peak memory 198848 kb
Host smart-0006478e-1507-4efe-809a-d728c367e67a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122188818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.122188818
Directory /workspace/39.uart_tx_ovrd/latest

Test location /workspace/coverage/default/39.uart_tx_rx.75501177
Short name T5
Test name
Test status
Simulation time 205916441013 ps
CPU time 108.9 seconds
Started Jun 05 04:16:42 PM PDT 24
Finished Jun 05 04:18:32 PM PDT 24
Peak memory 200444 kb
Host smart-beeff6e6-c65c-4f01-98d4-45c2c4e4e06d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75501177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.75501177
Directory /workspace/39.uart_tx_rx/latest

Test location /workspace/coverage/default/4.uart_alert_test.1604320780
Short name T376
Test name
Test status
Simulation time 69839614 ps
CPU time 0.52 seconds
Started Jun 05 04:14:59 PM PDT 24
Finished Jun 05 04:15:00 PM PDT 24
Peak memory 194776 kb
Host smart-82b89d09-8ace-4364-919a-53211cc76ebd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604320780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.1604320780
Directory /workspace/4.uart_alert_test/latest

Test location /workspace/coverage/default/4.uart_fifo_full.471059953
Short name T774
Test name
Test status
Simulation time 107845516236 ps
CPU time 101.34 seconds
Started Jun 05 04:14:41 PM PDT 24
Finished Jun 05 04:16:23 PM PDT 24
Peak memory 200440 kb
Host smart-baad98ed-b4c6-426a-b549-0814f2428635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471059953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.471059953
Directory /workspace/4.uart_fifo_full/latest

Test location /workspace/coverage/default/4.uart_fifo_overflow.1701108792
Short name T89
Test name
Test status
Simulation time 24213370702 ps
CPU time 10.4 seconds
Started Jun 05 04:14:52 PM PDT 24
Finished Jun 05 04:15:03 PM PDT 24
Peak memory 200420 kb
Host smart-34eea262-a98d-4a4d-a2d1-5e8c0ae6c5a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701108792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.1701108792
Directory /workspace/4.uart_fifo_overflow/latest

Test location /workspace/coverage/default/4.uart_fifo_reset.3736208490
Short name T249
Test name
Test status
Simulation time 25978513637 ps
CPU time 42.24 seconds
Started Jun 05 04:14:47 PM PDT 24
Finished Jun 05 04:15:35 PM PDT 24
Peak memory 200388 kb
Host smart-31f54304-2e08-4610-a9be-ed709d25031f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736208490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.3736208490
Directory /workspace/4.uart_fifo_reset/latest

Test location /workspace/coverage/default/4.uart_intr.3906989455
Short name T923
Test name
Test status
Simulation time 50668509968 ps
CPU time 13.76 seconds
Started Jun 05 04:15:05 PM PDT 24
Finished Jun 05 04:15:20 PM PDT 24
Peak memory 200408 kb
Host smart-4d65f492-8423-4b3a-8e8e-14211a86bfda
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906989455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.3906989455
Directory /workspace/4.uart_intr/latest

Test location /workspace/coverage/default/4.uart_long_xfer_wo_dly.1658897795
Short name T514
Test name
Test status
Simulation time 56543801217 ps
CPU time 297.33 seconds
Started Jun 05 04:15:02 PM PDT 24
Finished Jun 05 04:20:00 PM PDT 24
Peak memory 200512 kb
Host smart-7be299d6-9f19-4c06-b4d4-b7bb327f428d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1658897795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.1658897795
Directory /workspace/4.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/4.uart_loopback.3087014327
Short name T950
Test name
Test status
Simulation time 404687293 ps
CPU time 1.03 seconds
Started Jun 05 04:14:51 PM PDT 24
Finished Jun 05 04:14:53 PM PDT 24
Peak memory 197668 kb
Host smart-2bca3146-57c4-4d7e-a438-56d25b135121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087014327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_loopback.3087014327
Directory /workspace/4.uart_loopback/latest

Test location /workspace/coverage/default/4.uart_noise_filter.1394677348
Short name T1101
Test name
Test status
Simulation time 38329895876 ps
CPU time 70.95 seconds
Started Jun 05 04:14:49 PM PDT 24
Finished Jun 05 04:16:01 PM PDT 24
Peak memory 198436 kb
Host smart-6a7d1a7f-e506-4796-b44b-a981b924783a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394677348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_noise_filter.1394677348
Directory /workspace/4.uart_noise_filter/latest

Test location /workspace/coverage/default/4.uart_perf.1559247371
Short name T330
Test name
Test status
Simulation time 4332927188 ps
CPU time 47.28 seconds
Started Jun 05 04:14:52 PM PDT 24
Finished Jun 05 04:15:40 PM PDT 24
Peak memory 200392 kb
Host smart-71bc52eb-16d3-4f30-9f8b-8d15675cae5d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1559247371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.1559247371
Directory /workspace/4.uart_perf/latest

Test location /workspace/coverage/default/4.uart_rx_oversample.1325384455
Short name T594
Test name
Test status
Simulation time 6685434653 ps
CPU time 16.07 seconds
Started Jun 05 04:14:47 PM PDT 24
Finished Jun 05 04:15:08 PM PDT 24
Peak memory 198652 kb
Host smart-c50cd7db-94f9-4c48-9b77-4f39ed2dbab6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1325384455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.1325384455
Directory /workspace/4.uart_rx_oversample/latest

Test location /workspace/coverage/default/4.uart_rx_parity_err.1488623498
Short name T1086
Test name
Test status
Simulation time 115307214769 ps
CPU time 109.48 seconds
Started Jun 05 04:15:07 PM PDT 24
Finished Jun 05 04:16:57 PM PDT 24
Peak memory 200404 kb
Host smart-ed4f47e9-03a9-4154-8739-3d25029f025a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488623498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.1488623498
Directory /workspace/4.uart_rx_parity_err/latest

Test location /workspace/coverage/default/4.uart_rx_start_bit_filter.998673844
Short name T524
Test name
Test status
Simulation time 39813382194 ps
CPU time 63.51 seconds
Started Jun 05 04:15:02 PM PDT 24
Finished Jun 05 04:16:06 PM PDT 24
Peak memory 196120 kb
Host smart-85fb16f8-830a-407e-9d87-34b72b881bd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998673844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.998673844
Directory /workspace/4.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/4.uart_sec_cm.47704232
Short name T99
Test name
Test status
Simulation time 381347951 ps
CPU time 0.74 seconds
Started Jun 05 04:14:50 PM PDT 24
Finished Jun 05 04:14:52 PM PDT 24
Peak memory 218756 kb
Host smart-330dcd44-45b0-4192-94a5-69f61c95f7fb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47704232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.47704232
Directory /workspace/4.uart_sec_cm/latest

Test location /workspace/coverage/default/4.uart_smoke.871389553
Short name T1054
Test name
Test status
Simulation time 436805853 ps
CPU time 1.59 seconds
Started Jun 05 04:14:43 PM PDT 24
Finished Jun 05 04:14:45 PM PDT 24
Peak memory 199260 kb
Host smart-145db73f-dabd-4316-88ad-3e3a203690af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871389553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_smoke.871389553
Directory /workspace/4.uart_smoke/latest

Test location /workspace/coverage/default/4.uart_stress_all.2098767460
Short name T838
Test name
Test status
Simulation time 429094125252 ps
CPU time 317.89 seconds
Started Jun 05 04:14:46 PM PDT 24
Finished Jun 05 04:20:05 PM PDT 24
Peak memory 200460 kb
Host smart-d5f65da7-5f82-4d70-8cf6-ca11f2228c44
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098767460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.2098767460
Directory /workspace/4.uart_stress_all/latest

Test location /workspace/coverage/default/4.uart_tx_ovrd.2320042409
Short name T568
Test name
Test status
Simulation time 458744929 ps
CPU time 1.25 seconds
Started Jun 05 04:14:46 PM PDT 24
Finished Jun 05 04:14:47 PM PDT 24
Peak memory 198792 kb
Host smart-9d4f0c43-e3f6-4047-80f0-66806210c8ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320042409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.2320042409
Directory /workspace/4.uart_tx_ovrd/latest

Test location /workspace/coverage/default/4.uart_tx_rx.642269866
Short name T423
Test name
Test status
Simulation time 161916063731 ps
CPU time 71.72 seconds
Started Jun 05 04:14:38 PM PDT 24
Finished Jun 05 04:15:50 PM PDT 24
Peak memory 200376 kb
Host smart-efe2b579-e6dd-43bc-bd37-7ab1edf7a606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642269866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.642269866
Directory /workspace/4.uart_tx_rx/latest

Test location /workspace/coverage/default/40.uart_alert_test.2179252740
Short name T360
Test name
Test status
Simulation time 23627430 ps
CPU time 0.6 seconds
Started Jun 05 04:16:47 PM PDT 24
Finished Jun 05 04:16:49 PM PDT 24
Peak memory 195816 kb
Host smart-f7b9abfd-13cd-48da-b4e5-820d52fb129a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179252740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.2179252740
Directory /workspace/40.uart_alert_test/latest

Test location /workspace/coverage/default/40.uart_fifo_full.3181881638
Short name T992
Test name
Test status
Simulation time 151517037229 ps
CPU time 134.9 seconds
Started Jun 05 04:16:43 PM PDT 24
Finished Jun 05 04:18:59 PM PDT 24
Peak memory 200448 kb
Host smart-f5eaa870-e6ad-4a57-a1cb-8d63a165c335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181881638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.3181881638
Directory /workspace/40.uart_fifo_full/latest

Test location /workspace/coverage/default/40.uart_fifo_overflow.2372521039
Short name T614
Test name
Test status
Simulation time 158732786761 ps
CPU time 16.07 seconds
Started Jun 05 04:16:43 PM PDT 24
Finished Jun 05 04:17:00 PM PDT 24
Peak memory 200340 kb
Host smart-47516e16-d102-4de3-b626-35b26cc02c25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372521039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.2372521039
Directory /workspace/40.uart_fifo_overflow/latest

Test location /workspace/coverage/default/40.uart_fifo_reset.324170228
Short name T508
Test name
Test status
Simulation time 38313867833 ps
CPU time 19.06 seconds
Started Jun 05 04:16:45 PM PDT 24
Finished Jun 05 04:17:05 PM PDT 24
Peak memory 200356 kb
Host smart-5ef9871b-60da-4b9b-a4ff-a4b4170549c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324170228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.324170228
Directory /workspace/40.uart_fifo_reset/latest

Test location /workspace/coverage/default/40.uart_intr.3453309776
Short name T481
Test name
Test status
Simulation time 4637936863 ps
CPU time 11.59 seconds
Started Jun 05 04:16:43 PM PDT 24
Finished Jun 05 04:16:55 PM PDT 24
Peak memory 199856 kb
Host smart-be7b149d-42fe-4793-89e0-201a90eee45f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453309776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.3453309776
Directory /workspace/40.uart_intr/latest

Test location /workspace/coverage/default/40.uart_long_xfer_wo_dly.2567808154
Short name T691
Test name
Test status
Simulation time 107442899484 ps
CPU time 241.3 seconds
Started Jun 05 04:16:43 PM PDT 24
Finished Jun 05 04:20:45 PM PDT 24
Peak memory 200340 kb
Host smart-8adcbbe3-a3e8-4e15-a89f-310bd3e1b5a4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2567808154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.2567808154
Directory /workspace/40.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/40.uart_loopback.2002850927
Short name T339
Test name
Test status
Simulation time 7829505961 ps
CPU time 3.85 seconds
Started Jun 05 04:16:43 PM PDT 24
Finished Jun 05 04:16:47 PM PDT 24
Peak memory 199684 kb
Host smart-ec5587f1-8aec-41f5-aa8e-f978d35ae4c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002850927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_loopback.2002850927
Directory /workspace/40.uart_loopback/latest

Test location /workspace/coverage/default/40.uart_noise_filter.1976988741
Short name T1059
Test name
Test status
Simulation time 8275638756 ps
CPU time 15.75 seconds
Started Jun 05 04:16:45 PM PDT 24
Finished Jun 05 04:17:02 PM PDT 24
Peak memory 200380 kb
Host smart-0b616207-c672-44f3-b6d5-b84c80676d54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976988741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_noise_filter.1976988741
Directory /workspace/40.uart_noise_filter/latest

Test location /workspace/coverage/default/40.uart_perf.2055287103
Short name T1115
Test name
Test status
Simulation time 13022710495 ps
CPU time 361.53 seconds
Started Jun 05 04:16:42 PM PDT 24
Finished Jun 05 04:22:45 PM PDT 24
Peak memory 200364 kb
Host smart-9b344024-73b9-46e1-9874-297c445b9578
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2055287103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.2055287103
Directory /workspace/40.uart_perf/latest

Test location /workspace/coverage/default/40.uart_rx_oversample.4161294762
Short name T687
Test name
Test status
Simulation time 6385964442 ps
CPU time 16.56 seconds
Started Jun 05 04:16:43 PM PDT 24
Finished Jun 05 04:17:00 PM PDT 24
Peak memory 198596 kb
Host smart-2ab1cad0-370e-44f6-8945-4c37e2e46611
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4161294762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.4161294762
Directory /workspace/40.uart_rx_oversample/latest

Test location /workspace/coverage/default/40.uart_rx_parity_err.2341944808
Short name T1139
Test name
Test status
Simulation time 51532428000 ps
CPU time 20.66 seconds
Started Jun 05 04:16:42 PM PDT 24
Finished Jun 05 04:17:04 PM PDT 24
Peak memory 200428 kb
Host smart-34ea4e4c-0ae8-4ec1-bdc3-d21e5befb022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341944808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.2341944808
Directory /workspace/40.uart_rx_parity_err/latest

Test location /workspace/coverage/default/40.uart_rx_start_bit_filter.1945990863
Short name T942
Test name
Test status
Simulation time 4069605604 ps
CPU time 2.11 seconds
Started Jun 05 04:16:42 PM PDT 24
Finished Jun 05 04:16:45 PM PDT 24
Peak memory 196704 kb
Host smart-5c180d1e-7a17-4677-b8b4-68f8b1fd144a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945990863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.1945990863
Directory /workspace/40.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/40.uart_smoke.3693298653
Short name T821
Test name
Test status
Simulation time 5638771377 ps
CPU time 13.59 seconds
Started Jun 05 04:16:41 PM PDT 24
Finished Jun 05 04:16:56 PM PDT 24
Peak memory 200212 kb
Host smart-1c2bdc5f-627e-4503-93da-0f04fe100b7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693298653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_smoke.3693298653
Directory /workspace/40.uart_smoke/latest

Test location /workspace/coverage/default/40.uart_stress_all.2477366864
Short name T1089
Test name
Test status
Simulation time 202479494016 ps
CPU time 1698.6 seconds
Started Jun 05 04:16:42 PM PDT 24
Finished Jun 05 04:45:02 PM PDT 24
Peak memory 216280 kb
Host smart-e6425f0d-f026-4fab-a331-da2c98a20881
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477366864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.2477366864
Directory /workspace/40.uart_stress_all/latest

Test location /workspace/coverage/default/40.uart_tx_ovrd.683604119
Short name T73
Test name
Test status
Simulation time 1397032147 ps
CPU time 1.5 seconds
Started Jun 05 04:16:47 PM PDT 24
Finished Jun 05 04:16:49 PM PDT 24
Peak memory 198236 kb
Host smart-a03373b6-b9dd-43ea-84ba-f1a0d9d547da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683604119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.683604119
Directory /workspace/40.uart_tx_ovrd/latest

Test location /workspace/coverage/default/40.uart_tx_rx.2900375049
Short name T886
Test name
Test status
Simulation time 15576174439 ps
CPU time 7.91 seconds
Started Jun 05 04:16:42 PM PDT 24
Finished Jun 05 04:16:51 PM PDT 24
Peak memory 200188 kb
Host smart-6818eeb4-6fa0-4ea4-a157-d758a60a93bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900375049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.2900375049
Directory /workspace/40.uart_tx_rx/latest

Test location /workspace/coverage/default/41.uart_alert_test.416576593
Short name T634
Test name
Test status
Simulation time 19121983 ps
CPU time 0.56 seconds
Started Jun 05 04:16:52 PM PDT 24
Finished Jun 05 04:16:54 PM PDT 24
Peak memory 195696 kb
Host smart-ab5e35ad-8c1d-4769-aef3-114269f84440
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416576593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.416576593
Directory /workspace/41.uart_alert_test/latest

Test location /workspace/coverage/default/41.uart_fifo_full.4138672388
Short name T131
Test name
Test status
Simulation time 83394696941 ps
CPU time 20.88 seconds
Started Jun 05 04:16:45 PM PDT 24
Finished Jun 05 04:17:07 PM PDT 24
Peak memory 200412 kb
Host smart-4c2c2f4e-0fd6-4af8-ae84-3bfc95fc486e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138672388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.4138672388
Directory /workspace/41.uart_fifo_full/latest

Test location /workspace/coverage/default/41.uart_fifo_overflow.1511939247
Short name T987
Test name
Test status
Simulation time 32058506308 ps
CPU time 25.89 seconds
Started Jun 05 04:16:43 PM PDT 24
Finished Jun 05 04:17:10 PM PDT 24
Peak memory 200416 kb
Host smart-d13ede72-795e-4415-80a3-7dd3a4e38942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511939247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.1511939247
Directory /workspace/41.uart_fifo_overflow/latest

Test location /workspace/coverage/default/41.uart_fifo_reset.2620053694
Short name T1072
Test name
Test status
Simulation time 26150732050 ps
CPU time 48.15 seconds
Started Jun 05 04:16:44 PM PDT 24
Finished Jun 05 04:17:33 PM PDT 24
Peak memory 200424 kb
Host smart-bed6c9fc-0905-415f-be2b-64e04e1e3bd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620053694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.2620053694
Directory /workspace/41.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_intr.2314249346
Short name T1000
Test name
Test status
Simulation time 14490426186 ps
CPU time 7.69 seconds
Started Jun 05 04:16:51 PM PDT 24
Finished Jun 05 04:16:59 PM PDT 24
Peak memory 198440 kb
Host smart-b937c28a-d68b-454a-8f35-7f1e7e96b291
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314249346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.2314249346
Directory /workspace/41.uart_intr/latest

Test location /workspace/coverage/default/41.uart_long_xfer_wo_dly.4248264712
Short name T290
Test name
Test status
Simulation time 114777916818 ps
CPU time 1045.39 seconds
Started Jun 05 04:16:52 PM PDT 24
Finished Jun 05 04:34:18 PM PDT 24
Peak memory 200476 kb
Host smart-dc3d6793-f4de-4553-9335-43e1c90d4f0e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4248264712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.4248264712
Directory /workspace/41.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/41.uart_loopback.4170442567
Short name T414
Test name
Test status
Simulation time 2139514494 ps
CPU time 4.69 seconds
Started Jun 05 04:17:00 PM PDT 24
Finished Jun 05 04:17:06 PM PDT 24
Peak memory 198916 kb
Host smart-516ec804-7f7a-45fd-ba0c-f7462f3b6124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170442567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_loopback.4170442567
Directory /workspace/41.uart_loopback/latest

Test location /workspace/coverage/default/41.uart_noise_filter.1356520434
Short name T962
Test name
Test status
Simulation time 59258367078 ps
CPU time 88.35 seconds
Started Jun 05 04:16:51 PM PDT 24
Finished Jun 05 04:18:21 PM PDT 24
Peak memory 199472 kb
Host smart-8cc1dc70-7cd3-4867-ada6-8bd16fb32528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356520434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_noise_filter.1356520434
Directory /workspace/41.uart_noise_filter/latest

Test location /workspace/coverage/default/41.uart_perf.2359636269
Short name T430
Test name
Test status
Simulation time 15465155827 ps
CPU time 173.37 seconds
Started Jun 05 04:16:54 PM PDT 24
Finished Jun 05 04:19:48 PM PDT 24
Peak memory 200360 kb
Host smart-5352ee1a-121a-4195-9c39-918152f20301
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2359636269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.2359636269
Directory /workspace/41.uart_perf/latest

Test location /workspace/coverage/default/41.uart_rx_oversample.1792059403
Short name T999
Test name
Test status
Simulation time 7203197048 ps
CPU time 16.15 seconds
Started Jun 05 04:16:52 PM PDT 24
Finished Jun 05 04:17:09 PM PDT 24
Peak memory 200432 kb
Host smart-7bf43bd9-14f7-41b2-a987-d949222dd799
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1792059403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.1792059403
Directory /workspace/41.uart_rx_oversample/latest

Test location /workspace/coverage/default/41.uart_rx_parity_err.246085634
Short name T425
Test name
Test status
Simulation time 36807748490 ps
CPU time 54.52 seconds
Started Jun 05 04:16:50 PM PDT 24
Finished Jun 05 04:17:45 PM PDT 24
Peak memory 200340 kb
Host smart-5a8b6d20-a070-4ce1-b5ba-a9f3a18e4caf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246085634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.246085634
Directory /workspace/41.uart_rx_parity_err/latest

Test location /workspace/coverage/default/41.uart_rx_start_bit_filter.4084622760
Short name T943
Test name
Test status
Simulation time 2273142723 ps
CPU time 2.34 seconds
Started Jun 05 04:16:52 PM PDT 24
Finished Jun 05 04:16:55 PM PDT 24
Peak memory 195828 kb
Host smart-3f0cf7fe-579b-4b1f-825a-4488ad59d994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084622760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.4084622760
Directory /workspace/41.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/41.uart_smoke.3018969822
Short name T404
Test name
Test status
Simulation time 546806957 ps
CPU time 2.39 seconds
Started Jun 05 04:16:44 PM PDT 24
Finished Jun 05 04:16:47 PM PDT 24
Peak memory 199908 kb
Host smart-f600b7a7-1cbf-4a48-87af-e646e90ba2a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018969822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_smoke.3018969822
Directory /workspace/41.uart_smoke/latest

Test location /workspace/coverage/default/41.uart_stress_all.1768414331
Short name T612
Test name
Test status
Simulation time 310099469748 ps
CPU time 697.79 seconds
Started Jun 05 04:16:51 PM PDT 24
Finished Jun 05 04:28:30 PM PDT 24
Peak memory 208812 kb
Host smart-ab89af1f-0ce9-4593-98d7-6e64d515efb1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768414331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.1768414331
Directory /workspace/41.uart_stress_all/latest

Test location /workspace/coverage/default/41.uart_tx_ovrd.950516226
Short name T1002
Test name
Test status
Simulation time 1352440379 ps
CPU time 2.17 seconds
Started Jun 05 04:16:52 PM PDT 24
Finished Jun 05 04:16:55 PM PDT 24
Peak memory 199596 kb
Host smart-d5ea794c-aae5-4692-bcf2-d5ccb69e4ad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950516226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.950516226
Directory /workspace/41.uart_tx_ovrd/latest

Test location /workspace/coverage/default/41.uart_tx_rx.2981775651
Short name T1049
Test name
Test status
Simulation time 74850674567 ps
CPU time 110.54 seconds
Started Jun 05 04:16:45 PM PDT 24
Finished Jun 05 04:18:36 PM PDT 24
Peak memory 200448 kb
Host smart-9856c067-9190-4d06-8704-501b13769eea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981775651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.2981775651
Directory /workspace/41.uart_tx_rx/latest

Test location /workspace/coverage/default/42.uart_alert_test.447014705
Short name T479
Test name
Test status
Simulation time 16910861 ps
CPU time 0.54 seconds
Started Jun 05 04:16:51 PM PDT 24
Finished Jun 05 04:16:52 PM PDT 24
Peak memory 195812 kb
Host smart-b8ebe6d3-aae3-4215-bab9-e44062bedb46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447014705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.447014705
Directory /workspace/42.uart_alert_test/latest

Test location /workspace/coverage/default/42.uart_fifo_full.541913213
Short name T996
Test name
Test status
Simulation time 35855760527 ps
CPU time 16.39 seconds
Started Jun 05 04:16:54 PM PDT 24
Finished Jun 05 04:17:11 PM PDT 24
Peak memory 200448 kb
Host smart-c18d748b-abae-4279-8e5b-564cd662d875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541913213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.541913213
Directory /workspace/42.uart_fifo_full/latest

Test location /workspace/coverage/default/42.uart_fifo_overflow.577384632
Short name T147
Test name
Test status
Simulation time 247604928193 ps
CPU time 34.04 seconds
Started Jun 05 04:16:51 PM PDT 24
Finished Jun 05 04:17:26 PM PDT 24
Peak memory 200336 kb
Host smart-1b77d5ae-512e-45a8-9c55-80b337704dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577384632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.577384632
Directory /workspace/42.uart_fifo_overflow/latest

Test location /workspace/coverage/default/42.uart_fifo_reset.1210244214
Short name T1168
Test name
Test status
Simulation time 57104854955 ps
CPU time 25.79 seconds
Started Jun 05 04:16:59 PM PDT 24
Finished Jun 05 04:17:26 PM PDT 24
Peak memory 200444 kb
Host smart-7b6cecf1-f366-47e9-b253-18361aba4d02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210244214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.1210244214
Directory /workspace/42.uart_fifo_reset/latest

Test location /workspace/coverage/default/42.uart_intr.171647570
Short name T379
Test name
Test status
Simulation time 5465793695 ps
CPU time 18.71 seconds
Started Jun 05 04:16:54 PM PDT 24
Finished Jun 05 04:17:13 PM PDT 24
Peak memory 199708 kb
Host smart-35114152-e7b9-42aa-9e46-263ddcd119fc
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171647570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.171647570
Directory /workspace/42.uart_intr/latest

Test location /workspace/coverage/default/42.uart_long_xfer_wo_dly.3015708363
Short name T351
Test name
Test status
Simulation time 94663662058 ps
CPU time 519.38 seconds
Started Jun 05 04:16:51 PM PDT 24
Finished Jun 05 04:25:31 PM PDT 24
Peak memory 200416 kb
Host smart-7b63e406-cbed-4812-9a0e-287ee32b745f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3015708363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.3015708363
Directory /workspace/42.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/42.uart_loopback.4243736639
Short name T904
Test name
Test status
Simulation time 12239974306 ps
CPU time 10.57 seconds
Started Jun 05 04:16:52 PM PDT 24
Finished Jun 05 04:17:04 PM PDT 24
Peak memory 199808 kb
Host smart-960b9aea-7ea3-4829-b7a5-730a5047a33f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243736639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_loopback.4243736639
Directory /workspace/42.uart_loopback/latest

Test location /workspace/coverage/default/42.uart_noise_filter.630866195
Short name T473
Test name
Test status
Simulation time 115335871375 ps
CPU time 77.57 seconds
Started Jun 05 04:16:52 PM PDT 24
Finished Jun 05 04:18:10 PM PDT 24
Peak memory 199976 kb
Host smart-c74542de-3a83-4165-a36a-59292f4589ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630866195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_noise_filter.630866195
Directory /workspace/42.uart_noise_filter/latest

Test location /workspace/coverage/default/42.uart_perf.1844397273
Short name T915
Test name
Test status
Simulation time 16604398656 ps
CPU time 232.27 seconds
Started Jun 05 04:16:51 PM PDT 24
Finished Jun 05 04:20:44 PM PDT 24
Peak memory 200456 kb
Host smart-a69fa7af-6509-4999-90c1-b02c57f44e70
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1844397273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.1844397273
Directory /workspace/42.uart_perf/latest

Test location /workspace/coverage/default/42.uart_rx_oversample.146350367
Short name T917
Test name
Test status
Simulation time 5254722965 ps
CPU time 24.52 seconds
Started Jun 05 04:16:51 PM PDT 24
Finished Jun 05 04:17:16 PM PDT 24
Peak memory 198908 kb
Host smart-fde580f1-7b5b-436c-a159-78ec4136ba33
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=146350367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.146350367
Directory /workspace/42.uart_rx_oversample/latest

Test location /workspace/coverage/default/42.uart_rx_parity_err.4261211065
Short name T1076
Test name
Test status
Simulation time 204612040789 ps
CPU time 299.78 seconds
Started Jun 05 04:17:00 PM PDT 24
Finished Jun 05 04:22:01 PM PDT 24
Peak memory 200416 kb
Host smart-36af6ad9-c3e2-4ebf-a239-f3fff4342b70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261211065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.4261211065
Directory /workspace/42.uart_rx_parity_err/latest

Test location /workspace/coverage/default/42.uart_rx_start_bit_filter.288040952
Short name T748
Test name
Test status
Simulation time 45542041045 ps
CPU time 69.33 seconds
Started Jun 05 04:17:00 PM PDT 24
Finished Jun 05 04:18:10 PM PDT 24
Peak memory 196136 kb
Host smart-674d6775-73aa-4086-9594-4d5d97d28a44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288040952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.288040952
Directory /workspace/42.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/42.uart_smoke.3369004662
Short name T751
Test name
Test status
Simulation time 741255304 ps
CPU time 2.49 seconds
Started Jun 05 04:16:54 PM PDT 24
Finished Jun 05 04:16:57 PM PDT 24
Peak memory 198896 kb
Host smart-404fca18-b595-47f3-84b8-4271ea4d1def
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369004662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_smoke.3369004662
Directory /workspace/42.uart_smoke/latest

Test location /workspace/coverage/default/42.uart_stress_all.636132436
Short name T167
Test name
Test status
Simulation time 244345119426 ps
CPU time 456.21 seconds
Started Jun 05 04:16:52 PM PDT 24
Finished Jun 05 04:24:29 PM PDT 24
Peak memory 200428 kb
Host smart-60a86a8e-45ff-49bb-9675-3a4cdd67f734
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636132436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.636132436
Directory /workspace/42.uart_stress_all/latest

Test location /workspace/coverage/default/42.uart_stress_all_with_rand_reset.3624642011
Short name T870
Test name
Test status
Simulation time 18626593498 ps
CPU time 241.56 seconds
Started Jun 05 04:16:52 PM PDT 24
Finished Jun 05 04:20:55 PM PDT 24
Peak memory 216732 kb
Host smart-09f080a3-742b-41f3-a1e3-91a8afd48520
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624642011 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 42.uart_stress_all_with_rand_reset.3624642011
Directory /workspace/42.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.uart_tx_ovrd.2032184647
Short name T311
Test name
Test status
Simulation time 6890259878 ps
CPU time 18.95 seconds
Started Jun 05 04:16:54 PM PDT 24
Finished Jun 05 04:17:13 PM PDT 24
Peak memory 199812 kb
Host smart-544faec3-8277-4f04-9ccc-3c1f8fda50ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032184647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.2032184647
Directory /workspace/42.uart_tx_ovrd/latest

Test location /workspace/coverage/default/42.uart_tx_rx.3887036121
Short name T930
Test name
Test status
Simulation time 66679862006 ps
CPU time 31.29 seconds
Started Jun 05 04:16:51 PM PDT 24
Finished Jun 05 04:17:23 PM PDT 24
Peak memory 200444 kb
Host smart-b30d26fa-99f3-4423-a56f-2262c649c0e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887036121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.3887036121
Directory /workspace/42.uart_tx_rx/latest

Test location /workspace/coverage/default/43.uart_alert_test.3133773588
Short name T703
Test name
Test status
Simulation time 122048502 ps
CPU time 0.56 seconds
Started Jun 05 04:17:00 PM PDT 24
Finished Jun 05 04:17:01 PM PDT 24
Peak memory 195252 kb
Host smart-3987abcd-3891-47af-9132-8a000151faf4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133773588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.3133773588
Directory /workspace/43.uart_alert_test/latest

Test location /workspace/coverage/default/43.uart_fifo_full.2909011722
Short name T997
Test name
Test status
Simulation time 109698537513 ps
CPU time 27.86 seconds
Started Jun 05 04:16:50 PM PDT 24
Finished Jun 05 04:17:18 PM PDT 24
Peak memory 200304 kb
Host smart-5c5ef633-aa4d-4c4a-824b-ec04bce7cc04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909011722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.2909011722
Directory /workspace/43.uart_fifo_full/latest

Test location /workspace/coverage/default/43.uart_fifo_overflow.1806356035
Short name T994
Test name
Test status
Simulation time 111053973845 ps
CPU time 77.01 seconds
Started Jun 05 04:16:52 PM PDT 24
Finished Jun 05 04:18:10 PM PDT 24
Peak memory 200304 kb
Host smart-03ed9244-0bd4-4d09-9e8f-caa71caf7c84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806356035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.1806356035
Directory /workspace/43.uart_fifo_overflow/latest

Test location /workspace/coverage/default/43.uart_fifo_reset.475299491
Short name T975
Test name
Test status
Simulation time 19819659124 ps
CPU time 27.87 seconds
Started Jun 05 04:16:54 PM PDT 24
Finished Jun 05 04:17:22 PM PDT 24
Peak memory 200456 kb
Host smart-aa160a86-0a03-48b4-bea3-4d72e4317b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475299491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.475299491
Directory /workspace/43.uart_fifo_reset/latest

Test location /workspace/coverage/default/43.uart_intr.2405641806
Short name T593
Test name
Test status
Simulation time 12554520921 ps
CPU time 11.53 seconds
Started Jun 05 04:16:54 PM PDT 24
Finished Jun 05 04:17:07 PM PDT 24
Peak memory 200312 kb
Host smart-725d7d96-bf76-4e39-816a-00f839d14310
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405641806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.2405641806
Directory /workspace/43.uart_intr/latest

Test location /workspace/coverage/default/43.uart_long_xfer_wo_dly.971151597
Short name T1147
Test name
Test status
Simulation time 45233564257 ps
CPU time 399.66 seconds
Started Jun 05 04:17:00 PM PDT 24
Finished Jun 05 04:23:41 PM PDT 24
Peak memory 200372 kb
Host smart-de7b85c2-bf65-4ae4-b39f-d3c52c3e7de4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=971151597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.971151597
Directory /workspace/43.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/43.uart_loopback.419864333
Short name T345
Test name
Test status
Simulation time 2706428843 ps
CPU time 5.05 seconds
Started Jun 05 04:16:53 PM PDT 24
Finished Jun 05 04:16:59 PM PDT 24
Peak memory 197936 kb
Host smart-a869cc20-bb4b-4664-be0b-acb9a036497c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419864333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_loopback.419864333
Directory /workspace/43.uart_loopback/latest

Test location /workspace/coverage/default/43.uart_noise_filter.1053386295
Short name T433
Test name
Test status
Simulation time 35710254977 ps
CPU time 16.01 seconds
Started Jun 05 04:16:54 PM PDT 24
Finished Jun 05 04:17:11 PM PDT 24
Peak memory 195232 kb
Host smart-e47bedef-c843-4f36-9eae-4fc80523cd24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053386295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_noise_filter.1053386295
Directory /workspace/43.uart_noise_filter/latest

Test location /workspace/coverage/default/43.uart_perf.1743436789
Short name T881
Test name
Test status
Simulation time 13367731548 ps
CPU time 127.45 seconds
Started Jun 05 04:16:58 PM PDT 24
Finished Jun 05 04:19:06 PM PDT 24
Peak memory 200364 kb
Host smart-9292bcf7-5aa2-4a44-a749-5922687c3694
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1743436789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.1743436789
Directory /workspace/43.uart_perf/latest

Test location /workspace/coverage/default/43.uart_rx_oversample.1400944904
Short name T344
Test name
Test status
Simulation time 5250516491 ps
CPU time 10.83 seconds
Started Jun 05 04:16:53 PM PDT 24
Finished Jun 05 04:17:05 PM PDT 24
Peak memory 198484 kb
Host smart-f654e976-6c27-4865-a314-2ecfd606bdc6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1400944904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.1400944904
Directory /workspace/43.uart_rx_oversample/latest

Test location /workspace/coverage/default/43.uart_rx_parity_err.1850531854
Short name T630
Test name
Test status
Simulation time 57328787055 ps
CPU time 49.97 seconds
Started Jun 05 04:16:53 PM PDT 24
Finished Jun 05 04:17:44 PM PDT 24
Peak memory 200400 kb
Host smart-00a37dc9-7abb-430d-b1e9-9c82ed060cde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850531854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.1850531854
Directory /workspace/43.uart_rx_parity_err/latest

Test location /workspace/coverage/default/43.uart_rx_start_bit_filter.524464490
Short name T782
Test name
Test status
Simulation time 2053496703 ps
CPU time 2.27 seconds
Started Jun 05 04:16:52 PM PDT 24
Finished Jun 05 04:16:55 PM PDT 24
Peak memory 195772 kb
Host smart-e4107689-e4f2-4c3c-8b6f-d6867760c987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524464490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.524464490
Directory /workspace/43.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/43.uart_smoke.3650603867
Short name T553
Test name
Test status
Simulation time 667139869 ps
CPU time 1.77 seconds
Started Jun 05 04:16:52 PM PDT 24
Finished Jun 05 04:16:55 PM PDT 24
Peak memory 198908 kb
Host smart-c1d29285-7961-4113-91d1-658cff041160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650603867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_smoke.3650603867
Directory /workspace/43.uart_smoke/latest

Test location /workspace/coverage/default/43.uart_stress_all.2194822543
Short name T1094
Test name
Test status
Simulation time 149137921071 ps
CPU time 90.86 seconds
Started Jun 05 04:16:59 PM PDT 24
Finished Jun 05 04:18:30 PM PDT 24
Peak memory 208832 kb
Host smart-7a69707c-8c84-4c77-aa8d-6b13121cc76b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194822543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.2194822543
Directory /workspace/43.uart_stress_all/latest

Test location /workspace/coverage/default/43.uart_stress_all_with_rand_reset.2486827529
Short name T645
Test name
Test status
Simulation time 67329045053 ps
CPU time 699.33 seconds
Started Jun 05 04:16:59 PM PDT 24
Finished Jun 05 04:28:39 PM PDT 24
Peak memory 225284 kb
Host smart-da1009f3-16d7-41fb-b0e4-c495b9635757
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486827529 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 43.uart_stress_all_with_rand_reset.2486827529
Directory /workspace/43.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.uart_tx_ovrd.2924312411
Short name T308
Test name
Test status
Simulation time 1436154928 ps
CPU time 1.64 seconds
Started Jun 05 04:16:51 PM PDT 24
Finished Jun 05 04:16:54 PM PDT 24
Peak memory 200044 kb
Host smart-7b04f2ba-d42f-4686-a853-a7ef54e02e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924312411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.2924312411
Directory /workspace/43.uart_tx_ovrd/latest

Test location /workspace/coverage/default/43.uart_tx_rx.2621419332
Short name T1128
Test name
Test status
Simulation time 134696843678 ps
CPU time 73.48 seconds
Started Jun 05 04:17:00 PM PDT 24
Finished Jun 05 04:18:15 PM PDT 24
Peak memory 200444 kb
Host smart-d20f02f8-50d3-4d4a-9855-255d1c204e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621419332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.2621419332
Directory /workspace/43.uart_tx_rx/latest

Test location /workspace/coverage/default/44.uart_alert_test.2010443456
Short name T22
Test name
Test status
Simulation time 39423763 ps
CPU time 0.56 seconds
Started Jun 05 04:17:04 PM PDT 24
Finished Jun 05 04:17:06 PM PDT 24
Peak memory 195816 kb
Host smart-0be7de51-b5b2-4fef-b4c5-83ef05feadd4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010443456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.2010443456
Directory /workspace/44.uart_alert_test/latest

Test location /workspace/coverage/default/44.uart_fifo_full.214834845
Short name T1114
Test name
Test status
Simulation time 232330300655 ps
CPU time 89.52 seconds
Started Jun 05 04:16:57 PM PDT 24
Finished Jun 05 04:18:28 PM PDT 24
Peak memory 200436 kb
Host smart-d82d39c6-100b-4099-89f5-41b8572f0443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214834845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.214834845
Directory /workspace/44.uart_fifo_full/latest

Test location /workspace/coverage/default/44.uart_fifo_overflow.1911061034
Short name T637
Test name
Test status
Simulation time 79541353628 ps
CPU time 140.34 seconds
Started Jun 05 04:17:04 PM PDT 24
Finished Jun 05 04:19:25 PM PDT 24
Peak memory 200360 kb
Host smart-1d2d9c55-7755-4440-82d3-f18fe2c5f58a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911061034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.1911061034
Directory /workspace/44.uart_fifo_overflow/latest

Test location /workspace/coverage/default/44.uart_fifo_reset.770913279
Short name T1033
Test name
Test status
Simulation time 18614142477 ps
CPU time 33.09 seconds
Started Jun 05 04:17:01 PM PDT 24
Finished Jun 05 04:17:35 PM PDT 24
Peak memory 200476 kb
Host smart-d066ef5f-2608-4d6f-ac92-ea62756beeac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770913279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.770913279
Directory /workspace/44.uart_fifo_reset/latest

Test location /workspace/coverage/default/44.uart_intr.317381784
Short name T449
Test name
Test status
Simulation time 29286585305 ps
CPU time 25.22 seconds
Started Jun 05 04:17:00 PM PDT 24
Finished Jun 05 04:17:26 PM PDT 24
Peak memory 200416 kb
Host smart-7d0399bb-8e12-40f8-be06-bf3d69e3438c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317381784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.317381784
Directory /workspace/44.uart_intr/latest

Test location /workspace/coverage/default/44.uart_long_xfer_wo_dly.3390465223
Short name T256
Test name
Test status
Simulation time 166320687723 ps
CPU time 374.85 seconds
Started Jun 05 04:17:01 PM PDT 24
Finished Jun 05 04:23:17 PM PDT 24
Peak memory 200424 kb
Host smart-0bdb85d6-8a03-44de-a389-59cbee572db2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3390465223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.3390465223
Directory /workspace/44.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/44.uart_loopback.1116052409
Short name T694
Test name
Test status
Simulation time 9711255295 ps
CPU time 18.46 seconds
Started Jun 05 04:17:00 PM PDT 24
Finished Jun 05 04:17:20 PM PDT 24
Peak memory 199312 kb
Host smart-a984f2a0-5f64-4832-987d-3e52d31452e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116052409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_loopback.1116052409
Directory /workspace/44.uart_loopback/latest

Test location /workspace/coverage/default/44.uart_noise_filter.3268961379
Short name T538
Test name
Test status
Simulation time 92815816881 ps
CPU time 134.79 seconds
Started Jun 05 04:17:00 PM PDT 24
Finished Jun 05 04:19:16 PM PDT 24
Peak memory 200616 kb
Host smart-3f59dae6-33d0-4a6d-a9c5-2fc809cedc7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268961379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_noise_filter.3268961379
Directory /workspace/44.uart_noise_filter/latest

Test location /workspace/coverage/default/44.uart_perf.455066121
Short name T794
Test name
Test status
Simulation time 15983907436 ps
CPU time 300.54 seconds
Started Jun 05 04:16:58 PM PDT 24
Finished Jun 05 04:21:59 PM PDT 24
Peak memory 200388 kb
Host smart-381eae44-b6ae-42fd-acf2-2dec5c3e921d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=455066121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.455066121
Directory /workspace/44.uart_perf/latest

Test location /workspace/coverage/default/44.uart_rx_oversample.2382857828
Short name T982
Test name
Test status
Simulation time 3263978848 ps
CPU time 24.13 seconds
Started Jun 05 04:17:04 PM PDT 24
Finished Jun 05 04:17:29 PM PDT 24
Peak memory 199292 kb
Host smart-c74060e2-d11a-44cb-a969-745f5083352f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2382857828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.2382857828
Directory /workspace/44.uart_rx_oversample/latest

Test location /workspace/coverage/default/44.uart_rx_parity_err.3101513506
Short name T1028
Test name
Test status
Simulation time 266451881616 ps
CPU time 22.83 seconds
Started Jun 05 04:17:00 PM PDT 24
Finished Jun 05 04:17:23 PM PDT 24
Peak memory 200420 kb
Host smart-fdd75cef-4373-4a2b-b38f-1633df9299ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101513506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.3101513506
Directory /workspace/44.uart_rx_parity_err/latest

Test location /workspace/coverage/default/44.uart_rx_start_bit_filter.1167599603
Short name T494
Test name
Test status
Simulation time 3109078747 ps
CPU time 5.97 seconds
Started Jun 05 04:17:00 PM PDT 24
Finished Jun 05 04:17:06 PM PDT 24
Peak memory 196244 kb
Host smart-4e47b704-b5be-4066-88ae-a7be2168e28d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167599603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.1167599603
Directory /workspace/44.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/44.uart_smoke.3762287855
Short name T888
Test name
Test status
Simulation time 646507822 ps
CPU time 1.36 seconds
Started Jun 05 04:17:00 PM PDT 24
Finished Jun 05 04:17:02 PM PDT 24
Peak memory 199152 kb
Host smart-1c1532e4-2491-4d60-9a76-7798418891ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762287855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_smoke.3762287855
Directory /workspace/44.uart_smoke/latest

Test location /workspace/coverage/default/44.uart_stress_all.2941879380
Short name T580
Test name
Test status
Simulation time 427736495830 ps
CPU time 616.61 seconds
Started Jun 05 04:17:00 PM PDT 24
Finished Jun 05 04:27:18 PM PDT 24
Peak memory 200456 kb
Host smart-5c44b78c-f604-4fa9-bd5d-21a073ebaaf3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941879380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.2941879380
Directory /workspace/44.uart_stress_all/latest

Test location /workspace/coverage/default/44.uart_stress_all_with_rand_reset.3362529274
Short name T78
Test name
Test status
Simulation time 56696996150 ps
CPU time 651.02 seconds
Started Jun 05 04:17:01 PM PDT 24
Finished Jun 05 04:27:53 PM PDT 24
Peak memory 216916 kb
Host smart-0cb1dafa-0c51-4007-a9ec-1d26d85cf0e7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362529274 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 44.uart_stress_all_with_rand_reset.3362529274
Directory /workspace/44.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.uart_tx_ovrd.4111664782
Short name T822
Test name
Test status
Simulation time 589926956 ps
CPU time 2 seconds
Started Jun 05 04:17:04 PM PDT 24
Finished Jun 05 04:17:06 PM PDT 24
Peak memory 198860 kb
Host smart-7135206d-9c45-4388-b377-64fc191851e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111664782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.4111664782
Directory /workspace/44.uart_tx_ovrd/latest

Test location /workspace/coverage/default/44.uart_tx_rx.326396781
Short name T532
Test name
Test status
Simulation time 140600912491 ps
CPU time 128.15 seconds
Started Jun 05 04:17:01 PM PDT 24
Finished Jun 05 04:19:10 PM PDT 24
Peak memory 200404 kb
Host smart-bc0c5e24-3d64-4e62-80d0-c9b5e413140e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326396781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.326396781
Directory /workspace/44.uart_tx_rx/latest

Test location /workspace/coverage/default/45.uart_alert_test.159141108
Short name T405
Test name
Test status
Simulation time 48645104 ps
CPU time 0.58 seconds
Started Jun 05 04:17:10 PM PDT 24
Finished Jun 05 04:17:11 PM PDT 24
Peak memory 195708 kb
Host smart-7a2ce224-1218-482e-8f0f-1412749312c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159141108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.159141108
Directory /workspace/45.uart_alert_test/latest

Test location /workspace/coverage/default/45.uart_fifo_full.1407711988
Short name T1104
Test name
Test status
Simulation time 411087384538 ps
CPU time 121.8 seconds
Started Jun 05 04:17:01 PM PDT 24
Finished Jun 05 04:19:04 PM PDT 24
Peak memory 200384 kb
Host smart-c3ec4c5c-48a6-4faa-8709-15341ddbd3d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407711988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.1407711988
Directory /workspace/45.uart_fifo_full/latest

Test location /workspace/coverage/default/45.uart_fifo_overflow.1770935471
Short name T11
Test name
Test status
Simulation time 4616247824 ps
CPU time 10.74 seconds
Started Jun 05 04:17:03 PM PDT 24
Finished Jun 05 04:17:14 PM PDT 24
Peak memory 200428 kb
Host smart-a6c619df-e269-4c28-8a04-d2e96f1dbb61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770935471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.1770935471
Directory /workspace/45.uart_fifo_overflow/latest

Test location /workspace/coverage/default/45.uart_fifo_reset.540455470
Short name T527
Test name
Test status
Simulation time 9797745226 ps
CPU time 17.41 seconds
Started Jun 05 04:17:08 PM PDT 24
Finished Jun 05 04:17:26 PM PDT 24
Peak memory 200376 kb
Host smart-625ca786-f4c3-4948-a66a-a6ee6375332e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540455470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.540455470
Directory /workspace/45.uart_fifo_reset/latest

Test location /workspace/coverage/default/45.uart_intr.448163343
Short name T1158
Test name
Test status
Simulation time 130837691476 ps
CPU time 38.02 seconds
Started Jun 05 04:17:09 PM PDT 24
Finished Jun 05 04:17:47 PM PDT 24
Peak memory 200412 kb
Host smart-1ed423eb-bca6-4c4c-b990-e2cfb77a835f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448163343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.448163343
Directory /workspace/45.uart_intr/latest

Test location /workspace/coverage/default/45.uart_long_xfer_wo_dly.2539644292
Short name T271
Test name
Test status
Simulation time 60799465959 ps
CPU time 487.41 seconds
Started Jun 05 04:17:09 PM PDT 24
Finished Jun 05 04:25:18 PM PDT 24
Peak memory 200444 kb
Host smart-2aeea64a-9dcf-460a-b54d-e77183877c45
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2539644292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.2539644292
Directory /workspace/45.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/45.uart_loopback.3575466928
Short name T597
Test name
Test status
Simulation time 2198184763 ps
CPU time 2.96 seconds
Started Jun 05 04:17:08 PM PDT 24
Finished Jun 05 04:17:12 PM PDT 24
Peak memory 198884 kb
Host smart-b58bb7e6-0f9e-4edd-8d66-3d74f38291b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575466928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_loopback.3575466928
Directory /workspace/45.uart_loopback/latest

Test location /workspace/coverage/default/45.uart_noise_filter.4017272168
Short name T670
Test name
Test status
Simulation time 112399558845 ps
CPU time 65.37 seconds
Started Jun 05 04:17:07 PM PDT 24
Finished Jun 05 04:18:13 PM PDT 24
Peak memory 200588 kb
Host smart-b6afd0ce-b99e-4f25-b00b-dd11af311bda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017272168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_noise_filter.4017272168
Directory /workspace/45.uart_noise_filter/latest

Test location /workspace/coverage/default/45.uart_perf.4289818911
Short name T980
Test name
Test status
Simulation time 12244409781 ps
CPU time 85.76 seconds
Started Jun 05 04:17:10 PM PDT 24
Finished Jun 05 04:18:36 PM PDT 24
Peak memory 200356 kb
Host smart-13652aa1-cb4a-4112-a4c5-59e5f881c90e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4289818911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.4289818911
Directory /workspace/45.uart_perf/latest

Test location /workspace/coverage/default/45.uart_rx_oversample.405483698
Short name T373
Test name
Test status
Simulation time 4274440726 ps
CPU time 8.34 seconds
Started Jun 05 04:17:10 PM PDT 24
Finished Jun 05 04:17:19 PM PDT 24
Peak memory 198640 kb
Host smart-4f48a853-8de9-4d36-bb9b-5d14849297db
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=405483698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.405483698
Directory /workspace/45.uart_rx_oversample/latest

Test location /workspace/coverage/default/45.uart_rx_parity_err.2806484753
Short name T772
Test name
Test status
Simulation time 296884823122 ps
CPU time 149.68 seconds
Started Jun 05 04:17:08 PM PDT 24
Finished Jun 05 04:19:38 PM PDT 24
Peak memory 200436 kb
Host smart-b3cebe99-2e88-481e-863c-e64ce5d519e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806484753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.2806484753
Directory /workspace/45.uart_rx_parity_err/latest

Test location /workspace/coverage/default/45.uart_rx_start_bit_filter.3318652913
Short name T37
Test name
Test status
Simulation time 3256244908 ps
CPU time 3.26 seconds
Started Jun 05 04:17:10 PM PDT 24
Finished Jun 05 04:17:14 PM PDT 24
Peak memory 196400 kb
Host smart-eecb784c-76f9-4a56-94b4-53e0f818c320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318652913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.3318652913
Directory /workspace/45.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/45.uart_smoke.2232460010
Short name T639
Test name
Test status
Simulation time 5675687563 ps
CPU time 13.3 seconds
Started Jun 05 04:16:59 PM PDT 24
Finished Jun 05 04:17:13 PM PDT 24
Peak memory 199600 kb
Host smart-5ff613a2-8e34-4130-88f1-842fbc86eca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232460010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_smoke.2232460010
Directory /workspace/45.uart_smoke/latest

Test location /workspace/coverage/default/45.uart_stress_all.2109015003
Short name T585
Test name
Test status
Simulation time 119186401711 ps
CPU time 96.73 seconds
Started Jun 05 04:17:09 PM PDT 24
Finished Jun 05 04:18:46 PM PDT 24
Peak memory 200376 kb
Host smart-5ed3896e-1d38-4ff9-b784-ec1a73a157b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109015003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.2109015003
Directory /workspace/45.uart_stress_all/latest

Test location /workspace/coverage/default/45.uart_stress_all_with_rand_reset.144228671
Short name T738
Test name
Test status
Simulation time 48533529477 ps
CPU time 765.18 seconds
Started Jun 05 04:17:09 PM PDT 24
Finished Jun 05 04:29:55 PM PDT 24
Peak memory 216748 kb
Host smart-9c4c5b39-7f55-434a-8c93-2f6faeca40a5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144228671 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 45.uart_stress_all_with_rand_reset.144228671
Directory /workspace/45.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.uart_tx_ovrd.4184178885
Short name T278
Test name
Test status
Simulation time 6730222321 ps
CPU time 19.01 seconds
Started Jun 05 04:17:08 PM PDT 24
Finished Jun 05 04:17:27 PM PDT 24
Peak memory 200352 kb
Host smart-393ac063-1a92-4b21-8023-bc7c8380ca4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184178885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.4184178885
Directory /workspace/45.uart_tx_ovrd/latest

Test location /workspace/coverage/default/45.uart_tx_rx.3127960807
Short name T862
Test name
Test status
Simulation time 51858634476 ps
CPU time 85.59 seconds
Started Jun 05 04:17:00 PM PDT 24
Finished Jun 05 04:18:27 PM PDT 24
Peak memory 200576 kb
Host smart-077e3b41-30a8-4e9a-858b-f9c565faff2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127960807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.3127960807
Directory /workspace/45.uart_tx_rx/latest

Test location /workspace/coverage/default/46.uart_alert_test.3958822553
Short name T834
Test name
Test status
Simulation time 13292962 ps
CPU time 0.57 seconds
Started Jun 05 04:17:17 PM PDT 24
Finished Jun 05 04:17:18 PM PDT 24
Peak memory 195816 kb
Host smart-a4b0cd41-1eb9-40e4-b023-21f72616751b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958822553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.3958822553
Directory /workspace/46.uart_alert_test/latest

Test location /workspace/coverage/default/46.uart_fifo_full.1290042019
Short name T1126
Test name
Test status
Simulation time 265099897502 ps
CPU time 683.01 seconds
Started Jun 05 04:17:06 PM PDT 24
Finished Jun 05 04:28:30 PM PDT 24
Peak memory 200404 kb
Host smart-b9926a7c-5a9f-4a28-99db-a2134dcce3b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290042019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.1290042019
Directory /workspace/46.uart_fifo_full/latest

Test location /workspace/coverage/default/46.uart_fifo_overflow.2105444445
Short name T72
Test name
Test status
Simulation time 10393966334 ps
CPU time 15.87 seconds
Started Jun 05 04:17:13 PM PDT 24
Finished Jun 05 04:17:30 PM PDT 24
Peak memory 200428 kb
Host smart-1d9c037d-50cd-43dc-a33d-ac669723d6b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105444445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.2105444445
Directory /workspace/46.uart_fifo_overflow/latest

Test location /workspace/coverage/default/46.uart_fifo_reset.3330809193
Short name T198
Test name
Test status
Simulation time 70830191688 ps
CPU time 52.65 seconds
Started Jun 05 04:17:08 PM PDT 24
Finished Jun 05 04:18:01 PM PDT 24
Peak memory 200440 kb
Host smart-33ff04fb-79d1-49d6-bf8d-dbcf23e5ab38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330809193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.3330809193
Directory /workspace/46.uart_fifo_reset/latest

Test location /workspace/coverage/default/46.uart_intr.45901274
Short name T890
Test name
Test status
Simulation time 34869247840 ps
CPU time 68.83 seconds
Started Jun 05 04:17:10 PM PDT 24
Finished Jun 05 04:18:19 PM PDT 24
Peak memory 200384 kb
Host smart-35e6ceec-511f-48c6-b21a-9825ac9decf4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45901274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.45901274
Directory /workspace/46.uart_intr/latest

Test location /workspace/coverage/default/46.uart_long_xfer_wo_dly.3767814168
Short name T506
Test name
Test status
Simulation time 87059435098 ps
CPU time 429.14 seconds
Started Jun 05 04:17:19 PM PDT 24
Finished Jun 05 04:24:28 PM PDT 24
Peak memory 200472 kb
Host smart-54e6bce5-cff1-4ebe-a980-dde6185da017
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3767814168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.3767814168
Directory /workspace/46.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/46.uart_loopback.3243783217
Short name T19
Test name
Test status
Simulation time 1355761743 ps
CPU time 2.23 seconds
Started Jun 05 04:17:10 PM PDT 24
Finished Jun 05 04:17:13 PM PDT 24
Peak memory 198812 kb
Host smart-3cae2047-5fc9-4915-8b4a-0b8652eab2ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243783217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_loopback.3243783217
Directory /workspace/46.uart_loopback/latest

Test location /workspace/coverage/default/46.uart_noise_filter.2273259304
Short name T292
Test name
Test status
Simulation time 114018552470 ps
CPU time 107.87 seconds
Started Jun 05 04:17:11 PM PDT 24
Finished Jun 05 04:18:59 PM PDT 24
Peak memory 200588 kb
Host smart-f7a0150c-d94c-49a0-834a-b82aedc3dd5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273259304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_noise_filter.2273259304
Directory /workspace/46.uart_noise_filter/latest

Test location /workspace/coverage/default/46.uart_perf.2241380272
Short name T403
Test name
Test status
Simulation time 2653065170 ps
CPU time 24.26 seconds
Started Jun 05 04:17:17 PM PDT 24
Finished Jun 05 04:17:42 PM PDT 24
Peak memory 200436 kb
Host smart-6848d378-4b2c-4f4e-8806-49549ade0835
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2241380272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.2241380272
Directory /workspace/46.uart_perf/latest

Test location /workspace/coverage/default/46.uart_rx_oversample.3662948514
Short name T995
Test name
Test status
Simulation time 5261019554 ps
CPU time 23.71 seconds
Started Jun 05 04:17:07 PM PDT 24
Finished Jun 05 04:17:32 PM PDT 24
Peak memory 199220 kb
Host smart-9f8ee747-eb88-4864-9060-86f551c04359
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3662948514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.3662948514
Directory /workspace/46.uart_rx_oversample/latest

Test location /workspace/coverage/default/46.uart_rx_parity_err.2415911922
Short name T1136
Test name
Test status
Simulation time 24431187168 ps
CPU time 52.3 seconds
Started Jun 05 04:17:09 PM PDT 24
Finished Jun 05 04:18:02 PM PDT 24
Peak memory 200464 kb
Host smart-9d7294fc-c59c-41d6-bf5c-42be4759c365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415911922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.2415911922
Directory /workspace/46.uart_rx_parity_err/latest

Test location /workspace/coverage/default/46.uart_rx_start_bit_filter.3969311187
Short name T53
Test name
Test status
Simulation time 34129014196 ps
CPU time 5.54 seconds
Started Jun 05 04:17:07 PM PDT 24
Finished Jun 05 04:17:13 PM PDT 24
Peak memory 196612 kb
Host smart-b8f65239-f0fd-4b5d-b5be-393ad382285e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969311187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.3969311187
Directory /workspace/46.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/46.uart_smoke.2710019078
Short name T307
Test name
Test status
Simulation time 6079475611 ps
CPU time 10.85 seconds
Started Jun 05 04:17:06 PM PDT 24
Finished Jun 05 04:17:18 PM PDT 24
Peak memory 200344 kb
Host smart-a58c3b76-f2e6-4d6e-bc4b-676d5b73d48b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710019078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_smoke.2710019078
Directory /workspace/46.uart_smoke/latest

Test location /workspace/coverage/default/46.uart_stress_all.3411308877
Short name T581
Test name
Test status
Simulation time 134883090458 ps
CPU time 604.17 seconds
Started Jun 05 04:17:16 PM PDT 24
Finished Jun 05 04:27:21 PM PDT 24
Peak memory 200452 kb
Host smart-bd2a4bde-3ad6-4c50-b1b8-3912c9e4f01d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411308877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.3411308877
Directory /workspace/46.uart_stress_all/latest

Test location /workspace/coverage/default/46.uart_stress_all_with_rand_reset.369292955
Short name T812
Test name
Test status
Simulation time 26694711304 ps
CPU time 339.93 seconds
Started Jun 05 04:17:17 PM PDT 24
Finished Jun 05 04:22:58 PM PDT 24
Peak memory 208844 kb
Host smart-46150dc2-acee-43cc-b5f0-14b85319f30a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369292955 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 46.uart_stress_all_with_rand_reset.369292955
Directory /workspace/46.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.uart_tx_ovrd.2448049459
Short name T75
Test name
Test status
Simulation time 818901663 ps
CPU time 1.24 seconds
Started Jun 05 04:17:06 PM PDT 24
Finished Jun 05 04:17:08 PM PDT 24
Peak memory 200328 kb
Host smart-49bd3877-7ec2-4dee-a2a7-02db4be92773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448049459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.2448049459
Directory /workspace/46.uart_tx_ovrd/latest

Test location /workspace/coverage/default/46.uart_tx_rx.1546986660
Short name T484
Test name
Test status
Simulation time 69852219935 ps
CPU time 93.97 seconds
Started Jun 05 04:17:07 PM PDT 24
Finished Jun 05 04:18:41 PM PDT 24
Peak memory 200372 kb
Host smart-1a6e3ea4-5b52-4ee8-a911-ff380482cec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546986660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.1546986660
Directory /workspace/46.uart_tx_rx/latest

Test location /workspace/coverage/default/47.uart_alert_test.2455705076
Short name T586
Test name
Test status
Simulation time 12699926 ps
CPU time 0.57 seconds
Started Jun 05 04:17:16 PM PDT 24
Finished Jun 05 04:17:18 PM PDT 24
Peak memory 195832 kb
Host smart-7f78c44e-f19c-4529-b17e-4b5610f8f5ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455705076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.2455705076
Directory /workspace/47.uart_alert_test/latest

Test location /workspace/coverage/default/47.uart_fifo_full.2147326867
Short name T493
Test name
Test status
Simulation time 84622638513 ps
CPU time 62.53 seconds
Started Jun 05 04:17:15 PM PDT 24
Finished Jun 05 04:18:19 PM PDT 24
Peak memory 200380 kb
Host smart-38361532-fa40-4c1c-b4c4-6997dc5bb7bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147326867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.2147326867
Directory /workspace/47.uart_fifo_full/latest

Test location /workspace/coverage/default/47.uart_fifo_overflow.4269312514
Short name T1052
Test name
Test status
Simulation time 33687159570 ps
CPU time 46.28 seconds
Started Jun 05 04:17:16 PM PDT 24
Finished Jun 05 04:18:03 PM PDT 24
Peak memory 199952 kb
Host smart-605e9541-3874-41b7-aafe-ab319df3f530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269312514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.4269312514
Directory /workspace/47.uart_fifo_overflow/latest

Test location /workspace/coverage/default/47.uart_intr.2421496787
Short name T926
Test name
Test status
Simulation time 301383905178 ps
CPU time 271.22 seconds
Started Jun 05 04:17:17 PM PDT 24
Finished Jun 05 04:21:49 PM PDT 24
Peak memory 200368 kb
Host smart-39cd4088-3243-47e0-a869-999aded4f36e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421496787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.2421496787
Directory /workspace/47.uart_intr/latest

Test location /workspace/coverage/default/47.uart_long_xfer_wo_dly.2527584272
Short name T799
Test name
Test status
Simulation time 92666822304 ps
CPU time 375.66 seconds
Started Jun 05 04:17:18 PM PDT 24
Finished Jun 05 04:23:34 PM PDT 24
Peak memory 200348 kb
Host smart-2b266bc1-bd60-4fd7-83af-ebe30cde2960
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2527584272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.2527584272
Directory /workspace/47.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/47.uart_loopback.1995900069
Short name T1138
Test name
Test status
Simulation time 3245478000 ps
CPU time 2.33 seconds
Started Jun 05 04:17:17 PM PDT 24
Finished Jun 05 04:17:20 PM PDT 24
Peak memory 199096 kb
Host smart-ddc5768e-7e0b-4d5b-95b8-ddc8558a5116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995900069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_loopback.1995900069
Directory /workspace/47.uart_loopback/latest

Test location /workspace/coverage/default/47.uart_noise_filter.1380741851
Short name T570
Test name
Test status
Simulation time 43041980003 ps
CPU time 20.43 seconds
Started Jun 05 04:17:17 PM PDT 24
Finished Jun 05 04:17:38 PM PDT 24
Peak memory 196880 kb
Host smart-e95482e7-45ae-47f4-96db-6ec93e8fac2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380741851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_noise_filter.1380741851
Directory /workspace/47.uart_noise_filter/latest

Test location /workspace/coverage/default/47.uart_perf.912818065
Short name T989
Test name
Test status
Simulation time 14056213714 ps
CPU time 341.15 seconds
Started Jun 05 04:17:17 PM PDT 24
Finished Jun 05 04:22:59 PM PDT 24
Peak memory 200360 kb
Host smart-cefd23d4-07e9-481a-a800-10c3f3d79fc3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=912818065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.912818065
Directory /workspace/47.uart_perf/latest

Test location /workspace/coverage/default/47.uart_rx_oversample.2229382771
Short name T375
Test name
Test status
Simulation time 1815775686 ps
CPU time 2.85 seconds
Started Jun 05 04:17:16 PM PDT 24
Finished Jun 05 04:17:20 PM PDT 24
Peak memory 198160 kb
Host smart-7be5e86f-54a5-4379-a47d-506d11eddccd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2229382771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.2229382771
Directory /workspace/47.uart_rx_oversample/latest

Test location /workspace/coverage/default/47.uart_rx_parity_err.3759299854
Short name T301
Test name
Test status
Simulation time 69928379822 ps
CPU time 40.99 seconds
Started Jun 05 04:17:16 PM PDT 24
Finished Jun 05 04:17:58 PM PDT 24
Peak memory 200388 kb
Host smart-008734e8-7651-4e68-89da-f355432a9515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759299854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.3759299854
Directory /workspace/47.uart_rx_parity_err/latest

Test location /workspace/coverage/default/47.uart_rx_start_bit_filter.2940701941
Short name T347
Test name
Test status
Simulation time 5762047960 ps
CPU time 5.63 seconds
Started Jun 05 04:17:16 PM PDT 24
Finished Jun 05 04:17:23 PM PDT 24
Peak memory 196436 kb
Host smart-27f30dae-58af-4d90-b88b-475197f9f94b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940701941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.2940701941
Directory /workspace/47.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/47.uart_smoke.15515623
Short name T548
Test name
Test status
Simulation time 5459286076 ps
CPU time 11.22 seconds
Started Jun 05 04:17:16 PM PDT 24
Finished Jun 05 04:17:28 PM PDT 24
Peak memory 200428 kb
Host smart-15c9df6f-6a89-40fe-b6c0-b0ce87853955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15515623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_smoke.15515623
Directory /workspace/47.uart_smoke/latest

Test location /workspace/coverage/default/47.uart_stress_all.4128642899
Short name T306
Test name
Test status
Simulation time 393848811833 ps
CPU time 982.08 seconds
Started Jun 05 04:17:18 PM PDT 24
Finished Jun 05 04:33:41 PM PDT 24
Peak memory 200452 kb
Host smart-e58dccbd-f92e-44f8-971e-aa7e1fcd83a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128642899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.4128642899
Directory /workspace/47.uart_stress_all/latest

Test location /workspace/coverage/default/47.uart_stress_all_with_rand_reset.2993324058
Short name T649
Test name
Test status
Simulation time 33882671717 ps
CPU time 365.52 seconds
Started Jun 05 04:17:17 PM PDT 24
Finished Jun 05 04:23:24 PM PDT 24
Peak memory 216876 kb
Host smart-875a2932-917c-45f9-8370-eb6d3637a5d9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993324058 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 47.uart_stress_all_with_rand_reset.2993324058
Directory /workspace/47.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.uart_tx_ovrd.2450361949
Short name T1069
Test name
Test status
Simulation time 1702348973 ps
CPU time 2.13 seconds
Started Jun 05 04:17:19 PM PDT 24
Finished Jun 05 04:17:21 PM PDT 24
Peak memory 199016 kb
Host smart-a5366e08-8520-47b8-a272-4adb267210f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450361949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.2450361949
Directory /workspace/47.uart_tx_ovrd/latest

Test location /workspace/coverage/default/47.uart_tx_rx.815477142
Short name T1096
Test name
Test status
Simulation time 347730414681 ps
CPU time 41.81 seconds
Started Jun 05 04:17:16 PM PDT 24
Finished Jun 05 04:17:58 PM PDT 24
Peak memory 200424 kb
Host smart-42da5af4-9c2d-4f65-9d14-96bee250fb4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815477142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.815477142
Directory /workspace/47.uart_tx_rx/latest

Test location /workspace/coverage/default/48.uart_alert_test.3701531653
Short name T362
Test name
Test status
Simulation time 23223056 ps
CPU time 0.59 seconds
Started Jun 05 04:17:29 PM PDT 24
Finished Jun 05 04:17:30 PM PDT 24
Peak memory 195768 kb
Host smart-1c8e3fd5-4f24-4168-b31e-29150595356c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701531653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.3701531653
Directory /workspace/48.uart_alert_test/latest

Test location /workspace/coverage/default/48.uart_fifo_full.3621478705
Short name T534
Test name
Test status
Simulation time 97785959071 ps
CPU time 148.03 seconds
Started Jun 05 04:17:27 PM PDT 24
Finished Jun 05 04:19:55 PM PDT 24
Peak memory 200340 kb
Host smart-cead0a1f-c823-4f39-9477-35eb74728f29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621478705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.3621478705
Directory /workspace/48.uart_fifo_full/latest

Test location /workspace/coverage/default/48.uart_fifo_overflow.1822668458
Short name T598
Test name
Test status
Simulation time 67880745385 ps
CPU time 28 seconds
Started Jun 05 04:17:26 PM PDT 24
Finished Jun 05 04:17:55 PM PDT 24
Peak memory 200360 kb
Host smart-c21aebbc-356f-493d-8d34-a3a8e3691165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822668458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.1822668458
Directory /workspace/48.uart_fifo_overflow/latest

Test location /workspace/coverage/default/48.uart_fifo_reset.399708252
Short name T173
Test name
Test status
Simulation time 8868554773 ps
CPU time 15.65 seconds
Started Jun 05 04:17:25 PM PDT 24
Finished Jun 05 04:17:42 PM PDT 24
Peak memory 200464 kb
Host smart-03ace464-0ed1-4555-bdf9-8f1871f781af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399708252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.399708252
Directory /workspace/48.uart_fifo_reset/latest

Test location /workspace/coverage/default/48.uart_intr.3071181919
Short name T907
Test name
Test status
Simulation time 55473786327 ps
CPU time 30.2 seconds
Started Jun 05 04:17:24 PM PDT 24
Finished Jun 05 04:17:54 PM PDT 24
Peak memory 200420 kb
Host smart-3342a455-f9e7-4105-91d2-7c434b860635
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071181919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.3071181919
Directory /workspace/48.uart_intr/latest

Test location /workspace/coverage/default/48.uart_long_xfer_wo_dly.3091299726
Short name T1146
Test name
Test status
Simulation time 63129676384 ps
CPU time 109.57 seconds
Started Jun 05 04:17:31 PM PDT 24
Finished Jun 05 04:19:21 PM PDT 24
Peak memory 200440 kb
Host smart-d996be3b-fa5e-47ba-8d85-c3abe08d21d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3091299726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.3091299726
Directory /workspace/48.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/48.uart_loopback.642902922
Short name T814
Test name
Test status
Simulation time 5443836303 ps
CPU time 8.95 seconds
Started Jun 05 04:17:25 PM PDT 24
Finished Jun 05 04:17:35 PM PDT 24
Peak memory 199168 kb
Host smart-2189d27a-f29a-4dce-a983-b58208d2c614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642902922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_loopback.642902922
Directory /workspace/48.uart_loopback/latest

Test location /workspace/coverage/default/48.uart_noise_filter.3101990630
Short name T280
Test name
Test status
Simulation time 77780963019 ps
CPU time 127.89 seconds
Started Jun 05 04:17:25 PM PDT 24
Finished Jun 05 04:19:34 PM PDT 24
Peak memory 200616 kb
Host smart-e89cb0da-6c83-48ee-b716-6a1144335540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101990630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_noise_filter.3101990630
Directory /workspace/48.uart_noise_filter/latest

Test location /workspace/coverage/default/48.uart_perf.4279718413
Short name T291
Test name
Test status
Simulation time 4816724509 ps
CPU time 274.12 seconds
Started Jun 05 04:17:25 PM PDT 24
Finished Jun 05 04:21:59 PM PDT 24
Peak memory 200380 kb
Host smart-8f097da6-5864-47ca-84a1-afa5eeec1680
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4279718413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.4279718413
Directory /workspace/48.uart_perf/latest

Test location /workspace/coverage/default/48.uart_rx_oversample.150410729
Short name T1057
Test name
Test status
Simulation time 5592579338 ps
CPU time 45.91 seconds
Started Jun 05 04:17:26 PM PDT 24
Finished Jun 05 04:18:12 PM PDT 24
Peak memory 198240 kb
Host smart-43a641b0-bf9f-427d-81b1-f5e03f77b382
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=150410729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.150410729
Directory /workspace/48.uart_rx_oversample/latest

Test location /workspace/coverage/default/48.uart_rx_parity_err.2838837226
Short name T317
Test name
Test status
Simulation time 40660595879 ps
CPU time 19.21 seconds
Started Jun 05 04:17:27 PM PDT 24
Finished Jun 05 04:17:47 PM PDT 24
Peak memory 200452 kb
Host smart-c2263682-e4bf-4acc-a9bd-881b93b3ccba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838837226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.2838837226
Directory /workspace/48.uart_rx_parity_err/latest

Test location /workspace/coverage/default/48.uart_rx_start_bit_filter.792175762
Short name T384
Test name
Test status
Simulation time 39499331975 ps
CPU time 7.69 seconds
Started Jun 05 04:17:31 PM PDT 24
Finished Jun 05 04:17:39 PM PDT 24
Peak memory 196708 kb
Host smart-176bc4e0-b998-49e8-90f9-1cd025878feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792175762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.792175762
Directory /workspace/48.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/48.uart_smoke.1668826792
Short name T976
Test name
Test status
Simulation time 5813789801 ps
CPU time 11.9 seconds
Started Jun 05 04:17:31 PM PDT 24
Finished Jun 05 04:17:43 PM PDT 24
Peak memory 200380 kb
Host smart-65778421-3dc7-479f-8fa1-d247fa04bcf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668826792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_smoke.1668826792
Directory /workspace/48.uart_smoke/latest

Test location /workspace/coverage/default/48.uart_stress_all.921405662
Short name T474
Test name
Test status
Simulation time 278899624590 ps
CPU time 1323.22 seconds
Started Jun 05 04:17:26 PM PDT 24
Finished Jun 05 04:39:30 PM PDT 24
Peak memory 200380 kb
Host smart-80b94bbf-d489-4cc3-8f03-405a88de12af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921405662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.921405662
Directory /workspace/48.uart_stress_all/latest

Test location /workspace/coverage/default/48.uart_stress_all_with_rand_reset.970331271
Short name T756
Test name
Test status
Simulation time 215390026778 ps
CPU time 733.74 seconds
Started Jun 05 04:17:27 PM PDT 24
Finished Jun 05 04:29:41 PM PDT 24
Peak memory 216872 kb
Host smart-536ae93b-4eea-4876-89fb-1bd2a15dc65f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970331271 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 48.uart_stress_all_with_rand_reset.970331271
Directory /workspace/48.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.uart_tx_ovrd.3003802211
Short name T611
Test name
Test status
Simulation time 536410177 ps
CPU time 1.99 seconds
Started Jun 05 04:17:29 PM PDT 24
Finished Jun 05 04:17:32 PM PDT 24
Peak memory 199720 kb
Host smart-c97ae3d5-601a-4ce4-8c0e-47d2f310d18d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003802211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.3003802211
Directory /workspace/48.uart_tx_ovrd/latest

Test location /workspace/coverage/default/48.uart_tx_rx.2630884854
Short name T916
Test name
Test status
Simulation time 82555061123 ps
CPU time 70.2 seconds
Started Jun 05 04:17:25 PM PDT 24
Finished Jun 05 04:18:35 PM PDT 24
Peak memory 200356 kb
Host smart-be8720ac-a760-4619-afca-ed2d9f22f614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630884854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.2630884854
Directory /workspace/48.uart_tx_rx/latest

Test location /workspace/coverage/default/49.uart_alert_test.307304863
Short name T615
Test name
Test status
Simulation time 20467196 ps
CPU time 0.55 seconds
Started Jun 05 04:17:25 PM PDT 24
Finished Jun 05 04:17:27 PM PDT 24
Peak memory 195760 kb
Host smart-291b75b5-b7d9-48f3-90ca-bb9d90419c4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307304863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.307304863
Directory /workspace/49.uart_alert_test/latest

Test location /workspace/coverage/default/49.uart_fifo_full.2837641095
Short name T852
Test name
Test status
Simulation time 43313496397 ps
CPU time 22.31 seconds
Started Jun 05 04:17:25 PM PDT 24
Finished Jun 05 04:17:48 PM PDT 24
Peak memory 200432 kb
Host smart-e4ebf45e-9b49-42b9-a1be-232eb341c629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837641095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.2837641095
Directory /workspace/49.uart_fifo_full/latest

Test location /workspace/coverage/default/49.uart_fifo_overflow.245547344
Short name T312
Test name
Test status
Simulation time 266256159809 ps
CPU time 136.49 seconds
Started Jun 05 04:17:26 PM PDT 24
Finished Jun 05 04:19:43 PM PDT 24
Peak memory 200368 kb
Host smart-9f4eb2d0-cff2-4b2d-81c7-5e64a4cbf9d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245547344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.245547344
Directory /workspace/49.uart_fifo_overflow/latest

Test location /workspace/coverage/default/49.uart_fifo_reset.2870134800
Short name T864
Test name
Test status
Simulation time 9274684428 ps
CPU time 14.24 seconds
Started Jun 05 04:17:25 PM PDT 24
Finished Jun 05 04:17:39 PM PDT 24
Peak memory 200396 kb
Host smart-72dd9796-a6d6-445d-a50d-0b3d78a24b79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870134800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.2870134800
Directory /workspace/49.uart_fifo_reset/latest

Test location /workspace/coverage/default/49.uart_intr.2148689331
Short name T315
Test name
Test status
Simulation time 261597091950 ps
CPU time 449.63 seconds
Started Jun 05 04:17:29 PM PDT 24
Finished Jun 05 04:24:59 PM PDT 24
Peak memory 200372 kb
Host smart-69fe988b-d03d-4924-a9c3-02bb14a05d35
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148689331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.2148689331
Directory /workspace/49.uart_intr/latest

Test location /workspace/coverage/default/49.uart_long_xfer_wo_dly.640077353
Short name T371
Test name
Test status
Simulation time 192387615214 ps
CPU time 505.67 seconds
Started Jun 05 04:17:26 PM PDT 24
Finished Jun 05 04:25:52 PM PDT 24
Peak memory 200376 kb
Host smart-520b1e6c-dcf6-4e7e-b622-e27ade7bb314
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=640077353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.640077353
Directory /workspace/49.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/49.uart_loopback.203913054
Short name T323
Test name
Test status
Simulation time 1926540332 ps
CPU time 2.61 seconds
Started Jun 05 04:17:29 PM PDT 24
Finished Jun 05 04:17:32 PM PDT 24
Peak memory 197524 kb
Host smart-e8b0f207-a972-4e24-8276-49b2b25a512f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203913054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_loopback.203913054
Directory /workspace/49.uart_loopback/latest

Test location /workspace/coverage/default/49.uart_noise_filter.2185727114
Short name T90
Test name
Test status
Simulation time 35774263176 ps
CPU time 15.18 seconds
Started Jun 05 04:17:29 PM PDT 24
Finished Jun 05 04:17:44 PM PDT 24
Peak memory 200580 kb
Host smart-4ff786ec-8ab9-4bd2-812b-8bbd87fe0032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185727114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_noise_filter.2185727114
Directory /workspace/49.uart_noise_filter/latest

Test location /workspace/coverage/default/49.uart_perf.3277524455
Short name T519
Test name
Test status
Simulation time 11396397863 ps
CPU time 309.3 seconds
Started Jun 05 04:17:25 PM PDT 24
Finished Jun 05 04:22:35 PM PDT 24
Peak memory 200428 kb
Host smart-c7c1a5fc-e01e-4380-9f00-0ded20682a1a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3277524455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.3277524455
Directory /workspace/49.uart_perf/latest

Test location /workspace/coverage/default/49.uart_rx_oversample.1672303141
Short name T521
Test name
Test status
Simulation time 4631581597 ps
CPU time 9.72 seconds
Started Jun 05 04:17:31 PM PDT 24
Finished Jun 05 04:17:42 PM PDT 24
Peak memory 199500 kb
Host smart-1214a4d5-b66b-46ba-a66b-e14de3dbe757
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1672303141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.1672303141
Directory /workspace/49.uart_rx_oversample/latest

Test location /workspace/coverage/default/49.uart_rx_parity_err.3843217321
Short name T148
Test name
Test status
Simulation time 62117593773 ps
CPU time 105.74 seconds
Started Jun 05 04:17:29 PM PDT 24
Finished Jun 05 04:19:15 PM PDT 24
Peak memory 200352 kb
Host smart-7dfdb855-42d3-4bcd-89e6-b83ad6aee6cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843217321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.3843217321
Directory /workspace/49.uart_rx_parity_err/latest

Test location /workspace/coverage/default/49.uart_rx_start_bit_filter.1045928072
Short name T929
Test name
Test status
Simulation time 4582074646 ps
CPU time 2.32 seconds
Started Jun 05 04:17:25 PM PDT 24
Finished Jun 05 04:17:29 PM PDT 24
Peak memory 196436 kb
Host smart-296eedea-05ee-4d96-a9a7-0aa47433b992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045928072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.1045928072
Directory /workspace/49.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/49.uart_smoke.834550554
Short name T653
Test name
Test status
Simulation time 291263539 ps
CPU time 0.98 seconds
Started Jun 05 04:17:25 PM PDT 24
Finished Jun 05 04:17:27 PM PDT 24
Peak memory 198332 kb
Host smart-a4371fa5-097e-4f9f-b8c7-d597ee7e2af7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834550554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_smoke.834550554
Directory /workspace/49.uart_smoke/latest

Test location /workspace/coverage/default/49.uart_stress_all.3020445013
Short name T661
Test name
Test status
Simulation time 111645703907 ps
CPU time 244.98 seconds
Started Jun 05 04:17:31 PM PDT 24
Finished Jun 05 04:21:37 PM PDT 24
Peak memory 208820 kb
Host smart-78299498-1dc0-4cdb-bdbe-5b8490103ac9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020445013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.3020445013
Directory /workspace/49.uart_stress_all/latest

Test location /workspace/coverage/default/49.uart_tx_ovrd.2938405172
Short name T609
Test name
Test status
Simulation time 792750552 ps
CPU time 2.72 seconds
Started Jun 05 04:17:24 PM PDT 24
Finished Jun 05 04:17:27 PM PDT 24
Peak memory 199244 kb
Host smart-026eaf27-6c5c-4dde-8a7e-bc299e76402c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938405172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.2938405172
Directory /workspace/49.uart_tx_ovrd/latest

Test location /workspace/coverage/default/49.uart_tx_rx.3171977562
Short name T1018
Test name
Test status
Simulation time 65366612929 ps
CPU time 88.23 seconds
Started Jun 05 04:17:24 PM PDT 24
Finished Jun 05 04:18:53 PM PDT 24
Peak memory 200444 kb
Host smart-b52c87a7-99df-4c49-8d9c-55e3f3756125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171977562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.3171977562
Directory /workspace/49.uart_tx_rx/latest

Test location /workspace/coverage/default/5.uart_alert_test.2504497648
Short name T688
Test name
Test status
Simulation time 58490624 ps
CPU time 0.56 seconds
Started Jun 05 04:15:07 PM PDT 24
Finished Jun 05 04:15:08 PM PDT 24
Peak memory 195780 kb
Host smart-b232baf2-c57c-492d-a11c-335119faa9ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504497648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.2504497648
Directory /workspace/5.uart_alert_test/latest

Test location /workspace/coverage/default/5.uart_fifo_full.2239569442
Short name T966
Test name
Test status
Simulation time 78681597383 ps
CPU time 41.03 seconds
Started Jun 05 04:14:46 PM PDT 24
Finished Jun 05 04:15:28 PM PDT 24
Peak memory 200436 kb
Host smart-b6a8f5e5-d46e-4ae9-b525-325137cf5be7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239569442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.2239569442
Directory /workspace/5.uart_fifo_full/latest

Test location /workspace/coverage/default/5.uart_fifo_overflow.1210042647
Short name T963
Test name
Test status
Simulation time 165873396955 ps
CPU time 165.44 seconds
Started Jun 05 04:14:53 PM PDT 24
Finished Jun 05 04:17:39 PM PDT 24
Peak memory 200392 kb
Host smart-66f09b13-678a-4a57-ac1e-4c22dce7affb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210042647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.1210042647
Directory /workspace/5.uart_fifo_overflow/latest

Test location /workspace/coverage/default/5.uart_fifo_reset.1189328308
Short name T238
Test name
Test status
Simulation time 111795951342 ps
CPU time 29.22 seconds
Started Jun 05 04:14:50 PM PDT 24
Finished Jun 05 04:15:20 PM PDT 24
Peak memory 200448 kb
Host smart-042f7b25-b25a-4d7a-ad6a-2d20eaecd4d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189328308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.1189328308
Directory /workspace/5.uart_fifo_reset/latest

Test location /workspace/coverage/default/5.uart_intr.918029672
Short name T692
Test name
Test status
Simulation time 24264181892 ps
CPU time 13.62 seconds
Started Jun 05 04:14:50 PM PDT 24
Finished Jun 05 04:15:05 PM PDT 24
Peak memory 200328 kb
Host smart-ba36cf69-7dfe-41a7-949f-9a2a8c6e622e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918029672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.918029672
Directory /workspace/5.uart_intr/latest

Test location /workspace/coverage/default/5.uart_long_xfer_wo_dly.2778680600
Short name T1023
Test name
Test status
Simulation time 67435259413 ps
CPU time 254.94 seconds
Started Jun 05 04:15:08 PM PDT 24
Finished Jun 05 04:19:24 PM PDT 24
Peak memory 200424 kb
Host smart-17905864-49b3-48d4-a2d8-e81a29f17dce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2778680600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.2778680600
Directory /workspace/5.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/5.uart_loopback.2591210111
Short name T343
Test name
Test status
Simulation time 9529488556 ps
CPU time 3.43 seconds
Started Jun 05 04:14:50 PM PDT 24
Finished Jun 05 04:14:54 PM PDT 24
Peak memory 200056 kb
Host smart-95ff24ca-7704-44d8-908a-119f236dbd89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591210111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_loopback.2591210111
Directory /workspace/5.uart_loopback/latest

Test location /workspace/coverage/default/5.uart_noise_filter.354783682
Short name T310
Test name
Test status
Simulation time 11624451469 ps
CPU time 20.47 seconds
Started Jun 05 04:14:47 PM PDT 24
Finished Jun 05 04:15:08 PM PDT 24
Peak memory 200388 kb
Host smart-8d742c0e-c69d-40af-881e-e0f34d80c802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354783682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_noise_filter.354783682
Directory /workspace/5.uart_noise_filter/latest

Test location /workspace/coverage/default/5.uart_perf.2397884474
Short name T755
Test name
Test status
Simulation time 13717869988 ps
CPU time 439.7 seconds
Started Jun 05 04:14:50 PM PDT 24
Finished Jun 05 04:22:10 PM PDT 24
Peak memory 200360 kb
Host smart-5b22388b-257f-4802-ba75-e8440b269049
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2397884474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.2397884474
Directory /workspace/5.uart_perf/latest

Test location /workspace/coverage/default/5.uart_rx_oversample.3853380198
Short name T411
Test name
Test status
Simulation time 7049670296 ps
CPU time 17.78 seconds
Started Jun 05 04:14:52 PM PDT 24
Finished Jun 05 04:15:10 PM PDT 24
Peak memory 198548 kb
Host smart-b6d8fd44-d8d3-45fa-af4a-8fdd6a1e37a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3853380198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.3853380198
Directory /workspace/5.uart_rx_oversample/latest

Test location /workspace/coverage/default/5.uart_rx_parity_err.1858250176
Short name T1026
Test name
Test status
Simulation time 52614146300 ps
CPU time 24.22 seconds
Started Jun 05 04:14:46 PM PDT 24
Finished Jun 05 04:15:11 PM PDT 24
Peak memory 200308 kb
Host smart-c101aa47-3654-4e61-936e-ce470c518a62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858250176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.1858250176
Directory /workspace/5.uart_rx_parity_err/latest

Test location /workspace/coverage/default/5.uart_rx_start_bit_filter.3023312219
Short name T1007
Test name
Test status
Simulation time 3928433717 ps
CPU time 7.24 seconds
Started Jun 05 04:14:52 PM PDT 24
Finished Jun 05 04:15:00 PM PDT 24
Peak memory 196328 kb
Host smart-5bb40f15-24b9-4fb4-8884-cbac4ef99d25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023312219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.3023312219
Directory /workspace/5.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/5.uart_smoke.1572567528
Short name T972
Test name
Test status
Simulation time 712674496 ps
CPU time 4.78 seconds
Started Jun 05 04:14:52 PM PDT 24
Finished Jun 05 04:14:58 PM PDT 24
Peak memory 198744 kb
Host smart-142a1c75-37b0-4638-834b-dc7f63293927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572567528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_smoke.1572567528
Directory /workspace/5.uart_smoke/latest

Test location /workspace/coverage/default/5.uart_stress_all.619865424
Short name T763
Test name
Test status
Simulation time 367582777910 ps
CPU time 269.26 seconds
Started Jun 05 04:14:52 PM PDT 24
Finished Jun 05 04:19:22 PM PDT 24
Peak memory 200444 kb
Host smart-ec057099-6198-406d-a450-e93a972d4334
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619865424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.619865424
Directory /workspace/5.uart_stress_all/latest

Test location /workspace/coverage/default/5.uart_stress_all_with_rand_reset.2253287135
Short name T321
Test name
Test status
Simulation time 218488225814 ps
CPU time 875.25 seconds
Started Jun 05 04:14:59 PM PDT 24
Finished Jun 05 04:29:35 PM PDT 24
Peak memory 229872 kb
Host smart-84d777c6-608e-4b87-945d-72666d99a827
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253287135 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 5.uart_stress_all_with_rand_reset.2253287135
Directory /workspace/5.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.uart_tx_ovrd.1574997550
Short name T707
Test name
Test status
Simulation time 1086888814 ps
CPU time 2.56 seconds
Started Jun 05 04:14:56 PM PDT 24
Finished Jun 05 04:15:00 PM PDT 24
Peak memory 199228 kb
Host smart-d8181f76-8685-4818-a13b-593ac4e62139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574997550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.1574997550
Directory /workspace/5.uart_tx_ovrd/latest

Test location /workspace/coverage/default/5.uart_tx_rx.1325844085
Short name T893
Test name
Test status
Simulation time 169990278858 ps
CPU time 126.17 seconds
Started Jun 05 04:15:07 PM PDT 24
Finished Jun 05 04:17:14 PM PDT 24
Peak memory 200384 kb
Host smart-420ff10f-33fe-4f40-8f75-bcbe5af0b07b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325844085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.1325844085
Directory /workspace/5.uart_tx_rx/latest

Test location /workspace/coverage/default/50.uart_fifo_reset.3857195375
Short name T246
Test name
Test status
Simulation time 57220335503 ps
CPU time 38.13 seconds
Started Jun 05 04:17:25 PM PDT 24
Finished Jun 05 04:18:04 PM PDT 24
Peak memory 200376 kb
Host smart-5812d39e-cb2f-4945-8104-3ce7d5932bed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857195375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.3857195375
Directory /workspace/50.uart_fifo_reset/latest

Test location /workspace/coverage/default/50.uart_stress_all_with_rand_reset.680198890
Short name T110
Test name
Test status
Simulation time 9904362234 ps
CPU time 28.86 seconds
Started Jun 05 04:17:24 PM PDT 24
Finished Jun 05 04:17:53 PM PDT 24
Peak memory 216236 kb
Host smart-43d25baa-3c69-4283-93b3-5fba3cd86d9e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680198890 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 50.uart_stress_all_with_rand_reset.680198890
Directory /workspace/50.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/51.uart_fifo_reset.1101096136
Short name T627
Test name
Test status
Simulation time 34467310558 ps
CPU time 20.56 seconds
Started Jun 05 04:17:33 PM PDT 24
Finished Jun 05 04:17:54 PM PDT 24
Peak memory 200376 kb
Host smart-07af780d-f048-4800-9869-9692fec40885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101096136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.1101096136
Directory /workspace/51.uart_fifo_reset/latest

Test location /workspace/coverage/default/51.uart_stress_all_with_rand_reset.2980940606
Short name T854
Test name
Test status
Simulation time 11753872055 ps
CPU time 101.53 seconds
Started Jun 05 04:17:33 PM PDT 24
Finished Jun 05 04:19:15 PM PDT 24
Peak memory 216876 kb
Host smart-7b64023f-27c8-4c3d-aa21-39fe4c1377a4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980940606 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 51.uart_stress_all_with_rand_reset.2980940606
Directory /workspace/51.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.uart_fifo_reset.3300236389
Short name T789
Test name
Test status
Simulation time 16680257770 ps
CPU time 15.79 seconds
Started Jun 05 04:17:33 PM PDT 24
Finished Jun 05 04:17:50 PM PDT 24
Peak memory 200380 kb
Host smart-a73a43dd-f3c7-403c-b84b-3bf03d917093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300236389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.3300236389
Directory /workspace/52.uart_fifo_reset/latest

Test location /workspace/coverage/default/52.uart_stress_all_with_rand_reset.1637567370
Short name T243
Test name
Test status
Simulation time 205435386065 ps
CPU time 1431.49 seconds
Started Jun 05 04:17:31 PM PDT 24
Finished Jun 05 04:41:24 PM PDT 24
Peak memory 219856 kb
Host smart-89a88c5b-e74b-4cb3-b998-86bf007c6c8d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637567370 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 52.uart_stress_all_with_rand_reset.1637567370
Directory /workspace/52.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/53.uart_fifo_reset.3159599933
Short name T833
Test name
Test status
Simulation time 13524016019 ps
CPU time 24.58 seconds
Started Jun 05 04:17:33 PM PDT 24
Finished Jun 05 04:17:59 PM PDT 24
Peak memory 200356 kb
Host smart-0db8b281-3a45-42ea-bbc0-3c2dcde43c38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159599933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.3159599933
Directory /workspace/53.uart_fifo_reset/latest

Test location /workspace/coverage/default/53.uart_stress_all_with_rand_reset.3940436099
Short name T1035
Test name
Test status
Simulation time 66422927761 ps
CPU time 589.44 seconds
Started Jun 05 04:17:32 PM PDT 24
Finished Jun 05 04:27:22 PM PDT 24
Peak memory 216924 kb
Host smart-398b2623-b8da-46e9-b338-87fcb7c19325
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940436099 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 53.uart_stress_all_with_rand_reset.3940436099
Directory /workspace/53.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.uart_fifo_reset.2240588494
Short name T826
Test name
Test status
Simulation time 86760494280 ps
CPU time 139.19 seconds
Started Jun 05 04:17:31 PM PDT 24
Finished Jun 05 04:19:51 PM PDT 24
Peak memory 200356 kb
Host smart-bca31c9d-b83f-4901-80ed-e2cc4b5d5e61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240588494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.2240588494
Directory /workspace/54.uart_fifo_reset/latest

Test location /workspace/coverage/default/54.uart_stress_all_with_rand_reset.445429374
Short name T61
Test name
Test status
Simulation time 188443154849 ps
CPU time 602.62 seconds
Started Jun 05 04:17:33 PM PDT 24
Finished Jun 05 04:27:37 PM PDT 24
Peak memory 225296 kb
Host smart-823dd090-6c41-4e54-881c-924ca06f6437
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445429374 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 54.uart_stress_all_with_rand_reset.445429374
Directory /workspace/54.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.uart_fifo_reset.878784804
Short name T250
Test name
Test status
Simulation time 46140287018 ps
CPU time 49.08 seconds
Started Jun 05 04:17:33 PM PDT 24
Finished Jun 05 04:18:22 PM PDT 24
Peak memory 200356 kb
Host smart-8c816342-3bcf-4d12-9fd5-583df60fbf3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878784804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.878784804
Directory /workspace/55.uart_fifo_reset/latest

Test location /workspace/coverage/default/55.uart_stress_all_with_rand_reset.2281823421
Short name T431
Test name
Test status
Simulation time 92325629285 ps
CPU time 739.17 seconds
Started Jun 05 04:17:33 PM PDT 24
Finished Jun 05 04:29:53 PM PDT 24
Peak memory 216860 kb
Host smart-813f3254-9ab7-42a6-b17f-bf866b694d97
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281823421 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 55.uart_stress_all_with_rand_reset.2281823421
Directory /workspace/55.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/56.uart_fifo_reset.165645863
Short name T1111
Test name
Test status
Simulation time 31167199905 ps
CPU time 129.22 seconds
Started Jun 05 04:17:31 PM PDT 24
Finished Jun 05 04:19:41 PM PDT 24
Peak memory 200452 kb
Host smart-86a13022-479a-4739-87ec-23efe92f7248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165645863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.165645863
Directory /workspace/56.uart_fifo_reset/latest

Test location /workspace/coverage/default/56.uart_stress_all_with_rand_reset.2305090861
Short name T115
Test name
Test status
Simulation time 47425948051 ps
CPU time 263.62 seconds
Started Jun 05 04:17:32 PM PDT 24
Finished Jun 05 04:21:56 PM PDT 24
Peak memory 216944 kb
Host smart-56ec654f-786e-433a-8e2f-e15ca13523e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305090861 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 56.uart_stress_all_with_rand_reset.2305090861
Directory /workspace/56.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.uart_fifo_reset.1901747278
Short name T1053
Test name
Test status
Simulation time 61331598627 ps
CPU time 37.13 seconds
Started Jun 05 04:17:34 PM PDT 24
Finished Jun 05 04:18:12 PM PDT 24
Peak memory 200460 kb
Host smart-5f2d998f-3228-4458-9747-88ed37d1c139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901747278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.1901747278
Directory /workspace/57.uart_fifo_reset/latest

Test location /workspace/coverage/default/57.uart_stress_all_with_rand_reset.2734644867
Short name T496
Test name
Test status
Simulation time 166660825679 ps
CPU time 192.15 seconds
Started Jun 05 04:17:33 PM PDT 24
Finished Jun 05 04:20:46 PM PDT 24
Peak memory 216100 kb
Host smart-18a22d41-0346-4730-a79a-86c888c906b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734644867 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 57.uart_stress_all_with_rand_reset.2734644867
Directory /workspace/57.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/58.uart_fifo_reset.2868430630
Short name T208
Test name
Test status
Simulation time 107596499782 ps
CPU time 173.65 seconds
Started Jun 05 04:17:33 PM PDT 24
Finished Jun 05 04:20:28 PM PDT 24
Peak memory 200416 kb
Host smart-335523f6-31c0-4cda-9691-d83bfda70e9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868430630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.2868430630
Directory /workspace/58.uart_fifo_reset/latest

Test location /workspace/coverage/default/58.uart_stress_all_with_rand_reset.1643321193
Short name T932
Test name
Test status
Simulation time 81087023435 ps
CPU time 944.12 seconds
Started Jun 05 04:17:33 PM PDT 24
Finished Jun 05 04:33:18 PM PDT 24
Peak memory 225292 kb
Host smart-4bf63d4c-061b-47f7-8e7c-7b61318755ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643321193 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 58.uart_stress_all_with_rand_reset.1643321193
Directory /workspace/58.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/59.uart_fifo_reset.1174812895
Short name T453
Test name
Test status
Simulation time 89185804609 ps
CPU time 31.2 seconds
Started Jun 05 04:17:33 PM PDT 24
Finished Jun 05 04:18:05 PM PDT 24
Peak memory 200360 kb
Host smart-46b192fa-c686-46f6-b502-ed3eb248083a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174812895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.1174812895
Directory /workspace/59.uart_fifo_reset/latest

Test location /workspace/coverage/default/59.uart_stress_all_with_rand_reset.3893241078
Short name T628
Test name
Test status
Simulation time 120263692750 ps
CPU time 858.41 seconds
Started Jun 05 04:17:33 PM PDT 24
Finished Jun 05 04:31:52 PM PDT 24
Peak memory 225208 kb
Host smart-028159fd-b869-459f-a1ce-7b544ede549d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893241078 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 59.uart_stress_all_with_rand_reset.3893241078
Directory /workspace/59.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_alert_test.3434625112
Short name T588
Test name
Test status
Simulation time 12914716 ps
CPU time 0.57 seconds
Started Jun 05 04:14:48 PM PDT 24
Finished Jun 05 04:14:49 PM PDT 24
Peak memory 195804 kb
Host smart-cc84c4f5-25a8-4ad8-aa7e-34c754727b18
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434625112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.3434625112
Directory /workspace/6.uart_alert_test/latest

Test location /workspace/coverage/default/6.uart_fifo_full.4031539824
Short name T270
Test name
Test status
Simulation time 101910785912 ps
CPU time 279.97 seconds
Started Jun 05 04:14:53 PM PDT 24
Finished Jun 05 04:19:34 PM PDT 24
Peak memory 200424 kb
Host smart-a502181f-ba78-451d-941d-197f41c5d504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031539824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.4031539824
Directory /workspace/6.uart_fifo_full/latest

Test location /workspace/coverage/default/6.uart_fifo_overflow.3460973877
Short name T947
Test name
Test status
Simulation time 35543816264 ps
CPU time 42.89 seconds
Started Jun 05 04:15:11 PM PDT 24
Finished Jun 05 04:15:55 PM PDT 24
Peak memory 200400 kb
Host smart-6f47c4db-ebf0-4095-9a24-d937d22209be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460973877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.3460973877
Directory /workspace/6.uart_fifo_overflow/latest

Test location /workspace/coverage/default/6.uart_fifo_reset.4091332934
Short name T205
Test name
Test status
Simulation time 27664650754 ps
CPU time 57.77 seconds
Started Jun 05 04:14:47 PM PDT 24
Finished Jun 05 04:15:45 PM PDT 24
Peak memory 200312 kb
Host smart-a79af750-8f1f-4004-aace-e8e7fe818421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091332934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.4091332934
Directory /workspace/6.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_intr.2073074758
Short name T446
Test name
Test status
Simulation time 227036608673 ps
CPU time 128.19 seconds
Started Jun 05 04:15:10 PM PDT 24
Finished Jun 05 04:17:20 PM PDT 24
Peak memory 200212 kb
Host smart-f9a9cdff-42f9-4625-b7c0-fe5a9f67c1e5
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073074758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.2073074758
Directory /workspace/6.uart_intr/latest

Test location /workspace/coverage/default/6.uart_long_xfer_wo_dly.925177097
Short name T354
Test name
Test status
Simulation time 81693524164 ps
CPU time 447.27 seconds
Started Jun 05 04:15:10 PM PDT 24
Finished Jun 05 04:22:39 PM PDT 24
Peak memory 200424 kb
Host smart-a9319b94-fa3f-42a4-a225-ebbceacbc841
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=925177097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.925177097
Directory /workspace/6.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/6.uart_loopback.4088275312
Short name T107
Test name
Test status
Simulation time 3971632252 ps
CPU time 2.69 seconds
Started Jun 05 04:14:56 PM PDT 24
Finished Jun 05 04:15:00 PM PDT 24
Peak memory 199708 kb
Host smart-306e19c5-b29e-463f-b70a-f2b37e0561f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088275312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_loopback.4088275312
Directory /workspace/6.uart_loopback/latest

Test location /workspace/coverage/default/6.uart_noise_filter.936098741
Short name T117
Test name
Test status
Simulation time 149044710025 ps
CPU time 70.67 seconds
Started Jun 05 04:14:57 PM PDT 24
Finished Jun 05 04:16:08 PM PDT 24
Peak memory 200628 kb
Host smart-d384e768-3dc4-492b-abdf-0a1a1cf98e76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936098741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_noise_filter.936098741
Directory /workspace/6.uart_noise_filter/latest

Test location /workspace/coverage/default/6.uart_perf.904869262
Short name T752
Test name
Test status
Simulation time 32578913464 ps
CPU time 867.36 seconds
Started Jun 05 04:15:11 PM PDT 24
Finished Jun 05 04:29:49 PM PDT 24
Peak memory 200376 kb
Host smart-77328919-9740-4b67-a782-63f7bbba49ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=904869262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.904869262
Directory /workspace/6.uart_perf/latest

Test location /workspace/coverage/default/6.uart_rx_oversample.3639955264
Short name T623
Test name
Test status
Simulation time 2661452105 ps
CPU time 4.93 seconds
Started Jun 05 04:15:03 PM PDT 24
Finished Jun 05 04:15:08 PM PDT 24
Peak memory 200380 kb
Host smart-793a5b00-8630-4bf7-9678-eedc63a77689
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3639955264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.3639955264
Directory /workspace/6.uart_rx_oversample/latest

Test location /workspace/coverage/default/6.uart_rx_parity_err.1444615945
Short name T711
Test name
Test status
Simulation time 91349388901 ps
CPU time 246.3 seconds
Started Jun 05 04:15:08 PM PDT 24
Finished Jun 05 04:19:16 PM PDT 24
Peak memory 200336 kb
Host smart-dfc3f400-6934-469e-b19b-4ee88c9de897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444615945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.1444615945
Directory /workspace/6.uart_rx_parity_err/latest

Test location /workspace/coverage/default/6.uart_rx_start_bit_filter.338820172
Short name T1117
Test name
Test status
Simulation time 4358548442 ps
CPU time 2.12 seconds
Started Jun 05 04:14:46 PM PDT 24
Finished Jun 05 04:14:49 PM PDT 24
Peak memory 196848 kb
Host smart-116017c1-78b8-46f3-9a3b-388606f07f98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338820172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.338820172
Directory /workspace/6.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/6.uart_smoke.3009174916
Short name T102
Test name
Test status
Simulation time 6070088781 ps
CPU time 27.78 seconds
Started Jun 05 04:15:08 PM PDT 24
Finished Jun 05 04:15:38 PM PDT 24
Peak memory 200260 kb
Host smart-ca2c3efa-1f75-43e5-8149-c8bc6c509630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009174916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_smoke.3009174916
Directory /workspace/6.uart_smoke/latest

Test location /workspace/coverage/default/6.uart_stress_all_with_rand_reset.3066267746
Short name T57
Test name
Test status
Simulation time 42972816043 ps
CPU time 630.11 seconds
Started Jun 05 04:14:50 PM PDT 24
Finished Jun 05 04:25:21 PM PDT 24
Peak memory 217096 kb
Host smart-a05d61d1-d704-43e3-8e49-c33c3d3f67c2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066267746 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 6.uart_stress_all_with_rand_reset.3066267746
Directory /workspace/6.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_tx_ovrd.3944699455
Short name T512
Test name
Test status
Simulation time 977722750 ps
CPU time 5.9 seconds
Started Jun 05 04:15:05 PM PDT 24
Finished Jun 05 04:15:12 PM PDT 24
Peak memory 199480 kb
Host smart-7ebe7798-8098-4a37-94e3-dc52dba4075d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944699455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.3944699455
Directory /workspace/6.uart_tx_ovrd/latest

Test location /workspace/coverage/default/6.uart_tx_rx.2062211628
Short name T424
Test name
Test status
Simulation time 35135713987 ps
CPU time 13.84 seconds
Started Jun 05 04:14:50 PM PDT 24
Finished Jun 05 04:15:05 PM PDT 24
Peak memory 200372 kb
Host smart-62d8f1fa-9c37-47da-ade3-7c1292e5d28c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062211628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.2062211628
Directory /workspace/6.uart_tx_rx/latest

Test location /workspace/coverage/default/60.uart_fifo_reset.2551776387
Short name T773
Test name
Test status
Simulation time 107246050190 ps
CPU time 39.8 seconds
Started Jun 05 04:17:32 PM PDT 24
Finished Jun 05 04:18:12 PM PDT 24
Peak memory 200448 kb
Host smart-dfb35d4c-1c7e-44b1-84d8-e7f4b7e92508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551776387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.2551776387
Directory /workspace/60.uart_fifo_reset/latest

Test location /workspace/coverage/default/60.uart_stress_all_with_rand_reset.2066145755
Short name T1085
Test name
Test status
Simulation time 211927201071 ps
CPU time 1072.91 seconds
Started Jun 05 04:17:33 PM PDT 24
Finished Jun 05 04:35:27 PM PDT 24
Peak memory 215872 kb
Host smart-76dbe455-9c28-4b6f-a752-b3dc13521e29
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066145755 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 60.uart_stress_all_with_rand_reset.2066145755
Directory /workspace/60.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/61.uart_fifo_reset.2820097508
Short name T206
Test name
Test status
Simulation time 26342701101 ps
CPU time 47.93 seconds
Started Jun 05 04:17:32 PM PDT 24
Finished Jun 05 04:18:21 PM PDT 24
Peak memory 200464 kb
Host smart-bddd9398-92cd-4220-a515-4ecf4299d446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820097508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.2820097508
Directory /workspace/61.uart_fifo_reset/latest

Test location /workspace/coverage/default/61.uart_stress_all_with_rand_reset.280851245
Short name T153
Test name
Test status
Simulation time 287984538590 ps
CPU time 1394.48 seconds
Started Jun 05 04:17:31 PM PDT 24
Finished Jun 05 04:40:47 PM PDT 24
Peak memory 217264 kb
Host smart-198c766a-beb0-4a91-bcad-28f2f72cb0b2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280851245 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 61.uart_stress_all_with_rand_reset.280851245
Directory /workspace/61.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.uart_fifo_reset.1987990017
Short name T702
Test name
Test status
Simulation time 423877145238 ps
CPU time 106.33 seconds
Started Jun 05 04:17:33 PM PDT 24
Finished Jun 05 04:19:21 PM PDT 24
Peak memory 200400 kb
Host smart-c274f47c-0874-49b7-975d-932e20a0c15a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987990017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.1987990017
Directory /workspace/62.uart_fifo_reset/latest

Test location /workspace/coverage/default/62.uart_stress_all_with_rand_reset.3544686858
Short name T113
Test name
Test status
Simulation time 94225605986 ps
CPU time 322.14 seconds
Started Jun 05 04:17:31 PM PDT 24
Finished Jun 05 04:22:54 PM PDT 24
Peak memory 216852 kb
Host smart-ac6d6364-e03f-4418-a658-8057c795b821
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544686858 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 62.uart_stress_all_with_rand_reset.3544686858
Directory /workspace/62.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.uart_fifo_reset.69207752
Short name T1
Test name
Test status
Simulation time 10185380126 ps
CPU time 12.82 seconds
Started Jun 05 04:17:33 PM PDT 24
Finished Jun 05 04:17:47 PM PDT 24
Peak memory 200456 kb
Host smart-badd2162-2139-4261-91b3-9a2ff0297b7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69207752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.69207752
Directory /workspace/63.uart_fifo_reset/latest

Test location /workspace/coverage/default/63.uart_stress_all_with_rand_reset.2070204849
Short name T901
Test name
Test status
Simulation time 182415964698 ps
CPU time 590.56 seconds
Started Jun 05 04:17:34 PM PDT 24
Finished Jun 05 04:27:25 PM PDT 24
Peak memory 228632 kb
Host smart-549cf92b-e90e-4ba0-893d-ec5a9805189f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070204849 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 63.uart_stress_all_with_rand_reset.2070204849
Directory /workspace/63.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/64.uart_fifo_reset.3496999107
Short name T851
Test name
Test status
Simulation time 62525469289 ps
CPU time 19.52 seconds
Started Jun 05 04:17:33 PM PDT 24
Finished Jun 05 04:17:53 PM PDT 24
Peak memory 200384 kb
Host smart-bfe29492-5c23-4795-b581-8a1c94274100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496999107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.3496999107
Directory /workspace/64.uart_fifo_reset/latest

Test location /workspace/coverage/default/64.uart_stress_all_with_rand_reset.910320414
Short name T116
Test name
Test status
Simulation time 46056047105 ps
CPU time 515.3 seconds
Started Jun 05 04:17:43 PM PDT 24
Finished Jun 05 04:26:19 PM PDT 24
Peak memory 217000 kb
Host smart-46c13d48-8444-4b6c-92fb-410291cbbdb8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910320414 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 64.uart_stress_all_with_rand_reset.910320414
Directory /workspace/64.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/65.uart_fifo_reset.3885581454
Short name T624
Test name
Test status
Simulation time 280276666200 ps
CPU time 460.1 seconds
Started Jun 05 04:17:43 PM PDT 24
Finished Jun 05 04:25:24 PM PDT 24
Peak memory 200376 kb
Host smart-186eed62-4902-49bf-937a-7c9811103d7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885581454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.3885581454
Directory /workspace/65.uart_fifo_reset/latest

Test location /workspace/coverage/default/65.uart_stress_all_with_rand_reset.432789270
Short name T766
Test name
Test status
Simulation time 37379420078 ps
CPU time 375.82 seconds
Started Jun 05 04:17:42 PM PDT 24
Finished Jun 05 04:23:58 PM PDT 24
Peak memory 217040 kb
Host smart-0aa5a595-fd4e-4abe-85ad-dda2517fd762
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432789270 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 65.uart_stress_all_with_rand_reset.432789270
Directory /workspace/65.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/66.uart_fifo_reset.3576309750
Short name T832
Test name
Test status
Simulation time 138115064279 ps
CPU time 252.14 seconds
Started Jun 05 04:17:42 PM PDT 24
Finished Jun 05 04:21:54 PM PDT 24
Peak memory 200420 kb
Host smart-4dcd5759-ed97-4c42-a178-c5dc6c17a6f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576309750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.3576309750
Directory /workspace/66.uart_fifo_reset/latest

Test location /workspace/coverage/default/66.uart_stress_all_with_rand_reset.3860119263
Short name T322
Test name
Test status
Simulation time 99867678010 ps
CPU time 921.55 seconds
Started Jun 05 04:17:46 PM PDT 24
Finished Jun 05 04:33:08 PM PDT 24
Peak memory 230708 kb
Host smart-6d4c47e2-e424-4873-acd1-ed02a1bcd55b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860119263 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 66.uart_stress_all_with_rand_reset.3860119263
Directory /workspace/66.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.uart_fifo_reset.3940822987
Short name T7
Test name
Test status
Simulation time 5746516079 ps
CPU time 9.56 seconds
Started Jun 05 04:17:44 PM PDT 24
Finished Jun 05 04:17:54 PM PDT 24
Peak memory 198372 kb
Host smart-8e8425e2-0abe-47ba-8557-fd84cba545b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940822987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.3940822987
Directory /workspace/67.uart_fifo_reset/latest

Test location /workspace/coverage/default/67.uart_stress_all_with_rand_reset.2130976335
Short name T114
Test name
Test status
Simulation time 127022450344 ps
CPU time 534.87 seconds
Started Jun 05 04:17:43 PM PDT 24
Finished Jun 05 04:26:38 PM PDT 24
Peak memory 225412 kb
Host smart-33d512d2-5477-42b3-8f98-7e3091472dbe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130976335 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 67.uart_stress_all_with_rand_reset.2130976335
Directory /workspace/67.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/68.uart_fifo_reset.3148253778
Short name T213
Test name
Test status
Simulation time 33949630333 ps
CPU time 13.83 seconds
Started Jun 05 04:17:42 PM PDT 24
Finished Jun 05 04:17:57 PM PDT 24
Peak memory 199864 kb
Host smart-96e32429-1310-422a-93dd-e740c5ed4a8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148253778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.3148253778
Directory /workspace/68.uart_fifo_reset/latest

Test location /workspace/coverage/default/68.uart_stress_all_with_rand_reset.568949697
Short name T565
Test name
Test status
Simulation time 230858682238 ps
CPU time 794.4 seconds
Started Jun 05 04:17:46 PM PDT 24
Finished Jun 05 04:31:01 PM PDT 24
Peak memory 230760 kb
Host smart-6f94a383-79a2-4374-bb9c-cb904caed0a2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568949697 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 68.uart_stress_all_with_rand_reset.568949697
Directory /workspace/68.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.uart_fifo_reset.3454268168
Short name T787
Test name
Test status
Simulation time 118022365545 ps
CPU time 46.92 seconds
Started Jun 05 04:17:46 PM PDT 24
Finished Jun 05 04:18:34 PM PDT 24
Peak memory 200288 kb
Host smart-0c314c16-d578-497d-9dfd-746072b81e72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454268168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.3454268168
Directory /workspace/69.uart_fifo_reset/latest

Test location /workspace/coverage/default/69.uart_stress_all_with_rand_reset.3135746228
Short name T1143
Test name
Test status
Simulation time 95381665818 ps
CPU time 564.91 seconds
Started Jun 05 04:17:44 PM PDT 24
Finished Jun 05 04:27:09 PM PDT 24
Peak memory 213808 kb
Host smart-68f81676-8e9c-46a8-b989-38036026c84a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135746228 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 69.uart_stress_all_with_rand_reset.3135746228
Directory /workspace/69.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_alert_test.1639115349
Short name T970
Test name
Test status
Simulation time 31799736 ps
CPU time 0.52 seconds
Started Jun 05 04:14:55 PM PDT 24
Finished Jun 05 04:14:56 PM PDT 24
Peak memory 195792 kb
Host smart-cad057b1-14c4-4c4d-8ccb-e8ba05aecf7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639115349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.1639115349
Directory /workspace/7.uart_alert_test/latest

Test location /workspace/coverage/default/7.uart_fifo_full.3771315198
Short name T547
Test name
Test status
Simulation time 114121124484 ps
CPU time 204.92 seconds
Started Jun 05 04:15:06 PM PDT 24
Finished Jun 05 04:18:32 PM PDT 24
Peak memory 200488 kb
Host smart-b68908df-2805-434f-92e3-69c163d39cfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771315198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.3771315198
Directory /workspace/7.uart_fifo_full/latest

Test location /workspace/coverage/default/7.uart_fifo_overflow.3909867928
Short name T734
Test name
Test status
Simulation time 145315310924 ps
CPU time 73.79 seconds
Started Jun 05 04:15:03 PM PDT 24
Finished Jun 05 04:16:18 PM PDT 24
Peak memory 200444 kb
Host smart-5d51bcef-35d2-403d-8e35-db823f7c55f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909867928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.3909867928
Directory /workspace/7.uart_fifo_overflow/latest

Test location /workspace/coverage/default/7.uart_fifo_reset.4149221213
Short name T300
Test name
Test status
Simulation time 136819401131 ps
CPU time 109.14 seconds
Started Jun 05 04:15:11 PM PDT 24
Finished Jun 05 04:17:01 PM PDT 24
Peak memory 200436 kb
Host smart-31c87c1a-6fee-4761-a47e-ff66751947aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149221213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.4149221213
Directory /workspace/7.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_intr.48470389
Short name T680
Test name
Test status
Simulation time 15852974598 ps
CPU time 24.29 seconds
Started Jun 05 04:15:05 PM PDT 24
Finished Jun 05 04:15:29 PM PDT 24
Peak memory 197384 kb
Host smart-04ae345f-fc77-4717-8c43-a1211fdcddd8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48470389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.48470389
Directory /workspace/7.uart_intr/latest

Test location /workspace/coverage/default/7.uart_long_xfer_wo_dly.3856259844
Short name T877
Test name
Test status
Simulation time 69751227195 ps
CPU time 555.66 seconds
Started Jun 05 04:14:58 PM PDT 24
Finished Jun 05 04:24:14 PM PDT 24
Peak memory 200400 kb
Host smart-0b7dc807-3bcd-4b69-a225-83487743c12b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3856259844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.3856259844
Directory /workspace/7.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/7.uart_loopback.1073582503
Short name T606
Test name
Test status
Simulation time 5208943420 ps
CPU time 5.64 seconds
Started Jun 05 04:15:10 PM PDT 24
Finished Jun 05 04:15:18 PM PDT 24
Peak memory 199712 kb
Host smart-7760585c-ba4f-4fc9-9b09-36592bdaf6b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073582503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_loopback.1073582503
Directory /workspace/7.uart_loopback/latest

Test location /workspace/coverage/default/7.uart_noise_filter.170733827
Short name T1108
Test name
Test status
Simulation time 96250128218 ps
CPU time 173.11 seconds
Started Jun 05 04:14:51 PM PDT 24
Finished Jun 05 04:17:45 PM PDT 24
Peak memory 208304 kb
Host smart-974e44fc-80cf-4709-8569-515c78d6e1a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170733827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_noise_filter.170733827
Directory /workspace/7.uart_noise_filter/latest

Test location /workspace/coverage/default/7.uart_perf.3468868991
Short name T872
Test name
Test status
Simulation time 5890997768 ps
CPU time 151.59 seconds
Started Jun 05 04:14:44 PM PDT 24
Finished Jun 05 04:17:17 PM PDT 24
Peak memory 200396 kb
Host smart-4e22ff34-4ed1-4d4d-88f3-475f06d01e55
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3468868991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.3468868991
Directory /workspace/7.uart_perf/latest

Test location /workspace/coverage/default/7.uart_rx_oversample.2285701670
Short name T74
Test name
Test status
Simulation time 2123794049 ps
CPU time 12.3 seconds
Started Jun 05 04:15:07 PM PDT 24
Finished Jun 05 04:15:20 PM PDT 24
Peak memory 198404 kb
Host smart-d9028ae6-3eb6-4568-a405-0d3c3a21081a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2285701670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.2285701670
Directory /workspace/7.uart_rx_oversample/latest

Test location /workspace/coverage/default/7.uart_rx_parity_err.4026214192
Short name T406
Test name
Test status
Simulation time 8907503415 ps
CPU time 17.92 seconds
Started Jun 05 04:14:51 PM PDT 24
Finished Jun 05 04:15:09 PM PDT 24
Peak memory 199776 kb
Host smart-059d95d1-f319-42e9-817e-7bb0df311558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026214192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.4026214192
Directory /workspace/7.uart_rx_parity_err/latest

Test location /workspace/coverage/default/7.uart_rx_start_bit_filter.2160587164
Short name T961
Test name
Test status
Simulation time 5528384322 ps
CPU time 10.09 seconds
Started Jun 05 04:15:09 PM PDT 24
Finished Jun 05 04:15:21 PM PDT 24
Peak memory 196404 kb
Host smart-73e80601-3a25-4f27-8102-734af2c21978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160587164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.2160587164
Directory /workspace/7.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/7.uart_smoke.3785180019
Short name T1040
Test name
Test status
Simulation time 500072608 ps
CPU time 1.49 seconds
Started Jun 05 04:14:51 PM PDT 24
Finished Jun 05 04:14:54 PM PDT 24
Peak memory 198832 kb
Host smart-105e6095-85fa-4e0f-9acf-f9c79e0fe1f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785180019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_smoke.3785180019
Directory /workspace/7.uart_smoke/latest

Test location /workspace/coverage/default/7.uart_stress_all.6011547
Short name T764
Test name
Test status
Simulation time 103497400300 ps
CPU time 272.68 seconds
Started Jun 05 04:15:06 PM PDT 24
Finished Jun 05 04:19:39 PM PDT 24
Peak memory 200396 kb
Host smart-33e68ae0-e544-4930-9c2c-2bdc048bcd49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6011547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.6011547
Directory /workspace/7.uart_stress_all/latest

Test location /workspace/coverage/default/7.uart_stress_all_with_rand_reset.2533262579
Short name T879
Test name
Test status
Simulation time 199465695560 ps
CPU time 676.37 seconds
Started Jun 05 04:15:06 PM PDT 24
Finished Jun 05 04:26:23 PM PDT 24
Peak memory 226652 kb
Host smart-c4e11bfc-5336-48ef-bf7b-17a8a32f7284
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533262579 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 7.uart_stress_all_with_rand_reset.2533262579
Directory /workspace/7.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_tx_ovrd.431289113
Short name T283
Test name
Test status
Simulation time 6683527419 ps
CPU time 21.25 seconds
Started Jun 05 04:14:49 PM PDT 24
Finished Jun 05 04:15:11 PM PDT 24
Peak memory 200224 kb
Host smart-34013248-b351-4667-84d9-314dc1b37628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431289113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.431289113
Directory /workspace/7.uart_tx_ovrd/latest

Test location /workspace/coverage/default/7.uart_tx_rx.2724538224
Short name T277
Test name
Test status
Simulation time 218258726834 ps
CPU time 39.68 seconds
Started Jun 05 04:14:50 PM PDT 24
Finished Jun 05 04:15:31 PM PDT 24
Peak memory 200348 kb
Host smart-11176ff8-01d0-414d-804a-ae7004a33ad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724538224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.2724538224
Directory /workspace/7.uart_tx_rx/latest

Test location /workspace/coverage/default/70.uart_fifo_reset.4178623773
Short name T366
Test name
Test status
Simulation time 85730356034 ps
CPU time 36.5 seconds
Started Jun 05 04:17:42 PM PDT 24
Finished Jun 05 04:18:19 PM PDT 24
Peak memory 200372 kb
Host smart-e822234e-872b-4e3a-9feb-4b66acff9e64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178623773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.4178623773
Directory /workspace/70.uart_fifo_reset/latest

Test location /workspace/coverage/default/70.uart_stress_all_with_rand_reset.2274260585
Short name T828
Test name
Test status
Simulation time 15364946181 ps
CPU time 177.96 seconds
Started Jun 05 04:17:41 PM PDT 24
Finished Jun 05 04:20:40 PM PDT 24
Peak memory 208616 kb
Host smart-f57854cf-e554-4dd5-afd1-1c717ab18a5a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274260585 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 70.uart_stress_all_with_rand_reset.2274260585
Directory /workspace/70.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/71.uart_fifo_reset.3709495325
Short name T1019
Test name
Test status
Simulation time 155355527791 ps
CPU time 88.52 seconds
Started Jun 05 04:17:42 PM PDT 24
Finished Jun 05 04:19:11 PM PDT 24
Peak memory 200436 kb
Host smart-5a1e60ac-ecec-4c92-97a9-41f2405ff192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709495325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.3709495325
Directory /workspace/71.uart_fifo_reset/latest

Test location /workspace/coverage/default/71.uart_stress_all_with_rand_reset.3682220536
Short name T589
Test name
Test status
Simulation time 1859818810 ps
CPU time 22.12 seconds
Started Jun 05 04:17:43 PM PDT 24
Finished Jun 05 04:18:05 PM PDT 24
Peak memory 200512 kb
Host smart-3e5ae5c2-b106-4985-b263-f53ed7063d4f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682220536 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 71.uart_stress_all_with_rand_reset.3682220536
Directory /workspace/71.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/72.uart_fifo_reset.3196341436
Short name T931
Test name
Test status
Simulation time 92681221437 ps
CPU time 64.33 seconds
Started Jun 05 04:17:42 PM PDT 24
Finished Jun 05 04:18:47 PM PDT 24
Peak memory 200440 kb
Host smart-6b993a5d-2116-4a09-8de8-1ed4cb4c2301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196341436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.3196341436
Directory /workspace/72.uart_fifo_reset/latest

Test location /workspace/coverage/default/72.uart_stress_all_with_rand_reset.3432083139
Short name T60
Test name
Test status
Simulation time 62213567050 ps
CPU time 517.8 seconds
Started Jun 05 04:17:43 PM PDT 24
Finished Jun 05 04:26:21 PM PDT 24
Peak memory 225300 kb
Host smart-6f7ba601-f076-44d4-b455-885c128a283e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432083139 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 72.uart_stress_all_with_rand_reset.3432083139
Directory /workspace/72.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/73.uart_fifo_reset.1298147003
Short name T668
Test name
Test status
Simulation time 117602331894 ps
CPU time 234.45 seconds
Started Jun 05 04:17:42 PM PDT 24
Finished Jun 05 04:21:37 PM PDT 24
Peak memory 200380 kb
Host smart-2a281c3e-8788-48b5-9630-b20134362e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298147003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.1298147003
Directory /workspace/73.uart_fifo_reset/latest

Test location /workspace/coverage/default/73.uart_stress_all_with_rand_reset.4238857926
Short name T16
Test name
Test status
Simulation time 102993149010 ps
CPU time 1209.22 seconds
Started Jun 05 04:17:46 PM PDT 24
Finished Jun 05 04:37:56 PM PDT 24
Peak memory 229048 kb
Host smart-297b839a-d6d6-429e-8b70-481ec96a4f94
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238857926 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 73.uart_stress_all_with_rand_reset.4238857926
Directory /workspace/73.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/74.uart_fifo_reset.2055402211
Short name T420
Test name
Test status
Simulation time 29694218447 ps
CPU time 13.07 seconds
Started Jun 05 04:17:43 PM PDT 24
Finished Jun 05 04:17:57 PM PDT 24
Peak memory 200236 kb
Host smart-9af4b29b-fc0d-4cf8-a497-9141413f156a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055402211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.2055402211
Directory /workspace/74.uart_fifo_reset/latest

Test location /workspace/coverage/default/74.uart_stress_all_with_rand_reset.2675928664
Short name T319
Test name
Test status
Simulation time 30771671702 ps
CPU time 593.78 seconds
Started Jun 05 04:17:43 PM PDT 24
Finished Jun 05 04:27:37 PM PDT 24
Peak memory 215936 kb
Host smart-3c81f2f3-6122-4036-9665-315f495d415d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675928664 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 74.uart_stress_all_with_rand_reset.2675928664
Directory /workspace/74.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.uart_fifo_reset.1429803492
Short name T718
Test name
Test status
Simulation time 118717579276 ps
CPU time 40.32 seconds
Started Jun 05 04:17:46 PM PDT 24
Finished Jun 05 04:18:27 PM PDT 24
Peak memory 200396 kb
Host smart-0d2c6563-01e2-4d00-9d43-5a9093506f6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429803492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.1429803492
Directory /workspace/75.uart_fifo_reset/latest

Test location /workspace/coverage/default/75.uart_stress_all_with_rand_reset.1341698641
Short name T320
Test name
Test status
Simulation time 936243283705 ps
CPU time 650.97 seconds
Started Jun 05 04:17:45 PM PDT 24
Finished Jun 05 04:28:37 PM PDT 24
Peak memory 229884 kb
Host smart-34a1a280-65e0-44f1-83fd-f3006ebfce53
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341698641 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 75.uart_stress_all_with_rand_reset.1341698641
Directory /workspace/75.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/76.uart_fifo_reset.754939107
Short name T517
Test name
Test status
Simulation time 78206798509 ps
CPU time 33.09 seconds
Started Jun 05 04:17:41 PM PDT 24
Finished Jun 05 04:18:15 PM PDT 24
Peak memory 200160 kb
Host smart-36b6c9c3-4e1f-40dd-9ea6-d37be4ffda7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754939107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.754939107
Directory /workspace/76.uart_fifo_reset/latest

Test location /workspace/coverage/default/77.uart_fifo_reset.1404057588
Short name T510
Test name
Test status
Simulation time 215337115108 ps
CPU time 68.72 seconds
Started Jun 05 04:17:47 PM PDT 24
Finished Jun 05 04:18:56 PM PDT 24
Peak memory 200360 kb
Host smart-0b32281c-2e8a-47a6-82b8-5deb5231d5bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404057588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.1404057588
Directory /workspace/77.uart_fifo_reset/latest

Test location /workspace/coverage/default/77.uart_stress_all_with_rand_reset.1148726219
Short name T30
Test name
Test status
Simulation time 131998606551 ps
CPU time 493.44 seconds
Started Jun 05 04:17:43 PM PDT 24
Finished Jun 05 04:25:57 PM PDT 24
Peak memory 216884 kb
Host smart-19f8d25a-5381-4fc9-9373-83f58feaa622
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148726219 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 77.uart_stress_all_with_rand_reset.1148726219
Directory /workspace/77.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/78.uart_fifo_reset.298204770
Short name T682
Test name
Test status
Simulation time 175925087964 ps
CPU time 454.46 seconds
Started Jun 05 04:17:44 PM PDT 24
Finished Jun 05 04:25:19 PM PDT 24
Peak memory 200448 kb
Host smart-c6dba3c3-7059-4be0-86d3-e510b4f60c4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298204770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.298204770
Directory /workspace/78.uart_fifo_reset/latest

Test location /workspace/coverage/default/78.uart_stress_all_with_rand_reset.1084046797
Short name T209
Test name
Test status
Simulation time 347652164554 ps
CPU time 464.4 seconds
Started Jun 05 04:17:50 PM PDT 24
Finished Jun 05 04:25:35 PM PDT 24
Peak memory 225288 kb
Host smart-2ea99d55-9599-4c1e-a3ee-bb664bcf13e5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084046797 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 78.uart_stress_all_with_rand_reset.1084046797
Directory /workspace/78.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.uart_fifo_reset.1546117782
Short name T488
Test name
Test status
Simulation time 38911636445 ps
CPU time 10.78 seconds
Started Jun 05 04:17:53 PM PDT 24
Finished Jun 05 04:18:05 PM PDT 24
Peak memory 200384 kb
Host smart-476cdf95-9bdf-48e8-8f1c-97751e8a482d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546117782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.1546117782
Directory /workspace/79.uart_fifo_reset/latest

Test location /workspace/coverage/default/79.uart_stress_all_with_rand_reset.2281821444
Short name T762
Test name
Test status
Simulation time 42459775205 ps
CPU time 722.23 seconds
Started Jun 05 04:17:51 PM PDT 24
Finished Jun 05 04:29:54 PM PDT 24
Peak memory 216932 kb
Host smart-f5617b1c-c973-47b8-bd3a-3c421c97783d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281821444 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 79.uart_stress_all_with_rand_reset.2281821444
Directory /workspace/79.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_alert_test.23272587
Short name T576
Test name
Test status
Simulation time 22649456 ps
CPU time 0.57 seconds
Started Jun 05 04:15:07 PM PDT 24
Finished Jun 05 04:15:09 PM PDT 24
Peak memory 195784 kb
Host smart-f805b1c5-23fa-494c-9dab-ace533680460
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23272587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.23272587
Directory /workspace/8.uart_alert_test/latest

Test location /workspace/coverage/default/8.uart_fifo_full.2272068077
Short name T499
Test name
Test status
Simulation time 140938474028 ps
CPU time 196.16 seconds
Started Jun 05 04:15:10 PM PDT 24
Finished Jun 05 04:18:28 PM PDT 24
Peak memory 200408 kb
Host smart-1895f567-0079-42a3-8569-afa1521a24b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272068077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.2272068077
Directory /workspace/8.uart_fifo_full/latest

Test location /workspace/coverage/default/8.uart_fifo_overflow.802798488
Short name T71
Test name
Test status
Simulation time 55458521343 ps
CPU time 83.53 seconds
Started Jun 05 04:15:09 PM PDT 24
Finished Jun 05 04:16:35 PM PDT 24
Peak memory 200364 kb
Host smart-292bfdfa-3d0c-410e-884a-c5ce777120af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802798488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.802798488
Directory /workspace/8.uart_fifo_overflow/latest

Test location /workspace/coverage/default/8.uart_fifo_reset.1164480658
Short name T222
Test name
Test status
Simulation time 91757588921 ps
CPU time 43.05 seconds
Started Jun 05 04:14:59 PM PDT 24
Finished Jun 05 04:15:42 PM PDT 24
Peak memory 200392 kb
Host smart-05a91c32-b97f-4b67-8094-3ff20fbd2bed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164480658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.1164480658
Directory /workspace/8.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_intr.1562039008
Short name T318
Test name
Test status
Simulation time 59044741301 ps
CPU time 22.28 seconds
Started Jun 05 04:15:10 PM PDT 24
Finished Jun 05 04:15:34 PM PDT 24
Peak memory 200312 kb
Host smart-a17e9fe3-6f36-4d32-9e0e-b02b16f400ff
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562039008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.1562039008
Directory /workspace/8.uart_intr/latest

Test location /workspace/coverage/default/8.uart_long_xfer_wo_dly.2603379264
Short name T925
Test name
Test status
Simulation time 153574984461 ps
CPU time 432.53 seconds
Started Jun 05 04:15:03 PM PDT 24
Finished Jun 05 04:22:16 PM PDT 24
Peak memory 200436 kb
Host smart-cd407fb7-9c1d-4b78-8ef6-acab8f2bba87
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2603379264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.2603379264
Directory /workspace/8.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/8.uart_loopback.3949838809
Short name T447
Test name
Test status
Simulation time 3589564934 ps
CPU time 5.07 seconds
Started Jun 05 04:15:12 PM PDT 24
Finished Jun 05 04:15:18 PM PDT 24
Peak memory 199420 kb
Host smart-43fb772f-1cea-42a9-9791-66da46d23a3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949838809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_loopback.3949838809
Directory /workspace/8.uart_loopback/latest

Test location /workspace/coverage/default/8.uart_noise_filter.3107259775
Short name T672
Test name
Test status
Simulation time 26390866281 ps
CPU time 46.38 seconds
Started Jun 05 04:15:06 PM PDT 24
Finished Jun 05 04:15:53 PM PDT 24
Peak memory 200560 kb
Host smart-17d3d491-b678-4805-95c4-1f87fdb45d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107259775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_noise_filter.3107259775
Directory /workspace/8.uart_noise_filter/latest

Test location /workspace/coverage/default/8.uart_perf.3260895453
Short name T541
Test name
Test status
Simulation time 19339254078 ps
CPU time 534.26 seconds
Started Jun 05 04:14:56 PM PDT 24
Finished Jun 05 04:23:51 PM PDT 24
Peak memory 200264 kb
Host smart-c9bfde7a-35c7-4fd7-b98d-dfce81e9ed05
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3260895453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.3260895453
Directory /workspace/8.uart_perf/latest

Test location /workspace/coverage/default/8.uart_rx_oversample.1292612242
Short name T868
Test name
Test status
Simulation time 3685635270 ps
CPU time 3.66 seconds
Started Jun 05 04:15:12 PM PDT 24
Finished Jun 05 04:15:17 PM PDT 24
Peak memory 199756 kb
Host smart-d2c081f9-deb1-4e63-ad9a-a6617f29f27d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1292612242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.1292612242
Directory /workspace/8.uart_rx_oversample/latest

Test location /workspace/coverage/default/8.uart_rx_parity_err.2742036350
Short name T272
Test name
Test status
Simulation time 108711280038 ps
CPU time 32.11 seconds
Started Jun 05 04:14:55 PM PDT 24
Finished Jun 05 04:15:28 PM PDT 24
Peak memory 200256 kb
Host smart-87ecd267-728a-4270-9fe3-fad744f5faf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742036350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.2742036350
Directory /workspace/8.uart_rx_parity_err/latest

Test location /workspace/coverage/default/8.uart_rx_start_bit_filter.70781551
Short name T583
Test name
Test status
Simulation time 2678306921 ps
CPU time 4.71 seconds
Started Jun 05 04:14:56 PM PDT 24
Finished Jun 05 04:15:01 PM PDT 24
Peak memory 196156 kb
Host smart-616dfa84-e0ab-484f-b9bf-32d095342f5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70781551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.70781551
Directory /workspace/8.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/8.uart_smoke.871880366
Short name T784
Test name
Test status
Simulation time 306390614 ps
CPU time 1.65 seconds
Started Jun 05 04:15:09 PM PDT 24
Finished Jun 05 04:15:12 PM PDT 24
Peak memory 199148 kb
Host smart-9dd1e61e-d0ba-4078-acaf-8ddcfc865af5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871880366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_smoke.871880366
Directory /workspace/8.uart_smoke/latest

Test location /workspace/coverage/default/8.uart_stress_all.3851640224
Short name T335
Test name
Test status
Simulation time 123761515691 ps
CPU time 274.56 seconds
Started Jun 05 04:15:13 PM PDT 24
Finished Jun 05 04:19:48 PM PDT 24
Peak memory 200460 kb
Host smart-38ff1705-ecde-4025-9f94-f9c54ff730cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851640224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.3851640224
Directory /workspace/8.uart_stress_all/latest

Test location /workspace/coverage/default/8.uart_stress_all_with_rand_reset.494153695
Short name T768
Test name
Test status
Simulation time 14614925649 ps
CPU time 309.05 seconds
Started Jun 05 04:15:07 PM PDT 24
Finished Jun 05 04:20:17 PM PDT 24
Peak memory 216884 kb
Host smart-2624ccf5-4adb-40d3-9468-1ccea6b854f7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494153695 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 8.uart_stress_all_with_rand_reset.494153695
Directory /workspace/8.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_tx_ovrd.3473899634
Short name T284
Test name
Test status
Simulation time 1062394771 ps
CPU time 1.39 seconds
Started Jun 05 04:15:08 PM PDT 24
Finished Jun 05 04:15:10 PM PDT 24
Peak memory 199312 kb
Host smart-61b90a38-eebd-40f3-a467-c8af2baa6fc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473899634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.3473899634
Directory /workspace/8.uart_tx_ovrd/latest

Test location /workspace/coverage/default/8.uart_tx_rx.3040609470
Short name T1044
Test name
Test status
Simulation time 26083615175 ps
CPU time 65.53 seconds
Started Jun 05 04:15:09 PM PDT 24
Finished Jun 05 04:16:16 PM PDT 24
Peak memory 200408 kb
Host smart-5354d536-8e12-4c88-8e0a-d1d762e91502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040609470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.3040609470
Directory /workspace/8.uart_tx_rx/latest

Test location /workspace/coverage/default/80.uart_fifo_reset.3790461494
Short name T582
Test name
Test status
Simulation time 41673398653 ps
CPU time 17.95 seconds
Started Jun 05 04:17:52 PM PDT 24
Finished Jun 05 04:18:10 PM PDT 24
Peak memory 200444 kb
Host smart-6f6163a9-52c1-4b33-abec-d9eb925789c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790461494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.3790461494
Directory /workspace/80.uart_fifo_reset/latest

Test location /workspace/coverage/default/80.uart_stress_all_with_rand_reset.2062468211
Short name T63
Test name
Test status
Simulation time 226075539064 ps
CPU time 790.45 seconds
Started Jun 05 04:17:54 PM PDT 24
Finished Jun 05 04:31:05 PM PDT 24
Peak memory 217120 kb
Host smart-eb7014bd-9ce7-43a5-bbaa-242c0111fcc7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062468211 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 80.uart_stress_all_with_rand_reset.2062468211
Directory /workspace/80.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/81.uart_fifo_reset.4141847936
Short name T337
Test name
Test status
Simulation time 17915738201 ps
CPU time 16.06 seconds
Started Jun 05 04:17:51 PM PDT 24
Finished Jun 05 04:18:08 PM PDT 24
Peak memory 200080 kb
Host smart-e99fa4fb-ce42-4c5b-82bb-fb2cfae6c385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141847936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.4141847936
Directory /workspace/81.uart_fifo_reset/latest

Test location /workspace/coverage/default/81.uart_stress_all_with_rand_reset.309000729
Short name T171
Test name
Test status
Simulation time 36567215889 ps
CPU time 269.72 seconds
Started Jun 05 04:17:55 PM PDT 24
Finished Jun 05 04:22:25 PM PDT 24
Peak memory 216832 kb
Host smart-988adc25-046d-4b25-b819-4809f44053ad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309000729 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 81.uart_stress_all_with_rand_reset.309000729
Directory /workspace/81.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.uart_fifo_reset.2554619659
Short name T1031
Test name
Test status
Simulation time 115256902560 ps
CPU time 92.47 seconds
Started Jun 05 04:17:53 PM PDT 24
Finished Jun 05 04:19:26 PM PDT 24
Peak memory 200488 kb
Host smart-c86e9c42-5a4f-444f-8c9a-22c267f78153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554619659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.2554619659
Directory /workspace/82.uart_fifo_reset/latest

Test location /workspace/coverage/default/82.uart_stress_all_with_rand_reset.1382597941
Short name T1009
Test name
Test status
Simulation time 87745637352 ps
CPU time 408.98 seconds
Started Jun 05 04:17:50 PM PDT 24
Finished Jun 05 04:24:40 PM PDT 24
Peak memory 217128 kb
Host smart-42568825-df78-4397-aee2-16fb40c8f787
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382597941 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 82.uart_stress_all_with_rand_reset.1382597941
Directory /workspace/82.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/83.uart_fifo_reset.191847499
Short name T800
Test name
Test status
Simulation time 69764744389 ps
CPU time 38.02 seconds
Started Jun 05 04:17:54 PM PDT 24
Finished Jun 05 04:18:33 PM PDT 24
Peak memory 200464 kb
Host smart-6dc6f037-3a14-4d6b-a4a4-254aa4da0d50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191847499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.191847499
Directory /workspace/83.uart_fifo_reset/latest

Test location /workspace/coverage/default/83.uart_stress_all_with_rand_reset.1142377993
Short name T62
Test name
Test status
Simulation time 128396464616 ps
CPU time 611.09 seconds
Started Jun 05 04:17:50 PM PDT 24
Finished Jun 05 04:28:01 PM PDT 24
Peak memory 226016 kb
Host smart-031a944f-191f-47e6-a469-14cb4885ba11
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142377993 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 83.uart_stress_all_with_rand_reset.1142377993
Directory /workspace/83.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/84.uart_fifo_reset.1704502849
Short name T422
Test name
Test status
Simulation time 60816062088 ps
CPU time 103.58 seconds
Started Jun 05 04:17:50 PM PDT 24
Finished Jun 05 04:19:34 PM PDT 24
Peak memory 200372 kb
Host smart-4a8ce324-f98f-4c40-87c9-4170693a49e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704502849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.1704502849
Directory /workspace/84.uart_fifo_reset/latest

Test location /workspace/coverage/default/84.uart_stress_all_with_rand_reset.2672417844
Short name T898
Test name
Test status
Simulation time 122005385941 ps
CPU time 544.91 seconds
Started Jun 05 04:17:50 PM PDT 24
Finished Jun 05 04:26:56 PM PDT 24
Peak memory 225068 kb
Host smart-f9d2e1da-1a1d-4793-b6f7-965904080011
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672417844 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 84.uart_stress_all_with_rand_reset.2672417844
Directory /workspace/84.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.uart_fifo_reset.746576145
Short name T227
Test name
Test status
Simulation time 135401650128 ps
CPU time 64.98 seconds
Started Jun 05 04:17:53 PM PDT 24
Finished Jun 05 04:18:58 PM PDT 24
Peak memory 200476 kb
Host smart-070e2b73-d639-4fa6-885a-f84e222e554e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746576145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.746576145
Directory /workspace/85.uart_fifo_reset/latest

Test location /workspace/coverage/default/85.uart_stress_all_with_rand_reset.2821682396
Short name T1074
Test name
Test status
Simulation time 54206604931 ps
CPU time 485.49 seconds
Started Jun 05 04:17:50 PM PDT 24
Finished Jun 05 04:25:56 PM PDT 24
Peak memory 217044 kb
Host smart-81f5e965-fa2d-4d1b-986b-7b917be6f1a7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821682396 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 85.uart_stress_all_with_rand_reset.2821682396
Directory /workspace/85.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.uart_fifo_reset.1841262372
Short name T911
Test name
Test status
Simulation time 15063735129 ps
CPU time 12.32 seconds
Started Jun 05 04:17:50 PM PDT 24
Finished Jun 05 04:18:03 PM PDT 24
Peak memory 200444 kb
Host smart-9ad99838-1da3-4952-96be-72f4a0293783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841262372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.1841262372
Directory /workspace/86.uart_fifo_reset/latest

Test location /workspace/coverage/default/86.uart_stress_all_with_rand_reset.4236670358
Short name T779
Test name
Test status
Simulation time 47756414731 ps
CPU time 332.22 seconds
Started Jun 05 04:17:51 PM PDT 24
Finished Jun 05 04:23:24 PM PDT 24
Peak memory 217128 kb
Host smart-41ba4a8e-45f3-4924-a909-da34b29cd973
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236670358 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 86.uart_stress_all_with_rand_reset.4236670358
Directory /workspace/86.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/87.uart_fifo_reset.197032460
Short name T43
Test name
Test status
Simulation time 15264892571 ps
CPU time 30.97 seconds
Started Jun 05 04:17:56 PM PDT 24
Finished Jun 05 04:18:28 PM PDT 24
Peak memory 200372 kb
Host smart-59123c5c-fba8-479d-8deb-29ea9ef4198c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197032460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.197032460
Directory /workspace/87.uart_fifo_reset/latest

Test location /workspace/coverage/default/88.uart_fifo_reset.1801300938
Short name T432
Test name
Test status
Simulation time 25729201184 ps
CPU time 22.26 seconds
Started Jun 05 04:17:56 PM PDT 24
Finished Jun 05 04:18:19 PM PDT 24
Peak memory 200376 kb
Host smart-54da24de-2010-4eaa-b3f3-5150e1c18373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801300938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.1801300938
Directory /workspace/88.uart_fifo_reset/latest

Test location /workspace/coverage/default/88.uart_stress_all_with_rand_reset.117484882
Short name T112
Test name
Test status
Simulation time 71381230758 ps
CPU time 314.36 seconds
Started Jun 05 04:17:53 PM PDT 24
Finished Jun 05 04:23:08 PM PDT 24
Peak memory 216940 kb
Host smart-060e8b84-060c-4705-9c99-34332e2fbe36
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117484882 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 88.uart_stress_all_with_rand_reset.117484882
Directory /workspace/88.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.uart_fifo_reset.986348774
Short name T825
Test name
Test status
Simulation time 16206012765 ps
CPU time 29.03 seconds
Started Jun 05 04:17:52 PM PDT 24
Finished Jun 05 04:18:22 PM PDT 24
Peak memory 200464 kb
Host smart-315f7ccc-354f-48fd-9479-5f72d90e9f9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986348774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.986348774
Directory /workspace/89.uart_fifo_reset/latest

Test location /workspace/coverage/default/89.uart_stress_all_with_rand_reset.2813328254
Short name T1092
Test name
Test status
Simulation time 187652990961 ps
CPU time 603.58 seconds
Started Jun 05 04:17:52 PM PDT 24
Finished Jun 05 04:27:56 PM PDT 24
Peak memory 225320 kb
Host smart-bc56e6f9-64e9-4c22-9324-3774df3f583a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813328254 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 89.uart_stress_all_with_rand_reset.2813328254
Directory /workspace/89.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_alert_test.587298104
Short name T417
Test name
Test status
Simulation time 49045027 ps
CPU time 0.55 seconds
Started Jun 05 04:15:08 PM PDT 24
Finished Jun 05 04:15:10 PM PDT 24
Peak memory 195780 kb
Host smart-5d744c73-554f-45b5-aaa0-7d0b1c59b64c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587298104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.587298104
Directory /workspace/9.uart_alert_test/latest

Test location /workspace/coverage/default/9.uart_fifo_full.2716218052
Short name T295
Test name
Test status
Simulation time 161009035140 ps
CPU time 269.33 seconds
Started Jun 05 04:15:08 PM PDT 24
Finished Jun 05 04:19:39 PM PDT 24
Peak memory 200404 kb
Host smart-123aeacc-af94-4f65-a05e-409b34dce8e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716218052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.2716218052
Directory /workspace/9.uart_fifo_full/latest

Test location /workspace/coverage/default/9.uart_fifo_overflow.1717738089
Short name T896
Test name
Test status
Simulation time 11506461089 ps
CPU time 9.85 seconds
Started Jun 05 04:15:09 PM PDT 24
Finished Jun 05 04:15:20 PM PDT 24
Peak memory 199888 kb
Host smart-beb5ba50-ecda-427f-b44a-6a85a98a4fe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717738089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.1717738089
Directory /workspace/9.uart_fifo_overflow/latest

Test location /workspace/coverage/default/9.uart_fifo_reset.132306561
Short name T196
Test name
Test status
Simulation time 20603799386 ps
CPU time 37.18 seconds
Started Jun 05 04:14:57 PM PDT 24
Finished Jun 05 04:15:35 PM PDT 24
Peak memory 200444 kb
Host smart-e987b3db-a2a6-4c23-90c6-6d6832b2cd64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132306561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.132306561
Directory /workspace/9.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_intr.2730969567
Short name T592
Test name
Test status
Simulation time 370849685090 ps
CPU time 669.75 seconds
Started Jun 05 04:15:00 PM PDT 24
Finished Jun 05 04:26:11 PM PDT 24
Peak memory 200356 kb
Host smart-a9a814cd-f5df-494f-bb9b-3b88f10f94bd
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730969567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.2730969567
Directory /workspace/9.uart_intr/latest

Test location /workspace/coverage/default/9.uart_long_xfer_wo_dly.4274139192
Short name T984
Test name
Test status
Simulation time 116768216759 ps
CPU time 230.41 seconds
Started Jun 05 04:15:14 PM PDT 24
Finished Jun 05 04:19:05 PM PDT 24
Peak memory 200440 kb
Host smart-b18d1406-0f12-4ed9-8033-7d6dee9d7a76
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4274139192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.4274139192
Directory /workspace/9.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/9.uart_loopback.3119858529
Short name T492
Test name
Test status
Simulation time 5479910627 ps
CPU time 9.88 seconds
Started Jun 05 04:15:13 PM PDT 24
Finished Jun 05 04:15:24 PM PDT 24
Peak memory 199068 kb
Host smart-fdea17ec-c513-4348-ac8b-43f3722dd29c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119858529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_loopback.3119858529
Directory /workspace/9.uart_loopback/latest

Test location /workspace/coverage/default/9.uart_noise_filter.2496226923
Short name T954
Test name
Test status
Simulation time 153118876879 ps
CPU time 143.06 seconds
Started Jun 05 04:15:06 PM PDT 24
Finished Jun 05 04:17:29 PM PDT 24
Peak memory 200852 kb
Host smart-25a422d6-6474-440f-9d9f-04c4e8581f7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496226923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.2496226923
Directory /workspace/9.uart_noise_filter/latest

Test location /workspace/coverage/default/9.uart_perf.1272303055
Short name T254
Test name
Test status
Simulation time 24829240592 ps
CPU time 1172.22 seconds
Started Jun 05 04:15:00 PM PDT 24
Finished Jun 05 04:34:33 PM PDT 24
Peak memory 200360 kb
Host smart-74d85895-a133-46fe-a3db-13a9f6f99742
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1272303055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.1272303055
Directory /workspace/9.uart_perf/latest

Test location /workspace/coverage/default/9.uart_rx_oversample.2226702752
Short name T1176
Test name
Test status
Simulation time 2562989873 ps
CPU time 6.09 seconds
Started Jun 05 04:15:10 PM PDT 24
Finished Jun 05 04:15:18 PM PDT 24
Peak memory 198576 kb
Host smart-04ed091b-51bf-4cde-8f00-ee2ede07cdff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2226702752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.2226702752
Directory /workspace/9.uart_rx_oversample/latest

Test location /workspace/coverage/default/9.uart_rx_parity_err.3906482746
Short name T181
Test name
Test status
Simulation time 39650327356 ps
CPU time 11.57 seconds
Started Jun 05 04:15:04 PM PDT 24
Finished Jun 05 04:15:16 PM PDT 24
Peak memory 199708 kb
Host smart-ef4cb22c-86ed-4fe7-8aaf-57eec0876baa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906482746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.3906482746
Directory /workspace/9.uart_rx_parity_err/latest

Test location /workspace/coverage/default/9.uart_rx_start_bit_filter.2200630685
Short name T486
Test name
Test status
Simulation time 5203550862 ps
CPU time 3.11 seconds
Started Jun 05 04:14:59 PM PDT 24
Finished Jun 05 04:15:02 PM PDT 24
Peak memory 196412 kb
Host smart-3198a64b-1e64-4336-898f-b25a82d695f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200630685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.2200630685
Directory /workspace/9.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/9.uart_smoke.1301614036
Short name T867
Test name
Test status
Simulation time 690370606 ps
CPU time 1.59 seconds
Started Jun 05 04:15:05 PM PDT 24
Finished Jun 05 04:15:07 PM PDT 24
Peak memory 199024 kb
Host smart-6dc71c54-a92f-41d8-a3f9-3f05a805e1dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301614036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_smoke.1301614036
Directory /workspace/9.uart_smoke/latest

Test location /workspace/coverage/default/9.uart_stress_all.1108796009
Short name T849
Test name
Test status
Simulation time 84346614925 ps
CPU time 174.49 seconds
Started Jun 05 04:15:04 PM PDT 24
Finished Jun 05 04:17:59 PM PDT 24
Peak memory 200376 kb
Host smart-b4bb9829-cfc0-4020-b8c1-e776c883b6d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108796009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.1108796009
Directory /workspace/9.uart_stress_all/latest

Test location /workspace/coverage/default/9.uart_stress_all_with_rand_reset.1064982930
Short name T882
Test name
Test status
Simulation time 60450877503 ps
CPU time 1854.99 seconds
Started Jun 05 04:14:56 PM PDT 24
Finished Jun 05 04:45:52 PM PDT 24
Peak memory 225192 kb
Host smart-afcb873f-1ebd-463e-acd4-4f48ab17a770
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064982930 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 9.uart_stress_all_with_rand_reset.1064982930
Directory /workspace/9.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_tx_ovrd.1869602324
Short name T348
Test name
Test status
Simulation time 754913925 ps
CPU time 1.7 seconds
Started Jun 05 04:14:56 PM PDT 24
Finished Jun 05 04:14:58 PM PDT 24
Peak memory 199160 kb
Host smart-48e0723c-8e3f-4e47-921e-2d497ce92525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869602324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.1869602324
Directory /workspace/9.uart_tx_ovrd/latest

Test location /workspace/coverage/default/9.uart_tx_rx.796379229
Short name T285
Test name
Test status
Simulation time 39392407599 ps
CPU time 89.02 seconds
Started Jun 05 04:15:10 PM PDT 24
Finished Jun 05 04:16:40 PM PDT 24
Peak memory 200444 kb
Host smart-b6528fef-3568-4660-bfde-1ce7b8e6c52e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796379229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.796379229
Directory /workspace/9.uart_tx_rx/latest

Test location /workspace/coverage/default/90.uart_stress_all_with_rand_reset.94590704
Short name T217
Test name
Test status
Simulation time 43753076299 ps
CPU time 445.14 seconds
Started Jun 05 04:17:52 PM PDT 24
Finished Jun 05 04:25:18 PM PDT 24
Peak memory 216796 kb
Host smart-144d9675-9e8d-44c8-804e-52ae9074f551
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94590704 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 90.uart_stress_all_with_rand_reset.94590704
Directory /workspace/90.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.uart_fifo_reset.113519347
Short name T959
Test name
Test status
Simulation time 42001494054 ps
CPU time 18.03 seconds
Started Jun 05 04:17:56 PM PDT 24
Finished Jun 05 04:18:15 PM PDT 24
Peak memory 200484 kb
Host smart-2a78ed8e-964c-4839-849a-cbb28410eba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113519347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.113519347
Directory /workspace/91.uart_fifo_reset/latest

Test location /workspace/coverage/default/91.uart_stress_all_with_rand_reset.3237890280
Short name T880
Test name
Test status
Simulation time 156832074016 ps
CPU time 531.51 seconds
Started Jun 05 04:17:53 PM PDT 24
Finished Jun 05 04:26:45 PM PDT 24
Peak memory 212232 kb
Host smart-a241be4e-3c8b-4246-8a00-b89d21fba83d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237890280 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 91.uart_stress_all_with_rand_reset.3237890280
Directory /workspace/91.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.uart_fifo_reset.380005814
Short name T951
Test name
Test status
Simulation time 100534978123 ps
CPU time 73.51 seconds
Started Jun 05 04:17:54 PM PDT 24
Finished Jun 05 04:19:08 PM PDT 24
Peak memory 200400 kb
Host smart-be863757-7ced-4494-8297-23adc931b8ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380005814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.380005814
Directory /workspace/92.uart_fifo_reset/latest

Test location /workspace/coverage/default/92.uart_stress_all_with_rand_reset.453216858
Short name T1123
Test name
Test status
Simulation time 132563923954 ps
CPU time 443.62 seconds
Started Jun 05 04:17:53 PM PDT 24
Finished Jun 05 04:25:17 PM PDT 24
Peak memory 208928 kb
Host smart-d80bb816-409f-46a4-89f6-f86fc743d25f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453216858 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 92.uart_stress_all_with_rand_reset.453216858
Directory /workspace/92.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/93.uart_fifo_reset.3502996381
Short name T590
Test name
Test status
Simulation time 75460373737 ps
CPU time 87.57 seconds
Started Jun 05 04:17:54 PM PDT 24
Finished Jun 05 04:19:22 PM PDT 24
Peak memory 200380 kb
Host smart-9decc210-27c1-4b4d-af9c-4d75c64c01bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502996381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.3502996381
Directory /workspace/93.uart_fifo_reset/latest

Test location /workspace/coverage/default/93.uart_stress_all_with_rand_reset.2829861851
Short name T1050
Test name
Test status
Simulation time 103114059447 ps
CPU time 594.11 seconds
Started Jun 05 04:17:53 PM PDT 24
Finished Jun 05 04:27:47 PM PDT 24
Peak memory 212684 kb
Host smart-7eb907e5-052a-47af-869b-ab0759ea47e8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829861851 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 93.uart_stress_all_with_rand_reset.2829861851
Directory /workspace/93.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/94.uart_fifo_reset.765982316
Short name T892
Test name
Test status
Simulation time 73373667007 ps
CPU time 119.81 seconds
Started Jun 05 04:17:50 PM PDT 24
Finished Jun 05 04:19:50 PM PDT 24
Peak memory 200460 kb
Host smart-8f10a07a-d6d1-4f9c-9151-2d4325a28ae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765982316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.765982316
Directory /workspace/94.uart_fifo_reset/latest

Test location /workspace/coverage/default/94.uart_stress_all_with_rand_reset.170026063
Short name T1165
Test name
Test status
Simulation time 38229544999 ps
CPU time 434.36 seconds
Started Jun 05 04:18:01 PM PDT 24
Finished Jun 05 04:25:16 PM PDT 24
Peak memory 226620 kb
Host smart-145e9301-7495-460d-a0ce-e9c1535184ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170026063 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 94.uart_stress_all_with_rand_reset.170026063
Directory /workspace/94.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/95.uart_fifo_reset.597649855
Short name T974
Test name
Test status
Simulation time 290568738230 ps
CPU time 22.86 seconds
Started Jun 05 04:18:01 PM PDT 24
Finished Jun 05 04:18:25 PM PDT 24
Peak memory 200460 kb
Host smart-23ec4f8c-2f93-47ab-b68e-c7e84416f919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597649855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.597649855
Directory /workspace/95.uart_fifo_reset/latest

Test location /workspace/coverage/default/95.uart_stress_all_with_rand_reset.3502326078
Short name T736
Test name
Test status
Simulation time 94767111134 ps
CPU time 407.25 seconds
Started Jun 05 04:18:02 PM PDT 24
Finished Jun 05 04:24:50 PM PDT 24
Peak memory 217040 kb
Host smart-3cb1bab1-2776-4e64-b7da-9f3afc82dacf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502326078 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 95.uart_stress_all_with_rand_reset.3502326078
Directory /workspace/95.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/96.uart_fifo_reset.2049136929
Short name T919
Test name
Test status
Simulation time 22225375439 ps
CPU time 37.55 seconds
Started Jun 05 04:18:01 PM PDT 24
Finished Jun 05 04:18:40 PM PDT 24
Peak memory 200376 kb
Host smart-0dd177f7-12af-46be-a173-b222cff308f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049136929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.2049136929
Directory /workspace/96.uart_fifo_reset/latest

Test location /workspace/coverage/default/96.uart_stress_all_with_rand_reset.2114074448
Short name T656
Test name
Test status
Simulation time 54323160062 ps
CPU time 360.64 seconds
Started Jun 05 04:18:02 PM PDT 24
Finished Jun 05 04:24:03 PM PDT 24
Peak memory 217112 kb
Host smart-c5057e3a-c079-411b-bf41-3b28901f9f93
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114074448 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 96.uart_stress_all_with_rand_reset.2114074448
Directory /workspace/96.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.uart_fifo_reset.1699205753
Short name T121
Test name
Test status
Simulation time 29532124981 ps
CPU time 32.37 seconds
Started Jun 05 04:18:03 PM PDT 24
Finished Jun 05 04:18:36 PM PDT 24
Peak memory 200420 kb
Host smart-dbb5092c-9fa7-4137-a13e-ff18c7daf080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699205753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.1699205753
Directory /workspace/97.uart_fifo_reset/latest

Test location /workspace/coverage/default/97.uart_stress_all_with_rand_reset.205780342
Short name T955
Test name
Test status
Simulation time 244806663329 ps
CPU time 602.2 seconds
Started Jun 05 04:18:01 PM PDT 24
Finished Jun 05 04:28:04 PM PDT 24
Peak memory 216884 kb
Host smart-63c12e57-7957-48bc-934d-c1904b63969b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205780342 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 97.uart_stress_all_with_rand_reset.205780342
Directory /workspace/97.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/98.uart_fifo_reset.2804410819
Short name T906
Test name
Test status
Simulation time 144480470442 ps
CPU time 39.5 seconds
Started Jun 05 04:18:02 PM PDT 24
Finished Jun 05 04:18:43 PM PDT 24
Peak memory 200340 kb
Host smart-8e7dfd45-fe9e-4148-b9d5-6a8aaf33e726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804410819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.2804410819
Directory /workspace/98.uart_fifo_reset/latest

Test location /workspace/coverage/default/98.uart_stress_all_with_rand_reset.1931938082
Short name T679
Test name
Test status
Simulation time 155029035936 ps
CPU time 582.52 seconds
Started Jun 05 04:18:02 PM PDT 24
Finished Jun 05 04:27:45 PM PDT 24
Peak memory 220084 kb
Host smart-08a62e07-cbc9-4643-b566-137a0659b3f6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931938082 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 98.uart_stress_all_with_rand_reset.1931938082
Directory /workspace/98.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/99.uart_fifo_reset.3445844812
Short name T1083
Test name
Test status
Simulation time 12382318699 ps
CPU time 25.76 seconds
Started Jun 05 04:18:01 PM PDT 24
Finished Jun 05 04:18:27 PM PDT 24
Peak memory 200408 kb
Host smart-3ce41f97-4cfa-433a-90bb-a8db77555437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445844812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.3445844812
Directory /workspace/99.uart_fifo_reset/latest

Test location /workspace/coverage/default/99.uart_stress_all_with_rand_reset.192953474
Short name T715
Test name
Test status
Simulation time 35384238482 ps
CPU time 374.09 seconds
Started Jun 05 04:18:02 PM PDT 24
Finished Jun 05 04:24:17 PM PDT 24
Peak memory 209544 kb
Host smart-ae3907d3-51a2-4aa0-a04e-4257c2cd20d3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192953474 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 99.uart_stress_all_with_rand_reset.192953474
Directory /workspace/99.uart_stress_all_with_rand_reset/latest
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