Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	125866	1			T1	15		T2	31		T3	421
all_values[1]	125866	1			T1	15		T2	31		T3	421
all_values[2]	125866	1			T1	15		T2	31		T3	421
all_values[3]	125866	1			T1	15		T2	31		T3	421
all_values[4]	125866	1			T1	15		T2	31		T3	421
all_values[5]	125866	1			T1	15		T2	31		T3	421
all_values[6]	125866	1			T1	15		T2	31		T3	421
all_values[7]	125866	1			T1	15		T2	31		T3	421
all_values[8]	125866	1			T1	15		T2	31		T3	421

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

569717

1

T1

78

T2

166

T3

1398

auto[1]

563077

1

T1

57

T2

113

T3

2391

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1031262

1

T1

105

T2

243

T3

3407

auto[1]

101532

1

T1

30

T2

36

T3

382

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	36475	1			T2	2		T3	48		T7	1
all_values[0]	auto[0]	auto[1]	25102	1			T1	5		T2	3		T3	24
all_values[0]	auto[1]	auto[0]	38954	1			T2	11		T3	165		T11	37
all_values[0]	auto[1]	auto[1]	25335	1			T1	10		T2	15		T3	184
all_values[1]	auto[0]	auto[0]	63727	1			T1	10		T2	28		T3	130
all_values[1]	auto[0]	auto[1]	1726	1			T7	1		T11	24		T17	12
all_values[1]	auto[1]	auto[0]	58565	1			T1	5		T2	3		T3	291
all_values[1]	auto[1]	auto[1]	1848	1			T11	5		T13	1		T15	6
all_values[2]	auto[0]	auto[0]	62030	1			T1	11		T2	11		T3	174
all_values[2]	auto[0]	auto[1]	2893	1			T1	1		T2	1		T3	2
all_values[2]	auto[1]	auto[0]	58401	1			T1	2		T2	16		T3	240
all_values[2]	auto[1]	auto[1]	2542	1			T1	1		T2	3		T3	5
all_values[3]	auto[0]	auto[0]	64425	1			T1	10		T2	5		T3	59
all_values[3]	auto[0]	auto[1]	324	1			T11	2		T16	2		T17	4
all_values[3]	auto[1]	auto[0]	60809	1			T1	5		T2	26		T3	362
all_values[3]	auto[1]	auto[1]	308	1			T11	3		T15	1		T17	3
all_values[4]	auto[0]	auto[0]	56816	1			T1	3		T2	17		T3	175
all_values[4]	auto[0]	auto[1]	516	1			T17	1		T20	4		T24	2
all_values[4]	auto[1]	auto[0]	68075	1			T1	12		T2	14		T3	246
all_values[4]	auto[1]	auto[1]	459	1			T11	6		T15	6		T17	5
all_values[5]	auto[0]	auto[0]	66299	1			T1	13		T2	16		T3	118
all_values[5]	auto[0]	auto[1]	170	1			T17	4		T24	1		T33	4
all_values[5]	auto[1]	auto[0]	59180	1			T1	2		T2	15		T3	303
all_values[5]	auto[1]	auto[1]	217	1			T17	1		T24	1		T25	1
all_values[6]	auto[0]	auto[0]	60698	1			T1	2		T2	21		T3	118
all_values[6]	auto[0]	auto[1]	173	1			T17	2		T24	2		T33	5
all_values[6]	auto[1]	auto[0]	64818	1			T1	13		T2	10		T3	303
all_values[6]	auto[1]	auto[1]	177	1			T17	4		T24	2		T25	1
all_values[7]	auto[0]	auto[0]	61189	1			T1	10		T2	31		T3	304
all_values[7]	auto[0]	auto[1]	383	1			T15	6		T17	2		T20	2
all_values[7]	auto[1]	auto[0]	63883	1			T1	5		T3	117		T5	14
all_values[7]	auto[1]	auto[1]	411	1			T17	3		T20	5		T28	3
all_values[8]	auto[0]	auto[0]	46637	1			T2	17		T3	79		T7	5
all_values[8]	auto[0]	auto[1]	20134	1			T1	13		T2	14		T3	167
all_values[8]	auto[1]	auto[0]	40281	1			T1	2		T3	175		T11	39
all_values[8]	auto[1]	auto[1]	18814	1			T4	1		T5	14		T7	3