Summary for Variable cp_dir
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_dir
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[UartTx] |
2572 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
auto[UartRx] |
2572 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_rst_pos
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
11 |
0 |
11 |
100.00 |
User Defined Bins for cp_rst_pos
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0] |
4523 |
1 |
|
|
T1 |
2 |
|
T2 |
2 |
|
T3 |
2 |
values[1] |
43 |
1 |
|
|
T132 |
1 |
|
T130 |
1 |
|
T118 |
2 |
values[2] |
62 |
1 |
|
|
T17 |
2 |
|
T23 |
2 |
|
T33 |
1 |
values[3] |
54 |
1 |
|
|
T17 |
1 |
|
T23 |
3 |
|
T33 |
1 |
values[4] |
73 |
1 |
|
|
T23 |
4 |
|
T35 |
1 |
|
T36 |
1 |
values[5] |
62 |
1 |
|
|
T25 |
1 |
|
T33 |
1 |
|
T36 |
2 |
values[6] |
65 |
1 |
|
|
T17 |
1 |
|
T23 |
1 |
|
T34 |
2 |
values[7] |
61 |
1 |
|
|
T17 |
1 |
|
T25 |
2 |
|
T33 |
2 |
values[8] |
66 |
1 |
|
|
T34 |
1 |
|
T37 |
1 |
|
T58 |
1 |
values[9] |
54 |
1 |
|
|
T17 |
2 |
|
T23 |
1 |
|
T33 |
1 |
values[10] |
57 |
1 |
|
|
T23 |
1 |
|
T33 |
1 |
|
T34 |
2 |
Summary for Cross uart_reset_cg_cc
Samples crossed: cp_dir cp_rst_pos
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
22 |
0 |
22 |
100.00 |
|
Automatically Generated Cross Bins for uart_reset_cg_cc
Bins
cp_dir | cp_rst_pos | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[UartTx] |
values[0] |
2355 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
auto[UartTx] |
values[1] |
10 |
1 |
|
|
T130 |
1 |
|
T118 |
1 |
|
T319 |
1 |
auto[UartTx] |
values[2] |
24 |
1 |
|
|
T35 |
1 |
|
T38 |
1 |
|
T39 |
1 |
auto[UartTx] |
values[3] |
15 |
1 |
|
|
T17 |
1 |
|
T23 |
2 |
|
T33 |
1 |
auto[UartTx] |
values[4] |
26 |
1 |
|
|
T23 |
1 |
|
T36 |
1 |
|
T37 |
1 |
auto[UartTx] |
values[5] |
25 |
1 |
|
|
T25 |
1 |
|
T36 |
1 |
|
T38 |
1 |
auto[UartTx] |
values[6] |
25 |
1 |
|
|
T23 |
1 |
|
T34 |
1 |
|
T304 |
2 |
auto[UartTx] |
values[7] |
20 |
1 |
|
|
T25 |
1 |
|
T34 |
1 |
|
T39 |
1 |
auto[UartTx] |
values[8] |
21 |
1 |
|
|
T34 |
1 |
|
T117 |
1 |
|
T268 |
1 |
auto[UartTx] |
values[9] |
22 |
1 |
|
|
T34 |
1 |
|
T37 |
1 |
|
T133 |
1 |
auto[UartTx] |
values[10] |
21 |
1 |
|
|
T34 |
1 |
|
T38 |
2 |
|
T58 |
1 |
auto[UartRx] |
values[0] |
2168 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
auto[UartRx] |
values[1] |
33 |
1 |
|
|
T132 |
1 |
|
T118 |
1 |
|
T161 |
1 |
auto[UartRx] |
values[2] |
38 |
1 |
|
|
T17 |
2 |
|
T23 |
2 |
|
T33 |
1 |
auto[UartRx] |
values[3] |
39 |
1 |
|
|
T23 |
1 |
|
T38 |
1 |
|
T117 |
1 |
auto[UartRx] |
values[4] |
47 |
1 |
|
|
T23 |
3 |
|
T35 |
1 |
|
T38 |
2 |
auto[UartRx] |
values[5] |
37 |
1 |
|
|
T33 |
1 |
|
T36 |
1 |
|
T37 |
1 |
auto[UartRx] |
values[6] |
40 |
1 |
|
|
T17 |
1 |
|
T34 |
1 |
|
T36 |
1 |
auto[UartRx] |
values[7] |
41 |
1 |
|
|
T17 |
1 |
|
T25 |
1 |
|
T33 |
2 |
auto[UartRx] |
values[8] |
45 |
1 |
|
|
T37 |
1 |
|
T58 |
1 |
|
T117 |
1 |
auto[UartRx] |
values[9] |
32 |
1 |
|
|
T17 |
2 |
|
T23 |
1 |
|
T33 |
1 |
auto[UartRx] |
values[10] |
36 |
1 |
|
|
T23 |
1 |
|
T33 |
1 |
|
T34 |
1 |