Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	2478	1			T1	4		T2	2		T4	1
auto[BaudRate115200]	2032	1			T1	1		T2	3		T7	1
auto[BaudRate230400]	2072	1			T1	2		T5	1		T12	1
auto[BaudRate128Kbps]	2161	1			T1	1		T3	1		T10	1
auto[BaudRate256Kbps]	2281	1			T1	2		T2	1		T3	4
auto[BaudRate1Mbps]	1939	1			T2	1		T7	2		T11	6
auto[BaudRate1p5Mbps]	1319	1			T2	2		T14	2		T98	3

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Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	1512	1			T3	5		T45	9		T287	2
freqs[25]	1633	1			T14	9		T98	8		T125	8
freqs[48]	514	1			T8	1		T16	10		T257	8
freqs[50]	352	1			T4	1		T37	25		T315	9
freqs[100]	1417	1			T5	1		T10	2		T40	8

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Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	251	1			T45	1		T19	2		T20	3
auto[BaudRate9600]	freqs[25]	335	1			T125	1		T41	2		T122	1
auto[BaudRate9600]	freqs[48]	105	1			T16	3		T257	2		T300	1
auto[BaudRate9600]	freqs[50]	90	1			T4	1		T37	2		T315	2
auto[BaudRate9600]	freqs[100]	215	1			T10	1		T47	1		T253	1
auto[BaudRate115200]	freqs[24]	226	1			T45	2		T287	1		T20	3
auto[BaudRate115200]	freqs[25]	222	1			T14	1		T122	2		T153	3
auto[BaudRate115200]	freqs[48]	57	1			T257	2		T300	2		T155	15
auto[BaudRate115200]	freqs[50]	37	1			T37	3		T320	1		T191	1
auto[BaudRate115200]	freqs[100]	174	1			T40	1		T47	2		T54	1
auto[BaudRate230400]	freqs[24]	187	1			T20	2		T255	1		T55	1
auto[BaudRate230400]	freqs[25]	218	1			T14	2		T125	4		T41	1
auto[BaudRate230400]	freqs[48]	54	1			T16	1		T257	3		T300	1
auto[BaudRate230400]	freqs[50]	51	1			T37	4		T315	2		T191	1
auto[BaudRate230400]	freqs[100]	166	1			T5	1		T47	1		T262	1
auto[BaudRate128Kbps]	freqs[24]	235	1			T3	1		T45	1		T20	3
auto[BaudRate128Kbps]	freqs[25]	247	1			T14	2		T41	1		T184	1
auto[BaudRate128Kbps]	freqs[48]	82	1			T16	2		T300	1		T155	10
auto[BaudRate128Kbps]	freqs[50]	42	1			T37	5		T320	2		T191	1
auto[BaudRate128Kbps]	freqs[100]	185	1			T10	1		T47	2		T262	2
auto[BaudRate256Kbps]	freqs[24]	255	1			T3	4		T45	3		T287	1
auto[BaudRate256Kbps]	freqs[25]	251	1			T98	3		T122	1		T153	3
auto[BaudRate256Kbps]	freqs[48]	64	1			T8	1		T16	1		T300	1
auto[BaudRate256Kbps]	freqs[50]	40	1			T37	4		T315	1		T191	1
auto[BaudRate256Kbps]	freqs[100]	213	1			T40	4		T262	1		T258	4
auto[BaudRate1Mbps]	freqs[24]	243	1			T45	2		T20	2		T255	5
auto[BaudRate1Mbps]	freqs[25]	241	1			T14	2		T98	2		T125	2
auto[BaudRate1Mbps]	freqs[48]	89	1			T16	1		T300	1		T155	9
auto[BaudRate1Mbps]	freqs[50]	62	1			T37	6		T315	2		T320	2
auto[BaudRate1Mbps]	freqs[100]	243	1			T40	3		T47	2		T262	4
auto[BaudRate1p5Mbps]	freqs[25]	119	1			T14	2		T98	3		T125	1
auto[BaudRate1p5Mbps]	freqs[48]	63	1			T16	2		T257	1		T155	1
auto[BaudRate1p5Mbps]	freqs[50]	30	1			T37	1		T315	2		T320	3
auto[BaudRate1p5Mbps]	freqs[100]	221	1			T54	1		T57	3		T258	1

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded