Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::rx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::rx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.40	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	67	0	67	100.00
Crosses	130	13	117	90.00

Variables for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	65	0	65	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
rx_fifo_level_cg_cc	130	13	117	90.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	35379527	1			T1	23		T2	61		T3	116835
all_levels[1]	190054	1			T3	117		T7	43		T11	28
all_levels[2]	2560	1			T1	2		T7	16		T8	2
all_levels[3]	1160	1			T1	2		T7	14		T8	1
all_levels[4]	743	1			T7	3		T11	3		T45	3
all_levels[5]	546	1			T11	1		T13	7		T45	6
all_levels[6]	428	1			T1	2		T11	3		T14	1
all_levels[7]	332	1			T1	2		T11	3		T14	1
all_levels[8]	287	1			T8	1		T14	1		T139	1
all_levels[9]	256	1			T7	1		T11	2		T17	1
all_levels[10]	225	1			T1	1		T7	1		T11	1
all_levels[11]	203	1			T17	1		T28	1		T42	1
all_levels[12]	170	1			T11	3		T45	1		T40	1
all_levels[13]	148	1			T7	1		T11	1		T139	1
all_levels[14]	146	1			T42	1		T121	1		T47	2
all_levels[15]	117	1			T7	2		T11	1		T42	1
all_levels[16]	116	1			T17	1		T28	1		T122	3
all_levels[17]	95	1			T17	1		T40	1		T28	1
all_levels[18]	86	1			T40	1		T28	1		T42	2
all_levels[19]	87	1			T11	2		T40	1		T42	1
all_levels[20]	81	1			T40	1		T28	1		T47	1
all_levels[21]	67	1			T28	2		T140	1		T141	1
all_levels[22]	69	1			T28	1		T42	1		T121	2
all_levels[23]	75	1			T17	1		T142	1		T126	1
all_levels[24]	66	1			T11	4		T28	2		T143	1
all_levels[25]	54	1			T11	1		T17	1		T42	1
all_levels[26]	51	1			T28	1		T42	1		T123	1
all_levels[27]	33	1			T20	1		T144	1		T111	1
all_levels[28]	34	1			T20	1		T28	1		T145	1
all_levels[29]	37	1			T28	1		T42	2		T49	1
all_levels[30]	43	1			T139	2		T42	1		T48	2
all_levels[31]	40	1			T146	1		T147	1		T148	1
all_levels[32]	19	1			T149	1		T150	1		T151	2
all_levels[33]	62	1			T152	1		T153	1		T144	1
all_levels[34]	35	1			T28	1		T152	1		T50	1
all_levels[35]	16	1			T40	1		T154	1		T155	1
all_levels[36]	20	1			T141	1		T148	1		T156	1
all_levels[37]	19	1			T157	1		T158	3		T154	1
all_levels[38]	20	1			T28	1		T157	1		T154	1
all_levels[39]	20	1			T140	1		T146	1		T159	1
all_levels[40]	32	1			T7	1		T125	2		T49	1
all_levels[41]	15	1			T13	2		T28	2		T144	1
all_levels[42]	21	1			T41	2		T36	1		T160	3
all_levels[43]	11	1			T161	1		T60	1		T162	1
all_levels[44]	21	1			T125	1		T36	1		T163	1
all_levels[45]	18	1			T17	1		T146	1		T164	1
all_levels[46]	10	1			T165	1		T118	1		T166	1
all_levels[47]	19	1			T145	1		T161	1		T167	1
all_levels[48]	16	1			T28	1		T157	1		T140	1
all_levels[49]	13	1			T161	1		T168	1		T167	1
all_levels[50]	8	1			T60	1		T169	1		T167	1
all_levels[51]	14	1			T122	2		T159	2		T170	1
all_levels[52]	15	1			T40	1		T28	3		T153	1
all_levels[53]	7	1			T163	1		T171	1		T155	1
all_levels[54]	8	1			T172	1		T173	1		T174	1
all_levels[55]	12	1			T40	1		T39	1		T154	1
all_levels[56]	9	1			T11	1		T28	1		T169	1
all_levels[57]	11	1			T140	1		T111	1		T175	1
all_levels[58]	15	1			T153	2		T140	1		T176	1
all_levels[59]	11	1			T177	1		T155	2		T178	1
all_levels[60]	9	1			T109	1		T149	1		T179	1
all_levels[61]	5	1			T56	1		T180	1		T181	1
all_levels[62]	11	1			T35	1		T182	6		T183	1
all_levels[63]	8	1			T183	1		T161	1		T176	1
all_levels[64]	106	1			T11	2		T16	2		T184	1

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

35573611

1

T1

23

T2

55

T3

116952

auto[1]

4961

1

T1

9

T2

6

T4

1

---

Summary for Cross rx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	13	117	90.00	13

Automatically Generated Cross Bins for rx_fifo_level_cg_cc

Uncovered bins

cp_lvl	cp_rst	COUNT	AT LEAST	NUMBER	STATUS
[all_levels[35] , all_levels[36]]	[auto[1]]	--	--	2
[all_levels[41]]	[auto[1]]	0	1	1
[all_levels[44]]	[auto[1]]	0	1	1
[all_levels[46]]	[auto[1]]	0	1	1
[all_levels[50]]	[auto[1]]	0	1	1
[all_levels[53] , all_levels[54] , all_levels[55] , all_levels[56] , all_levels[57]]	[auto[1]]	--	--	5
[all_levels[59]]	[auto[1]]	0	1	1
[all_levels[61]]	[auto[1]]	0	1	1

Covered bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	35375058	1			T1	15		T2	55		T3	116835
all_levels[0]	auto[1]	4469	1			T1	8		T2	6		T4	1
all_levels[1]	auto[0]	189950	1			T3	117		T7	41		T11	28
all_levels[1]	auto[1]	104	1			T7	2		T41	1		T121	1
all_levels[2]	auto[0]	2527	1			T1	2		T7	16		T8	2
all_levels[2]	auto[1]	33	1			T153	1		T185	1		T186	2
all_levels[3]	auto[0]	1139	1			T1	2		T7	14		T8	1
all_levels[3]	auto[1]	21	1			T187	2		T188	2		T189	1
all_levels[4]	auto[0]	729	1			T7	3		T11	3		T45	3
all_levels[4]	auto[1]	14	1			T126	2		T186	1		T190	1
all_levels[5]	auto[0]	529	1			T11	1		T13	2		T45	6
all_levels[5]	auto[1]	17	1			T13	5		T191	2		T192	2
all_levels[6]	auto[0]	414	1			T1	1		T11	3		T14	1
all_levels[6]	auto[1]	14	1			T1	1		T125	1		T185	1
all_levels[7]	auto[0]	321	1			T1	2		T11	3		T14	1
all_levels[7]	auto[1]	11	1			T178	1		T193	1		T194	1
all_levels[8]	auto[0]	265	1			T8	1		T14	1		T139	1
all_levels[8]	auto[1]	22	1			T44	2		T184	1		T57	1
all_levels[9]	auto[0]	243	1			T7	1		T11	1		T17	1
all_levels[9]	auto[1]	13	1			T11	1		T195	1		T190	1
all_levels[10]	auto[0]	215	1			T1	1		T7	1		T11	1
all_levels[10]	auto[1]	10	1			T48	1		T53	1		T196	1
all_levels[11]	auto[0]	193	1			T17	1		T28	1		T42	1
all_levels[11]	auto[1]	10	1			T197	1		T198	2		T199	1
all_levels[12]	auto[0]	165	1			T11	3		T45	1		T40	1
all_levels[12]	auto[1]	5	1			T200	1		T201	1		T202	1
all_levels[13]	auto[0]	140	1			T7	1		T11	1		T139	1
all_levels[13]	auto[1]	8	1			T85	1		T203	1		T204	1
all_levels[14]	auto[0]	136	1			T42	1		T121	1		T47	2
all_levels[14]	auto[1]	10	1			T145	1		T205	1		T206	1
all_levels[15]	auto[0]	106	1			T7	1		T11	1		T42	1
all_levels[15]	auto[1]	11	1			T7	1		T207	1		T208	1
all_levels[16]	auto[0]	95	1			T17	1		T28	1		T122	1
all_levels[16]	auto[1]	21	1			T122	2		T48	1		T157	3
all_levels[17]	auto[0]	85	1			T17	1		T40	1		T28	1
all_levels[17]	auto[1]	10	1			T209	3		T204	1		T210	1
all_levels[18]	auto[0]	80	1			T40	1		T28	1		T42	2
all_levels[18]	auto[1]	6	1			T211	3		T206	1		T212	1
all_levels[19]	auto[0]	76	1			T11	2		T40	1		T42	1
all_levels[19]	auto[1]	11	1			T213	2		T214	1		T201	1
all_levels[20]	auto[0]	74	1			T40	1		T28	1		T47	1
all_levels[20]	auto[1]	7	1			T53	3		T215	1		T216	1
all_levels[21]	auto[0]	61	1			T28	2		T140	1		T141	1
all_levels[21]	auto[1]	6	1			T217	3		T218	2		T219	1
all_levels[22]	auto[0]	61	1			T28	1		T42	1		T121	1
all_levels[22]	auto[1]	8	1			T121	1		T220	2		T221	1
all_levels[23]	auto[0]	72	1			T17	1		T142	1		T126	1
all_levels[23]	auto[1]	3	1			T205	1		T222	1		T223	1
all_levels[24]	auto[0]	57	1			T11	1		T28	2		T143	1
all_levels[24]	auto[1]	9	1			T11	3		T224	1		T205	1
all_levels[25]	auto[0]	48	1			T11	1		T17	1		T42	1
all_levels[25]	auto[1]	6	1			T48	1		T182	2		T225	3
all_levels[26]	auto[0]	46	1			T28	1		T42	1		T123	1
all_levels[26]	auto[1]	5	1			T202	1		T226	2		T227	2
all_levels[27]	auto[0]	29	1			T20	1		T144	1		T111	1
all_levels[27]	auto[1]	4	1			T216	4		-	-		-	-
all_levels[28]	auto[0]	32	1			T20	1		T28	1		T145	1
all_levels[28]	auto[1]	2	1			T218	1		T228	1		-	-
all_levels[29]	auto[0]	34	1			T28	1		T42	2		T49	1
all_levels[29]	auto[1]	3	1			T196	1		T229	2		-	-
all_levels[30]	auto[0]	34	1			T139	1		T42	1		T48	1
all_levels[30]	auto[1]	9	1			T139	1		T48	1		T81	2
all_levels[31]	auto[0]	39	1			T146	1		T147	1		T148	1
all_levels[31]	auto[1]	1	1			T214	1		-	-		-	-
all_levels[32]	auto[0]	18	1			T149	1		T150	1		T151	2
all_levels[32]	auto[1]	1	1			T230	1		-	-		-	-
all_levels[33]	auto[0]	46	1			T152	1		T153	1		T144	1
all_levels[33]	auto[1]	16	1			T231	1		T217	3		T232	3
all_levels[34]	auto[0]	30	1			T28	1		T152	1		T50	1
all_levels[34]	auto[1]	5	1			T233	2		T234	3		-	-
all_levels[35]	auto[0]	16	1			T40	1		T154	1		T155	1
all_levels[36]	auto[0]	20	1			T141	1		T148	1		T156	1
all_levels[37]	auto[0]	17	1			T157	1		T158	1		T154	1
all_levels[37]	auto[1]	2	1			T158	2		-	-		-	-
all_levels[38]	auto[0]	17	1			T28	1		T157	1		T154	1
all_levels[38]	auto[1]	3	1			T235	2		T236	1		-	-
all_levels[39]	auto[0]	18	1			T140	1		T146	1		T159	1
all_levels[39]	auto[1]	2	1			T193	2		-	-		-	-
all_levels[40]	auto[0]	24	1			T7	1		T125	1		T49	1
all_levels[40]	auto[1]	8	1			T125	1		T237	1		T238	3
all_levels[41]	auto[0]	15	1			T13	2		T28	2		T144	1
all_levels[42]	auto[0]	17	1			T41	1		T36	1		T160	1
all_levels[42]	auto[1]	4	1			T41	1		T160	2		T239	1
all_levels[43]	auto[0]	9	1			T161	1		T60	1		T162	1
all_levels[43]	auto[1]	2	1			T240	1		T223	1		-	-
all_levels[44]	auto[0]	21	1			T125	1		T36	1		T163	1
all_levels[45]	auto[0]	17	1			T17	1		T146	1		T164	1
all_levels[45]	auto[1]	1	1			T241	1		-	-		-	-
all_levels[46]	auto[0]	10	1			T165	1		T118	1		T166	1
all_levels[47]	auto[0]	15	1			T145	1		T161	1		T167	1
all_levels[47]	auto[1]	4	1			T242	2		T243	2		-	-
all_levels[48]	auto[0]	13	1			T28	1		T157	1		T140	1
all_levels[48]	auto[1]	3	1			T244	2		T245	1		-	-
all_levels[49]	auto[0]	10	1			T161	1		T168	1		T167	1
all_levels[49]	auto[1]	3	1			T246	2		T247	1		-	-
all_levels[50]	auto[0]	8	1			T60	1		T169	1		T167	1
all_levels[51]	auto[0]	11	1			T122	1		T159	1		T170	1
all_levels[51]	auto[1]	3	1			T122	1		T159	1		T227	1
all_levels[52]	auto[0]	11	1			T40	1		T28	1		T153	1
all_levels[52]	auto[1]	4	1			T28	2		T182	2		-	-
all_levels[53]	auto[0]	7	1			T163	1		T171	1		T155	1
all_levels[54]	auto[0]	8	1			T172	1		T173	1		T174	1
all_levels[55]	auto[0]	12	1			T40	1		T39	1		T154	1
all_levels[56]	auto[0]	9	1			T11	1		T28	1		T169	1
all_levels[57]	auto[0]	11	1			T140	1		T111	1		T175	1
all_levels[58]	auto[0]	12	1			T153	1		T140	1		T176	1
all_levels[58]	auto[1]	3	1			T153	1		T220	2		-	-
all_levels[59]	auto[0]	11	1			T177	1		T155	2		T178	1
all_levels[60]	auto[0]	8	1			T109	1		T149	1		T179	1
all_levels[60]	auto[1]	1	1			T248	1		-	-		-	-
all_levels[61]	auto[0]	5	1			T56	1		T180	1		T181	1
all_levels[62]	auto[0]	9	1			T35	1		T182	5		T183	1
all_levels[62]	auto[1]	2	1			T182	1		T249	1		-	-
all_levels[63]	auto[0]	7	1			T183	1		T161	1		T176	1
all_levels[63]	auto[1]	1	1			T250	1		-	-		-	-
all_levels[64]	auto[0]	96	1			T11	1		T16	2		T184	1
all_levels[64]	auto[1]	10	1			T11	1		T208	1		T251	3