Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	9	0	9	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	125866	1			T1	15		T2	31		T3	421
all_pins[1]	125866	1			T1	15		T2	31		T3	421
all_pins[2]	125866	1			T1	15		T2	31		T3	421
all_pins[3]	125866	1			T1	15		T2	31		T3	421
all_pins[4]	125866	1			T1	15		T2	31		T3	421
all_pins[5]	125866	1			T1	15		T2	31		T3	421
all_pins[6]	125866	1			T1	15		T2	31		T3	421
all_pins[7]	125866	1			T1	15		T2	31		T3	421
all_pins[8]	125866	1			T1	15		T2	31		T3	421

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1081569	1			T1	122		T2	261		T3	3600
values[0x1]	51225	1			T1	13		T2	18		T3	189
transitions[0x0=>0x1]	39652	1			T1	13		T2	18		T3	189
transitions[0x1=>0x0]	39431	1			T1	13		T2	17		T3	189

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	100449	1			T1	5		T2	16		T3	237
all_pins[0]	values[0x1]	25417	1			T1	10		T2	15		T3	184
all_pins[0]	transitions[0x0=>0x1]	24738	1			T1	10		T2	15		T3	184
all_pins[0]	transitions[0x1=>0x0]	1169	1			T11	3		T13	1		T15	6
all_pins[1]	values[0x0]	124018	1			T1	15		T2	31		T3	421
all_pins[1]	values[0x1]	1848	1			T11	5		T13	1		T15	6
all_pins[1]	transitions[0x0=>0x1]	1729	1			T11	5		T13	1		T15	6
all_pins[1]	transitions[0x1=>0x0]	2500	1			T1	1		T2	3		T3	5
all_pins[2]	values[0x0]	123247	1			T1	14		T2	28		T3	416
all_pins[2]	values[0x1]	2619	1			T1	1		T2	3		T3	5
all_pins[2]	transitions[0x0=>0x1]	2569	1			T1	1		T2	3		T3	5
all_pins[2]	transitions[0x1=>0x0]	258	1			T11	2		T15	1		T17	3
all_pins[3]	values[0x0]	125558	1			T1	15		T2	31		T3	421
all_pins[3]	values[0x1]	308	1			T11	3		T15	1		T17	3
all_pins[3]	transitions[0x0=>0x1]	267	1			T11	3		T15	1		T17	1
all_pins[3]	transitions[0x1=>0x0]	418	1			T11	6		T15	6		T17	3
all_pins[4]	values[0x0]	125407	1			T1	15		T2	31		T3	421
all_pins[4]	values[0x1]	459	1			T11	6		T15	6		T17	5
all_pins[4]	transitions[0x0=>0x1]	371	1			T11	6		T15	5		T17	4
all_pins[4]	transitions[0x1=>0x0]	205	1			T20	1		T24	1		T25	1
all_pins[5]	values[0x0]	125573	1			T1	15		T2	31		T3	421
all_pins[5]	values[0x1]	293	1			T15	1		T17	1		T20	1
all_pins[5]	transitions[0x0=>0x1]	240	1			T15	1		T20	1		T24	1
all_pins[5]	transitions[0x1=>0x0]	902	1			T1	2		T11	6		T125	1
all_pins[6]	values[0x0]	124911	1			T1	13		T2	31		T3	421
all_pins[6]	values[0x1]	955	1			T1	2		T11	6		T125	1
all_pins[6]	transitions[0x0=>0x1]	909	1			T1	2		T11	6		T125	1
all_pins[6]	transitions[0x1=>0x0]	365	1			T17	2		T20	5		T28	3
all_pins[7]	values[0x0]	125455	1			T1	15		T2	31		T3	421
all_pins[7]	values[0x1]	411	1			T17	3		T20	5		T28	3
all_pins[7]	transitions[0x0=>0x1]	236	1			T17	1		T20	5		T24	3
all_pins[7]	transitions[0x1=>0x0]	18740	1			T4	1		T5	14		T7	3
all_pins[8]	values[0x0]	106951	1			T1	15		T2	31		T3	421
all_pins[8]	values[0x1]	18915	1			T4	1		T5	14		T7	3
all_pins[8]	transitions[0x0=>0x1]	8593	1			T5	13		T7	1		T8	2
all_pins[8]	transitions[0x1=>0x0]	14874	1			T1	10		T2	14		T3	184