Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::tx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::tx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	35	0	35	100.00
Crosses	66	0	66	100.00

Variables for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	33	0	33	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tx_fifo_level_cg_cc	66	0	66	100.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	8886572	1			T1	7		T2	1		T3	82602
all_levels[1]	1664180	1			T3	1956		T7	6		T8	2
all_levels[2]	271202	1			T3	1949		T7	2		T11	2
all_levels[3]	235351	1			T1	1		T3	1937		T11	3
all_levels[4]	495404	1			T3	1949		T7	1		T11	1
all_levels[5]	335628	1			T1	1		T3	1922		T7	3
all_levels[6]	474532	1			T3	1956		T7	1		T11	56
all_levels[7]	278287	1			T1	3		T3	1951		T14	1
all_levels[8]	329652	1			T3	1931		T7	2		T11	1
all_levels[9]	299386	1			T1	3		T3	965		T7	1
all_levels[10]	574310	1			T1	3		T2	45		T3	965
all_levels[11]	313485	1			T3	948		T7	1		T14	5
all_levels[12]	221593	1			T3	965		T7	2		T11	1
all_levels[13]	350610	1			T3	951		T7	2		T11	1
all_levels[14]	356662	1			T3	961		T7	2		T11	5
all_levels[15]	218624	1			T2	3		T3	964		T7	1
all_levels[16]	287558	1			T3	962		T11	3		T98	32
all_levels[17]	342953	1			T3	961		T7	1		T11	47
all_levels[18]	266679	1			T3	965		T11	4		T98	24
all_levels[19]	213083	1			T3	954		T7	1		T11	55
all_levels[20]	238667	1			T3	939		T11	2		T98	32
all_levels[21]	247279	1			T3	927		T11	50		T98	25
all_levels[22]	373945	1			T3	964		T7	1		T13	5
all_levels[23]	261661	1			T3	827		T7	1		T98	34
all_levels[24]	530478	1			T2	4		T3	495		T11	2
all_levels[25]	222324	1			T1	4		T3	487		T98	26
all_levels[26]	301341	1			T3	495		T11	6		T98	34
all_levels[27]	267204	1			T3	494		T98	25		T44	3
all_levels[28]	274829	1			T2	1		T3	478		T98	32
all_levels[29]	301145	1			T3	486		T98	31		T17	70
all_levels[30]	338888	1			T1	4		T3	490		T98	26
all_levels[31]	908158	1			T1	5		T2	2		T3	516
all_levels[32]	14896367	1			T2	7		T3	640		T11	35

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

35573611

1

T1

23

T2

55

T3

116952

auto[1]

4426

1

T1

8

T2

8

T5

9

---

Summary for Cross tx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	66	0	66	100.00

Automatically Generated Cross Bins for tx_fifo_level_cg_cc

Bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	8883942	1			T1	5		T3	82602		T7	129
all_levels[0]	auto[1]	2630	1			T1	2		T2	1		T5	9
all_levels[1]	auto[0]	1663801	1			T3	1956		T7	6		T8	2
all_levels[1]	auto[1]	379	1			T11	1		T13	4		T44	1
all_levels[2]	auto[0]	271172	1			T3	1949		T7	2		T11	2
all_levels[2]	auto[1]	30	1			T44	1		T184	1		T262	4
all_levels[3]	auto[0]	235264	1			T1	1		T3	1937		T11	3
all_levels[3]	auto[1]	87	1			T41	1		T119	3		T321	6
all_levels[4]	auto[0]	495369	1			T3	1949		T7	1		T11	1
all_levels[4]	auto[1]	35	1			T253	2		T213	1		T195	1
all_levels[5]	auto[0]	335616	1			T1	1		T3	1922		T7	3
all_levels[5]	auto[1]	12	1			T265	1		T145	1		T163	1
all_levels[6]	auto[0]	474493	1			T3	1956		T7	1		T11	51
all_levels[6]	auto[1]	39	1			T11	5		T45	1		T28	1
all_levels[7]	auto[0]	278184	1			T1	3		T3	1951		T14	1
all_levels[7]	auto[1]	103	1			T139	3		T33	1		T56	2
all_levels[8]	auto[0]	329635	1			T3	1931		T7	2		T11	1
all_levels[8]	auto[1]	17	1			T184	1		T153	2		T252	1
all_levels[9]	auto[0]	299363	1			T1	3		T3	965		T7	1
all_levels[9]	auto[1]	23	1			T48	1		T252	1		T322	1
all_levels[10]	auto[0]	574286	1			T1	3		T2	43		T3	965
all_levels[10]	auto[1]	24	1			T2	2		T20	1		T255	1
all_levels[11]	auto[0]	313469	1			T3	948		T7	1		T14	5
all_levels[11]	auto[1]	16	1			T165	1		T209	3		T323	1
all_levels[12]	auto[0]	221577	1			T3	965		T7	2		T11	1
all_levels[12]	auto[1]	16	1			T141	1		T154	3		T324	1
all_levels[13]	auto[0]	350580	1			T3	951		T7	2		T11	1
all_levels[13]	auto[1]	30	1			T153	1		T50	1		T57	2
all_levels[14]	auto[0]	356640	1			T3	961		T7	2		T11	5
all_levels[14]	auto[1]	22	1			T45	1		T260	1		T185	1
all_levels[15]	auto[0]	218554	1			T2	2		T3	964		T7	1
all_levels[15]	auto[1]	70	1			T2	1		T125	2		T267	3
all_levels[16]	auto[0]	287531	1			T3	962		T11	3		T98	32
all_levels[16]	auto[1]	27	1			T122	2		T53	1		T316	3
all_levels[17]	auto[0]	342921	1			T3	961		T7	1		T11	46
all_levels[17]	auto[1]	32	1			T11	1		T157	1		T262	1
all_levels[18]	auto[0]	266663	1			T3	965		T11	4		T98	24
all_levels[18]	auto[1]	16	1			T154	1		T325	1		T209	1
all_levels[19]	auto[0]	213055	1			T3	954		T7	1		T11	55
all_levels[19]	auto[1]	28	1			T57	1		T279	3		T154	2
all_levels[20]	auto[0]	238633	1			T3	939		T11	2		T98	32
all_levels[20]	auto[1]	34	1			T253	2		T213	2		T195	1
all_levels[21]	auto[0]	247242	1			T3	927		T11	50		T98	25
all_levels[21]	auto[1]	37	1			T282	4		T182	1		T326	1
all_levels[22]	auto[0]	373933	1			T3	964		T7	1		T13	4
all_levels[22]	auto[1]	12	1			T13	1		T327	2		T81	1
all_levels[23]	auto[0]	261640	1			T3	827		T7	1		T98	34
all_levels[23]	auto[1]	21	1			T257	1		T278	1		T190	1
all_levels[24]	auto[0]	530458	1			T2	2		T3	495		T11	2
all_levels[24]	auto[1]	20	1			T2	2		T122	1		T263	1
all_levels[25]	auto[0]	222302	1			T1	2		T3	487		T98	26
all_levels[25]	auto[1]	22	1			T1	2		T55	3		T158	2
all_levels[26]	auto[0]	301324	1			T3	495		T11	3		T98	34
all_levels[26]	auto[1]	17	1			T11	3		T274	4		T328	3
all_levels[27]	auto[0]	267188	1			T3	494		T98	25		T44	1
all_levels[27]	auto[1]	16	1			T44	2		T121	2		T49	1
all_levels[28]	auto[0]	274817	1			T2	1		T3	478		T98	32
all_levels[28]	auto[1]	12	1			T28	1		T224	1		T231	1
all_levels[29]	auto[0]	301126	1			T3	486		T98	31		T17	70
all_levels[29]	auto[1]	19	1			T47	1		T157	3		T224	2
all_levels[30]	auto[0]	338862	1			T1	4		T3	490		T98	26
all_levels[30]	auto[1]	26	1			T153	1		T329	1		T81	1
all_levels[31]	auto[0]	908127	1			T1	1		T2	2		T3	516
all_levels[31]	auto[1]	31	1			T1	4		T28	2		T266	1
all_levels[32]	auto[0]	14895844	1			T2	5		T3	640		T11	34
all_levels[32]	auto[1]	523	1			T2	2		T11	1		T98	1