Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.30	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	54	6	48	88.89

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	54	6	48	88.89	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	815	1			T17	14		T24	7		T25	4
all_values[1]	815	1			T17	14		T24	7		T25	4
all_values[2]	815	1			T17	14		T24	7		T25	4
all_values[3]	815	1			T17	14		T24	7		T25	4
all_values[4]	815	1			T17	14		T24	7		T25	4
all_values[5]	815	1			T17	14		T24	7		T25	4
all_values[6]	815	1			T17	14		T24	7		T25	4
all_values[7]	815	1			T17	14		T24	7		T25	4
all_values[8]	815	1			T17	14		T24	7		T25	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4008

1

T17

64

T24

34

T25

17

auto[1]

3327

1

T17

62

T24

29

T25

19

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2472

1

T17

35

T24

20

T25

17

auto[1]

4863

1

T17

91

T24

43

T25

19

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4336

1

T17

67

T24

36

T25

25

auto[1]

2999

1

T17

59

T24

27

T25

11

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	54	6	48	88.89	6
Automatically Generated Cross Bins	54	6	48	88.89	6
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	*	[auto[0]]	--	--	2
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2
[all_values[8]]	[auto[0]]	*	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	251	1			T17	1		T24	3		T25	3
all_values[0]	auto[0]	auto[1]	auto[1]	217	1			T17	8		T24	2		T33	3
all_values[0]	auto[1]	auto[0]	auto[1]	194	1			T17	3		T24	1		T33	5
all_values[0]	auto[1]	auto[1]	auto[1]	153	1			T17	2		T24	1		T25	1
all_values[1]	auto[0]	auto[0]	auto[0]	272	1			T17	4		T24	2		T33	2
all_values[1]	auto[0]	auto[1]	auto[0]	206	1			T17	3		T24	1		T25	2
all_values[1]	auto[1]	auto[0]	auto[1]	193	1			T17	5		T24	2		T25	1
all_values[1]	auto[1]	auto[1]	auto[1]	144	1			T17	2		T24	2		T25	1
all_values[2]	auto[0]	auto[0]	auto[0]	195	1			T17	2		T24	2		T33	6
all_values[2]	auto[0]	auto[0]	auto[1]	71	1			T17	2		T25	1		T33	1
all_values[2]	auto[0]	auto[1]	auto[0]	147	1			T17	2		T24	2		T25	1
all_values[2]	auto[0]	auto[1]	auto[1]	60	1			T17	1		T24	1		T38	1
all_values[2]	auto[1]	auto[0]	auto[1]	196	1			T17	5		T25	2		T33	3
all_values[2]	auto[1]	auto[1]	auto[1]	146	1			T17	2		T24	2		T38	4
all_values[3]	auto[0]	auto[0]	auto[0]	164	1			T17	1		T24	1		T25	1
all_values[3]	auto[0]	auto[0]	auto[1]	65	1			T17	2		T24	1		T33	1
all_values[3]	auto[0]	auto[1]	auto[0]	166	1			T17	1		T24	2		T25	2
all_values[3]	auto[0]	auto[1]	auto[1]	92	1			T17	1		T33	1		T38	3
all_values[3]	auto[1]	auto[0]	auto[1]	178	1			T17	6		T24	2		T33	2
all_values[3]	auto[1]	auto[1]	auto[1]	150	1			T17	3		T24	1		T25	1
all_values[4]	auto[0]	auto[0]	auto[0]	178	1			T17	1		T25	3		T33	4
all_values[4]	auto[0]	auto[0]	auto[1]	86	1			T17	1		T33	1		T38	1
all_values[4]	auto[0]	auto[1]	auto[0]	159	1			T17	4		T24	2		T33	1
all_values[4]	auto[0]	auto[1]	auto[1]	59	1			T17	1		T130	1		T131	1
all_values[4]	auto[1]	auto[0]	auto[1]	184	1			T17	2		T24	3		T25	1
all_values[4]	auto[1]	auto[1]	auto[1]	149	1			T17	5		T24	2		T33	2
all_values[5]	auto[0]	auto[0]	auto[0]	167	1			T17	3		T24	3		T25	2
all_values[5]	auto[0]	auto[0]	auto[1]	84	1			T17	2		T33	3		T132	1
all_values[5]	auto[0]	auto[1]	auto[0]	131	1			T24	1		T25	1		T38	2
all_values[5]	auto[0]	auto[1]	auto[1]	93	1			T33	1		T38	3		T133	1
all_values[5]	auto[1]	auto[0]	auto[1]	191	1			T17	5		T24	2		T33	4
all_values[5]	auto[1]	auto[1]	auto[1]	149	1			T17	4		T24	1		T25	1
all_values[6]	auto[0]	auto[0]	auto[0]	181	1			T17	3		T24	1		T25	2
all_values[6]	auto[0]	auto[0]	auto[1]	68	1			T17	1		T24	1		T33	2
all_values[6]	auto[0]	auto[1]	auto[0]	149	1			T17	3		T24	1		T25	1
all_values[6]	auto[0]	auto[1]	auto[1]	88	1			T17	2		T24	1		T38	1
all_values[6]	auto[1]	auto[0]	auto[1]	189	1			T17	2		T24	2		T33	4
all_values[6]	auto[1]	auto[1]	auto[1]	140	1			T17	3		T24	1		T25	1
all_values[7]	auto[0]	auto[0]	auto[0]	196	1			T17	4		T24	1		T33	2
all_values[7]	auto[0]	auto[0]	auto[1]	73	1			T17	1		T24	1		T38	2
all_values[7]	auto[0]	auto[1]	auto[0]	161	1			T17	4		T24	1		T25	2
all_values[7]	auto[0]	auto[1]	auto[1]	73	1			T17	2		T24	2		T33	5
all_values[7]	auto[1]	auto[0]	auto[1]	171	1			T17	1		T25	1		T33	1
all_values[7]	auto[1]	auto[1]	auto[1]	141	1			T17	2		T24	2		T25	1
all_values[8]	auto[0]	auto[0]	auto[1]	266	1			T17	2		T24	4		T33	5
all_values[8]	auto[0]	auto[1]	auto[1]	218	1			T17	5		T25	4		T33	1
all_values[8]	auto[1]	auto[0]	auto[1]	195	1			T17	5		T24	2		T33	3
all_values[8]	auto[1]	auto[1]	auto[1]	136	1			T17	2		T24	1		T33	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal