Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.10 99.10 97.65 100.00 98.38 100.00 99.48


Total test records in report: 1320
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T1262 /workspace/coverage/cover_reg_top/8.uart_intr_test.649565627 Jun 06 12:53:20 PM PDT 24 Jun 06 12:53:22 PM PDT 24 92940256 ps
T1263 /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.445323945 Jun 06 12:53:51 PM PDT 24 Jun 06 12:53:53 PM PDT 24 53479440 ps
T1264 /workspace/coverage/cover_reg_top/12.uart_tl_errors.2186634859 Jun 06 12:53:33 PM PDT 24 Jun 06 12:53:36 PM PDT 24 75731174 ps
T1265 /workspace/coverage/cover_reg_top/17.uart_intr_test.1946954213 Jun 06 12:53:50 PM PDT 24 Jun 06 12:53:52 PM PDT 24 26468420 ps
T1266 /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.3128444628 Jun 06 12:53:24 PM PDT 24 Jun 06 12:53:26 PM PDT 24 142361680 ps
T70 /workspace/coverage/cover_reg_top/17.uart_csr_rw.3636161609 Jun 06 12:53:57 PM PDT 24 Jun 06 12:53:58 PM PDT 24 17928043 ps
T1267 /workspace/coverage/cover_reg_top/39.uart_intr_test.84800890 Jun 06 12:54:01 PM PDT 24 Jun 06 12:54:03 PM PDT 24 48011531 ps
T1268 /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.906406585 Jun 06 12:53:53 PM PDT 24 Jun 06 12:53:55 PM PDT 24 22221581 ps
T1269 /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.3313210054 Jun 06 12:53:53 PM PDT 24 Jun 06 12:53:55 PM PDT 24 55071101 ps
T1270 /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.2692024453 Jun 06 12:53:51 PM PDT 24 Jun 06 12:53:53 PM PDT 24 223684529 ps
T1271 /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.1582480956 Jun 06 12:53:54 PM PDT 24 Jun 06 12:53:56 PM PDT 24 157990466 ps
T1272 /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.925913932 Jun 06 12:53:20 PM PDT 24 Jun 06 12:53:22 PM PDT 24 41672196 ps
T1273 /workspace/coverage/cover_reg_top/29.uart_intr_test.2569884458 Jun 06 12:53:50 PM PDT 24 Jun 06 12:53:52 PM PDT 24 13195209 ps
T1274 /workspace/coverage/cover_reg_top/23.uart_intr_test.2716374108 Jun 06 12:53:53 PM PDT 24 Jun 06 12:53:55 PM PDT 24 14821080 ps
T1275 /workspace/coverage/cover_reg_top/2.uart_tl_errors.3958916751 Jun 06 12:53:10 PM PDT 24 Jun 06 12:53:14 PM PDT 24 96696325 ps
T1276 /workspace/coverage/cover_reg_top/14.uart_intr_test.1318814704 Jun 06 12:53:40 PM PDT 24 Jun 06 12:53:41 PM PDT 24 12796853 ps
T86 /workspace/coverage/cover_reg_top/11.uart_csr_rw.2485584214 Jun 06 12:53:32 PM PDT 24 Jun 06 12:53:34 PM PDT 24 39914566 ps
T1277 /workspace/coverage/cover_reg_top/1.uart_intr_test.2476524754 Jun 06 12:53:10 PM PDT 24 Jun 06 12:53:13 PM PDT 24 45105596 ps
T1278 /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.3603194752 Jun 06 12:53:40 PM PDT 24 Jun 06 12:53:42 PM PDT 24 15923997 ps
T103 /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.4282819320 Jun 06 12:53:20 PM PDT 24 Jun 06 12:53:22 PM PDT 24 386993815 ps
T1279 /workspace/coverage/cover_reg_top/3.uart_csr_rw.335133741 Jun 06 12:53:11 PM PDT 24 Jun 06 12:53:15 PM PDT 24 23061215 ps
T1280 /workspace/coverage/cover_reg_top/10.uart_intr_test.2303989414 Jun 06 12:53:30 PM PDT 24 Jun 06 12:53:32 PM PDT 24 13557755 ps
T1281 /workspace/coverage/cover_reg_top/18.uart_intr_test.2482776745 Jun 06 12:53:59 PM PDT 24 Jun 06 12:54:01 PM PDT 24 66599413 ps
T1282 /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.1404620174 Jun 06 12:53:12 PM PDT 24 Jun 06 12:53:18 PM PDT 24 1277944874 ps
T1283 /workspace/coverage/cover_reg_top/22.uart_intr_test.1836249628 Jun 06 12:53:51 PM PDT 24 Jun 06 12:53:53 PM PDT 24 12859944 ps
T1284 /workspace/coverage/cover_reg_top/28.uart_intr_test.3040131924 Jun 06 12:53:52 PM PDT 24 Jun 06 12:53:54 PM PDT 24 40151538 ps
T1285 /workspace/coverage/cover_reg_top/8.uart_tl_errors.3008232218 Jun 06 12:53:19 PM PDT 24 Jun 06 12:53:22 PM PDT 24 85345084 ps
T1286 /workspace/coverage/cover_reg_top/6.uart_tl_errors.2613211952 Jun 06 12:53:19 PM PDT 24 Jun 06 12:53:22 PM PDT 24 631972287 ps
T1287 /workspace/coverage/cover_reg_top/14.uart_csr_rw.1419210064 Jun 06 12:53:43 PM PDT 24 Jun 06 12:53:44 PM PDT 24 65788168 ps
T1288 /workspace/coverage/cover_reg_top/0.uart_tl_errors.3369028261 Jun 06 12:53:03 PM PDT 24 Jun 06 12:53:07 PM PDT 24 183799466 ps
T1289 /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.2473889340 Jun 06 12:53:10 PM PDT 24 Jun 06 12:53:15 PM PDT 24 16281660 ps
T1290 /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.2922480386 Jun 06 12:53:30 PM PDT 24 Jun 06 12:53:32 PM PDT 24 311168837 ps
T1291 /workspace/coverage/cover_reg_top/16.uart_intr_test.2096434282 Jun 06 12:53:48 PM PDT 24 Jun 06 12:53:49 PM PDT 24 63095050 ps
T87 /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.2580115422 Jun 06 12:53:13 PM PDT 24 Jun 06 12:53:18 PM PDT 24 16886361 ps
T138 /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.3447764605 Jun 06 12:53:30 PM PDT 24 Jun 06 12:53:32 PM PDT 24 52236916 ps
T1292 /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.4036168724 Jun 06 12:53:02 PM PDT 24 Jun 06 12:53:05 PM PDT 24 88397871 ps
T1293 /workspace/coverage/cover_reg_top/35.uart_intr_test.3189990878 Jun 06 12:53:52 PM PDT 24 Jun 06 12:53:54 PM PDT 24 11952927 ps
T1294 /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.3765430213 Jun 06 12:53:12 PM PDT 24 Jun 06 12:53:17 PM PDT 24 24200482 ps
T1295 /workspace/coverage/cover_reg_top/40.uart_intr_test.2862167602 Jun 06 12:54:01 PM PDT 24 Jun 06 12:54:03 PM PDT 24 48034631 ps
T1296 /workspace/coverage/cover_reg_top/13.uart_tl_errors.2796419199 Jun 06 12:53:42 PM PDT 24 Jun 06 12:53:44 PM PDT 24 55673124 ps
T71 /workspace/coverage/cover_reg_top/18.uart_csr_rw.3748019212 Jun 06 12:53:52 PM PDT 24 Jun 06 12:53:54 PM PDT 24 30666799 ps
T1297 /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.2406290584 Jun 06 12:53:04 PM PDT 24 Jun 06 12:53:05 PM PDT 24 30223412 ps
T72 /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.3282314444 Jun 06 12:53:04 PM PDT 24 Jun 06 12:53:05 PM PDT 24 49441454 ps
T1298 /workspace/coverage/cover_reg_top/33.uart_intr_test.3584961495 Jun 06 12:53:50 PM PDT 24 Jun 06 12:53:52 PM PDT 24 94051272 ps
T1299 /workspace/coverage/cover_reg_top/45.uart_intr_test.3646732404 Jun 06 12:53:59 PM PDT 24 Jun 06 12:54:01 PM PDT 24 12702657 ps
T136 /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.1202284272 Jun 06 12:53:20 PM PDT 24 Jun 06 12:53:22 PM PDT 24 44282852 ps
T1300 /workspace/coverage/cover_reg_top/43.uart_intr_test.4107227420 Jun 06 12:54:00 PM PDT 24 Jun 06 12:54:02 PM PDT 24 39783202 ps
T1301 /workspace/coverage/cover_reg_top/25.uart_intr_test.81652023 Jun 06 12:53:50 PM PDT 24 Jun 06 12:53:52 PM PDT 24 18847710 ps
T1302 /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.1904268778 Jun 06 12:53:04 PM PDT 24 Jun 06 12:53:06 PM PDT 24 130773499 ps
T1303 /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.2510567339 Jun 06 12:53:41 PM PDT 24 Jun 06 12:53:44 PM PDT 24 187956073 ps
T1304 /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.768035313 Jun 06 12:53:41 PM PDT 24 Jun 06 12:53:43 PM PDT 24 93070412 ps
T137 /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.2270519184 Jun 06 12:53:40 PM PDT 24 Jun 06 12:53:43 PM PDT 24 128712244 ps
T1305 /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.1572925115 Jun 06 12:53:12 PM PDT 24 Jun 06 12:53:17 PM PDT 24 14268195 ps
T1306 /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.3734884622 Jun 06 12:53:41 PM PDT 24 Jun 06 12:53:44 PM PDT 24 120627718 ps
T73 /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.183030069 Jun 06 12:53:14 PM PDT 24 Jun 06 12:53:20 PM PDT 24 113657196 ps
T1307 /workspace/coverage/cover_reg_top/2.uart_csr_rw.91790264 Jun 06 12:53:12 PM PDT 24 Jun 06 12:53:17 PM PDT 24 50479075 ps
T1308 /workspace/coverage/cover_reg_top/10.uart_csr_rw.3655319795 Jun 06 12:53:31 PM PDT 24 Jun 06 12:53:33 PM PDT 24 49660741 ps
T74 /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.543962151 Jun 06 12:53:04 PM PDT 24 Jun 06 12:53:05 PM PDT 24 15856087 ps
T1309 /workspace/coverage/cover_reg_top/38.uart_intr_test.1482723589 Jun 06 12:54:02 PM PDT 24 Jun 06 12:54:04 PM PDT 24 12559624 ps
T1310 /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.1342802893 Jun 06 12:53:32 PM PDT 24 Jun 06 12:53:34 PM PDT 24 31249382 ps
T1311 /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.533493716 Jun 06 12:53:53 PM PDT 24 Jun 06 12:53:56 PM PDT 24 52297117 ps
T1312 /workspace/coverage/cover_reg_top/1.uart_csr_rw.2605780266 Jun 06 12:53:10 PM PDT 24 Jun 06 12:53:13 PM PDT 24 48390267 ps
T1313 /workspace/coverage/cover_reg_top/7.uart_csr_rw.3711759463 Jun 06 12:53:27 PM PDT 24 Jun 06 12:53:29 PM PDT 24 18005882 ps
T1314 /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.3523473319 Jun 06 12:53:30 PM PDT 24 Jun 06 12:53:31 PM PDT 24 33477874 ps
T1315 /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.4216392270 Jun 06 12:53:12 PM PDT 24 Jun 06 12:53:16 PM PDT 24 22034169 ps
T1316 /workspace/coverage/cover_reg_top/42.uart_intr_test.2239260044 Jun 06 12:53:59 PM PDT 24 Jun 06 12:54:01 PM PDT 24 16614676 ps
T1317 /workspace/coverage/cover_reg_top/41.uart_intr_test.2024045537 Jun 06 12:53:59 PM PDT 24 Jun 06 12:54:00 PM PDT 24 13633094 ps
T1318 /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.3853832596 Jun 06 12:53:39 PM PDT 24 Jun 06 12:53:41 PM PDT 24 2207150339 ps
T1319 /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.413267978 Jun 06 12:53:12 PM PDT 24 Jun 06 12:53:18 PM PDT 24 476868009 ps
T1320 /workspace/coverage/cover_reg_top/5.uart_tl_errors.3307603474 Jun 06 12:53:23 PM PDT 24 Jun 06 12:53:26 PM PDT 24 61582525 ps

Test location /workspace/coverage/default/5.uart_perf.1501710817
Short name T3
Test name
Test status
Simulation time 15567167032 ps
CPU time 185.17 seconds
Started Jun 06 12:58:11 PM PDT 24
Finished Jun 06 01:01:17 PM PDT 24
Peak memory 200204 kb
Host smart-852453d1-7c63-4ab6-9334-252122cae29c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1501710817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.1501710817
Directory /workspace/5.uart_perf/latest

Test location /workspace/coverage/default/93.uart_stress_all_with_rand_reset.1675942830
Short name T17
Test name
Test status
Simulation time 253690896129 ps
CPU time 930.72 seconds
Started Jun 06 01:02:25 PM PDT 24
Finished Jun 06 01:17:57 PM PDT 24
Peak memory 225036 kb
Host smart-497c8671-0c95-48d4-856e-6e92199a1cd1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675942830 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 93.uart_stress_all_with_rand_reset.1675942830
Directory /workspace/93.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.uart_stress_all.92710190
Short name T11
Test name
Test status
Simulation time 472034214726 ps
CPU time 167.23 seconds
Started Jun 06 01:01:31 PM PDT 24
Finished Jun 06 01:04:20 PM PDT 24
Peak memory 216996 kb
Host smart-ed7b6749-6503-42a2-8184-a0c324cb844c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92710190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.92710190
Directory /workspace/45.uart_stress_all/latest

Test location /workspace/coverage/default/29.uart_stress_all.3730959556
Short name T28
Test name
Test status
Simulation time 373898494085 ps
CPU time 280.01 seconds
Started Jun 06 01:00:05 PM PDT 24
Finished Jun 06 01:04:47 PM PDT 24
Peak memory 200372 kb
Host smart-7504f14a-27e7-47e2-a478-fdf1d5558198
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730959556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.3730959556
Directory /workspace/29.uart_stress_all/latest

Test location /workspace/coverage/default/42.uart_stress_all.3584542636
Short name T141
Test name
Test status
Simulation time 615935618954 ps
CPU time 236.41 seconds
Started Jun 06 01:01:21 PM PDT 24
Finished Jun 06 01:05:18 PM PDT 24
Peak memory 200364 kb
Host smart-1b47ec36-7449-44f1-bc4a-90842e9a619e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584542636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.3584542636
Directory /workspace/42.uart_stress_all/latest

Test location /workspace/coverage/default/48.uart_long_xfer_wo_dly.3182287374
Short name T46
Test name
Test status
Simulation time 155658729508 ps
CPU time 756.74 seconds
Started Jun 06 01:01:49 PM PDT 24
Finished Jun 06 01:14:27 PM PDT 24
Peak memory 200312 kb
Host smart-c4129dc5-c228-4352-a5a4-edfef5109328
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3182287374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.3182287374
Directory /workspace/48.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/21.uart_stress_all.3656477881
Short name T140
Test name
Test status
Simulation time 702354587007 ps
CPU time 573.58 seconds
Started Jun 06 12:59:28 PM PDT 24
Finished Jun 06 01:09:02 PM PDT 24
Peak memory 200268 kb
Host smart-a9758fa3-2b44-41bf-bc98-fac1d88acb3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656477881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.3656477881
Directory /workspace/21.uart_stress_all/latest

Test location /workspace/coverage/default/36.uart_stress_all_with_rand_reset.1788570358
Short name T35
Test name
Test status
Simulation time 383490516788 ps
CPU time 599.2 seconds
Started Jun 06 01:00:47 PM PDT 24
Finished Jun 06 01:10:47 PM PDT 24
Peak memory 216868 kb
Host smart-e2fd169d-9732-493f-9802-ac740860c9ce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788570358 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 36.uart_stress_all_with_rand_reset.1788570358
Directory /workspace/36.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.uart_sec_cm.2395716572
Short name T30
Test name
Test status
Simulation time 178671707 ps
CPU time 0.82 seconds
Started Jun 06 12:58:04 PM PDT 24
Finished Jun 06 12:58:06 PM PDT 24
Peak memory 218692 kb
Host smart-1b604707-1814-4d9e-9a76-c3fa1e65f73c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395716572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.2395716572
Directory /workspace/4.uart_sec_cm/latest

Test location /workspace/coverage/default/110.uart_fifo_reset.2302099517
Short name T263
Test name
Test status
Simulation time 48350066670 ps
CPU time 78.79 seconds
Started Jun 06 01:02:30 PM PDT 24
Finished Jun 06 01:03:49 PM PDT 24
Peak memory 200328 kb
Host smart-ac25c275-39fe-4219-80db-c655ea936bf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302099517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.2302099517
Directory /workspace/110.uart_fifo_reset/latest

Test location /workspace/coverage/default/36.uart_stress_all.529293006
Short name T256
Test name
Test status
Simulation time 261197489840 ps
CPU time 573.76 seconds
Started Jun 06 01:00:46 PM PDT 24
Finished Jun 06 01:10:21 PM PDT 24
Peak memory 208824 kb
Host smart-5de559af-da5c-458b-81b5-e1801f2a90d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529293006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.529293006
Directory /workspace/36.uart_stress_all/latest

Test location /workspace/coverage/default/7.uart_stress_all_with_rand_reset.532573926
Short name T59
Test name
Test status
Simulation time 454270777359 ps
CPU time 240.8 seconds
Started Jun 06 12:58:14 PM PDT 24
Finished Jun 06 01:02:16 PM PDT 24
Peak memory 217068 kb
Host smart-9b74079e-4e1f-4f59-8ca1-840bd650ba7c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532573926 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 7.uart_stress_all_with_rand_reset.532573926
Directory /workspace/7.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.uart_stress_all.197506209
Short name T155
Test name
Test status
Simulation time 292548420576 ps
CPU time 896.2 seconds
Started Jun 06 01:00:39 PM PDT 24
Finished Jun 06 01:15:36 PM PDT 24
Peak memory 200364 kb
Host smart-29a0aa24-8cad-4265-94b3-8543a9db7bd4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197506209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.197506209
Directory /workspace/35.uart_stress_all/latest

Test location /workspace/coverage/default/45.uart_long_xfer_wo_dly.1425350979
Short name T98
Test name
Test status
Simulation time 93812569956 ps
CPU time 219.05 seconds
Started Jun 06 01:01:34 PM PDT 24
Finished Jun 06 01:05:14 PM PDT 24
Peak memory 200356 kb
Host smart-17c87cfa-eb89-4479-a5a9-65136c6eeb7f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1425350979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.1425350979
Directory /workspace/45.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/53.uart_stress_all_with_rand_reset.2532090091
Short name T36
Test name
Test status
Simulation time 943787063150 ps
CPU time 754.28 seconds
Started Jun 06 01:01:59 PM PDT 24
Finished Jun 06 01:14:35 PM PDT 24
Peak memory 216932 kb
Host smart-619dd3b9-5405-4b36-984a-c58ca1d02d27
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532090091 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 53.uart_stress_all_with_rand_reset.2532090091
Directory /workspace/53.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.4282819320
Short name T103
Test name
Test status
Simulation time 386993815 ps
CPU time 1.34 seconds
Started Jun 06 12:53:20 PM PDT 24
Finished Jun 06 12:53:22 PM PDT 24
Peak memory 200076 kb
Host smart-9f91aaed-1d47-42c6-9349-cc8625302e8b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282819320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.4282819320
Directory /workspace/8.uart_tl_intg_err/latest

Test location /workspace/coverage/default/59.uart_stress_all_with_rand_reset.1473611779
Short name T268
Test name
Test status
Simulation time 172079196532 ps
CPU time 761.84 seconds
Started Jun 06 01:01:59 PM PDT 24
Finished Jun 06 01:14:42 PM PDT 24
Peak memory 216836 kb
Host smart-be8b0f77-7aca-40db-a3ea-61559d3848bc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473611779 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 59.uart_stress_all_with_rand_reset.1473611779
Directory /workspace/59.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.uart_rx_parity_err.3621239778
Short name T123
Test name
Test status
Simulation time 145101676881 ps
CPU time 84.56 seconds
Started Jun 06 01:00:25 PM PDT 24
Finished Jun 06 01:01:51 PM PDT 24
Peak memory 200352 kb
Host smart-680d506b-7690-472e-ae12-463dd6561eac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621239778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.3621239778
Directory /workspace/33.uart_rx_parity_err/latest

Test location /workspace/coverage/default/1.uart_alert_test.3227572334
Short name T343
Test name
Test status
Simulation time 11612490 ps
CPU time 0.55 seconds
Started Jun 06 12:58:01 PM PDT 24
Finished Jun 06 12:58:03 PM PDT 24
Peak memory 194976 kb
Host smart-1a5bec5c-341e-4713-9a0b-8c06f7eb1040
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227572334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.3227572334
Directory /workspace/1.uart_alert_test/latest

Test location /workspace/coverage/default/3.uart_stress_all.1711263016
Short name T175
Test name
Test status
Simulation time 304487020026 ps
CPU time 1068.05 seconds
Started Jun 06 12:58:02 PM PDT 24
Finished Jun 06 01:15:52 PM PDT 24
Peak memory 200280 kb
Host smart-1201f7f1-f27c-48db-9e17-2c6b669b19d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711263016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.1711263016
Directory /workspace/3.uart_stress_all/latest

Test location /workspace/coverage/default/75.uart_stress_all_with_rand_reset.1060408528
Short name T161
Test name
Test status
Simulation time 633641970122 ps
CPU time 1301.91 seconds
Started Jun 06 01:02:14 PM PDT 24
Finished Jun 06 01:23:57 PM PDT 24
Peak memory 233472 kb
Host smart-0d0b025f-cf47-4eb0-9f72-b52c1df75507
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060408528 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 75.uart_stress_all_with_rand_reset.1060408528
Directory /workspace/75.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/109.uart_fifo_reset.1815300180
Short name T125
Test name
Test status
Simulation time 122064762368 ps
CPU time 53.59 seconds
Started Jun 06 01:02:30 PM PDT 24
Finished Jun 06 01:03:24 PM PDT 24
Peak memory 200336 kb
Host smart-b093dd83-e877-4972-9994-c125331dea07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815300180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.1815300180
Directory /workspace/109.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.3992962880
Short name T67
Test name
Test status
Simulation time 130764542 ps
CPU time 0.67 seconds
Started Jun 06 12:53:10 PM PDT 24
Finished Jun 06 12:53:13 PM PDT 24
Peak memory 195520 kb
Host smart-b1153442-4880-48e3-af5a-8a3b5a2d646d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992962880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.3992962880
Directory /workspace/0.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.1022414424
Short name T88
Test name
Test status
Simulation time 77700364 ps
CPU time 0.67 seconds
Started Jun 06 12:53:04 PM PDT 24
Finished Jun 06 12:53:05 PM PDT 24
Peak memory 196352 kb
Host smart-3f7ba704-c808-4fc4-b173-0b8c09605182
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022414424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr
_outstanding.1022414424
Directory /workspace/0.uart_same_csr_outstanding/latest

Test location /workspace/coverage/default/76.uart_stress_all_with_rand_reset.1894460857
Short name T130
Test name
Test status
Simulation time 45664240699 ps
CPU time 307.05 seconds
Started Jun 06 01:02:14 PM PDT 24
Finished Jun 06 01:07:22 PM PDT 24
Peak memory 216840 kb
Host smart-d4e93c66-4357-4767-8786-24cc97bbd350
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894460857 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 76.uart_stress_all_with_rand_reset.1894460857
Directory /workspace/76.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.uart_stress_all.3336090042
Short name T157
Test name
Test status
Simulation time 460359483468 ps
CPU time 347.94 seconds
Started Jun 06 12:57:52 PM PDT 24
Finished Jun 06 01:03:41 PM PDT 24
Peak memory 200344 kb
Host smart-a04c9247-8329-4b32-abd4-ff0d6677a3c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336090042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.3336090042
Directory /workspace/1.uart_stress_all/latest

Test location /workspace/coverage/default/5.uart_fifo_full.4177715023
Short name T315
Test name
Test status
Simulation time 93732882474 ps
CPU time 76.34 seconds
Started Jun 06 12:58:12 PM PDT 24
Finished Jun 06 12:59:30 PM PDT 24
Peak memory 200412 kb
Host smart-155f45e8-3664-492a-ae9d-b536936e19f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177715023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.4177715023
Directory /workspace/5.uart_fifo_full/latest

Test location /workspace/coverage/default/238.uart_fifo_reset.1079479628
Short name T153
Test name
Test status
Simulation time 97850073823 ps
CPU time 51 seconds
Started Jun 06 01:03:30 PM PDT 24
Finished Jun 06 01:04:22 PM PDT 24
Peak memory 200336 kb
Host smart-c72f8105-4ccf-4aa6-a450-3993de776df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079479628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.1079479628
Directory /workspace/238.uart_fifo_reset/latest

Test location /workspace/coverage/default/197.uart_fifo_reset.2207629580
Short name T121
Test name
Test status
Simulation time 22684896858 ps
CPU time 31.21 seconds
Started Jun 06 01:02:59 PM PDT 24
Finished Jun 06 01:03:31 PM PDT 24
Peak memory 200348 kb
Host smart-cc87b52e-081a-471c-bbd5-f77f139c78ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207629580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.2207629580
Directory /workspace/197.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_fifo_full.3194348488
Short name T47
Test name
Test status
Simulation time 93012805985 ps
CPU time 194.18 seconds
Started Jun 06 12:59:31 PM PDT 24
Finished Jun 06 01:02:46 PM PDT 24
Peak memory 200384 kb
Host smart-57332b1b-fca9-4e58-a5c4-9e3e948b1236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194348488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.3194348488
Directory /workspace/24.uart_fifo_full/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.3047933377
Short name T135
Test name
Test status
Simulation time 140208255 ps
CPU time 0.96 seconds
Started Jun 06 12:53:30 PM PDT 24
Finished Jun 06 12:53:32 PM PDT 24
Peak memory 199296 kb
Host smart-56ff7c20-024f-41fc-83b5-b3033425c030
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047933377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.3047933377
Directory /workspace/10.uart_tl_intg_err/latest

Test location /workspace/coverage/default/123.uart_fifo_reset.230489524
Short name T227
Test name
Test status
Simulation time 216103636480 ps
CPU time 76.23 seconds
Started Jun 06 01:02:39 PM PDT 24
Finished Jun 06 01:03:58 PM PDT 24
Peak memory 200348 kb
Host smart-cbae03b1-5229-413a-98d0-4622fbed0e4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230489524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.230489524
Directory /workspace/123.uart_fifo_reset/latest

Test location /workspace/coverage/default/268.uart_fifo_reset.3782537015
Short name T179
Test name
Test status
Simulation time 18624021408 ps
CPU time 21.17 seconds
Started Jun 06 01:03:38 PM PDT 24
Finished Jun 06 01:04:00 PM PDT 24
Peak memory 200272 kb
Host smart-e8458773-0183-4730-afe8-3ec6caf9bc3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782537015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.3782537015
Directory /workspace/268.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_fifo_reset.3700459773
Short name T150
Test name
Test status
Simulation time 136760617055 ps
CPU time 24.63 seconds
Started Jun 06 12:58:11 PM PDT 24
Finished Jun 06 12:58:37 PM PDT 24
Peak memory 200272 kb
Host smart-c60955ea-918e-4879-95d8-1f5e78f2df6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700459773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.3700459773
Directory /workspace/6.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_fifo_reset.3537984037
Short name T57
Test name
Test status
Simulation time 14565073192 ps
CPU time 25.23 seconds
Started Jun 06 12:58:34 PM PDT 24
Finished Jun 06 12:59:00 PM PDT 24
Peak memory 200064 kb
Host smart-8b0cd011-d9d8-411d-8c92-9896e44a97a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537984037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.3537984037
Directory /workspace/13.uart_fifo_reset/latest

Test location /workspace/coverage/default/250.uart_fifo_reset.2971622970
Short name T81
Test name
Test status
Simulation time 64893665518 ps
CPU time 105.42 seconds
Started Jun 06 01:03:37 PM PDT 24
Finished Jun 06 01:05:24 PM PDT 24
Peak memory 200284 kb
Host smart-a8d7e032-eb15-458c-bc19-3dc6da32262d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971622970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.2971622970
Directory /workspace/250.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_rx_parity_err.2822986174
Short name T174
Test name
Test status
Simulation time 85011971305 ps
CPU time 82.87 seconds
Started Jun 06 12:58:03 PM PDT 24
Finished Jun 06 12:59:27 PM PDT 24
Peak memory 200288 kb
Host smart-cddb20fd-5f6c-48c1-8be8-cd882b0ca1c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822986174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.2822986174
Directory /workspace/0.uart_rx_parity_err/latest

Test location /workspace/coverage/default/215.uart_fifo_reset.295037765
Short name T218
Test name
Test status
Simulation time 30676128184 ps
CPU time 29.18 seconds
Started Jun 06 01:03:50 PM PDT 24
Finished Jun 06 01:04:20 PM PDT 24
Peak memory 200316 kb
Host smart-9a451186-590b-466d-9f32-ed39c9f350f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295037765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.295037765
Directory /workspace/215.uart_fifo_reset/latest

Test location /workspace/coverage/default/69.uart_fifo_reset.2139513244
Short name T145
Test name
Test status
Simulation time 48218431121 ps
CPU time 76.22 seconds
Started Jun 06 01:02:11 PM PDT 24
Finished Jun 06 01:03:29 PM PDT 24
Peak memory 200216 kb
Host smart-a5c711a5-2b8b-464f-ac57-f21833a5b813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139513244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.2139513244
Directory /workspace/69.uart_fifo_reset/latest

Test location /workspace/coverage/default/10.uart_fifo_overflow.1278552556
Short name T318
Test name
Test status
Simulation time 77335190586 ps
CPU time 15.12 seconds
Started Jun 06 12:58:24 PM PDT 24
Finished Jun 06 12:58:41 PM PDT 24
Peak memory 200084 kb
Host smart-d478d7fd-a5fa-4c09-af7c-d1ae39669dd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278552556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.1278552556
Directory /workspace/10.uart_fifo_overflow/latest

Test location /workspace/coverage/default/148.uart_fifo_reset.4109406134
Short name T744
Test name
Test status
Simulation time 136179843129 ps
CPU time 81.87 seconds
Started Jun 06 01:02:43 PM PDT 24
Finished Jun 06 01:04:06 PM PDT 24
Peak memory 200360 kb
Host smart-8424037e-542a-4429-8e31-4cadb90e675d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109406134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.4109406134
Directory /workspace/148.uart_fifo_reset/latest

Test location /workspace/coverage/default/51.uart_fifo_reset.252893498
Short name T182
Test name
Test status
Simulation time 122052819712 ps
CPU time 25.85 seconds
Started Jun 06 01:01:58 PM PDT 24
Finished Jun 06 01:02:25 PM PDT 24
Peak memory 200404 kb
Host smart-1c422f8d-1098-403b-a0a1-8ac148e6dc3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252893498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.252893498
Directory /workspace/51.uart_fifo_reset/latest

Test location /workspace/coverage/default/53.uart_fifo_reset.100202279
Short name T56
Test name
Test status
Simulation time 108779669491 ps
CPU time 22.44 seconds
Started Jun 06 01:02:00 PM PDT 24
Finished Jun 06 01:02:24 PM PDT 24
Peak memory 200320 kb
Host smart-cf5c60e6-3910-4d7f-a2f4-5939e8075383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100202279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.100202279
Directory /workspace/53.uart_fifo_reset/latest

Test location /workspace/coverage/default/137.uart_fifo_reset.797287726
Short name T85
Test name
Test status
Simulation time 73016447758 ps
CPU time 29.75 seconds
Started Jun 06 01:02:43 PM PDT 24
Finished Jun 06 01:03:14 PM PDT 24
Peak memory 200368 kb
Host smart-192e4712-888c-45c9-9be4-a949f92e169f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797287726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.797287726
Directory /workspace/137.uart_fifo_reset/latest

Test location /workspace/coverage/default/149.uart_fifo_reset.1826303892
Short name T201
Test name
Test status
Simulation time 68919582498 ps
CPU time 133.02 seconds
Started Jun 06 01:02:43 PM PDT 24
Finished Jun 06 01:04:57 PM PDT 24
Peak memory 200304 kb
Host smart-8bb8ed8c-5ada-4404-9c8d-22c59d26b2af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826303892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.1826303892
Directory /workspace/149.uart_fifo_reset/latest

Test location /workspace/coverage/default/154.uart_fifo_reset.4196338614
Short name T158
Test name
Test status
Simulation time 32225557639 ps
CPU time 25.25 seconds
Started Jun 06 01:02:40 PM PDT 24
Finished Jun 06 01:03:07 PM PDT 24
Peak memory 200344 kb
Host smart-76a39501-a1fb-4946-95db-b3a66c743440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196338614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.4196338614
Directory /workspace/154.uart_fifo_reset/latest

Test location /workspace/coverage/default/174.uart_fifo_reset.2074983532
Short name T222
Test name
Test status
Simulation time 8079506512 ps
CPU time 14.2 seconds
Started Jun 06 01:02:58 PM PDT 24
Finished Jun 06 01:03:13 PM PDT 24
Peak memory 200304 kb
Host smart-3cd40e73-1956-4624-a4d4-d6f7166ed1d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074983532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.2074983532
Directory /workspace/174.uart_fifo_reset/latest

Test location /workspace/coverage/default/198.uart_fifo_reset.2046633468
Short name T392
Test name
Test status
Simulation time 135747088670 ps
CPU time 121.17 seconds
Started Jun 06 01:03:13 PM PDT 24
Finished Jun 06 01:05:15 PM PDT 24
Peak memory 200200 kb
Host smart-669689e3-2f86-46ad-8914-45d238932eff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046633468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.2046633468
Directory /workspace/198.uart_fifo_reset/latest

Test location /workspace/coverage/default/295.uart_fifo_reset.1250180941
Short name T1082
Test name
Test status
Simulation time 61326403544 ps
CPU time 12.51 seconds
Started Jun 06 01:03:49 PM PDT 24
Finished Jun 06 01:04:02 PM PDT 24
Peak memory 200616 kb
Host smart-abff087b-ee1b-4f9a-a163-6728057c734f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250180941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.1250180941
Directory /workspace/295.uart_fifo_reset/latest

Test location /workspace/coverage/default/62.uart_stress_all_with_rand_reset.2051840766
Short name T34
Test name
Test status
Simulation time 89762292338 ps
CPU time 567.52 seconds
Started Jun 06 01:02:02 PM PDT 24
Finished Jun 06 01:11:31 PM PDT 24
Peak memory 216480 kb
Host smart-d81bb3f2-ec1f-4a1a-848d-0669464c72f3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051840766 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 62.uart_stress_all_with_rand_reset.2051840766
Directory /workspace/62.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.uart_fifo_full.867164844
Short name T518
Test name
Test status
Simulation time 149596467299 ps
CPU time 31.95 seconds
Started Jun 06 12:57:52 PM PDT 24
Finished Jun 06 12:58:25 PM PDT 24
Peak memory 200360 kb
Host smart-cd20c8a8-8334-4bc7-9593-5c3d14c754a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867164844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.867164844
Directory /workspace/0.uart_fifo_full/latest

Test location /workspace/coverage/default/0.uart_fifo_reset.902113303
Short name T231
Test name
Test status
Simulation time 57726915001 ps
CPU time 99.68 seconds
Started Jun 06 12:57:51 PM PDT 24
Finished Jun 06 12:59:32 PM PDT 24
Peak memory 200276 kb
Host smart-8982b952-a5a3-459a-907c-aef848075cf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902113303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.902113303
Directory /workspace/0.uart_fifo_reset/latest

Test location /workspace/coverage/default/107.uart_fifo_reset.2400312739
Short name T247
Test name
Test status
Simulation time 102417871476 ps
CPU time 142.43 seconds
Started Jun 06 01:02:31 PM PDT 24
Finished Jun 06 01:04:54 PM PDT 24
Peak memory 200344 kb
Host smart-f463eaf1-0f6f-40e5-83f9-9122d19fbd92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400312739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.2400312739
Directory /workspace/107.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_fifo_reset.2476908850
Short name T250
Test name
Test status
Simulation time 133918886837 ps
CPU time 69.97 seconds
Started Jun 06 12:58:27 PM PDT 24
Finished Jun 06 12:59:38 PM PDT 24
Peak memory 200272 kb
Host smart-161b55a1-15d5-45fb-8784-9921b4a9c7cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476908850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.2476908850
Directory /workspace/11.uart_fifo_reset/latest

Test location /workspace/coverage/default/122.uart_fifo_reset.1649389138
Short name T235
Test name
Test status
Simulation time 58506760944 ps
CPU time 150.27 seconds
Started Jun 06 01:02:35 PM PDT 24
Finished Jun 06 01:05:07 PM PDT 24
Peak memory 200340 kb
Host smart-d41299a7-cfe3-4ace-bd57-0cab2a106928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649389138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.1649389138
Directory /workspace/122.uart_fifo_reset/latest

Test location /workspace/coverage/default/129.uart_fifo_reset.456748771
Short name T628
Test name
Test status
Simulation time 24064680790 ps
CPU time 19.71 seconds
Started Jun 06 01:02:39 PM PDT 24
Finished Jun 06 01:03:01 PM PDT 24
Peak memory 200340 kb
Host smart-b755c0d0-de13-4ccf-af7e-69bbd62d423b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456748771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.456748771
Directory /workspace/129.uart_fifo_reset/latest

Test location /workspace/coverage/default/131.uart_fifo_reset.2808843076
Short name T7
Test name
Test status
Simulation time 124115394258 ps
CPU time 102.38 seconds
Started Jun 06 01:02:38 PM PDT 24
Finished Jun 06 01:04:23 PM PDT 24
Peak memory 200300 kb
Host smart-787bc0d3-e252-4317-93e3-0c2d96a9aa74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808843076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.2808843076
Directory /workspace/131.uart_fifo_reset/latest

Test location /workspace/coverage/default/134.uart_fifo_reset.3979295506
Short name T229
Test name
Test status
Simulation time 31660821233 ps
CPU time 51.42 seconds
Started Jun 06 01:02:45 PM PDT 24
Finished Jun 06 01:03:37 PM PDT 24
Peak memory 200356 kb
Host smart-9d99202b-f806-49b0-890c-5a0ab0b70f9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979295506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.3979295506
Directory /workspace/134.uart_fifo_reset/latest

Test location /workspace/coverage/default/136.uart_fifo_reset.834473323
Short name T245
Test name
Test status
Simulation time 48436498188 ps
CPU time 41.1 seconds
Started Jun 06 01:02:41 PM PDT 24
Finished Jun 06 01:03:24 PM PDT 24
Peak memory 200328 kb
Host smart-7359c2fd-ce4f-4146-82d7-372078415b92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834473323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.834473323
Directory /workspace/136.uart_fifo_reset/latest

Test location /workspace/coverage/default/171.uart_fifo_reset.2589767934
Short name T240
Test name
Test status
Simulation time 47713440198 ps
CPU time 77.54 seconds
Started Jun 06 01:02:49 PM PDT 24
Finished Jun 06 01:04:07 PM PDT 24
Peak memory 200220 kb
Host smart-74d1d991-df09-4d74-9d2b-196b2da32d7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589767934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.2589767934
Directory /workspace/171.uart_fifo_reset/latest

Test location /workspace/coverage/default/189.uart_fifo_reset.1868207949
Short name T41
Test name
Test status
Simulation time 109273527167 ps
CPU time 89.14 seconds
Started Jun 06 01:03:02 PM PDT 24
Finished Jun 06 01:04:32 PM PDT 24
Peak memory 200348 kb
Host smart-31fd5e4e-d8b2-49e4-9807-930b6c75ba1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868207949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.1868207949
Directory /workspace/189.uart_fifo_reset/latest

Test location /workspace/coverage/default/194.uart_fifo_reset.2534271350
Short name T248
Test name
Test status
Simulation time 44474792260 ps
CPU time 13.21 seconds
Started Jun 06 01:03:00 PM PDT 24
Finished Jun 06 01:03:14 PM PDT 24
Peak memory 200240 kb
Host smart-3b4f46c9-f849-41ce-80c1-c6234f9fac4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534271350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.2534271350
Directory /workspace/194.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_fifo_reset.3778969716
Short name T214
Test name
Test status
Simulation time 32492492671 ps
CPU time 14.37 seconds
Started Jun 06 12:58:04 PM PDT 24
Finished Jun 06 12:58:19 PM PDT 24
Peak memory 200356 kb
Host smart-0987f9b7-d5c7-4112-aa5f-b105fa1d5a6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778969716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.3778969716
Directory /workspace/2.uart_fifo_reset/latest

Test location /workspace/coverage/default/240.uart_fifo_reset.1049802164
Short name T241
Test name
Test status
Simulation time 32876260577 ps
CPU time 17.86 seconds
Started Jun 06 01:03:28 PM PDT 24
Finished Jun 06 01:03:47 PM PDT 24
Peak memory 200364 kb
Host smart-596ef244-3eef-417f-b822-15d36b32003d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049802164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.1049802164
Directory /workspace/240.uart_fifo_reset/latest

Test location /workspace/coverage/default/270.uart_fifo_reset.1755282754
Short name T243
Test name
Test status
Simulation time 12398082872 ps
CPU time 19.44 seconds
Started Jun 06 01:03:39 PM PDT 24
Finished Jun 06 01:04:00 PM PDT 24
Peak memory 200296 kb
Host smart-568f71ae-4fbe-4751-bd47-9080fa0a9476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755282754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.1755282754
Directory /workspace/270.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_fifo_reset.2518254265
Short name T216
Test name
Test status
Simulation time 147546816125 ps
CPU time 64.5 seconds
Started Jun 06 01:00:06 PM PDT 24
Finished Jun 06 01:01:12 PM PDT 24
Peak memory 200328 kb
Host smart-423d5e89-d8f0-41de-a27e-e20bca409807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518254265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.2518254265
Directory /workspace/30.uart_fifo_reset/latest

Test location /workspace/coverage/default/36.uart_fifo_reset.2011243015
Short name T233
Test name
Test status
Simulation time 130051474714 ps
CPU time 57.95 seconds
Started Jun 06 01:00:38 PM PDT 24
Finished Jun 06 01:01:37 PM PDT 24
Peak memory 200328 kb
Host smart-33279cea-b1bf-4510-aeee-10a911c53118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011243015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.2011243015
Directory /workspace/36.uart_fifo_reset/latest

Test location /workspace/coverage/default/57.uart_fifo_reset.4280746487
Short name T193
Test name
Test status
Simulation time 29505452945 ps
CPU time 48.7 seconds
Started Jun 06 01:02:02 PM PDT 24
Finished Jun 06 01:02:52 PM PDT 24
Peak memory 200388 kb
Host smart-ce7e7ed1-d1e7-4ac5-a2c9-e222ae565ddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280746487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.4280746487
Directory /workspace/57.uart_fifo_reset/latest

Test location /workspace/coverage/default/75.uart_fifo_reset.2104775242
Short name T230
Test name
Test status
Simulation time 61270586292 ps
CPU time 27.29 seconds
Started Jun 06 01:02:15 PM PDT 24
Finished Jun 06 01:02:43 PM PDT 24
Peak memory 200344 kb
Host smart-56265965-8b41-4caa-8d1e-4df76ec84428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104775242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.2104775242
Directory /workspace/75.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.2463032009
Short name T1231
Test name
Test status
Simulation time 209979489 ps
CPU time 2.23 seconds
Started Jun 06 12:53:04 PM PDT 24
Finished Jun 06 12:53:07 PM PDT 24
Peak memory 198324 kb
Host smart-ea0b8158-9c06-4b89-94a6-5a20b6259e6a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463032009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.2463032009
Directory /workspace/0.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.2406290584
Short name T1297
Test name
Test status
Simulation time 30223412 ps
CPU time 0.58 seconds
Started Jun 06 12:53:04 PM PDT 24
Finished Jun 06 12:53:05 PM PDT 24
Peak memory 196092 kb
Host smart-e468148f-33d8-4957-a351-eb6c54017c75
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406290584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.2406290584
Directory /workspace/0.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.608316527
Short name T1206
Test name
Test status
Simulation time 36837148 ps
CPU time 0.65 seconds
Started Jun 06 12:53:03 PM PDT 24
Finished Jun 06 12:53:05 PM PDT 24
Peak memory 198176 kb
Host smart-83933241-ba61-4bee-ba03-c1194c0958e8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608316527 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.608316527
Directory /workspace/0.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_rw.454091468
Short name T1230
Test name
Test status
Simulation time 16707839 ps
CPU time 0.65 seconds
Started Jun 06 12:53:03 PM PDT 24
Finished Jun 06 12:53:04 PM PDT 24
Peak memory 196036 kb
Host smart-c34befe7-ffba-498c-96e0-559faedc9aa4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454091468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.454091468
Directory /workspace/0.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.uart_intr_test.3068201831
Short name T1207
Test name
Test status
Simulation time 72208631 ps
CPU time 0.57 seconds
Started Jun 06 12:53:04 PM PDT 24
Finished Jun 06 12:53:06 PM PDT 24
Peak memory 195012 kb
Host smart-5f8e9b76-1f35-4f6b-8fb0-6d7379fd59da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068201831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.3068201831
Directory /workspace/0.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_errors.3369028261
Short name T1288
Test name
Test status
Simulation time 183799466 ps
CPU time 2.13 seconds
Started Jun 06 12:53:03 PM PDT 24
Finished Jun 06 12:53:07 PM PDT 24
Peak memory 200652 kb
Host smart-077f5e86-6307-4b1e-a484-7ef5ad548b0f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369028261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.3369028261
Directory /workspace/0.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.4036168724
Short name T1292
Test name
Test status
Simulation time 88397871 ps
CPU time 1.32 seconds
Started Jun 06 12:53:02 PM PDT 24
Finished Jun 06 12:53:05 PM PDT 24
Peak memory 199852 kb
Host smart-997eab8c-1c9c-4395-8544-3714955e03b9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036168724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.4036168724
Directory /workspace/0.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.2884516136
Short name T76
Test name
Test status
Simulation time 238253423 ps
CPU time 0.77 seconds
Started Jun 06 12:53:04 PM PDT 24
Finished Jun 06 12:53:06 PM PDT 24
Peak memory 197060 kb
Host smart-1343aecf-cfb3-4990-9baa-b3433ec37e36
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884516136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.2884516136
Directory /workspace/1.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.1995343555
Short name T1201
Test name
Test status
Simulation time 119642590 ps
CPU time 2.19 seconds
Started Jun 06 12:53:09 PM PDT 24
Finished Jun 06 12:53:12 PM PDT 24
Peak memory 198480 kb
Host smart-73a2c5ac-7d79-442a-9d49-b8fce5187910
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995343555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.1995343555
Directory /workspace/1.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.3282314444
Short name T72
Test name
Test status
Simulation time 49441454 ps
CPU time 0.62 seconds
Started Jun 06 12:53:04 PM PDT 24
Finished Jun 06 12:53:05 PM PDT 24
Peak memory 196044 kb
Host smart-1771a467-5fb4-4467-9160-4bb57a5194ec
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282314444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.3282314444
Directory /workspace/1.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.822376815
Short name T1214
Test name
Test status
Simulation time 25694211 ps
CPU time 1.03 seconds
Started Jun 06 12:53:05 PM PDT 24
Finished Jun 06 12:53:07 PM PDT 24
Peak memory 200652 kb
Host smart-e538ed02-3906-47be-9358-c275359cd3ec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822376815 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.822376815
Directory /workspace/1.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_rw.2605780266
Short name T1312
Test name
Test status
Simulation time 48390267 ps
CPU time 0.55 seconds
Started Jun 06 12:53:10 PM PDT 24
Finished Jun 06 12:53:13 PM PDT 24
Peak memory 196060 kb
Host smart-c41b4940-d72d-4f70-8594-ad50be1934eb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605780266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.2605780266
Directory /workspace/1.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.uart_intr_test.2476524754
Short name T1277
Test name
Test status
Simulation time 45105596 ps
CPU time 0.56 seconds
Started Jun 06 12:53:10 PM PDT 24
Finished Jun 06 12:53:13 PM PDT 24
Peak memory 195108 kb
Host smart-468ce23e-7a9f-40da-b8a1-2ea0ce5cf6a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476524754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.2476524754
Directory /workspace/1.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.1013224657
Short name T1256
Test name
Test status
Simulation time 35297570 ps
CPU time 0.8 seconds
Started Jun 06 12:53:28 PM PDT 24
Finished Jun 06 12:53:29 PM PDT 24
Peak memory 197772 kb
Host smart-36bd5920-a0dc-413c-adde-faedd86ca0fc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013224657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr
_outstanding.1013224657
Directory /workspace/1.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_errors.877407502
Short name T1249
Test name
Test status
Simulation time 348053396 ps
CPU time 1.67 seconds
Started Jun 06 12:53:02 PM PDT 24
Finished Jun 06 12:53:05 PM PDT 24
Peak memory 200784 kb
Host smart-3dc580ed-684d-47d1-92d1-617e7e2ea2c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877407502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.877407502
Directory /workspace/1.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.916657385
Short name T102
Test name
Test status
Simulation time 754379756 ps
CPU time 1.1 seconds
Started Jun 06 12:53:02 PM PDT 24
Finished Jun 06 12:53:04 PM PDT 24
Peak memory 199696 kb
Host smart-0cfa6c6d-c698-42b2-9003-8891badc7514
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916657385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.916657385
Directory /workspace/1.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.326850268
Short name T1258
Test name
Test status
Simulation time 34002666 ps
CPU time 1.49 seconds
Started Jun 06 12:53:31 PM PDT 24
Finished Jun 06 12:53:34 PM PDT 24
Peak memory 200712 kb
Host smart-23ca2d64-6045-4c2f-8a7f-4675511647e1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326850268 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.326850268
Directory /workspace/10.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_rw.3655319795
Short name T1308
Test name
Test status
Simulation time 49660741 ps
CPU time 0.66 seconds
Started Jun 06 12:53:31 PM PDT 24
Finished Jun 06 12:53:33 PM PDT 24
Peak memory 196140 kb
Host smart-2f2b4d3d-2679-43b4-85a8-2c4893a6e43a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655319795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.3655319795
Directory /workspace/10.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.uart_intr_test.2303989414
Short name T1280
Test name
Test status
Simulation time 13557755 ps
CPU time 0.6 seconds
Started Jun 06 12:53:30 PM PDT 24
Finished Jun 06 12:53:32 PM PDT 24
Peak memory 195128 kb
Host smart-6ddda59c-7d82-4319-925e-eee5a9e5a5fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303989414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.2303989414
Directory /workspace/10.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.1294851196
Short name T1212
Test name
Test status
Simulation time 28768296 ps
CPU time 0.76 seconds
Started Jun 06 12:53:33 PM PDT 24
Finished Jun 06 12:53:35 PM PDT 24
Peak memory 197196 kb
Host smart-daadc60d-59d0-4163-b911-06bb6d6ceb9f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294851196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_cs
r_outstanding.1294851196
Directory /workspace/10.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_errors.318931972
Short name T1205
Test name
Test status
Simulation time 121613105 ps
CPU time 1.49 seconds
Started Jun 06 12:53:30 PM PDT 24
Finished Jun 06 12:53:32 PM PDT 24
Peak memory 200684 kb
Host smart-fa10379d-8a69-491d-acc2-3978048c7cd2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318931972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.318931972
Directory /workspace/10.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.3002770009
Short name T1203
Test name
Test status
Simulation time 24619725 ps
CPU time 0.68 seconds
Started Jun 06 12:53:31 PM PDT 24
Finished Jun 06 12:53:33 PM PDT 24
Peak memory 198320 kb
Host smart-988a663c-bf2c-4564-a381-ea6226dc65ef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002770009 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.3002770009
Directory /workspace/11.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_rw.2485584214
Short name T86
Test name
Test status
Simulation time 39914566 ps
CPU time 0.59 seconds
Started Jun 06 12:53:32 PM PDT 24
Finished Jun 06 12:53:34 PM PDT 24
Peak memory 195972 kb
Host smart-0233a932-f842-4c05-a813-ab904d5e1cfd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485584214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.2485584214
Directory /workspace/11.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.uart_intr_test.963250888
Short name T1193
Test name
Test status
Simulation time 34467610 ps
CPU time 0.59 seconds
Started Jun 06 12:53:31 PM PDT 24
Finished Jun 06 12:53:33 PM PDT 24
Peak memory 195084 kb
Host smart-a051b412-2374-44a5-96e2-250bc7199ed9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963250888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.963250888
Directory /workspace/11.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.2353056241
Short name T95
Test name
Test status
Simulation time 55764762 ps
CPU time 0.75 seconds
Started Jun 06 12:53:30 PM PDT 24
Finished Jun 06 12:53:32 PM PDT 24
Peak memory 196852 kb
Host smart-9e7dcc19-c358-4d36-aee0-d4fa16ca6c12
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353056241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_cs
r_outstanding.2353056241
Directory /workspace/11.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_errors.901147163
Short name T1234
Test name
Test status
Simulation time 181683783 ps
CPU time 1.19 seconds
Started Jun 06 12:53:32 PM PDT 24
Finished Jun 06 12:53:35 PM PDT 24
Peak memory 200700 kb
Host smart-2fc9ee12-e5aa-4028-861f-59a5dd7623f0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901147163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.901147163
Directory /workspace/11.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.3447764605
Short name T138
Test name
Test status
Simulation time 52236916 ps
CPU time 1.03 seconds
Started Jun 06 12:53:30 PM PDT 24
Finished Jun 06 12:53:32 PM PDT 24
Peak memory 199344 kb
Host smart-86aee378-8bdf-41ef-8ded-309b0de58b9b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447764605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.3447764605
Directory /workspace/11.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.3734884622
Short name T1306
Test name
Test status
Simulation time 120627718 ps
CPU time 0.99 seconds
Started Jun 06 12:53:41 PM PDT 24
Finished Jun 06 12:53:44 PM PDT 24
Peak memory 200508 kb
Host smart-52be0dfc-839b-48da-a2ff-bf6b1d40ef61
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734884622 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.3734884622
Directory /workspace/12.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_rw.308690451
Short name T69
Test name
Test status
Simulation time 92008645 ps
CPU time 0.6 seconds
Started Jun 06 12:53:31 PM PDT 24
Finished Jun 06 12:53:33 PM PDT 24
Peak memory 196348 kb
Host smart-d9b7a8a6-3a4f-4abc-bf13-70fd3d30e192
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308690451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.308690451
Directory /workspace/12.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.uart_intr_test.593735915
Short name T1239
Test name
Test status
Simulation time 70471209 ps
CPU time 0.53 seconds
Started Jun 06 12:53:30 PM PDT 24
Finished Jun 06 12:53:31 PM PDT 24
Peak memory 195004 kb
Host smart-b6345bc3-6817-4c3f-9c5c-bc7fe28c6e29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593735915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.593735915
Directory /workspace/12.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.3833640418
Short name T1246
Test name
Test status
Simulation time 46265948 ps
CPU time 0.68 seconds
Started Jun 06 12:53:41 PM PDT 24
Finished Jun 06 12:53:43 PM PDT 24
Peak memory 196204 kb
Host smart-5f397d79-6cd6-49b9-9e0c-e3be45cbb1ef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833640418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_cs
r_outstanding.3833640418
Directory /workspace/12.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_errors.2186634859
Short name T1264
Test name
Test status
Simulation time 75731174 ps
CPU time 1.92 seconds
Started Jun 06 12:53:33 PM PDT 24
Finished Jun 06 12:53:36 PM PDT 24
Peak memory 200648 kb
Host smart-e0abec75-5bbf-4ab1-bb1c-48572dfb448d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186634859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.2186634859
Directory /workspace/12.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.3911876866
Short name T1250
Test name
Test status
Simulation time 88072583 ps
CPU time 0.99 seconds
Started Jun 06 12:53:31 PM PDT 24
Finished Jun 06 12:53:33 PM PDT 24
Peak memory 199780 kb
Host smart-9ef10d98-de0c-469e-8199-fed0bfed9e48
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911876866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.3911876866
Directory /workspace/12.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.768035313
Short name T1304
Test name
Test status
Simulation time 93070412 ps
CPU time 0.78 seconds
Started Jun 06 12:53:41 PM PDT 24
Finished Jun 06 12:53:43 PM PDT 24
Peak memory 199712 kb
Host smart-862ac21c-f319-4b49-b577-7f23b15b8fa6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768035313 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.768035313
Directory /workspace/13.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_rw.1506027097
Short name T68
Test name
Test status
Simulation time 26231034 ps
CPU time 0.6 seconds
Started Jun 06 12:53:43 PM PDT 24
Finished Jun 06 12:53:45 PM PDT 24
Peak memory 196304 kb
Host smart-222bf9d4-8409-4d81-9d83-ce23fa045fcb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506027097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.1506027097
Directory /workspace/13.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.uart_intr_test.3763768686
Short name T1233
Test name
Test status
Simulation time 51387381 ps
CPU time 0.57 seconds
Started Jun 06 12:53:42 PM PDT 24
Finished Jun 06 12:53:44 PM PDT 24
Peak memory 195028 kb
Host smart-afc0df61-f0da-4c23-a291-93fe968ee15f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763768686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.3763768686
Directory /workspace/13.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.2466429014
Short name T1237
Test name
Test status
Simulation time 22256187 ps
CPU time 0.69 seconds
Started Jun 06 12:53:42 PM PDT 24
Finished Jun 06 12:53:44 PM PDT 24
Peak memory 197456 kb
Host smart-b0dd1a66-2505-4d92-a9fe-49b76474fcdf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466429014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_cs
r_outstanding.2466429014
Directory /workspace/13.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_errors.2796419199
Short name T1296
Test name
Test status
Simulation time 55673124 ps
CPU time 0.92 seconds
Started Jun 06 12:53:42 PM PDT 24
Finished Jun 06 12:53:44 PM PDT 24
Peak memory 200452 kb
Host smart-cc61fed3-0f9c-403c-956e-59bdea5d758c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796419199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.2796419199
Directory /workspace/13.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.2510567339
Short name T1303
Test name
Test status
Simulation time 187956073 ps
CPU time 1.01 seconds
Started Jun 06 12:53:41 PM PDT 24
Finished Jun 06 12:53:44 PM PDT 24
Peak memory 199908 kb
Host smart-e1c91628-55d2-412f-9576-04a9467ffaa4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510567339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.2510567339
Directory /workspace/13.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.4112527589
Short name T1222
Test name
Test status
Simulation time 19336597 ps
CPU time 0.69 seconds
Started Jun 06 12:53:40 PM PDT 24
Finished Jun 06 12:53:42 PM PDT 24
Peak memory 198836 kb
Host smart-cef66e76-586e-4fb2-9452-79565563ce0e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112527589 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.4112527589
Directory /workspace/14.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_rw.1419210064
Short name T1287
Test name
Test status
Simulation time 65788168 ps
CPU time 0.61 seconds
Started Jun 06 12:53:43 PM PDT 24
Finished Jun 06 12:53:44 PM PDT 24
Peak memory 196104 kb
Host smart-cd892a17-d89b-42cc-878e-90076f4c8fff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419210064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.1419210064
Directory /workspace/14.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.uart_intr_test.1318814704
Short name T1276
Test name
Test status
Simulation time 12796853 ps
CPU time 0.59 seconds
Started Jun 06 12:53:40 PM PDT 24
Finished Jun 06 12:53:41 PM PDT 24
Peak memory 195024 kb
Host smart-0b6dc1a6-af88-4b81-ba89-809199cefd8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318814704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.1318814704
Directory /workspace/14.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.3603194752
Short name T1278
Test name
Test status
Simulation time 15923997 ps
CPU time 0.7 seconds
Started Jun 06 12:53:40 PM PDT 24
Finished Jun 06 12:53:42 PM PDT 24
Peak memory 197512 kb
Host smart-17170340-bf21-4a76-86f2-8a6e494e06fa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603194752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_cs
r_outstanding.3603194752
Directory /workspace/14.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_errors.4141239565
Short name T1211
Test name
Test status
Simulation time 71086149 ps
CPU time 1.17 seconds
Started Jun 06 12:53:40 PM PDT 24
Finished Jun 06 12:53:43 PM PDT 24
Peak memory 200788 kb
Host smart-c13c162b-3586-4bf4-99f6-8290981d1086
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141239565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.4141239565
Directory /workspace/14.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.3853832596
Short name T1318
Test name
Test status
Simulation time 2207150339 ps
CPU time 1.19 seconds
Started Jun 06 12:53:39 PM PDT 24
Finished Jun 06 12:53:41 PM PDT 24
Peak memory 199792 kb
Host smart-3a064798-6887-4b15-a25b-014569e3c571
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853832596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.3853832596
Directory /workspace/14.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.2620643290
Short name T1224
Test name
Test status
Simulation time 17588053 ps
CPU time 0.63 seconds
Started Jun 06 12:53:41 PM PDT 24
Finished Jun 06 12:53:43 PM PDT 24
Peak memory 197352 kb
Host smart-0dd5f18c-5469-4dea-966a-a389b6779cb3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620643290 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.2620643290
Directory /workspace/15.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_rw.613605495
Short name T94
Test name
Test status
Simulation time 42316554 ps
CPU time 0.58 seconds
Started Jun 06 12:53:42 PM PDT 24
Finished Jun 06 12:53:44 PM PDT 24
Peak memory 196076 kb
Host smart-2ae9e0d2-507f-4dab-b52e-539785513520
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613605495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.613605495
Directory /workspace/15.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.uart_intr_test.3969715131
Short name T1228
Test name
Test status
Simulation time 49711777 ps
CPU time 0.56 seconds
Started Jun 06 12:53:41 PM PDT 24
Finished Jun 06 12:53:42 PM PDT 24
Peak memory 195068 kb
Host smart-af736531-6cbc-4b38-b6d6-dfa70e580c4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969715131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.3969715131
Directory /workspace/15.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.3339480669
Short name T93
Test name
Test status
Simulation time 114490311 ps
CPU time 0.62 seconds
Started Jun 06 12:53:40 PM PDT 24
Finished Jun 06 12:53:41 PM PDT 24
Peak memory 195484 kb
Host smart-0b90319c-7db4-4edd-93d6-6d1f4a4c3432
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339480669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_cs
r_outstanding.3339480669
Directory /workspace/15.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_errors.4194333309
Short name T1254
Test name
Test status
Simulation time 206063761 ps
CPU time 1.44 seconds
Started Jun 06 12:53:42 PM PDT 24
Finished Jun 06 12:53:45 PM PDT 24
Peak memory 200760 kb
Host smart-ceb8fd3f-01f8-4c1f-99ad-073e04eaaea8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194333309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.4194333309
Directory /workspace/15.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.2270519184
Short name T137
Test name
Test status
Simulation time 128712244 ps
CPU time 1.29 seconds
Started Jun 06 12:53:40 PM PDT 24
Finished Jun 06 12:53:43 PM PDT 24
Peak memory 200100 kb
Host smart-6a08592b-94a9-48dd-b972-c807ae5585b0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270519184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.2270519184
Directory /workspace/15.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.1013160808
Short name T1248
Test name
Test status
Simulation time 20554264 ps
CPU time 0.94 seconds
Started Jun 06 12:53:51 PM PDT 24
Finished Jun 06 12:53:54 PM PDT 24
Peak memory 200580 kb
Host smart-fa7195b1-62fc-4482-ae3c-ace162136594
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013160808 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.1013160808
Directory /workspace/16.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_rw.1520392576
Short name T1217
Test name
Test status
Simulation time 80667598 ps
CPU time 0.61 seconds
Started Jun 06 12:53:50 PM PDT 24
Finished Jun 06 12:53:52 PM PDT 24
Peak memory 196212 kb
Host smart-bb1c4692-58d1-4fd3-aaff-8536ebb0afc1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520392576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.1520392576
Directory /workspace/16.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.uart_intr_test.2096434282
Short name T1291
Test name
Test status
Simulation time 63095050 ps
CPU time 0.56 seconds
Started Jun 06 12:53:48 PM PDT 24
Finished Jun 06 12:53:49 PM PDT 24
Peak memory 195064 kb
Host smart-c459a084-59a5-404d-94ea-335c427010aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096434282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.2096434282
Directory /workspace/16.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.3313210054
Short name T1269
Test name
Test status
Simulation time 55071101 ps
CPU time 0.77 seconds
Started Jun 06 12:53:53 PM PDT 24
Finished Jun 06 12:53:55 PM PDT 24
Peak memory 197684 kb
Host smart-25902bde-7267-4a6a-ae6b-7ab04525740d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313210054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_cs
r_outstanding.3313210054
Directory /workspace/16.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_errors.1020350221
Short name T1191
Test name
Test status
Simulation time 20626297 ps
CPU time 0.99 seconds
Started Jun 06 12:53:40 PM PDT 24
Finished Jun 06 12:53:42 PM PDT 24
Peak memory 200508 kb
Host smart-18ad4286-01d2-4bf6-9d84-5d7eddc94270
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020350221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.1020350221
Directory /workspace/16.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.2682323772
Short name T106
Test name
Test status
Simulation time 353478568 ps
CPU time 1.31 seconds
Started Jun 06 12:53:52 PM PDT 24
Finished Jun 06 12:53:55 PM PDT 24
Peak memory 199988 kb
Host smart-db78d7aa-03a3-4425-9eb7-f8dae7b3b4a5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682323772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.2682323772
Directory /workspace/16.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.906406585
Short name T1268
Test name
Test status
Simulation time 22221581 ps
CPU time 0.71 seconds
Started Jun 06 12:53:53 PM PDT 24
Finished Jun 06 12:53:55 PM PDT 24
Peak memory 199072 kb
Host smart-8fd32b35-3555-40a9-a105-327a3843da82
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906406585 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.906406585
Directory /workspace/17.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_rw.3636161609
Short name T70
Test name
Test status
Simulation time 17928043 ps
CPU time 0.62 seconds
Started Jun 06 12:53:57 PM PDT 24
Finished Jun 06 12:53:58 PM PDT 24
Peak memory 196292 kb
Host smart-a72a289e-4090-46c8-8211-c5183a1d90c4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636161609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.3636161609
Directory /workspace/17.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.uart_intr_test.1946954213
Short name T1265
Test name
Test status
Simulation time 26468420 ps
CPU time 0.59 seconds
Started Jun 06 12:53:50 PM PDT 24
Finished Jun 06 12:53:52 PM PDT 24
Peak memory 194996 kb
Host smart-a61dd30f-9e67-4f1d-915d-62453c89cd3a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946954213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.1946954213
Directory /workspace/17.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.523235888
Short name T1213
Test name
Test status
Simulation time 29196227 ps
CPU time 0.74 seconds
Started Jun 06 12:53:51 PM PDT 24
Finished Jun 06 12:53:53 PM PDT 24
Peak memory 197620 kb
Host smart-11d08fdc-2213-4f79-935b-d191912020a6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523235888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_csr
_outstanding.523235888
Directory /workspace/17.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_errors.3028195457
Short name T1195
Test name
Test status
Simulation time 85316221 ps
CPU time 1.83 seconds
Started Jun 06 12:53:53 PM PDT 24
Finished Jun 06 12:53:56 PM PDT 24
Peak memory 200692 kb
Host smart-cd8e6796-013c-4b61-b7ee-1105f0573b3d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028195457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.3028195457
Directory /workspace/17.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.3531504881
Short name T100
Test name
Test status
Simulation time 82333607 ps
CPU time 1.27 seconds
Started Jun 06 12:53:54 PM PDT 24
Finished Jun 06 12:53:56 PM PDT 24
Peak memory 200048 kb
Host smart-9c504eae-9bcd-45ea-b001-8c5dd28ca264
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531504881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.3531504881
Directory /workspace/17.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.445323945
Short name T1263
Test name
Test status
Simulation time 53479440 ps
CPU time 0.66 seconds
Started Jun 06 12:53:51 PM PDT 24
Finished Jun 06 12:53:53 PM PDT 24
Peak memory 198328 kb
Host smart-dc026672-7548-4761-aadd-68d4a30fe75e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445323945 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.445323945
Directory /workspace/18.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_rw.3748019212
Short name T71
Test name
Test status
Simulation time 30666799 ps
CPU time 0.56 seconds
Started Jun 06 12:53:52 PM PDT 24
Finished Jun 06 12:53:54 PM PDT 24
Peak memory 196096 kb
Host smart-7a16ee21-965a-4660-bf27-1db48effacf3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748019212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.3748019212
Directory /workspace/18.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.uart_intr_test.2482776745
Short name T1281
Test name
Test status
Simulation time 66599413 ps
CPU time 0.56 seconds
Started Jun 06 12:53:59 PM PDT 24
Finished Jun 06 12:54:01 PM PDT 24
Peak memory 195040 kb
Host smart-dd30805c-764d-4dc4-ba97-09da26dbad33
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482776745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.2482776745
Directory /workspace/18.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.2692024453
Short name T1270
Test name
Test status
Simulation time 223684529 ps
CPU time 0.77 seconds
Started Jun 06 12:53:51 PM PDT 24
Finished Jun 06 12:53:53 PM PDT 24
Peak memory 197696 kb
Host smart-40b1d50c-6117-4bf5-8382-c9b166b01ca1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692024453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_cs
r_outstanding.2692024453
Directory /workspace/18.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_errors.3060267106
Short name T1220
Test name
Test status
Simulation time 931747859 ps
CPU time 1.96 seconds
Started Jun 06 12:53:51 PM PDT 24
Finished Jun 06 12:53:54 PM PDT 24
Peak memory 200684 kb
Host smart-4845bdda-918c-450f-9ae8-da867421b1d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060267106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.3060267106
Directory /workspace/18.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.3870845524
Short name T134
Test name
Test status
Simulation time 43111439 ps
CPU time 0.92 seconds
Started Jun 06 12:53:52 PM PDT 24
Finished Jun 06 12:53:54 PM PDT 24
Peak memory 199332 kb
Host smart-a157553d-c339-43bf-a5c5-90d4308dbf6e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870845524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.3870845524
Directory /workspace/18.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.1582480956
Short name T1271
Test name
Test status
Simulation time 157990466 ps
CPU time 0.8 seconds
Started Jun 06 12:53:54 PM PDT 24
Finished Jun 06 12:53:56 PM PDT 24
Peak memory 199544 kb
Host smart-7bcb9454-b055-440f-8ef8-29eb96e5691d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582480956 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.1582480956
Directory /workspace/19.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_rw.2016744986
Short name T75
Test name
Test status
Simulation time 11786383 ps
CPU time 0.61 seconds
Started Jun 06 12:53:51 PM PDT 24
Finished Jun 06 12:53:53 PM PDT 24
Peak memory 196000 kb
Host smart-de7f82cc-cf71-48ac-8900-66a96a708052
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016744986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.2016744986
Directory /workspace/19.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.uart_intr_test.2820104334
Short name T1252
Test name
Test status
Simulation time 15313067 ps
CPU time 0.58 seconds
Started Jun 06 12:53:50 PM PDT 24
Finished Jun 06 12:53:51 PM PDT 24
Peak memory 195048 kb
Host smart-2a7f11a2-f824-4da1-8ed1-bfe1c65e8f49
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820104334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.2820104334
Directory /workspace/19.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.887646680
Short name T92
Test name
Test status
Simulation time 31978859 ps
CPU time 0.74 seconds
Started Jun 06 12:53:51 PM PDT 24
Finished Jun 06 12:53:53 PM PDT 24
Peak memory 197660 kb
Host smart-4ec6f19c-b2d8-40d4-871a-2eaca00f124c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887646680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_csr
_outstanding.887646680
Directory /workspace/19.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_errors.76137329
Short name T1190
Test name
Test status
Simulation time 75243454 ps
CPU time 1.6 seconds
Started Jun 06 12:53:51 PM PDT 24
Finished Jun 06 12:53:54 PM PDT 24
Peak memory 200648 kb
Host smart-79283d6f-5c42-4360-8150-0209925f6071
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76137329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.76137329
Directory /workspace/19.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.533493716
Short name T1311
Test name
Test status
Simulation time 52297117 ps
CPU time 0.94 seconds
Started Jun 06 12:53:53 PM PDT 24
Finished Jun 06 12:53:56 PM PDT 24
Peak memory 199908 kb
Host smart-ea8b9ab6-3438-4e1b-a881-008454611f47
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533493716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.533493716
Directory /workspace/19.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.1168634803
Short name T1253
Test name
Test status
Simulation time 21523505 ps
CPU time 0.76 seconds
Started Jun 06 12:53:12 PM PDT 24
Finished Jun 06 12:53:17 PM PDT 24
Peak memory 196980 kb
Host smart-32bd8984-fc83-428b-b290-8139d6524a0b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168634803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.1168634803
Directory /workspace/2.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.3526350158
Short name T1244
Test name
Test status
Simulation time 554314384 ps
CPU time 1.58 seconds
Started Jun 06 12:53:12 PM PDT 24
Finished Jun 06 12:53:18 PM PDT 24
Peak memory 198636 kb
Host smart-a5215fb6-9253-40f9-b222-3238fd48c029
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526350158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.3526350158
Directory /workspace/2.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.543962151
Short name T74
Test name
Test status
Simulation time 15856087 ps
CPU time 0.61 seconds
Started Jun 06 12:53:04 PM PDT 24
Finished Jun 06 12:53:05 PM PDT 24
Peak memory 196068 kb
Host smart-10f0dc62-ed70-427d-81c7-9a91ebe14178
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543962151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.543962151
Directory /workspace/2.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.2279263246
Short name T1197
Test name
Test status
Simulation time 14972797 ps
CPU time 0.7 seconds
Started Jun 06 12:53:12 PM PDT 24
Finished Jun 06 12:53:17 PM PDT 24
Peak memory 199168 kb
Host smart-8c191741-051b-4459-96d4-76ac7a9ef124
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279263246 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.2279263246
Directory /workspace/2.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_rw.91790264
Short name T1307
Test name
Test status
Simulation time 50479075 ps
CPU time 0.6 seconds
Started Jun 06 12:53:12 PM PDT 24
Finished Jun 06 12:53:17 PM PDT 24
Peak memory 196036 kb
Host smart-1f60fa98-1105-4786-86da-6dd0089a5fe6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91790264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.91790264
Directory /workspace/2.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.uart_intr_test.2716988647
Short name T1221
Test name
Test status
Simulation time 125340208 ps
CPU time 0.57 seconds
Started Jun 06 12:53:10 PM PDT 24
Finished Jun 06 12:53:13 PM PDT 24
Peak memory 195108 kb
Host smart-1503df2e-7ecd-4c48-aaa0-7fc5c6b4e31a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716988647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.2716988647
Directory /workspace/2.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.1202404016
Short name T91
Test name
Test status
Simulation time 62131625 ps
CPU time 0.76 seconds
Started Jun 06 12:53:14 PM PDT 24
Finished Jun 06 12:53:18 PM PDT 24
Peak memory 197628 kb
Host smart-9ccae629-1a14-4deb-9667-f751f2cda7f3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202404016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr
_outstanding.1202404016
Directory /workspace/2.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_errors.3958916751
Short name T1275
Test name
Test status
Simulation time 96696325 ps
CPU time 1.47 seconds
Started Jun 06 12:53:10 PM PDT 24
Finished Jun 06 12:53:14 PM PDT 24
Peak memory 200752 kb
Host smart-5c57089c-9ff9-4841-ad92-321d2b7fcb8b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958916751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.3958916751
Directory /workspace/2.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.1904268778
Short name T1302
Test name
Test status
Simulation time 130773499 ps
CPU time 1.01 seconds
Started Jun 06 12:53:04 PM PDT 24
Finished Jun 06 12:53:06 PM PDT 24
Peak memory 199712 kb
Host smart-11976f73-da12-4d0b-bd37-3c21a9ef0811
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904268778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.1904268778
Directory /workspace/2.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.uart_intr_test.283236624
Short name T1242
Test name
Test status
Simulation time 24475813 ps
CPU time 0.56 seconds
Started Jun 06 12:53:50 PM PDT 24
Finished Jun 06 12:53:52 PM PDT 24
Peak memory 195008 kb
Host smart-58ec300a-7326-48f3-a522-c0d0342fc510
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283236624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.283236624
Directory /workspace/20.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.uart_intr_test.1882053559
Short name T1216
Test name
Test status
Simulation time 104760583 ps
CPU time 0.54 seconds
Started Jun 06 12:53:52 PM PDT 24
Finished Jun 06 12:53:54 PM PDT 24
Peak memory 195024 kb
Host smart-067acc79-9fd7-459a-ab85-b048180689e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882053559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.1882053559
Directory /workspace/21.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.uart_intr_test.1836249628
Short name T1283
Test name
Test status
Simulation time 12859944 ps
CPU time 0.6 seconds
Started Jun 06 12:53:51 PM PDT 24
Finished Jun 06 12:53:53 PM PDT 24
Peak memory 195048 kb
Host smart-6d273a16-92cc-476b-869f-04102e7ee70f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836249628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.1836249628
Directory /workspace/22.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.uart_intr_test.2716374108
Short name T1274
Test name
Test status
Simulation time 14821080 ps
CPU time 0.66 seconds
Started Jun 06 12:53:53 PM PDT 24
Finished Jun 06 12:53:55 PM PDT 24
Peak memory 195084 kb
Host smart-6dea268a-e99d-4796-beea-7de5451ed0aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716374108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.2716374108
Directory /workspace/23.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.uart_intr_test.3771091102
Short name T1260
Test name
Test status
Simulation time 48098731 ps
CPU time 0.59 seconds
Started Jun 06 12:53:52 PM PDT 24
Finished Jun 06 12:53:54 PM PDT 24
Peak memory 195096 kb
Host smart-b9a35b23-fcea-4d05-a253-620891b95b7c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771091102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.3771091102
Directory /workspace/24.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.uart_intr_test.81652023
Short name T1301
Test name
Test status
Simulation time 18847710 ps
CPU time 0.53 seconds
Started Jun 06 12:53:50 PM PDT 24
Finished Jun 06 12:53:52 PM PDT 24
Peak memory 195056 kb
Host smart-ae1e5968-8f8f-4dc4-8d0a-192d27c825f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81652023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.81652023
Directory /workspace/25.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.uart_intr_test.4159257723
Short name T1198
Test name
Test status
Simulation time 16953418 ps
CPU time 0.62 seconds
Started Jun 06 12:53:53 PM PDT 24
Finished Jun 06 12:53:55 PM PDT 24
Peak memory 195148 kb
Host smart-a72e2208-fb40-4595-a1b2-4a632acf6839
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159257723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.4159257723
Directory /workspace/26.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.uart_intr_test.3672379493
Short name T1259
Test name
Test status
Simulation time 13924118 ps
CPU time 0.58 seconds
Started Jun 06 12:53:52 PM PDT 24
Finished Jun 06 12:53:54 PM PDT 24
Peak memory 195116 kb
Host smart-595612f1-69ba-4a55-9f52-87565a69fff9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672379493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.3672379493
Directory /workspace/27.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.uart_intr_test.3040131924
Short name T1284
Test name
Test status
Simulation time 40151538 ps
CPU time 0.58 seconds
Started Jun 06 12:53:52 PM PDT 24
Finished Jun 06 12:53:54 PM PDT 24
Peak memory 195048 kb
Host smart-bb958f2f-1bcb-4576-8f8b-341c3fb19b25
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040131924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.3040131924
Directory /workspace/28.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.uart_intr_test.2569884458
Short name T1273
Test name
Test status
Simulation time 13195209 ps
CPU time 0.59 seconds
Started Jun 06 12:53:50 PM PDT 24
Finished Jun 06 12:53:52 PM PDT 24
Peak memory 195068 kb
Host smart-5f5bcf0f-0e8a-4d33-8c82-63a03a1a67b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569884458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.2569884458
Directory /workspace/29.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.2580115422
Short name T87
Test name
Test status
Simulation time 16886361 ps
CPU time 0.76 seconds
Started Jun 06 12:53:13 PM PDT 24
Finished Jun 06 12:53:18 PM PDT 24
Peak memory 196896 kb
Host smart-a828db98-897e-43f9-8686-eab366a1616b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580115422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.2580115422
Directory /workspace/3.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.1404620174
Short name T1282
Test name
Test status
Simulation time 1277944874 ps
CPU time 2.34 seconds
Started Jun 06 12:53:12 PM PDT 24
Finished Jun 06 12:53:18 PM PDT 24
Peak memory 197892 kb
Host smart-d2d23427-09e8-4f6f-b42a-f74756ef3601
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404620174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.1404620174
Directory /workspace/3.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.2473889340
Short name T1289
Test name
Test status
Simulation time 16281660 ps
CPU time 0.57 seconds
Started Jun 06 12:53:10 PM PDT 24
Finished Jun 06 12:53:15 PM PDT 24
Peak memory 196056 kb
Host smart-985ca83a-39ce-426b-9878-4a4cb074ee1e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473889340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.2473889340
Directory /workspace/3.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.4216392270
Short name T1315
Test name
Test status
Simulation time 22034169 ps
CPU time 0.71 seconds
Started Jun 06 12:53:12 PM PDT 24
Finished Jun 06 12:53:16 PM PDT 24
Peak memory 198648 kb
Host smart-e5dcc323-b83b-42c2-88a0-5cba4c65c550
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216392270 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.4216392270
Directory /workspace/3.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_rw.335133741
Short name T1279
Test name
Test status
Simulation time 23061215 ps
CPU time 0.59 seconds
Started Jun 06 12:53:11 PM PDT 24
Finished Jun 06 12:53:15 PM PDT 24
Peak memory 196048 kb
Host smart-061afa67-e8ac-47af-b9ef-5633eca1958b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335133741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.335133741
Directory /workspace/3.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.uart_intr_test.956722244
Short name T1251
Test name
Test status
Simulation time 17935015 ps
CPU time 0.55 seconds
Started Jun 06 12:53:12 PM PDT 24
Finished Jun 06 12:53:17 PM PDT 24
Peak memory 195092 kb
Host smart-1349ea05-7b66-4da4-9f2b-34b7e1314481
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956722244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.956722244
Directory /workspace/3.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.3765430213
Short name T1294
Test name
Test status
Simulation time 24200482 ps
CPU time 0.72 seconds
Started Jun 06 12:53:12 PM PDT 24
Finished Jun 06 12:53:17 PM PDT 24
Peak memory 197468 kb
Host smart-3742effc-8202-4259-a176-343820b85ef4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765430213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr
_outstanding.3765430213
Directory /workspace/3.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_errors.423263904
Short name T1227
Test name
Test status
Simulation time 167429643 ps
CPU time 2.25 seconds
Started Jun 06 12:53:11 PM PDT 24
Finished Jun 06 12:53:17 PM PDT 24
Peak memory 200752 kb
Host smart-4d78f36f-7836-4c5e-9efe-8a94aa5f96b9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423263904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.423263904
Directory /workspace/3.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.413267978
Short name T1319
Test name
Test status
Simulation time 476868009 ps
CPU time 1.31 seconds
Started Jun 06 12:53:12 PM PDT 24
Finished Jun 06 12:53:18 PM PDT 24
Peak memory 200016 kb
Host smart-7f5c62dc-8eae-4f06-8dba-cc0594512788
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413267978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.413267978
Directory /workspace/3.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.uart_intr_test.2783326115
Short name T1232
Test name
Test status
Simulation time 49931712 ps
CPU time 0.55 seconds
Started Jun 06 12:53:50 PM PDT 24
Finished Jun 06 12:53:51 PM PDT 24
Peak memory 195120 kb
Host smart-cc3b9216-b108-404d-8da0-ebb804cfc790
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783326115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.2783326115
Directory /workspace/30.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.uart_intr_test.11109083
Short name T1200
Test name
Test status
Simulation time 22286485 ps
CPU time 0.56 seconds
Started Jun 06 12:53:52 PM PDT 24
Finished Jun 06 12:53:54 PM PDT 24
Peak memory 195112 kb
Host smart-8f3e7424-141c-4d20-ab9b-d4b9f072fd20
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11109083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.11109083
Directory /workspace/31.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.uart_intr_test.614923166
Short name T1192
Test name
Test status
Simulation time 42116619 ps
CPU time 0.58 seconds
Started Jun 06 12:53:53 PM PDT 24
Finished Jun 06 12:53:54 PM PDT 24
Peak memory 195108 kb
Host smart-89cbe24b-526c-49e4-bffa-8f1ab37a5c87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614923166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.614923166
Directory /workspace/32.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.uart_intr_test.3584961495
Short name T1298
Test name
Test status
Simulation time 94051272 ps
CPU time 0.55 seconds
Started Jun 06 12:53:50 PM PDT 24
Finished Jun 06 12:53:52 PM PDT 24
Peak memory 195028 kb
Host smart-8aa2e97d-eb20-400a-9eba-da3f33b9e64d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584961495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.3584961495
Directory /workspace/33.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.uart_intr_test.467272294
Short name T1209
Test name
Test status
Simulation time 16492546 ps
CPU time 0.55 seconds
Started Jun 06 12:53:50 PM PDT 24
Finished Jun 06 12:53:52 PM PDT 24
Peak memory 195056 kb
Host smart-85dd5803-beb8-46bc-a7bc-c898414ff06f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467272294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.467272294
Directory /workspace/34.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.uart_intr_test.3189990878
Short name T1293
Test name
Test status
Simulation time 11952927 ps
CPU time 0.55 seconds
Started Jun 06 12:53:52 PM PDT 24
Finished Jun 06 12:53:54 PM PDT 24
Peak memory 195048 kb
Host smart-8edeaf97-c62b-410a-b56d-de5b7bd21414
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189990878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.3189990878
Directory /workspace/35.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.uart_intr_test.2940442746
Short name T1202
Test name
Test status
Simulation time 47785890 ps
CPU time 0.59 seconds
Started Jun 06 12:53:52 PM PDT 24
Finished Jun 06 12:53:54 PM PDT 24
Peak memory 195048 kb
Host smart-eb808228-ef2d-428e-ac70-e14577a1e040
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940442746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.2940442746
Directory /workspace/36.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.uart_intr_test.2758107213
Short name T1204
Test name
Test status
Simulation time 12844722 ps
CPU time 0.59 seconds
Started Jun 06 12:53:50 PM PDT 24
Finished Jun 06 12:53:52 PM PDT 24
Peak memory 195032 kb
Host smart-5297b50b-387d-42d9-9a1a-488c0ea1683c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758107213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.2758107213
Directory /workspace/37.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.uart_intr_test.1482723589
Short name T1309
Test name
Test status
Simulation time 12559624 ps
CPU time 0.57 seconds
Started Jun 06 12:54:02 PM PDT 24
Finished Jun 06 12:54:04 PM PDT 24
Peak memory 195052 kb
Host smart-5709ee25-d54e-40ca-8ba9-e7764b341b5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482723589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.1482723589
Directory /workspace/38.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.uart_intr_test.84800890
Short name T1267
Test name
Test status
Simulation time 48011531 ps
CPU time 0.57 seconds
Started Jun 06 12:54:01 PM PDT 24
Finished Jun 06 12:54:03 PM PDT 24
Peak memory 195048 kb
Host smart-9d605ed2-514d-4126-bd79-1f1d9c0fc2e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84800890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.84800890
Directory /workspace/39.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.593641555
Short name T1218
Test name
Test status
Simulation time 78641978 ps
CPU time 0.79 seconds
Started Jun 06 12:53:11 PM PDT 24
Finished Jun 06 12:53:15 PM PDT 24
Peak memory 196948 kb
Host smart-15f07e67-0b14-425c-9b15-4030c4b82657
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593641555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.593641555
Directory /workspace/4.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.183030069
Short name T73
Test name
Test status
Simulation time 113657196 ps
CPU time 2.16 seconds
Started Jun 06 12:53:14 PM PDT 24
Finished Jun 06 12:53:20 PM PDT 24
Peak memory 197908 kb
Host smart-de2b97b3-a6f3-4b33-ba8d-c586d950d339
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183030069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.183030069
Directory /workspace/4.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.1572925115
Short name T1305
Test name
Test status
Simulation time 14268195 ps
CPU time 0.58 seconds
Started Jun 06 12:53:12 PM PDT 24
Finished Jun 06 12:53:17 PM PDT 24
Peak memory 195920 kb
Host smart-2b744e42-1c68-474d-9157-0b38f9015a70
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572925115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.1572925115
Directory /workspace/4.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.4061194656
Short name T1199
Test name
Test status
Simulation time 29635089 ps
CPU time 1.41 seconds
Started Jun 06 12:53:13 PM PDT 24
Finished Jun 06 12:53:18 PM PDT 24
Peak memory 200700 kb
Host smart-a1ef1a27-af4d-4f6b-850d-50eddf7bf9f3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061194656 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.4061194656
Directory /workspace/4.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_rw.577685684
Short name T1219
Test name
Test status
Simulation time 38936061 ps
CPU time 0.59 seconds
Started Jun 06 12:53:13 PM PDT 24
Finished Jun 06 12:53:17 PM PDT 24
Peak memory 196032 kb
Host smart-a46f304a-63bc-4643-9e66-190c62792e13
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577685684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.577685684
Directory /workspace/4.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.uart_intr_test.1626479605
Short name T1241
Test name
Test status
Simulation time 49604723 ps
CPU time 0.59 seconds
Started Jun 06 12:53:13 PM PDT 24
Finished Jun 06 12:53:17 PM PDT 24
Peak memory 195104 kb
Host smart-3c3134bb-8fca-4c4f-b138-4285fbcd2dfb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626479605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.1626479605
Directory /workspace/4.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.829034389
Short name T96
Test name
Test status
Simulation time 14626046 ps
CPU time 0.67 seconds
Started Jun 06 12:53:11 PM PDT 24
Finished Jun 06 12:53:15 PM PDT 24
Peak memory 195420 kb
Host smart-8245307d-979d-4b79-9b0d-a20c1097490e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829034389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr_
outstanding.829034389
Directory /workspace/4.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_errors.224000328
Short name T1261
Test name
Test status
Simulation time 29915816 ps
CPU time 1.38 seconds
Started Jun 06 12:53:14 PM PDT 24
Finished Jun 06 12:53:19 PM PDT 24
Peak memory 200764 kb
Host smart-3afb147b-be15-4dec-91ad-fbe14112d74f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224000328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.224000328
Directory /workspace/4.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.918303722
Short name T104
Test name
Test status
Simulation time 330242438 ps
CPU time 1.34 seconds
Started Jun 06 12:53:13 PM PDT 24
Finished Jun 06 12:53:18 PM PDT 24
Peak memory 199892 kb
Host smart-77cda32e-c54c-426f-b16f-946025827da0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918303722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.918303722
Directory /workspace/4.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.uart_intr_test.2862167602
Short name T1295
Test name
Test status
Simulation time 48034631 ps
CPU time 0.56 seconds
Started Jun 06 12:54:01 PM PDT 24
Finished Jun 06 12:54:03 PM PDT 24
Peak memory 195136 kb
Host smart-5b37d150-af8f-4e91-b2b7-c1d26f98a197
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862167602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.2862167602
Directory /workspace/40.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.uart_intr_test.2024045537
Short name T1317
Test name
Test status
Simulation time 13633094 ps
CPU time 0.57 seconds
Started Jun 06 12:53:59 PM PDT 24
Finished Jun 06 12:54:00 PM PDT 24
Peak memory 195040 kb
Host smart-db283df7-56b0-4187-b33d-19591bf9d257
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024045537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.2024045537
Directory /workspace/41.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.uart_intr_test.2239260044
Short name T1316
Test name
Test status
Simulation time 16614676 ps
CPU time 0.59 seconds
Started Jun 06 12:53:59 PM PDT 24
Finished Jun 06 12:54:01 PM PDT 24
Peak memory 195080 kb
Host smart-320fbf9f-0aec-4922-9280-4d68be728daf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239260044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.2239260044
Directory /workspace/42.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.uart_intr_test.4107227420
Short name T1300
Test name
Test status
Simulation time 39783202 ps
CPU time 0.59 seconds
Started Jun 06 12:54:00 PM PDT 24
Finished Jun 06 12:54:02 PM PDT 24
Peak memory 195072 kb
Host smart-a22d5eb6-cb17-4336-99a8-eefdbe871151
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107227420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.4107227420
Directory /workspace/43.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.uart_intr_test.3665674761
Short name T1196
Test name
Test status
Simulation time 67011193 ps
CPU time 0.59 seconds
Started Jun 06 12:54:00 PM PDT 24
Finished Jun 06 12:54:01 PM PDT 24
Peak memory 195100 kb
Host smart-3ecfaaf6-65a3-4788-9644-ede982b1bb96
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665674761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.3665674761
Directory /workspace/44.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.uart_intr_test.3646732404
Short name T1299
Test name
Test status
Simulation time 12702657 ps
CPU time 0.58 seconds
Started Jun 06 12:53:59 PM PDT 24
Finished Jun 06 12:54:01 PM PDT 24
Peak memory 195112 kb
Host smart-f0f43e98-a674-4250-a11d-bdf7734a7484
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646732404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.3646732404
Directory /workspace/45.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.uart_intr_test.2453099183
Short name T1226
Test name
Test status
Simulation time 46174203 ps
CPU time 0.61 seconds
Started Jun 06 12:54:02 PM PDT 24
Finished Jun 06 12:54:03 PM PDT 24
Peak memory 194928 kb
Host smart-3787b4c5-9874-4af1-9f93-0d13c31d66bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453099183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.2453099183
Directory /workspace/46.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.uart_intr_test.1810141670
Short name T1194
Test name
Test status
Simulation time 25232695 ps
CPU time 0.57 seconds
Started Jun 06 12:54:02 PM PDT 24
Finished Jun 06 12:54:04 PM PDT 24
Peak memory 195012 kb
Host smart-63edeb06-4500-411a-8e6f-c5fc50b1bc71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810141670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.1810141670
Directory /workspace/47.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.uart_intr_test.3793567224
Short name T1223
Test name
Test status
Simulation time 15113990 ps
CPU time 0.58 seconds
Started Jun 06 12:54:01 PM PDT 24
Finished Jun 06 12:54:03 PM PDT 24
Peak memory 195080 kb
Host smart-c201d088-b8b5-4ef3-a4d3-1473c4d96bee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793567224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.3793567224
Directory /workspace/48.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.uart_intr_test.2520567303
Short name T1243
Test name
Test status
Simulation time 45818648 ps
CPU time 0.6 seconds
Started Jun 06 12:53:59 PM PDT 24
Finished Jun 06 12:54:01 PM PDT 24
Peak memory 195016 kb
Host smart-a102eb10-dca1-4f39-9414-80b3f852bef5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520567303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.2520567303
Directory /workspace/49.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.2064821679
Short name T1235
Test name
Test status
Simulation time 59029581 ps
CPU time 0.76 seconds
Started Jun 06 12:53:21 PM PDT 24
Finished Jun 06 12:53:23 PM PDT 24
Peak memory 200124 kb
Host smart-31e8c0a6-a27b-4a5f-88f2-e42decf48fba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064821679 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.2064821679
Directory /workspace/5.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_rw.362478289
Short name T1238
Test name
Test status
Simulation time 82407614 ps
CPU time 0.6 seconds
Started Jun 06 12:53:30 PM PDT 24
Finished Jun 06 12:53:32 PM PDT 24
Peak memory 196128 kb
Host smart-7acbd0f2-958e-4dbb-8dcc-74b143d2527e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362478289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.362478289
Directory /workspace/5.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.uart_intr_test.1482259656
Short name T1215
Test name
Test status
Simulation time 198097300 ps
CPU time 0.57 seconds
Started Jun 06 12:53:19 PM PDT 24
Finished Jun 06 12:53:21 PM PDT 24
Peak memory 195124 kb
Host smart-5f159dc8-94ae-45a5-a3a6-9ef60cd208a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482259656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.1482259656
Directory /workspace/5.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.1780536622
Short name T90
Test name
Test status
Simulation time 38112504 ps
CPU time 0.61 seconds
Started Jun 06 12:53:20 PM PDT 24
Finished Jun 06 12:53:22 PM PDT 24
Peak memory 196212 kb
Host smart-5af0ebc5-10cb-491d-8574-3e8be757fe88
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780536622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr
_outstanding.1780536622
Directory /workspace/5.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_errors.3307603474
Short name T1320
Test name
Test status
Simulation time 61582525 ps
CPU time 1.76 seconds
Started Jun 06 12:53:23 PM PDT 24
Finished Jun 06 12:53:26 PM PDT 24
Peak memory 200744 kb
Host smart-dbd69752-f1cc-493a-ae77-31c91af40d42
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307603474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.3307603474
Directory /workspace/5.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.1202284272
Short name T136
Test name
Test status
Simulation time 44282852 ps
CPU time 0.87 seconds
Started Jun 06 12:53:20 PM PDT 24
Finished Jun 06 12:53:22 PM PDT 24
Peak memory 199724 kb
Host smart-f0ec4c8e-e8c0-4fdf-a94d-caee81f73a2f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202284272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.1202284272
Directory /workspace/5.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.925913932
Short name T1272
Test name
Test status
Simulation time 41672196 ps
CPU time 0.75 seconds
Started Jun 06 12:53:20 PM PDT 24
Finished Jun 06 12:53:22 PM PDT 24
Peak memory 199556 kb
Host smart-f4271747-8d24-47d4-8786-b27eb24f044f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925913932 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.925913932
Directory /workspace/6.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_rw.885241207
Short name T89
Test name
Test status
Simulation time 41284888 ps
CPU time 0.61 seconds
Started Jun 06 12:53:21 PM PDT 24
Finished Jun 06 12:53:23 PM PDT 24
Peak memory 196272 kb
Host smart-5ce12f81-5205-41ec-8db6-06ac56dc7457
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885241207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.885241207
Directory /workspace/6.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.uart_intr_test.723175261
Short name T1236
Test name
Test status
Simulation time 13145939 ps
CPU time 0.61 seconds
Started Jun 06 12:53:22 PM PDT 24
Finished Jun 06 12:53:24 PM PDT 24
Peak memory 195016 kb
Host smart-96b4d31a-d45f-4a27-bc88-261ae510edf1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723175261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.723175261
Directory /workspace/6.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.2708082804
Short name T1257
Test name
Test status
Simulation time 75805868 ps
CPU time 0.63 seconds
Started Jun 06 12:53:20 PM PDT 24
Finished Jun 06 12:53:22 PM PDT 24
Peak memory 196232 kb
Host smart-87beecbc-f3a7-4075-b8ae-928b7997cb9f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708082804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr
_outstanding.2708082804
Directory /workspace/6.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_errors.2613211952
Short name T1286
Test name
Test status
Simulation time 631972287 ps
CPU time 1.87 seconds
Started Jun 06 12:53:19 PM PDT 24
Finished Jun 06 12:53:22 PM PDT 24
Peak memory 200752 kb
Host smart-bef5c3be-a763-47ad-b985-0900525158f2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613211952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.2613211952
Directory /workspace/6.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.1307338090
Short name T105
Test name
Test status
Simulation time 48751151 ps
CPU time 0.97 seconds
Started Jun 06 12:53:23 PM PDT 24
Finished Jun 06 12:53:25 PM PDT 24
Peak memory 199568 kb
Host smart-345ba491-b06a-49ce-89da-5a177eb22c01
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307338090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.1307338090
Directory /workspace/6.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.3128444628
Short name T1266
Test name
Test status
Simulation time 142361680 ps
CPU time 0.95 seconds
Started Jun 06 12:53:24 PM PDT 24
Finished Jun 06 12:53:26 PM PDT 24
Peak memory 200516 kb
Host smart-9e380e39-abfa-4fc7-b7ec-3d59982a2931
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128444628 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.3128444628
Directory /workspace/7.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_rw.3711759463
Short name T1313
Test name
Test status
Simulation time 18005882 ps
CPU time 0.6 seconds
Started Jun 06 12:53:27 PM PDT 24
Finished Jun 06 12:53:29 PM PDT 24
Peak memory 196060 kb
Host smart-b0d18b07-282e-48e4-a8e4-3095db113511
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711759463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.3711759463
Directory /workspace/7.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.uart_intr_test.17250197
Short name T1208
Test name
Test status
Simulation time 19845341 ps
CPU time 0.55 seconds
Started Jun 06 12:53:22 PM PDT 24
Finished Jun 06 12:53:23 PM PDT 24
Peak memory 195016 kb
Host smart-137d734b-2c03-4d2a-98cc-33b213ca9644
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17250197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.17250197
Directory /workspace/7.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.3117156705
Short name T97
Test name
Test status
Simulation time 51405775 ps
CPU time 0.71 seconds
Started Jun 06 12:53:23 PM PDT 24
Finished Jun 06 12:53:24 PM PDT 24
Peak memory 197572 kb
Host smart-45847eca-15a0-49df-927e-a7c31ed18d30
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117156705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr
_outstanding.3117156705
Directory /workspace/7.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_errors.2180019576
Short name T1245
Test name
Test status
Simulation time 110977281 ps
CPU time 2.4 seconds
Started Jun 06 12:53:21 PM PDT 24
Finished Jun 06 12:53:24 PM PDT 24
Peak memory 200640 kb
Host smart-91affc02-3a8f-4b4c-b42d-dba580842283
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180019576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.2180019576
Directory /workspace/7.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.2363685460
Short name T101
Test name
Test status
Simulation time 93770227 ps
CPU time 0.92 seconds
Started Jun 06 12:53:19 PM PDT 24
Finished Jun 06 12:53:21 PM PDT 24
Peak memory 199700 kb
Host smart-ed78fb61-43f5-418c-8dab-f27f273009b3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363685460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.2363685460
Directory /workspace/7.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.1927942519
Short name T1229
Test name
Test status
Simulation time 59638981 ps
CPU time 0.87 seconds
Started Jun 06 12:53:31 PM PDT 24
Finished Jun 06 12:53:33 PM PDT 24
Peak memory 200516 kb
Host smart-f28dbd32-7c37-4908-87b9-e98b0391c813
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927942519 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.1927942519
Directory /workspace/8.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_rw.430272731
Short name T1255
Test name
Test status
Simulation time 19371181 ps
CPU time 0.57 seconds
Started Jun 06 12:53:30 PM PDT 24
Finished Jun 06 12:53:32 PM PDT 24
Peak memory 195996 kb
Host smart-091a40a4-2531-4ccc-8b60-618270aa9dcf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430272731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.430272731
Directory /workspace/8.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.uart_intr_test.649565627
Short name T1262
Test name
Test status
Simulation time 92940256 ps
CPU time 0.57 seconds
Started Jun 06 12:53:20 PM PDT 24
Finished Jun 06 12:53:22 PM PDT 24
Peak memory 195088 kb
Host smart-ea44ba68-1a4a-47d9-a9bc-d8ec53c41f61
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649565627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.649565627
Directory /workspace/8.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.929206827
Short name T1210
Test name
Test status
Simulation time 23949647 ps
CPU time 0.67 seconds
Started Jun 06 12:53:29 PM PDT 24
Finished Jun 06 12:53:31 PM PDT 24
Peak memory 196104 kb
Host smart-a1ebf042-70ec-4039-9eb5-c0979fc97d5e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929206827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr_
outstanding.929206827
Directory /workspace/8.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_errors.3008232218
Short name T1285
Test name
Test status
Simulation time 85345084 ps
CPU time 2.25 seconds
Started Jun 06 12:53:19 PM PDT 24
Finished Jun 06 12:53:22 PM PDT 24
Peak memory 200644 kb
Host smart-8475c927-a7b4-464c-a97a-ac8dcd7dbf17
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008232218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.3008232218
Directory /workspace/8.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.3523473319
Short name T1314
Test name
Test status
Simulation time 33477874 ps
CPU time 0.63 seconds
Started Jun 06 12:53:30 PM PDT 24
Finished Jun 06 12:53:31 PM PDT 24
Peak memory 198160 kb
Host smart-710df0e9-cbce-4a18-8c8c-09dc54a1eba0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523473319 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.3523473319
Directory /workspace/9.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_rw.2220983914
Short name T1240
Test name
Test status
Simulation time 16624630 ps
CPU time 0.58 seconds
Started Jun 06 12:53:31 PM PDT 24
Finished Jun 06 12:53:32 PM PDT 24
Peak memory 196088 kb
Host smart-9b161819-e3f6-4e20-86fd-b038380b1dbb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220983914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.2220983914
Directory /workspace/9.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.uart_intr_test.317931087
Short name T1225
Test name
Test status
Simulation time 30982645 ps
CPU time 0.55 seconds
Started Jun 06 12:53:31 PM PDT 24
Finished Jun 06 12:53:33 PM PDT 24
Peak memory 194992 kb
Host smart-f4460c39-f91c-4e6c-9a26-d9f7074ffa4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317931087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.317931087
Directory /workspace/9.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.1342802893
Short name T1310
Test name
Test status
Simulation time 31249382 ps
CPU time 0.72 seconds
Started Jun 06 12:53:32 PM PDT 24
Finished Jun 06 12:53:34 PM PDT 24
Peak memory 196328 kb
Host smart-9cf34008-f20f-4f4b-9d6e-0d4845b286f5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342802893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr
_outstanding.1342802893
Directory /workspace/9.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_errors.1583697700
Short name T1247
Test name
Test status
Simulation time 211446261 ps
CPU time 1.34 seconds
Started Jun 06 12:53:30 PM PDT 24
Finished Jun 06 12:53:32 PM PDT 24
Peak memory 201032 kb
Host smart-9e0cab23-6732-4c95-bac2-7a86ac01b7d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583697700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.1583697700
Directory /workspace/9.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.2922480386
Short name T1290
Test name
Test status
Simulation time 311168837 ps
CPU time 1.36 seconds
Started Jun 06 12:53:30 PM PDT 24
Finished Jun 06 12:53:32 PM PDT 24
Peak memory 200012 kb
Host smart-7ddd74d9-60dd-4170-9652-549017783bea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922480386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.2922480386
Directory /workspace/9.uart_tl_intg_err/latest

Test location /workspace/coverage/default/0.uart_alert_test.2822635269
Short name T917
Test name
Test status
Simulation time 21045668 ps
CPU time 0.55 seconds
Started Jun 06 12:57:52 PM PDT 24
Finished Jun 06 12:57:54 PM PDT 24
Peak memory 195740 kb
Host smart-ce8605cb-85ef-4920-bc83-fd67ed878916
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822635269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.2822635269
Directory /workspace/0.uart_alert_test/latest

Test location /workspace/coverage/default/0.uart_fifo_overflow.841750453
Short name T1123
Test name
Test status
Simulation time 96505310799 ps
CPU time 71.11 seconds
Started Jun 06 12:57:59 PM PDT 24
Finished Jun 06 12:59:10 PM PDT 24
Peak memory 200196 kb
Host smart-07d74b94-5433-4ae1-a013-d967bbfec5bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841750453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.841750453
Directory /workspace/0.uart_fifo_overflow/latest

Test location /workspace/coverage/default/0.uart_intr.1610941924
Short name T761
Test name
Test status
Simulation time 47523890511 ps
CPU time 36.91 seconds
Started Jun 06 12:57:52 PM PDT 24
Finished Jun 06 12:58:30 PM PDT 24
Peak memory 200092 kb
Host smart-dcebc2e5-63b8-45f5-b624-5cf13931acff
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610941924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.1610941924
Directory /workspace/0.uart_intr/latest

Test location /workspace/coverage/default/0.uart_long_xfer_wo_dly.1982160230
Short name T314
Test name
Test status
Simulation time 130745317974 ps
CPU time 1028.44 seconds
Started Jun 06 12:57:55 PM PDT 24
Finished Jun 06 01:15:04 PM PDT 24
Peak memory 200252 kb
Host smart-88bc0e7c-3554-40de-b0aa-287c50cb2e35
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1982160230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.1982160230
Directory /workspace/0.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/0.uart_loopback.3117162753
Short name T390
Test name
Test status
Simulation time 13776392324 ps
CPU time 11.06 seconds
Started Jun 06 12:57:55 PM PDT 24
Finished Jun 06 12:58:07 PM PDT 24
Peak memory 200272 kb
Host smart-fe44cbe3-fe6b-498e-9d9b-6583894c6581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117162753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_loopback.3117162753
Directory /workspace/0.uart_loopback/latest

Test location /workspace/coverage/default/0.uart_noise_filter.1296943513
Short name T474
Test name
Test status
Simulation time 69437819992 ps
CPU time 70.72 seconds
Started Jun 06 12:57:59 PM PDT 24
Finished Jun 06 12:59:10 PM PDT 24
Peak memory 200552 kb
Host smart-a25d9156-bcce-48af-ac7e-8b67679e92e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296943513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_noise_filter.1296943513
Directory /workspace/0.uart_noise_filter/latest

Test location /workspace/coverage/default/0.uart_perf.1211513860
Short name T272
Test name
Test status
Simulation time 22034592642 ps
CPU time 840.97 seconds
Started Jun 06 12:57:53 PM PDT 24
Finished Jun 06 01:11:55 PM PDT 24
Peak memory 200288 kb
Host smart-a316b8fd-eb40-47af-b2a6-c393fc57c04c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1211513860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.1211513860
Directory /workspace/0.uart_perf/latest

Test location /workspace/coverage/default/0.uart_rx_oversample.3088030900
Short name T382
Test name
Test status
Simulation time 4667843465 ps
CPU time 9.91 seconds
Started Jun 06 12:57:53 PM PDT 24
Finished Jun 06 12:58:05 PM PDT 24
Peak memory 198464 kb
Host smart-fce59a1d-4663-4918-a40d-a91f75ca9e1c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3088030900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.3088030900
Directory /workspace/0.uart_rx_oversample/latest

Test location /workspace/coverage/default/0.uart_rx_start_bit_filter.3565307373
Short name T605
Test name
Test status
Simulation time 47131456507 ps
CPU time 33.89 seconds
Started Jun 06 12:57:52 PM PDT 24
Finished Jun 06 12:58:27 PM PDT 24
Peak memory 196392 kb
Host smart-9fb0728e-d556-4e9b-af9e-55befdcf895a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565307373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.3565307373
Directory /workspace/0.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/0.uart_sec_cm.755646269
Short name T108
Test name
Test status
Simulation time 448307263 ps
CPU time 0.88 seconds
Started Jun 06 12:57:54 PM PDT 24
Finished Jun 06 12:57:56 PM PDT 24
Peak memory 218916 kb
Host smart-5a9318d6-fd4b-4ad3-9302-eb05feaf3b46
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755646269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.755646269
Directory /workspace/0.uart_sec_cm/latest

Test location /workspace/coverage/default/0.uart_smoke.338856978
Short name T355
Test name
Test status
Simulation time 502568283 ps
CPU time 1.67 seconds
Started Jun 06 12:57:55 PM PDT 24
Finished Jun 06 12:57:58 PM PDT 24
Peak memory 199656 kb
Host smart-13fb0dda-070f-47cb-b393-0219374db3b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338856978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_smoke.338856978
Directory /workspace/0.uart_smoke/latest

Test location /workspace/coverage/default/0.uart_stress_all.2330618684
Short name T282
Test name
Test status
Simulation time 172147143591 ps
CPU time 112.52 seconds
Started Jun 06 12:57:53 PM PDT 24
Finished Jun 06 12:59:47 PM PDT 24
Peak memory 200256 kb
Host smart-c0738329-e65b-4c7a-8414-850bde977eed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330618684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.2330618684
Directory /workspace/0.uart_stress_all/latest

Test location /workspace/coverage/default/0.uart_stress_all_with_rand_reset.3569130756
Short name T238
Test name
Test status
Simulation time 328709066225 ps
CPU time 568.13 seconds
Started Jun 06 12:57:55 PM PDT 24
Finished Jun 06 01:07:24 PM PDT 24
Peak memory 216896 kb
Host smart-362bf907-5410-453b-bbc7-db2a117a0f2f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569130756 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.uart_stress_all_with_rand_reset.3569130756
Directory /workspace/0.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.uart_tx_ovrd.1152540192
Short name T43
Test name
Test status
Simulation time 474729108 ps
CPU time 1.55 seconds
Started Jun 06 12:58:03 PM PDT 24
Finished Jun 06 12:58:06 PM PDT 24
Peak memory 198284 kb
Host smart-025dd059-04a4-493f-bc63-c4a753466ba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152540192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.1152540192
Directory /workspace/0.uart_tx_ovrd/latest

Test location /workspace/coverage/default/0.uart_tx_rx.1067046942
Short name T510
Test name
Test status
Simulation time 2593695510 ps
CPU time 5.03 seconds
Started Jun 06 12:57:52 PM PDT 24
Finished Jun 06 12:57:58 PM PDT 24
Peak memory 197624 kb
Host smart-34d4ed6f-3e74-45a6-9fb5-39dea392829a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067046942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.1067046942
Directory /workspace/0.uart_tx_rx/latest

Test location /workspace/coverage/default/1.uart_fifo_full.4196659716
Short name T1164
Test name
Test status
Simulation time 71767221389 ps
CPU time 55.99 seconds
Started Jun 06 12:57:55 PM PDT 24
Finished Jun 06 12:58:51 PM PDT 24
Peak memory 200232 kb
Host smart-d87cadc2-91ed-44c7-8aba-30652c5c2c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196659716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.4196659716
Directory /workspace/1.uart_fifo_full/latest

Test location /workspace/coverage/default/1.uart_fifo_overflow.1952080449
Short name T42
Test name
Test status
Simulation time 173512496955 ps
CPU time 260.45 seconds
Started Jun 06 12:57:57 PM PDT 24
Finished Jun 06 01:02:18 PM PDT 24
Peak memory 200340 kb
Host smart-8871139f-a7f0-4cf4-bff9-7c710249331c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952080449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.1952080449
Directory /workspace/1.uart_fifo_overflow/latest

Test location /workspace/coverage/default/1.uart_fifo_reset.1653136621
Short name T183
Test name
Test status
Simulation time 35937704296 ps
CPU time 51.58 seconds
Started Jun 06 12:57:52 PM PDT 24
Finished Jun 06 12:58:44 PM PDT 24
Peak memory 200340 kb
Host smart-64e26064-0e84-4923-a034-7be22164e2c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653136621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.1653136621
Directory /workspace/1.uart_fifo_reset/latest

Test location /workspace/coverage/default/1.uart_intr.177757445
Short name T875
Test name
Test status
Simulation time 32359324837 ps
CPU time 13.47 seconds
Started Jun 06 12:57:56 PM PDT 24
Finished Jun 06 12:58:11 PM PDT 24
Peak memory 199960 kb
Host smart-15534a1c-7f70-49ff-8723-dfedf49ed0d0
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177757445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.177757445
Directory /workspace/1.uart_intr/latest

Test location /workspace/coverage/default/1.uart_long_xfer_wo_dly.1955770990
Short name T998
Test name
Test status
Simulation time 124269937196 ps
CPU time 857.84 seconds
Started Jun 06 12:57:58 PM PDT 24
Finished Jun 06 01:12:17 PM PDT 24
Peak memory 200312 kb
Host smart-ca843947-b6d6-455d-8fd4-58a96aeef649
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1955770990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.1955770990
Directory /workspace/1.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/1.uart_loopback.1763751414
Short name T635
Test name
Test status
Simulation time 4301210327 ps
CPU time 3.85 seconds
Started Jun 06 12:57:52 PM PDT 24
Finished Jun 06 12:57:57 PM PDT 24
Peak memory 199044 kb
Host smart-c131180b-50f0-4b23-b715-7af954baf9da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763751414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_loopback.1763751414
Directory /workspace/1.uart_loopback/latest

Test location /workspace/coverage/default/1.uart_noise_filter.3714882411
Short name T370
Test name
Test status
Simulation time 33585670570 ps
CPU time 50.35 seconds
Started Jun 06 12:57:55 PM PDT 24
Finished Jun 06 12:58:46 PM PDT 24
Peak memory 200496 kb
Host smart-33a8b656-e2c3-4a6a-8b8d-fd1912a743f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714882411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_noise_filter.3714882411
Directory /workspace/1.uart_noise_filter/latest

Test location /workspace/coverage/default/1.uart_perf.4263945667
Short name T292
Test name
Test status
Simulation time 28768093279 ps
CPU time 264.06 seconds
Started Jun 06 12:57:53 PM PDT 24
Finished Jun 06 01:02:18 PM PDT 24
Peak memory 200224 kb
Host smart-97372970-9b15-4995-a47c-85bc6288e34b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4263945667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.4263945667
Directory /workspace/1.uart_perf/latest

Test location /workspace/coverage/default/1.uart_rx_oversample.3223498602
Short name T849
Test name
Test status
Simulation time 7540177439 ps
CPU time 32.58 seconds
Started Jun 06 12:58:03 PM PDT 24
Finished Jun 06 12:58:36 PM PDT 24
Peak memory 198572 kb
Host smart-ee324073-5001-4f64-b026-727efc897714
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3223498602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.3223498602
Directory /workspace/1.uart_rx_oversample/latest

Test location /workspace/coverage/default/1.uart_rx_parity_err.1675118728
Short name T493
Test name
Test status
Simulation time 21661053887 ps
CPU time 37.5 seconds
Started Jun 06 12:57:59 PM PDT 24
Finished Jun 06 12:58:37 PM PDT 24
Peak memory 200244 kb
Host smart-c6fbaa6b-4fa4-45eb-b78a-9e4e1e7eba23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675118728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.1675118728
Directory /workspace/1.uart_rx_parity_err/latest

Test location /workspace/coverage/default/1.uart_rx_start_bit_filter.1124161592
Short name T426
Test name
Test status
Simulation time 53899134137 ps
CPU time 40.31 seconds
Started Jun 06 12:58:04 PM PDT 24
Finished Jun 06 12:58:46 PM PDT 24
Peak memory 195800 kb
Host smart-a6c180db-6086-41f4-99fb-81a470803c6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124161592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.1124161592
Directory /workspace/1.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/1.uart_sec_cm.1037574864
Short name T107
Test name
Test status
Simulation time 37910484 ps
CPU time 0.79 seconds
Started Jun 06 12:58:01 PM PDT 24
Finished Jun 06 12:58:03 PM PDT 24
Peak memory 218644 kb
Host smart-52f4e8c1-58ad-42d5-a44c-b20ea7f2ddfa
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037574864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.1037574864
Directory /workspace/1.uart_sec_cm/latest

Test location /workspace/coverage/default/1.uart_smoke.3014883952
Short name T732
Test name
Test status
Simulation time 5733330895 ps
CPU time 19.02 seconds
Started Jun 06 12:58:04 PM PDT 24
Finished Jun 06 12:58:24 PM PDT 24
Peak memory 199264 kb
Host smart-20b7016b-210f-4a18-a2cd-574946c612b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014883952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_smoke.3014883952
Directory /workspace/1.uart_smoke/latest

Test location /workspace/coverage/default/1.uart_stress_all_with_rand_reset.2272289796
Short name T304
Test name
Test status
Simulation time 125955046758 ps
CPU time 445.04 seconds
Started Jun 06 12:57:51 PM PDT 24
Finished Jun 06 01:05:17 PM PDT 24
Peak memory 217064 kb
Host smart-15398ced-1e1f-4c64-8e2e-4e05f25aedd3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272289796 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.uart_stress_all_with_rand_reset.2272289796
Directory /workspace/1.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.uart_tx_ovrd.2431041852
Short name T383
Test name
Test status
Simulation time 6658956288 ps
CPU time 17 seconds
Started Jun 06 12:57:57 PM PDT 24
Finished Jun 06 12:58:14 PM PDT 24
Peak memory 199580 kb
Host smart-61f4071a-2342-4e65-a1d7-4a6e71149b07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431041852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.2431041852
Directory /workspace/1.uart_tx_ovrd/latest

Test location /workspace/coverage/default/1.uart_tx_rx.1543032417
Short name T813
Test name
Test status
Simulation time 50823005424 ps
CPU time 45.98 seconds
Started Jun 06 12:57:53 PM PDT 24
Finished Jun 06 12:58:40 PM PDT 24
Peak memory 200384 kb
Host smart-46936dc1-d80b-452b-b3f6-224dbb7a1c33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543032417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.1543032417
Directory /workspace/1.uart_tx_rx/latest

Test location /workspace/coverage/default/10.uart_alert_test.1556679151
Short name T842
Test name
Test status
Simulation time 32349992 ps
CPU time 0.55 seconds
Started Jun 06 12:58:25 PM PDT 24
Finished Jun 06 12:58:27 PM PDT 24
Peak memory 195680 kb
Host smart-32e84bb4-6dc1-421b-8027-4458d749cfa6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556679151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.1556679151
Directory /workspace/10.uart_alert_test/latest

Test location /workspace/coverage/default/10.uart_fifo_full.284231037
Short name T1134
Test name
Test status
Simulation time 81032835311 ps
CPU time 134.82 seconds
Started Jun 06 12:58:23 PM PDT 24
Finished Jun 06 01:00:39 PM PDT 24
Peak memory 200320 kb
Host smart-b45ce4e2-3474-419b-942a-3179198ad296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284231037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.284231037
Directory /workspace/10.uart_fifo_full/latest

Test location /workspace/coverage/default/10.uart_fifo_reset.971804336
Short name T583
Test name
Test status
Simulation time 20598637227 ps
CPU time 33.47 seconds
Started Jun 06 12:58:23 PM PDT 24
Finished Jun 06 12:58:58 PM PDT 24
Peak memory 200624 kb
Host smart-41ce6e8c-854d-49a3-8da1-14add9d6c93b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971804336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.971804336
Directory /workspace/10.uart_fifo_reset/latest

Test location /workspace/coverage/default/10.uart_intr.1742047707
Short name T1018
Test name
Test status
Simulation time 3225403335 ps
CPU time 5.88 seconds
Started Jun 06 12:58:24 PM PDT 24
Finished Jun 06 12:58:32 PM PDT 24
Peak memory 197012 kb
Host smart-326d2697-f570-48b5-8963-1eba1be947d1
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742047707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.1742047707
Directory /workspace/10.uart_intr/latest

Test location /workspace/coverage/default/10.uart_long_xfer_wo_dly.1788472476
Short name T587
Test name
Test status
Simulation time 87422877821 ps
CPU time 639.97 seconds
Started Jun 06 12:58:26 PM PDT 24
Finished Jun 06 01:09:07 PM PDT 24
Peak memory 200392 kb
Host smart-e9460104-b625-4687-be63-b5b7b2ba5469
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1788472476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.1788472476
Directory /workspace/10.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/10.uart_loopback.760392093
Short name T456
Test name
Test status
Simulation time 2794164168 ps
CPU time 2.96 seconds
Started Jun 06 12:58:24 PM PDT 24
Finished Jun 06 12:58:28 PM PDT 24
Peak memory 198664 kb
Host smart-3dafdd8d-17e2-4600-b3b8-7157ee3fa8f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760392093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_loopback.760392093
Directory /workspace/10.uart_loopback/latest

Test location /workspace/coverage/default/10.uart_noise_filter.3893719664
Short name T609
Test name
Test status
Simulation time 77801856369 ps
CPU time 66.61 seconds
Started Jun 06 12:58:22 PM PDT 24
Finished Jun 06 12:59:30 PM PDT 24
Peak memory 200472 kb
Host smart-04c09027-24cd-45ba-88f2-6cd0f3e5dbb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893719664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_noise_filter.3893719664
Directory /workspace/10.uart_noise_filter/latest

Test location /workspace/coverage/default/10.uart_perf.2265999650
Short name T1074
Test name
Test status
Simulation time 24778910503 ps
CPU time 1430.82 seconds
Started Jun 06 12:58:24 PM PDT 24
Finished Jun 06 01:22:16 PM PDT 24
Peak memory 200260 kb
Host smart-fd4c7eee-0684-4350-8404-e211802ca6e7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2265999650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.2265999650
Directory /workspace/10.uart_perf/latest

Test location /workspace/coverage/default/10.uart_rx_oversample.95402901
Short name T991
Test name
Test status
Simulation time 4669610896 ps
CPU time 5.24 seconds
Started Jun 06 12:58:24 PM PDT 24
Finished Jun 06 12:58:31 PM PDT 24
Peak memory 198600 kb
Host smart-4e8fb9fb-7639-484b-9586-56c35f60d5be
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=95402901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.95402901
Directory /workspace/10.uart_rx_oversample/latest

Test location /workspace/coverage/default/10.uart_rx_parity_err.1703446899
Short name T745
Test name
Test status
Simulation time 35292530880 ps
CPU time 52.02 seconds
Started Jun 06 12:58:25 PM PDT 24
Finished Jun 06 12:59:19 PM PDT 24
Peak memory 200312 kb
Host smart-2825e380-22c7-4e39-9988-577bf6642612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703446899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.1703446899
Directory /workspace/10.uart_rx_parity_err/latest

Test location /workspace/coverage/default/10.uart_rx_start_bit_filter.233782819
Short name T367
Test name
Test status
Simulation time 3640041989 ps
CPU time 1.73 seconds
Started Jun 06 12:58:23 PM PDT 24
Finished Jun 06 12:58:27 PM PDT 24
Peak memory 196756 kb
Host smart-f47ddd49-6f17-484e-878f-bf8eb57d9368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233782819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.233782819
Directory /workspace/10.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/10.uart_smoke.2263379613
Short name T113
Test name
Test status
Simulation time 706724400 ps
CPU time 1.45 seconds
Started Jun 06 12:58:23 PM PDT 24
Finished Jun 06 12:58:26 PM PDT 24
Peak memory 198732 kb
Host smart-1ced53af-aa7c-4391-88b0-da6f7ecf16de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263379613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_smoke.2263379613
Directory /workspace/10.uart_smoke/latest

Test location /workspace/coverage/default/10.uart_stress_all.1066718654
Short name T838
Test name
Test status
Simulation time 289542126742 ps
CPU time 672.5 seconds
Started Jun 06 12:58:29 PM PDT 24
Finished Jun 06 01:09:43 PM PDT 24
Peak memory 211428 kb
Host smart-315a4ccf-2f98-4e06-ba19-c077595a26d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066718654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.1066718654
Directory /workspace/10.uart_stress_all/latest

Test location /workspace/coverage/default/10.uart_stress_all_with_rand_reset.3467399528
Short name T764
Test name
Test status
Simulation time 50833973843 ps
CPU time 408.03 seconds
Started Jun 06 12:58:23 PM PDT 24
Finished Jun 06 01:05:12 PM PDT 24
Peak memory 217092 kb
Host smart-99cb1ee3-dba1-47ff-9cb6-9ff4164aeaaa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467399528 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 10.uart_stress_all_with_rand_reset.3467399528
Directory /workspace/10.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.uart_tx_ovrd.2428971466
Short name T378
Test name
Test status
Simulation time 1016221371 ps
CPU time 4.4 seconds
Started Jun 06 12:58:24 PM PDT 24
Finished Jun 06 12:58:30 PM PDT 24
Peak memory 198732 kb
Host smart-918d5243-54ac-4c0d-8c5c-99659adb4848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428971466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.2428971466
Directory /workspace/10.uart_tx_ovrd/latest

Test location /workspace/coverage/default/10.uart_tx_rx.3472816951
Short name T893
Test name
Test status
Simulation time 24607352625 ps
CPU time 31.03 seconds
Started Jun 06 12:58:25 PM PDT 24
Finished Jun 06 12:58:57 PM PDT 24
Peak memory 200268 kb
Host smart-b76f6ee8-2a43-4a46-bded-4cdc62c0d25a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472816951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.3472816951
Directory /workspace/10.uart_tx_rx/latest

Test location /workspace/coverage/default/100.uart_fifo_reset.14887706
Short name T205
Test name
Test status
Simulation time 25046061191 ps
CPU time 37.84 seconds
Started Jun 06 01:02:30 PM PDT 24
Finished Jun 06 01:03:08 PM PDT 24
Peak memory 200340 kb
Host smart-8b7ffc78-f599-4b8a-b391-06a8e6bfddd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14887706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.14887706
Directory /workspace/100.uart_fifo_reset/latest

Test location /workspace/coverage/default/101.uart_fifo_reset.1385156690
Short name T1015
Test name
Test status
Simulation time 54819676993 ps
CPU time 90.07 seconds
Started Jun 06 01:02:29 PM PDT 24
Finished Jun 06 01:04:00 PM PDT 24
Peak memory 200396 kb
Host smart-e728512a-f8c2-4301-b7fe-c60417cb3390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385156690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.1385156690
Directory /workspace/101.uart_fifo_reset/latest

Test location /workspace/coverage/default/102.uart_fifo_reset.1263051835
Short name T885
Test name
Test status
Simulation time 11707170749 ps
CPU time 7.75 seconds
Started Jun 06 01:02:30 PM PDT 24
Finished Jun 06 01:02:39 PM PDT 24
Peak memory 200372 kb
Host smart-bc3cea3d-64bd-4e49-9db7-51a34417313e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263051835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.1263051835
Directory /workspace/102.uart_fifo_reset/latest

Test location /workspace/coverage/default/103.uart_fifo_reset.2163478697
Short name T654
Test name
Test status
Simulation time 62011708003 ps
CPU time 25.21 seconds
Started Jun 06 01:02:27 PM PDT 24
Finished Jun 06 01:02:53 PM PDT 24
Peak memory 200396 kb
Host smart-49c76267-0231-4691-bf0d-919d4b44812a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163478697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.2163478697
Directory /workspace/103.uart_fifo_reset/latest

Test location /workspace/coverage/default/104.uart_fifo_reset.4232840649
Short name T700
Test name
Test status
Simulation time 17565474263 ps
CPU time 29.65 seconds
Started Jun 06 01:02:31 PM PDT 24
Finished Jun 06 01:03:02 PM PDT 24
Peak memory 200316 kb
Host smart-6f293497-13a6-4139-8886-d383cf95da47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232840649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.4232840649
Directory /workspace/104.uart_fifo_reset/latest

Test location /workspace/coverage/default/105.uart_fifo_reset.4221442429
Short name T544
Test name
Test status
Simulation time 51293320337 ps
CPU time 17.12 seconds
Started Jun 06 01:02:30 PM PDT 24
Finished Jun 06 01:02:48 PM PDT 24
Peak memory 200312 kb
Host smart-1d9076b3-96aa-4f36-84fb-1b6147688e7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221442429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.4221442429
Directory /workspace/105.uart_fifo_reset/latest

Test location /workspace/coverage/default/106.uart_fifo_reset.1920305660
Short name T316
Test name
Test status
Simulation time 45400715369 ps
CPU time 5.55 seconds
Started Jun 06 01:02:30 PM PDT 24
Finished Jun 06 01:02:36 PM PDT 24
Peak memory 199216 kb
Host smart-0714a2f1-88f7-4544-85b7-857c60baaf44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920305660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.1920305660
Directory /workspace/106.uart_fifo_reset/latest

Test location /workspace/coverage/default/108.uart_fifo_reset.590761025
Short name T225
Test name
Test status
Simulation time 32469387752 ps
CPU time 38.23 seconds
Started Jun 06 01:02:32 PM PDT 24
Finished Jun 06 01:03:12 PM PDT 24
Peak memory 200336 kb
Host smart-f7217dac-2e8e-4b5c-8e85-634104e0d070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590761025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.590761025
Directory /workspace/108.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_alert_test.2094878645
Short name T854
Test name
Test status
Simulation time 80520129 ps
CPU time 0.58 seconds
Started Jun 06 12:58:34 PM PDT 24
Finished Jun 06 12:58:36 PM PDT 24
Peak memory 195972 kb
Host smart-b3841c52-485d-4e1d-aeeb-7a61a923b1ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094878645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.2094878645
Directory /workspace/11.uart_alert_test/latest

Test location /workspace/coverage/default/11.uart_fifo_full.315141682
Short name T771
Test name
Test status
Simulation time 74091984815 ps
CPU time 38.92 seconds
Started Jun 06 12:58:26 PM PDT 24
Finished Jun 06 12:59:06 PM PDT 24
Peak memory 200408 kb
Host smart-b12b23d1-0807-4359-b337-5d826c1eaa6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315141682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.315141682
Directory /workspace/11.uart_fifo_full/latest

Test location /workspace/coverage/default/11.uart_fifo_overflow.1949672697
Short name T812
Test name
Test status
Simulation time 138495318196 ps
CPU time 64.23 seconds
Started Jun 06 12:58:26 PM PDT 24
Finished Jun 06 12:59:32 PM PDT 24
Peak memory 200328 kb
Host smart-94338138-bfad-400d-9d99-ed5f15c2f757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949672697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.1949672697
Directory /workspace/11.uart_fifo_overflow/latest

Test location /workspace/coverage/default/11.uart_intr.1575310328
Short name T1161
Test name
Test status
Simulation time 14859452032 ps
CPU time 13.97 seconds
Started Jun 06 12:58:25 PM PDT 24
Finished Jun 06 12:58:40 PM PDT 24
Peak memory 200288 kb
Host smart-b64975c7-c875-4c88-8d82-0184391d8da4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575310328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.1575310328
Directory /workspace/11.uart_intr/latest

Test location /workspace/coverage/default/11.uart_long_xfer_wo_dly.4137867314
Short name T573
Test name
Test status
Simulation time 135291805926 ps
CPU time 1077.41 seconds
Started Jun 06 12:58:33 PM PDT 24
Finished Jun 06 01:16:31 PM PDT 24
Peak memory 200328 kb
Host smart-6cbfde9d-3625-41ce-9eb0-78b64d5eab45
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4137867314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.4137867314
Directory /workspace/11.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/11.uart_loopback.1542908635
Short name T1092
Test name
Test status
Simulation time 4802421868 ps
CPU time 3.57 seconds
Started Jun 06 12:58:32 PM PDT 24
Finished Jun 06 12:58:36 PM PDT 24
Peak memory 200168 kb
Host smart-ef01c961-b85b-4757-b307-891957fe83ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542908635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_loopback.1542908635
Directory /workspace/11.uart_loopback/latest

Test location /workspace/coverage/default/11.uart_noise_filter.245656467
Short name T819
Test name
Test status
Simulation time 99374481649 ps
CPU time 175.94 seconds
Started Jun 06 12:58:23 PM PDT 24
Finished Jun 06 01:01:20 PM PDT 24
Peak memory 208856 kb
Host smart-4e63cbee-043a-41ed-8eeb-8d2bd73afe73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245656467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_noise_filter.245656467
Directory /workspace/11.uart_noise_filter/latest

Test location /workspace/coverage/default/11.uart_perf.3153172818
Short name T1089
Test name
Test status
Simulation time 22602289832 ps
CPU time 719.38 seconds
Started Jun 06 12:58:31 PM PDT 24
Finished Jun 06 01:10:31 PM PDT 24
Peak memory 200360 kb
Host smart-bbb4f003-30d9-4af8-aa01-8c6ddb5d727c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3153172818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.3153172818
Directory /workspace/11.uart_perf/latest

Test location /workspace/coverage/default/11.uart_rx_oversample.19061122
Short name T985
Test name
Test status
Simulation time 4507255459 ps
CPU time 8.36 seconds
Started Jun 06 12:58:24 PM PDT 24
Finished Jun 06 12:58:34 PM PDT 24
Peak memory 199604 kb
Host smart-3cb1fd60-c0b3-48b7-83fa-42fc9d4eba23
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=19061122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.19061122
Directory /workspace/11.uart_rx_oversample/latest

Test location /workspace/coverage/default/11.uart_rx_parity_err.2498662432
Short name T1169
Test name
Test status
Simulation time 248874170910 ps
CPU time 121.85 seconds
Started Jun 06 12:58:21 PM PDT 24
Finished Jun 06 01:00:24 PM PDT 24
Peak memory 200356 kb
Host smart-a5a9ed8f-e8fc-4c4e-b6ce-3634c237c106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498662432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.2498662432
Directory /workspace/11.uart_rx_parity_err/latest

Test location /workspace/coverage/default/11.uart_rx_start_bit_filter.289403675
Short name T27
Test name
Test status
Simulation time 4329644682 ps
CPU time 2.19 seconds
Started Jun 06 12:58:24 PM PDT 24
Finished Jun 06 12:58:28 PM PDT 24
Peak memory 196620 kb
Host smart-f7aeb3e3-34f4-4be8-8821-1a0ab42db0ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289403675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.289403675
Directory /workspace/11.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/11.uart_smoke.2742665363
Short name T862
Test name
Test status
Simulation time 5813834826 ps
CPU time 5.21 seconds
Started Jun 06 12:58:23 PM PDT 24
Finished Jun 06 12:58:30 PM PDT 24
Peak memory 200252 kb
Host smart-808225ec-2b81-417a-86bb-ce5883a064a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742665363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_smoke.2742665363
Directory /workspace/11.uart_smoke/latest

Test location /workspace/coverage/default/11.uart_stress_all.292233224
Short name T1049
Test name
Test status
Simulation time 325943990424 ps
CPU time 847.72 seconds
Started Jun 06 12:58:43 PM PDT 24
Finished Jun 06 01:12:52 PM PDT 24
Peak memory 200048 kb
Host smart-96645215-75bb-4842-8755-750611772beb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292233224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.292233224
Directory /workspace/11.uart_stress_all/latest

Test location /workspace/coverage/default/11.uart_stress_all_with_rand_reset.2676549848
Short name T1184
Test name
Test status
Simulation time 30327975243 ps
CPU time 279.09 seconds
Started Jun 06 12:58:29 PM PDT 24
Finished Jun 06 01:03:09 PM PDT 24
Peak memory 213348 kb
Host smart-94f96644-51f9-4eff-b725-b828081624bc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676549848 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 11.uart_stress_all_with_rand_reset.2676549848
Directory /workspace/11.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.uart_tx_ovrd.4053380729
Short name T508
Test name
Test status
Simulation time 6194428590 ps
CPU time 29.46 seconds
Started Jun 06 12:58:22 PM PDT 24
Finished Jun 06 12:58:53 PM PDT 24
Peak memory 199776 kb
Host smart-453eb8ce-ae34-47dd-9911-c3711ead6ac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053380729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.4053380729
Directory /workspace/11.uart_tx_ovrd/latest

Test location /workspace/coverage/default/11.uart_tx_rx.1362640543
Short name T1098
Test name
Test status
Simulation time 59256563904 ps
CPU time 115.5 seconds
Started Jun 06 12:58:28 PM PDT 24
Finished Jun 06 01:00:25 PM PDT 24
Peak memory 200400 kb
Host smart-9de81b37-e893-4c17-9ec7-6c562f7be5d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362640543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.1362640543
Directory /workspace/11.uart_tx_rx/latest

Test location /workspace/coverage/default/111.uart_fifo_reset.1834551720
Short name T220
Test name
Test status
Simulation time 43744629242 ps
CPU time 23.11 seconds
Started Jun 06 01:02:31 PM PDT 24
Finished Jun 06 01:02:55 PM PDT 24
Peak memory 200300 kb
Host smart-35db4907-ebe2-4ce0-9916-191d2da57e49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834551720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.1834551720
Directory /workspace/111.uart_fifo_reset/latest

Test location /workspace/coverage/default/112.uart_fifo_reset.191160427
Short name T629
Test name
Test status
Simulation time 35962228659 ps
CPU time 52.03 seconds
Started Jun 06 01:02:30 PM PDT 24
Finished Jun 06 01:03:23 PM PDT 24
Peak memory 200232 kb
Host smart-d27a5c29-80ac-40d3-bd0a-21623f468971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191160427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.191160427
Directory /workspace/112.uart_fifo_reset/latest

Test location /workspace/coverage/default/113.uart_fifo_reset.1732314599
Short name T2
Test name
Test status
Simulation time 27442057315 ps
CPU time 52.02 seconds
Started Jun 06 01:02:35 PM PDT 24
Finished Jun 06 01:03:29 PM PDT 24
Peak memory 200328 kb
Host smart-e2c35ff7-bc21-49a5-af29-a8303b05cf3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732314599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.1732314599
Directory /workspace/113.uart_fifo_reset/latest

Test location /workspace/coverage/default/114.uart_fifo_reset.1670544186
Short name T337
Test name
Test status
Simulation time 25813997313 ps
CPU time 12.05 seconds
Started Jun 06 01:02:31 PM PDT 24
Finished Jun 06 01:02:44 PM PDT 24
Peak memory 200316 kb
Host smart-5e535f57-3d18-4997-9517-1b8b290e865f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670544186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.1670544186
Directory /workspace/114.uart_fifo_reset/latest

Test location /workspace/coverage/default/115.uart_fifo_reset.14480617
Short name T498
Test name
Test status
Simulation time 55284784804 ps
CPU time 23.41 seconds
Started Jun 06 01:02:30 PM PDT 24
Finished Jun 06 01:02:55 PM PDT 24
Peak memory 199436 kb
Host smart-7e139191-3b81-4758-8b98-84000d07d966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14480617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.14480617
Directory /workspace/115.uart_fifo_reset/latest

Test location /workspace/coverage/default/116.uart_fifo_reset.3904382909
Short name T961
Test name
Test status
Simulation time 86214405088 ps
CPU time 135.91 seconds
Started Jun 06 01:02:35 PM PDT 24
Finished Jun 06 01:04:53 PM PDT 24
Peak memory 200304 kb
Host smart-9cd00904-10e5-49ac-93dd-02a2d6b94d59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904382909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.3904382909
Directory /workspace/116.uart_fifo_reset/latest

Test location /workspace/coverage/default/117.uart_fifo_reset.755558939
Short name T1027
Test name
Test status
Simulation time 226635571959 ps
CPU time 31.15 seconds
Started Jun 06 01:02:35 PM PDT 24
Finished Jun 06 01:03:08 PM PDT 24
Peak memory 200372 kb
Host smart-4a7a4769-b761-4180-8b1d-6713e0aa6d74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755558939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.755558939
Directory /workspace/117.uart_fifo_reset/latest

Test location /workspace/coverage/default/118.uart_fifo_reset.1696209837
Short name T283
Test name
Test status
Simulation time 173777135541 ps
CPU time 49.8 seconds
Started Jun 06 01:02:34 PM PDT 24
Finished Jun 06 01:03:25 PM PDT 24
Peak memory 200372 kb
Host smart-1bf64c5a-a6d9-4b98-86b9-c15b0e2e931d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696209837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.1696209837
Directory /workspace/118.uart_fifo_reset/latest

Test location /workspace/coverage/default/119.uart_fifo_reset.2479490583
Short name T588
Test name
Test status
Simulation time 152629772917 ps
CPU time 90.98 seconds
Started Jun 06 01:02:32 PM PDT 24
Finished Jun 06 01:04:04 PM PDT 24
Peak memory 200212 kb
Host smart-b476e321-a98f-484a-9045-448035392325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479490583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.2479490583
Directory /workspace/119.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_alert_test.323091507
Short name T792
Test name
Test status
Simulation time 22547413 ps
CPU time 0.53 seconds
Started Jun 06 12:58:32 PM PDT 24
Finished Jun 06 12:58:34 PM PDT 24
Peak memory 195716 kb
Host smart-89dc2050-58c6-4390-9a8c-36ff965d8b55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323091507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.323091507
Directory /workspace/12.uart_alert_test/latest

Test location /workspace/coverage/default/12.uart_fifo_full.3256957409
Short name T288
Test name
Test status
Simulation time 32836105380 ps
CPU time 59.99 seconds
Started Jun 06 12:58:34 PM PDT 24
Finished Jun 06 12:59:35 PM PDT 24
Peak memory 200396 kb
Host smart-2ce0793a-24f4-4c91-93c5-653021cf14b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256957409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.3256957409
Directory /workspace/12.uart_fifo_full/latest

Test location /workspace/coverage/default/12.uart_fifo_overflow.1727607816
Short name T582
Test name
Test status
Simulation time 118869882084 ps
CPU time 66.66 seconds
Started Jun 06 12:58:32 PM PDT 24
Finished Jun 06 12:59:40 PM PDT 24
Peak memory 200288 kb
Host smart-395d49c3-a826-44bf-aa7d-db1f694883fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727607816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.1727607816
Directory /workspace/12.uart_fifo_overflow/latest

Test location /workspace/coverage/default/12.uart_fifo_reset.2341393591
Short name T178
Test name
Test status
Simulation time 45786543514 ps
CPU time 27.09 seconds
Started Jun 06 12:58:34 PM PDT 24
Finished Jun 06 12:59:03 PM PDT 24
Peak memory 200312 kb
Host smart-0092c1a5-dd9b-4055-b08a-d4e9b587a10f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341393591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.2341393591
Directory /workspace/12.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_intr.1569472579
Short name T1182
Test name
Test status
Simulation time 44700604196 ps
CPU time 22.03 seconds
Started Jun 06 12:58:33 PM PDT 24
Finished Jun 06 12:58:56 PM PDT 24
Peak memory 200404 kb
Host smart-8e13461f-ea4a-40f6-b177-469df63b92c9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569472579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.1569472579
Directory /workspace/12.uart_intr/latest

Test location /workspace/coverage/default/12.uart_long_xfer_wo_dly.2861956513
Short name T1141
Test name
Test status
Simulation time 139240730604 ps
CPU time 327.28 seconds
Started Jun 06 12:58:34 PM PDT 24
Finished Jun 06 01:04:02 PM PDT 24
Peak memory 200332 kb
Host smart-78379d99-c09f-473e-b7d8-ef9f9b59f086
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2861956513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.2861956513
Directory /workspace/12.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/12.uart_loopback.1734915005
Short name T715
Test name
Test status
Simulation time 2187335773 ps
CPU time 4.72 seconds
Started Jun 06 12:58:30 PM PDT 24
Finished Jun 06 12:58:37 PM PDT 24
Peak memory 198580 kb
Host smart-938d5ffe-0782-4d04-a2ff-04405bf1f9c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734915005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_loopback.1734915005
Directory /workspace/12.uart_loopback/latest

Test location /workspace/coverage/default/12.uart_noise_filter.399843689
Short name T8
Test name
Test status
Simulation time 19193525839 ps
CPU time 14.57 seconds
Started Jun 06 12:58:31 PM PDT 24
Finished Jun 06 12:58:46 PM PDT 24
Peak memory 200356 kb
Host smart-d5ea05d1-7677-491f-8989-84c549c27a69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399843689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_noise_filter.399843689
Directory /workspace/12.uart_noise_filter/latest

Test location /workspace/coverage/default/12.uart_perf.1544784154
Short name T752
Test name
Test status
Simulation time 10300374650 ps
CPU time 377.31 seconds
Started Jun 06 12:58:29 PM PDT 24
Finished Jun 06 01:04:48 PM PDT 24
Peak memory 200340 kb
Host smart-fd4a8553-87cc-4803-b13d-8787aa348af5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1544784154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.1544784154
Directory /workspace/12.uart_perf/latest

Test location /workspace/coverage/default/12.uart_rx_oversample.1376485479
Short name T953
Test name
Test status
Simulation time 6594890497 ps
CPU time 13.78 seconds
Started Jun 06 12:58:43 PM PDT 24
Finished Jun 06 12:58:58 PM PDT 24
Peak memory 199288 kb
Host smart-ee307ff3-f81b-49f2-b402-9e9e05b90f57
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1376485479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.1376485479
Directory /workspace/12.uart_rx_oversample/latest

Test location /workspace/coverage/default/12.uart_rx_parity_err.276051313
Short name T539
Test name
Test status
Simulation time 45735627724 ps
CPU time 40.72 seconds
Started Jun 06 12:58:30 PM PDT 24
Finished Jun 06 12:59:12 PM PDT 24
Peak memory 200320 kb
Host smart-04b134dd-44cd-4dfd-ba9f-0036eef86c23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276051313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.276051313
Directory /workspace/12.uart_rx_parity_err/latest

Test location /workspace/coverage/default/12.uart_rx_start_bit_filter.165781207
Short name T630
Test name
Test status
Simulation time 3368462337 ps
CPU time 6.18 seconds
Started Jun 06 12:58:34 PM PDT 24
Finished Jun 06 12:58:42 PM PDT 24
Peak memory 196820 kb
Host smart-f6697217-5e34-4624-ad85-bdfc779d1292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165781207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.165781207
Directory /workspace/12.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/12.uart_smoke.1286324490
Short name T354
Test name
Test status
Simulation time 124039101 ps
CPU time 0.9 seconds
Started Jun 06 12:58:43 PM PDT 24
Finished Jun 06 12:58:45 PM PDT 24
Peak memory 197220 kb
Host smart-a73c13f8-9001-48a2-82e4-aa9e1d68b5b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286324490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_smoke.1286324490
Directory /workspace/12.uart_smoke/latest

Test location /workspace/coverage/default/12.uart_stress_all.1930324090
Short name T1095
Test name
Test status
Simulation time 137879901300 ps
CPU time 137.25 seconds
Started Jun 06 12:58:31 PM PDT 24
Finished Jun 06 01:00:49 PM PDT 24
Peak memory 208776 kb
Host smart-ee359864-9fe7-47ec-a591-884f176d905e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930324090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.1930324090
Directory /workspace/12.uart_stress_all/latest

Test location /workspace/coverage/default/12.uart_stress_all_with_rand_reset.1262553124
Short name T1144
Test name
Test status
Simulation time 38314053352 ps
CPU time 458.01 seconds
Started Jun 06 12:58:31 PM PDT 24
Finished Jun 06 01:06:11 PM PDT 24
Peak memory 217004 kb
Host smart-17ba45aa-d206-41a2-a69a-62dbd5c0d691
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262553124 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 12.uart_stress_all_with_rand_reset.1262553124
Directory /workspace/12.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.uart_tx_ovrd.3226008393
Short name T506
Test name
Test status
Simulation time 6344160978 ps
CPU time 15.88 seconds
Started Jun 06 12:58:30 PM PDT 24
Finished Jun 06 12:58:48 PM PDT 24
Peak memory 199632 kb
Host smart-af8dba32-3a78-401d-8c92-6af2562fffe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226008393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.3226008393
Directory /workspace/12.uart_tx_ovrd/latest

Test location /workspace/coverage/default/12.uart_tx_rx.1334354554
Short name T1053
Test name
Test status
Simulation time 162831389601 ps
CPU time 62.78 seconds
Started Jun 06 12:58:32 PM PDT 24
Finished Jun 06 12:59:36 PM PDT 24
Peak memory 200356 kb
Host smart-4e2bf2d9-859d-484e-b443-cb93304ae9f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334354554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.1334354554
Directory /workspace/12.uart_tx_rx/latest

Test location /workspace/coverage/default/120.uart_fifo_reset.1058173719
Short name T1079
Test name
Test status
Simulation time 91720620705 ps
CPU time 30.02 seconds
Started Jun 06 01:02:36 PM PDT 24
Finished Jun 06 01:03:08 PM PDT 24
Peak memory 199404 kb
Host smart-1261943d-4a8b-4f6e-9e5e-ed7b5a874daa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058173719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.1058173719
Directory /workspace/120.uart_fifo_reset/latest

Test location /workspace/coverage/default/121.uart_fifo_reset.4006222672
Short name T943
Test name
Test status
Simulation time 61566074828 ps
CPU time 90.97 seconds
Started Jun 06 01:02:37 PM PDT 24
Finished Jun 06 01:04:09 PM PDT 24
Peak memory 200372 kb
Host smart-cbfe2bc0-beae-4429-88f9-a566e48fe59a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006222672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.4006222672
Directory /workspace/121.uart_fifo_reset/latest

Test location /workspace/coverage/default/124.uart_fifo_reset.3197182440
Short name T602
Test name
Test status
Simulation time 56559772626 ps
CPU time 8.92 seconds
Started Jun 06 01:02:35 PM PDT 24
Finished Jun 06 01:02:46 PM PDT 24
Peak memory 200400 kb
Host smart-19644576-ba16-4e40-89dc-31f7152300d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197182440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.3197182440
Directory /workspace/124.uart_fifo_reset/latest

Test location /workspace/coverage/default/125.uart_fifo_reset.858298400
Short name T564
Test name
Test status
Simulation time 78078179970 ps
CPU time 143.61 seconds
Started Jun 06 01:02:36 PM PDT 24
Finished Jun 06 01:05:01 PM PDT 24
Peak memory 200324 kb
Host smart-f4a2c1cf-4369-44c7-ad7b-c4c8f23eed68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858298400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.858298400
Directory /workspace/125.uart_fifo_reset/latest

Test location /workspace/coverage/default/126.uart_fifo_reset.1649080168
Short name T1076
Test name
Test status
Simulation time 52901948531 ps
CPU time 71.78 seconds
Started Jun 06 01:02:38 PM PDT 24
Finished Jun 06 01:03:52 PM PDT 24
Peak memory 200312 kb
Host smart-cfd22ea5-4a1b-419b-94f7-f6766253d307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649080168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.1649080168
Directory /workspace/126.uart_fifo_reset/latest

Test location /workspace/coverage/default/127.uart_fifo_reset.2908244123
Short name T1088
Test name
Test status
Simulation time 94314293915 ps
CPU time 45.73 seconds
Started Jun 06 01:02:36 PM PDT 24
Finished Jun 06 01:03:24 PM PDT 24
Peak memory 200376 kb
Host smart-7ef235bd-221e-4a80-a9e7-1a5f319d2a77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908244123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.2908244123
Directory /workspace/127.uart_fifo_reset/latest

Test location /workspace/coverage/default/128.uart_fifo_reset.2116745875
Short name T599
Test name
Test status
Simulation time 331513799191 ps
CPU time 35.55 seconds
Started Jun 06 01:02:38 PM PDT 24
Finished Jun 06 01:03:15 PM PDT 24
Peak memory 200004 kb
Host smart-da80cd03-40b9-4399-90d5-a1c3275d5e25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116745875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.2116745875
Directory /workspace/128.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_alert_test.658872297
Short name T375
Test name
Test status
Simulation time 12554762 ps
CPU time 0.61 seconds
Started Jun 06 12:58:31 PM PDT 24
Finished Jun 06 12:58:33 PM PDT 24
Peak memory 195996 kb
Host smart-819f6ca0-ea37-48df-9ce0-4fa957157364
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658872297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.658872297
Directory /workspace/13.uart_alert_test/latest

Test location /workspace/coverage/default/13.uart_fifo_full.860672031
Short name T619
Test name
Test status
Simulation time 23467503300 ps
CPU time 40.64 seconds
Started Jun 06 12:58:31 PM PDT 24
Finished Jun 06 12:59:13 PM PDT 24
Peak memory 200244 kb
Host smart-dad9fa1a-533f-47c7-a843-62e59f576d67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860672031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.860672031
Directory /workspace/13.uart_fifo_full/latest

Test location /workspace/coverage/default/13.uart_fifo_overflow.427782819
Short name T499
Test name
Test status
Simulation time 40783427085 ps
CPU time 45.46 seconds
Started Jun 06 12:58:43 PM PDT 24
Finished Jun 06 12:59:30 PM PDT 24
Peak memory 200088 kb
Host smart-b9233769-2a3f-435c-9608-691d0ccf3baa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427782819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.427782819
Directory /workspace/13.uart_fifo_overflow/latest

Test location /workspace/coverage/default/13.uart_intr.4204509353
Short name T664
Test name
Test status
Simulation time 38810712590 ps
CPU time 17.39 seconds
Started Jun 06 12:58:32 PM PDT 24
Finished Jun 06 12:58:51 PM PDT 24
Peak memory 200320 kb
Host smart-80c36ae6-6b51-48cf-bb1a-863b68d645a0
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204509353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.4204509353
Directory /workspace/13.uart_intr/latest

Test location /workspace/coverage/default/13.uart_long_xfer_wo_dly.3349535543
Short name T340
Test name
Test status
Simulation time 94226027836 ps
CPU time 680.62 seconds
Started Jun 06 12:58:31 PM PDT 24
Finished Jun 06 01:09:53 PM PDT 24
Peak memory 200216 kb
Host smart-8bc5eef1-f8d5-4cd5-8554-394611b1f6cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3349535543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.3349535543
Directory /workspace/13.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/13.uart_loopback.3056877827
Short name T339
Test name
Test status
Simulation time 3207073351 ps
CPU time 7.72 seconds
Started Jun 06 12:58:32 PM PDT 24
Finished Jun 06 12:58:41 PM PDT 24
Peak memory 200220 kb
Host smart-188c1cd6-042e-434b-a71c-9a3726df09a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056877827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_loopback.3056877827
Directory /workspace/13.uart_loopback/latest

Test location /workspace/coverage/default/13.uart_noise_filter.2120916234
Short name T531
Test name
Test status
Simulation time 78725428986 ps
CPU time 35.12 seconds
Started Jun 06 12:58:32 PM PDT 24
Finished Jun 06 12:59:08 PM PDT 24
Peak memory 200536 kb
Host smart-5159a4af-f3e1-4889-9e24-1d59c667b40d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120916234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_noise_filter.2120916234
Directory /workspace/13.uart_noise_filter/latest

Test location /workspace/coverage/default/13.uart_perf.1420636593
Short name T1146
Test name
Test status
Simulation time 16569076440 ps
CPU time 921.29 seconds
Started Jun 06 12:58:31 PM PDT 24
Finished Jun 06 01:13:53 PM PDT 24
Peak memory 200312 kb
Host smart-7525d1a1-ab97-43a2-9174-bb7514ba9003
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1420636593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.1420636593
Directory /workspace/13.uart_perf/latest

Test location /workspace/coverage/default/13.uart_rx_oversample.2761952409
Short name T997
Test name
Test status
Simulation time 6233778307 ps
CPU time 50.84 seconds
Started Jun 06 12:58:34 PM PDT 24
Finished Jun 06 12:59:26 PM PDT 24
Peak memory 198552 kb
Host smart-fd990fca-86d1-4200-ad66-b9095b10e733
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2761952409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.2761952409
Directory /workspace/13.uart_rx_oversample/latest

Test location /workspace/coverage/default/13.uart_rx_parity_err.346438963
Short name T162
Test name
Test status
Simulation time 66483306750 ps
CPU time 148.52 seconds
Started Jun 06 12:58:43 PM PDT 24
Finished Jun 06 01:01:13 PM PDT 24
Peak memory 200116 kb
Host smart-72cb8c5f-6a95-435a-879e-9230d4720504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346438963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.346438963
Directory /workspace/13.uart_rx_parity_err/latest

Test location /workspace/coverage/default/13.uart_rx_start_bit_filter.3833112832
Short name T411
Test name
Test status
Simulation time 4377522895 ps
CPU time 1.83 seconds
Started Jun 06 12:58:33 PM PDT 24
Finished Jun 06 12:58:36 PM PDT 24
Peak memory 196644 kb
Host smart-5f02b0f2-6bc3-46fa-9396-6968cfccaf9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833112832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.3833112832
Directory /workspace/13.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/13.uart_smoke.925127925
Short name T704
Test name
Test status
Simulation time 650951281 ps
CPU time 1.79 seconds
Started Jun 06 12:58:43 PM PDT 24
Finished Jun 06 12:58:46 PM PDT 24
Peak memory 200036 kb
Host smart-0a9f45ee-713d-479f-a4f7-014d46a496b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925127925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_smoke.925127925
Directory /workspace/13.uart_smoke/latest

Test location /workspace/coverage/default/13.uart_stress_all.149975989
Short name T894
Test name
Test status
Simulation time 242425482260 ps
CPU time 610.64 seconds
Started Jun 06 12:58:32 PM PDT 24
Finished Jun 06 01:08:44 PM PDT 24
Peak memory 200436 kb
Host smart-50550eff-e6ab-4fa8-8cf5-d30d620d307c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149975989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.149975989
Directory /workspace/13.uart_stress_all/latest

Test location /workspace/coverage/default/13.uart_stress_all_with_rand_reset.3004220411
Short name T779
Test name
Test status
Simulation time 22409054343 ps
CPU time 264.63 seconds
Started Jun 06 12:58:34 PM PDT 24
Finished Jun 06 01:03:00 PM PDT 24
Peak memory 213604 kb
Host smart-cff1a513-327d-42a1-a0a4-bf08c91fe1a2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004220411 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 13.uart_stress_all_with_rand_reset.3004220411
Directory /workspace/13.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.uart_tx_ovrd.902370352
Short name T52
Test name
Test status
Simulation time 1320568840 ps
CPU time 1.85 seconds
Started Jun 06 12:58:33 PM PDT 24
Finished Jun 06 12:58:36 PM PDT 24
Peak memory 198872 kb
Host smart-e1489504-92a5-4a4c-ad0d-efbd243c4965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902370352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.902370352
Directory /workspace/13.uart_tx_ovrd/latest

Test location /workspace/coverage/default/13.uart_tx_rx.4037166069
Short name T967
Test name
Test status
Simulation time 28778966775 ps
CPU time 35.8 seconds
Started Jun 06 12:58:31 PM PDT 24
Finished Jun 06 12:59:08 PM PDT 24
Peak memory 200256 kb
Host smart-97130c7f-35aa-4f69-9210-3c22836fe7b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037166069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.4037166069
Directory /workspace/13.uart_tx_rx/latest

Test location /workspace/coverage/default/130.uart_fifo_reset.421244377
Short name T198
Test name
Test status
Simulation time 18906409011 ps
CPU time 29.67 seconds
Started Jun 06 01:02:36 PM PDT 24
Finished Jun 06 01:03:08 PM PDT 24
Peak memory 200300 kb
Host smart-833dee4f-cd56-437e-b9b6-8fbaf453f43b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421244377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.421244377
Directory /workspace/130.uart_fifo_reset/latest

Test location /workspace/coverage/default/132.uart_fifo_reset.661210034
Short name T946
Test name
Test status
Simulation time 46114458863 ps
CPU time 46.07 seconds
Started Jun 06 01:02:41 PM PDT 24
Finished Jun 06 01:03:29 PM PDT 24
Peak memory 200328 kb
Host smart-51814fed-0f0e-4f52-9cd5-e9a8f8d15675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661210034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.661210034
Directory /workspace/132.uart_fifo_reset/latest

Test location /workspace/coverage/default/133.uart_fifo_reset.875438050
Short name T666
Test name
Test status
Simulation time 159197887540 ps
CPU time 60.42 seconds
Started Jun 06 01:02:39 PM PDT 24
Finished Jun 06 01:03:42 PM PDT 24
Peak memory 200288 kb
Host smart-eea21768-4e91-4a36-9c1b-b270e595d986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875438050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.875438050
Directory /workspace/133.uart_fifo_reset/latest

Test location /workspace/coverage/default/135.uart_fifo_reset.2276264460
Short name T558
Test name
Test status
Simulation time 230380120862 ps
CPU time 120.44 seconds
Started Jun 06 01:02:39 PM PDT 24
Finished Jun 06 01:04:41 PM PDT 24
Peak memory 200300 kb
Host smart-147c7f6c-28ca-4dd5-baf7-38037734b72c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276264460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.2276264460
Directory /workspace/135.uart_fifo_reset/latest

Test location /workspace/coverage/default/138.uart_fifo_reset.3628325095
Short name T190
Test name
Test status
Simulation time 33660276287 ps
CPU time 58.58 seconds
Started Jun 06 01:02:38 PM PDT 24
Finished Jun 06 01:03:38 PM PDT 24
Peak memory 200308 kb
Host smart-17dda6d8-fe54-4847-b508-2156b2afcca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628325095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.3628325095
Directory /workspace/138.uart_fifo_reset/latest

Test location /workspace/coverage/default/139.uart_fifo_reset.3684254862
Short name T469
Test name
Test status
Simulation time 20018235058 ps
CPU time 29.64 seconds
Started Jun 06 01:02:45 PM PDT 24
Finished Jun 06 01:03:16 PM PDT 24
Peak memory 200276 kb
Host smart-b23db8aa-4882-4964-a328-8aa67973a25d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684254862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.3684254862
Directory /workspace/139.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_alert_test.2971916385
Short name T377
Test name
Test status
Simulation time 14680677 ps
CPU time 0.54 seconds
Started Jun 06 12:58:44 PM PDT 24
Finished Jun 06 12:58:45 PM PDT 24
Peak memory 195528 kb
Host smart-2e1a3975-68c1-4869-aef9-87eeb425a38d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971916385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.2971916385
Directory /workspace/14.uart_alert_test/latest

Test location /workspace/coverage/default/14.uart_fifo_full.454030504
Short name T723
Test name
Test status
Simulation time 128724683342 ps
CPU time 199.27 seconds
Started Jun 06 12:58:31 PM PDT 24
Finished Jun 06 01:01:51 PM PDT 24
Peak memory 200324 kb
Host smart-2ebcf5bc-a3c9-4b6e-9055-ba0313385abd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454030504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.454030504
Directory /workspace/14.uart_fifo_full/latest

Test location /workspace/coverage/default/14.uart_fifo_overflow.467992858
Short name T956
Test name
Test status
Simulation time 129555470441 ps
CPU time 106.69 seconds
Started Jun 06 12:58:31 PM PDT 24
Finished Jun 06 01:00:19 PM PDT 24
Peak memory 200308 kb
Host smart-c63c95ee-2220-4ae1-8169-41e407502e8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467992858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.467992858
Directory /workspace/14.uart_fifo_overflow/latest

Test location /workspace/coverage/default/14.uart_fifo_reset.633745364
Short name T834
Test name
Test status
Simulation time 97083765320 ps
CPU time 87.25 seconds
Started Jun 06 12:58:31 PM PDT 24
Finished Jun 06 12:59:59 PM PDT 24
Peak memory 200352 kb
Host smart-d6215f2a-f00b-48f0-93dc-c66756178eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633745364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.633745364
Directory /workspace/14.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_intr.1472291909
Short name T570
Test name
Test status
Simulation time 10151975231 ps
CPU time 15.68 seconds
Started Jun 06 12:58:43 PM PDT 24
Finished Jun 06 12:59:00 PM PDT 24
Peak memory 196452 kb
Host smart-0b9e711b-30b3-41f2-85f5-85f923804873
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472291909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.1472291909
Directory /workspace/14.uart_intr/latest

Test location /workspace/coverage/default/14.uart_long_xfer_wo_dly.1031086165
Short name T258
Test name
Test status
Simulation time 125128293867 ps
CPU time 878.23 seconds
Started Jun 06 12:58:40 PM PDT 24
Finished Jun 06 01:13:20 PM PDT 24
Peak memory 200380 kb
Host smart-e18c3e32-feac-4fed-9cba-900e191c5c6c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1031086165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.1031086165
Directory /workspace/14.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/14.uart_loopback.10056379
Short name T1093
Test name
Test status
Simulation time 7883592559 ps
CPU time 4.64 seconds
Started Jun 06 12:58:40 PM PDT 24
Finished Jun 06 12:58:45 PM PDT 24
Peak memory 200024 kb
Host smart-fc461a51-19e1-4111-af1b-34c814ba97b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10056379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_loopback.10056379
Directory /workspace/14.uart_loopback/latest

Test location /workspace/coverage/default/14.uart_noise_filter.2315277161
Short name T990
Test name
Test status
Simulation time 159245270374 ps
CPU time 374.1 seconds
Started Jun 06 12:58:31 PM PDT 24
Finished Jun 06 01:04:47 PM PDT 24
Peak memory 200656 kb
Host smart-781c6dd3-91b9-48b3-b281-578398643b02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315277161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_noise_filter.2315277161
Directory /workspace/14.uart_noise_filter/latest

Test location /workspace/coverage/default/14.uart_perf.3798305987
Short name T556
Test name
Test status
Simulation time 20963875760 ps
CPU time 1068.14 seconds
Started Jun 06 12:58:42 PM PDT 24
Finished Jun 06 01:16:31 PM PDT 24
Peak memory 200324 kb
Host smart-19eb0851-db6b-4ff8-8f53-c347fab0aaf5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3798305987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.3798305987
Directory /workspace/14.uart_perf/latest

Test location /workspace/coverage/default/14.uart_rx_oversample.2934326247
Short name T4
Test name
Test status
Simulation time 1487826229 ps
CPU time 3.27 seconds
Started Jun 06 12:58:30 PM PDT 24
Finished Jun 06 12:58:35 PM PDT 24
Peak memory 198436 kb
Host smart-ff29b59f-2b72-4b79-982f-0170fe5eb9d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2934326247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.2934326247
Directory /workspace/14.uart_rx_oversample/latest

Test location /workspace/coverage/default/14.uart_rx_parity_err.1411810839
Short name T770
Test name
Test status
Simulation time 8797210995 ps
CPU time 2.48 seconds
Started Jun 06 12:58:32 PM PDT 24
Finished Jun 06 12:58:35 PM PDT 24
Peak memory 200192 kb
Host smart-731c0fff-6e45-4b6c-b243-dac8054a5e29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411810839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.1411810839
Directory /workspace/14.uart_rx_parity_err/latest

Test location /workspace/coverage/default/14.uart_rx_start_bit_filter.486252809
Short name T575
Test name
Test status
Simulation time 2473188914 ps
CPU time 1.82 seconds
Started Jun 06 12:58:34 PM PDT 24
Finished Jun 06 12:58:37 PM PDT 24
Peak memory 196060 kb
Host smart-ed5a161b-48da-4747-971d-f62c92785c26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486252809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.486252809
Directory /workspace/14.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/14.uart_smoke.1391121016
Short name T419
Test name
Test status
Simulation time 494300303 ps
CPU time 1.54 seconds
Started Jun 06 12:58:34 PM PDT 24
Finished Jun 06 12:58:37 PM PDT 24
Peak memory 198760 kb
Host smart-17c7ff5c-69f3-4103-be30-f3cd46d73704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391121016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_smoke.1391121016
Directory /workspace/14.uart_smoke/latest

Test location /workspace/coverage/default/14.uart_stress_all.2641435560
Short name T757
Test name
Test status
Simulation time 159574128166 ps
CPU time 1206.64 seconds
Started Jun 06 12:58:41 PM PDT 24
Finished Jun 06 01:18:49 PM PDT 24
Peak memory 208632 kb
Host smart-823314e7-6a41-4238-9313-8bf2205261a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641435560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.2641435560
Directory /workspace/14.uart_stress_all/latest

Test location /workspace/coverage/default/14.uart_stress_all_with_rand_reset.1870405745
Short name T962
Test name
Test status
Simulation time 51550145071 ps
CPU time 920.43 seconds
Started Jun 06 12:58:39 PM PDT 24
Finished Jun 06 01:14:01 PM PDT 24
Peak memory 216872 kb
Host smart-ad33914c-206c-4873-a16d-52fa39ee2b91
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870405745 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 14.uart_stress_all_with_rand_reset.1870405745
Directory /workspace/14.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.uart_tx_ovrd.602890710
Short name T811
Test name
Test status
Simulation time 1117323310 ps
CPU time 1.56 seconds
Started Jun 06 12:58:40 PM PDT 24
Finished Jun 06 12:58:43 PM PDT 24
Peak memory 200132 kb
Host smart-38252638-2fd9-4b40-82a8-f1c187b4df4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602890710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.602890710
Directory /workspace/14.uart_tx_ovrd/latest

Test location /workspace/coverage/default/14.uart_tx_rx.539321876
Short name T906
Test name
Test status
Simulation time 89214734460 ps
CPU time 99.53 seconds
Started Jun 06 12:58:34 PM PDT 24
Finished Jun 06 01:00:15 PM PDT 24
Peak memory 200328 kb
Host smart-9e4c8540-d24a-4907-98a6-621fbe1cfd0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539321876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.539321876
Directory /workspace/14.uart_tx_rx/latest

Test location /workspace/coverage/default/140.uart_fifo_reset.1511434104
Short name T874
Test name
Test status
Simulation time 16322023010 ps
CPU time 2.97 seconds
Started Jun 06 01:02:44 PM PDT 24
Finished Jun 06 01:02:48 PM PDT 24
Peak memory 199348 kb
Host smart-17f40fed-dbc5-4908-bbfd-8d9641944963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511434104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.1511434104
Directory /workspace/140.uart_fifo_reset/latest

Test location /workspace/coverage/default/141.uart_fifo_reset.1647985544
Short name T814
Test name
Test status
Simulation time 14756972574 ps
CPU time 20.81 seconds
Started Jun 06 01:02:43 PM PDT 24
Finished Jun 06 01:03:05 PM PDT 24
Peak memory 200360 kb
Host smart-0be5631a-d790-48cf-8fa2-71b4779a7ff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647985544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.1647985544
Directory /workspace/141.uart_fifo_reset/latest

Test location /workspace/coverage/default/142.uart_fifo_reset.593618968
Short name T191
Test name
Test status
Simulation time 125065748185 ps
CPU time 108.82 seconds
Started Jun 06 01:02:39 PM PDT 24
Finished Jun 06 01:04:30 PM PDT 24
Peak memory 200360 kb
Host smart-0df0cbbb-afc8-4ee1-94ea-880e93746d1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593618968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.593618968
Directory /workspace/142.uart_fifo_reset/latest

Test location /workspace/coverage/default/143.uart_fifo_reset.3560839143
Short name T281
Test name
Test status
Simulation time 15990267572 ps
CPU time 29.98 seconds
Started Jun 06 01:02:40 PM PDT 24
Finished Jun 06 01:03:13 PM PDT 24
Peak memory 200272 kb
Host smart-a00cc5b4-e0e3-42ed-be6b-7fe5a9b69c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560839143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.3560839143
Directory /workspace/143.uart_fifo_reset/latest

Test location /workspace/coverage/default/144.uart_fifo_reset.987637283
Short name T334
Test name
Test status
Simulation time 19349861456 ps
CPU time 12.84 seconds
Started Jun 06 01:02:44 PM PDT 24
Finished Jun 06 01:02:58 PM PDT 24
Peak memory 200352 kb
Host smart-341217d3-c1a4-4e1c-ac7c-5de441563c0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987637283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.987637283
Directory /workspace/144.uart_fifo_reset/latest

Test location /workspace/coverage/default/145.uart_fifo_reset.2187471051
Short name T616
Test name
Test status
Simulation time 151202221740 ps
CPU time 78.68 seconds
Started Jun 06 01:02:44 PM PDT 24
Finished Jun 06 01:04:03 PM PDT 24
Peak memory 200316 kb
Host smart-ba63dfbd-41ee-45a6-974a-b5f62e360b64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187471051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.2187471051
Directory /workspace/145.uart_fifo_reset/latest

Test location /workspace/coverage/default/146.uart_fifo_reset.2231655671
Short name T741
Test name
Test status
Simulation time 74061327521 ps
CPU time 36.13 seconds
Started Jun 06 01:02:47 PM PDT 24
Finished Jun 06 01:03:23 PM PDT 24
Peak memory 200296 kb
Host smart-fd35ae74-3c2d-465a-af7a-9ecb99d13e7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231655671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.2231655671
Directory /workspace/146.uart_fifo_reset/latest

Test location /workspace/coverage/default/147.uart_fifo_reset.1796596183
Short name T843
Test name
Test status
Simulation time 41569991261 ps
CPU time 57.66 seconds
Started Jun 06 01:02:39 PM PDT 24
Finished Jun 06 01:03:39 PM PDT 24
Peak memory 200344 kb
Host smart-ffd7ea91-0243-46ad-b834-9677f10597ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796596183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.1796596183
Directory /workspace/147.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_alert_test.709933481
Short name T476
Test name
Test status
Simulation time 15645852 ps
CPU time 0.56 seconds
Started Jun 06 12:58:54 PM PDT 24
Finished Jun 06 12:58:56 PM PDT 24
Peak memory 195952 kb
Host smart-dbeb4dce-f6a7-4fe1-8400-76d87be63e65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709933481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.709933481
Directory /workspace/15.uart_alert_test/latest

Test location /workspace/coverage/default/15.uart_fifo_full.2259777729
Short name T317
Test name
Test status
Simulation time 101046141946 ps
CPU time 61.43 seconds
Started Jun 06 12:58:40 PM PDT 24
Finished Jun 06 12:59:42 PM PDT 24
Peak memory 200340 kb
Host smart-4dc6519f-e4c2-4cde-89af-c79077659ecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259777729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.2259777729
Directory /workspace/15.uart_fifo_full/latest

Test location /workspace/coverage/default/15.uart_fifo_overflow.2922149432
Short name T881
Test name
Test status
Simulation time 71481558835 ps
CPU time 118.36 seconds
Started Jun 06 12:58:39 PM PDT 24
Finished Jun 06 01:00:39 PM PDT 24
Peak memory 200296 kb
Host smart-7ebb2165-c599-4d5f-bb3c-3ea7125df3db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922149432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.2922149432
Directory /workspace/15.uart_fifo_overflow/latest

Test location /workspace/coverage/default/15.uart_fifo_reset.4229446094
Short name T55
Test name
Test status
Simulation time 111897768663 ps
CPU time 115.45 seconds
Started Jun 06 12:58:38 PM PDT 24
Finished Jun 06 01:00:34 PM PDT 24
Peak memory 200268 kb
Host smart-1aee89e7-597c-46fc-86c4-574809f73cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229446094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.4229446094
Directory /workspace/15.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_intr.3835214244
Short name T515
Test name
Test status
Simulation time 12711629669 ps
CPU time 5.47 seconds
Started Jun 06 12:58:40 PM PDT 24
Finished Jun 06 12:58:46 PM PDT 24
Peak memory 197452 kb
Host smart-2b2e1ee5-0e63-443b-bb71-af9f0ae0913b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835214244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.3835214244
Directory /workspace/15.uart_intr/latest

Test location /workspace/coverage/default/15.uart_long_xfer_wo_dly.4134190931
Short name T289
Test name
Test status
Simulation time 188436263547 ps
CPU time 351.14 seconds
Started Jun 06 12:58:52 PM PDT 24
Finished Jun 06 01:04:44 PM PDT 24
Peak memory 200304 kb
Host smart-658b77b1-5f7a-447b-932b-8c2b4c95a439
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4134190931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.4134190931
Directory /workspace/15.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/15.uart_loopback.3905445005
Short name T457
Test name
Test status
Simulation time 6714121275 ps
CPU time 4.48 seconds
Started Jun 06 12:58:54 PM PDT 24
Finished Jun 06 12:58:59 PM PDT 24
Peak memory 199728 kb
Host smart-85febef4-126f-4ee5-80d5-e18673f5e253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905445005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_loopback.3905445005
Directory /workspace/15.uart_loopback/latest

Test location /workspace/coverage/default/15.uart_noise_filter.1186438256
Short name T1142
Test name
Test status
Simulation time 150036739986 ps
CPU time 69.09 seconds
Started Jun 06 12:58:41 PM PDT 24
Finished Jun 06 12:59:51 PM PDT 24
Peak memory 200868 kb
Host smart-53bd58f9-198d-41ff-92f2-58d60c7d6aaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186438256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_noise_filter.1186438256
Directory /workspace/15.uart_noise_filter/latest

Test location /workspace/coverage/default/15.uart_perf.3135683761
Short name T280
Test name
Test status
Simulation time 10343359570 ps
CPU time 123.12 seconds
Started Jun 06 12:58:51 PM PDT 24
Finished Jun 06 01:00:55 PM PDT 24
Peak memory 200292 kb
Host smart-4636c7bd-844b-420d-bdbe-23dade6250ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3135683761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.3135683761
Directory /workspace/15.uart_perf/latest

Test location /workspace/coverage/default/15.uart_rx_oversample.1131425807
Short name T442
Test name
Test status
Simulation time 5837478889 ps
CPU time 54.67 seconds
Started Jun 06 12:58:40 PM PDT 24
Finished Jun 06 12:59:36 PM PDT 24
Peak memory 199292 kb
Host smart-fc99e386-26f1-4c95-8ce5-eb5053cecff2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1131425807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.1131425807
Directory /workspace/15.uart_rx_oversample/latest

Test location /workspace/coverage/default/15.uart_rx_parity_err.2687689706
Short name T344
Test name
Test status
Simulation time 39818591676 ps
CPU time 62.01 seconds
Started Jun 06 12:58:53 PM PDT 24
Finished Jun 06 12:59:56 PM PDT 24
Peak memory 200196 kb
Host smart-24a34566-1dbb-45c3-ad2f-0ff081043b3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687689706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.2687689706
Directory /workspace/15.uart_rx_parity_err/latest

Test location /workspace/coverage/default/15.uart_rx_start_bit_filter.524188984
Short name T799
Test name
Test status
Simulation time 48294735221 ps
CPU time 20.99 seconds
Started Jun 06 12:58:40 PM PDT 24
Finished Jun 06 12:59:02 PM PDT 24
Peak memory 196136 kb
Host smart-f5772fbb-9625-40dd-bbb3-aac843e48ac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524188984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.524188984
Directory /workspace/15.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/15.uart_smoke.2347787185
Short name T968
Test name
Test status
Simulation time 5356954056 ps
CPU time 19.8 seconds
Started Jun 06 12:58:40 PM PDT 24
Finished Jun 06 12:59:01 PM PDT 24
Peak memory 199600 kb
Host smart-d68c13ff-b080-4cad-80ce-5d7a6edf8bf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347787185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_smoke.2347787185
Directory /workspace/15.uart_smoke/latest

Test location /workspace/coverage/default/15.uart_stress_all.675760318
Short name T111
Test name
Test status
Simulation time 903338675989 ps
CPU time 136.23 seconds
Started Jun 06 12:58:53 PM PDT 24
Finished Jun 06 01:01:10 PM PDT 24
Peak memory 216016 kb
Host smart-ca35dc0f-bd29-406e-86a8-89263da96d2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675760318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.675760318
Directory /workspace/15.uart_stress_all/latest

Test location /workspace/coverage/default/15.uart_stress_all_with_rand_reset.3749594406
Short name T882
Test name
Test status
Simulation time 95554110746 ps
CPU time 850.02 seconds
Started Jun 06 12:58:54 PM PDT 24
Finished Jun 06 01:13:05 PM PDT 24
Peak memory 225356 kb
Host smart-668d29ac-c272-45aa-8585-63d5b1d2f642
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749594406 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 15.uart_stress_all_with_rand_reset.3749594406
Directory /workspace/15.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.uart_tx_ovrd.4176409970
Short name T1081
Test name
Test status
Simulation time 8715064203 ps
CPU time 10 seconds
Started Jun 06 12:58:53 PM PDT 24
Finished Jun 06 12:59:04 PM PDT 24
Peak memory 200264 kb
Host smart-31138a6f-ae7a-452a-9fe5-4c0feb70bbdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176409970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.4176409970
Directory /workspace/15.uart_tx_ovrd/latest

Test location /workspace/coverage/default/15.uart_tx_rx.3988242400
Short name T781
Test name
Test status
Simulation time 14607962988 ps
CPU time 21.98 seconds
Started Jun 06 12:58:40 PM PDT 24
Finished Jun 06 12:59:03 PM PDT 24
Peak memory 200208 kb
Host smart-c4c054d8-3823-4978-9362-fa5e2485de0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988242400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.3988242400
Directory /workspace/15.uart_tx_rx/latest

Test location /workspace/coverage/default/150.uart_fifo_reset.1806782089
Short name T975
Test name
Test status
Simulation time 58303279224 ps
CPU time 46.59 seconds
Started Jun 06 01:02:41 PM PDT 24
Finished Jun 06 01:03:29 PM PDT 24
Peak memory 200376 kb
Host smart-b84b61b3-ba81-4bb6-b67b-30fd084d5bbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806782089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.1806782089
Directory /workspace/150.uart_fifo_reset/latest

Test location /workspace/coverage/default/151.uart_fifo_reset.3695919389
Short name T828
Test name
Test status
Simulation time 94257525811 ps
CPU time 21.65 seconds
Started Jun 06 01:02:44 PM PDT 24
Finished Jun 06 01:03:07 PM PDT 24
Peak memory 200320 kb
Host smart-2a5705fe-c939-4738-bfaa-7e140c4fd625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695919389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.3695919389
Directory /workspace/151.uart_fifo_reset/latest

Test location /workspace/coverage/default/152.uart_fifo_reset.75425365
Short name T1054
Test name
Test status
Simulation time 23894271832 ps
CPU time 42.2 seconds
Started Jun 06 01:02:41 PM PDT 24
Finished Jun 06 01:03:25 PM PDT 24
Peak memory 200364 kb
Host smart-2be2aa5b-275c-45ee-ba44-abeb5d193c2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75425365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.75425365
Directory /workspace/152.uart_fifo_reset/latest

Test location /workspace/coverage/default/153.uart_fifo_reset.3424280440
Short name T298
Test name
Test status
Simulation time 169161911568 ps
CPU time 257.41 seconds
Started Jun 06 01:02:44 PM PDT 24
Finished Jun 06 01:07:02 PM PDT 24
Peak memory 200400 kb
Host smart-1218b83d-527f-4a9b-97ae-13cea11b197b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424280440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.3424280440
Directory /workspace/153.uart_fifo_reset/latest

Test location /workspace/coverage/default/155.uart_fifo_reset.616777735
Short name T572
Test name
Test status
Simulation time 21933952038 ps
CPU time 50.1 seconds
Started Jun 06 01:02:48 PM PDT 24
Finished Jun 06 01:03:39 PM PDT 24
Peak memory 200324 kb
Host smart-4222a96b-d853-4a6a-92d7-9788baed8370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616777735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.616777735
Directory /workspace/155.uart_fifo_reset/latest

Test location /workspace/coverage/default/156.uart_fifo_reset.1858899122
Short name T163
Test name
Test status
Simulation time 37694769474 ps
CPU time 33.53 seconds
Started Jun 06 01:02:48 PM PDT 24
Finished Jun 06 01:03:22 PM PDT 24
Peak memory 200344 kb
Host smart-dee3e7a7-3c52-48c4-a102-b86afe4310bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858899122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.1858899122
Directory /workspace/156.uart_fifo_reset/latest

Test location /workspace/coverage/default/157.uart_fifo_reset.722135338
Short name T326
Test name
Test status
Simulation time 46793403810 ps
CPU time 114.55 seconds
Started Jun 06 01:02:51 PM PDT 24
Finished Jun 06 01:04:46 PM PDT 24
Peak memory 200288 kb
Host smart-9f452e39-33ec-43c3-b47c-2c56e44527f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722135338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.722135338
Directory /workspace/157.uart_fifo_reset/latest

Test location /workspace/coverage/default/158.uart_fifo_reset.2978951223
Short name T151
Test name
Test status
Simulation time 18519182788 ps
CPU time 20.89 seconds
Started Jun 06 01:02:49 PM PDT 24
Finished Jun 06 01:03:11 PM PDT 24
Peak memory 200340 kb
Host smart-1dbde5c4-73c6-4ff9-9be7-2d87202a169d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978951223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.2978951223
Directory /workspace/158.uart_fifo_reset/latest

Test location /workspace/coverage/default/159.uart_fifo_reset.511222555
Short name T194
Test name
Test status
Simulation time 68118154112 ps
CPU time 35.58 seconds
Started Jun 06 01:02:47 PM PDT 24
Finished Jun 06 01:03:23 PM PDT 24
Peak memory 200260 kb
Host smart-32b9c1b9-a45c-4b88-bbfb-fb26e5220785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511222555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.511222555
Directory /workspace/159.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_alert_test.3154237203
Short name T847
Test name
Test status
Simulation time 13769678 ps
CPU time 0.54 seconds
Started Jun 06 12:58:53 PM PDT 24
Finished Jun 06 12:58:55 PM PDT 24
Peak memory 195668 kb
Host smart-b80b0e89-a4b1-4961-9d0e-a80435dd40ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154237203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.3154237203
Directory /workspace/16.uart_alert_test/latest

Test location /workspace/coverage/default/16.uart_fifo_full.864806807
Short name T152
Test name
Test status
Simulation time 139426590912 ps
CPU time 148.01 seconds
Started Jun 06 12:58:54 PM PDT 24
Finished Jun 06 01:01:23 PM PDT 24
Peak memory 200292 kb
Host smart-c14ba0bf-560c-43af-a26f-7bb195977b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864806807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.864806807
Directory /workspace/16.uart_fifo_full/latest

Test location /workspace/coverage/default/16.uart_fifo_overflow.649526121
Short name T818
Test name
Test status
Simulation time 39412484858 ps
CPU time 13.92 seconds
Started Jun 06 12:58:53 PM PDT 24
Finished Jun 06 12:59:08 PM PDT 24
Peak memory 199636 kb
Host smart-c7e4e52a-80e9-4321-a8ab-e5c73cc2fcf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649526121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.649526121
Directory /workspace/16.uart_fifo_overflow/latest

Test location /workspace/coverage/default/16.uart_fifo_reset.118842760
Short name T362
Test name
Test status
Simulation time 145320298004 ps
CPU time 58.06 seconds
Started Jun 06 12:59:05 PM PDT 24
Finished Jun 06 01:00:05 PM PDT 24
Peak memory 200372 kb
Host smart-ae34b8bd-e5c3-4c20-affe-6ffe567c9bb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118842760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.118842760
Directory /workspace/16.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_intr.1868144439
Short name T532
Test name
Test status
Simulation time 26071272678 ps
CPU time 51.08 seconds
Started Jun 06 12:58:54 PM PDT 24
Finished Jun 06 12:59:46 PM PDT 24
Peak memory 200360 kb
Host smart-89668d59-319f-4b49-9c7e-9f19804514f5
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868144439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.1868144439
Directory /workspace/16.uart_intr/latest

Test location /workspace/coverage/default/16.uart_long_xfer_wo_dly.1582698105
Short name T349
Test name
Test status
Simulation time 134840499316 ps
CPU time 233.84 seconds
Started Jun 06 12:58:52 PM PDT 24
Finished Jun 06 01:02:47 PM PDT 24
Peak memory 200272 kb
Host smart-5a9db1a3-c0b3-44c3-a672-c726519d03a4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1582698105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.1582698105
Directory /workspace/16.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/16.uart_loopback.3386204241
Short name T376
Test name
Test status
Simulation time 12629233714 ps
CPU time 12.96 seconds
Started Jun 06 12:58:53 PM PDT 24
Finished Jun 06 12:59:08 PM PDT 24
Peak memory 200360 kb
Host smart-458e11f7-e815-4852-b796-e2e6c1ace067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386204241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_loopback.3386204241
Directory /workspace/16.uart_loopback/latest

Test location /workspace/coverage/default/16.uart_noise_filter.1613043493
Short name T891
Test name
Test status
Simulation time 197471329435 ps
CPU time 101.25 seconds
Started Jun 06 12:58:54 PM PDT 24
Finished Jun 06 01:00:36 PM PDT 24
Peak memory 200560 kb
Host smart-2045a213-2b31-45ea-bfe6-81edaf105377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613043493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_noise_filter.1613043493
Directory /workspace/16.uart_noise_filter/latest

Test location /workspace/coverage/default/16.uart_perf.3475875064
Short name T276
Test name
Test status
Simulation time 14576576732 ps
CPU time 512.16 seconds
Started Jun 06 12:58:55 PM PDT 24
Finished Jun 06 01:07:28 PM PDT 24
Peak memory 200332 kb
Host smart-b36fb91d-ba85-4bc6-8bbe-ad5327193788
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3475875064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.3475875064
Directory /workspace/16.uart_perf/latest

Test location /workspace/coverage/default/16.uart_rx_oversample.2555307340
Short name T653
Test name
Test status
Simulation time 2647749436 ps
CPU time 5.75 seconds
Started Jun 06 12:58:52 PM PDT 24
Finished Jun 06 12:58:59 PM PDT 24
Peak memory 198496 kb
Host smart-101484d4-ea15-49f6-9de3-aa875ee75002
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2555307340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.2555307340
Directory /workspace/16.uart_rx_oversample/latest

Test location /workspace/coverage/default/16.uart_rx_parity_err.336280494
Short name T1143
Test name
Test status
Simulation time 49046675201 ps
CPU time 90.59 seconds
Started Jun 06 12:58:53 PM PDT 24
Finished Jun 06 01:00:25 PM PDT 24
Peak memory 200348 kb
Host smart-171ca409-d0b7-421f-958f-3a8b5d2438b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336280494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.336280494
Directory /workspace/16.uart_rx_parity_err/latest

Test location /workspace/coverage/default/16.uart_rx_start_bit_filter.429074668
Short name T432
Test name
Test status
Simulation time 47576537573 ps
CPU time 41.39 seconds
Started Jun 06 12:58:53 PM PDT 24
Finished Jun 06 12:59:35 PM PDT 24
Peak memory 196164 kb
Host smart-8a915263-6e95-4d61-b7cf-735423258ac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429074668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.429074668
Directory /workspace/16.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/16.uart_smoke.3039347256
Short name T415
Test name
Test status
Simulation time 649853606 ps
CPU time 2.74 seconds
Started Jun 06 12:58:51 PM PDT 24
Finished Jun 06 12:58:55 PM PDT 24
Peak memory 198676 kb
Host smart-5fe1bc5e-c6b3-4f22-a689-b9d960419bec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039347256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_smoke.3039347256
Directory /workspace/16.uart_smoke/latest

Test location /workspace/coverage/default/16.uart_stress_all.3739758296
Short name T1039
Test name
Test status
Simulation time 333689900433 ps
CPU time 1358.09 seconds
Started Jun 06 12:58:51 PM PDT 24
Finished Jun 06 01:21:30 PM PDT 24
Peak memory 200296 kb
Host smart-ff068506-d7d3-4f22-938d-6a610d533ff9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739758296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.3739758296
Directory /workspace/16.uart_stress_all/latest

Test location /workspace/coverage/default/16.uart_stress_all_with_rand_reset.2920933759
Short name T999
Test name
Test status
Simulation time 72202112699 ps
CPU time 1106.06 seconds
Started Jun 06 12:58:53 PM PDT 24
Finished Jun 06 01:17:20 PM PDT 24
Peak memory 211552 kb
Host smart-ecfdf4b4-0b4c-4e14-b6ec-289f6a759efc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920933759 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 16.uart_stress_all_with_rand_reset.2920933759
Directory /workspace/16.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.uart_tx_ovrd.1964643892
Short name T576
Test name
Test status
Simulation time 6200423286 ps
CPU time 19.23 seconds
Started Jun 06 12:58:51 PM PDT 24
Finished Jun 06 12:59:11 PM PDT 24
Peak memory 200192 kb
Host smart-54d12482-66fe-482d-9f8f-ee876114ca8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964643892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.1964643892
Directory /workspace/16.uart_tx_ovrd/latest

Test location /workspace/coverage/default/16.uart_tx_rx.498269283
Short name T1125
Test name
Test status
Simulation time 9484249460 ps
CPU time 16.67 seconds
Started Jun 06 12:58:54 PM PDT 24
Finished Jun 06 12:59:11 PM PDT 24
Peak memory 200332 kb
Host smart-8aa229e6-db94-4b4e-8a25-46f06c01f591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498269283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.498269283
Directory /workspace/16.uart_tx_rx/latest

Test location /workspace/coverage/default/160.uart_fifo_reset.1436696540
Short name T1023
Test name
Test status
Simulation time 33019925612 ps
CPU time 26.81 seconds
Started Jun 06 01:02:48 PM PDT 24
Finished Jun 06 01:03:15 PM PDT 24
Peak memory 200292 kb
Host smart-e4fb180d-7af9-4329-9a1c-5a7eda967dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436696540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.1436696540
Directory /workspace/160.uart_fifo_reset/latest

Test location /workspace/coverage/default/161.uart_fifo_reset.2587460426
Short name T209
Test name
Test status
Simulation time 64169523110 ps
CPU time 41.08 seconds
Started Jun 06 01:02:48 PM PDT 24
Finished Jun 06 01:03:30 PM PDT 24
Peak memory 200432 kb
Host smart-f5a4c23b-971d-4d81-affe-fe7e81be8c85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587460426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.2587460426
Directory /workspace/161.uart_fifo_reset/latest

Test location /workspace/coverage/default/162.uart_fifo_reset.2153589052
Short name T1009
Test name
Test status
Simulation time 94594419769 ps
CPU time 80.35 seconds
Started Jun 06 01:02:51 PM PDT 24
Finished Jun 06 01:04:12 PM PDT 24
Peak memory 200356 kb
Host smart-bb4a31e5-c0cf-4b71-8190-5d09e2ec8fee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153589052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.2153589052
Directory /workspace/162.uart_fifo_reset/latest

Test location /workspace/coverage/default/163.uart_fifo_reset.1366726462
Short name T213
Test name
Test status
Simulation time 15478929427 ps
CPU time 24.88 seconds
Started Jun 06 01:02:50 PM PDT 24
Finished Jun 06 01:03:16 PM PDT 24
Peak memory 200116 kb
Host smart-e5108f35-2e8f-44f1-9345-87b551334e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366726462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.1366726462
Directory /workspace/163.uart_fifo_reset/latest

Test location /workspace/coverage/default/164.uart_fifo_reset.1653582470
Short name T692
Test name
Test status
Simulation time 67063651405 ps
CPU time 119.59 seconds
Started Jun 06 01:02:48 PM PDT 24
Finished Jun 06 01:04:49 PM PDT 24
Peak memory 200328 kb
Host smart-a7923a53-0856-47ca-9031-896be13f9708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653582470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.1653582470
Directory /workspace/164.uart_fifo_reset/latest

Test location /workspace/coverage/default/165.uart_fifo_reset.3064742454
Short name T952
Test name
Test status
Simulation time 30391355819 ps
CPU time 48.63 seconds
Started Jun 06 01:02:52 PM PDT 24
Finished Jun 06 01:03:41 PM PDT 24
Peak memory 200304 kb
Host smart-a0554ef3-697b-48a5-980b-997bcd210092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064742454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.3064742454
Directory /workspace/165.uart_fifo_reset/latest

Test location /workspace/coverage/default/166.uart_fifo_reset.2832479172
Short name T228
Test name
Test status
Simulation time 37183485637 ps
CPU time 15.46 seconds
Started Jun 06 01:02:48 PM PDT 24
Finished Jun 06 01:03:04 PM PDT 24
Peak memory 200404 kb
Host smart-7e8abd9f-c131-4cfa-8cdd-5fd49963dff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832479172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.2832479172
Directory /workspace/166.uart_fifo_reset/latest

Test location /workspace/coverage/default/167.uart_fifo_reset.2997004815
Short name T798
Test name
Test status
Simulation time 14582704991 ps
CPU time 10.88 seconds
Started Jun 06 01:02:50 PM PDT 24
Finished Jun 06 01:03:02 PM PDT 24
Peak memory 200336 kb
Host smart-ee5dda7d-4cc4-42f6-86e0-74bbd96f903a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997004815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.2997004815
Directory /workspace/167.uart_fifo_reset/latest

Test location /workspace/coverage/default/168.uart_fifo_reset.851110052
Short name T196
Test name
Test status
Simulation time 16537167260 ps
CPU time 23.83 seconds
Started Jun 06 01:02:51 PM PDT 24
Finished Jun 06 01:03:16 PM PDT 24
Peak memory 200368 kb
Host smart-9a595428-82fb-411f-ba12-61aed78048dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851110052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.851110052
Directory /workspace/168.uart_fifo_reset/latest

Test location /workspace/coverage/default/169.uart_fifo_reset.1330860137
Short name T495
Test name
Test status
Simulation time 123847561997 ps
CPU time 44.78 seconds
Started Jun 06 01:02:47 PM PDT 24
Finished Jun 06 01:03:33 PM PDT 24
Peak memory 200324 kb
Host smart-2f041263-4b2d-4cf9-93e5-57b9b542d8c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330860137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.1330860137
Directory /workspace/169.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_alert_test.1263310476
Short name T804
Test name
Test status
Simulation time 38765081 ps
CPU time 0.54 seconds
Started Jun 06 12:59:04 PM PDT 24
Finished Jun 06 12:59:06 PM PDT 24
Peak memory 195380 kb
Host smart-d0c64d6f-f061-430b-86b8-c1209f39016c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263310476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.1263310476
Directory /workspace/17.uart_alert_test/latest

Test location /workspace/coverage/default/17.uart_fifo_full.3737302649
Short name T927
Test name
Test status
Simulation time 19225641269 ps
CPU time 12.18 seconds
Started Jun 06 12:59:05 PM PDT 24
Finished Jun 06 12:59:18 PM PDT 24
Peak memory 200356 kb
Host smart-f7a95e5c-90ff-47da-bb95-3939d076e24b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737302649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.3737302649
Directory /workspace/17.uart_fifo_full/latest

Test location /workspace/coverage/default/17.uart_fifo_overflow.858791640
Short name T889
Test name
Test status
Simulation time 54028404464 ps
CPU time 42.07 seconds
Started Jun 06 12:59:08 PM PDT 24
Finished Jun 06 12:59:52 PM PDT 24
Peak memory 200364 kb
Host smart-88b9fcde-f1d3-4763-862a-92513ce4a8f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858791640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.858791640
Directory /workspace/17.uart_fifo_overflow/latest

Test location /workspace/coverage/default/17.uart_fifo_reset.307613004
Short name T154
Test name
Test status
Simulation time 31887204088 ps
CPU time 35.57 seconds
Started Jun 06 12:59:03 PM PDT 24
Finished Jun 06 12:59:40 PM PDT 24
Peak memory 200396 kb
Host smart-138c25f9-c766-49ba-88cf-d4c290fabb97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307613004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.307613004
Directory /workspace/17.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_intr.3865971409
Short name T718
Test name
Test status
Simulation time 27948060889 ps
CPU time 13.97 seconds
Started Jun 06 12:59:02 PM PDT 24
Finished Jun 06 12:59:17 PM PDT 24
Peak memory 200264 kb
Host smart-cd087a78-d141-4087-a48a-5b02bf89951d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865971409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.3865971409
Directory /workspace/17.uart_intr/latest

Test location /workspace/coverage/default/17.uart_long_xfer_wo_dly.3060778927
Short name T639
Test name
Test status
Simulation time 115786599022 ps
CPU time 1003.66 seconds
Started Jun 06 12:59:03 PM PDT 24
Finished Jun 06 01:15:48 PM PDT 24
Peak memory 200376 kb
Host smart-c1cae889-57b9-4142-b9c2-1bdb50669994
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3060778927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.3060778927
Directory /workspace/17.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/17.uart_loopback.3595892687
Short name T338
Test name
Test status
Simulation time 2209941943 ps
CPU time 2.41 seconds
Started Jun 06 12:59:06 PM PDT 24
Finished Jun 06 12:59:11 PM PDT 24
Peak memory 199784 kb
Host smart-6af85f0d-19e7-40ae-bf05-b6e26b25f919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595892687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_loopback.3595892687
Directory /workspace/17.uart_loopback/latest

Test location /workspace/coverage/default/17.uart_noise_filter.3148364687
Short name T695
Test name
Test status
Simulation time 136303811803 ps
CPU time 92.53 seconds
Started Jun 06 12:59:03 PM PDT 24
Finished Jun 06 01:00:37 PM PDT 24
Peak memory 200500 kb
Host smart-72dad360-b66c-4e0f-9c31-966274d6f206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148364687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_noise_filter.3148364687
Directory /workspace/17.uart_noise_filter/latest

Test location /workspace/coverage/default/17.uart_perf.2350777949
Short name T950
Test name
Test status
Simulation time 6240961794 ps
CPU time 315.91 seconds
Started Jun 06 12:59:03 PM PDT 24
Finished Jun 06 01:04:20 PM PDT 24
Peak memory 200268 kb
Host smart-828f2a6a-7b55-4aa0-9e72-abf47fa888df
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2350777949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.2350777949
Directory /workspace/17.uart_perf/latest

Test location /workspace/coverage/default/17.uart_rx_oversample.801181354
Short name T1090
Test name
Test status
Simulation time 5749068351 ps
CPU time 45.38 seconds
Started Jun 06 12:59:02 PM PDT 24
Finished Jun 06 12:59:49 PM PDT 24
Peak memory 198428 kb
Host smart-cddf3ede-824e-44e7-937a-ee1b2bc6bde9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=801181354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.801181354
Directory /workspace/17.uart_rx_oversample/latest

Test location /workspace/coverage/default/17.uart_rx_parity_err.2514752859
Short name T826
Test name
Test status
Simulation time 20947833558 ps
CPU time 50.17 seconds
Started Jun 06 12:59:06 PM PDT 24
Finished Jun 06 12:59:58 PM PDT 24
Peak memory 200196 kb
Host smart-81fcce74-0766-4956-ac56-20abb38b546a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514752859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.2514752859
Directory /workspace/17.uart_rx_parity_err/latest

Test location /workspace/coverage/default/17.uart_rx_start_bit_filter.2535776683
Short name T634
Test name
Test status
Simulation time 2855101474 ps
CPU time 5.54 seconds
Started Jun 06 12:59:02 PM PDT 24
Finished Jun 06 12:59:09 PM PDT 24
Peak memory 196068 kb
Host smart-93df66be-a561-4b55-808b-4d5b67f9703f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535776683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.2535776683
Directory /workspace/17.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/17.uart_smoke.3387502145
Short name T803
Test name
Test status
Simulation time 122664712 ps
CPU time 0.88 seconds
Started Jun 06 12:58:52 PM PDT 24
Finished Jun 06 12:58:54 PM PDT 24
Peak memory 197416 kb
Host smart-de641e02-eb0c-473d-ae25-8a879787b5c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387502145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_smoke.3387502145
Directory /workspace/17.uart_smoke/latest

Test location /workspace/coverage/default/17.uart_stress_all.2489810180
Short name T124
Test name
Test status
Simulation time 281085295432 ps
CPU time 295.15 seconds
Started Jun 06 12:59:04 PM PDT 24
Finished Jun 06 01:04:01 PM PDT 24
Peak memory 200316 kb
Host smart-bfe84416-ddab-401b-8aaa-6049c88b0c9a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489810180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.2489810180
Directory /workspace/17.uart_stress_all/latest

Test location /workspace/coverage/default/17.uart_stress_all_with_rand_reset.3385929601
Short name T1026
Test name
Test status
Simulation time 107191179164 ps
CPU time 517.85 seconds
Started Jun 06 12:59:04 PM PDT 24
Finished Jun 06 01:07:44 PM PDT 24
Peak memory 226732 kb
Host smart-539a6d66-4f6e-4457-b35d-5fd68261ffeb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385929601 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 17.uart_stress_all_with_rand_reset.3385929601
Directory /workspace/17.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.uart_tx_ovrd.1821151505
Short name T717
Test name
Test status
Simulation time 7464442969 ps
CPU time 14.5 seconds
Started Jun 06 12:59:06 PM PDT 24
Finished Jun 06 12:59:22 PM PDT 24
Peak memory 200324 kb
Host smart-ce318884-55e8-44ed-9cfb-503ba06f3cbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821151505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.1821151505
Directory /workspace/17.uart_tx_ovrd/latest

Test location /workspace/coverage/default/17.uart_tx_rx.1656557051
Short name T1080
Test name
Test status
Simulation time 290439262763 ps
CPU time 60.13 seconds
Started Jun 06 12:59:02 PM PDT 24
Finished Jun 06 01:00:03 PM PDT 24
Peak memory 200296 kb
Host smart-2f68b941-f8b4-4375-93c2-bff2c430a0b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656557051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.1656557051
Directory /workspace/17.uart_tx_rx/latest

Test location /workspace/coverage/default/170.uart_fifo_reset.2880440700
Short name T586
Test name
Test status
Simulation time 102154194128 ps
CPU time 171.37 seconds
Started Jun 06 01:02:47 PM PDT 24
Finished Jun 06 01:05:39 PM PDT 24
Peak memory 200284 kb
Host smart-0635eda1-7ebf-4eb6-8247-edb7e7ba8864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880440700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.2880440700
Directory /workspace/170.uart_fifo_reset/latest

Test location /workspace/coverage/default/172.uart_fifo_reset.3765133489
Short name T252
Test name
Test status
Simulation time 25720567026 ps
CPU time 39.06 seconds
Started Jun 06 01:02:52 PM PDT 24
Finished Jun 06 01:03:32 PM PDT 24
Peak memory 200084 kb
Host smart-897c8313-7fb5-40ae-b70c-56b9ab67e97a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765133489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.3765133489
Directory /workspace/172.uart_fifo_reset/latest

Test location /workspace/coverage/default/173.uart_fifo_reset.2928720905
Short name T725
Test name
Test status
Simulation time 44798571790 ps
CPU time 71.82 seconds
Started Jun 06 01:02:51 PM PDT 24
Finished Jun 06 01:04:03 PM PDT 24
Peak memory 200392 kb
Host smart-3ba762a8-52a8-44bc-90e3-6da7f09da612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928720905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.2928720905
Directory /workspace/173.uart_fifo_reset/latest

Test location /workspace/coverage/default/175.uart_fifo_reset.781431834
Short name T215
Test name
Test status
Simulation time 64471271182 ps
CPU time 56.83 seconds
Started Jun 06 01:03:01 PM PDT 24
Finished Jun 06 01:03:59 PM PDT 24
Peak memory 200052 kb
Host smart-0b2d4506-f8e1-443d-a2d0-95170640fe8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781431834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.781431834
Directory /workspace/175.uart_fifo_reset/latest

Test location /workspace/coverage/default/176.uart_fifo_reset.3021943948
Short name T802
Test name
Test status
Simulation time 116343797446 ps
CPU time 187.47 seconds
Started Jun 06 01:03:00 PM PDT 24
Finished Jun 06 01:06:08 PM PDT 24
Peak memory 200336 kb
Host smart-90e00779-1101-4397-bca2-45169634fdb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021943948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.3021943948
Directory /workspace/176.uart_fifo_reset/latest

Test location /workspace/coverage/default/177.uart_fifo_reset.2881468604
Short name T864
Test name
Test status
Simulation time 148761007004 ps
CPU time 121 seconds
Started Jun 06 01:03:01 PM PDT 24
Finished Jun 06 01:05:03 PM PDT 24
Peak memory 200240 kb
Host smart-cb977177-c2ad-4429-a210-19a978730513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881468604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.2881468604
Directory /workspace/177.uart_fifo_reset/latest

Test location /workspace/coverage/default/178.uart_fifo_reset.3195326016
Short name T921
Test name
Test status
Simulation time 24246241396 ps
CPU time 10.8 seconds
Started Jun 06 01:02:59 PM PDT 24
Finished Jun 06 01:03:11 PM PDT 24
Peak memory 200376 kb
Host smart-bed21d15-ea58-464e-9dfa-2ee484bcb897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195326016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.3195326016
Directory /workspace/178.uart_fifo_reset/latest

Test location /workspace/coverage/default/179.uart_fifo_reset.151195576
Short name T185
Test name
Test status
Simulation time 172483520275 ps
CPU time 105.09 seconds
Started Jun 06 01:03:01 PM PDT 24
Finished Jun 06 01:04:47 PM PDT 24
Peak memory 200372 kb
Host smart-df18440c-b8a9-47d1-a166-30d622dc64bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151195576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.151195576
Directory /workspace/179.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_alert_test.2783420224
Short name T379
Test name
Test status
Simulation time 16286672 ps
CPU time 0.59 seconds
Started Jun 06 12:59:09 PM PDT 24
Finished Jun 06 12:59:11 PM PDT 24
Peak memory 196028 kb
Host smart-5db17163-1da6-45a1-8bdd-43c184815b4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783420224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.2783420224
Directory /workspace/18.uart_alert_test/latest

Test location /workspace/coverage/default/18.uart_fifo_full.977614611
Short name T308
Test name
Test status
Simulation time 131391797841 ps
CPU time 46.05 seconds
Started Jun 06 12:59:04 PM PDT 24
Finished Jun 06 12:59:51 PM PDT 24
Peak memory 200364 kb
Host smart-76c275b7-8c99-4b54-944f-e754ff826d15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977614611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.977614611
Directory /workspace/18.uart_fifo_full/latest

Test location /workspace/coverage/default/18.uart_fifo_overflow.3187780787
Short name T709
Test name
Test status
Simulation time 155406225772 ps
CPU time 63.6 seconds
Started Jun 06 12:59:04 PM PDT 24
Finished Jun 06 01:00:09 PM PDT 24
Peak memory 200308 kb
Host smart-b20e8238-a903-4a44-ba98-cdc76858fcf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187780787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.3187780787
Directory /workspace/18.uart_fifo_overflow/latest

Test location /workspace/coverage/default/18.uart_fifo_reset.3876855681
Short name T794
Test name
Test status
Simulation time 79936247289 ps
CPU time 23.11 seconds
Started Jun 06 12:59:06 PM PDT 24
Finished Jun 06 12:59:31 PM PDT 24
Peak memory 200364 kb
Host smart-7bf5f81f-7fdb-4a99-b40b-2239365e9f93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876855681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.3876855681
Directory /workspace/18.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_intr.2362591096
Short name T129
Test name
Test status
Simulation time 30307688147 ps
CPU time 13.44 seconds
Started Jun 06 12:59:08 PM PDT 24
Finished Jun 06 12:59:23 PM PDT 24
Peak memory 200276 kb
Host smart-8335e0b0-8b5c-4001-b120-6751b3af9fc2
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362591096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.2362591096
Directory /workspace/18.uart_intr/latest

Test location /workspace/coverage/default/18.uart_long_xfer_wo_dly.192708998
Short name T551
Test name
Test status
Simulation time 264238447150 ps
CPU time 210.92 seconds
Started Jun 06 12:59:06 PM PDT 24
Finished Jun 06 01:02:39 PM PDT 24
Peak memory 200376 kb
Host smart-b8490ef0-ffcc-4623-b3d3-e9bfc286a5d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=192708998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.192708998
Directory /workspace/18.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/18.uart_loopback.2905012752
Short name T637
Test name
Test status
Simulation time 1689720745 ps
CPU time 2.16 seconds
Started Jun 06 12:59:07 PM PDT 24
Finished Jun 06 12:59:11 PM PDT 24
Peak memory 199076 kb
Host smart-491657a5-af4f-448c-89b6-5e1b6191522a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905012752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_loopback.2905012752
Directory /workspace/18.uart_loopback/latest

Test location /workspace/coverage/default/18.uart_noise_filter.2425626084
Short name T1059
Test name
Test status
Simulation time 29040728301 ps
CPU time 44.24 seconds
Started Jun 06 12:59:06 PM PDT 24
Finished Jun 06 12:59:52 PM PDT 24
Peak memory 199520 kb
Host smart-6d3f4e93-458d-4552-a4b0-4c558eede9e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425626084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_noise_filter.2425626084
Directory /workspace/18.uart_noise_filter/latest

Test location /workspace/coverage/default/18.uart_perf.4213412618
Short name T1070
Test name
Test status
Simulation time 23320869678 ps
CPU time 1068.97 seconds
Started Jun 06 12:59:07 PM PDT 24
Finished Jun 06 01:16:58 PM PDT 24
Peak memory 200188 kb
Host smart-826d8cc2-c655-49d0-bf54-9778b4ddef8d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4213412618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.4213412618
Directory /workspace/18.uart_perf/latest

Test location /workspace/coverage/default/18.uart_rx_oversample.2465714579
Short name T400
Test name
Test status
Simulation time 5898971949 ps
CPU time 46.52 seconds
Started Jun 06 12:59:10 PM PDT 24
Finished Jun 06 12:59:57 PM PDT 24
Peak memory 198364 kb
Host smart-9210b2e0-ea8a-4b26-b71f-e968ec4318cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2465714579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.2465714579
Directory /workspace/18.uart_rx_oversample/latest

Test location /workspace/coverage/default/18.uart_rx_parity_err.1965046105
Short name T981
Test name
Test status
Simulation time 125336964975 ps
CPU time 54.17 seconds
Started Jun 06 12:59:06 PM PDT 24
Finished Jun 06 01:00:02 PM PDT 24
Peak memory 200288 kb
Host smart-a9b6ae5d-5882-4261-a075-22752c7c2d6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965046105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.1965046105
Directory /workspace/18.uart_rx_parity_err/latest

Test location /workspace/coverage/default/18.uart_rx_start_bit_filter.2837186940
Short name T313
Test name
Test status
Simulation time 41098449845 ps
CPU time 15.69 seconds
Started Jun 06 12:59:07 PM PDT 24
Finished Jun 06 12:59:25 PM PDT 24
Peak memory 196512 kb
Host smart-0dbce773-9370-4b47-a567-e11d9472ecac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837186940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.2837186940
Directory /workspace/18.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/18.uart_smoke.2927165173
Short name T627
Test name
Test status
Simulation time 685459034 ps
CPU time 1.64 seconds
Started Jun 06 12:59:04 PM PDT 24
Finished Jun 06 12:59:06 PM PDT 24
Peak memory 198708 kb
Host smart-d41d7d04-31be-4d88-b29f-3f2de7c2f0db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927165173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_smoke.2927165173
Directory /workspace/18.uart_smoke/latest

Test location /workspace/coverage/default/18.uart_stress_all.3384680132
Short name T632
Test name
Test status
Simulation time 436193894154 ps
CPU time 1076.43 seconds
Started Jun 06 12:59:08 PM PDT 24
Finished Jun 06 01:17:06 PM PDT 24
Peak memory 200344 kb
Host smart-982bf838-e838-41e2-8932-b55f576c9a38
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384680132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.3384680132
Directory /workspace/18.uart_stress_all/latest

Test location /workspace/coverage/default/18.uart_stress_all_with_rand_reset.1143072881
Short name T64
Test name
Test status
Simulation time 82231622729 ps
CPU time 670.38 seconds
Started Jun 06 12:59:05 PM PDT 24
Finished Jun 06 01:10:16 PM PDT 24
Peak memory 217096 kb
Host smart-edb14505-5d95-487a-813d-37af782103d4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143072881 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 18.uart_stress_all_with_rand_reset.1143072881
Directory /workspace/18.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.uart_tx_ovrd.3616089222
Short name T488
Test name
Test status
Simulation time 7011621172 ps
CPU time 10.35 seconds
Started Jun 06 12:59:06 PM PDT 24
Finished Jun 06 12:59:18 PM PDT 24
Peak memory 199796 kb
Host smart-df6bf846-caa1-45b2-8b23-33c2cab84f77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616089222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.3616089222
Directory /workspace/18.uart_tx_ovrd/latest

Test location /workspace/coverage/default/18.uart_tx_rx.606254447
Short name T1038
Test name
Test status
Simulation time 16305017750 ps
CPU time 14.53 seconds
Started Jun 06 12:59:05 PM PDT 24
Finished Jun 06 12:59:20 PM PDT 24
Peak memory 200344 kb
Host smart-409d9874-b164-4c41-a783-d2900bc024bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606254447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.606254447
Directory /workspace/18.uart_tx_rx/latest

Test location /workspace/coverage/default/180.uart_fifo_reset.1536280824
Short name T45
Test name
Test status
Simulation time 108476695865 ps
CPU time 131.19 seconds
Started Jun 06 01:02:59 PM PDT 24
Finished Jun 06 01:05:11 PM PDT 24
Peak memory 200260 kb
Host smart-7ec849ec-ae39-44f1-9a81-48a38d06747c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536280824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.1536280824
Directory /workspace/180.uart_fifo_reset/latest

Test location /workspace/coverage/default/181.uart_fifo_reset.2762631075
Short name T845
Test name
Test status
Simulation time 101723884177 ps
CPU time 84.32 seconds
Started Jun 06 01:03:00 PM PDT 24
Finished Jun 06 01:04:25 PM PDT 24
Peak memory 200392 kb
Host smart-e0c48af3-1478-4f75-a817-efcbc340e7c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762631075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.2762631075
Directory /workspace/181.uart_fifo_reset/latest

Test location /workspace/coverage/default/182.uart_fifo_reset.42510237
Short name T672
Test name
Test status
Simulation time 98298765166 ps
CPU time 139.88 seconds
Started Jun 06 01:03:00 PM PDT 24
Finished Jun 06 01:05:21 PM PDT 24
Peak memory 200376 kb
Host smart-a3d3688f-7647-4ddc-adcf-ed4bf9c26248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42510237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.42510237
Directory /workspace/182.uart_fifo_reset/latest

Test location /workspace/coverage/default/183.uart_fifo_reset.3888768254
Short name T1188
Test name
Test status
Simulation time 106637486461 ps
CPU time 177.16 seconds
Started Jun 06 01:02:58 PM PDT 24
Finished Jun 06 01:05:56 PM PDT 24
Peak memory 200132 kb
Host smart-b400fc4a-9361-4a73-a9f1-4bfc6782a88d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888768254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.3888768254
Directory /workspace/183.uart_fifo_reset/latest

Test location /workspace/coverage/default/184.uart_fifo_reset.3721546680
Short name T1
Test name
Test status
Simulation time 123339159054 ps
CPU time 28.2 seconds
Started Jun 06 01:02:58 PM PDT 24
Finished Jun 06 01:03:27 PM PDT 24
Peak memory 200388 kb
Host smart-3c361b14-0b14-4c8a-ade4-068db21f1968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721546680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.3721546680
Directory /workspace/184.uart_fifo_reset/latest

Test location /workspace/coverage/default/185.uart_fifo_reset.571242911
Short name T1001
Test name
Test status
Simulation time 48327366977 ps
CPU time 37 seconds
Started Jun 06 01:02:59 PM PDT 24
Finished Jun 06 01:03:37 PM PDT 24
Peak memory 199308 kb
Host smart-11be3698-b242-437d-97d5-79f3ceef115f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571242911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.571242911
Directory /workspace/185.uart_fifo_reset/latest

Test location /workspace/coverage/default/186.uart_fifo_reset.2960204191
Short name T1126
Test name
Test status
Simulation time 35015177874 ps
CPU time 76.12 seconds
Started Jun 06 01:03:00 PM PDT 24
Finished Jun 06 01:04:17 PM PDT 24
Peak memory 200388 kb
Host smart-84fdfaa9-1afa-460d-887b-179b7add4cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960204191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.2960204191
Directory /workspace/186.uart_fifo_reset/latest

Test location /workspace/coverage/default/187.uart_fifo_reset.1674091421
Short name T509
Test name
Test status
Simulation time 65797778090 ps
CPU time 421.69 seconds
Started Jun 06 01:03:03 PM PDT 24
Finished Jun 06 01:10:05 PM PDT 24
Peak memory 200376 kb
Host smart-718ac30d-e84d-421d-947b-8b976f202f9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674091421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.1674091421
Directory /workspace/187.uart_fifo_reset/latest

Test location /workspace/coverage/default/188.uart_fifo_reset.2671363508
Short name T13
Test name
Test status
Simulation time 82171005442 ps
CPU time 24.99 seconds
Started Jun 06 01:02:59 PM PDT 24
Finished Jun 06 01:03:25 PM PDT 24
Peak memory 200300 kb
Host smart-65d545ba-74d1-4718-b59e-e1a8dc9e965d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671363508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.2671363508
Directory /workspace/188.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_alert_test.2232195688
Short name T755
Test name
Test status
Simulation time 12506918 ps
CPU time 0.55 seconds
Started Jun 06 12:59:11 PM PDT 24
Finished Jun 06 12:59:13 PM PDT 24
Peak memory 195740 kb
Host smart-cb68b59c-6b10-419b-b5cb-87304c07ffd1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232195688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.2232195688
Directory /workspace/19.uart_alert_test/latest

Test location /workspace/coverage/default/19.uart_fifo_full.936081981
Short name T300
Test name
Test status
Simulation time 110746331439 ps
CPU time 120.15 seconds
Started Jun 06 12:59:08 PM PDT 24
Finished Jun 06 01:01:10 PM PDT 24
Peak memory 200212 kb
Host smart-9aaa8a8a-25e6-4ef0-8374-428ee96f9e1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936081981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.936081981
Directory /workspace/19.uart_fifo_full/latest

Test location /workspace/coverage/default/19.uart_fifo_overflow.2581113964
Short name T690
Test name
Test status
Simulation time 23398846242 ps
CPU time 22.27 seconds
Started Jun 06 12:59:07 PM PDT 24
Finished Jun 06 12:59:31 PM PDT 24
Peak memory 200304 kb
Host smart-8aaa56ac-9fa3-48ec-a5ec-8ac5907d99e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581113964 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.2581113964
Directory /workspace/19.uart_fifo_overflow/latest

Test location /workspace/coverage/default/19.uart_fifo_reset.3743062533
Short name T211
Test name
Test status
Simulation time 11473155397 ps
CPU time 17.59 seconds
Started Jun 06 12:59:08 PM PDT 24
Finished Jun 06 12:59:28 PM PDT 24
Peak memory 200268 kb
Host smart-f652b8bd-c056-46b2-8958-6481ae365e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743062533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.3743062533
Directory /workspace/19.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_intr.2480811863
Short name T775
Test name
Test status
Simulation time 65280950849 ps
CPU time 108.37 seconds
Started Jun 06 12:59:10 PM PDT 24
Finished Jun 06 01:01:00 PM PDT 24
Peak memory 200260 kb
Host smart-0ef379a6-a84a-42e7-bc4f-9b122e1c0441
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480811863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.2480811863
Directory /workspace/19.uart_intr/latest

Test location /workspace/coverage/default/19.uart_long_xfer_wo_dly.2242123075
Short name T568
Test name
Test status
Simulation time 72612014512 ps
CPU time 424.34 seconds
Started Jun 06 12:59:13 PM PDT 24
Finished Jun 06 01:06:19 PM PDT 24
Peak memory 200656 kb
Host smart-df01a078-715f-459f-bae2-8a81ff90d425
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2242123075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.2242123075
Directory /workspace/19.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/19.uart_loopback.2464072600
Short name T1181
Test name
Test status
Simulation time 805642307 ps
CPU time 1.49 seconds
Started Jun 06 12:59:11 PM PDT 24
Finished Jun 06 12:59:14 PM PDT 24
Peak memory 198788 kb
Host smart-2bb95c30-1d78-407a-96b2-e202a6a7983d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464072600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_loopback.2464072600
Directory /workspace/19.uart_loopback/latest

Test location /workspace/coverage/default/19.uart_noise_filter.3577983962
Short name T1159
Test name
Test status
Simulation time 147204843279 ps
CPU time 16.94 seconds
Started Jun 06 12:59:12 PM PDT 24
Finished Jun 06 12:59:31 PM PDT 24
Peak memory 200556 kb
Host smart-c8b1eee6-d085-4608-a6b9-3694f758ac7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577983962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_noise_filter.3577983962
Directory /workspace/19.uart_noise_filter/latest

Test location /workspace/coverage/default/19.uart_perf.1091175976
Short name T959
Test name
Test status
Simulation time 7567248579 ps
CPU time 132.27 seconds
Started Jun 06 12:59:10 PM PDT 24
Finished Jun 06 01:01:24 PM PDT 24
Peak memory 200392 kb
Host smart-08842e0e-5b53-4239-99e4-45e013ae6496
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1091175976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.1091175976
Directory /workspace/19.uart_perf/latest

Test location /workspace/coverage/default/19.uart_rx_oversample.245282758
Short name T1066
Test name
Test status
Simulation time 6234302420 ps
CPU time 57.86 seconds
Started Jun 06 12:59:08 PM PDT 24
Finished Jun 06 01:00:08 PM PDT 24
Peak memory 199180 kb
Host smart-42f219f5-b6dd-42eb-848d-20f8e64845bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=245282758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.245282758
Directory /workspace/19.uart_rx_oversample/latest

Test location /workspace/coverage/default/19.uart_rx_parity_err.459384841
Short name T697
Test name
Test status
Simulation time 21182015179 ps
CPU time 12.77 seconds
Started Jun 06 12:59:12 PM PDT 24
Finished Jun 06 12:59:26 PM PDT 24
Peak memory 199956 kb
Host smart-1c2e79a3-4aef-497b-9d1b-7ff38113908f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459384841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.459384841
Directory /workspace/19.uart_rx_parity_err/latest

Test location /workspace/coverage/default/19.uart_rx_start_bit_filter.580860255
Short name T468
Test name
Test status
Simulation time 4879250409 ps
CPU time 4.18 seconds
Started Jun 06 12:59:11 PM PDT 24
Finished Jun 06 12:59:17 PM PDT 24
Peak memory 196564 kb
Host smart-822ea043-02b8-45b8-9cbd-8fd2e6a2547c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580860255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.580860255
Directory /workspace/19.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/19.uart_smoke.3769973662
Short name T974
Test name
Test status
Simulation time 864915840 ps
CPU time 3.37 seconds
Started Jun 06 12:59:07 PM PDT 24
Finished Jun 06 12:59:13 PM PDT 24
Peak memory 199228 kb
Host smart-c209db69-fd88-4d22-a0d4-757acee4dcd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769973662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_smoke.3769973662
Directory /workspace/19.uart_smoke/latest

Test location /workspace/coverage/default/19.uart_stress_all.830936163
Short name T810
Test name
Test status
Simulation time 209530597339 ps
CPU time 342.69 seconds
Started Jun 06 12:59:12 PM PDT 24
Finished Jun 06 01:04:57 PM PDT 24
Peak memory 208648 kb
Host smart-284b5b00-71a3-4561-9599-d7b4fa01d312
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830936163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.830936163
Directory /workspace/19.uart_stress_all/latest

Test location /workspace/coverage/default/19.uart_stress_all_with_rand_reset.3347905794
Short name T892
Test name
Test status
Simulation time 76924679652 ps
CPU time 393.57 seconds
Started Jun 06 12:59:12 PM PDT 24
Finished Jun 06 01:05:47 PM PDT 24
Peak memory 217152 kb
Host smart-de600641-1a9b-4a51-b8fa-6f68408b984e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347905794 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 19.uart_stress_all_with_rand_reset.3347905794
Directory /workspace/19.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.uart_tx_ovrd.3204843090
Short name T269
Test name
Test status
Simulation time 2688184512 ps
CPU time 2.83 seconds
Started Jun 06 12:59:12 PM PDT 24
Finished Jun 06 12:59:16 PM PDT 24
Peak memory 200200 kb
Host smart-39038299-b3e2-44ed-84f8-f9634024c3fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204843090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.3204843090
Directory /workspace/19.uart_tx_ovrd/latest

Test location /workspace/coverage/default/19.uart_tx_rx.3871691113
Short name T1137
Test name
Test status
Simulation time 123236290740 ps
CPU time 67.92 seconds
Started Jun 06 12:59:07 PM PDT 24
Finished Jun 06 01:00:16 PM PDT 24
Peak memory 200268 kb
Host smart-48638296-ec92-4ee2-ba23-55219eb07f2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871691113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.3871691113
Directory /workspace/19.uart_tx_rx/latest

Test location /workspace/coverage/default/190.uart_fifo_reset.724429108
Short name T251
Test name
Test status
Simulation time 143627004269 ps
CPU time 66.35 seconds
Started Jun 06 01:03:01 PM PDT 24
Finished Jun 06 01:04:08 PM PDT 24
Peak memory 200320 kb
Host smart-c8351347-c4d1-49f5-8a84-980d2f6d205f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724429108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.724429108
Directory /workspace/190.uart_fifo_reset/latest

Test location /workspace/coverage/default/191.uart_fifo_reset.2652399165
Short name T322
Test name
Test status
Simulation time 94510993688 ps
CPU time 36.39 seconds
Started Jun 06 01:03:02 PM PDT 24
Finished Jun 06 01:03:39 PM PDT 24
Peak memory 200312 kb
Host smart-a833b4c5-db26-4795-80c5-5e38c2edfdcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652399165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.2652399165
Directory /workspace/191.uart_fifo_reset/latest

Test location /workspace/coverage/default/192.uart_fifo_reset.1060139538
Short name T762
Test name
Test status
Simulation time 211697955445 ps
CPU time 182.57 seconds
Started Jun 06 01:03:00 PM PDT 24
Finished Jun 06 01:06:04 PM PDT 24
Peak memory 200144 kb
Host smart-b0248672-e78e-41e1-88cd-b42f573253d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060139538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.1060139538
Directory /workspace/192.uart_fifo_reset/latest

Test location /workspace/coverage/default/193.uart_fifo_reset.3864904019
Short name T1153
Test name
Test status
Simulation time 70468805916 ps
CPU time 35.26 seconds
Started Jun 06 01:03:01 PM PDT 24
Finished Jun 06 01:03:37 PM PDT 24
Peak memory 200276 kb
Host smart-494688e5-601b-400d-8b0b-179807a49c80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864904019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.3864904019
Directory /workspace/193.uart_fifo_reset/latest

Test location /workspace/coverage/default/195.uart_fifo_reset.4228651162
Short name T1031
Test name
Test status
Simulation time 57054000833 ps
CPU time 17.84 seconds
Started Jun 06 01:03:01 PM PDT 24
Finished Jun 06 01:03:20 PM PDT 24
Peak memory 200564 kb
Host smart-aea2cf05-6498-409e-9376-e7dd3a44f830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228651162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.4228651162
Directory /workspace/195.uart_fifo_reset/latest

Test location /workspace/coverage/default/196.uart_fifo_reset.1535136858
Short name T733
Test name
Test status
Simulation time 34607006569 ps
CPU time 31.55 seconds
Started Jun 06 01:03:00 PM PDT 24
Finished Jun 06 01:03:33 PM PDT 24
Peak memory 200336 kb
Host smart-353e5131-718c-4938-ac6a-76bd71c2c760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535136858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.1535136858
Directory /workspace/196.uart_fifo_reset/latest

Test location /workspace/coverage/default/199.uart_fifo_reset.4255575677
Short name T1171
Test name
Test status
Simulation time 139742556593 ps
CPU time 218.3 seconds
Started Jun 06 01:03:11 PM PDT 24
Finished Jun 06 01:06:50 PM PDT 24
Peak memory 200252 kb
Host smart-40172204-29cf-4a82-915d-142fa50dd786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255575677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.4255575677
Directory /workspace/199.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_alert_test.1308334041
Short name T1035
Test name
Test status
Simulation time 13238024 ps
CPU time 0.54 seconds
Started Jun 06 12:58:05 PM PDT 24
Finished Jun 06 12:58:07 PM PDT 24
Peak memory 195152 kb
Host smart-a308ada0-a428-4cf4-af0d-a91cd9367602
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308334041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.1308334041
Directory /workspace/2.uart_alert_test/latest

Test location /workspace/coverage/default/2.uart_fifo_full.2140199397
Short name T1085
Test name
Test status
Simulation time 124939010595 ps
CPU time 105.63 seconds
Started Jun 06 12:58:00 PM PDT 24
Finished Jun 06 12:59:47 PM PDT 24
Peak memory 200228 kb
Host smart-36b5c95c-40f5-4f1d-a82f-bd540c989510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140199397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.2140199397
Directory /workspace/2.uart_fifo_full/latest

Test location /workspace/coverage/default/2.uart_fifo_overflow.3480097786
Short name T857
Test name
Test status
Simulation time 102924336939 ps
CPU time 117.35 seconds
Started Jun 06 12:58:01 PM PDT 24
Finished Jun 06 12:59:59 PM PDT 24
Peak memory 200352 kb
Host smart-4e066a30-aaf2-4903-bd23-e229671e24c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480097786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.3480097786
Directory /workspace/2.uart_fifo_overflow/latest

Test location /workspace/coverage/default/2.uart_intr.936005513
Short name T698
Test name
Test status
Simulation time 10017002314 ps
CPU time 25.77 seconds
Started Jun 06 12:58:02 PM PDT 24
Finished Jun 06 12:58:29 PM PDT 24
Peak memory 200332 kb
Host smart-092b50ab-9a92-4bf3-9ec4-6b06bac19294
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936005513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.936005513
Directory /workspace/2.uart_intr/latest

Test location /workspace/coverage/default/2.uart_long_xfer_wo_dly.2499155592
Short name T787
Test name
Test status
Simulation time 134675459041 ps
CPU time 940.58 seconds
Started Jun 06 12:58:03 PM PDT 24
Finished Jun 06 01:13:45 PM PDT 24
Peak memory 200380 kb
Host smart-6c3b21fa-e77f-48d9-a090-fda219a34adc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2499155592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.2499155592
Directory /workspace/2.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/2.uart_loopback.954233983
Short name T364
Test name
Test status
Simulation time 5775041659 ps
CPU time 14.53 seconds
Started Jun 06 12:58:05 PM PDT 24
Finished Jun 06 12:58:21 PM PDT 24
Peak memory 198828 kb
Host smart-926a864e-e3b2-4fe4-bc13-2dc52b8c291e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954233983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_loopback.954233983
Directory /workspace/2.uart_loopback/latest

Test location /workspace/coverage/default/2.uart_noise_filter.3050345537
Short name T533
Test name
Test status
Simulation time 38446775422 ps
CPU time 57.92 seconds
Started Jun 06 12:58:04 PM PDT 24
Finished Jun 06 12:59:03 PM PDT 24
Peak memory 200568 kb
Host smart-2eb5e40c-bd48-43c7-a9e3-842a9f3822d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050345537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_noise_filter.3050345537
Directory /workspace/2.uart_noise_filter/latest

Test location /workspace/coverage/default/2.uart_perf.3411521384
Short name T596
Test name
Test status
Simulation time 6171963383 ps
CPU time 337.35 seconds
Started Jun 06 12:58:07 PM PDT 24
Finished Jun 06 01:03:45 PM PDT 24
Peak memory 200356 kb
Host smart-8b832121-dfca-4cb5-9c24-8b216961e38d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3411521384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.3411521384
Directory /workspace/2.uart_perf/latest

Test location /workspace/coverage/default/2.uart_rx_oversample.1598500727
Short name T483
Test name
Test status
Simulation time 4965863682 ps
CPU time 12.14 seconds
Started Jun 06 12:58:06 PM PDT 24
Finished Jun 06 12:58:19 PM PDT 24
Peak memory 200364 kb
Host smart-32db822a-5098-421c-a028-1cabf7561b7c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1598500727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.1598500727
Directory /workspace/2.uart_rx_oversample/latest

Test location /workspace/coverage/default/2.uart_rx_parity_err.2469796868
Short name T907
Test name
Test status
Simulation time 45258343090 ps
CPU time 103.91 seconds
Started Jun 06 12:58:01 PM PDT 24
Finished Jun 06 12:59:46 PM PDT 24
Peak memory 200264 kb
Host smart-9e0fd06a-c102-4294-9a82-12f5a80b5978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469796868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.2469796868
Directory /workspace/2.uart_rx_parity_err/latest

Test location /workspace/coverage/default/2.uart_rx_start_bit_filter.906503554
Short name T26
Test name
Test status
Simulation time 1964263696 ps
CPU time 1.15 seconds
Started Jun 06 12:58:00 PM PDT 24
Finished Jun 06 12:58:02 PM PDT 24
Peak memory 195712 kb
Host smart-aa86d3b9-2a33-4486-a15c-66259ec44560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906503554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.906503554
Directory /workspace/2.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/2.uart_sec_cm.1752264210
Short name T31
Test name
Test status
Simulation time 37335262 ps
CPU time 0.79 seconds
Started Jun 06 12:58:02 PM PDT 24
Finished Jun 06 12:58:04 PM PDT 24
Peak memory 218812 kb
Host smart-0a31536c-2bc5-400d-87f4-5855700bd44c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752264210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.1752264210
Directory /workspace/2.uart_sec_cm/latest

Test location /workspace/coverage/default/2.uart_smoke.606123754
Short name T742
Test name
Test status
Simulation time 1009350628 ps
CPU time 1.32 seconds
Started Jun 06 12:58:01 PM PDT 24
Finished Jun 06 12:58:04 PM PDT 24
Peak memory 198852 kb
Host smart-58f03de6-496e-4af4-a987-fb0e5b4945f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606123754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_smoke.606123754
Directory /workspace/2.uart_smoke/latest

Test location /workspace/coverage/default/2.uart_stress_all.1710376720
Short name T24
Test name
Test status
Simulation time 24722500270 ps
CPU time 20.83 seconds
Started Jun 06 12:58:04 PM PDT 24
Finished Jun 06 12:58:26 PM PDT 24
Peak memory 200268 kb
Host smart-e60dba98-fc29-406d-80d6-fe0681ba2a79
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710376720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.1710376720
Directory /workspace/2.uart_stress_all/latest

Test location /workspace/coverage/default/2.uart_stress_all_with_rand_reset.530914160
Short name T923
Test name
Test status
Simulation time 70656097293 ps
CPU time 157.79 seconds
Started Jun 06 12:58:03 PM PDT 24
Finished Jun 06 01:00:42 PM PDT 24
Peak memory 217080 kb
Host smart-fea77ad2-dbc9-4ef8-8083-5dc107f20e3c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530914160 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 2.uart_stress_all_with_rand_reset.530914160
Directory /workspace/2.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.uart_tx_ovrd.1574497845
Short name T679
Test name
Test status
Simulation time 8004794250 ps
CPU time 10.5 seconds
Started Jun 06 12:58:05 PM PDT 24
Finished Jun 06 12:58:16 PM PDT 24
Peak memory 200032 kb
Host smart-aa700a00-01ea-4faa-a8a7-a7a610636058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574497845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.1574497845
Directory /workspace/2.uart_tx_ovrd/latest

Test location /workspace/coverage/default/2.uart_tx_rx.2366177964
Short name T793
Test name
Test status
Simulation time 31964689494 ps
CPU time 54.97 seconds
Started Jun 06 12:58:05 PM PDT 24
Finished Jun 06 12:59:01 PM PDT 24
Peak memory 200276 kb
Host smart-282d3e96-3813-40e8-a85a-4e9eab55d7af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366177964 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.2366177964
Directory /workspace/2.uart_tx_rx/latest

Test location /workspace/coverage/default/20.uart_alert_test.3339776977
Short name T720
Test name
Test status
Simulation time 31592667 ps
CPU time 0.54 seconds
Started Jun 06 12:59:13 PM PDT 24
Finished Jun 06 12:59:15 PM PDT 24
Peak memory 194676 kb
Host smart-b8b76c76-bcd7-4253-8aa1-d6caa83731f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339776977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.3339776977
Directory /workspace/20.uart_alert_test/latest

Test location /workspace/coverage/default/20.uart_fifo_full.3225229793
Short name T353
Test name
Test status
Simulation time 148380182088 ps
CPU time 139.84 seconds
Started Jun 06 12:59:13 PM PDT 24
Finished Jun 06 01:01:34 PM PDT 24
Peak memory 200276 kb
Host smart-6c3abdc9-4ede-4ac6-925f-1e9e4eb018f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225229793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.3225229793
Directory /workspace/20.uart_fifo_full/latest

Test location /workspace/coverage/default/20.uart_fifo_overflow.3678989993
Short name T623
Test name
Test status
Simulation time 56780187797 ps
CPU time 89.44 seconds
Started Jun 06 12:59:15 PM PDT 24
Finished Jun 06 01:00:47 PM PDT 24
Peak memory 200280 kb
Host smart-93480321-f827-42af-9cae-de276f4c155b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678989993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.3678989993
Directory /workspace/20.uart_fifo_overflow/latest

Test location /workspace/coverage/default/20.uart_fifo_reset.1371839326
Short name T44
Test name
Test status
Simulation time 23557886579 ps
CPU time 17.64 seconds
Started Jun 06 12:59:14 PM PDT 24
Finished Jun 06 12:59:33 PM PDT 24
Peak memory 200328 kb
Host smart-28321205-0f0f-4aec-955f-f5e931ae6f0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371839326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.1371839326
Directory /workspace/20.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_intr.1784216734
Short name T1050
Test name
Test status
Simulation time 276700506994 ps
CPU time 73.65 seconds
Started Jun 06 12:59:14 PM PDT 24
Finished Jun 06 01:00:29 PM PDT 24
Peak memory 200252 kb
Host smart-f05572b2-e84d-47b4-a5e7-98720755eb8a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784216734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.1784216734
Directory /workspace/20.uart_intr/latest

Test location /workspace/coverage/default/20.uart_long_xfer_wo_dly.4197054346
Short name T423
Test name
Test status
Simulation time 131965827019 ps
CPU time 383.98 seconds
Started Jun 06 12:59:14 PM PDT 24
Finished Jun 06 01:05:39 PM PDT 24
Peak memory 200304 kb
Host smart-40f4f87d-9dbb-4801-97f6-fde233495d29
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4197054346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.4197054346
Directory /workspace/20.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/20.uart_loopback.1541050298
Short name T1140
Test name
Test status
Simulation time 7143528765 ps
CPU time 10.99 seconds
Started Jun 06 12:59:13 PM PDT 24
Finished Jun 06 12:59:26 PM PDT 24
Peak memory 198948 kb
Host smart-20c45a9a-23b8-4089-929b-da3419be17f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541050298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_loopback.1541050298
Directory /workspace/20.uart_loopback/latest

Test location /workspace/coverage/default/20.uart_noise_filter.3732535909
Short name T115
Test name
Test status
Simulation time 133727765472 ps
CPU time 58.57 seconds
Started Jun 06 12:59:13 PM PDT 24
Finished Jun 06 01:00:14 PM PDT 24
Peak memory 200600 kb
Host smart-c91f3d80-93c7-4963-bcc2-483f855c6153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732535909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_noise_filter.3732535909
Directory /workspace/20.uart_noise_filter/latest

Test location /workspace/coverage/default/20.uart_perf.108015438
Short name T1185
Test name
Test status
Simulation time 8892770358 ps
CPU time 75.34 seconds
Started Jun 06 12:59:12 PM PDT 24
Finished Jun 06 01:00:29 PM PDT 24
Peak memory 200304 kb
Host smart-1710da46-2254-48f3-9922-49e859af6148
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=108015438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.108015438
Directory /workspace/20.uart_perf/latest

Test location /workspace/coverage/default/20.uart_rx_oversample.599716563
Short name T399
Test name
Test status
Simulation time 4627866991 ps
CPU time 2.61 seconds
Started Jun 06 12:59:14 PM PDT 24
Finished Jun 06 12:59:18 PM PDT 24
Peak memory 198484 kb
Host smart-25a9c646-c019-4ea8-bd00-2b2039745236
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=599716563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.599716563
Directory /workspace/20.uart_rx_oversample/latest

Test location /workspace/coverage/default/20.uart_rx_parity_err.1719229159
Short name T1105
Test name
Test status
Simulation time 18839138570 ps
CPU time 14.76 seconds
Started Jun 06 12:59:13 PM PDT 24
Finished Jun 06 12:59:30 PM PDT 24
Peak memory 200372 kb
Host smart-c5026d7a-6a36-4009-bb1d-3be1d14a0c42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719229159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.1719229159
Directory /workspace/20.uart_rx_parity_err/latest

Test location /workspace/coverage/default/20.uart_rx_start_bit_filter.3912464204
Short name T449
Test name
Test status
Simulation time 3457290490 ps
CPU time 3.38 seconds
Started Jun 06 12:59:24 PM PDT 24
Finished Jun 06 12:59:28 PM PDT 24
Peak memory 196344 kb
Host smart-bf6f56a9-68f1-4d40-b01f-2351cba047ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912464204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.3912464204
Directory /workspace/20.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/20.uart_smoke.143699798
Short name T1032
Test name
Test status
Simulation time 295406953 ps
CPU time 0.93 seconds
Started Jun 06 12:59:12 PM PDT 24
Finished Jun 06 12:59:15 PM PDT 24
Peak memory 198784 kb
Host smart-8198d603-6bf5-469a-895d-706b244b8fe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143699798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_smoke.143699798
Directory /workspace/20.uart_smoke/latest

Test location /workspace/coverage/default/20.uart_stress_all.2823167108
Short name T204
Test name
Test status
Simulation time 216660241754 ps
CPU time 398.46 seconds
Started Jun 06 12:59:16 PM PDT 24
Finished Jun 06 01:05:56 PM PDT 24
Peak memory 200264 kb
Host smart-4cce0bd1-062c-4bb4-9b9f-a96923580987
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823167108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.2823167108
Directory /workspace/20.uart_stress_all/latest

Test location /workspace/coverage/default/20.uart_stress_all_with_rand_reset.748275341
Short name T239
Test name
Test status
Simulation time 366117027566 ps
CPU time 764.74 seconds
Started Jun 06 12:59:16 PM PDT 24
Finished Jun 06 01:12:03 PM PDT 24
Peak memory 213320 kb
Host smart-5215a289-bee8-49d8-b32f-fa8c25584ac2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748275341 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 20.uart_stress_all_with_rand_reset.748275341
Directory /workspace/20.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.uart_tx_ovrd.3604121075
Short name T481
Test name
Test status
Simulation time 1091067156 ps
CPU time 3.74 seconds
Started Jun 06 12:59:12 PM PDT 24
Finished Jun 06 12:59:18 PM PDT 24
Peak memory 200164 kb
Host smart-83bf9646-a13d-4c97-9181-98885d90e0d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604121075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.3604121075
Directory /workspace/20.uart_tx_ovrd/latest

Test location /workspace/coverage/default/20.uart_tx_rx.2138531794
Short name T261
Test name
Test status
Simulation time 54944570207 ps
CPU time 60.51 seconds
Started Jun 06 12:59:12 PM PDT 24
Finished Jun 06 01:00:14 PM PDT 24
Peak memory 200300 kb
Host smart-13e27131-92b0-4754-9d8e-d39bea2bc6a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138531794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.2138531794
Directory /workspace/20.uart_tx_rx/latest

Test location /workspace/coverage/default/200.uart_fifo_reset.314527075
Short name T1020
Test name
Test status
Simulation time 52914990096 ps
CPU time 23.06 seconds
Started Jun 06 01:03:11 PM PDT 24
Finished Jun 06 01:03:35 PM PDT 24
Peak memory 200292 kb
Host smart-82282339-8b6e-4807-ad7d-d262630f67e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314527075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.314527075
Directory /workspace/200.uart_fifo_reset/latest

Test location /workspace/coverage/default/201.uart_fifo_reset.1436867339
Short name T801
Test name
Test status
Simulation time 13742582013 ps
CPU time 9.65 seconds
Started Jun 06 01:03:14 PM PDT 24
Finished Jun 06 01:03:24 PM PDT 24
Peak memory 200272 kb
Host smart-11f9ff31-4602-465d-8618-7434f9246860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436867339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.1436867339
Directory /workspace/201.uart_fifo_reset/latest

Test location /workspace/coverage/default/202.uart_fifo_reset.1684003636
Short name T312
Test name
Test status
Simulation time 3813945718 ps
CPU time 10.16 seconds
Started Jun 06 01:03:13 PM PDT 24
Finished Jun 06 01:03:24 PM PDT 24
Peak memory 200336 kb
Host smart-6fb856bb-d7d8-4e5e-bd6b-6cd94eeae7b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684003636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.1684003636
Directory /workspace/202.uart_fifo_reset/latest

Test location /workspace/coverage/default/203.uart_fifo_reset.98638920
Short name T212
Test name
Test status
Simulation time 339253438543 ps
CPU time 32.32 seconds
Started Jun 06 01:03:13 PM PDT 24
Finished Jun 06 01:03:46 PM PDT 24
Peak memory 200364 kb
Host smart-4ea33e3d-de96-48c7-9da4-2561219e0d1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98638920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.98638920
Directory /workspace/203.uart_fifo_reset/latest

Test location /workspace/coverage/default/204.uart_fifo_reset.3288002447
Short name T236
Test name
Test status
Simulation time 41040259026 ps
CPU time 100.53 seconds
Started Jun 06 01:03:14 PM PDT 24
Finished Jun 06 01:04:56 PM PDT 24
Peak memory 200352 kb
Host smart-162bbbcb-8e44-47fb-9b7e-a99f85720f96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288002447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.3288002447
Directory /workspace/204.uart_fifo_reset/latest

Test location /workspace/coverage/default/205.uart_fifo_reset.3935761453
Short name T327
Test name
Test status
Simulation time 188067673764 ps
CPU time 141.12 seconds
Started Jun 06 01:03:18 PM PDT 24
Finished Jun 06 01:05:40 PM PDT 24
Peak memory 200316 kb
Host smart-4bf6731b-e52a-4146-8a4b-9502cb8b3603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935761453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.3935761453
Directory /workspace/205.uart_fifo_reset/latest

Test location /workspace/coverage/default/206.uart_fifo_reset.2345634683
Short name T226
Test name
Test status
Simulation time 33187422945 ps
CPU time 13.95 seconds
Started Jun 06 01:03:12 PM PDT 24
Finished Jun 06 01:03:27 PM PDT 24
Peak memory 200244 kb
Host smart-100e63ad-ee65-48f1-b287-5ab29392b637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345634683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.2345634683
Directory /workspace/206.uart_fifo_reset/latest

Test location /workspace/coverage/default/207.uart_fifo_reset.525246132
Short name T126
Test name
Test status
Simulation time 169855904038 ps
CPU time 207.94 seconds
Started Jun 06 01:03:21 PM PDT 24
Finished Jun 06 01:06:49 PM PDT 24
Peak memory 200408 kb
Host smart-94d78f3a-5351-4270-b3fd-dcd1d615a1c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525246132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.525246132
Directory /workspace/207.uart_fifo_reset/latest

Test location /workspace/coverage/default/208.uart_fifo_reset.3337996272
Short name T824
Test name
Test status
Simulation time 54664848548 ps
CPU time 30.92 seconds
Started Jun 06 01:03:14 PM PDT 24
Finished Jun 06 01:03:46 PM PDT 24
Peak memory 200360 kb
Host smart-fb8aad56-acfe-491c-b3f6-1bc5cbd2f2e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337996272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.3337996272
Directory /workspace/208.uart_fifo_reset/latest

Test location /workspace/coverage/default/209.uart_fifo_reset.936300084
Short name T301
Test name
Test status
Simulation time 14900182944 ps
CPU time 38.35 seconds
Started Jun 06 01:03:13 PM PDT 24
Finished Jun 06 01:03:52 PM PDT 24
Peak memory 200236 kb
Host smart-92102d88-2ecf-4b7f-82e5-3e11110b0e69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936300084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.936300084
Directory /workspace/209.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_alert_test.2287985927
Short name T1150
Test name
Test status
Simulation time 26831748 ps
CPU time 0.55 seconds
Started Jun 06 12:59:25 PM PDT 24
Finished Jun 06 12:59:27 PM PDT 24
Peak memory 194720 kb
Host smart-3dbbfa73-9cc8-4a62-a61d-8d6dda640d17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287985927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.2287985927
Directory /workspace/21.uart_alert_test/latest

Test location /workspace/coverage/default/21.uart_fifo_full.4259404479
Short name T181
Test name
Test status
Simulation time 41829172832 ps
CPU time 14.16 seconds
Started Jun 06 12:59:14 PM PDT 24
Finished Jun 06 12:59:30 PM PDT 24
Peak memory 200284 kb
Host smart-7b8efbf0-656f-4a96-b249-55e5405e6fbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259404479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.4259404479
Directory /workspace/21.uart_fifo_full/latest

Test location /workspace/coverage/default/21.uart_fifo_overflow.3954518898
Short name T514
Test name
Test status
Simulation time 72096962966 ps
CPU time 38.59 seconds
Started Jun 06 12:59:14 PM PDT 24
Finished Jun 06 12:59:54 PM PDT 24
Peak memory 199868 kb
Host smart-62dae565-65a8-4020-8226-2d2dbad98f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954518898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.3954518898
Directory /workspace/21.uart_fifo_overflow/latest

Test location /workspace/coverage/default/21.uart_fifo_reset.498337512
Short name T192
Test name
Test status
Simulation time 84653655763 ps
CPU time 132.95 seconds
Started Jun 06 12:59:36 PM PDT 24
Finished Jun 06 01:01:50 PM PDT 24
Peak memory 200296 kb
Host smart-7426121d-b218-4afc-9280-db60e4dadb69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498337512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.498337512
Directory /workspace/21.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_intr.2333190363
Short name T944
Test name
Test status
Simulation time 58802110440 ps
CPU time 51.4 seconds
Started Jun 06 12:59:15 PM PDT 24
Finished Jun 06 01:00:08 PM PDT 24
Peak memory 200340 kb
Host smart-3713a751-2b40-4201-809d-fa26bc50f693
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333190363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.2333190363
Directory /workspace/21.uart_intr/latest

Test location /workspace/coverage/default/21.uart_long_xfer_wo_dly.33535251
Short name T1152
Test name
Test status
Simulation time 60801096220 ps
CPU time 335.11 seconds
Started Jun 06 12:59:22 PM PDT 24
Finished Jun 06 01:04:58 PM PDT 24
Peak memory 200240 kb
Host smart-c7702609-97e3-4fe8-89bf-77fccc001589
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=33535251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.33535251
Directory /workspace/21.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/21.uart_loopback.2890680542
Short name T369
Test name
Test status
Simulation time 448077388 ps
CPU time 1.81 seconds
Started Jun 06 12:59:26 PM PDT 24
Finished Jun 06 12:59:29 PM PDT 24
Peak memory 200136 kb
Host smart-67f1f718-83d7-4f6d-af74-9d81173c0c36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890680542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_loopback.2890680542
Directory /workspace/21.uart_loopback/latest

Test location /workspace/coverage/default/21.uart_noise_filter.3500395250
Short name T552
Test name
Test status
Simulation time 25028495207 ps
CPU time 17.8 seconds
Started Jun 06 12:59:15 PM PDT 24
Finished Jun 06 12:59:34 PM PDT 24
Peak memory 195008 kb
Host smart-e0de7fbe-eab2-4ebf-af25-8f229c69cd3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500395250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_noise_filter.3500395250
Directory /workspace/21.uart_noise_filter/latest

Test location /workspace/coverage/default/21.uart_perf.1232602061
Short name T1145
Test name
Test status
Simulation time 13126340921 ps
CPU time 627.33 seconds
Started Jun 06 12:59:27 PM PDT 24
Finished Jun 06 01:09:55 PM PDT 24
Peak memory 200360 kb
Host smart-d1b865d5-e116-4a00-947d-65fabde19335
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1232602061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.1232602061
Directory /workspace/21.uart_perf/latest

Test location /workspace/coverage/default/21.uart_rx_oversample.2336473975
Short name T676
Test name
Test status
Simulation time 2423883854 ps
CPU time 17.77 seconds
Started Jun 06 12:59:13 PM PDT 24
Finished Jun 06 12:59:33 PM PDT 24
Peak memory 198768 kb
Host smart-2ac9c66b-4697-4cdf-b39c-cfeadb37945b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2336473975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.2336473975
Directory /workspace/21.uart_rx_oversample/latest

Test location /workspace/coverage/default/21.uart_rx_parity_err.188307760
Short name T16
Test name
Test status
Simulation time 290113051353 ps
CPU time 263.04 seconds
Started Jun 06 12:59:15 PM PDT 24
Finished Jun 06 01:03:40 PM PDT 24
Peak memory 200316 kb
Host smart-0450901c-79ca-4164-bfed-608527f724c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188307760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.188307760
Directory /workspace/21.uart_rx_parity_err/latest

Test location /workspace/coverage/default/21.uart_rx_start_bit_filter.2690883086
Short name T500
Test name
Test status
Simulation time 3698822532 ps
CPU time 3.62 seconds
Started Jun 06 12:59:15 PM PDT 24
Finished Jun 06 12:59:21 PM PDT 24
Peak memory 196212 kb
Host smart-78102d13-fb4b-4034-96df-2761042cc57d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690883086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.2690883086
Directory /workspace/21.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/21.uart_smoke.3246610549
Short name T872
Test name
Test status
Simulation time 5341615938 ps
CPU time 20.67 seconds
Started Jun 06 12:59:17 PM PDT 24
Finished Jun 06 12:59:39 PM PDT 24
Peak memory 200052 kb
Host smart-57f2b3a4-8404-4acd-8a19-0b6b7d34926d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246610549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_smoke.3246610549
Directory /workspace/21.uart_smoke/latest

Test location /workspace/coverage/default/21.uart_stress_all_with_rand_reset.3129815073
Short name T963
Test name
Test status
Simulation time 70252780098 ps
CPU time 869.04 seconds
Started Jun 06 12:59:25 PM PDT 24
Finished Jun 06 01:13:56 PM PDT 24
Peak memory 225248 kb
Host smart-943d5ae3-a284-4268-9294-08faf1a8187a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129815073 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 21.uart_stress_all_with_rand_reset.3129815073
Directory /workspace/21.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.uart_tx_ovrd.834325414
Short name T821
Test name
Test status
Simulation time 740285169 ps
CPU time 1.1 seconds
Started Jun 06 12:59:31 PM PDT 24
Finished Jun 06 12:59:33 PM PDT 24
Peak memory 197284 kb
Host smart-2b17ff54-35f3-4b71-a98b-4f5e44a87872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834325414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.834325414
Directory /workspace/21.uart_tx_ovrd/latest

Test location /workspace/coverage/default/21.uart_tx_rx.3069170735
Short name T487
Test name
Test status
Simulation time 6256207583 ps
CPU time 12.61 seconds
Started Jun 06 12:59:17 PM PDT 24
Finished Jun 06 12:59:31 PM PDT 24
Peak memory 200248 kb
Host smart-a6d0f2b9-322a-4a87-8bd5-a58bac22018c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069170735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.3069170735
Directory /workspace/21.uart_tx_rx/latest

Test location /workspace/coverage/default/210.uart_fifo_reset.593086188
Short name T199
Test name
Test status
Simulation time 70705195022 ps
CPU time 52.27 seconds
Started Jun 06 01:03:13 PM PDT 24
Finished Jun 06 01:04:06 PM PDT 24
Peak memory 200324 kb
Host smart-34fbdba7-abe4-4f86-b980-b664a803d510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593086188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.593086188
Directory /workspace/210.uart_fifo_reset/latest

Test location /workspace/coverage/default/211.uart_fifo_reset.3249883133
Short name T127
Test name
Test status
Simulation time 22302126688 ps
CPU time 8.54 seconds
Started Jun 06 01:03:14 PM PDT 24
Finished Jun 06 01:03:23 PM PDT 24
Peak memory 200292 kb
Host smart-7ef230b8-135b-40f2-93e9-2546c100a07c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249883133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.3249883133
Directory /workspace/211.uart_fifo_reset/latest

Test location /workspace/coverage/default/212.uart_fifo_reset.122629165
Short name T257
Test name
Test status
Simulation time 24087394101 ps
CPU time 21.92 seconds
Started Jun 06 01:03:14 PM PDT 24
Finished Jun 06 01:03:37 PM PDT 24
Peak memory 200288 kb
Host smart-c61b6fdd-d312-4eeb-a919-e45427c65664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122629165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.122629165
Directory /workspace/212.uart_fifo_reset/latest

Test location /workspace/coverage/default/213.uart_fifo_reset.247427813
Short name T156
Test name
Test status
Simulation time 125023713409 ps
CPU time 423.53 seconds
Started Jun 06 01:03:15 PM PDT 24
Finished Jun 06 01:10:20 PM PDT 24
Peak memory 200336 kb
Host smart-b5e70e84-d999-48c7-b8ab-3d0c5e06700c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247427813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.247427813
Directory /workspace/213.uart_fifo_reset/latest

Test location /workspace/coverage/default/214.uart_fifo_reset.953227278
Short name T490
Test name
Test status
Simulation time 89444797943 ps
CPU time 127.43 seconds
Started Jun 06 01:03:14 PM PDT 24
Finished Jun 06 01:05:22 PM PDT 24
Peak memory 200372 kb
Host smart-3e3ebb78-7409-4918-93e1-ce375b9b087c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953227278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.953227278
Directory /workspace/214.uart_fifo_reset/latest

Test location /workspace/coverage/default/216.uart_fifo_reset.1292802661
Short name T1158
Test name
Test status
Simulation time 18672460861 ps
CPU time 42.77 seconds
Started Jun 06 01:03:27 PM PDT 24
Finished Jun 06 01:04:11 PM PDT 24
Peak memory 200300 kb
Host smart-52d390ad-5e9c-4968-a333-c905830da004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292802661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.1292802661
Directory /workspace/216.uart_fifo_reset/latest

Test location /workspace/coverage/default/217.uart_fifo_reset.4245004345
Short name T1014
Test name
Test status
Simulation time 13697840565 ps
CPU time 14.13 seconds
Started Jun 06 01:03:26 PM PDT 24
Finished Jun 06 01:03:42 PM PDT 24
Peak memory 200284 kb
Host smart-dabe1a30-e72a-4447-9310-7ecf6c8f436f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245004345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.4245004345
Directory /workspace/217.uart_fifo_reset/latest

Test location /workspace/coverage/default/218.uart_fifo_reset.984507053
Short name T859
Test name
Test status
Simulation time 21794083480 ps
CPU time 37.41 seconds
Started Jun 06 01:03:26 PM PDT 24
Finished Jun 06 01:04:05 PM PDT 24
Peak memory 200300 kb
Host smart-ded41890-0681-4938-a552-5e57f8c56945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984507053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.984507053
Directory /workspace/218.uart_fifo_reset/latest

Test location /workspace/coverage/default/219.uart_fifo_reset.356898286
Short name T774
Test name
Test status
Simulation time 156194196812 ps
CPU time 67.17 seconds
Started Jun 06 01:03:24 PM PDT 24
Finished Jun 06 01:04:32 PM PDT 24
Peak memory 200316 kb
Host smart-700e6c28-6050-4d1a-a0a5-7e3b0b72600f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356898286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.356898286
Directory /workspace/219.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_alert_test.1939397030
Short name T1065
Test name
Test status
Simulation time 20166349 ps
CPU time 0.54 seconds
Started Jun 06 12:59:28 PM PDT 24
Finished Jun 06 12:59:30 PM PDT 24
Peak memory 195688 kb
Host smart-c3fae1b2-b4ba-445c-9ea1-f60f4882e1a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939397030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.1939397030
Directory /workspace/22.uart_alert_test/latest

Test location /workspace/coverage/default/22.uart_fifo_full.3804909216
Short name T550
Test name
Test status
Simulation time 19854741839 ps
CPU time 29.87 seconds
Started Jun 06 12:59:23 PM PDT 24
Finished Jun 06 12:59:55 PM PDT 24
Peak memory 200296 kb
Host smart-a519dc41-1d86-4263-b44f-3ff1346968b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804909216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.3804909216
Directory /workspace/22.uart_fifo_full/latest

Test location /workspace/coverage/default/22.uart_fifo_overflow.3565386055
Short name T878
Test name
Test status
Simulation time 42494669334 ps
CPU time 26.29 seconds
Started Jun 06 12:59:24 PM PDT 24
Finished Jun 06 12:59:52 PM PDT 24
Peak memory 200348 kb
Host smart-11fbc133-1ede-44ca-a764-a51a95dd7d4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565386055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.3565386055
Directory /workspace/22.uart_fifo_overflow/latest

Test location /workspace/coverage/default/22.uart_fifo_reset.2633313150
Short name T262
Test name
Test status
Simulation time 28622326836 ps
CPU time 48.5 seconds
Started Jun 06 12:59:25 PM PDT 24
Finished Jun 06 01:00:15 PM PDT 24
Peak memory 200364 kb
Host smart-fd3f15a8-3d34-4114-8c55-7b3557faa058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633313150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.2633313150
Directory /workspace/22.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_intr.2933912780
Short name T443
Test name
Test status
Simulation time 14627854052 ps
CPU time 14.42 seconds
Started Jun 06 12:59:25 PM PDT 24
Finished Jun 06 12:59:41 PM PDT 24
Peak memory 200184 kb
Host smart-43ffe081-ca02-4496-b84f-4e0e9a8abd93
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933912780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.2933912780
Directory /workspace/22.uart_intr/latest

Test location /workspace/coverage/default/22.uart_long_xfer_wo_dly.2042696975
Short name T659
Test name
Test status
Simulation time 74191058385 ps
CPU time 200.66 seconds
Started Jun 06 12:59:25 PM PDT 24
Finished Jun 06 01:02:47 PM PDT 24
Peak memory 200200 kb
Host smart-3816fe57-ebac-4412-9fbb-559efc287140
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2042696975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.2042696975
Directory /workspace/22.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/22.uart_loopback.905537380
Short name T80
Test name
Test status
Simulation time 3784894799 ps
CPU time 2.87 seconds
Started Jun 06 12:59:30 PM PDT 24
Finished Jun 06 12:59:35 PM PDT 24
Peak memory 198164 kb
Host smart-85b9405a-1b70-4c6d-96a1-b7d06422be5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905537380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_loopback.905537380
Directory /workspace/22.uart_loopback/latest

Test location /workspace/coverage/default/22.uart_noise_filter.1215821721
Short name T264
Test name
Test status
Simulation time 102778623117 ps
CPU time 180.09 seconds
Started Jun 06 12:59:27 PM PDT 24
Finished Jun 06 01:02:28 PM PDT 24
Peak memory 208796 kb
Host smart-9004a5f2-9b91-435e-92d8-000fdcdc3e9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215821721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_noise_filter.1215821721
Directory /workspace/22.uart_noise_filter/latest

Test location /workspace/coverage/default/22.uart_perf.2868008585
Short name T1166
Test name
Test status
Simulation time 16415620014 ps
CPU time 621.06 seconds
Started Jun 06 12:59:24 PM PDT 24
Finished Jun 06 01:09:46 PM PDT 24
Peak memory 200340 kb
Host smart-f66a63a8-3a71-4c1e-b42c-f0c1cfd80f1a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2868008585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.2868008585
Directory /workspace/22.uart_perf/latest

Test location /workspace/coverage/default/22.uart_rx_oversample.3586704877
Short name T683
Test name
Test status
Simulation time 3222048332 ps
CPU time 10.89 seconds
Started Jun 06 12:59:23 PM PDT 24
Finished Jun 06 12:59:35 PM PDT 24
Peak memory 198860 kb
Host smart-dbcda95b-9424-420c-b488-10ab69570181
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3586704877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.3586704877
Directory /workspace/22.uart_rx_oversample/latest

Test location /workspace/coverage/default/22.uart_rx_parity_err.3331869521
Short name T902
Test name
Test status
Simulation time 61308037234 ps
CPU time 58.75 seconds
Started Jun 06 12:59:28 PM PDT 24
Finished Jun 06 01:00:28 PM PDT 24
Peak memory 200376 kb
Host smart-33ca6411-b1b4-4107-b721-beb2e49d899b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331869521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.3331869521
Directory /workspace/22.uart_rx_parity_err/latest

Test location /workspace/coverage/default/22.uart_rx_start_bit_filter.2714573912
Short name T1183
Test name
Test status
Simulation time 1740768771 ps
CPU time 1.37 seconds
Started Jun 06 12:59:23 PM PDT 24
Finished Jun 06 12:59:26 PM PDT 24
Peak memory 195872 kb
Host smart-6316571c-f9c3-426e-a334-1cd05ff245e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714573912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.2714573912
Directory /workspace/22.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/22.uart_smoke.2528138375
Short name T866
Test name
Test status
Simulation time 950309367 ps
CPU time 1.21 seconds
Started Jun 06 12:59:23 PM PDT 24
Finished Jun 06 12:59:26 PM PDT 24
Peak memory 198688 kb
Host smart-4c5904ab-6615-4da7-ae41-0fa924dc6c35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528138375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_smoke.2528138375
Directory /workspace/22.uart_smoke/latest

Test location /workspace/coverage/default/22.uart_stress_all.1957318241
Short name T594
Test name
Test status
Simulation time 243916160710 ps
CPU time 736.31 seconds
Started Jun 06 12:59:25 PM PDT 24
Finished Jun 06 01:11:43 PM PDT 24
Peak memory 216608 kb
Host smart-2ed57b4c-ebe7-4a8c-967f-6f0b9f127b03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957318241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.1957318241
Directory /workspace/22.uart_stress_all/latest

Test location /workspace/coverage/default/22.uart_stress_all_with_rand_reset.2996808935
Short name T837
Test name
Test status
Simulation time 105827706462 ps
CPU time 1769.56 seconds
Started Jun 06 12:59:23 PM PDT 24
Finished Jun 06 01:28:54 PM PDT 24
Peak memory 233440 kb
Host smart-86540937-3b9d-49fb-af24-f202ec454a65
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996808935 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 22.uart_stress_all_with_rand_reset.2996808935
Directory /workspace/22.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.uart_tx_ovrd.3994397094
Short name T120
Test name
Test status
Simulation time 1962200668 ps
CPU time 3.14 seconds
Started Jun 06 12:59:23 PM PDT 24
Finished Jun 06 12:59:28 PM PDT 24
Peak memory 198692 kb
Host smart-7b310dda-1add-4912-babb-b59469f55699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994397094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.3994397094
Directory /workspace/22.uart_tx_ovrd/latest

Test location /workspace/coverage/default/22.uart_tx_rx.665624361
Short name T336
Test name
Test status
Simulation time 169086520508 ps
CPU time 19.4 seconds
Started Jun 06 12:59:27 PM PDT 24
Finished Jun 06 12:59:47 PM PDT 24
Peak memory 200316 kb
Host smart-caca6215-1ae3-49d8-9a24-5a41cc560210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665624361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.665624361
Directory /workspace/22.uart_tx_rx/latest

Test location /workspace/coverage/default/220.uart_fifo_reset.3363212785
Short name T869
Test name
Test status
Simulation time 131645027344 ps
CPU time 64.84 seconds
Started Jun 06 01:03:24 PM PDT 24
Finished Jun 06 01:04:30 PM PDT 24
Peak memory 200432 kb
Host smart-60a5165b-6ae2-456a-9b23-a702bd0e5a85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363212785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.3363212785
Directory /workspace/220.uart_fifo_reset/latest

Test location /workspace/coverage/default/221.uart_fifo_reset.4094070794
Short name T731
Test name
Test status
Simulation time 64341277828 ps
CPU time 64.43 seconds
Started Jun 06 01:03:25 PM PDT 24
Finished Jun 06 01:04:31 PM PDT 24
Peak memory 200284 kb
Host smart-899b0ba8-bacc-42a9-9e0b-c1f8e78247fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094070794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.4094070794
Directory /workspace/221.uart_fifo_reset/latest

Test location /workspace/coverage/default/222.uart_fifo_reset.2043870418
Short name T1087
Test name
Test status
Simulation time 18398651292 ps
CPU time 26.06 seconds
Started Jun 06 01:03:25 PM PDT 24
Finished Jun 06 01:03:52 PM PDT 24
Peak memory 199928 kb
Host smart-2ba77f97-bd5c-4686-a626-d5e458bfca7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043870418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.2043870418
Directory /workspace/222.uart_fifo_reset/latest

Test location /workspace/coverage/default/223.uart_fifo_reset.2598034955
Short name T440
Test name
Test status
Simulation time 35490167466 ps
CPU time 15.47 seconds
Started Jun 06 01:03:27 PM PDT 24
Finished Jun 06 01:03:44 PM PDT 24
Peak memory 200092 kb
Host smart-78a76b68-b2d1-4542-8d9f-9fae9a1b7741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598034955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.2598034955
Directory /workspace/223.uart_fifo_reset/latest

Test location /workspace/coverage/default/224.uart_fifo_reset.2464370400
Short name T511
Test name
Test status
Simulation time 124154872195 ps
CPU time 124.83 seconds
Started Jun 06 01:03:26 PM PDT 24
Finished Jun 06 01:05:32 PM PDT 24
Peak memory 200324 kb
Host smart-8b1694b6-4e9a-42d3-8596-2d468e1b4c86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464370400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.2464370400
Directory /workspace/224.uart_fifo_reset/latest

Test location /workspace/coverage/default/225.uart_fifo_reset.4207024338
Short name T455
Test name
Test status
Simulation time 44270216799 ps
CPU time 68.9 seconds
Started Jun 06 01:03:25 PM PDT 24
Finished Jun 06 01:04:35 PM PDT 24
Peak memory 200252 kb
Host smart-bb7eec1a-c626-471f-abd5-ba385c93fdb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207024338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.4207024338
Directory /workspace/225.uart_fifo_reset/latest

Test location /workspace/coverage/default/226.uart_fifo_reset.3466061835
Short name T460
Test name
Test status
Simulation time 22200079955 ps
CPU time 14.94 seconds
Started Jun 06 01:03:25 PM PDT 24
Finished Jun 06 01:03:41 PM PDT 24
Peak memory 200024 kb
Host smart-d73f4452-860f-4fd7-a755-755018136b6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466061835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.3466061835
Directory /workspace/226.uart_fifo_reset/latest

Test location /workspace/coverage/default/227.uart_fifo_reset.3664878922
Short name T450
Test name
Test status
Simulation time 9065829228 ps
CPU time 17.94 seconds
Started Jun 06 01:03:27 PM PDT 24
Finished Jun 06 01:03:46 PM PDT 24
Peak memory 200396 kb
Host smart-1c5dfa81-b892-486f-9fbc-f8c4a8d4d95f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664878922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.3664878922
Directory /workspace/227.uart_fifo_reset/latest

Test location /workspace/coverage/default/228.uart_fifo_reset.1907807503
Short name T520
Test name
Test status
Simulation time 30408107226 ps
CPU time 49.61 seconds
Started Jun 06 01:03:28 PM PDT 24
Finished Jun 06 01:04:19 PM PDT 24
Peak memory 200368 kb
Host smart-0b655a4c-31ec-4dbb-ac89-8406891a5651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907807503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.1907807503
Directory /workspace/228.uart_fifo_reset/latest

Test location /workspace/coverage/default/229.uart_fifo_reset.2908566031
Short name T912
Test name
Test status
Simulation time 22819425871 ps
CPU time 38.27 seconds
Started Jun 06 01:03:27 PM PDT 24
Finished Jun 06 01:04:06 PM PDT 24
Peak memory 200328 kb
Host smart-78b710d4-06de-417d-a4b3-cca3bf6151d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908566031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.2908566031
Directory /workspace/229.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_alert_test.2145455959
Short name T987
Test name
Test status
Simulation time 15480600 ps
CPU time 0.54 seconds
Started Jun 06 12:59:31 PM PDT 24
Finished Jun 06 12:59:34 PM PDT 24
Peak memory 195932 kb
Host smart-b1591955-efed-4866-9f09-828c4f144ee1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145455959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.2145455959
Directory /workspace/23.uart_alert_test/latest

Test location /workspace/coverage/default/23.uart_fifo_full.1872920520
Short name T1083
Test name
Test status
Simulation time 84460143310 ps
CPU time 45.87 seconds
Started Jun 06 12:59:31 PM PDT 24
Finished Jun 06 01:00:18 PM PDT 24
Peak memory 200352 kb
Host smart-1ee756eb-adc7-4f3c-87c9-5d6b49740954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872920520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.1872920520
Directory /workspace/23.uart_fifo_full/latest

Test location /workspace/coverage/default/23.uart_fifo_overflow.335862006
Short name T143
Test name
Test status
Simulation time 193058772436 ps
CPU time 88.79 seconds
Started Jun 06 12:59:26 PM PDT 24
Finished Jun 06 01:00:56 PM PDT 24
Peak memory 200136 kb
Host smart-8ba74a9d-b5b0-4189-bf5e-434c7e6a1595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335862006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.335862006
Directory /workspace/23.uart_fifo_overflow/latest

Test location /workspace/coverage/default/23.uart_fifo_reset.4271307648
Short name T647
Test name
Test status
Simulation time 27907153850 ps
CPU time 30.02 seconds
Started Jun 06 12:59:25 PM PDT 24
Finished Jun 06 12:59:56 PM PDT 24
Peak memory 200284 kb
Host smart-43e55901-cc0a-4cca-935a-bee8af7e5448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271307648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.4271307648
Directory /workspace/23.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_intr.1618892472
Short name T739
Test name
Test status
Simulation time 187556479184 ps
CPU time 281.49 seconds
Started Jun 06 12:59:28 PM PDT 24
Finished Jun 06 01:04:10 PM PDT 24
Peak memory 200288 kb
Host smart-5966d344-e791-4930-82a4-92baf85463da
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618892472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.1618892472
Directory /workspace/23.uart_intr/latest

Test location /workspace/coverage/default/23.uart_long_xfer_wo_dly.1308551037
Short name T486
Test name
Test status
Simulation time 146892263568 ps
CPU time 937.01 seconds
Started Jun 06 12:59:23 PM PDT 24
Finished Jun 06 01:15:01 PM PDT 24
Peak memory 200364 kb
Host smart-7166bc3f-197a-4e03-bdd5-6b834217709e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1308551037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.1308551037
Directory /workspace/23.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/23.uart_loopback.515002163
Short name T578
Test name
Test status
Simulation time 1805040686 ps
CPU time 0.93 seconds
Started Jun 06 12:59:23 PM PDT 24
Finished Jun 06 12:59:25 PM PDT 24
Peak memory 195952 kb
Host smart-fdbb6453-936b-4301-afe5-0b74a0d0196c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515002163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_loopback.515002163
Directory /workspace/23.uart_loopback/latest

Test location /workspace/coverage/default/23.uart_noise_filter.3132971323
Short name T681
Test name
Test status
Simulation time 54604917384 ps
CPU time 43.6 seconds
Started Jun 06 12:59:23 PM PDT 24
Finished Jun 06 01:00:08 PM PDT 24
Peak memory 199864 kb
Host smart-b7e0a056-fd36-4bc9-8a1c-7eacbfd8f3a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132971323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_noise_filter.3132971323
Directory /workspace/23.uart_noise_filter/latest

Test location /workspace/coverage/default/23.uart_perf.510698710
Short name T836
Test name
Test status
Simulation time 23422101508 ps
CPU time 100.09 seconds
Started Jun 06 12:59:24 PM PDT 24
Finished Jun 06 01:01:05 PM PDT 24
Peak memory 200252 kb
Host smart-c70e24fc-e139-4341-9758-b473cb5832eb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=510698710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.510698710
Directory /workspace/23.uart_perf/latest

Test location /workspace/coverage/default/23.uart_rx_oversample.1396115339
Short name T621
Test name
Test status
Simulation time 6135241899 ps
CPU time 13.55 seconds
Started Jun 06 12:59:30 PM PDT 24
Finished Jun 06 12:59:45 PM PDT 24
Peak memory 200316 kb
Host smart-ed316de9-0116-4ba3-9157-65197d41ac51
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1396115339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.1396115339
Directory /workspace/23.uart_rx_oversample/latest

Test location /workspace/coverage/default/23.uart_rx_parity_err.2425441564
Short name T640
Test name
Test status
Simulation time 336922915515 ps
CPU time 37.19 seconds
Started Jun 06 12:59:23 PM PDT 24
Finished Jun 06 01:00:01 PM PDT 24
Peak memory 200180 kb
Host smart-5e012689-cce1-4e13-9ad5-a5f8919bfc45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425441564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.2425441564
Directory /workspace/23.uart_rx_parity_err/latest

Test location /workspace/coverage/default/23.uart_rx_start_bit_filter.379801252
Short name T420
Test name
Test status
Simulation time 52676466949 ps
CPU time 5.72 seconds
Started Jun 06 12:59:25 PM PDT 24
Finished Jun 06 12:59:33 PM PDT 24
Peak memory 196568 kb
Host smart-a2bbab9d-0fa3-46bd-a316-8f219c88bfbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379801252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.379801252
Directory /workspace/23.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/23.uart_smoke.112011046
Short name T941
Test name
Test status
Simulation time 5512630694 ps
CPU time 12.71 seconds
Started Jun 06 12:59:25 PM PDT 24
Finished Jun 06 12:59:39 PM PDT 24
Peak memory 200172 kb
Host smart-ad537912-8086-4b91-8197-313686148bb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112011046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_smoke.112011046
Directory /workspace/23.uart_smoke/latest

Test location /workspace/coverage/default/23.uart_stress_all.1023522550
Short name T884
Test name
Test status
Simulation time 371169732806 ps
CPU time 481.59 seconds
Started Jun 06 12:59:33 PM PDT 24
Finished Jun 06 01:07:36 PM PDT 24
Peak memory 208828 kb
Host smart-155c7420-07ed-4245-bf41-415ed39a2bf3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023522550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.1023522550
Directory /workspace/23.uart_stress_all/latest

Test location /workspace/coverage/default/23.uart_stress_all_with_rand_reset.2831632344
Short name T978
Test name
Test status
Simulation time 9114945233 ps
CPU time 98.15 seconds
Started Jun 06 12:59:37 PM PDT 24
Finished Jun 06 01:01:16 PM PDT 24
Peak memory 216168 kb
Host smart-97b5bdd1-1e8a-4ba3-ab18-276fcdfdd0f7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831632344 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 23.uart_stress_all_with_rand_reset.2831632344
Directory /workspace/23.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.uart_tx_ovrd.3858217807
Short name T613
Test name
Test status
Simulation time 7178494988 ps
CPU time 21.23 seconds
Started Jun 06 12:59:27 PM PDT 24
Finished Jun 06 12:59:49 PM PDT 24
Peak memory 199980 kb
Host smart-ef144148-4734-4c9e-a5b9-8861ea2fb90b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858217807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.3858217807
Directory /workspace/23.uart_tx_ovrd/latest

Test location /workspace/coverage/default/23.uart_tx_rx.452907992
Short name T776
Test name
Test status
Simulation time 78427416066 ps
CPU time 66.97 seconds
Started Jun 06 12:59:25 PM PDT 24
Finished Jun 06 01:00:33 PM PDT 24
Peak memory 200368 kb
Host smart-a64a6cde-de5e-42e4-8afe-dd975f86a462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452907992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.452907992
Directory /workspace/23.uart_tx_rx/latest

Test location /workspace/coverage/default/230.uart_fifo_reset.3072788436
Short name T207
Test name
Test status
Simulation time 56064907412 ps
CPU time 174.23 seconds
Started Jun 06 01:03:28 PM PDT 24
Finished Jun 06 01:06:23 PM PDT 24
Peak memory 200312 kb
Host smart-78e25c0b-d205-46c4-b546-29c04c8e4f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072788436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.3072788436
Directory /workspace/230.uart_fifo_reset/latest

Test location /workspace/coverage/default/231.uart_fifo_reset.3431926734
Short name T159
Test name
Test status
Simulation time 16809682298 ps
CPU time 29.71 seconds
Started Jun 06 01:03:25 PM PDT 24
Finished Jun 06 01:03:56 PM PDT 24
Peak memory 200208 kb
Host smart-66e76477-98d2-4a66-8f61-8b9e8ade4c5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431926734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.3431926734
Directory /workspace/231.uart_fifo_reset/latest

Test location /workspace/coverage/default/232.uart_fifo_reset.2251321677
Short name T122
Test name
Test status
Simulation time 117083551865 ps
CPU time 110.98 seconds
Started Jun 06 01:03:25 PM PDT 24
Finished Jun 06 01:05:17 PM PDT 24
Peak memory 200368 kb
Host smart-0ea83a1d-b12c-4fe9-9b17-a1d11fcb9799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251321677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.2251321677
Directory /workspace/232.uart_fifo_reset/latest

Test location /workspace/coverage/default/233.uart_fifo_reset.3905844542
Short name T673
Test name
Test status
Simulation time 120389981470 ps
CPU time 52.1 seconds
Started Jun 06 01:03:25 PM PDT 24
Finished Jun 06 01:04:19 PM PDT 24
Peak memory 200336 kb
Host smart-39a6fd64-8fb6-458d-8ea7-18354f21b908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905844542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.3905844542
Directory /workspace/233.uart_fifo_reset/latest

Test location /workspace/coverage/default/234.uart_fifo_reset.3455499121
Short name T979
Test name
Test status
Simulation time 157001669081 ps
CPU time 125.5 seconds
Started Jun 06 01:03:29 PM PDT 24
Finished Jun 06 01:05:35 PM PDT 24
Peak memory 200552 kb
Host smart-10fb0174-1c12-4400-9322-48ec2b092f94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455499121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.3455499121
Directory /workspace/234.uart_fifo_reset/latest

Test location /workspace/coverage/default/235.uart_fifo_reset.510706407
Short name T99
Test name
Test status
Simulation time 81993269454 ps
CPU time 31.4 seconds
Started Jun 06 01:03:27 PM PDT 24
Finished Jun 06 01:04:00 PM PDT 24
Peak memory 200208 kb
Host smart-c01ff748-c5b1-414a-ba9d-5d092d892dc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510706407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.510706407
Directory /workspace/235.uart_fifo_reset/latest

Test location /workspace/coverage/default/236.uart_fifo_reset.3463595912
Short name T735
Test name
Test status
Simulation time 94964007971 ps
CPU time 37.55 seconds
Started Jun 06 01:03:30 PM PDT 24
Finished Jun 06 01:04:08 PM PDT 24
Peak memory 200532 kb
Host smart-ad6ae4af-69b4-4b15-be61-fff6ca72274f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463595912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.3463595912
Directory /workspace/236.uart_fifo_reset/latest

Test location /workspace/coverage/default/237.uart_fifo_reset.85480981
Short name T1106
Test name
Test status
Simulation time 37911585148 ps
CPU time 37.2 seconds
Started Jun 06 01:03:28 PM PDT 24
Finished Jun 06 01:04:06 PM PDT 24
Peak memory 200328 kb
Host smart-e70556ce-6a4a-4c8c-a79f-b54fe5fc78ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85480981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.85480981
Directory /workspace/237.uart_fifo_reset/latest

Test location /workspace/coverage/default/239.uart_fifo_reset.4179075058
Short name T916
Test name
Test status
Simulation time 30200368042 ps
CPU time 27.22 seconds
Started Jun 06 01:03:28 PM PDT 24
Finished Jun 06 01:03:56 PM PDT 24
Peak memory 200376 kb
Host smart-2ec13cbe-2e9c-42f0-8408-331e451e6b69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179075058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.4179075058
Directory /workspace/239.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_alert_test.3131187974
Short name T346
Test name
Test status
Simulation time 15350759 ps
CPU time 0.53 seconds
Started Jun 06 12:59:36 PM PDT 24
Finished Jun 06 12:59:37 PM PDT 24
Peak memory 195680 kb
Host smart-ef7e3f06-c7c5-4da5-80e8-d9486a93af71
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131187974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.3131187974
Directory /workspace/24.uart_alert_test/latest

Test location /workspace/coverage/default/24.uart_fifo_overflow.3661957160
Short name T840
Test name
Test status
Simulation time 120394661098 ps
CPU time 29.79 seconds
Started Jun 06 12:59:32 PM PDT 24
Finished Jun 06 01:00:04 PM PDT 24
Peak memory 200232 kb
Host smart-ed773742-c4fb-4993-816b-f32290791511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661957160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.3661957160
Directory /workspace/24.uart_fifo_overflow/latest

Test location /workspace/coverage/default/24.uart_fifo_reset.2307011492
Short name T186
Test name
Test status
Simulation time 102742718137 ps
CPU time 158.22 seconds
Started Jun 06 12:59:31 PM PDT 24
Finished Jun 06 01:02:11 PM PDT 24
Peak memory 200368 kb
Host smart-9b83c277-d015-4377-a7c9-fb7c99cf59c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307011492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.2307011492
Directory /workspace/24.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_intr.3498043904
Short name T858
Test name
Test status
Simulation time 23708270374 ps
CPU time 10.94 seconds
Started Jun 06 01:00:17 PM PDT 24
Finished Jun 06 01:00:29 PM PDT 24
Peak memory 200232 kb
Host smart-7597977f-5b04-4fce-910c-952f732857d1
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498043904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.3498043904
Directory /workspace/24.uart_intr/latest

Test location /workspace/coverage/default/24.uart_long_xfer_wo_dly.52912423
Short name T1132
Test name
Test status
Simulation time 83493923209 ps
CPU time 148.48 seconds
Started Jun 06 12:59:37 PM PDT 24
Finished Jun 06 01:02:07 PM PDT 24
Peak memory 200256 kb
Host smart-94ffa85e-fdca-440f-accf-3cd0e7faa558
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=52912423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.52912423
Directory /workspace/24.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/24.uart_loopback.928749248
Short name T386
Test name
Test status
Simulation time 3111877463 ps
CPU time 1.75 seconds
Started Jun 06 12:59:33 PM PDT 24
Finished Jun 06 12:59:36 PM PDT 24
Peak memory 200164 kb
Host smart-e82c6ea8-7bfb-4a44-a096-c0bd913b3099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928749248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_loopback.928749248
Directory /workspace/24.uart_loopback/latest

Test location /workspace/coverage/default/24.uart_noise_filter.3765045186
Short name T507
Test name
Test status
Simulation time 31935048408 ps
CPU time 53.68 seconds
Started Jun 06 12:59:36 PM PDT 24
Finished Jun 06 01:00:32 PM PDT 24
Peak memory 198088 kb
Host smart-540c5b4b-d0d0-4f5f-9322-a69d2ccf8f60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765045186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_noise_filter.3765045186
Directory /workspace/24.uart_noise_filter/latest

Test location /workspace/coverage/default/24.uart_perf.919235645
Short name T1160
Test name
Test status
Simulation time 13850619509 ps
CPU time 48.58 seconds
Started Jun 06 12:59:37 PM PDT 24
Finished Jun 06 01:00:27 PM PDT 24
Peak memory 200244 kb
Host smart-c32e0d24-b48d-4c59-a988-181628ed6412
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=919235645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.919235645
Directory /workspace/24.uart_perf/latest

Test location /workspace/coverage/default/24.uart_rx_oversample.3737310809
Short name T643
Test name
Test status
Simulation time 2859206570 ps
CPU time 4.88 seconds
Started Jun 06 12:59:31 PM PDT 24
Finished Jun 06 12:59:38 PM PDT 24
Peak memory 198700 kb
Host smart-82e2d73b-d6c7-4b28-8360-c643241a7d07
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3737310809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.3737310809
Directory /workspace/24.uart_rx_oversample/latest

Test location /workspace/coverage/default/24.uart_rx_parity_err.1406727441
Short name T146
Test name
Test status
Simulation time 55867425211 ps
CPU time 46.3 seconds
Started Jun 06 12:59:31 PM PDT 24
Finished Jun 06 01:00:19 PM PDT 24
Peak memory 200284 kb
Host smart-1a54446d-b3b7-4225-9c67-e99d560bd00c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406727441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.1406727441
Directory /workspace/24.uart_rx_parity_err/latest

Test location /workspace/coverage/default/24.uart_rx_start_bit_filter.2508229736
Short name T719
Test name
Test status
Simulation time 1655988441 ps
CPU time 1.9 seconds
Started Jun 06 12:59:30 PM PDT 24
Finished Jun 06 12:59:33 PM PDT 24
Peak memory 195628 kb
Host smart-b532a574-7944-4dc3-94b5-67d1e165bcb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508229736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.2508229736
Directory /workspace/24.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/24.uart_smoke.1995073256
Short name T371
Test name
Test status
Simulation time 274084777 ps
CPU time 1.08 seconds
Started Jun 06 12:59:32 PM PDT 24
Finished Jun 06 12:59:34 PM PDT 24
Peak memory 198696 kb
Host smart-2b22bb01-fdd1-42ee-b942-c5c8f7da96ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995073256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_smoke.1995073256
Directory /workspace/24.uart_smoke/latest

Test location /workspace/coverage/default/24.uart_stress_all.1705043661
Short name T865
Test name
Test status
Simulation time 80889783746 ps
CPU time 81.55 seconds
Started Jun 06 12:59:31 PM PDT 24
Finished Jun 06 01:00:54 PM PDT 24
Peak memory 200148 kb
Host smart-1696fe99-5a4a-42e5-b55d-52f76c509885
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705043661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.1705043661
Directory /workspace/24.uart_stress_all/latest

Test location /workspace/coverage/default/24.uart_stress_all_with_rand_reset.3102244597
Short name T33
Test name
Test status
Simulation time 54599899560 ps
CPU time 373.6 seconds
Started Jun 06 12:59:36 PM PDT 24
Finished Jun 06 01:05:51 PM PDT 24
Peak memory 216772 kb
Host smart-6a9d81f2-4083-44e0-8cbb-ac4a3af79c00
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102244597 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 24.uart_stress_all_with_rand_reset.3102244597
Directory /workspace/24.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.uart_tx_ovrd.3361221052
Short name T305
Test name
Test status
Simulation time 1134746596 ps
CPU time 1.96 seconds
Started Jun 06 12:59:36 PM PDT 24
Finished Jun 06 12:59:39 PM PDT 24
Peak memory 200196 kb
Host smart-16652714-711e-481c-8fb9-f00b2d53989b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361221052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.3361221052
Directory /workspace/24.uart_tx_ovrd/latest

Test location /workspace/coverage/default/24.uart_tx_rx.2343838108
Short name T751
Test name
Test status
Simulation time 108965147733 ps
CPU time 235.13 seconds
Started Jun 06 12:59:33 PM PDT 24
Finished Jun 06 01:03:30 PM PDT 24
Peak memory 200292 kb
Host smart-ac64bbc4-3135-48be-8dec-67bd3665b288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343838108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.2343838108
Directory /workspace/24.uart_tx_rx/latest

Test location /workspace/coverage/default/241.uart_fifo_reset.1576471668
Short name T473
Test name
Test status
Simulation time 95699164182 ps
CPU time 60.62 seconds
Started Jun 06 01:03:27 PM PDT 24
Finished Jun 06 01:04:28 PM PDT 24
Peak memory 200296 kb
Host smart-009fd8e5-dedb-4b59-b7af-b7516c616198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576471668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.1576471668
Directory /workspace/241.uart_fifo_reset/latest

Test location /workspace/coverage/default/242.uart_fifo_reset.4232638496
Short name T825
Test name
Test status
Simulation time 99461822631 ps
CPU time 166.88 seconds
Started Jun 06 01:03:29 PM PDT 24
Finished Jun 06 01:06:17 PM PDT 24
Peak memory 200284 kb
Host smart-8b24e39a-4c3f-476e-902c-14ef40b52ffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232638496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.4232638496
Directory /workspace/242.uart_fifo_reset/latest

Test location /workspace/coverage/default/243.uart_fifo_reset.819455948
Short name T323
Test name
Test status
Simulation time 313125986260 ps
CPU time 73.39 seconds
Started Jun 06 01:03:28 PM PDT 24
Finished Jun 06 01:04:43 PM PDT 24
Peak memory 200388 kb
Host smart-0f825a96-e81f-484f-a1ee-c4295a4e7283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819455948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.819455948
Directory /workspace/243.uart_fifo_reset/latest

Test location /workspace/coverage/default/244.uart_fifo_reset.3240568471
Short name T200
Test name
Test status
Simulation time 79269589204 ps
CPU time 34.29 seconds
Started Jun 06 01:03:29 PM PDT 24
Finished Jun 06 01:04:04 PM PDT 24
Peak memory 200336 kb
Host smart-77ca5145-38fb-497a-9fcf-e7de20356f1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240568471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.3240568471
Directory /workspace/244.uart_fifo_reset/latest

Test location /workspace/coverage/default/245.uart_fifo_reset.314061173
Short name T168
Test name
Test status
Simulation time 71334026752 ps
CPU time 29.6 seconds
Started Jun 06 01:03:38 PM PDT 24
Finished Jun 06 01:04:09 PM PDT 24
Peak memory 200376 kb
Host smart-dbfe3861-7e2e-4efe-a4d6-97d40357268c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314061173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.314061173
Directory /workspace/245.uart_fifo_reset/latest

Test location /workspace/coverage/default/246.uart_fifo_reset.681224858
Short name T1167
Test name
Test status
Simulation time 177930252603 ps
CPU time 277.02 seconds
Started Jun 06 01:03:37 PM PDT 24
Finished Jun 06 01:08:15 PM PDT 24
Peak memory 200628 kb
Host smart-30031373-d70d-4a2b-9660-a6542d3786cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681224858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.681224858
Directory /workspace/246.uart_fifo_reset/latest

Test location /workspace/coverage/default/247.uart_fifo_reset.915682896
Short name T696
Test name
Test status
Simulation time 50172491366 ps
CPU time 46.21 seconds
Started Jun 06 01:03:36 PM PDT 24
Finished Jun 06 01:04:24 PM PDT 24
Peak memory 200408 kb
Host smart-79755155-b8f2-47dc-bfb9-6eac2eb5a4a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915682896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.915682896
Directory /workspace/247.uart_fifo_reset/latest

Test location /workspace/coverage/default/248.uart_fifo_reset.4085370202
Short name T934
Test name
Test status
Simulation time 51171911577 ps
CPU time 11.14 seconds
Started Jun 06 01:03:37 PM PDT 24
Finished Jun 06 01:03:49 PM PDT 24
Peak memory 200188 kb
Host smart-eae464a3-8e61-4da0-b871-ab5344769f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085370202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.4085370202
Directory /workspace/248.uart_fifo_reset/latest

Test location /workspace/coverage/default/249.uart_fifo_reset.1693378511
Short name T1037
Test name
Test status
Simulation time 73279401650 ps
CPU time 36.16 seconds
Started Jun 06 01:03:51 PM PDT 24
Finished Jun 06 01:04:28 PM PDT 24
Peak memory 200304 kb
Host smart-3651acd2-bc38-4fad-b4f9-38a9a99ed5c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693378511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.1693378511
Directory /workspace/249.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_alert_test.643067659
Short name T6
Test name
Test status
Simulation time 97389201 ps
CPU time 0.57 seconds
Started Jun 06 12:59:45 PM PDT 24
Finished Jun 06 12:59:47 PM PDT 24
Peak memory 195708 kb
Host smart-99b47f73-5050-4180-8eaa-f2628e981ca0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643067659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.643067659
Directory /workspace/25.uart_alert_test/latest

Test location /workspace/coverage/default/25.uart_fifo_full.3641781657
Short name T275
Test name
Test status
Simulation time 73965342242 ps
CPU time 67.76 seconds
Started Jun 06 12:59:37 PM PDT 24
Finished Jun 06 01:00:46 PM PDT 24
Peak memory 200264 kb
Host smart-d1e599b8-28d1-420a-892f-4be59a0798cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641781657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.3641781657
Directory /workspace/25.uart_fifo_full/latest

Test location /workspace/coverage/default/25.uart_fifo_overflow.941969273
Short name T736
Test name
Test status
Simulation time 12526603942 ps
CPU time 22.29 seconds
Started Jun 06 12:59:33 PM PDT 24
Finished Jun 06 12:59:57 PM PDT 24
Peak memory 200348 kb
Host smart-83ccdda5-f239-414a-a82b-ff86787c5351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941969273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.941969273
Directory /workspace/25.uart_fifo_overflow/latest

Test location /workspace/coverage/default/25.uart_fifo_reset.3324367399
Short name T1180
Test name
Test status
Simulation time 142648527779 ps
CPU time 70.45 seconds
Started Jun 06 12:59:37 PM PDT 24
Finished Jun 06 01:00:49 PM PDT 24
Peak memory 200236 kb
Host smart-54593380-7988-4efc-b267-c9378fee05a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324367399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.3324367399
Directory /workspace/25.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_intr.3594027739
Short name T5
Test name
Test status
Simulation time 11169811257 ps
CPU time 17.01 seconds
Started Jun 06 12:59:37 PM PDT 24
Finished Jun 06 12:59:55 PM PDT 24
Peak memory 198004 kb
Host smart-d3311a29-87e0-41d4-b37a-25a67ccf0056
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594027739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.3594027739
Directory /workspace/25.uart_intr/latest

Test location /workspace/coverage/default/25.uart_long_xfer_wo_dly.535284357
Short name T860
Test name
Test status
Simulation time 100677819993 ps
CPU time 854.78 seconds
Started Jun 06 12:59:43 PM PDT 24
Finished Jun 06 01:14:00 PM PDT 24
Peak memory 200248 kb
Host smart-0eb311a4-08ad-49ae-b2ed-bbc4fedafc3c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=535284357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.535284357
Directory /workspace/25.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/25.uart_loopback.2233847273
Short name T425
Test name
Test status
Simulation time 7596987484 ps
CPU time 31.28 seconds
Started Jun 06 12:59:42 PM PDT 24
Finished Jun 06 01:00:15 PM PDT 24
Peak memory 200452 kb
Host smart-7bf304f0-5396-46b1-8a99-6b91101147ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233847273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_loopback.2233847273
Directory /workspace/25.uart_loopback/latest

Test location /workspace/coverage/default/25.uart_noise_filter.718990197
Short name T706
Test name
Test status
Simulation time 92391683124 ps
CPU time 10.42 seconds
Started Jun 06 12:59:32 PM PDT 24
Finished Jun 06 12:59:44 PM PDT 24
Peak memory 196884 kb
Host smart-38c4d54d-691e-439d-b0df-d43821724d05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718990197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_noise_filter.718990197
Directory /workspace/25.uart_noise_filter/latest

Test location /workspace/coverage/default/25.uart_perf.1771023648
Short name T1086
Test name
Test status
Simulation time 7126280860 ps
CPU time 188.49 seconds
Started Jun 06 12:59:52 PM PDT 24
Finished Jun 06 01:03:02 PM PDT 24
Peak memory 200320 kb
Host smart-8a344646-0077-428e-a9c2-e1e1700f08ce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1771023648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.1771023648
Directory /workspace/25.uart_perf/latest

Test location /workspace/coverage/default/25.uart_rx_oversample.434207743
Short name T936
Test name
Test status
Simulation time 5703637086 ps
CPU time 8.9 seconds
Started Jun 06 12:59:31 PM PDT 24
Finished Jun 06 12:59:42 PM PDT 24
Peak memory 198784 kb
Host smart-943b18a2-f4bc-4942-9483-c4c22ee1bb90
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=434207743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.434207743
Directory /workspace/25.uart_rx_oversample/latest

Test location /workspace/coverage/default/25.uart_rx_parity_err.3899182555
Short name T148
Test name
Test status
Simulation time 239136233217 ps
CPU time 52.58 seconds
Started Jun 06 12:59:45 PM PDT 24
Finished Jun 06 01:00:39 PM PDT 24
Peak memory 200268 kb
Host smart-01bfa30e-6f5c-43b4-9faf-24dc5bb20796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899182555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.3899182555
Directory /workspace/25.uart_rx_parity_err/latest

Test location /workspace/coverage/default/25.uart_rx_start_bit_filter.328032734
Short name T396
Test name
Test status
Simulation time 6417820103 ps
CPU time 10.74 seconds
Started Jun 06 12:59:41 PM PDT 24
Finished Jun 06 12:59:53 PM PDT 24
Peak memory 196648 kb
Host smart-6cff2a0c-bbdc-409d-8b6b-601359f5a017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328032734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.328032734
Directory /workspace/25.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/25.uart_smoke.1021144649
Short name T389
Test name
Test status
Simulation time 475236964 ps
CPU time 1.71 seconds
Started Jun 06 12:59:32 PM PDT 24
Finished Jun 06 12:59:36 PM PDT 24
Peak memory 199844 kb
Host smart-840da2f9-4457-428c-9423-14b1cfc40eb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021144649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_smoke.1021144649
Directory /workspace/25.uart_smoke/latest

Test location /workspace/coverage/default/25.uart_stress_all.437380621
Short name T604
Test name
Test status
Simulation time 37307077070 ps
CPU time 63.84 seconds
Started Jun 06 12:59:41 PM PDT 24
Finished Jun 06 01:00:47 PM PDT 24
Peak memory 200364 kb
Host smart-d728d4be-1d34-4081-ae94-080a91758fb3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437380621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.437380621
Directory /workspace/25.uart_stress_all/latest

Test location /workspace/coverage/default/25.uart_stress_all_with_rand_reset.1734495841
Short name T1003
Test name
Test status
Simulation time 57054511464 ps
CPU time 668.08 seconds
Started Jun 06 12:59:44 PM PDT 24
Finished Jun 06 01:10:54 PM PDT 24
Peak memory 216988 kb
Host smart-66244380-2c2a-4f6f-99ae-f592daab2f6d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734495841 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 25.uart_stress_all_with_rand_reset.1734495841
Directory /workspace/25.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.uart_tx_ovrd.883358848
Short name T302
Test name
Test status
Simulation time 727948257 ps
CPU time 1.33 seconds
Started Jun 06 12:59:44 PM PDT 24
Finished Jun 06 12:59:47 PM PDT 24
Peak memory 197304 kb
Host smart-38e5cb6c-a803-4b1c-bc5d-84f5c3acefb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883358848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.883358848
Directory /workspace/25.uart_tx_ovrd/latest

Test location /workspace/coverage/default/25.uart_tx_rx.1647385046
Short name T789
Test name
Test status
Simulation time 40183924764 ps
CPU time 15.36 seconds
Started Jun 06 12:59:37 PM PDT 24
Finished Jun 06 12:59:54 PM PDT 24
Peak memory 200216 kb
Host smart-3269ea93-24ea-4892-bc93-75ff35a44622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647385046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.1647385046
Directory /workspace/25.uart_tx_rx/latest

Test location /workspace/coverage/default/251.uart_fifo_reset.1707540357
Short name T538
Test name
Test status
Simulation time 124054054029 ps
CPU time 183.82 seconds
Started Jun 06 01:03:35 PM PDT 24
Finished Jun 06 01:06:39 PM PDT 24
Peak memory 200236 kb
Host smart-59bb4068-907b-4b3d-b082-962e3166e420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707540357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.1707540357
Directory /workspace/251.uart_fifo_reset/latest

Test location /workspace/coverage/default/252.uart_fifo_reset.3617380070
Short name T1002
Test name
Test status
Simulation time 100149195155 ps
CPU time 140.51 seconds
Started Jun 06 01:03:36 PM PDT 24
Finished Jun 06 01:05:57 PM PDT 24
Peak memory 200308 kb
Host smart-f9ac1132-5ccd-47ef-b5c4-89a07c2b3faa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617380070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.3617380070
Directory /workspace/252.uart_fifo_reset/latest

Test location /workspace/coverage/default/253.uart_fifo_reset.2303835300
Short name T1008
Test name
Test status
Simulation time 103090940132 ps
CPU time 74.27 seconds
Started Jun 06 01:03:36 PM PDT 24
Finished Jun 06 01:04:51 PM PDT 24
Peak memory 200340 kb
Host smart-575410e8-32ea-45ef-bda9-e3a2fa8c5a24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303835300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.2303835300
Directory /workspace/253.uart_fifo_reset/latest

Test location /workspace/coverage/default/254.uart_fifo_reset.1394455852
Short name T911
Test name
Test status
Simulation time 99204792533 ps
CPU time 179.67 seconds
Started Jun 06 01:03:35 PM PDT 24
Finished Jun 06 01:06:35 PM PDT 24
Peak memory 200404 kb
Host smart-9a0f6053-89b1-4cbf-870b-645eecc4197b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394455852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.1394455852
Directory /workspace/254.uart_fifo_reset/latest

Test location /workspace/coverage/default/255.uart_fifo_reset.4081250553
Short name T291
Test name
Test status
Simulation time 14766820947 ps
CPU time 14.68 seconds
Started Jun 06 01:03:37 PM PDT 24
Finished Jun 06 01:03:53 PM PDT 24
Peak memory 200276 kb
Host smart-eb951cd3-20c1-4e2b-900f-52e5a026439a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081250553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.4081250553
Directory /workspace/255.uart_fifo_reset/latest

Test location /workspace/coverage/default/256.uart_fifo_reset.2796568109
Short name T139
Test name
Test status
Simulation time 17241516039 ps
CPU time 14.7 seconds
Started Jun 06 01:03:40 PM PDT 24
Finished Jun 06 01:03:56 PM PDT 24
Peak memory 200284 kb
Host smart-3e5a30f1-c003-46d3-a677-e0f928d8b6af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796568109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.2796568109
Directory /workspace/256.uart_fifo_reset/latest

Test location /workspace/coverage/default/257.uart_fifo_reset.88866305
Short name T266
Test name
Test status
Simulation time 12741138594 ps
CPU time 17.91 seconds
Started Jun 06 01:03:37 PM PDT 24
Finished Jun 06 01:03:56 PM PDT 24
Peak memory 200376 kb
Host smart-054e373c-8844-40a2-a4b0-2d06ba6e8615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88866305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.88866305
Directory /workspace/257.uart_fifo_reset/latest

Test location /workspace/coverage/default/258.uart_fifo_reset.1409970202
Short name T563
Test name
Test status
Simulation time 49522387415 ps
CPU time 19.88 seconds
Started Jun 06 01:03:37 PM PDT 24
Finished Jun 06 01:03:58 PM PDT 24
Peak memory 200356 kb
Host smart-b215ec5f-18a4-44d7-9afd-f38bcf8b467d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409970202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.1409970202
Directory /workspace/258.uart_fifo_reset/latest

Test location /workspace/coverage/default/259.uart_fifo_reset.2499410022
Short name T1040
Test name
Test status
Simulation time 119068933816 ps
CPU time 38.77 seconds
Started Jun 06 01:03:38 PM PDT 24
Finished Jun 06 01:04:18 PM PDT 24
Peak memory 200168 kb
Host smart-095838fa-0a8f-440c-9590-a574d46d912c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499410022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.2499410022
Directory /workspace/259.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_alert_test.4119040005
Short name T919
Test name
Test status
Simulation time 15975666 ps
CPU time 0.55 seconds
Started Jun 06 12:59:53 PM PDT 24
Finished Jun 06 12:59:54 PM PDT 24
Peak memory 195716 kb
Host smart-ffcb0801-ea80-4beb-97df-66fa62932f7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119040005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.4119040005
Directory /workspace/26.uart_alert_test/latest

Test location /workspace/coverage/default/26.uart_fifo_full.4219945052
Short name T494
Test name
Test status
Simulation time 129358995149 ps
CPU time 112.21 seconds
Started Jun 06 12:59:40 PM PDT 24
Finished Jun 06 01:01:34 PM PDT 24
Peak memory 200368 kb
Host smart-b68a232a-512e-4570-80e6-968be846180e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219945052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.4219945052
Directory /workspace/26.uart_fifo_full/latest

Test location /workspace/coverage/default/26.uart_fifo_overflow.672843497
Short name T569
Test name
Test status
Simulation time 98204574125 ps
CPU time 537.33 seconds
Started Jun 06 12:59:42 PM PDT 24
Finished Jun 06 01:08:41 PM PDT 24
Peak memory 200376 kb
Host smart-ad5267e5-e8fb-468b-b5cf-19b64e19a2ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672843497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.672843497
Directory /workspace/26.uart_fifo_overflow/latest

Test location /workspace/coverage/default/26.uart_fifo_reset.1498083026
Short name T452
Test name
Test status
Simulation time 52147459307 ps
CPU time 57.09 seconds
Started Jun 06 12:59:43 PM PDT 24
Finished Jun 06 01:00:42 PM PDT 24
Peak memory 200320 kb
Host smart-fb05803d-9033-4035-9f16-876a4097f672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498083026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.1498083026
Directory /workspace/26.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_intr.4171792940
Short name T989
Test name
Test status
Simulation time 461763631262 ps
CPU time 719.41 seconds
Started Jun 06 12:59:45 PM PDT 24
Finished Jun 06 01:11:46 PM PDT 24
Peak memory 200284 kb
Host smart-0f9d35f9-4e7a-4260-8b2a-8ae6f7d954b9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171792940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.4171792940
Directory /workspace/26.uart_intr/latest

Test location /workspace/coverage/default/26.uart_long_xfer_wo_dly.4250381073
Short name T1028
Test name
Test status
Simulation time 64980211661 ps
CPU time 196.34 seconds
Started Jun 06 12:59:41 PM PDT 24
Finished Jun 06 01:02:59 PM PDT 24
Peak memory 200368 kb
Host smart-0b57965b-3228-4a5c-ae7f-f04dd74f3f95
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4250381073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.4250381073
Directory /workspace/26.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/26.uart_loopback.3730108338
Short name T410
Test name
Test status
Simulation time 9338954024 ps
CPU time 18.14 seconds
Started Jun 06 12:59:42 PM PDT 24
Finished Jun 06 01:00:02 PM PDT 24
Peak memory 199312 kb
Host smart-ed1e5ea7-3943-4be3-81da-930ed1d0ec74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730108338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_loopback.3730108338
Directory /workspace/26.uart_loopback/latest

Test location /workspace/coverage/default/26.uart_noise_filter.2359155139
Short name T669
Test name
Test status
Simulation time 76208336166 ps
CPU time 188.77 seconds
Started Jun 06 12:59:46 PM PDT 24
Finished Jun 06 01:02:56 PM PDT 24
Peak memory 200560 kb
Host smart-37873cf3-001b-4d49-aba2-e375ba99fd8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359155139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_noise_filter.2359155139
Directory /workspace/26.uart_noise_filter/latest

Test location /workspace/coverage/default/26.uart_perf.916114915
Short name T1021
Test name
Test status
Simulation time 8784447209 ps
CPU time 500.27 seconds
Started Jun 06 12:59:41 PM PDT 24
Finished Jun 06 01:08:03 PM PDT 24
Peak memory 200284 kb
Host smart-c48d0386-eee3-453e-ba21-0d55e7240403
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=916114915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.916114915
Directory /workspace/26.uart_perf/latest

Test location /workspace/coverage/default/26.uart_rx_oversample.612142157
Short name T1052
Test name
Test status
Simulation time 5164876367 ps
CPU time 24.77 seconds
Started Jun 06 12:59:42 PM PDT 24
Finished Jun 06 01:00:09 PM PDT 24
Peak memory 199168 kb
Host smart-2dc85eb1-2a9b-4c04-acbe-9cf5853b5525
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=612142157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.612142157
Directory /workspace/26.uart_rx_oversample/latest

Test location /workspace/coverage/default/26.uart_rx_parity_err.2219648200
Short name T397
Test name
Test status
Simulation time 114718924189 ps
CPU time 87.64 seconds
Started Jun 06 12:59:43 PM PDT 24
Finished Jun 06 01:01:12 PM PDT 24
Peak memory 200392 kb
Host smart-fda2f2d8-7d32-4e12-b2a4-d5aeb5d9be2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219648200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.2219648200
Directory /workspace/26.uart_rx_parity_err/latest

Test location /workspace/coverage/default/26.uart_rx_start_bit_filter.1599441529
Short name T384
Test name
Test status
Simulation time 36726209248 ps
CPU time 13.92 seconds
Started Jun 06 12:59:43 PM PDT 24
Finished Jun 06 12:59:59 PM PDT 24
Peak memory 196176 kb
Host smart-0a777753-2e3b-4ba3-8985-c37f79bca4b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599441529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.1599441529
Directory /workspace/26.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/26.uart_smoke.2251386987
Short name T51
Test name
Test status
Simulation time 466642032 ps
CPU time 1.46 seconds
Started Jun 06 12:59:43 PM PDT 24
Finished Jun 06 12:59:46 PM PDT 24
Peak memory 198744 kb
Host smart-23479d19-ddba-4358-a10e-5ae6f29bb6f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251386987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_smoke.2251386987
Directory /workspace/26.uart_smoke/latest

Test location /workspace/coverage/default/26.uart_stress_all.2451591164
Short name T536
Test name
Test status
Simulation time 136135745074 ps
CPU time 2155.94 seconds
Started Jun 06 12:59:54 PM PDT 24
Finished Jun 06 01:35:52 PM PDT 24
Peak memory 200340 kb
Host smart-a733cb8b-659b-4ebc-be5f-dfb82bc3107a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451591164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.2451591164
Directory /workspace/26.uart_stress_all/latest

Test location /workspace/coverage/default/26.uart_stress_all_with_rand_reset.2920876275
Short name T1034
Test name
Test status
Simulation time 39666880706 ps
CPU time 359.83 seconds
Started Jun 06 12:59:44 PM PDT 24
Finished Jun 06 01:05:45 PM PDT 24
Peak memory 216920 kb
Host smart-e83ec2e8-187a-428a-87f7-95f00d486800
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920876275 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 26.uart_stress_all_with_rand_reset.2920876275
Directory /workspace/26.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.uart_tx_ovrd.752155353
Short name T363
Test name
Test status
Simulation time 1329415203 ps
CPU time 1.37 seconds
Started Jun 06 12:59:42 PM PDT 24
Finished Jun 06 12:59:45 PM PDT 24
Peak memory 198348 kb
Host smart-2f439a1e-79df-46c7-8ea6-6b7ffb948382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752155353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.752155353
Directory /workspace/26.uart_tx_ovrd/latest

Test location /workspace/coverage/default/26.uart_tx_rx.1163981665
Short name T645
Test name
Test status
Simulation time 61961219012 ps
CPU time 26.14 seconds
Started Jun 06 12:59:41 PM PDT 24
Finished Jun 06 01:00:08 PM PDT 24
Peak memory 200140 kb
Host smart-59ed6063-0841-436f-8710-9f2a86946e10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163981665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.1163981665
Directory /workspace/26.uart_tx_rx/latest

Test location /workspace/coverage/default/260.uart_fifo_reset.2886451747
Short name T217
Test name
Test status
Simulation time 191104775744 ps
CPU time 254.82 seconds
Started Jun 06 01:03:38 PM PDT 24
Finished Jun 06 01:07:54 PM PDT 24
Peak memory 200120 kb
Host smart-f64418c0-8adf-4f87-a03a-361cadd21196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886451747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.2886451747
Directory /workspace/260.uart_fifo_reset/latest

Test location /workspace/coverage/default/261.uart_fifo_reset.1133417158
Short name T933
Test name
Test status
Simulation time 206402047647 ps
CPU time 323.83 seconds
Started Jun 06 01:03:38 PM PDT 24
Finished Jun 06 01:09:03 PM PDT 24
Peak memory 200120 kb
Host smart-07f05ae6-73d0-4b84-9482-ab84ff3035e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133417158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.1133417158
Directory /workspace/261.uart_fifo_reset/latest

Test location /workspace/coverage/default/262.uart_fifo_reset.1473754598
Short name T965
Test name
Test status
Simulation time 79262057814 ps
CPU time 62.37 seconds
Started Jun 06 01:03:37 PM PDT 24
Finished Jun 06 01:04:41 PM PDT 24
Peak memory 200424 kb
Host smart-86d2bd62-9e8b-4a25-80cc-662baf1dcc38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473754598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.1473754598
Directory /workspace/262.uart_fifo_reset/latest

Test location /workspace/coverage/default/263.uart_fifo_reset.2316647189
Short name T663
Test name
Test status
Simulation time 156252291924 ps
CPU time 30.33 seconds
Started Jun 06 01:03:40 PM PDT 24
Finished Jun 06 01:04:11 PM PDT 24
Peak memory 200376 kb
Host smart-a7c5a9a2-ad5d-42ec-8134-78c521313169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316647189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.2316647189
Directory /workspace/263.uart_fifo_reset/latest

Test location /workspace/coverage/default/264.uart_fifo_reset.4044377342
Short name T188
Test name
Test status
Simulation time 139090916953 ps
CPU time 225.24 seconds
Started Jun 06 01:03:40 PM PDT 24
Finished Jun 06 01:07:27 PM PDT 24
Peak memory 200288 kb
Host smart-63ff2652-ebd9-4bf1-91e9-6d0c97c2f061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044377342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.4044377342
Directory /workspace/264.uart_fifo_reset/latest

Test location /workspace/coverage/default/265.uart_fifo_reset.1238986272
Short name T1118
Test name
Test status
Simulation time 99641595369 ps
CPU time 49.39 seconds
Started Jun 06 01:03:39 PM PDT 24
Finished Jun 06 01:04:30 PM PDT 24
Peak memory 200332 kb
Host smart-ee272cc3-a73d-4d2e-8370-9c2296dfa668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238986272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.1238986272
Directory /workspace/265.uart_fifo_reset/latest

Test location /workspace/coverage/default/266.uart_fifo_reset.3300163150
Short name T778
Test name
Test status
Simulation time 31583131823 ps
CPU time 56.17 seconds
Started Jun 06 01:03:40 PM PDT 24
Finished Jun 06 01:04:37 PM PDT 24
Peak memory 200368 kb
Host smart-dd2ccf44-3c46-4fce-baa4-1a07bea81878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300163150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.3300163150
Directory /workspace/266.uart_fifo_reset/latest

Test location /workspace/coverage/default/267.uart_fifo_reset.3042990365
Short name T1135
Test name
Test status
Simulation time 168662215552 ps
CPU time 103.87 seconds
Started Jun 06 01:03:36 PM PDT 24
Finished Jun 06 01:05:21 PM PDT 24
Peak memory 200280 kb
Host smart-da0908d1-a8c1-42fb-b6a9-28dbf1d355d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042990365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.3042990365
Directory /workspace/267.uart_fifo_reset/latest

Test location /workspace/coverage/default/269.uart_fifo_reset.2072634353
Short name T1068
Test name
Test status
Simulation time 54586270617 ps
CPU time 99.87 seconds
Started Jun 06 01:03:41 PM PDT 24
Finished Jun 06 01:05:22 PM PDT 24
Peak memory 200316 kb
Host smart-7168e835-24ac-48ff-9513-9fed454e686e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072634353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.2072634353
Directory /workspace/269.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_alert_test.1114084727
Short name T1063
Test name
Test status
Simulation time 197033263 ps
CPU time 0.57 seconds
Started Jun 06 12:59:56 PM PDT 24
Finished Jun 06 12:59:58 PM PDT 24
Peak memory 195960 kb
Host smart-09ff58f3-04a9-4f8c-8b05-9e63e56e735b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114084727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.1114084727
Directory /workspace/27.uart_alert_test/latest

Test location /workspace/coverage/default/27.uart_fifo_full.520665239
Short name T1174
Test name
Test status
Simulation time 142649003126 ps
CPU time 61.63 seconds
Started Jun 06 12:59:54 PM PDT 24
Finished Jun 06 01:00:58 PM PDT 24
Peak memory 200244 kb
Host smart-7ad6864d-1d3c-4e61-830c-b7d0a431775e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520665239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.520665239
Directory /workspace/27.uart_fifo_full/latest

Test location /workspace/coverage/default/27.uart_fifo_overflow.2093395895
Short name T790
Test name
Test status
Simulation time 41968748458 ps
CPU time 44.91 seconds
Started Jun 06 12:59:54 PM PDT 24
Finished Jun 06 01:00:41 PM PDT 24
Peak memory 200304 kb
Host smart-19f9ffe1-dda6-4b6f-8625-15eb9a87bcd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093395895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.2093395895
Directory /workspace/27.uart_fifo_overflow/latest

Test location /workspace/coverage/default/27.uart_fifo_reset.3101981418
Short name T195
Test name
Test status
Simulation time 48813623444 ps
CPU time 144.38 seconds
Started Jun 06 12:59:55 PM PDT 24
Finished Jun 06 01:02:21 PM PDT 24
Peak memory 200312 kb
Host smart-e926b6f2-d81c-4376-b4b1-b5908e6a1b9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101981418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.3101981418
Directory /workspace/27.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_intr.113026458
Short name T128
Test name
Test status
Simulation time 45752565372 ps
CPU time 25.54 seconds
Started Jun 06 12:59:58 PM PDT 24
Finished Jun 06 01:00:24 PM PDT 24
Peak memory 200336 kb
Host smart-95a43ed2-efff-4325-bc6a-a655ee4a184e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113026458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.113026458
Directory /workspace/27.uart_intr/latest

Test location /workspace/coverage/default/27.uart_long_xfer_wo_dly.1383079139
Short name T409
Test name
Test status
Simulation time 126043170854 ps
CPU time 276.31 seconds
Started Jun 06 12:59:56 PM PDT 24
Finished Jun 06 01:04:34 PM PDT 24
Peak memory 200372 kb
Host smart-19ad9dbf-1d37-446b-b817-73aa7f770eec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1383079139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.1383079139
Directory /workspace/27.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/27.uart_loopback.2143078514
Short name T84
Test name
Test status
Simulation time 3963901866 ps
CPU time 6.99 seconds
Started Jun 06 12:59:54 PM PDT 24
Finished Jun 06 01:00:03 PM PDT 24
Peak memory 199220 kb
Host smart-4c7e997c-8503-45cf-95ae-8249be90f62f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143078514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_loopback.2143078514
Directory /workspace/27.uart_loopback/latest

Test location /workspace/coverage/default/27.uart_noise_filter.2102017440
Short name T638
Test name
Test status
Simulation time 166102202397 ps
CPU time 76.53 seconds
Started Jun 06 12:59:55 PM PDT 24
Finished Jun 06 01:01:13 PM PDT 24
Peak memory 208752 kb
Host smart-6923c69d-abc3-4fe0-ac81-7e0151d31d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102017440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_noise_filter.2102017440
Directory /workspace/27.uart_noise_filter/latest

Test location /workspace/coverage/default/27.uart_perf.2931752584
Short name T466
Test name
Test status
Simulation time 25477443953 ps
CPU time 1503.51 seconds
Started Jun 06 12:59:56 PM PDT 24
Finished Jun 06 01:25:01 PM PDT 24
Peak memory 200380 kb
Host smart-69207fd7-abb7-4539-a976-865727bf8c4d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2931752584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.2931752584
Directory /workspace/27.uart_perf/latest

Test location /workspace/coverage/default/27.uart_rx_oversample.489105924
Short name T942
Test name
Test status
Simulation time 5037563309 ps
CPU time 10.66 seconds
Started Jun 06 12:59:53 PM PDT 24
Finished Jun 06 01:00:04 PM PDT 24
Peak memory 198576 kb
Host smart-ca9d7fcb-75ea-4501-9d1a-6bbc717a131f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=489105924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.489105924
Directory /workspace/27.uart_rx_oversample/latest

Test location /workspace/coverage/default/27.uart_rx_parity_err.1427093127
Short name T513
Test name
Test status
Simulation time 92104350523 ps
CPU time 34.87 seconds
Started Jun 06 12:59:54 PM PDT 24
Finished Jun 06 01:00:31 PM PDT 24
Peak memory 200216 kb
Host smart-ec8bdae8-bb53-43a4-9c42-4a248d4ddcc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427093127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.1427093127
Directory /workspace/27.uart_rx_parity_err/latest

Test location /workspace/coverage/default/27.uart_rx_start_bit_filter.4143750393
Short name T535
Test name
Test status
Simulation time 39515485387 ps
CPU time 14.98 seconds
Started Jun 06 12:59:57 PM PDT 24
Finished Jun 06 01:00:13 PM PDT 24
Peak memory 196676 kb
Host smart-11c16a6f-9ef3-4c52-8e5e-1db52da3fe0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143750393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.4143750393
Directory /workspace/27.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/27.uart_smoke.3652221883
Short name T773
Test name
Test status
Simulation time 5292900959 ps
CPU time 14.35 seconds
Started Jun 06 12:59:53 PM PDT 24
Finished Jun 06 01:00:09 PM PDT 24
Peak memory 200048 kb
Host smart-0dc4ff5b-2a68-4fad-9dc6-b8b24bdaac56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652221883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_smoke.3652221883
Directory /workspace/27.uart_smoke/latest

Test location /workspace/coverage/default/27.uart_stress_all.1354184268
Short name T170
Test name
Test status
Simulation time 480666879033 ps
CPU time 122.53 seconds
Started Jun 06 12:59:56 PM PDT 24
Finished Jun 06 01:02:00 PM PDT 24
Peak memory 200332 kb
Host smart-d8a41cb6-8d04-451f-868d-540c9dfaf485
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354184268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.1354184268
Directory /workspace/27.uart_stress_all/latest

Test location /workspace/coverage/default/27.uart_stress_all_with_rand_reset.3833627806
Short name T622
Test name
Test status
Simulation time 129345589583 ps
CPU time 2444.07 seconds
Started Jun 06 12:59:57 PM PDT 24
Finished Jun 06 01:40:42 PM PDT 24
Peak memory 233544 kb
Host smart-53c03a27-84e7-4cf6-a9ba-28009ff5581b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833627806 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 27.uart_stress_all_with_rand_reset.3833627806
Directory /workspace/27.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.uart_tx_ovrd.2234901402
Short name T926
Test name
Test status
Simulation time 6659352856 ps
CPU time 15.45 seconds
Started Jun 06 12:59:54 PM PDT 24
Finished Jun 06 01:00:12 PM PDT 24
Peak memory 199796 kb
Host smart-224ab741-1c03-490f-bb8d-d27cb5664416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234901402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.2234901402
Directory /workspace/27.uart_tx_ovrd/latest

Test location /workspace/coverage/default/27.uart_tx_rx.3195648290
Short name T464
Test name
Test status
Simulation time 45993238454 ps
CPU time 43.57 seconds
Started Jun 06 12:59:54 PM PDT 24
Finished Jun 06 01:00:40 PM PDT 24
Peak memory 200068 kb
Host smart-34865f6a-21c1-43d6-956a-f0d19e7d8c48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195648290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.3195648290
Directory /workspace/27.uart_tx_rx/latest

Test location /workspace/coverage/default/271.uart_fifo_reset.2114294484
Short name T475
Test name
Test status
Simulation time 22112575949 ps
CPU time 37.79 seconds
Started Jun 06 01:03:39 PM PDT 24
Finished Jun 06 01:04:18 PM PDT 24
Peak memory 200328 kb
Host smart-7733e0d2-0dc5-45ef-ab4d-2ae70fca5835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114294484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.2114294484
Directory /workspace/271.uart_fifo_reset/latest

Test location /workspace/coverage/default/272.uart_fifo_reset.3181388599
Short name T453
Test name
Test status
Simulation time 60982199094 ps
CPU time 114.35 seconds
Started Jun 06 01:03:40 PM PDT 24
Finished Jun 06 01:05:36 PM PDT 24
Peak memory 200400 kb
Host smart-e48341bf-2a88-4ac7-b593-eadfd3b3c9e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181388599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.3181388599
Directory /workspace/272.uart_fifo_reset/latest

Test location /workspace/coverage/default/273.uart_fifo_reset.4091420372
Short name T1148
Test name
Test status
Simulation time 14014285381 ps
CPU time 21.87 seconds
Started Jun 06 01:03:41 PM PDT 24
Finished Jun 06 01:04:04 PM PDT 24
Peak memory 200376 kb
Host smart-be96d8ba-5fa4-4e22-8c3c-8f3d08df2fd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091420372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.4091420372
Directory /workspace/273.uart_fifo_reset/latest

Test location /workspace/coverage/default/274.uart_fifo_reset.4262268079
Short name T48
Test name
Test status
Simulation time 223361890798 ps
CPU time 739.29 seconds
Started Jun 06 01:03:40 PM PDT 24
Finished Jun 06 01:16:01 PM PDT 24
Peak memory 200364 kb
Host smart-fa29bd9b-0bbb-468e-a58a-04f909455905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262268079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.4262268079
Directory /workspace/274.uart_fifo_reset/latest

Test location /workspace/coverage/default/275.uart_fifo_reset.1099888824
Short name T274
Test name
Test status
Simulation time 33162440555 ps
CPU time 20.78 seconds
Started Jun 06 01:03:43 PM PDT 24
Finished Jun 06 01:04:05 PM PDT 24
Peak memory 200396 kb
Host smart-f9ae6c18-a9f1-4d9e-976b-5ce473341df3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099888824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.1099888824
Directory /workspace/275.uart_fifo_reset/latest

Test location /workspace/coverage/default/276.uart_fifo_reset.298627733
Short name T208
Test name
Test status
Simulation time 26836020481 ps
CPU time 41.28 seconds
Started Jun 06 01:03:45 PM PDT 24
Finished Jun 06 01:04:28 PM PDT 24
Peak memory 200408 kb
Host smart-a035633f-d3fe-4741-8a7a-c8e03449666f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298627733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.298627733
Directory /workspace/276.uart_fifo_reset/latest

Test location /workspace/coverage/default/277.uart_fifo_reset.2472240710
Short name T951
Test name
Test status
Simulation time 20840481064 ps
CPU time 36.83 seconds
Started Jun 06 01:03:46 PM PDT 24
Finished Jun 06 01:04:24 PM PDT 24
Peak memory 200340 kb
Host smart-7c70f107-b1cb-4f81-8cf7-dff87c06ac7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472240710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.2472240710
Directory /workspace/277.uart_fifo_reset/latest

Test location /workspace/coverage/default/278.uart_fifo_reset.3954758551
Short name T523
Test name
Test status
Simulation time 147155471310 ps
CPU time 56.05 seconds
Started Jun 06 01:03:44 PM PDT 24
Finished Jun 06 01:04:41 PM PDT 24
Peak memory 200184 kb
Host smart-98a70f3e-bcf2-4171-914c-c838d8e81c52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954758551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.3954758551
Directory /workspace/278.uart_fifo_reset/latest

Test location /workspace/coverage/default/279.uart_fifo_reset.366629400
Short name T1124
Test name
Test status
Simulation time 22171460188 ps
CPU time 36.14 seconds
Started Jun 06 01:03:44 PM PDT 24
Finished Jun 06 01:04:21 PM PDT 24
Peak memory 200336 kb
Host smart-47035f22-43d8-4c90-bfea-54f5dd3ee33f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366629400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.366629400
Directory /workspace/279.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_alert_test.2939955909
Short name T394
Test name
Test status
Simulation time 26969505 ps
CPU time 0.56 seconds
Started Jun 06 01:00:01 PM PDT 24
Finished Jun 06 01:00:03 PM PDT 24
Peak memory 195612 kb
Host smart-d5447ef6-8752-481c-be6b-b4f58bf92dbf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939955909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.2939955909
Directory /workspace/28.uart_alert_test/latest

Test location /workspace/coverage/default/28.uart_fifo_full.1756728397
Short name T50
Test name
Test status
Simulation time 143841760574 ps
CPU time 179.93 seconds
Started Jun 06 12:59:58 PM PDT 24
Finished Jun 06 01:02:59 PM PDT 24
Peak memory 200300 kb
Host smart-a59e73ea-14b1-4f01-852a-87d1aca83705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756728397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.1756728397
Directory /workspace/28.uart_fifo_full/latest

Test location /workspace/coverage/default/28.uart_fifo_overflow.795957129
Short name T662
Test name
Test status
Simulation time 64519366313 ps
CPU time 19.46 seconds
Started Jun 06 12:59:56 PM PDT 24
Finished Jun 06 01:00:17 PM PDT 24
Peak memory 199756 kb
Host smart-4a09d8f9-630b-4069-9c4b-f94452bff121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795957129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.795957129
Directory /workspace/28.uart_fifo_overflow/latest

Test location /workspace/coverage/default/28.uart_fifo_reset.2662509110
Short name T903
Test name
Test status
Simulation time 25253033603 ps
CPU time 40.03 seconds
Started Jun 06 12:59:56 PM PDT 24
Finished Jun 06 01:00:38 PM PDT 24
Peak memory 200304 kb
Host smart-83daee9a-5d4a-44ad-91ee-f01e2f9794e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662509110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.2662509110
Directory /workspace/28.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_intr.1981254297
Short name T366
Test name
Test status
Simulation time 152151375525 ps
CPU time 185.53 seconds
Started Jun 06 12:59:57 PM PDT 24
Finished Jun 06 01:03:04 PM PDT 24
Peak memory 200344 kb
Host smart-e869abf1-107c-4d89-b85f-efbec1570602
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981254297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.1981254297
Directory /workspace/28.uart_intr/latest

Test location /workspace/coverage/default/28.uart_long_xfer_wo_dly.1812827315
Short name T901
Test name
Test status
Simulation time 102954370764 ps
CPU time 163.94 seconds
Started Jun 06 01:00:00 PM PDT 24
Finished Jun 06 01:02:46 PM PDT 24
Peak memory 200276 kb
Host smart-b88fb92a-3b0b-4ce4-84d3-1da8246698e7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1812827315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.1812827315
Directory /workspace/28.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/28.uart_loopback.2414502640
Short name T702
Test name
Test status
Simulation time 7435482812 ps
CPU time 15.67 seconds
Started Jun 06 12:59:57 PM PDT 24
Finished Jun 06 01:00:14 PM PDT 24
Peak memory 200216 kb
Host smart-de042457-7e15-4fa7-a2df-d91d4db1a765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414502640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_loopback.2414502640
Directory /workspace/28.uart_loopback/latest

Test location /workspace/coverage/default/28.uart_noise_filter.2850243333
Short name T986
Test name
Test status
Simulation time 82831546987 ps
CPU time 117.71 seconds
Started Jun 06 12:59:56 PM PDT 24
Finished Jun 06 01:01:55 PM PDT 24
Peak memory 200520 kb
Host smart-dcd7f506-0142-4e80-a2b8-3df1c7f58433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850243333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_noise_filter.2850243333
Directory /workspace/28.uart_noise_filter/latest

Test location /workspace/coverage/default/28.uart_perf.3968353654
Short name T571
Test name
Test status
Simulation time 14639117226 ps
CPU time 430.89 seconds
Started Jun 06 12:59:57 PM PDT 24
Finished Jun 06 01:07:09 PM PDT 24
Peak memory 200232 kb
Host smart-1975a35f-ee40-4bc3-8787-c1ebec12c222
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3968353654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.3968353654
Directory /workspace/28.uart_perf/latest

Test location /workspace/coverage/default/28.uart_rx_oversample.1353202116
Short name T909
Test name
Test status
Simulation time 5828826604 ps
CPU time 52.5 seconds
Started Jun 06 12:59:56 PM PDT 24
Finished Jun 06 01:00:50 PM PDT 24
Peak memory 199548 kb
Host smart-00bd7074-9ad8-4ba0-a8b1-6e489ddbcc20
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1353202116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.1353202116
Directory /workspace/28.uart_rx_oversample/latest

Test location /workspace/coverage/default/28.uart_rx_parity_err.875698702
Short name T758
Test name
Test status
Simulation time 19793424580 ps
CPU time 19.55 seconds
Started Jun 06 12:59:56 PM PDT 24
Finished Jun 06 01:00:17 PM PDT 24
Peak memory 200296 kb
Host smart-ef8aa2a7-c4a7-4448-9264-146cef38a27c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875698702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.875698702
Directory /workspace/28.uart_rx_parity_err/latest

Test location /workspace/coverage/default/28.uart_rx_start_bit_filter.1522277150
Short name T754
Test name
Test status
Simulation time 33237022909 ps
CPU time 14.19 seconds
Started Jun 06 12:59:55 PM PDT 24
Finished Jun 06 01:00:11 PM PDT 24
Peak memory 196632 kb
Host smart-e2392a32-dd58-456f-9d5a-1d0de770c20d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522277150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.1522277150
Directory /workspace/28.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/28.uart_smoke.80185632
Short name T10
Test name
Test status
Simulation time 6282566331 ps
CPU time 37.7 seconds
Started Jun 06 12:59:54 PM PDT 24
Finished Jun 06 01:00:33 PM PDT 24
Peak memory 200144 kb
Host smart-198f95e0-e468-4bbb-90a7-ac966164d5f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80185632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_smoke.80185632
Directory /workspace/28.uart_smoke/latest

Test location /workspace/coverage/default/28.uart_stress_all.1343427303
Short name T1004
Test name
Test status
Simulation time 76587792018 ps
CPU time 286.71 seconds
Started Jun 06 01:00:04 PM PDT 24
Finished Jun 06 01:04:52 PM PDT 24
Peak memory 200280 kb
Host smart-7fc7ffff-b9a2-4142-9f17-876425aa8b1f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343427303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.1343427303
Directory /workspace/28.uart_stress_all/latest

Test location /workspace/coverage/default/28.uart_stress_all_with_rand_reset.639645454
Short name T693
Test name
Test status
Simulation time 280131592526 ps
CPU time 632.91 seconds
Started Jun 06 01:00:07 PM PDT 24
Finished Jun 06 01:10:41 PM PDT 24
Peak memory 225296 kb
Host smart-24d8e920-43be-4e5a-8144-04c4a49d867c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639645454 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 28.uart_stress_all_with_rand_reset.639645454
Directory /workspace/28.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.uart_tx_ovrd.3927760132
Short name T12
Test name
Test status
Simulation time 1040420819 ps
CPU time 3.04 seconds
Started Jun 06 12:59:56 PM PDT 24
Finished Jun 06 01:00:01 PM PDT 24
Peak memory 199080 kb
Host smart-7844faba-5d0a-4ba7-881c-95f6b6248145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927760132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.3927760132
Directory /workspace/28.uart_tx_ovrd/latest

Test location /workspace/coverage/default/28.uart_tx_rx.1381779619
Short name T782
Test name
Test status
Simulation time 87159491752 ps
CPU time 19.2 seconds
Started Jun 06 12:59:54 PM PDT 24
Finished Jun 06 01:00:15 PM PDT 24
Peak memory 200360 kb
Host smart-58270270-1861-48b3-af69-d9e13bd9c9e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381779619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.1381779619
Directory /workspace/28.uart_tx_rx/latest

Test location /workspace/coverage/default/280.uart_fifo_reset.938757580
Short name T1045
Test name
Test status
Simulation time 34082772669 ps
CPU time 61.11 seconds
Started Jun 06 01:03:45 PM PDT 24
Finished Jun 06 01:04:47 PM PDT 24
Peak memory 200360 kb
Host smart-cd4a921e-4610-4492-a410-0e696d88e29d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938757580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.938757580
Directory /workspace/280.uart_fifo_reset/latest

Test location /workspace/coverage/default/281.uart_fifo_reset.1685289999
Short name T561
Test name
Test status
Simulation time 97564277608 ps
CPU time 13.23 seconds
Started Jun 06 01:03:45 PM PDT 24
Finished Jun 06 01:03:59 PM PDT 24
Peak memory 200244 kb
Host smart-281c2324-9940-485e-bd2b-efa0bb66a210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685289999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.1685289999
Directory /workspace/281.uart_fifo_reset/latest

Test location /workspace/coverage/default/282.uart_fifo_reset.3410576239
Short name T160
Test name
Test status
Simulation time 175821499359 ps
CPU time 107.11 seconds
Started Jun 06 01:03:47 PM PDT 24
Finished Jun 06 01:05:35 PM PDT 24
Peak memory 200376 kb
Host smart-44b4489f-4763-4940-b2c8-8af8715211ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410576239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.3410576239
Directory /workspace/282.uart_fifo_reset/latest

Test location /workspace/coverage/default/283.uart_fifo_reset.3076004486
Short name T202
Test name
Test status
Simulation time 102862075470 ps
CPU time 29.41 seconds
Started Jun 06 01:03:44 PM PDT 24
Finished Jun 06 01:04:15 PM PDT 24
Peak memory 200268 kb
Host smart-fb0590b5-daad-4a61-a028-6009e7adedc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076004486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.3076004486
Directory /workspace/283.uart_fifo_reset/latest

Test location /workspace/coverage/default/284.uart_fifo_reset.2787746207
Short name T206
Test name
Test status
Simulation time 19697072546 ps
CPU time 30.65 seconds
Started Jun 06 01:03:47 PM PDT 24
Finished Jun 06 01:04:18 PM PDT 24
Peak memory 200328 kb
Host smart-3d317ccd-154b-470c-a262-2ef876740be6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787746207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.2787746207
Directory /workspace/284.uart_fifo_reset/latest

Test location /workspace/coverage/default/285.uart_fifo_reset.3074649010
Short name T831
Test name
Test status
Simulation time 42837973146 ps
CPU time 35.76 seconds
Started Jun 06 01:03:44 PM PDT 24
Finished Jun 06 01:04:20 PM PDT 24
Peak memory 200252 kb
Host smart-e6d5d425-cdb4-411a-b4da-e56059b13f94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074649010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.3074649010
Directory /workspace/285.uart_fifo_reset/latest

Test location /workspace/coverage/default/286.uart_fifo_reset.3663963378
Short name T244
Test name
Test status
Simulation time 97047108419 ps
CPU time 40.11 seconds
Started Jun 06 01:03:49 PM PDT 24
Finished Jun 06 01:04:29 PM PDT 24
Peak memory 200316 kb
Host smart-d6c1fe91-c15c-4c85-a379-a46291c778ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663963378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.3663963378
Directory /workspace/286.uart_fifo_reset/latest

Test location /workspace/coverage/default/287.uart_fifo_reset.886919177
Short name T1071
Test name
Test status
Simulation time 27874954891 ps
CPU time 40.8 seconds
Started Jun 06 01:03:45 PM PDT 24
Finished Jun 06 01:04:26 PM PDT 24
Peak memory 200012 kb
Host smart-9e4d838a-556a-4df8-883b-a532539137d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886919177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.886919177
Directory /workspace/287.uart_fifo_reset/latest

Test location /workspace/coverage/default/288.uart_fifo_reset.3280611590
Short name T765
Test name
Test status
Simulation time 110748241162 ps
CPU time 65.7 seconds
Started Jun 06 01:03:46 PM PDT 24
Finished Jun 06 01:04:52 PM PDT 24
Peak memory 200252 kb
Host smart-5f5337c4-94e4-4b3c-acfd-4e255ee31d36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280611590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.3280611590
Directory /workspace/288.uart_fifo_reset/latest

Test location /workspace/coverage/default/289.uart_fifo_reset.3236049977
Short name T253
Test name
Test status
Simulation time 42916803728 ps
CPU time 59.27 seconds
Started Jun 06 01:03:49 PM PDT 24
Finished Jun 06 01:04:49 PM PDT 24
Peak memory 200320 kb
Host smart-550bcb8c-6b33-488a-8c06-6b22b528d574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236049977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.3236049977
Directory /workspace/289.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_alert_test.724142766
Short name T387
Test name
Test status
Simulation time 50701330 ps
CPU time 0.53 seconds
Started Jun 06 01:00:00 PM PDT 24
Finished Jun 06 01:00:01 PM PDT 24
Peak memory 195944 kb
Host smart-c6add940-b6d4-48ac-a1ad-5cca915d06e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724142766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.724142766
Directory /workspace/29.uart_alert_test/latest

Test location /workspace/coverage/default/29.uart_fifo_full.3775997903
Short name T772
Test name
Test status
Simulation time 43013978471 ps
CPU time 37.01 seconds
Started Jun 06 01:00:01 PM PDT 24
Finished Jun 06 01:00:39 PM PDT 24
Peak memory 200312 kb
Host smart-e4759eab-9d28-4907-bcb4-8b895b06c4f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775997903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.3775997903
Directory /workspace/29.uart_fifo_full/latest

Test location /workspace/coverage/default/29.uart_fifo_overflow.3447413952
Short name T374
Test name
Test status
Simulation time 38407070963 ps
CPU time 8.45 seconds
Started Jun 06 01:00:06 PM PDT 24
Finished Jun 06 01:00:15 PM PDT 24
Peak memory 200352 kb
Host smart-aadb0ce2-fcd2-4dd8-acdd-72722b08c201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447413952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.3447413952
Directory /workspace/29.uart_fifo_overflow/latest

Test location /workspace/coverage/default/29.uart_fifo_reset.2336837677
Short name T53
Test name
Test status
Simulation time 12651877892 ps
CPU time 21.44 seconds
Started Jun 06 01:00:02 PM PDT 24
Finished Jun 06 01:00:25 PM PDT 24
Peak memory 200344 kb
Host smart-e20c63ca-bdce-4d14-8fcf-aae01f9fbaa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336837677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.2336837677
Directory /workspace/29.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_intr.2663377668
Short name T644
Test name
Test status
Simulation time 43283274117 ps
CPU time 18.53 seconds
Started Jun 06 01:00:03 PM PDT 24
Finished Jun 06 01:00:23 PM PDT 24
Peak memory 199292 kb
Host smart-532a53e1-7bc2-4031-8316-029bd8ecdba1
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663377668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.2663377668
Directory /workspace/29.uart_intr/latest

Test location /workspace/coverage/default/29.uart_long_xfer_wo_dly.3427946943
Short name T459
Test name
Test status
Simulation time 118853803274 ps
CPU time 291.95 seconds
Started Jun 06 01:00:04 PM PDT 24
Finished Jun 06 01:04:57 PM PDT 24
Peak memory 200332 kb
Host smart-f42a00a1-49c8-42fa-86cf-91e06e7f0fbd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3427946943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.3427946943
Directory /workspace/29.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/29.uart_loopback.1399566089
Short name T924
Test name
Test status
Simulation time 12677125236 ps
CPU time 12.92 seconds
Started Jun 06 01:00:00 PM PDT 24
Finished Jun 06 01:00:14 PM PDT 24
Peak memory 200272 kb
Host smart-854a9a26-4219-4113-a767-1dab93855195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399566089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_loopback.1399566089
Directory /workspace/29.uart_loopback/latest

Test location /workspace/coverage/default/29.uart_noise_filter.843577718
Short name T612
Test name
Test status
Simulation time 93089032820 ps
CPU time 224.3 seconds
Started Jun 06 01:00:01 PM PDT 24
Finished Jun 06 01:03:46 PM PDT 24
Peak memory 200432 kb
Host smart-71e674b0-7d3a-4180-952c-521e4b4cee37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843577718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_noise_filter.843577718
Directory /workspace/29.uart_noise_filter/latest

Test location /workspace/coverage/default/29.uart_perf.598264603
Short name T625
Test name
Test status
Simulation time 9592422430 ps
CPU time 274.22 seconds
Started Jun 06 01:00:01 PM PDT 24
Finished Jun 06 01:04:36 PM PDT 24
Peak memory 200312 kb
Host smart-c3972cad-0317-4a64-9a35-5eeb748bde76
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=598264603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.598264603
Directory /workspace/29.uart_perf/latest

Test location /workspace/coverage/default/29.uart_rx_oversample.2539766391
Short name T1162
Test name
Test status
Simulation time 6135319122 ps
CPU time 53.84 seconds
Started Jun 06 12:59:59 PM PDT 24
Finished Jun 06 01:00:54 PM PDT 24
Peak memory 198324 kb
Host smart-5adc7635-4c89-4141-9efa-a836d07a7385
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2539766391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.2539766391
Directory /workspace/29.uart_rx_oversample/latest

Test location /workspace/coverage/default/29.uart_rx_parity_err.1227472589
Short name T841
Test name
Test status
Simulation time 97320785080 ps
CPU time 25.44 seconds
Started Jun 06 01:00:06 PM PDT 24
Finished Jun 06 01:00:33 PM PDT 24
Peak memory 199932 kb
Host smart-d3d158ee-a6a8-4d27-a16e-4b965c7a0c46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227472589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.1227472589
Directory /workspace/29.uart_rx_parity_err/latest

Test location /workspace/coverage/default/29.uart_rx_start_bit_filter.3190030345
Short name T886
Test name
Test status
Simulation time 35670723192 ps
CPU time 26.66 seconds
Started Jun 06 01:00:00 PM PDT 24
Finished Jun 06 01:00:28 PM PDT 24
Peak memory 196512 kb
Host smart-aa2e5d68-f02c-43d7-8c5a-26779f2a5954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190030345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.3190030345
Directory /workspace/29.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/29.uart_smoke.3193035481
Short name T356
Test name
Test status
Simulation time 261890406 ps
CPU time 1.35 seconds
Started Jun 06 01:00:06 PM PDT 24
Finished Jun 06 01:00:08 PM PDT 24
Peak memory 198892 kb
Host smart-898a977b-c7e7-4617-a198-9606d8e00d5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193035481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_smoke.3193035481
Directory /workspace/29.uart_smoke/latest

Test location /workspace/coverage/default/29.uart_stress_all_with_rand_reset.726822931
Short name T66
Test name
Test status
Simulation time 203520310251 ps
CPU time 472.34 seconds
Started Jun 06 01:00:06 PM PDT 24
Finished Jun 06 01:07:59 PM PDT 24
Peak memory 216896 kb
Host smart-33e06014-b909-4899-aebe-77cdbd644a71
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726822931 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 29.uart_stress_all_with_rand_reset.726822931
Directory /workspace/29.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.uart_tx_ovrd.3904078583
Short name T846
Test name
Test status
Simulation time 1335498360 ps
CPU time 2.11 seconds
Started Jun 06 01:00:00 PM PDT 24
Finished Jun 06 01:00:03 PM PDT 24
Peak memory 198956 kb
Host smart-53437a63-db25-4f1c-91f2-88623a2614b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904078583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.3904078583
Directory /workspace/29.uart_tx_ovrd/latest

Test location /workspace/coverage/default/29.uart_tx_rx.2284515355
Short name T713
Test name
Test status
Simulation time 92504102457 ps
CPU time 25.06 seconds
Started Jun 06 01:00:03 PM PDT 24
Finished Jun 06 01:00:29 PM PDT 24
Peak memory 200376 kb
Host smart-bdea2181-afa3-4f1b-9be5-c4f4b1c5a705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284515355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.2284515355
Directory /workspace/29.uart_tx_rx/latest

Test location /workspace/coverage/default/290.uart_fifo_reset.4166740237
Short name T537
Test name
Test status
Simulation time 18495392729 ps
CPU time 14.69 seconds
Started Jun 06 01:03:49 PM PDT 24
Finished Jun 06 01:04:05 PM PDT 24
Peak memory 200284 kb
Host smart-0a7798b9-becb-493d-8275-cb1ad2c74ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166740237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.4166740237
Directory /workspace/290.uart_fifo_reset/latest

Test location /workspace/coverage/default/291.uart_fifo_reset.2519221324
Short name T325
Test name
Test status
Simulation time 68443423855 ps
CPU time 113.66 seconds
Started Jun 06 01:03:47 PM PDT 24
Finished Jun 06 01:05:42 PM PDT 24
Peak memory 200276 kb
Host smart-09e6a889-9991-4094-be6a-1429d9bb4cff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519221324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.2519221324
Directory /workspace/291.uart_fifo_reset/latest

Test location /workspace/coverage/default/292.uart_fifo_reset.1234542278
Short name T184
Test name
Test status
Simulation time 104334832680 ps
CPU time 74.79 seconds
Started Jun 06 01:03:45 PM PDT 24
Finished Jun 06 01:05:01 PM PDT 24
Peak memory 200264 kb
Host smart-3861aa94-70da-400f-ba8b-4c7dc17d6772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234542278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.1234542278
Directory /workspace/292.uart_fifo_reset/latest

Test location /workspace/coverage/default/293.uart_fifo_reset.1735550741
Short name T562
Test name
Test status
Simulation time 44664289399 ps
CPU time 37.53 seconds
Started Jun 06 01:03:45 PM PDT 24
Finished Jun 06 01:04:24 PM PDT 24
Peak memory 200344 kb
Host smart-c182ad4a-7410-4b46-8bad-f2ec48d64afb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735550741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.1735550741
Directory /workspace/293.uart_fifo_reset/latest

Test location /workspace/coverage/default/294.uart_fifo_reset.658758543
Short name T49
Test name
Test status
Simulation time 139734052696 ps
CPU time 52.23 seconds
Started Jun 06 01:03:46 PM PDT 24
Finished Jun 06 01:04:39 PM PDT 24
Peak memory 200408 kb
Host smart-9163df57-452d-4382-bc89-371839962a9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658758543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.658758543
Directory /workspace/294.uart_fifo_reset/latest

Test location /workspace/coverage/default/296.uart_fifo_reset.2113703762
Short name T529
Test name
Test status
Simulation time 71247844414 ps
CPU time 278.99 seconds
Started Jun 06 01:03:46 PM PDT 24
Finished Jun 06 01:08:26 PM PDT 24
Peak memory 200268 kb
Host smart-8085418c-6c8a-4fae-887d-e0acc69ac6e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113703762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.2113703762
Directory /workspace/296.uart_fifo_reset/latest

Test location /workspace/coverage/default/297.uart_fifo_reset.3460529795
Short name T823
Test name
Test status
Simulation time 172037817483 ps
CPU time 102.61 seconds
Started Jun 06 01:03:48 PM PDT 24
Finished Jun 06 01:05:31 PM PDT 24
Peak memory 200248 kb
Host smart-a9f6d07e-b664-4b87-8015-37f0d51b2e5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460529795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.3460529795
Directory /workspace/297.uart_fifo_reset/latest

Test location /workspace/coverage/default/298.uart_fifo_reset.3119694687
Short name T1084
Test name
Test status
Simulation time 142317659952 ps
CPU time 233.35 seconds
Started Jun 06 01:03:49 PM PDT 24
Finished Jun 06 01:07:43 PM PDT 24
Peak memory 200340 kb
Host smart-87eb512e-4750-4001-ac80-655c7a74e201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119694687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.3119694687
Directory /workspace/298.uart_fifo_reset/latest

Test location /workspace/coverage/default/299.uart_fifo_reset.601104114
Short name T747
Test name
Test status
Simulation time 109748516776 ps
CPU time 48.21 seconds
Started Jun 06 01:03:53 PM PDT 24
Finished Jun 06 01:04:42 PM PDT 24
Peak memory 200324 kb
Host smart-ae63e73d-c407-4374-a29f-61b5bdd5d9f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601104114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.601104114
Directory /workspace/299.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_alert_test.2744481304
Short name T957
Test name
Test status
Simulation time 22039287 ps
CPU time 0.55 seconds
Started Jun 06 12:58:05 PM PDT 24
Finished Jun 06 12:58:06 PM PDT 24
Peak memory 195192 kb
Host smart-2eeb19f6-e349-4901-8744-d71752b66aaf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744481304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.2744481304
Directory /workspace/3.uart_alert_test/latest

Test location /workspace/coverage/default/3.uart_fifo_full.3906487962
Short name T1173
Test name
Test status
Simulation time 112651760043 ps
CPU time 168.43 seconds
Started Jun 06 12:58:00 PM PDT 24
Finished Jun 06 01:00:50 PM PDT 24
Peak memory 200340 kb
Host smart-0a43c5e9-e573-45b9-867c-8345024c0088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906487962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.3906487962
Directory /workspace/3.uart_fifo_full/latest

Test location /workspace/coverage/default/3.uart_fifo_overflow.2069508066
Short name T922
Test name
Test status
Simulation time 60347886678 ps
CPU time 28.27 seconds
Started Jun 06 12:58:04 PM PDT 24
Finished Jun 06 12:58:33 PM PDT 24
Peak memory 200228 kb
Host smart-ff7c0598-9b68-4339-b858-83c40b68b11e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069508066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.2069508066
Directory /workspace/3.uart_fifo_overflow/latest

Test location /workspace/coverage/default/3.uart_fifo_reset.2073811987
Short name T796
Test name
Test status
Simulation time 47539091350 ps
CPU time 412.88 seconds
Started Jun 06 12:58:03 PM PDT 24
Finished Jun 06 01:04:57 PM PDT 24
Peak memory 200352 kb
Host smart-1e6d77b2-6b2e-4810-8846-2e281f90217e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073811987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.2073811987
Directory /workspace/3.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_intr.1060142470
Short name T650
Test name
Test status
Simulation time 26789502588 ps
CPU time 12.24 seconds
Started Jun 06 12:58:01 PM PDT 24
Finished Jun 06 12:58:15 PM PDT 24
Peak memory 200336 kb
Host smart-9a6b244e-010d-4e8b-bd3d-f7096feba60f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060142470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.1060142470
Directory /workspace/3.uart_intr/latest

Test location /workspace/coverage/default/3.uart_long_xfer_wo_dly.2569851130
Short name T341
Test name
Test status
Simulation time 103179186392 ps
CPU time 388.43 seconds
Started Jun 06 12:58:06 PM PDT 24
Finished Jun 06 01:04:35 PM PDT 24
Peak memory 200336 kb
Host smart-0477f4b0-2ddd-44b7-b05e-d26e2d554e57
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2569851130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.2569851130
Directory /workspace/3.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/3.uart_loopback.1929210223
Short name T727
Test name
Test status
Simulation time 1784487954 ps
CPU time 2.39 seconds
Started Jun 06 12:58:04 PM PDT 24
Finished Jun 06 12:58:07 PM PDT 24
Peak memory 197936 kb
Host smart-f9f8e5b5-d631-4613-a202-e10645d318f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929210223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_loopback.1929210223
Directory /workspace/3.uart_loopback/latest

Test location /workspace/coverage/default/3.uart_noise_filter.2962895999
Short name T651
Test name
Test status
Simulation time 179647107332 ps
CPU time 75.56 seconds
Started Jun 06 12:58:01 PM PDT 24
Finished Jun 06 12:59:18 PM PDT 24
Peak memory 208932 kb
Host smart-63596674-3c53-4778-b7f5-1e86676015b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962895999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_noise_filter.2962895999
Directory /workspace/3.uart_noise_filter/latest

Test location /workspace/coverage/default/3.uart_perf.3827529197
Short name T285
Test name
Test status
Simulation time 8461963886 ps
CPU time 504.36 seconds
Started Jun 06 12:58:03 PM PDT 24
Finished Jun 06 01:06:29 PM PDT 24
Peak memory 200388 kb
Host smart-371c656a-2b73-4540-b17e-6ab418cad416
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3827529197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.3827529197
Directory /workspace/3.uart_perf/latest

Test location /workspace/coverage/default/3.uart_rx_oversample.3278627861
Short name T900
Test name
Test status
Simulation time 5915347814 ps
CPU time 13.77 seconds
Started Jun 06 12:58:08 PM PDT 24
Finished Jun 06 12:58:23 PM PDT 24
Peak memory 198556 kb
Host smart-9450c4ad-e298-4c3d-a161-241368543832
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3278627861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.3278627861
Directory /workspace/3.uart_rx_oversample/latest

Test location /workspace/coverage/default/3.uart_rx_parity_err.250801651
Short name T955
Test name
Test status
Simulation time 20650569240 ps
CPU time 31.05 seconds
Started Jun 06 12:58:04 PM PDT 24
Finished Jun 06 12:58:36 PM PDT 24
Peak memory 200376 kb
Host smart-77fe54aa-ba7c-4314-95ea-a3f920de287b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250801651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.250801651
Directory /workspace/3.uart_rx_parity_err/latest

Test location /workspace/coverage/default/3.uart_rx_start_bit_filter.377695332
Short name T284
Test name
Test status
Simulation time 2954415869 ps
CPU time 5.18 seconds
Started Jun 06 12:58:02 PM PDT 24
Finished Jun 06 12:58:08 PM PDT 24
Peak memory 196184 kb
Host smart-f4685530-8fcc-458b-ab73-cc0adb0a2d85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377695332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.377695332
Directory /workspace/3.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/3.uart_sec_cm.3125840957
Short name T32
Test name
Test status
Simulation time 35671079 ps
CPU time 0.77 seconds
Started Jun 06 12:58:07 PM PDT 24
Finished Jun 06 12:58:09 PM PDT 24
Peak memory 218824 kb
Host smart-cea994d3-ad32-4038-a75d-b488034f8674
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125840957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.3125840957
Directory /workspace/3.uart_sec_cm/latest

Test location /workspace/coverage/default/3.uart_smoke.3543029148
Short name T405
Test name
Test status
Simulation time 5292624653 ps
CPU time 7.63 seconds
Started Jun 06 12:58:00 PM PDT 24
Finished Jun 06 12:58:09 PM PDT 24
Peak memory 199584 kb
Host smart-af014ed5-ddac-4d2e-960c-a8d3d188367a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543029148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_smoke.3543029148
Directory /workspace/3.uart_smoke/latest

Test location /workspace/coverage/default/3.uart_stress_all_with_rand_reset.1135268610
Short name T406
Test name
Test status
Simulation time 39624695144 ps
CPU time 647.72 seconds
Started Jun 06 12:58:08 PM PDT 24
Finished Jun 06 01:08:57 PM PDT 24
Peak memory 216876 kb
Host smart-34a5d92e-bbb0-4f04-947b-2671bbc30a63
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135268610 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.uart_stress_all_with_rand_reset.1135268610
Directory /workspace/3.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.uart_tx_ovrd.1129687178
Short name T548
Test name
Test status
Simulation time 783559523 ps
CPU time 2.46 seconds
Started Jun 06 12:58:03 PM PDT 24
Finished Jun 06 12:58:06 PM PDT 24
Peak memory 198880 kb
Host smart-4de8a8ec-86ff-485c-aedf-7fce15496e57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129687178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.1129687178
Directory /workspace/3.uart_tx_ovrd/latest

Test location /workspace/coverage/default/3.uart_tx_rx.1362244142
Short name T822
Test name
Test status
Simulation time 10679259026 ps
CPU time 8.69 seconds
Started Jun 06 12:58:07 PM PDT 24
Finished Jun 06 12:58:17 PM PDT 24
Peak memory 199124 kb
Host smart-6d73727e-7bc3-4236-b4f1-4ecd9d0ad2fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362244142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.1362244142
Directory /workspace/3.uart_tx_rx/latest

Test location /workspace/coverage/default/30.uart_alert_test.4150154979
Short name T611
Test name
Test status
Simulation time 13741109 ps
CPU time 0.57 seconds
Started Jun 06 01:00:10 PM PDT 24
Finished Jun 06 01:00:12 PM PDT 24
Peak memory 196032 kb
Host smart-184b090d-0d6a-4faa-b616-c60c123593aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150154979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.4150154979
Directory /workspace/30.uart_alert_test/latest

Test location /workspace/coverage/default/30.uart_fifo_full.2159526187
Short name T657
Test name
Test status
Simulation time 26341159780 ps
CPU time 44.02 seconds
Started Jun 06 01:00:02 PM PDT 24
Finished Jun 06 01:00:47 PM PDT 24
Peak memory 200300 kb
Host smart-c4781eef-5e00-43eb-b409-a659b37b22e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159526187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.2159526187
Directory /workspace/30.uart_fifo_full/latest

Test location /workspace/coverage/default/30.uart_fifo_overflow.679921928
Short name T173
Test name
Test status
Simulation time 142377797325 ps
CPU time 117.48 seconds
Started Jun 06 01:00:05 PM PDT 24
Finished Jun 06 01:02:04 PM PDT 24
Peak memory 200288 kb
Host smart-5ecbe73e-e0ef-4c0c-8356-575d69d619af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679921928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.679921928
Directory /workspace/30.uart_fifo_overflow/latest

Test location /workspace/coverage/default/30.uart_intr.3043569663
Short name T1168
Test name
Test status
Simulation time 7915797105 ps
CPU time 5.97 seconds
Started Jun 06 12:59:59 PM PDT 24
Finished Jun 06 01:00:06 PM PDT 24
Peak memory 200272 kb
Host smart-7623db06-13b9-448b-8817-d1dd61905889
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043569663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.3043569663
Directory /workspace/30.uart_intr/latest

Test location /workspace/coverage/default/30.uart_long_xfer_wo_dly.409446012
Short name T861
Test name
Test status
Simulation time 301828914976 ps
CPU time 251.09 seconds
Started Jun 06 01:00:10 PM PDT 24
Finished Jun 06 01:04:22 PM PDT 24
Peak memory 200108 kb
Host smart-1640fd7e-c28d-4c31-98c6-2e09837ec1a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=409446012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.409446012
Directory /workspace/30.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/30.uart_loopback.3402229914
Short name T674
Test name
Test status
Simulation time 8228912669 ps
CPU time 14.78 seconds
Started Jun 06 01:00:09 PM PDT 24
Finished Jun 06 01:00:25 PM PDT 24
Peak memory 200344 kb
Host smart-8fe6011b-beed-438d-92b6-c47240967b9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402229914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_loopback.3402229914
Directory /workspace/30.uart_loopback/latest

Test location /workspace/coverage/default/30.uart_noise_filter.2962155525
Short name T729
Test name
Test status
Simulation time 68279479512 ps
CPU time 28.79 seconds
Started Jun 06 01:00:06 PM PDT 24
Finished Jun 06 01:00:36 PM PDT 24
Peak memory 200532 kb
Host smart-a6810bfb-97d9-4da6-b75e-7c1814910728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962155525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_noise_filter.2962155525
Directory /workspace/30.uart_noise_filter/latest

Test location /workspace/coverage/default/30.uart_perf.2831031085
Short name T777
Test name
Test status
Simulation time 3447699805 ps
CPU time 118.87 seconds
Started Jun 06 01:00:09 PM PDT 24
Finished Jun 06 01:02:09 PM PDT 24
Peak memory 200308 kb
Host smart-f81bc834-ccf9-42fc-a201-999730257d2d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2831031085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.2831031085
Directory /workspace/30.uart_perf/latest

Test location /workspace/coverage/default/30.uart_rx_oversample.1945961718
Short name T402
Test name
Test status
Simulation time 2107955813 ps
CPU time 6.86 seconds
Started Jun 06 01:00:05 PM PDT 24
Finished Jun 06 01:00:13 PM PDT 24
Peak memory 198456 kb
Host smart-6e1a6f3b-95cb-4c10-a40d-a3b153907183
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1945961718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.1945961718
Directory /workspace/30.uart_rx_oversample/latest

Test location /workspace/coverage/default/30.uart_rx_parity_err.1799551446
Short name T144
Test name
Test status
Simulation time 27243902723 ps
CPU time 47.38 seconds
Started Jun 06 01:00:11 PM PDT 24
Finished Jun 06 01:01:00 PM PDT 24
Peak memory 200380 kb
Host smart-fcd4743c-0366-407c-9b79-6ee2d63e9d42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799551446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.1799551446
Directory /workspace/30.uart_rx_parity_err/latest

Test location /workspace/coverage/default/30.uart_rx_start_bit_filter.994671462
Short name T1024
Test name
Test status
Simulation time 2831083828 ps
CPU time 3.01 seconds
Started Jun 06 01:00:09 PM PDT 24
Finished Jun 06 01:00:13 PM PDT 24
Peak memory 196092 kb
Host smart-7a6b6e73-aefb-4104-81f1-26b65e9a0440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994671462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.994671462
Directory /workspace/30.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/30.uart_smoke.2504773001
Short name T589
Test name
Test status
Simulation time 650584014 ps
CPU time 1.54 seconds
Started Jun 06 01:00:01 PM PDT 24
Finished Jun 06 01:00:04 PM PDT 24
Peak memory 198840 kb
Host smart-c24532e2-11bb-43fd-b6ac-db02c66fbbe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504773001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_smoke.2504773001
Directory /workspace/30.uart_smoke/latest

Test location /workspace/coverage/default/30.uart_stress_all.3507206132
Short name T255
Test name
Test status
Simulation time 96724213928 ps
CPU time 96.75 seconds
Started Jun 06 01:00:09 PM PDT 24
Finished Jun 06 01:01:47 PM PDT 24
Peak memory 208760 kb
Host smart-217cd365-b44f-473b-b8bb-656dedb1a378
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507206132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.3507206132
Directory /workspace/30.uart_stress_all/latest

Test location /workspace/coverage/default/30.uart_stress_all_with_rand_reset.1267097026
Short name T132
Test name
Test status
Simulation time 8263163855 ps
CPU time 128.79 seconds
Started Jun 06 01:00:09 PM PDT 24
Finished Jun 06 01:02:19 PM PDT 24
Peak memory 208696 kb
Host smart-0bb6b17c-ebb0-4944-97b1-bf5daccd188d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267097026 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 30.uart_stress_all_with_rand_reset.1267097026
Directory /workspace/30.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.uart_tx_ovrd.3142981857
Short name T746
Test name
Test status
Simulation time 1535310865 ps
CPU time 1.95 seconds
Started Jun 06 01:00:09 PM PDT 24
Finished Jun 06 01:00:12 PM PDT 24
Peak memory 198616 kb
Host smart-e73f733f-470a-490b-9b0f-fa4e8c911247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142981857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.3142981857
Directory /workspace/30.uart_tx_ovrd/latest

Test location /workspace/coverage/default/30.uart_tx_rx.2888401294
Short name T707
Test name
Test status
Simulation time 80098875294 ps
CPU time 31.38 seconds
Started Jun 06 01:00:03 PM PDT 24
Finished Jun 06 01:00:35 PM PDT 24
Peak memory 200384 kb
Host smart-68a0c205-d88f-4584-88d3-5032aacff200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888401294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.2888401294
Directory /workspace/30.uart_tx_rx/latest

Test location /workspace/coverage/default/31.uart_alert_test.3979737372
Short name T29
Test name
Test status
Simulation time 13752048 ps
CPU time 0.56 seconds
Started Jun 06 01:00:13 PM PDT 24
Finished Jun 06 01:00:15 PM PDT 24
Peak memory 196000 kb
Host smart-55d47866-58aa-45b6-9df0-11852bb161eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979737372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.3979737372
Directory /workspace/31.uart_alert_test/latest

Test location /workspace/coverage/default/31.uart_fifo_full.2650525006
Short name T418
Test name
Test status
Simulation time 212036362868 ps
CPU time 30.93 seconds
Started Jun 06 01:00:10 PM PDT 24
Finished Jun 06 01:00:43 PM PDT 24
Peak memory 200404 kb
Host smart-b3c6e69a-c3da-427d-9fe5-8025c29cf42b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650525006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.2650525006
Directory /workspace/31.uart_fifo_full/latest

Test location /workspace/coverage/default/31.uart_fifo_overflow.1189801057
Short name T320
Test name
Test status
Simulation time 121005194134 ps
CPU time 104.7 seconds
Started Jun 06 01:00:10 PM PDT 24
Finished Jun 06 01:01:55 PM PDT 24
Peak memory 200240 kb
Host smart-82415758-36dc-4a08-a89d-c54e36af4b05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189801057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.1189801057
Directory /workspace/31.uart_fifo_overflow/latest

Test location /workspace/coverage/default/31.uart_fifo_reset.3074844169
Short name T784
Test name
Test status
Simulation time 54613208112 ps
CPU time 55.75 seconds
Started Jun 06 01:00:09 PM PDT 24
Finished Jun 06 01:01:06 PM PDT 24
Peak memory 200368 kb
Host smart-de5ef184-4acc-49cf-862f-90f27e9db8bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074844169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.3074844169
Directory /workspace/31.uart_fifo_reset/latest

Test location /workspace/coverage/default/31.uart_intr.1441316060
Short name T430
Test name
Test status
Simulation time 15395336577 ps
CPU time 21.47 seconds
Started Jun 06 01:00:12 PM PDT 24
Finished Jun 06 01:00:35 PM PDT 24
Peak memory 200336 kb
Host smart-bd621f4b-ec93-4b3a-8e34-16e935ec79db
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441316060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.1441316060
Directory /workspace/31.uart_intr/latest

Test location /workspace/coverage/default/31.uart_long_xfer_wo_dly.1045446932
Short name T691
Test name
Test status
Simulation time 166735887560 ps
CPU time 809.66 seconds
Started Jun 06 01:00:11 PM PDT 24
Finished Jun 06 01:13:42 PM PDT 24
Peak memory 200276 kb
Host smart-51f8b38c-494e-4f05-b942-d558dc229b42
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1045446932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.1045446932
Directory /workspace/31.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/31.uart_loopback.2512861705
Short name T816
Test name
Test status
Simulation time 1259580828 ps
CPU time 1.38 seconds
Started Jun 06 01:00:11 PM PDT 24
Finished Jun 06 01:00:14 PM PDT 24
Peak memory 199052 kb
Host smart-70842bc1-8176-47ce-8b6e-0f604c36aff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512861705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_loopback.2512861705
Directory /workspace/31.uart_loopback/latest

Test location /workspace/coverage/default/31.uart_noise_filter.2970498630
Short name T759
Test name
Test status
Simulation time 34068112169 ps
CPU time 33.57 seconds
Started Jun 06 01:00:12 PM PDT 24
Finished Jun 06 01:00:47 PM PDT 24
Peak memory 200500 kb
Host smart-ff555b26-9726-4851-b8a3-11bf6a4f8171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970498630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_noise_filter.2970498630
Directory /workspace/31.uart_noise_filter/latest

Test location /workspace/coverage/default/31.uart_perf.2531703222
Short name T677
Test name
Test status
Simulation time 19195087941 ps
CPU time 92.72 seconds
Started Jun 06 01:00:12 PM PDT 24
Finished Jun 06 01:01:46 PM PDT 24
Peak memory 200284 kb
Host smart-05691d66-f1b5-4bc6-8bec-227779a59459
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2531703222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.2531703222
Directory /workspace/31.uart_perf/latest

Test location /workspace/coverage/default/31.uart_rx_oversample.2862692058
Short name T701
Test name
Test status
Simulation time 2116694658 ps
CPU time 9.63 seconds
Started Jun 06 01:00:11 PM PDT 24
Finished Jun 06 01:00:22 PM PDT 24
Peak memory 198368 kb
Host smart-92ac938d-6d00-433a-9b5f-624c4f721bc3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2862692058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.2862692058
Directory /workspace/31.uart_rx_oversample/latest

Test location /workspace/coverage/default/31.uart_rx_parity_err.2521005302
Short name T83
Test name
Test status
Simulation time 17259095765 ps
CPU time 26.97 seconds
Started Jun 06 01:00:11 PM PDT 24
Finished Jun 06 01:00:40 PM PDT 24
Peak memory 200208 kb
Host smart-d6d8ceb4-dff8-4548-ba87-ab0286b98067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521005302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.2521005302
Directory /workspace/31.uart_rx_parity_err/latest

Test location /workspace/coverage/default/31.uart_rx_start_bit_filter.1602591869
Short name T797
Test name
Test status
Simulation time 2498684018 ps
CPU time 4.11 seconds
Started Jun 06 01:00:13 PM PDT 24
Finished Jun 06 01:00:18 PM PDT 24
Peak memory 196820 kb
Host smart-8ad91a35-c288-4091-a344-65925d2ed43b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602591869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.1602591869
Directory /workspace/31.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/31.uart_smoke.3804356450
Short name T904
Test name
Test status
Simulation time 674160194 ps
CPU time 2.53 seconds
Started Jun 06 01:00:10 PM PDT 24
Finished Jun 06 01:00:14 PM PDT 24
Peak memory 199140 kb
Host smart-ac92f304-6c43-450e-98aa-9266d1027852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804356450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_smoke.3804356450
Directory /workspace/31.uart_smoke/latest

Test location /workspace/coverage/default/31.uart_stress_all.2756122682
Short name T580
Test name
Test status
Simulation time 180593316860 ps
CPU time 330.8 seconds
Started Jun 06 01:00:11 PM PDT 24
Finished Jun 06 01:05:43 PM PDT 24
Peak memory 200348 kb
Host smart-e5a013e1-6129-4021-ac46-8e69559ff250
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756122682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.2756122682
Directory /workspace/31.uart_stress_all/latest

Test location /workspace/coverage/default/31.uart_stress_all_with_rand_reset.2130748064
Short name T25
Test name
Test status
Simulation time 61864876282 ps
CPU time 97.12 seconds
Started Jun 06 01:00:11 PM PDT 24
Finished Jun 06 01:01:49 PM PDT 24
Peak memory 217032 kb
Host smart-d44b58cc-bb4a-4553-8739-436ccf27e968
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130748064 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 31.uart_stress_all_with_rand_reset.2130748064
Directory /workspace/31.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.uart_tx_ovrd.3785293972
Short name T299
Test name
Test status
Simulation time 6258222638 ps
CPU time 43.92 seconds
Started Jun 06 01:00:11 PM PDT 24
Finished Jun 06 01:00:56 PM PDT 24
Peak memory 200344 kb
Host smart-cdb372d0-5396-4dd5-805d-bffca381de6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785293972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.3785293972
Directory /workspace/31.uart_tx_ovrd/latest

Test location /workspace/coverage/default/31.uart_tx_rx.3164007851
Short name T270
Test name
Test status
Simulation time 41656305127 ps
CPU time 85.43 seconds
Started Jun 06 01:00:10 PM PDT 24
Finished Jun 06 01:01:37 PM PDT 24
Peak memory 200268 kb
Host smart-0593deaa-c7ac-4c6c-be8d-d1ea60f02a2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164007851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.3164007851
Directory /workspace/31.uart_tx_rx/latest

Test location /workspace/coverage/default/32.uart_alert_test.456449182
Short name T601
Test name
Test status
Simulation time 13728207 ps
CPU time 0.55 seconds
Started Jun 06 01:00:23 PM PDT 24
Finished Jun 06 01:00:26 PM PDT 24
Peak memory 195740 kb
Host smart-9811ade1-cb4d-4b47-a396-7b7037467ad5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456449182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.456449182
Directory /workspace/32.uart_alert_test/latest

Test location /workspace/coverage/default/32.uart_fifo_full.1235815625
Short name T633
Test name
Test status
Simulation time 128592678344 ps
CPU time 47.5 seconds
Started Jun 06 01:00:21 PM PDT 24
Finished Jun 06 01:01:10 PM PDT 24
Peak memory 200280 kb
Host smart-e34be4cd-30d2-42fb-bc6c-a55996c96db8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235815625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.1235815625
Directory /workspace/32.uart_fifo_full/latest

Test location /workspace/coverage/default/32.uart_fifo_overflow.3013175997
Short name T1096
Test name
Test status
Simulation time 91921925619 ps
CPU time 36.21 seconds
Started Jun 06 01:00:19 PM PDT 24
Finished Jun 06 01:00:57 PM PDT 24
Peak memory 200320 kb
Host smart-0207cdcd-48d9-478d-affb-53d2454428c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013175997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.3013175997
Directory /workspace/32.uart_fifo_overflow/latest

Test location /workspace/coverage/default/32.uart_fifo_reset.3886556222
Short name T689
Test name
Test status
Simulation time 106119818206 ps
CPU time 141.87 seconds
Started Jun 06 01:00:20 PM PDT 24
Finished Jun 06 01:02:43 PM PDT 24
Peak memory 200300 kb
Host smart-2f2ef9ab-0744-4a7f-b779-90414041c405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886556222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.3886556222
Directory /workspace/32.uart_fifo_reset/latest

Test location /workspace/coverage/default/32.uart_intr.2977970527
Short name T722
Test name
Test status
Simulation time 191683012987 ps
CPU time 283.74 seconds
Started Jun 06 01:00:19 PM PDT 24
Finished Jun 06 01:05:04 PM PDT 24
Peak memory 198404 kb
Host smart-4a1a8c4e-d9ab-4833-9af0-d492013d2e3d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977970527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.2977970527
Directory /workspace/32.uart_intr/latest

Test location /workspace/coverage/default/32.uart_long_xfer_wo_dly.2508936792
Short name T615
Test name
Test status
Simulation time 126799256127 ps
CPU time 151.39 seconds
Started Jun 06 01:00:21 PM PDT 24
Finished Jun 06 01:02:54 PM PDT 24
Peak memory 200300 kb
Host smart-e5de17d1-b740-471a-b08c-31a31e8852e1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2508936792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.2508936792
Directory /workspace/32.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/32.uart_loopback.687445039
Short name T908
Test name
Test status
Simulation time 5215154937 ps
CPU time 8.92 seconds
Started Jun 06 01:00:21 PM PDT 24
Finished Jun 06 01:00:31 PM PDT 24
Peak memory 197048 kb
Host smart-1a7660a9-ecc5-4687-a269-b992b9f2607e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687445039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_loopback.687445039
Directory /workspace/32.uart_loopback/latest

Test location /workspace/coverage/default/32.uart_noise_filter.1440331815
Short name T441
Test name
Test status
Simulation time 223265469959 ps
CPU time 89.89 seconds
Started Jun 06 01:00:19 PM PDT 24
Finished Jun 06 01:01:50 PM PDT 24
Peak memory 208588 kb
Host smart-955275aa-10a5-451b-a18d-1fdb8518350c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440331815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_noise_filter.1440331815
Directory /workspace/32.uart_noise_filter/latest

Test location /workspace/coverage/default/32.uart_perf.856663641
Short name T451
Test name
Test status
Simulation time 18888822180 ps
CPU time 1065.33 seconds
Started Jun 06 01:00:22 PM PDT 24
Finished Jun 06 01:18:09 PM PDT 24
Peak memory 200288 kb
Host smart-caaaab36-bc88-43ab-86fb-9053bb865559
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=856663641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.856663641
Directory /workspace/32.uart_perf/latest

Test location /workspace/coverage/default/32.uart_rx_oversample.3647233463
Short name T431
Test name
Test status
Simulation time 5965013047 ps
CPU time 12.23 seconds
Started Jun 06 01:00:21 PM PDT 24
Finished Jun 06 01:00:34 PM PDT 24
Peak memory 199548 kb
Host smart-72e28a13-dbf6-4764-8962-ebcc96320049
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3647233463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.3647233463
Directory /workspace/32.uart_rx_oversample/latest

Test location /workspace/coverage/default/32.uart_rx_parity_err.1028471411
Short name T110
Test name
Test status
Simulation time 59180075847 ps
CPU time 110.21 seconds
Started Jun 06 01:00:20 PM PDT 24
Finished Jun 06 01:02:11 PM PDT 24
Peak memory 200268 kb
Host smart-8b9019a1-d16b-42aa-98b2-a6dc060ba479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028471411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.1028471411
Directory /workspace/32.uart_rx_parity_err/latest

Test location /workspace/coverage/default/32.uart_rx_start_bit_filter.1689376977
Short name T293
Test name
Test status
Simulation time 32811112651 ps
CPU time 14.76 seconds
Started Jun 06 01:00:19 PM PDT 24
Finished Jun 06 01:00:35 PM PDT 24
Peak memory 196176 kb
Host smart-6808f19f-2ff8-45a9-ae1d-9ab444244e7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689376977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.1689376977
Directory /workspace/32.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/32.uart_smoke.550441943
Short name T273
Test name
Test status
Simulation time 354173273 ps
CPU time 1.09 seconds
Started Jun 06 01:00:11 PM PDT 24
Finished Jun 06 01:00:13 PM PDT 24
Peak memory 198624 kb
Host smart-7c550ace-97e3-4a2c-b74f-83bbcb852cc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550441943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_smoke.550441943
Directory /workspace/32.uart_smoke/latest

Test location /workspace/coverage/default/32.uart_stress_all.3523346210
Short name T232
Test name
Test status
Simulation time 928153279208 ps
CPU time 364.37 seconds
Started Jun 06 01:00:20 PM PDT 24
Finished Jun 06 01:06:26 PM PDT 24
Peak memory 208836 kb
Host smart-053d05c4-bfa0-4bf0-9b26-da330d4e5da3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523346210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.3523346210
Directory /workspace/32.uart_stress_all/latest

Test location /workspace/coverage/default/32.uart_stress_all_with_rand_reset.34084209
Short name T528
Test name
Test status
Simulation time 283632608817 ps
CPU time 806.3 seconds
Started Jun 06 01:00:21 PM PDT 24
Finished Jun 06 01:13:48 PM PDT 24
Peak memory 217160 kb
Host smart-758564b9-9559-4811-929d-f0c5a0f13a8d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34084209 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 32.uart_stress_all_with_rand_reset.34084209
Directory /workspace/32.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.uart_tx_ovrd.2839867204
Short name T19
Test name
Test status
Simulation time 13879323237 ps
CPU time 16.34 seconds
Started Jun 06 01:00:20 PM PDT 24
Finished Jun 06 01:00:38 PM PDT 24
Peak memory 200304 kb
Host smart-b9d3babf-29af-42cd-b0ae-6b04926b59ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839867204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.2839867204
Directory /workspace/32.uart_tx_ovrd/latest

Test location /workspace/coverage/default/32.uart_tx_rx.848534559
Short name T716
Test name
Test status
Simulation time 119729334508 ps
CPU time 55.3 seconds
Started Jun 06 01:00:19 PM PDT 24
Finished Jun 06 01:01:16 PM PDT 24
Peak memory 200364 kb
Host smart-b308b366-bae7-45eb-ae23-86e794e8a23a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848534559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.848534559
Directory /workspace/32.uart_tx_rx/latest

Test location /workspace/coverage/default/33.uart_alert_test.496115514
Short name T655
Test name
Test status
Simulation time 14445175 ps
CPU time 0.6 seconds
Started Jun 06 01:00:23 PM PDT 24
Finished Jun 06 01:00:25 PM PDT 24
Peak memory 195712 kb
Host smart-8e7baf33-6e36-4f4a-8d26-6f62eae40312
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496115514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.496115514
Directory /workspace/33.uart_alert_test/latest

Test location /workspace/coverage/default/33.uart_fifo_full.4142564062
Short name T559
Test name
Test status
Simulation time 50507107037 ps
CPU time 39.81 seconds
Started Jun 06 01:00:24 PM PDT 24
Finished Jun 06 01:01:05 PM PDT 24
Peak memory 200344 kb
Host smart-b993f817-a5fc-4e85-b219-e8a37e2f930d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142564062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.4142564062
Directory /workspace/33.uart_fifo_full/latest

Test location /workspace/coverage/default/33.uart_fifo_overflow.2760932756
Short name T444
Test name
Test status
Simulation time 92341070710 ps
CPU time 20.18 seconds
Started Jun 06 01:00:23 PM PDT 24
Finished Jun 06 01:00:44 PM PDT 24
Peak memory 200372 kb
Host smart-cdcf4a94-4a8d-450f-8a0e-74b71f4ba9ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760932756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.2760932756
Directory /workspace/33.uart_fifo_overflow/latest

Test location /workspace/coverage/default/33.uart_fifo_reset.4283205026
Short name T461
Test name
Test status
Simulation time 71402106408 ps
CPU time 29.41 seconds
Started Jun 06 01:00:23 PM PDT 24
Finished Jun 06 01:00:54 PM PDT 24
Peak memory 200368 kb
Host smart-322ad3de-8317-4965-a455-08b6462c7db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283205026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.4283205026
Directory /workspace/33.uart_fifo_reset/latest

Test location /workspace/coverage/default/33.uart_intr.2301619877
Short name T15
Test name
Test status
Simulation time 5884681611 ps
CPU time 9.25 seconds
Started Jun 06 01:00:22 PM PDT 24
Finished Jun 06 01:00:32 PM PDT 24
Peak memory 196808 kb
Host smart-043aaef9-a35a-4d2f-962b-d3e84c7b1764
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301619877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.2301619877
Directory /workspace/33.uart_intr/latest

Test location /workspace/coverage/default/33.uart_long_xfer_wo_dly.17120645
Short name T686
Test name
Test status
Simulation time 126689108866 ps
CPU time 663.12 seconds
Started Jun 06 01:00:24 PM PDT 24
Finished Jun 06 01:11:29 PM PDT 24
Peak memory 200208 kb
Host smart-32e7e2b2-28f7-4c0b-9c98-f907bf03a6d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=17120645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.17120645
Directory /workspace/33.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/33.uart_loopback.2733876472
Short name T1189
Test name
Test status
Simulation time 10094214551 ps
CPU time 19.78 seconds
Started Jun 06 01:00:28 PM PDT 24
Finished Jun 06 01:00:48 PM PDT 24
Peak memory 200280 kb
Host smart-db7585f2-0e01-4af6-a9b4-762db57a0976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733876472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_loopback.2733876472
Directory /workspace/33.uart_loopback/latest

Test location /workspace/coverage/default/33.uart_noise_filter.77858801
Short name T277
Test name
Test status
Simulation time 67207618958 ps
CPU time 30.21 seconds
Started Jun 06 01:00:23 PM PDT 24
Finished Jun 06 01:00:54 PM PDT 24
Peak memory 199668 kb
Host smart-10c5e35a-ea15-44e2-bd19-c28b230b5dcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77858801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_noise_filter.77858801
Directory /workspace/33.uart_noise_filter/latest

Test location /workspace/coverage/default/33.uart_perf.2263145832
Short name T980
Test name
Test status
Simulation time 7082639283 ps
CPU time 297.56 seconds
Started Jun 06 01:00:22 PM PDT 24
Finished Jun 06 01:05:21 PM PDT 24
Peak memory 200308 kb
Host smart-346bfa9e-94fd-4f10-a157-98d3be57332a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2263145832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.2263145832
Directory /workspace/33.uart_perf/latest

Test location /workspace/coverage/default/33.uart_rx_oversample.440310674
Short name T517
Test name
Test status
Simulation time 6159447404 ps
CPU time 25.59 seconds
Started Jun 06 01:00:24 PM PDT 24
Finished Jun 06 01:00:51 PM PDT 24
Peak memory 199824 kb
Host smart-c943405a-d5ba-4965-ab78-038fc5b646be
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=440310674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.440310674
Directory /workspace/33.uart_rx_oversample/latest

Test location /workspace/coverage/default/33.uart_rx_start_bit_filter.1867212420
Short name T489
Test name
Test status
Simulation time 5245249806 ps
CPU time 2.07 seconds
Started Jun 06 01:00:22 PM PDT 24
Finished Jun 06 01:00:26 PM PDT 24
Peak memory 196424 kb
Host smart-fd76327f-d1c5-4f21-abce-d2aeeb22066f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867212420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.1867212420
Directory /workspace/33.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/33.uart_smoke.2191763736
Short name T660
Test name
Test status
Simulation time 86631243 ps
CPU time 0.9 seconds
Started Jun 06 01:00:23 PM PDT 24
Finished Jun 06 01:00:25 PM PDT 24
Peak memory 197336 kb
Host smart-c0ab1af5-28d1-4101-93ed-8c824f6995ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191763736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_smoke.2191763736
Directory /workspace/33.uart_smoke/latest

Test location /workspace/coverage/default/33.uart_stress_all.3066565524
Short name T525
Test name
Test status
Simulation time 223661796193 ps
CPU time 444.71 seconds
Started Jun 06 01:00:25 PM PDT 24
Finished Jun 06 01:07:51 PM PDT 24
Peak memory 200372 kb
Host smart-8124bb1f-b9a7-42c0-bdf7-3533edd3106d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066565524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.3066565524
Directory /workspace/33.uart_stress_all/latest

Test location /workspace/coverage/default/33.uart_stress_all_with_rand_reset.3587502638
Short name T180
Test name
Test status
Simulation time 143780567918 ps
CPU time 1339.2 seconds
Started Jun 06 01:00:22 PM PDT 24
Finished Jun 06 01:22:43 PM PDT 24
Peak memory 230280 kb
Host smart-99c60d4a-5875-4e10-857f-407a2bf84663
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587502638 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 33.uart_stress_all_with_rand_reset.3587502638
Directory /workspace/33.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.uart_tx_ovrd.4284926934
Short name T1067
Test name
Test status
Simulation time 813250447 ps
CPU time 2.89 seconds
Started Jun 06 01:00:28 PM PDT 24
Finished Jun 06 01:00:32 PM PDT 24
Peak memory 198588 kb
Host smart-5057d46b-34d8-403c-91d9-babb2f0b7523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284926934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.4284926934
Directory /workspace/33.uart_tx_ovrd/latest

Test location /workspace/coverage/default/33.uart_tx_rx.158285480
Short name T112
Test name
Test status
Simulation time 46818851436 ps
CPU time 69.19 seconds
Started Jun 06 01:00:24 PM PDT 24
Finished Jun 06 01:01:35 PM PDT 24
Peak memory 200328 kb
Host smart-64f36a01-f9c8-4e0d-8a97-7bcb43f34eeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158285480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.158285480
Directory /workspace/33.uart_tx_rx/latest

Test location /workspace/coverage/default/34.uart_alert_test.620310041
Short name T1149
Test name
Test status
Simulation time 12732239 ps
CPU time 0.52 seconds
Started Jun 06 01:00:30 PM PDT 24
Finished Jun 06 01:00:31 PM PDT 24
Peak memory 194928 kb
Host smart-62a5c622-7bbf-48a7-838d-ae3d65074065
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620310041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.620310041
Directory /workspace/34.uart_alert_test/latest

Test location /workspace/coverage/default/34.uart_fifo_full.3973858982
Short name T688
Test name
Test status
Simulation time 31202312496 ps
CPU time 12.73 seconds
Started Jun 06 01:00:28 PM PDT 24
Finished Jun 06 01:00:41 PM PDT 24
Peak memory 200232 kb
Host smart-8f5e78bb-f883-47a7-8f2d-cc638d061269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973858982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.3973858982
Directory /workspace/34.uart_fifo_full/latest

Test location /workspace/coverage/default/34.uart_fifo_overflow.3365791908
Short name T1016
Test name
Test status
Simulation time 148516089349 ps
CPU time 49.21 seconds
Started Jun 06 01:00:28 PM PDT 24
Finished Jun 06 01:01:18 PM PDT 24
Peak memory 200064 kb
Host smart-397f55d4-1528-4858-827b-18aa1d2bba84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365791908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.3365791908
Directory /workspace/34.uart_fifo_overflow/latest

Test location /workspace/coverage/default/34.uart_fifo_reset.276712779
Short name T935
Test name
Test status
Simulation time 88561371121 ps
CPU time 40.58 seconds
Started Jun 06 01:00:34 PM PDT 24
Finished Jun 06 01:01:16 PM PDT 24
Peak memory 200384 kb
Host smart-b2045ead-675b-4ab8-b074-983ed70a4522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276712779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.276712779
Directory /workspace/34.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_intr.1255571648
Short name T1104
Test name
Test status
Simulation time 21433392173 ps
CPU time 41.62 seconds
Started Jun 06 01:00:31 PM PDT 24
Finished Jun 06 01:01:13 PM PDT 24
Peak memory 200312 kb
Host smart-76d1a1bd-fc84-486d-aac0-2ded62029264
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255571648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.1255571648
Directory /workspace/34.uart_intr/latest

Test location /workspace/coverage/default/34.uart_long_xfer_wo_dly.2995634594
Short name T388
Test name
Test status
Simulation time 170437277857 ps
CPU time 334.94 seconds
Started Jun 06 01:00:39 PM PDT 24
Finished Jun 06 01:06:15 PM PDT 24
Peak memory 200396 kb
Host smart-3b337133-fd22-4170-8dcf-1bff3006efb9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2995634594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.2995634594
Directory /workspace/34.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/34.uart_loopback.2715786224
Short name T567
Test name
Test status
Simulation time 6901830973 ps
CPU time 1.91 seconds
Started Jun 06 01:00:35 PM PDT 24
Finished Jun 06 01:00:38 PM PDT 24
Peak memory 197736 kb
Host smart-01bbeff2-c0d4-444a-9a2f-3780ec5101a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715786224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_loopback.2715786224
Directory /workspace/34.uart_loopback/latest

Test location /workspace/coverage/default/34.uart_noise_filter.1812739685
Short name T429
Test name
Test status
Simulation time 65426808581 ps
CPU time 22.74 seconds
Started Jun 06 01:00:32 PM PDT 24
Finished Jun 06 01:00:56 PM PDT 24
Peak memory 200332 kb
Host smart-aa31085f-c095-4ebd-82e4-4268dd71fb82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812739685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_noise_filter.1812739685
Directory /workspace/34.uart_noise_filter/latest

Test location /workspace/coverage/default/34.uart_perf.543081756
Short name T1170
Test name
Test status
Simulation time 15134318001 ps
CPU time 844.66 seconds
Started Jun 06 01:00:39 PM PDT 24
Finished Jun 06 01:14:45 PM PDT 24
Peak memory 200296 kb
Host smart-1225649e-6111-493b-b40d-289960f344eb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=543081756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.543081756
Directory /workspace/34.uart_perf/latest

Test location /workspace/coverage/default/34.uart_rx_oversample.3891617674
Short name T1172
Test name
Test status
Simulation time 1908016522 ps
CPU time 13.25 seconds
Started Jun 06 01:00:38 PM PDT 24
Finished Jun 06 01:00:53 PM PDT 24
Peak memory 198516 kb
Host smart-fd0bf169-9c17-48a4-86ea-6a21517d8da8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3891617674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.3891617674
Directory /workspace/34.uart_rx_oversample/latest

Test location /workspace/coverage/default/34.uart_rx_parity_err.1252172487
Short name T1112
Test name
Test status
Simulation time 227643178330 ps
CPU time 242.89 seconds
Started Jun 06 01:00:30 PM PDT 24
Finished Jun 06 01:04:33 PM PDT 24
Peak memory 200144 kb
Host smart-94612e1f-44cd-4c2a-acdb-9e6d4eb3747d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252172487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.1252172487
Directory /workspace/34.uart_rx_parity_err/latest

Test location /workspace/coverage/default/34.uart_rx_start_bit_filter.2026675169
Short name T439
Test name
Test status
Simulation time 3315239315 ps
CPU time 3.18 seconds
Started Jun 06 01:00:39 PM PDT 24
Finished Jun 06 01:00:43 PM PDT 24
Peak memory 196412 kb
Host smart-68b35a67-d61e-4346-b41f-7fa1d061eeab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026675169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.2026675169
Directory /workspace/34.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/34.uart_smoke.2489222349
Short name T297
Test name
Test status
Simulation time 665213490 ps
CPU time 1.72 seconds
Started Jun 06 01:00:28 PM PDT 24
Finished Jun 06 01:00:30 PM PDT 24
Peak memory 198600 kb
Host smart-6d704d93-03d3-410a-b724-aeb8fdeb08e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489222349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_smoke.2489222349
Directory /workspace/34.uart_smoke/latest

Test location /workspace/coverage/default/34.uart_stress_all.2988196219
Short name T1007
Test name
Test status
Simulation time 182779162446 ps
CPU time 168.98 seconds
Started Jun 06 01:00:38 PM PDT 24
Finished Jun 06 01:03:28 PM PDT 24
Peak memory 200344 kb
Host smart-c19c0181-e1f7-46c8-aedf-dc9a105b61bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988196219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.2988196219
Directory /workspace/34.uart_stress_all/latest

Test location /workspace/coverage/default/34.uart_stress_all_with_rand_reset.3091539493
Short name T992
Test name
Test status
Simulation time 43358072745 ps
CPU time 450.1 seconds
Started Jun 06 01:00:35 PM PDT 24
Finished Jun 06 01:08:06 PM PDT 24
Peak memory 217040 kb
Host smart-3376eca8-c010-4436-bbff-a8f55b0f352b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091539493 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 34.uart_stress_all_with_rand_reset.3091539493
Directory /workspace/34.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.uart_tx_ovrd.3502736999
Short name T785
Test name
Test status
Simulation time 1864293939 ps
CPU time 1.77 seconds
Started Jun 06 01:00:35 PM PDT 24
Finished Jun 06 01:00:38 PM PDT 24
Peak memory 200232 kb
Host smart-1ca20e67-d475-4db5-8352-9d11eca8ca8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502736999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.3502736999
Directory /workspace/34.uart_tx_ovrd/latest

Test location /workspace/coverage/default/34.uart_tx_rx.2873224580
Short name T888
Test name
Test status
Simulation time 21487750311 ps
CPU time 7.39 seconds
Started Jun 06 01:00:25 PM PDT 24
Finished Jun 06 01:00:34 PM PDT 24
Peak memory 198236 kb
Host smart-d4f9c9cc-24e0-446b-b5b8-b438cfa765a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873224580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.2873224580
Directory /workspace/34.uart_tx_rx/latest

Test location /workspace/coverage/default/35.uart_alert_test.4015930903
Short name T435
Test name
Test status
Simulation time 78516317 ps
CPU time 0.57 seconds
Started Jun 06 01:00:38 PM PDT 24
Finished Jun 06 01:00:40 PM PDT 24
Peak memory 195684 kb
Host smart-f20cafe4-6700-43ea-95c5-302668f8791c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015930903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.4015930903
Directory /workspace/35.uart_alert_test/latest

Test location /workspace/coverage/default/35.uart_fifo_full.1041802585
Short name T726
Test name
Test status
Simulation time 115405426822 ps
CPU time 56.76 seconds
Started Jun 06 01:00:34 PM PDT 24
Finished Jun 06 01:01:32 PM PDT 24
Peak memory 200384 kb
Host smart-f0372258-4741-45eb-9c8a-65c96700c8c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041802585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.1041802585
Directory /workspace/35.uart_fifo_full/latest

Test location /workspace/coverage/default/35.uart_fifo_overflow.3520653012
Short name T914
Test name
Test status
Simulation time 63889920979 ps
CPU time 13.02 seconds
Started Jun 06 01:00:29 PM PDT 24
Finished Jun 06 01:00:43 PM PDT 24
Peak memory 200284 kb
Host smart-ca0f019f-3292-49c2-90d8-a8fc95712c20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520653012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.3520653012
Directory /workspace/35.uart_fifo_overflow/latest

Test location /workspace/coverage/default/35.uart_fifo_reset.699261670
Short name T165
Test name
Test status
Simulation time 52749876737 ps
CPU time 27.39 seconds
Started Jun 06 01:00:28 PM PDT 24
Finished Jun 06 01:00:57 PM PDT 24
Peak memory 200320 kb
Host smart-3270648a-ce54-4da7-88f0-6dfadf50e986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699261670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.699261670
Directory /workspace/35.uart_fifo_reset/latest

Test location /workspace/coverage/default/35.uart_intr.3013856824
Short name T788
Test name
Test status
Simulation time 58974153725 ps
CPU time 103.25 seconds
Started Jun 06 01:00:28 PM PDT 24
Finished Jun 06 01:02:12 PM PDT 24
Peak memory 200312 kb
Host smart-2e89e368-e09e-43e5-b7a5-d995b3f55549
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013856824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.3013856824
Directory /workspace/35.uart_intr/latest

Test location /workspace/coverage/default/35.uart_long_xfer_wo_dly.1983407342
Short name T667
Test name
Test status
Simulation time 147133026051 ps
CPU time 623.32 seconds
Started Jun 06 01:00:37 PM PDT 24
Finished Jun 06 01:11:02 PM PDT 24
Peak memory 200276 kb
Host smart-8d107159-7ec7-4177-9c56-7f3c6b290a2f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1983407342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.1983407342
Directory /workspace/35.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/35.uart_loopback.1657215695
Short name T1108
Test name
Test status
Simulation time 6261818272 ps
CPU time 13.04 seconds
Started Jun 06 01:00:37 PM PDT 24
Finished Jun 06 01:00:51 PM PDT 24
Peak memory 200008 kb
Host smart-01bc00a2-134d-4fe8-bfce-afa867ad8293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657215695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_loopback.1657215695
Directory /workspace/35.uart_loopback/latest

Test location /workspace/coverage/default/35.uart_noise_filter.3709442115
Short name T590
Test name
Test status
Simulation time 60399040426 ps
CPU time 53.99 seconds
Started Jun 06 01:00:34 PM PDT 24
Finished Jun 06 01:01:30 PM PDT 24
Peak memory 200536 kb
Host smart-1649fccd-b42f-4035-9301-bbe47db49aad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709442115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_noise_filter.3709442115
Directory /workspace/35.uart_noise_filter/latest

Test location /workspace/coverage/default/35.uart_perf.534245059
Short name T1139
Test name
Test status
Simulation time 12353542601 ps
CPU time 566.93 seconds
Started Jun 06 01:00:41 PM PDT 24
Finished Jun 06 01:10:09 PM PDT 24
Peak memory 200256 kb
Host smart-b0e3259d-9fbd-40c4-9f4e-6529de89f0e1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=534245059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.534245059
Directory /workspace/35.uart_perf/latest

Test location /workspace/coverage/default/35.uart_rx_oversample.2641092560
Short name T545
Test name
Test status
Simulation time 1591553109 ps
CPU time 4.67 seconds
Started Jun 06 01:00:26 PM PDT 24
Finished Jun 06 01:00:32 PM PDT 24
Peak memory 198476 kb
Host smart-e0ea8ec6-376d-46c8-89cb-70f0575ff376
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2641092560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.2641092560
Directory /workspace/35.uart_rx_oversample/latest

Test location /workspace/coverage/default/35.uart_rx_parity_err.2242803774
Short name T1115
Test name
Test status
Simulation time 183918801089 ps
CPU time 80.64 seconds
Started Jun 06 01:00:37 PM PDT 24
Finished Jun 06 01:01:58 PM PDT 24
Peak memory 200288 kb
Host smart-48645e37-6637-4096-b51e-fb5d2c09777c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242803774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.2242803774
Directory /workspace/35.uart_rx_parity_err/latest

Test location /workspace/coverage/default/35.uart_rx_start_bit_filter.968477504
Short name T477
Test name
Test status
Simulation time 38179542735 ps
CPU time 30.14 seconds
Started Jun 06 01:00:37 PM PDT 24
Finished Jun 06 01:01:08 PM PDT 24
Peak memory 196652 kb
Host smart-9527aaff-99da-4f71-84b5-43837f1531e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968477504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.968477504
Directory /workspace/35.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/35.uart_smoke.3754612326
Short name T712
Test name
Test status
Simulation time 631160070 ps
CPU time 1.5 seconds
Started Jun 06 01:00:29 PM PDT 24
Finished Jun 06 01:00:31 PM PDT 24
Peak memory 200124 kb
Host smart-95c67a5a-5b84-48ac-a3bf-703e62ce9096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754612326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_smoke.3754612326
Directory /workspace/35.uart_smoke/latest

Test location /workspace/coverage/default/35.uart_stress_all_with_rand_reset.3438656481
Short name T37
Test name
Test status
Simulation time 44577703444 ps
CPU time 313.61 seconds
Started Jun 06 01:00:37 PM PDT 24
Finished Jun 06 01:05:52 PM PDT 24
Peak memory 216468 kb
Host smart-31476207-e921-4643-97c1-cc636fdb3787
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438656481 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 35.uart_stress_all_with_rand_reset.3438656481
Directory /workspace/35.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.uart_tx_ovrd.3430947663
Short name T505
Test name
Test status
Simulation time 6498012978 ps
CPU time 24.8 seconds
Started Jun 06 01:00:41 PM PDT 24
Finished Jun 06 01:01:07 PM PDT 24
Peak memory 200216 kb
Host smart-781e1f59-ebfb-490e-8080-a584ca28ef67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430947663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.3430947663
Directory /workspace/35.uart_tx_ovrd/latest

Test location /workspace/coverage/default/35.uart_tx_rx.3978578563
Short name T740
Test name
Test status
Simulation time 8338309864 ps
CPU time 5.13 seconds
Started Jun 06 01:00:35 PM PDT 24
Finished Jun 06 01:00:41 PM PDT 24
Peak memory 200268 kb
Host smart-e530c138-5472-484b-8f28-ae7769b888a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978578563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.3978578563
Directory /workspace/35.uart_tx_rx/latest

Test location /workspace/coverage/default/36.uart_alert_test.2234799143
Short name T1109
Test name
Test status
Simulation time 15693884 ps
CPU time 0.56 seconds
Started Jun 06 01:01:00 PM PDT 24
Finished Jun 06 01:01:01 PM PDT 24
Peak memory 195648 kb
Host smart-751b5294-a3e6-45b0-af90-ca5bf9e9ed12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234799143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.2234799143
Directory /workspace/36.uart_alert_test/latest

Test location /workspace/coverage/default/36.uart_fifo_full.1547994820
Short name T395
Test name
Test status
Simulation time 24549386564 ps
CPU time 19.1 seconds
Started Jun 06 01:00:41 PM PDT 24
Finished Jun 06 01:01:01 PM PDT 24
Peak memory 200260 kb
Host smart-49f728cd-b8c5-4b4e-b475-322c176a5eb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547994820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.1547994820
Directory /workspace/36.uart_fifo_full/latest

Test location /workspace/coverage/default/36.uart_fifo_overflow.4193566594
Short name T844
Test name
Test status
Simulation time 15575987326 ps
CPU time 12.99 seconds
Started Jun 06 01:00:39 PM PDT 24
Finished Jun 06 01:00:53 PM PDT 24
Peak memory 199488 kb
Host smart-0b35de81-5e9e-435b-b4c8-034ef9eba57e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193566594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.4193566594
Directory /workspace/36.uart_fifo_overflow/latest

Test location /workspace/coverage/default/36.uart_intr.3744975129
Short name T348
Test name
Test status
Simulation time 32856412713 ps
CPU time 67.03 seconds
Started Jun 06 01:00:38 PM PDT 24
Finished Jun 06 01:01:46 PM PDT 24
Peak memory 200340 kb
Host smart-3fe4fbc9-3fdf-4037-bac6-e73251034ea2
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744975129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.3744975129
Directory /workspace/36.uart_intr/latest

Test location /workspace/coverage/default/36.uart_long_xfer_wo_dly.2037142733
Short name T448
Test name
Test status
Simulation time 235409817192 ps
CPU time 399.67 seconds
Started Jun 06 01:00:40 PM PDT 24
Finished Jun 06 01:07:21 PM PDT 24
Peak memory 200364 kb
Host smart-dd2d310d-37b8-4610-b6d6-1844ec9f882d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2037142733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.2037142733
Directory /workspace/36.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/36.uart_loopback.4256511412
Short name T925
Test name
Test status
Simulation time 8159000380 ps
CPU time 4.81 seconds
Started Jun 06 01:00:42 PM PDT 24
Finished Jun 06 01:00:48 PM PDT 24
Peak memory 198928 kb
Host smart-6f73115c-5ede-4af7-a304-eb277880900a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256511412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_loopback.4256511412
Directory /workspace/36.uart_loopback/latest

Test location /workspace/coverage/default/36.uart_noise_filter.1195723756
Short name T114
Test name
Test status
Simulation time 58912395665 ps
CPU time 164.02 seconds
Started Jun 06 01:00:38 PM PDT 24
Finished Jun 06 01:03:24 PM PDT 24
Peak memory 208756 kb
Host smart-b372ed3c-b134-4e69-8e49-445ffa68d83b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195723756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_noise_filter.1195723756
Directory /workspace/36.uart_noise_filter/latest

Test location /workspace/coverage/default/36.uart_perf.2362143395
Short name T1147
Test name
Test status
Simulation time 11514972371 ps
CPU time 166.54 seconds
Started Jun 06 01:00:38 PM PDT 24
Finished Jun 06 01:03:26 PM PDT 24
Peak memory 200320 kb
Host smart-be37973b-521b-4b9b-a617-1e75315551ca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2362143395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.2362143395
Directory /workspace/36.uart_perf/latest

Test location /workspace/coverage/default/36.uart_rx_oversample.3643044426
Short name T585
Test name
Test status
Simulation time 5064686870 ps
CPU time 7.49 seconds
Started Jun 06 01:00:39 PM PDT 24
Finished Jun 06 01:00:48 PM PDT 24
Peak memory 198556 kb
Host smart-a9103bd5-6b48-4e42-abe3-f4e060320e72
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3643044426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.3643044426
Directory /workspace/36.uart_rx_oversample/latest

Test location /workspace/coverage/default/36.uart_rx_parity_err.3929085076
Short name T164
Test name
Test status
Simulation time 215254173073 ps
CPU time 59.8 seconds
Started Jun 06 01:00:42 PM PDT 24
Finished Jun 06 01:01:42 PM PDT 24
Peak memory 200376 kb
Host smart-3dda37b7-75ae-47ff-b318-6d7db1a27d4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929085076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.3929085076
Directory /workspace/36.uart_rx_parity_err/latest

Test location /workspace/coverage/default/36.uart_rx_start_bit_filter.2074758561
Short name T750
Test name
Test status
Simulation time 30322159953 ps
CPU time 5.28 seconds
Started Jun 06 01:00:38 PM PDT 24
Finished Jun 06 01:00:45 PM PDT 24
Peak memory 196072 kb
Host smart-79f0ac64-d6df-43f6-8106-747180621d4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074758561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.2074758561
Directory /workspace/36.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/36.uart_smoke.175996492
Short name T852
Test name
Test status
Simulation time 5674393610 ps
CPU time 12.56 seconds
Started Jun 06 01:00:39 PM PDT 24
Finished Jun 06 01:00:53 PM PDT 24
Peak memory 199948 kb
Host smart-acda84b0-2ab7-48e8-8c7b-7b5214592c7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175996492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_smoke.175996492
Directory /workspace/36.uart_smoke/latest

Test location /workspace/coverage/default/36.uart_tx_ovrd.830925822
Short name T973
Test name
Test status
Simulation time 1430305850 ps
CPU time 1.47 seconds
Started Jun 06 01:00:42 PM PDT 24
Finished Jun 06 01:00:44 PM PDT 24
Peak memory 198592 kb
Host smart-5ea26638-ca95-4b12-b80b-d8f33ffd3d81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830925822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.830925822
Directory /workspace/36.uart_tx_ovrd/latest

Test location /workspace/coverage/default/36.uart_tx_rx.3284751019
Short name T427
Test name
Test status
Simulation time 61791818061 ps
CPU time 108.05 seconds
Started Jun 06 01:00:40 PM PDT 24
Finished Jun 06 01:02:29 PM PDT 24
Peak memory 200208 kb
Host smart-03f72441-8e11-44a2-b227-20d0cdaa944d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284751019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.3284751019
Directory /workspace/36.uart_tx_rx/latest

Test location /workspace/coverage/default/37.uart_alert_test.3387135866
Short name T1012
Test name
Test status
Simulation time 13264601 ps
CPU time 0.54 seconds
Started Jun 06 01:01:18 PM PDT 24
Finished Jun 06 01:01:20 PM PDT 24
Peak memory 195740 kb
Host smart-22db9153-6d2d-4c3d-a51e-00f2de98c6ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387135866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.3387135866
Directory /workspace/37.uart_alert_test/latest

Test location /workspace/coverage/default/37.uart_fifo_full.3374702258
Short name T470
Test name
Test status
Simulation time 151284393697 ps
CPU time 224.59 seconds
Started Jun 06 01:00:47 PM PDT 24
Finished Jun 06 01:04:33 PM PDT 24
Peak memory 200304 kb
Host smart-aafb3f29-9139-4b68-9f7c-fa23101c490b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374702258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.3374702258
Directory /workspace/37.uart_fifo_full/latest

Test location /workspace/coverage/default/37.uart_fifo_overflow.1168357762
Short name T109
Test name
Test status
Simulation time 53902704470 ps
CPU time 41.2 seconds
Started Jun 06 01:00:49 PM PDT 24
Finished Jun 06 01:01:31 PM PDT 24
Peak memory 200248 kb
Host smart-11eb37a1-7f5e-43d8-8c9a-734d4a87338b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168357762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.1168357762
Directory /workspace/37.uart_fifo_overflow/latest

Test location /workspace/coverage/default/37.uart_fifo_reset.216445862
Short name T1155
Test name
Test status
Simulation time 9444639491 ps
CPU time 12.97 seconds
Started Jun 06 01:00:47 PM PDT 24
Finished Jun 06 01:01:00 PM PDT 24
Peak memory 200136 kb
Host smart-302aaee8-b0ab-4707-8e04-4605a1d28ccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216445862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.216445862
Directory /workspace/37.uart_fifo_reset/latest

Test location /workspace/coverage/default/37.uart_intr.1476518374
Short name T791
Test name
Test status
Simulation time 20715090970 ps
CPU time 37.59 seconds
Started Jun 06 01:00:49 PM PDT 24
Finished Jun 06 01:01:27 PM PDT 24
Peak memory 197852 kb
Host smart-cd67884f-7d0a-4e00-a5ce-aa7750bf55ed
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476518374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.1476518374
Directory /workspace/37.uart_intr/latest

Test location /workspace/coverage/default/37.uart_long_xfer_wo_dly.4277196920
Short name T1062
Test name
Test status
Simulation time 90758968656 ps
CPU time 482.04 seconds
Started Jun 06 01:00:45 PM PDT 24
Finished Jun 06 01:08:48 PM PDT 24
Peak memory 200388 kb
Host smart-68b47e87-e385-49db-9773-3cd253e54082
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4277196920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.4277196920
Directory /workspace/37.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/37.uart_loopback.1006353932
Short name T995
Test name
Test status
Simulation time 7101948954 ps
CPU time 4.98 seconds
Started Jun 06 01:00:47 PM PDT 24
Finished Jun 06 01:00:52 PM PDT 24
Peak memory 199872 kb
Host smart-1e385162-3555-4e66-a245-a932be1c89cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006353932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_loopback.1006353932
Directory /workspace/37.uart_loopback/latest

Test location /workspace/coverage/default/37.uart_noise_filter.2595958802
Short name T14
Test name
Test status
Simulation time 123967490577 ps
CPU time 48.36 seconds
Started Jun 06 01:01:12 PM PDT 24
Finished Jun 06 01:02:02 PM PDT 24
Peak memory 200544 kb
Host smart-a4f641af-c621-418a-af56-3890a62024e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595958802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_noise_filter.2595958802
Directory /workspace/37.uart_noise_filter/latest

Test location /workspace/coverage/default/37.uart_perf.2849834462
Short name T749
Test name
Test status
Simulation time 53278869814 ps
CPU time 318.67 seconds
Started Jun 06 01:00:50 PM PDT 24
Finished Jun 06 01:06:09 PM PDT 24
Peak memory 200312 kb
Host smart-4114d369-e4c3-44f6-822d-2f9f02c7cb45
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2849834462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.2849834462
Directory /workspace/37.uart_perf/latest

Test location /workspace/coverage/default/37.uart_rx_oversample.2424840954
Short name T446
Test name
Test status
Simulation time 3676470726 ps
CPU time 33.08 seconds
Started Jun 06 01:00:49 PM PDT 24
Finished Jun 06 01:01:23 PM PDT 24
Peak memory 198840 kb
Host smart-b36febc5-6efa-48c3-a296-a21392aa2845
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2424840954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.2424840954
Directory /workspace/37.uart_rx_oversample/latest

Test location /workspace/coverage/default/37.uart_rx_parity_err.1575262476
Short name T769
Test name
Test status
Simulation time 23730436792 ps
CPU time 10.01 seconds
Started Jun 06 01:00:47 PM PDT 24
Finished Jun 06 01:00:58 PM PDT 24
Peak memory 200256 kb
Host smart-93e40c2a-d97e-4529-a4c2-52909d877fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575262476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.1575262476
Directory /workspace/37.uart_rx_parity_err/latest

Test location /workspace/coverage/default/37.uart_rx_start_bit_filter.3602800944
Short name T358
Test name
Test status
Simulation time 40939681830 ps
CPU time 19.24 seconds
Started Jun 06 01:00:51 PM PDT 24
Finished Jun 06 01:01:11 PM PDT 24
Peak memory 196180 kb
Host smart-a538391e-bcab-4df2-8e2a-d1d636b24216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602800944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.3602800944
Directory /workspace/37.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/37.uart_smoke.2819504207
Short name T352
Test name
Test status
Simulation time 443309532 ps
CPU time 1.56 seconds
Started Jun 06 01:00:55 PM PDT 24
Finished Jun 06 01:00:58 PM PDT 24
Peak memory 199808 kb
Host smart-acbecef7-f85d-4e5b-a978-ab286ae4c96d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819504207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_smoke.2819504207
Directory /workspace/37.uart_smoke/latest

Test location /workspace/coverage/default/37.uart_stress_all.1279628550
Short name T1114
Test name
Test status
Simulation time 22577965995 ps
CPU time 398.72 seconds
Started Jun 06 01:00:48 PM PDT 24
Finished Jun 06 01:07:27 PM PDT 24
Peak memory 200288 kb
Host smart-ce08ce9f-f2a0-48a6-833e-83f4ab740284
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279628550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.1279628550
Directory /workspace/37.uart_stress_all/latest

Test location /workspace/coverage/default/37.uart_stress_all_with_rand_reset.1707305483
Short name T63
Test name
Test status
Simulation time 55763764531 ps
CPU time 590.11 seconds
Started Jun 06 01:00:48 PM PDT 24
Finished Jun 06 01:10:39 PM PDT 24
Peak memory 217064 kb
Host smart-b1a1e457-cfbd-46e7-bf89-cdd93071b111
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707305483 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 37.uart_stress_all_with_rand_reset.1707305483
Directory /workspace/37.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.uart_tx_ovrd.4290844528
Short name T333
Test name
Test status
Simulation time 2192951771 ps
CPU time 1.67 seconds
Started Jun 06 01:00:48 PM PDT 24
Finished Jun 06 01:00:50 PM PDT 24
Peak memory 197308 kb
Host smart-e3fdcd3c-1488-4934-b320-5579dbbec5a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290844528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.4290844528
Directory /workspace/37.uart_tx_ovrd/latest

Test location /workspace/coverage/default/37.uart_tx_rx.2822848388
Short name T581
Test name
Test status
Simulation time 76411728999 ps
CPU time 222.11 seconds
Started Jun 06 01:00:47 PM PDT 24
Finished Jun 06 01:04:30 PM PDT 24
Peak memory 200196 kb
Host smart-fe2d923c-cd83-4567-b4f3-bb7af324daa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822848388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.2822848388
Directory /workspace/37.uart_tx_rx/latest

Test location /workspace/coverage/default/38.uart_alert_test.2909764378
Short name T668
Test name
Test status
Simulation time 13813376 ps
CPU time 0.55 seconds
Started Jun 06 01:01:01 PM PDT 24
Finished Jun 06 01:01:02 PM PDT 24
Peak memory 195648 kb
Host smart-88830650-4142-4603-9594-71afa27a326d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909764378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.2909764378
Directory /workspace/38.uart_alert_test/latest

Test location /workspace/coverage/default/38.uart_fifo_full.784021527
Short name T422
Test name
Test status
Simulation time 120380694298 ps
CPU time 148.24 seconds
Started Jun 06 01:00:50 PM PDT 24
Finished Jun 06 01:03:19 PM PDT 24
Peak memory 200264 kb
Host smart-7ddca5e6-99c5-4500-9eab-0a8bd399e4a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784021527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.784021527
Directory /workspace/38.uart_fifo_full/latest

Test location /workspace/coverage/default/38.uart_fifo_overflow.739032252
Short name T1133
Test name
Test status
Simulation time 111657740674 ps
CPU time 25.84 seconds
Started Jun 06 01:00:48 PM PDT 24
Finished Jun 06 01:01:14 PM PDT 24
Peak memory 200156 kb
Host smart-8ddd9977-84bb-4033-a2c5-f3fbe051c7a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739032252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.739032252
Directory /workspace/38.uart_fifo_overflow/latest

Test location /workspace/coverage/default/38.uart_fifo_reset.1494555267
Short name T485
Test name
Test status
Simulation time 15035670886 ps
CPU time 27.25 seconds
Started Jun 06 01:00:50 PM PDT 24
Finished Jun 06 01:01:18 PM PDT 24
Peak memory 200092 kb
Host smart-1726a9ac-9e1c-4272-9370-c772b379bd5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494555267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.1494555267
Directory /workspace/38.uart_fifo_reset/latest

Test location /workspace/coverage/default/38.uart_intr.876860755
Short name T21
Test name
Test status
Simulation time 145420231306 ps
CPU time 97.07 seconds
Started Jun 06 01:00:49 PM PDT 24
Finished Jun 06 01:02:27 PM PDT 24
Peak memory 198812 kb
Host smart-96b8f054-52f8-45d0-a7be-eddd9f58f360
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876860755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.876860755
Directory /workspace/38.uart_intr/latest

Test location /workspace/coverage/default/38.uart_long_xfer_wo_dly.258179811
Short name T830
Test name
Test status
Simulation time 60704295480 ps
CPU time 419.23 seconds
Started Jun 06 01:01:01 PM PDT 24
Finished Jun 06 01:08:02 PM PDT 24
Peak memory 200328 kb
Host smart-48bc370e-410b-487c-bcb3-d87ac5415e1b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=258179811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.258179811
Directory /workspace/38.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/38.uart_loopback.223637630
Short name T357
Test name
Test status
Simulation time 1933482522 ps
CPU time 4.13 seconds
Started Jun 06 01:01:21 PM PDT 24
Finished Jun 06 01:01:26 PM PDT 24
Peak memory 199000 kb
Host smart-20adea0c-ef43-49f3-921f-7731522c78d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223637630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_loopback.223637630
Directory /workspace/38.uart_loopback/latest

Test location /workspace/coverage/default/38.uart_noise_filter.1444932070
Short name T1157
Test name
Test status
Simulation time 211095819045 ps
CPU time 51.42 seconds
Started Jun 06 01:00:52 PM PDT 24
Finished Jun 06 01:01:44 PM PDT 24
Peak memory 208628 kb
Host smart-bbc4cbcf-6e44-48e6-9b60-9d9b2fabbc31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444932070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_noise_filter.1444932070
Directory /workspace/38.uart_noise_filter/latest

Test location /workspace/coverage/default/38.uart_perf.1015782406
Short name T710
Test name
Test status
Simulation time 14239427039 ps
CPU time 270.44 seconds
Started Jun 06 01:01:01 PM PDT 24
Finished Jun 06 01:05:32 PM PDT 24
Peak memory 200368 kb
Host smart-a28f9b15-103a-432c-95fa-766ad19af9c5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1015782406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.1015782406
Directory /workspace/38.uart_perf/latest

Test location /workspace/coverage/default/38.uart_rx_oversample.4285808740
Short name T887
Test name
Test status
Simulation time 6074357732 ps
CPU time 54.71 seconds
Started Jun 06 01:00:50 PM PDT 24
Finished Jun 06 01:01:46 PM PDT 24
Peak memory 199680 kb
Host smart-241fb9a5-df89-4a5a-b3e5-44803e8feb33
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4285808740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.4285808740
Directory /workspace/38.uart_rx_oversample/latest

Test location /workspace/coverage/default/38.uart_rx_parity_err.3030982338
Short name T177
Test name
Test status
Simulation time 181701369698 ps
CPU time 325.96 seconds
Started Jun 06 01:01:01 PM PDT 24
Finished Jun 06 01:06:28 PM PDT 24
Peak memory 200268 kb
Host smart-35ebf947-2a0c-47d8-bea8-fc0338a84b14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030982338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.3030982338
Directory /workspace/38.uart_rx_parity_err/latest

Test location /workspace/coverage/default/38.uart_rx_start_bit_filter.3758517460
Short name T465
Test name
Test status
Simulation time 3306971784 ps
CPU time 3.23 seconds
Started Jun 06 01:00:54 PM PDT 24
Finished Jun 06 01:00:58 PM PDT 24
Peak memory 197128 kb
Host smart-d1e83a36-5291-4194-8b8a-e3a71516ec3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758517460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.3758517460
Directory /workspace/38.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/38.uart_smoke.4005364843
Short name T1072
Test name
Test status
Simulation time 898434013 ps
CPU time 1.47 seconds
Started Jun 06 01:00:49 PM PDT 24
Finished Jun 06 01:00:52 PM PDT 24
Peak memory 199444 kb
Host smart-737bb800-916c-4b5f-931b-0b900d080657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005364843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_smoke.4005364843
Directory /workspace/38.uart_smoke/latest

Test location /workspace/coverage/default/38.uart_stress_all.1726022597
Short name T982
Test name
Test status
Simulation time 215588624068 ps
CPU time 291.3 seconds
Started Jun 06 01:01:01 PM PDT 24
Finished Jun 06 01:05:54 PM PDT 24
Peak memory 200340 kb
Host smart-e53ff21b-6a1a-43e0-8217-6a84a69b2975
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726022597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.1726022597
Directory /workspace/38.uart_stress_all/latest

Test location /workspace/coverage/default/38.uart_stress_all_with_rand_reset.1844213572
Short name T524
Test name
Test status
Simulation time 102952350797 ps
CPU time 649.26 seconds
Started Jun 06 01:01:03 PM PDT 24
Finished Jun 06 01:11:53 PM PDT 24
Peak memory 217148 kb
Host smart-7f6fc67a-99f3-4eb4-a48d-df3e5255e9b7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844213572 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 38.uart_stress_all_with_rand_reset.1844213572
Directory /workspace/38.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.uart_tx_ovrd.3670342222
Short name T1019
Test name
Test status
Simulation time 1260623848 ps
CPU time 5.17 seconds
Started Jun 06 01:01:08 PM PDT 24
Finished Jun 06 01:01:14 PM PDT 24
Peak memory 199340 kb
Host smart-c63305a2-8731-498f-bf30-92b1342982c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670342222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.3670342222
Directory /workspace/38.uart_tx_ovrd/latest

Test location /workspace/coverage/default/38.uart_tx_rx.3863986771
Short name T938
Test name
Test status
Simulation time 319219820319 ps
CPU time 31.44 seconds
Started Jun 06 01:00:52 PM PDT 24
Finished Jun 06 01:01:24 PM PDT 24
Peak memory 200328 kb
Host smart-db5d9020-f061-428e-90bb-c667cd27f99d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863986771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.3863986771
Directory /workspace/38.uart_tx_rx/latest

Test location /workspace/coverage/default/39.uart_alert_test.2321609746
Short name T527
Test name
Test status
Simulation time 14209344 ps
CPU time 0.59 seconds
Started Jun 06 01:01:07 PM PDT 24
Finished Jun 06 01:01:09 PM PDT 24
Peak memory 195676 kb
Host smart-a34216da-bdbc-4c02-b4a6-d6f8577acdce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321609746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.2321609746
Directory /workspace/39.uart_alert_test/latest

Test location /workspace/coverage/default/39.uart_fifo_full.3820467015
Short name T176
Test name
Test status
Simulation time 145076831781 ps
CPU time 21.11 seconds
Started Jun 06 01:01:04 PM PDT 24
Finished Jun 06 01:01:26 PM PDT 24
Peak memory 200316 kb
Host smart-776b541e-2968-4296-b35a-5bacfcc7b983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820467015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.3820467015
Directory /workspace/39.uart_fifo_full/latest

Test location /workspace/coverage/default/39.uart_fifo_overflow.1868588026
Short name T496
Test name
Test status
Simulation time 115249365022 ps
CPU time 166.59 seconds
Started Jun 06 01:00:59 PM PDT 24
Finished Jun 06 01:03:47 PM PDT 24
Peak memory 199904 kb
Host smart-95c7f7ab-ac12-4f9f-8042-47c485e33bd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868588026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.1868588026
Directory /workspace/39.uart_fifo_overflow/latest

Test location /workspace/coverage/default/39.uart_fifo_reset.281392077
Short name T1077
Test name
Test status
Simulation time 20472734425 ps
CPU time 29.91 seconds
Started Jun 06 01:01:00 PM PDT 24
Finished Jun 06 01:01:31 PM PDT 24
Peak memory 200268 kb
Host smart-3e677e38-4c2c-4fee-9fe9-cfaa8249ac65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281392077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.281392077
Directory /workspace/39.uart_fifo_reset/latest

Test location /workspace/coverage/default/39.uart_intr.1719418311
Short name T1013
Test name
Test status
Simulation time 9594716238 ps
CPU time 19.23 seconds
Started Jun 06 01:01:00 PM PDT 24
Finished Jun 06 01:01:21 PM PDT 24
Peak memory 200072 kb
Host smart-7b742980-c544-4569-a2cb-06b976fbd188
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719418311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.1719418311
Directory /workspace/39.uart_intr/latest

Test location /workspace/coverage/default/39.uart_long_xfer_wo_dly.1046439288
Short name T380
Test name
Test status
Simulation time 92724600152 ps
CPU time 382.29 seconds
Started Jun 06 01:01:02 PM PDT 24
Finished Jun 06 01:07:25 PM PDT 24
Peak memory 200336 kb
Host smart-0fa96832-8e61-410e-9166-422432e60c0b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1046439288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.1046439288
Directory /workspace/39.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/39.uart_loopback.3885892791
Short name T947
Test name
Test status
Simulation time 8334470754 ps
CPU time 9 seconds
Started Jun 06 01:01:02 PM PDT 24
Finished Jun 06 01:01:12 PM PDT 24
Peak memory 199164 kb
Host smart-fd52cae4-01b5-4a66-8286-0e3fd9bc60b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885892791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_loopback.3885892791
Directory /workspace/39.uart_loopback/latest

Test location /workspace/coverage/default/39.uart_noise_filter.3300815459
Short name T1041
Test name
Test status
Simulation time 55959175909 ps
CPU time 104.14 seconds
Started Jun 06 01:01:00 PM PDT 24
Finished Jun 06 01:02:45 PM PDT 24
Peak memory 200500 kb
Host smart-7547be21-5fc0-4476-a48e-6c1119c6d894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300815459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_noise_filter.3300815459
Directory /workspace/39.uart_noise_filter/latest

Test location /workspace/coverage/default/39.uart_perf.1053566836
Short name T743
Test name
Test status
Simulation time 16138445042 ps
CPU time 942.3 seconds
Started Jun 06 01:01:04 PM PDT 24
Finished Jun 06 01:16:47 PM PDT 24
Peak memory 200328 kb
Host smart-26b58342-0544-4cda-8edf-6a47bc2ce96e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1053566836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.1053566836
Directory /workspace/39.uart_perf/latest

Test location /workspace/coverage/default/39.uart_rx_oversample.2637582364
Short name T929
Test name
Test status
Simulation time 2985059844 ps
CPU time 25.77 seconds
Started Jun 06 01:01:08 PM PDT 24
Finished Jun 06 01:01:34 PM PDT 24
Peak memory 199484 kb
Host smart-d11b1632-9a96-49e3-94b4-ea505b3ba3db
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2637582364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.2637582364
Directory /workspace/39.uart_rx_oversample/latest

Test location /workspace/coverage/default/39.uart_rx_parity_err.548730271
Short name T447
Test name
Test status
Simulation time 44993423770 ps
CPU time 79.11 seconds
Started Jun 06 01:01:01 PM PDT 24
Finished Jun 06 01:02:21 PM PDT 24
Peak memory 200264 kb
Host smart-662d19b6-d60a-4b3f-acda-c74640f00b79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548730271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.548730271
Directory /workspace/39.uart_rx_parity_err/latest

Test location /workspace/coverage/default/39.uart_rx_start_bit_filter.885728303
Short name T286
Test name
Test status
Simulation time 45023577580 ps
CPU time 18.44 seconds
Started Jun 06 01:01:02 PM PDT 24
Finished Jun 06 01:01:22 PM PDT 24
Peak memory 196608 kb
Host smart-3fa72014-ec9a-4104-911e-708deffa1f3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885728303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.885728303
Directory /workspace/39.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/39.uart_smoke.3703919418
Short name T454
Test name
Test status
Simulation time 711786671 ps
CPU time 2.76 seconds
Started Jun 06 01:01:02 PM PDT 24
Finished Jun 06 01:01:06 PM PDT 24
Peak memory 199024 kb
Host smart-51c148a9-6c09-4e78-b592-cd007976f9a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703919418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_smoke.3703919418
Directory /workspace/39.uart_smoke/latest

Test location /workspace/coverage/default/39.uart_stress_all.1556396364
Short name T648
Test name
Test status
Simulation time 304611905800 ps
CPU time 311.53 seconds
Started Jun 06 01:01:00 PM PDT 24
Finished Jun 06 01:06:13 PM PDT 24
Peak memory 208740 kb
Host smart-78e7ab3c-0bb5-434a-af67-967a74e2a1e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556396364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.1556396364
Directory /workspace/39.uart_stress_all/latest

Test location /workspace/coverage/default/39.uart_stress_all_with_rand_reset.2783550540
Short name T983
Test name
Test status
Simulation time 151393502124 ps
CPU time 408.01 seconds
Started Jun 06 01:00:59 PM PDT 24
Finished Jun 06 01:07:48 PM PDT 24
Peak memory 225288 kb
Host smart-deaa2ff0-53ec-4f06-9cea-3d20f4501d4d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783550540 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 39.uart_stress_all_with_rand_reset.2783550540
Directory /workspace/39.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.uart_tx_ovrd.860371006
Short name T18
Test name
Test status
Simulation time 1363850596 ps
CPU time 3.73 seconds
Started Jun 06 01:01:03 PM PDT 24
Finished Jun 06 01:01:08 PM PDT 24
Peak memory 198604 kb
Host smart-e84a153e-e90a-4974-a000-94004ac5bfc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860371006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.860371006
Directory /workspace/39.uart_tx_ovrd/latest

Test location /workspace/coverage/default/39.uart_tx_rx.3657038755
Short name T403
Test name
Test status
Simulation time 66993125649 ps
CPU time 136.24 seconds
Started Jun 06 01:01:00 PM PDT 24
Finished Jun 06 01:03:17 PM PDT 24
Peak memory 200376 kb
Host smart-0ea82cba-d937-4cb4-9147-5714e4ab03f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657038755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.3657038755
Directory /workspace/39.uart_tx_rx/latest

Test location /workspace/coverage/default/4.uart_alert_test.1623210452
Short name T850
Test name
Test status
Simulation time 41305271 ps
CPU time 0.56 seconds
Started Jun 06 12:58:05 PM PDT 24
Finished Jun 06 12:58:07 PM PDT 24
Peak memory 195652 kb
Host smart-266e3a6d-f6a8-4fed-b2d8-3b0eab870bf4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623210452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.1623210452
Directory /workspace/4.uart_alert_test/latest

Test location /workspace/coverage/default/4.uart_fifo_full.2276747964
Short name T1178
Test name
Test status
Simulation time 90086245967 ps
CPU time 10.97 seconds
Started Jun 06 12:58:02 PM PDT 24
Finished Jun 06 12:58:14 PM PDT 24
Peak memory 200344 kb
Host smart-22d70b03-6694-4796-a8d9-db009b139469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276747964 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.2276747964
Directory /workspace/4.uart_fifo_full/latest

Test location /workspace/coverage/default/4.uart_fifo_overflow.479686585
Short name T408
Test name
Test status
Simulation time 12867163608 ps
CPU time 23.05 seconds
Started Jun 06 12:58:00 PM PDT 24
Finished Jun 06 12:58:24 PM PDT 24
Peak memory 200348 kb
Host smart-2d83ea2a-10f7-4da1-adbc-bd9512be312a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479686585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.479686585
Directory /workspace/4.uart_fifo_overflow/latest

Test location /workspace/coverage/default/4.uart_fifo_reset.1359466727
Short name T896
Test name
Test status
Simulation time 179971936440 ps
CPU time 308.3 seconds
Started Jun 06 12:58:07 PM PDT 24
Finished Jun 06 01:03:17 PM PDT 24
Peak memory 200376 kb
Host smart-84f41099-bd9a-4181-90c6-493ed709a69a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359466727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.1359466727
Directory /workspace/4.uart_fifo_reset/latest

Test location /workspace/coverage/default/4.uart_intr.1720086374
Short name T512
Test name
Test status
Simulation time 8059531901 ps
CPU time 6.04 seconds
Started Jun 06 12:58:01 PM PDT 24
Finished Jun 06 12:58:08 PM PDT 24
Peak memory 200292 kb
Host smart-181c4f61-ad78-4b1a-a89a-7344e7971460
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720086374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.1720086374
Directory /workspace/4.uart_intr/latest

Test location /workspace/coverage/default/4.uart_long_xfer_wo_dly.4190815981
Short name T835
Test name
Test status
Simulation time 163741694524 ps
CPU time 1506.89 seconds
Started Jun 06 12:58:02 PM PDT 24
Finished Jun 06 01:23:11 PM PDT 24
Peak memory 200304 kb
Host smart-67be76a3-6d6e-47bd-b3e9-4bebd2b0b0ce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4190815981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.4190815981
Directory /workspace/4.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/4.uart_loopback.2533411923
Short name T458
Test name
Test status
Simulation time 4919611773 ps
CPU time 8.66 seconds
Started Jun 06 12:58:02 PM PDT 24
Finished Jun 06 12:58:12 PM PDT 24
Peak memory 200272 kb
Host smart-a566600c-42d5-4778-8091-e1366fe43b3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533411923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_loopback.2533411923
Directory /workspace/4.uart_loopback/latest

Test location /workspace/coverage/default/4.uart_noise_filter.188229564
Short name T1138
Test name
Test status
Simulation time 83763204514 ps
CPU time 124.76 seconds
Started Jun 06 12:58:06 PM PDT 24
Finished Jun 06 01:00:12 PM PDT 24
Peak memory 200676 kb
Host smart-eddc2262-64e2-4acd-b8fe-9e83b8620092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188229564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_noise_filter.188229564
Directory /workspace/4.uart_noise_filter/latest

Test location /workspace/coverage/default/4.uart_perf.519663543
Short name T724
Test name
Test status
Simulation time 14266040789 ps
CPU time 805.01 seconds
Started Jun 06 12:58:01 PM PDT 24
Finished Jun 06 01:11:28 PM PDT 24
Peak memory 200344 kb
Host smart-35d2c072-cd73-49c2-b043-92c565670724
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=519663543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.519663543
Directory /workspace/4.uart_perf/latest

Test location /workspace/coverage/default/4.uart_rx_oversample.2243884785
Short name T705
Test name
Test status
Simulation time 7269099640 ps
CPU time 17.19 seconds
Started Jun 06 12:58:00 PM PDT 24
Finished Jun 06 12:58:19 PM PDT 24
Peak memory 199788 kb
Host smart-7b85478d-5fb6-4ec6-9e13-04648f0d57f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2243884785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.2243884785
Directory /workspace/4.uart_rx_oversample/latest

Test location /workspace/coverage/default/4.uart_rx_parity_err.457765895
Short name T618
Test name
Test status
Simulation time 98301659301 ps
CPU time 191.12 seconds
Started Jun 06 12:58:07 PM PDT 24
Finished Jun 06 01:01:19 PM PDT 24
Peak memory 200280 kb
Host smart-12260360-5ce7-496c-9dc1-3763fe919333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457765895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.457765895
Directory /workspace/4.uart_rx_parity_err/latest

Test location /workspace/coverage/default/4.uart_rx_start_bit_filter.2309275114
Short name T480
Test name
Test status
Simulation time 2945674375 ps
CPU time 1.73 seconds
Started Jun 06 12:58:07 PM PDT 24
Finished Jun 06 12:58:09 PM PDT 24
Peak memory 196308 kb
Host smart-1266b3d6-b73f-4cdf-9ab0-c1187146da81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309275114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.2309275114
Directory /workspace/4.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/4.uart_smoke.2517388431
Short name T287
Test name
Test status
Simulation time 697557474 ps
CPU time 1.54 seconds
Started Jun 06 12:58:03 PM PDT 24
Finished Jun 06 12:58:06 PM PDT 24
Peak memory 199200 kb
Host smart-f5564628-35a1-4177-a15d-53ab10809ba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517388431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_smoke.2517388431
Directory /workspace/4.uart_smoke/latest

Test location /workspace/coverage/default/4.uart_stress_all.2739861354
Short name T171
Test name
Test status
Simulation time 235071379142 ps
CPU time 492.82 seconds
Started Jun 06 12:58:05 PM PDT 24
Finished Jun 06 01:06:19 PM PDT 24
Peak memory 208840 kb
Host smart-73d2f0f2-5e24-4fd0-b15d-9156b7d8a066
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739861354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.2739861354
Directory /workspace/4.uart_stress_all/latest

Test location /workspace/coverage/default/4.uart_stress_all_with_rand_reset.2054607815
Short name T1116
Test name
Test status
Simulation time 300013463834 ps
CPU time 235.27 seconds
Started Jun 06 12:58:04 PM PDT 24
Finished Jun 06 01:02:01 PM PDT 24
Peak memory 217028 kb
Host smart-f6b0267a-670c-46e7-b352-9a4caec89982
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054607815 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.uart_stress_all_with_rand_reset.2054607815
Directory /workspace/4.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.uart_tx_ovrd.988670377
Short name T332
Test name
Test status
Simulation time 1509353465 ps
CPU time 2.78 seconds
Started Jun 06 12:58:07 PM PDT 24
Finished Jun 06 12:58:10 PM PDT 24
Peak memory 200124 kb
Host smart-2c787729-d119-40d1-acbf-860a9bec90cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988670377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.988670377
Directory /workspace/4.uart_tx_ovrd/latest

Test location /workspace/coverage/default/4.uart_tx_rx.1346151167
Short name T1048
Test name
Test status
Simulation time 70601823583 ps
CPU time 43.81 seconds
Started Jun 06 12:58:04 PM PDT 24
Finished Jun 06 12:58:49 PM PDT 24
Peak memory 200128 kb
Host smart-614273e0-4ec1-4f79-8b06-69417d6ae167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346151167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.1346151167
Directory /workspace/4.uart_tx_rx/latest

Test location /workspace/coverage/default/40.uart_alert_test.4243680724
Short name T373
Test name
Test status
Simulation time 10981099 ps
CPU time 0.56 seconds
Started Jun 06 01:01:15 PM PDT 24
Finished Jun 06 01:01:17 PM PDT 24
Peak memory 195720 kb
Host smart-a50e0167-a296-4ff0-9429-d15dc62ae668
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243680724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.4243680724
Directory /workspace/40.uart_alert_test/latest

Test location /workspace/coverage/default/40.uart_fifo_full.2848903723
Short name T303
Test name
Test status
Simulation time 253705954818 ps
CPU time 532.15 seconds
Started Jun 06 01:01:03 PM PDT 24
Finished Jun 06 01:09:56 PM PDT 24
Peak memory 200384 kb
Host smart-a54806a9-e04f-4af2-bba4-762988324d55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848903723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.2848903723
Directory /workspace/40.uart_fifo_full/latest

Test location /workspace/coverage/default/40.uart_fifo_overflow.3316609054
Short name T606
Test name
Test status
Simulation time 145689441734 ps
CPU time 89.59 seconds
Started Jun 06 01:01:02 PM PDT 24
Finished Jun 06 01:02:32 PM PDT 24
Peak memory 200296 kb
Host smart-77c05365-f4d7-4cd1-b8f6-806b932bf1b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316609054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.3316609054
Directory /workspace/40.uart_fifo_overflow/latest

Test location /workspace/coverage/default/40.uart_fifo_reset.1851811619
Short name T560
Test name
Test status
Simulation time 68610276759 ps
CPU time 39.68 seconds
Started Jun 06 01:01:03 PM PDT 24
Finished Jun 06 01:01:43 PM PDT 24
Peak memory 200352 kb
Host smart-8b6c5804-df54-4cc3-864c-3b7bd1c9d3af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851811619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.1851811619
Directory /workspace/40.uart_fifo_reset/latest

Test location /workspace/coverage/default/40.uart_intr.221203257
Short name T416
Test name
Test status
Simulation time 27652138487 ps
CPU time 11.8 seconds
Started Jun 06 01:01:07 PM PDT 24
Finished Jun 06 01:01:20 PM PDT 24
Peak memory 199548 kb
Host smart-90d2e463-564d-4b50-b929-f864e09d9595
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221203257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.221203257
Directory /workspace/40.uart_intr/latest

Test location /workspace/coverage/default/40.uart_long_xfer_wo_dly.2906765169
Short name T1177
Test name
Test status
Simulation time 41202825173 ps
CPU time 59.27 seconds
Started Jun 06 01:01:10 PM PDT 24
Finished Jun 06 01:02:11 PM PDT 24
Peak memory 200348 kb
Host smart-f094717c-5f10-4a88-bfc8-1dc83f5b3a3c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2906765169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.2906765169
Directory /workspace/40.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/40.uart_loopback.186004699
Short name T116
Test name
Test status
Simulation time 1884854268 ps
CPU time 1.02 seconds
Started Jun 06 01:01:11 PM PDT 24
Finished Jun 06 01:01:13 PM PDT 24
Peak memory 195724 kb
Host smart-b2ea17b1-b73b-4716-a01c-81b1645d3ed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186004699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_loopback.186004699
Directory /workspace/40.uart_loopback/latest

Test location /workspace/coverage/default/40.uart_noise_filter.1110841018
Short name T437
Test name
Test status
Simulation time 67202651360 ps
CPU time 37.94 seconds
Started Jun 06 01:01:04 PM PDT 24
Finished Jun 06 01:01:42 PM PDT 24
Peak memory 200584 kb
Host smart-60c783f5-90cd-40f9-b1f2-f8f31d95d548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110841018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_noise_filter.1110841018
Directory /workspace/40.uart_noise_filter/latest

Test location /workspace/coverage/default/40.uart_perf.4181011736
Short name T1163
Test name
Test status
Simulation time 7250154591 ps
CPU time 419.02 seconds
Started Jun 06 01:01:12 PM PDT 24
Finished Jun 06 01:08:12 PM PDT 24
Peak memory 200336 kb
Host smart-9b2d2e3c-cdcb-479b-8f64-3501c9509984
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4181011736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.4181011736
Directory /workspace/40.uart_perf/latest

Test location /workspace/coverage/default/40.uart_rx_oversample.3359529478
Short name T381
Test name
Test status
Simulation time 2819434161 ps
CPU time 7.97 seconds
Started Jun 06 01:01:01 PM PDT 24
Finished Jun 06 01:01:10 PM PDT 24
Peak memory 199284 kb
Host smart-6f8f4dde-8808-4bf9-93d9-8785f400ca0d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3359529478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.3359529478
Directory /workspace/40.uart_rx_oversample/latest

Test location /workspace/coverage/default/40.uart_rx_parity_err.3965565635
Short name T993
Test name
Test status
Simulation time 193292867550 ps
CPU time 91.98 seconds
Started Jun 06 01:01:11 PM PDT 24
Finished Jun 06 01:02:45 PM PDT 24
Peak memory 200332 kb
Host smart-7411d52a-67af-41f5-9e2e-54c3500dc997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965565635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.3965565635
Directory /workspace/40.uart_rx_parity_err/latest

Test location /workspace/coverage/default/40.uart_rx_start_bit_filter.2773333412
Short name T54
Test name
Test status
Simulation time 3395809418 ps
CPU time 6.41 seconds
Started Jun 06 01:01:12 PM PDT 24
Finished Jun 06 01:01:19 PM PDT 24
Peak memory 196788 kb
Host smart-e59104eb-a0a0-4167-a893-87e2453f46e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773333412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.2773333412
Directory /workspace/40.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/40.uart_smoke.1328335408
Short name T433
Test name
Test status
Simulation time 500902149 ps
CPU time 1.69 seconds
Started Jun 06 01:01:02 PM PDT 24
Finished Jun 06 01:01:05 PM PDT 24
Peak memory 199080 kb
Host smart-1c232d33-56d2-4230-a813-55189cdb8a98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328335408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_smoke.1328335408
Directory /workspace/40.uart_smoke/latest

Test location /workspace/coverage/default/40.uart_stress_all.2003968010
Short name T665
Test name
Test status
Simulation time 1041647163012 ps
CPU time 229.8 seconds
Started Jun 06 01:01:12 PM PDT 24
Finished Jun 06 01:05:04 PM PDT 24
Peak memory 216472 kb
Host smart-7f2c00d0-6072-439d-af00-86e38e862d2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003968010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.2003968010
Directory /workspace/40.uart_stress_all/latest

Test location /workspace/coverage/default/40.uart_stress_all_with_rand_reset.3764912915
Short name T1022
Test name
Test status
Simulation time 61642150853 ps
CPU time 345.12 seconds
Started Jun 06 01:01:11 PM PDT 24
Finished Jun 06 01:06:57 PM PDT 24
Peak memory 217124 kb
Host smart-fb2ad6c3-240d-4ec8-aa62-dbcdeaad65ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764912915 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 40.uart_stress_all_with_rand_reset.3764912915
Directory /workspace/40.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.uart_tx_ovrd.2685928536
Short name T1151
Test name
Test status
Simulation time 5990840736 ps
CPU time 25 seconds
Started Jun 06 01:01:14 PM PDT 24
Finished Jun 06 01:01:40 PM PDT 24
Peak memory 200380 kb
Host smart-135cc1fd-1087-4c4b-ba88-4e116eb3e916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685928536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.2685928536
Directory /workspace/40.uart_tx_ovrd/latest

Test location /workspace/coverage/default/40.uart_tx_rx.168349192
Short name T1044
Test name
Test status
Simulation time 65220117701 ps
CPU time 26.55 seconds
Started Jun 06 01:01:03 PM PDT 24
Finished Jun 06 01:01:30 PM PDT 24
Peak memory 200392 kb
Host smart-d599395b-c8dc-413e-bde3-efc05c1a0342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168349192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.168349192
Directory /workspace/40.uart_tx_rx/latest

Test location /workspace/coverage/default/41.uart_alert_test.782631435
Short name T1057
Test name
Test status
Simulation time 21037957 ps
CPU time 0.55 seconds
Started Jun 06 01:01:13 PM PDT 24
Finished Jun 06 01:01:15 PM PDT 24
Peak memory 195736 kb
Host smart-d27e37c9-95a1-490f-84bb-571289ee3526
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782631435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.782631435
Directory /workspace/41.uart_alert_test/latest

Test location /workspace/coverage/default/41.uart_fifo_full.3937169161
Short name T969
Test name
Test status
Simulation time 180201875725 ps
CPU time 115.59 seconds
Started Jun 06 01:01:11 PM PDT 24
Finished Jun 06 01:03:08 PM PDT 24
Peak memory 200328 kb
Host smart-5a90f855-d937-4f26-a134-8a5c756468a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937169161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.3937169161
Directory /workspace/41.uart_fifo_full/latest

Test location /workspace/coverage/default/41.uart_fifo_overflow.948930309
Short name T610
Test name
Test status
Simulation time 84842951418 ps
CPU time 40.86 seconds
Started Jun 06 01:01:11 PM PDT 24
Finished Jun 06 01:01:54 PM PDT 24
Peak memory 200292 kb
Host smart-297fb6bc-5f8b-4268-bcec-e24f32d21284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948930309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.948930309
Directory /workspace/41.uart_fifo_overflow/latest

Test location /workspace/coverage/default/41.uart_fifo_reset.2198951198
Short name T694
Test name
Test status
Simulation time 18010417693 ps
CPU time 24.9 seconds
Started Jun 06 01:01:12 PM PDT 24
Finished Jun 06 01:01:38 PM PDT 24
Peak memory 200112 kb
Host smart-ad8233c1-be12-46af-bc2a-c2376819cf57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198951198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.2198951198
Directory /workspace/41.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_intr.573928592
Short name T555
Test name
Test status
Simulation time 25851642481 ps
CPU time 26.62 seconds
Started Jun 06 01:01:11 PM PDT 24
Finished Jun 06 01:01:39 PM PDT 24
Peak memory 200252 kb
Host smart-e5ee0aef-2fa5-458b-b470-e7ace03c5f50
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573928592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.573928592
Directory /workspace/41.uart_intr/latest

Test location /workspace/coverage/default/41.uart_long_xfer_wo_dly.4205193053
Short name T832
Test name
Test status
Simulation time 121934052984 ps
CPU time 293.48 seconds
Started Jun 06 01:01:12 PM PDT 24
Finished Jun 06 01:06:07 PM PDT 24
Peak memory 200384 kb
Host smart-06ecf27a-c744-43ec-8774-70a7686e74d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4205193053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.4205193053
Directory /workspace/41.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/41.uart_loopback.1423067446
Short name T519
Test name
Test status
Simulation time 1768948248 ps
CPU time 1.58 seconds
Started Jun 06 01:01:13 PM PDT 24
Finished Jun 06 01:01:16 PM PDT 24
Peak memory 196336 kb
Host smart-9e7d8e53-fb0d-4096-bf34-5e829a8b93b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423067446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_loopback.1423067446
Directory /workspace/41.uart_loopback/latest

Test location /workspace/coverage/default/41.uart_noise_filter.2683934379
Short name T1055
Test name
Test status
Simulation time 111073416996 ps
CPU time 158.25 seconds
Started Jun 06 01:01:12 PM PDT 24
Finished Jun 06 01:03:51 PM PDT 24
Peak memory 199292 kb
Host smart-31b7e7bb-066d-4bc2-bf8b-c3a7e7b3abed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683934379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_noise_filter.2683934379
Directory /workspace/41.uart_noise_filter/latest

Test location /workspace/coverage/default/41.uart_perf.2924034434
Short name T342
Test name
Test status
Simulation time 2433210580 ps
CPU time 72.02 seconds
Started Jun 06 01:01:12 PM PDT 24
Finished Jun 06 01:02:26 PM PDT 24
Peak memory 200204 kb
Host smart-15b28992-dc77-4cc1-a635-12537863e8bb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2924034434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.2924034434
Directory /workspace/41.uart_perf/latest

Test location /workspace/coverage/default/41.uart_rx_oversample.3646510
Short name T833
Test name
Test status
Simulation time 6451317807 ps
CPU time 7.2 seconds
Started Jun 06 01:01:12 PM PDT 24
Finished Jun 06 01:01:21 PM PDT 24
Peak memory 198484 kb
Host smart-bdc69e40-f5bc-4a88-937c-58d198581dad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3646510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.3646510
Directory /workspace/41.uart_rx_oversample/latest

Test location /workspace/coverage/default/41.uart_rx_parity_err.3233422349
Short name T680
Test name
Test status
Simulation time 33171569700 ps
CPU time 17.32 seconds
Started Jun 06 01:01:11 PM PDT 24
Finished Jun 06 01:01:30 PM PDT 24
Peak memory 200208 kb
Host smart-9ee15b5d-b550-47cb-979f-105c88648e2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233422349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.3233422349
Directory /workspace/41.uart_rx_parity_err/latest

Test location /workspace/coverage/default/41.uart_rx_start_bit_filter.1163970595
Short name T829
Test name
Test status
Simulation time 7209990954 ps
CPU time 3.26 seconds
Started Jun 06 01:01:12 PM PDT 24
Finished Jun 06 01:01:17 PM PDT 24
Peak memory 196360 kb
Host smart-fba90076-3016-48ca-8b16-6a52433933f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163970595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.1163970595
Directory /workspace/41.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/41.uart_smoke.1497705052
Short name T1000
Test name
Test status
Simulation time 438342353 ps
CPU time 1.45 seconds
Started Jun 06 01:01:12 PM PDT 24
Finished Jun 06 01:01:15 PM PDT 24
Peak memory 198548 kb
Host smart-e622175c-288d-402f-af72-313102c9c093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497705052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_smoke.1497705052
Directory /workspace/41.uart_smoke/latest

Test location /workspace/coverage/default/41.uart_stress_all.854942577
Short name T910
Test name
Test status
Simulation time 827366628052 ps
CPU time 122.26 seconds
Started Jun 06 01:01:13 PM PDT 24
Finished Jun 06 01:03:17 PM PDT 24
Peak memory 200324 kb
Host smart-25df097e-f5f9-4ee3-8cc6-6f6f8c1e9467
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854942577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.854942577
Directory /workspace/41.uart_stress_all/latest

Test location /workspace/coverage/default/41.uart_stress_all_with_rand_reset.298641505
Short name T1119
Test name
Test status
Simulation time 43801390989 ps
CPU time 390.82 seconds
Started Jun 06 01:01:14 PM PDT 24
Finished Jun 06 01:07:46 PM PDT 24
Peak memory 217132 kb
Host smart-8425db1b-38ab-4bbf-a14e-6b7f8a74fbdd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298641505 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 41.uart_stress_all_with_rand_reset.298641505
Directory /workspace/41.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.uart_tx_ovrd.2409357956
Short name T932
Test name
Test status
Simulation time 6247275875 ps
CPU time 1.63 seconds
Started Jun 06 01:01:13 PM PDT 24
Finished Jun 06 01:01:16 PM PDT 24
Peak memory 199480 kb
Host smart-5a1530ed-f8d6-4332-a799-a2a872657f3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409357956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.2409357956
Directory /workspace/41.uart_tx_ovrd/latest

Test location /workspace/coverage/default/41.uart_tx_rx.445105365
Short name T870
Test name
Test status
Simulation time 66338673939 ps
CPU time 61.74 seconds
Started Jun 06 01:01:10 PM PDT 24
Finished Jun 06 01:02:13 PM PDT 24
Peak memory 200388 kb
Host smart-2318bbc2-c4e8-4208-a001-8136b2f32e22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445105365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.445105365
Directory /workspace/41.uart_tx_rx/latest

Test location /workspace/coverage/default/42.uart_alert_test.1122871481
Short name T9
Test name
Test status
Simulation time 28643301 ps
CPU time 0.57 seconds
Started Jun 06 01:01:26 PM PDT 24
Finished Jun 06 01:01:28 PM PDT 24
Peak memory 195988 kb
Host smart-07b1b6cb-21f4-4c65-8307-ccd5e80c8fe7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122871481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.1122871481
Directory /workspace/42.uart_alert_test/latest

Test location /workspace/coverage/default/42.uart_fifo_full.60487227
Short name T1051
Test name
Test status
Simulation time 9072727144 ps
CPU time 13.5 seconds
Started Jun 06 01:01:15 PM PDT 24
Finished Jun 06 01:01:30 PM PDT 24
Peak memory 200308 kb
Host smart-d1a903dc-5f49-406c-bbf7-21f89374b526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60487227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.60487227
Directory /workspace/42.uart_fifo_full/latest

Test location /workspace/coverage/default/42.uart_fifo_overflow.358274088
Short name T1011
Test name
Test status
Simulation time 128712703582 ps
CPU time 99.99 seconds
Started Jun 06 01:01:13 PM PDT 24
Finished Jun 06 01:02:55 PM PDT 24
Peak memory 200128 kb
Host smart-865fe0cd-fdba-4520-9900-f3ae1bb1c480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358274088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.358274088
Directory /workspace/42.uart_fifo_overflow/latest

Test location /workspace/coverage/default/42.uart_fifo_reset.2569307496
Short name T649
Test name
Test status
Simulation time 93477795020 ps
CPU time 34.79 seconds
Started Jun 06 01:01:14 PM PDT 24
Finished Jun 06 01:01:50 PM PDT 24
Peak memory 200632 kb
Host smart-4c76ce74-afe7-485f-8578-f66e36a1aa1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569307496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.2569307496
Directory /workspace/42.uart_fifo_reset/latest

Test location /workspace/coverage/default/42.uart_intr.1647718087
Short name T504
Test name
Test status
Simulation time 19758313048 ps
CPU time 34.98 seconds
Started Jun 06 01:01:16 PM PDT 24
Finished Jun 06 01:01:52 PM PDT 24
Peak memory 200364 kb
Host smart-da021154-1130-4711-bad6-26cd79dc7da4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647718087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.1647718087
Directory /workspace/42.uart_intr/latest

Test location /workspace/coverage/default/42.uart_long_xfer_wo_dly.2999738838
Short name T768
Test name
Test status
Simulation time 144559387413 ps
CPU time 436.5 seconds
Started Jun 06 01:01:20 PM PDT 24
Finished Jun 06 01:08:38 PM PDT 24
Peak memory 200320 kb
Host smart-9550958b-32fa-4f05-bf04-f91bf4ab17d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2999738838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.2999738838
Directory /workspace/42.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/42.uart_loopback.2277866231
Short name T642
Test name
Test status
Simulation time 6595630225 ps
CPU time 6.06 seconds
Started Jun 06 01:01:21 PM PDT 24
Finished Jun 06 01:01:29 PM PDT 24
Peak memory 200012 kb
Host smart-534e773e-466e-4d76-9fe3-80b2f09c7f79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277866231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_loopback.2277866231
Directory /workspace/42.uart_loopback/latest

Test location /workspace/coverage/default/42.uart_noise_filter.583147178
Short name T1186
Test name
Test status
Simulation time 37486592478 ps
CPU time 76.31 seconds
Started Jun 06 01:01:13 PM PDT 24
Finished Jun 06 01:02:31 PM PDT 24
Peak memory 208804 kb
Host smart-a4ff0ff1-c6cf-489f-989f-89a504d78a4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583147178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_noise_filter.583147178
Directory /workspace/42.uart_noise_filter/latest

Test location /workspace/coverage/default/42.uart_perf.1837537094
Short name T260
Test name
Test status
Simulation time 32405754150 ps
CPU time 408.87 seconds
Started Jun 06 01:01:25 PM PDT 24
Finished Jun 06 01:08:16 PM PDT 24
Peak memory 200388 kb
Host smart-fa97c86c-8bd5-4c5d-bb7e-3642d83b7dcd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1837537094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.1837537094
Directory /workspace/42.uart_perf/latest

Test location /workspace/coverage/default/42.uart_rx_oversample.299646292
Short name T675
Test name
Test status
Simulation time 4540026467 ps
CPU time 17.69 seconds
Started Jun 06 01:01:15 PM PDT 24
Finished Jun 06 01:01:35 PM PDT 24
Peak memory 198268 kb
Host smart-b176601e-36fb-4882-b862-41e0f9fa271d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=299646292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.299646292
Directory /workspace/42.uart_rx_oversample/latest

Test location /workspace/coverage/default/42.uart_rx_parity_err.1094790365
Short name T1069
Test name
Test status
Simulation time 20054703030 ps
CPU time 67.42 seconds
Started Jun 06 01:01:17 PM PDT 24
Finished Jun 06 01:02:25 PM PDT 24
Peak memory 200308 kb
Host smart-7e89bae3-61a9-40ac-8dde-aecc08767ac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094790365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.1094790365
Directory /workspace/42.uart_rx_parity_err/latest

Test location /workspace/coverage/default/42.uart_rx_start_bit_filter.1064690757
Short name T414
Test name
Test status
Simulation time 39055565329 ps
CPU time 60.7 seconds
Started Jun 06 01:01:12 PM PDT 24
Finished Jun 06 01:02:15 PM PDT 24
Peak memory 196336 kb
Host smart-cd9e3226-d275-4206-9e68-fcbb9927b1f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064690757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.1064690757
Directory /workspace/42.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/42.uart_smoke.2562955224
Short name T641
Test name
Test status
Simulation time 800396428 ps
CPU time 2.77 seconds
Started Jun 06 01:01:14 PM PDT 24
Finished Jun 06 01:01:18 PM PDT 24
Peak memory 198992 kb
Host smart-9c6d034e-1058-49f8-9474-b1a421b7af37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562955224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_smoke.2562955224
Directory /workspace/42.uart_smoke/latest

Test location /workspace/coverage/default/42.uart_stress_all_with_rand_reset.3587301689
Short name T482
Test name
Test status
Simulation time 342759057768 ps
CPU time 950.28 seconds
Started Jun 06 01:01:22 PM PDT 24
Finished Jun 06 01:17:14 PM PDT 24
Peak memory 225272 kb
Host smart-7ed1184e-0698-450c-82e1-bd7ea19db0ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587301689 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 42.uart_stress_all_with_rand_reset.3587301689
Directory /workspace/42.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.uart_tx_ovrd.3903087149
Short name T631
Test name
Test status
Simulation time 7229153278 ps
CPU time 17.25 seconds
Started Jun 06 01:01:19 PM PDT 24
Finished Jun 06 01:01:37 PM PDT 24
Peak memory 200328 kb
Host smart-6279e6f1-3512-4d9b-8373-011b88e3f6a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903087149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.3903087149
Directory /workspace/42.uart_tx_ovrd/latest

Test location /workspace/coverage/default/42.uart_tx_rx.3408230873
Short name T1165
Test name
Test status
Simulation time 36154898409 ps
CPU time 61.07 seconds
Started Jun 06 01:01:15 PM PDT 24
Finished Jun 06 01:02:17 PM PDT 24
Peak memory 200388 kb
Host smart-e5ff34ba-c823-4a19-9916-6e8c4047dd2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408230873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.3408230873
Directory /workspace/42.uart_tx_rx/latest

Test location /workspace/coverage/default/43.uart_alert_test.1171031002
Short name T368
Test name
Test status
Simulation time 12930609 ps
CPU time 0.54 seconds
Started Jun 06 01:01:21 PM PDT 24
Finished Jun 06 01:01:22 PM PDT 24
Peak memory 194716 kb
Host smart-db9321cd-8ea5-4d63-a03c-e703d3677c1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171031002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.1171031002
Directory /workspace/43.uart_alert_test/latest

Test location /workspace/coverage/default/43.uart_fifo_full.1599421601
Short name T149
Test name
Test status
Simulation time 69330001218 ps
CPU time 26.97 seconds
Started Jun 06 01:01:23 PM PDT 24
Finished Jun 06 01:01:52 PM PDT 24
Peak memory 200356 kb
Host smart-9a3b4d21-1e84-40f8-b144-3a0d8664497f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599421601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.1599421601
Directory /workspace/43.uart_fifo_full/latest

Test location /workspace/coverage/default/43.uart_fifo_overflow.1495245242
Short name T928
Test name
Test status
Simulation time 16722528572 ps
CPU time 8.57 seconds
Started Jun 06 01:01:23 PM PDT 24
Finished Jun 06 01:01:33 PM PDT 24
Peak memory 200096 kb
Host smart-e2fdb801-6aa5-401e-9e0a-2959df53214d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495245242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.1495245242
Directory /workspace/43.uart_fifo_overflow/latest

Test location /workspace/coverage/default/43.uart_fifo_reset.3819691994
Short name T329
Test name
Test status
Simulation time 18171044717 ps
CPU time 29.05 seconds
Started Jun 06 01:01:22 PM PDT 24
Finished Jun 06 01:01:53 PM PDT 24
Peak memory 200192 kb
Host smart-d6920e8b-403c-447e-a903-9a6a15beb853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819691994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.3819691994
Directory /workspace/43.uart_fifo_reset/latest

Test location /workspace/coverage/default/43.uart_intr.1116899529
Short name T311
Test name
Test status
Simulation time 69663162468 ps
CPU time 16.62 seconds
Started Jun 06 01:01:21 PM PDT 24
Finished Jun 06 01:01:40 PM PDT 24
Peak memory 200292 kb
Host smart-4effb31e-0711-4e07-b041-d537ddb2964d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116899529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.1116899529
Directory /workspace/43.uart_intr/latest

Test location /workspace/coverage/default/43.uart_long_xfer_wo_dly.3972856715
Short name T259
Test name
Test status
Simulation time 132734934532 ps
CPU time 390.12 seconds
Started Jun 06 01:01:24 PM PDT 24
Finished Jun 06 01:07:56 PM PDT 24
Peak memory 200372 kb
Host smart-28aeb011-3707-4f50-917c-04edb66c4728
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3972856715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.3972856715
Directory /workspace/43.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/43.uart_loopback.4019860806
Short name T1100
Test name
Test status
Simulation time 7662837555 ps
CPU time 7.05 seconds
Started Jun 06 01:01:22 PM PDT 24
Finished Jun 06 01:01:31 PM PDT 24
Peak memory 200284 kb
Host smart-b9cbdeb8-8e6f-4f88-831d-0327f575f7ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019860806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_loopback.4019860806
Directory /workspace/43.uart_loopback/latest

Test location /workspace/coverage/default/43.uart_noise_filter.265500970
Short name T309
Test name
Test status
Simulation time 125183949793 ps
CPU time 41.52 seconds
Started Jun 06 01:01:21 PM PDT 24
Finished Jun 06 01:02:04 PM PDT 24
Peak memory 208636 kb
Host smart-e79a4ae9-02af-431f-aa49-9533b9846a0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265500970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_noise_filter.265500970
Directory /workspace/43.uart_noise_filter/latest

Test location /workspace/coverage/default/43.uart_perf.944086876
Short name T521
Test name
Test status
Simulation time 35548060834 ps
CPU time 286.93 seconds
Started Jun 06 01:01:22 PM PDT 24
Finished Jun 06 01:06:10 PM PDT 24
Peak memory 200384 kb
Host smart-e1b128bd-93f0-43f0-92cc-a2004c064505
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=944086876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.944086876
Directory /workspace/43.uart_perf/latest

Test location /workspace/coverage/default/43.uart_rx_oversample.3378890117
Short name T472
Test name
Test status
Simulation time 3233118501 ps
CPU time 23.92 seconds
Started Jun 06 01:01:22 PM PDT 24
Finished Jun 06 01:01:48 PM PDT 24
Peak memory 198440 kb
Host smart-2ea179d6-11cb-4673-a041-5ca01d01d06c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3378890117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.3378890117
Directory /workspace/43.uart_rx_oversample/latest

Test location /workspace/coverage/default/43.uart_rx_parity_err.3712970556
Short name T1111
Test name
Test status
Simulation time 73879422323 ps
CPU time 12.03 seconds
Started Jun 06 01:01:22 PM PDT 24
Finished Jun 06 01:01:36 PM PDT 24
Peak memory 198752 kb
Host smart-1fe2d289-772d-4cf4-a461-aa3e3a9de247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712970556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.3712970556
Directory /workspace/43.uart_rx_parity_err/latest

Test location /workspace/coverage/default/43.uart_rx_start_bit_filter.3136629817
Short name T404
Test name
Test status
Simulation time 35733906535 ps
CPU time 16.09 seconds
Started Jun 06 01:01:22 PM PDT 24
Finished Jun 06 01:01:39 PM PDT 24
Peak memory 196436 kb
Host smart-d394213b-ef4c-4771-8e0d-187c4fd1a354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136629817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.3136629817
Directory /workspace/43.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/43.uart_smoke.201749327
Short name T763
Test name
Test status
Simulation time 535859177 ps
CPU time 1.36 seconds
Started Jun 06 01:01:22 PM PDT 24
Finished Jun 06 01:01:25 PM PDT 24
Peak memory 199072 kb
Host smart-993d27c3-168f-4b3a-a8f4-cb36a110d4a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201749327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_smoke.201749327
Directory /workspace/43.uart_smoke/latest

Test location /workspace/coverage/default/43.uart_stress_all.2870664026
Short name T131
Test name
Test status
Simulation time 381345619077 ps
CPU time 505.03 seconds
Started Jun 06 01:01:23 PM PDT 24
Finished Jun 06 01:09:50 PM PDT 24
Peak memory 216312 kb
Host smart-e21911b3-bc85-4ef5-a0a0-19436fee1e1f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870664026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.2870664026
Directory /workspace/43.uart_stress_all/latest

Test location /workspace/coverage/default/43.uart_stress_all_with_rand_reset.1853019860
Short name T319
Test name
Test status
Simulation time 30011631591 ps
CPU time 220.5 seconds
Started Jun 06 01:01:24 PM PDT 24
Finished Jun 06 01:05:06 PM PDT 24
Peak memory 216012 kb
Host smart-4c9ba2f2-f6c2-4044-afca-a5e913ca69c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853019860 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 43.uart_stress_all_with_rand_reset.1853019860
Directory /workspace/43.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.uart_tx_ovrd.742095079
Short name T557
Test name
Test status
Simulation time 6062117310 ps
CPU time 13.98 seconds
Started Jun 06 01:01:19 PM PDT 24
Finished Jun 06 01:01:34 PM PDT 24
Peak memory 199656 kb
Host smart-82062309-8f74-46c5-a634-6f02b3dbce0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742095079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.742095079
Directory /workspace/43.uart_tx_ovrd/latest

Test location /workspace/coverage/default/43.uart_tx_rx.2343688502
Short name T600
Test name
Test status
Simulation time 74477756135 ps
CPU time 121.83 seconds
Started Jun 06 01:01:20 PM PDT 24
Finished Jun 06 01:03:23 PM PDT 24
Peak memory 200260 kb
Host smart-27712c96-7ec8-4a18-b135-b2c4d82f1640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343688502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.2343688502
Directory /workspace/43.uart_tx_rx/latest

Test location /workspace/coverage/default/44.uart_alert_test.3797439344
Short name T827
Test name
Test status
Simulation time 22975423 ps
CPU time 0.56 seconds
Started Jun 06 01:01:30 PM PDT 24
Finished Jun 06 01:01:33 PM PDT 24
Peak memory 195712 kb
Host smart-1c64d550-aa84-40f6-aebd-58ef94bf28b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797439344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.3797439344
Directory /workspace/44.uart_alert_test/latest

Test location /workspace/coverage/default/44.uart_fifo_full.2938475871
Short name T365
Test name
Test status
Simulation time 165762558229 ps
CPU time 38.22 seconds
Started Jun 06 01:01:22 PM PDT 24
Finished Jun 06 01:02:01 PM PDT 24
Peak memory 200340 kb
Host smart-01b459ea-e304-44c3-b999-8e6eb9657727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938475871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.2938475871
Directory /workspace/44.uart_fifo_full/latest

Test location /workspace/coverage/default/44.uart_fifo_overflow.3361737419
Short name T876
Test name
Test status
Simulation time 86768384420 ps
CPU time 137.85 seconds
Started Jun 06 01:01:23 PM PDT 24
Finished Jun 06 01:03:42 PM PDT 24
Peak memory 200372 kb
Host smart-e71f46c0-35ff-4ced-9b28-92923243ae48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361737419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.3361737419
Directory /workspace/44.uart_fifo_overflow/latest

Test location /workspace/coverage/default/44.uart_fifo_reset.2888712500
Short name T197
Test name
Test status
Simulation time 93450417543 ps
CPU time 291.35 seconds
Started Jun 06 01:01:24 PM PDT 24
Finished Jun 06 01:06:17 PM PDT 24
Peak memory 200328 kb
Host smart-0ebdbe22-cbc5-458d-a900-18b81850c77b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888712500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.2888712500
Directory /workspace/44.uart_fifo_reset/latest

Test location /workspace/coverage/default/44.uart_intr.3279462396
Short name T491
Test name
Test status
Simulation time 328588891800 ps
CPU time 133.58 seconds
Started Jun 06 01:01:25 PM PDT 24
Finished Jun 06 01:03:40 PM PDT 24
Peak memory 198300 kb
Host smart-14300536-e8fd-41ec-badc-0b7cad61f5a9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279462396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.3279462396
Directory /workspace/44.uart_intr/latest

Test location /workspace/coverage/default/44.uart_long_xfer_wo_dly.3201315712
Short name T977
Test name
Test status
Simulation time 34660598425 ps
CPU time 39.31 seconds
Started Jun 06 01:01:22 PM PDT 24
Finished Jun 06 01:02:03 PM PDT 24
Peak memory 200280 kb
Host smart-e6a64e01-6532-4694-8d96-b0cc9a9dcfce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3201315712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.3201315712
Directory /workspace/44.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/44.uart_loopback.3820779188
Short name T393
Test name
Test status
Simulation time 7709052713 ps
CPU time 22.98 seconds
Started Jun 06 01:01:23 PM PDT 24
Finished Jun 06 01:01:48 PM PDT 24
Peak memory 200248 kb
Host smart-4876e5e5-665a-4720-a67c-df91af139b6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820779188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_loopback.3820779188
Directory /workspace/44.uart_loopback/latest

Test location /workspace/coverage/default/44.uart_noise_filter.3203775650
Short name T503
Test name
Test status
Simulation time 57567835710 ps
CPU time 48.57 seconds
Started Jun 06 01:01:26 PM PDT 24
Finished Jun 06 01:02:16 PM PDT 24
Peak memory 200484 kb
Host smart-cf22ec07-f5d8-4ba6-a9a2-83d5a05119ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203775650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_noise_filter.3203775650
Directory /workspace/44.uart_noise_filter/latest

Test location /workspace/coverage/default/44.uart_perf.555179526
Short name T970
Test name
Test status
Simulation time 22727581116 ps
CPU time 162.31 seconds
Started Jun 06 01:01:25 PM PDT 24
Finished Jun 06 01:04:09 PM PDT 24
Peak memory 200356 kb
Host smart-d1db787c-5f16-4199-acf1-172b8c21479a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=555179526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.555179526
Directory /workspace/44.uart_perf/latest

Test location /workspace/coverage/default/44.uart_rx_oversample.1568850252
Short name T954
Test name
Test status
Simulation time 5039602140 ps
CPU time 3.2 seconds
Started Jun 06 01:01:22 PM PDT 24
Finished Jun 06 01:01:26 PM PDT 24
Peak memory 198512 kb
Host smart-6616341b-4b35-4a67-b2af-44aa25647052
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1568850252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.1568850252
Directory /workspace/44.uart_rx_oversample/latest

Test location /workspace/coverage/default/44.uart_rx_parity_err.1957246577
Short name T492
Test name
Test status
Simulation time 177278402416 ps
CPU time 454.41 seconds
Started Jun 06 01:01:26 PM PDT 24
Finished Jun 06 01:09:02 PM PDT 24
Peak memory 200292 kb
Host smart-17473bed-6177-419e-867a-68f82d552979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957246577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.1957246577
Directory /workspace/44.uart_rx_parity_err/latest

Test location /workspace/coverage/default/44.uart_rx_start_bit_filter.82325032
Short name T1101
Test name
Test status
Simulation time 37884181763 ps
CPU time 54.35 seconds
Started Jun 06 01:01:25 PM PDT 24
Finished Jun 06 01:02:21 PM PDT 24
Peak memory 196444 kb
Host smart-ed7dfcff-8907-44f1-bebc-55df18efac7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82325032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.82325032
Directory /workspace/44.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/44.uart_smoke.3101273911
Short name T553
Test name
Test status
Simulation time 5473463380 ps
CPU time 25.86 seconds
Started Jun 06 01:01:24 PM PDT 24
Finished Jun 06 01:01:51 PM PDT 24
Peak memory 199592 kb
Host smart-5ca9b799-35ba-4d4a-a536-8661f6f7f2cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101273911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_smoke.3101273911
Directory /workspace/44.uart_smoke/latest

Test location /workspace/coverage/default/44.uart_stress_all.2186881574
Short name T20
Test name
Test status
Simulation time 550008879256 ps
CPU time 250 seconds
Started Jun 06 01:01:24 PM PDT 24
Finished Jun 06 01:05:36 PM PDT 24
Peak memory 200284 kb
Host smart-e15b28df-b968-467c-9627-81092dfa560d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186881574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.2186881574
Directory /workspace/44.uart_stress_all/latest

Test location /workspace/coverage/default/44.uart_stress_all_with_rand_reset.880531090
Short name T534
Test name
Test status
Simulation time 23270064339 ps
CPU time 131.02 seconds
Started Jun 06 01:01:22 PM PDT 24
Finished Jun 06 01:03:35 PM PDT 24
Peak memory 208752 kb
Host smart-48b42fca-b902-4b4d-a22a-93ca604c20a2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880531090 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 44.uart_stress_all_with_rand_reset.880531090
Directory /workspace/44.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.uart_tx_ovrd.2566552632
Short name T306
Test name
Test status
Simulation time 1908875753 ps
CPU time 1.78 seconds
Started Jun 06 01:01:28 PM PDT 24
Finished Jun 06 01:01:30 PM PDT 24
Peak memory 198784 kb
Host smart-6c8bf472-a14f-4d33-80ac-041db94b6a57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566552632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.2566552632
Directory /workspace/44.uart_tx_ovrd/latest

Test location /workspace/coverage/default/44.uart_tx_rx.886603679
Short name T1154
Test name
Test status
Simulation time 28537800030 ps
CPU time 22.63 seconds
Started Jun 06 01:01:24 PM PDT 24
Finished Jun 06 01:01:48 PM PDT 24
Peak memory 200116 kb
Host smart-476f166d-d28b-4987-9790-604fb07a0bd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886603679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.886603679
Directory /workspace/44.uart_tx_rx/latest

Test location /workspace/coverage/default/45.uart_alert_test.617593080
Short name T331
Test name
Test status
Simulation time 20267947 ps
CPU time 0.56 seconds
Started Jun 06 01:01:31 PM PDT 24
Finished Jun 06 01:01:33 PM PDT 24
Peak memory 195716 kb
Host smart-49bc3b2f-6e10-4ad1-8a65-0b266da57bf9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617593080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.617593080
Directory /workspace/45.uart_alert_test/latest

Test location /workspace/coverage/default/45.uart_fifo_full.2523433668
Short name T592
Test name
Test status
Simulation time 88767354242 ps
CPU time 38.51 seconds
Started Jun 06 01:01:30 PM PDT 24
Finished Jun 06 01:02:10 PM PDT 24
Peak memory 200296 kb
Host smart-f97ac3ca-8d70-45bb-baff-adfd4c42b713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523433668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.2523433668
Directory /workspace/45.uart_fifo_full/latest

Test location /workspace/coverage/default/45.uart_fifo_overflow.887459779
Short name T972
Test name
Test status
Simulation time 45763678649 ps
CPU time 63.64 seconds
Started Jun 06 01:01:24 PM PDT 24
Finished Jun 06 01:02:29 PM PDT 24
Peak memory 200368 kb
Host smart-57a5f19a-0f9d-4243-b510-41cf731c3cd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887459779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.887459779
Directory /workspace/45.uart_fifo_overflow/latest

Test location /workspace/coverage/default/45.uart_fifo_reset.3299705366
Short name T591
Test name
Test status
Simulation time 235076152487 ps
CPU time 31.13 seconds
Started Jun 06 01:01:30 PM PDT 24
Finished Jun 06 01:02:03 PM PDT 24
Peak memory 200328 kb
Host smart-44ac14fe-066b-4643-9198-410b42c61e43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299705366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.3299705366
Directory /workspace/45.uart_fifo_reset/latest

Test location /workspace/coverage/default/45.uart_intr.4253665287
Short name T1043
Test name
Test status
Simulation time 22519773293 ps
CPU time 9.79 seconds
Started Jun 06 01:01:28 PM PDT 24
Finished Jun 06 01:01:39 PM PDT 24
Peak memory 199300 kb
Host smart-186e0aa2-a46a-4460-bbeb-47400aa8349d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253665287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.4253665287
Directory /workspace/45.uart_intr/latest

Test location /workspace/coverage/default/45.uart_loopback.2281793234
Short name T330
Test name
Test status
Simulation time 3767904535 ps
CPU time 2.86 seconds
Started Jun 06 01:01:28 PM PDT 24
Finished Jun 06 01:01:32 PM PDT 24
Peak memory 199448 kb
Host smart-42331da5-c828-4f87-9b24-f2107614302f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281793234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_loopback.2281793234
Directory /workspace/45.uart_loopback/latest

Test location /workspace/coverage/default/45.uart_noise_filter.3312326142
Short name T1058
Test name
Test status
Simulation time 19469378489 ps
CPU time 33.13 seconds
Started Jun 06 01:01:49 PM PDT 24
Finished Jun 06 01:02:24 PM PDT 24
Peak memory 200192 kb
Host smart-217de951-2ed8-48e6-aa70-f9e64c512e9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312326142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_noise_filter.3312326142
Directory /workspace/45.uart_noise_filter/latest

Test location /workspace/coverage/default/45.uart_perf.540794083
Short name T294
Test name
Test status
Simulation time 16552478518 ps
CPU time 839.66 seconds
Started Jun 06 01:01:33 PM PDT 24
Finished Jun 06 01:15:34 PM PDT 24
Peak memory 200076 kb
Host smart-7cc098e8-a705-4d71-a59a-7e00fffce0bc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=540794083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.540794083
Directory /workspace/45.uart_perf/latest

Test location /workspace/coverage/default/45.uart_rx_oversample.3890947356
Short name T687
Test name
Test status
Simulation time 2783445904 ps
CPU time 5.1 seconds
Started Jun 06 01:01:31 PM PDT 24
Finished Jun 06 01:01:37 PM PDT 24
Peak memory 198432 kb
Host smart-c8667438-cd95-4d7c-840f-832526a70725
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3890947356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.3890947356
Directory /workspace/45.uart_rx_oversample/latest

Test location /workspace/coverage/default/45.uart_rx_parity_err.1816341666
Short name T817
Test name
Test status
Simulation time 113982345147 ps
CPU time 179.97 seconds
Started Jun 06 01:01:30 PM PDT 24
Finished Jun 06 01:04:31 PM PDT 24
Peak memory 200312 kb
Host smart-3bdf8126-3ae2-45ce-8380-27b39b406b59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816341666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.1816341666
Directory /workspace/45.uart_rx_parity_err/latest

Test location /workspace/coverage/default/45.uart_rx_start_bit_filter.2999472729
Short name T711
Test name
Test status
Simulation time 1883955201 ps
CPU time 3.57 seconds
Started Jun 06 01:01:31 PM PDT 24
Finished Jun 06 01:01:36 PM PDT 24
Peak memory 195688 kb
Host smart-f8b361b3-5dd7-475c-9408-39faccd461c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999472729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.2999472729
Directory /workspace/45.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/45.uart_smoke.3356916705
Short name T808
Test name
Test status
Simulation time 5389797521 ps
CPU time 15.7 seconds
Started Jun 06 01:01:25 PM PDT 24
Finished Jun 06 01:01:43 PM PDT 24
Peak memory 200320 kb
Host smart-19d257e6-59e5-4be6-bb84-4ecc30a4e70d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356916705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_smoke.3356916705
Directory /workspace/45.uart_smoke/latest

Test location /workspace/coverage/default/45.uart_stress_all_with_rand_reset.1807483246
Short name T324
Test name
Test status
Simulation time 266293538166 ps
CPU time 827.68 seconds
Started Jun 06 01:01:35 PM PDT 24
Finished Jun 06 01:15:24 PM PDT 24
Peak memory 217148 kb
Host smart-51bafbad-7acb-4db2-86aa-a27f7dd874af
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807483246 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 45.uart_stress_all_with_rand_reset.1807483246
Directory /workspace/45.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.uart_tx_ovrd.1976097429
Short name T413
Test name
Test status
Simulation time 6820085033 ps
CPU time 36.26 seconds
Started Jun 06 01:01:31 PM PDT 24
Finished Jun 06 01:02:09 PM PDT 24
Peak memory 199708 kb
Host smart-ba2336a7-d09d-49af-905b-8cdf96dd40cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976097429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.1976097429
Directory /workspace/45.uart_tx_ovrd/latest

Test location /workspace/coverage/default/45.uart_tx_rx.96387479
Short name T873
Test name
Test status
Simulation time 6710171365 ps
CPU time 13.13 seconds
Started Jun 06 01:01:25 PM PDT 24
Finished Jun 06 01:01:39 PM PDT 24
Peak memory 200344 kb
Host smart-02d4cab1-0fab-4334-8e89-99946b398298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96387479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.96387479
Directory /workspace/45.uart_tx_rx/latest

Test location /workspace/coverage/default/46.uart_alert_test.2544636966
Short name T661
Test name
Test status
Simulation time 36948132 ps
CPU time 0.55 seconds
Started Jun 06 01:01:40 PM PDT 24
Finished Jun 06 01:01:42 PM PDT 24
Peak memory 195740 kb
Host smart-2cf4062c-9fcb-45fa-95ef-97d270c6ba91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544636966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.2544636966
Directory /workspace/46.uart_alert_test/latest

Test location /workspace/coverage/default/46.uart_fifo_full.1822705351
Short name T863
Test name
Test status
Simulation time 25636611266 ps
CPU time 38.37 seconds
Started Jun 06 01:01:36 PM PDT 24
Finished Jun 06 01:02:16 PM PDT 24
Peak memory 200324 kb
Host smart-1ad6249c-2d36-4d42-a92d-a7041d54309d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822705351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.1822705351
Directory /workspace/46.uart_fifo_full/latest

Test location /workspace/coverage/default/46.uart_fifo_overflow.1231209872
Short name T172
Test name
Test status
Simulation time 32836434058 ps
CPU time 13.51 seconds
Started Jun 06 01:01:31 PM PDT 24
Finished Jun 06 01:01:46 PM PDT 24
Peak memory 200056 kb
Host smart-7ebb58d1-203b-4e9b-96b6-2cab808ac8f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231209872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.1231209872
Directory /workspace/46.uart_fifo_overflow/latest

Test location /workspace/coverage/default/46.uart_fifo_reset.2776346404
Short name T234
Test name
Test status
Simulation time 73384502527 ps
CPU time 62.33 seconds
Started Jun 06 01:01:51 PM PDT 24
Finished Jun 06 01:02:54 PM PDT 24
Peak memory 200352 kb
Host smart-3a0acba2-1238-4ad7-b6b2-b89f3942a99b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776346404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.2776346404
Directory /workspace/46.uart_fifo_reset/latest

Test location /workspace/coverage/default/46.uart_intr.4074360342
Short name T1110
Test name
Test status
Simulation time 18182357270 ps
CPU time 17.52 seconds
Started Jun 06 01:01:31 PM PDT 24
Finished Jun 06 01:01:50 PM PDT 24
Peak memory 200376 kb
Host smart-b73af015-957e-4244-aef1-236bd432ff93
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074360342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.4074360342
Directory /workspace/46.uart_intr/latest

Test location /workspace/coverage/default/46.uart_long_xfer_wo_dly.3958926169
Short name T1187
Test name
Test status
Simulation time 99471155557 ps
CPU time 308.79 seconds
Started Jun 06 01:01:33 PM PDT 24
Finished Jun 06 01:06:43 PM PDT 24
Peak memory 200316 kb
Host smart-ff45da2d-bd67-4855-8beb-55ad601daf21
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3958926169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.3958926169
Directory /workspace/46.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/46.uart_loopback.1984754285
Short name T658
Test name
Test status
Simulation time 8090571713 ps
CPU time 4.29 seconds
Started Jun 06 01:01:32 PM PDT 24
Finished Jun 06 01:01:37 PM PDT 24
Peak memory 199036 kb
Host smart-3f6ce918-5d31-4e85-9c5c-98bd2545cd5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984754285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_loopback.1984754285
Directory /workspace/46.uart_loopback/latest

Test location /workspace/coverage/default/46.uart_noise_filter.3057566243
Short name T77
Test name
Test status
Simulation time 261920874949 ps
CPU time 77.76 seconds
Started Jun 06 01:01:33 PM PDT 24
Finished Jun 06 01:02:52 PM PDT 24
Peak memory 208332 kb
Host smart-2102cbb1-3516-4f02-b66f-c73fb2b74887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057566243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_noise_filter.3057566243
Directory /workspace/46.uart_noise_filter/latest

Test location /workspace/coverage/default/46.uart_perf.3332579847
Short name T566
Test name
Test status
Simulation time 7229312967 ps
CPU time 379.31 seconds
Started Jun 06 01:01:33 PM PDT 24
Finished Jun 06 01:07:54 PM PDT 24
Peak memory 200236 kb
Host smart-00601030-841e-4b9f-8f6c-c2e6f97ffb38
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3332579847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.3332579847
Directory /workspace/46.uart_perf/latest

Test location /workspace/coverage/default/46.uart_rx_oversample.3999578194
Short name T428
Test name
Test status
Simulation time 6909626902 ps
CPU time 30.95 seconds
Started Jun 06 01:01:30 PM PDT 24
Finished Jun 06 01:02:03 PM PDT 24
Peak memory 199112 kb
Host smart-f95cf3ee-f087-423c-ac15-47bc6eaf827f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3999578194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.3999578194
Directory /workspace/46.uart_rx_oversample/latest

Test location /workspace/coverage/default/46.uart_rx_parity_err.2808862293
Short name T565
Test name
Test status
Simulation time 90949258552 ps
CPU time 36.69 seconds
Started Jun 06 01:01:33 PM PDT 24
Finished Jun 06 01:02:10 PM PDT 24
Peak memory 199992 kb
Host smart-4745a58e-0854-4a14-888f-4e98cf7d4b45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808862293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.2808862293
Directory /workspace/46.uart_rx_parity_err/latest

Test location /workspace/coverage/default/46.uart_rx_start_bit_filter.2888221803
Short name T438
Test name
Test status
Simulation time 6103862309 ps
CPU time 5.31 seconds
Started Jun 06 01:01:36 PM PDT 24
Finished Jun 06 01:01:43 PM PDT 24
Peak memory 196604 kb
Host smart-23fb1504-87c6-4a79-9149-d12764ccd1a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888221803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.2888221803
Directory /workspace/46.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/46.uart_smoke.2167564210
Short name T898
Test name
Test status
Simulation time 694764370 ps
CPU time 2.41 seconds
Started Jun 06 01:01:29 PM PDT 24
Finished Jun 06 01:01:33 PM PDT 24
Peak memory 198624 kb
Host smart-4fd10179-4d2c-4c51-8c31-73d29811f9c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167564210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_smoke.2167564210
Directory /workspace/46.uart_smoke/latest

Test location /workspace/coverage/default/46.uart_stress_all.4063790450
Short name T597
Test name
Test status
Simulation time 34454622974 ps
CPU time 59.59 seconds
Started Jun 06 01:01:31 PM PDT 24
Finished Jun 06 01:02:32 PM PDT 24
Peak memory 200344 kb
Host smart-ffb22cae-f44b-4fd9-8131-294ee39015d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063790450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.4063790450
Directory /workspace/46.uart_stress_all/latest

Test location /workspace/coverage/default/46.uart_stress_all_with_rand_reset.1887432727
Short name T703
Test name
Test status
Simulation time 32726689785 ps
CPU time 196.44 seconds
Started Jun 06 01:01:40 PM PDT 24
Finished Jun 06 01:04:57 PM PDT 24
Peak memory 217112 kb
Host smart-225a731d-bea7-406b-9f6f-0bcc011690c3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887432727 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 46.uart_stress_all_with_rand_reset.1887432727
Directory /workspace/46.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.uart_tx_ovrd.4290147531
Short name T335
Test name
Test status
Simulation time 390701003 ps
CPU time 1.54 seconds
Started Jun 06 01:01:36 PM PDT 24
Finished Jun 06 01:01:39 PM PDT 24
Peak memory 198552 kb
Host smart-8dd7c175-7e20-44fc-8e67-883431c81b72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290147531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.4290147531
Directory /workspace/46.uart_tx_ovrd/latest

Test location /workspace/coverage/default/46.uart_tx_rx.69402272
Short name T670
Test name
Test status
Simulation time 59463943582 ps
CPU time 27.16 seconds
Started Jun 06 01:01:32 PM PDT 24
Finished Jun 06 01:02:00 PM PDT 24
Peak memory 200328 kb
Host smart-735523e8-e240-4751-ab3f-29e6d9ce8be2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69402272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.69402272
Directory /workspace/46.uart_tx_rx/latest

Test location /workspace/coverage/default/47.uart_alert_test.1086253791
Short name T479
Test name
Test status
Simulation time 32645504 ps
CPU time 0.53 seconds
Started Jun 06 01:01:42 PM PDT 24
Finished Jun 06 01:01:44 PM PDT 24
Peak memory 196020 kb
Host smart-ef1b5c8c-dcf3-495b-b984-530f54d19549
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086253791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.1086253791
Directory /workspace/47.uart_alert_test/latest

Test location /workspace/coverage/default/47.uart_fifo_full.630391778
Short name T1061
Test name
Test status
Simulation time 218943732209 ps
CPU time 83.79 seconds
Started Jun 06 01:01:43 PM PDT 24
Finished Jun 06 01:03:07 PM PDT 24
Peak memory 200384 kb
Host smart-f8a8a8d1-bd7e-40a7-99fb-03d4d07ee78d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630391778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.630391778
Directory /workspace/47.uart_fifo_full/latest

Test location /workspace/coverage/default/47.uart_fifo_overflow.1641855685
Short name T890
Test name
Test status
Simulation time 181614957102 ps
CPU time 500.9 seconds
Started Jun 06 01:01:45 PM PDT 24
Finished Jun 06 01:10:07 PM PDT 24
Peak memory 200276 kb
Host smart-1806bf3d-4375-4a4d-beff-f8e9f64308f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641855685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.1641855685
Directory /workspace/47.uart_fifo_overflow/latest

Test location /workspace/coverage/default/47.uart_fifo_reset.2988007180
Short name T856
Test name
Test status
Simulation time 25113901683 ps
CPU time 54.61 seconds
Started Jun 06 01:01:40 PM PDT 24
Finished Jun 06 01:02:35 PM PDT 24
Peak memory 200264 kb
Host smart-9d4b972f-bc22-4ae8-89f2-677741b0a6b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988007180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.2988007180
Directory /workspace/47.uart_fifo_reset/latest

Test location /workspace/coverage/default/47.uart_intr.3556354383
Short name T598
Test name
Test status
Simulation time 138308913151 ps
CPU time 54.57 seconds
Started Jun 06 01:01:40 PM PDT 24
Finished Jun 06 01:02:36 PM PDT 24
Peak memory 198092 kb
Host smart-6cb54548-6ca7-4ed7-bfe3-5833eb4b005c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556354383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.3556354383
Directory /workspace/47.uart_intr/latest

Test location /workspace/coverage/default/47.uart_long_xfer_wo_dly.2162433677
Short name T855
Test name
Test status
Simulation time 60919008912 ps
CPU time 71.86 seconds
Started Jun 06 01:01:46 PM PDT 24
Finished Jun 06 01:02:59 PM PDT 24
Peak memory 200356 kb
Host smart-74405329-e84a-4e03-aa93-19341986fbd1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2162433677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.2162433677
Directory /workspace/47.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/47.uart_loopback.3888533630
Short name T421
Test name
Test status
Simulation time 6051021666 ps
CPU time 6.02 seconds
Started Jun 06 01:01:40 PM PDT 24
Finished Jun 06 01:01:47 PM PDT 24
Peak memory 199172 kb
Host smart-eba3b9b7-fc33-4a1b-b8ce-1d783fd325d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888533630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_loopback.3888533630
Directory /workspace/47.uart_loopback/latest

Test location /workspace/coverage/default/47.uart_noise_filter.2149244474
Short name T424
Test name
Test status
Simulation time 35006522124 ps
CPU time 13 seconds
Started Jun 06 01:01:42 PM PDT 24
Finished Jun 06 01:01:56 PM PDT 24
Peak memory 200576 kb
Host smart-42a91e29-74cd-4268-b0d7-91d083ef1a92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149244474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_noise_filter.2149244474
Directory /workspace/47.uart_noise_filter/latest

Test location /workspace/coverage/default/47.uart_perf.1201430906
Short name T307
Test name
Test status
Simulation time 18187928830 ps
CPU time 126.12 seconds
Started Jun 06 01:01:39 PM PDT 24
Finished Jun 06 01:03:46 PM PDT 24
Peak memory 200304 kb
Host smart-1d7fc3ee-9e3f-425e-8ed2-a97d5c4c8b93
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1201430906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.1201430906
Directory /workspace/47.uart_perf/latest

Test location /workspace/coverage/default/47.uart_rx_oversample.872564843
Short name T574
Test name
Test status
Simulation time 6292927902 ps
CPU time 51.74 seconds
Started Jun 06 01:01:53 PM PDT 24
Finished Jun 06 01:02:46 PM PDT 24
Peak memory 199168 kb
Host smart-15f830fa-7610-4d67-9017-73a54cdc16bf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=872564843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.872564843
Directory /workspace/47.uart_rx_oversample/latest

Test location /workspace/coverage/default/47.uart_rx_parity_err.4025232687
Short name T142
Test name
Test status
Simulation time 110291451439 ps
CPU time 411.22 seconds
Started Jun 06 01:01:40 PM PDT 24
Finished Jun 06 01:08:32 PM PDT 24
Peak memory 200292 kb
Host smart-9ec9f4be-6774-444e-a329-65d60b3e8dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025232687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.4025232687
Directory /workspace/47.uart_rx_parity_err/latest

Test location /workspace/coverage/default/47.uart_rx_start_bit_filter.3056366982
Short name T542
Test name
Test status
Simulation time 1482675724 ps
CPU time 1.26 seconds
Started Jun 06 01:01:41 PM PDT 24
Finished Jun 06 01:01:43 PM PDT 24
Peak memory 195688 kb
Host smart-de9ee7d5-dbe8-4212-806d-86db4668c171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056366982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.3056366982
Directory /workspace/47.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/47.uart_smoke.548990919
Short name T971
Test name
Test status
Simulation time 474440853 ps
CPU time 1.5 seconds
Started Jun 06 01:01:42 PM PDT 24
Finished Jun 06 01:01:44 PM PDT 24
Peak memory 198872 kb
Host smart-76d2a906-8112-47ad-ae5f-57d234e03d79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548990919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_smoke.548990919
Directory /workspace/47.uart_smoke/latest

Test location /workspace/coverage/default/47.uart_stress_all.1841375822
Short name T636
Test name
Test status
Simulation time 43746386179 ps
CPU time 81.04 seconds
Started Jun 06 01:01:41 PM PDT 24
Finished Jun 06 01:03:03 PM PDT 24
Peak memory 200328 kb
Host smart-499a9925-ad0a-4b1a-97e7-4603a34d4034
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841375822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.1841375822
Directory /workspace/47.uart_stress_all/latest

Test location /workspace/coverage/default/47.uart_stress_all_with_rand_reset.3137700540
Short name T948
Test name
Test status
Simulation time 145351529145 ps
CPU time 636.8 seconds
Started Jun 06 01:01:41 PM PDT 24
Finished Jun 06 01:12:19 PM PDT 24
Peak memory 216968 kb
Host smart-aeea5e8a-e23d-445d-bc9e-f1058919d3ce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137700540 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 47.uart_stress_all_with_rand_reset.3137700540
Directory /workspace/47.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.uart_tx_ovrd.2091977551
Short name T360
Test name
Test status
Simulation time 7491154805 ps
CPU time 19.98 seconds
Started Jun 06 01:01:38 PM PDT 24
Finished Jun 06 01:01:59 PM PDT 24
Peak memory 200288 kb
Host smart-9d131aca-56ac-4764-8ef8-37da4d83f1f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091977551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.2091977551
Directory /workspace/47.uart_tx_ovrd/latest

Test location /workspace/coverage/default/47.uart_tx_rx.858755356
Short name T434
Test name
Test status
Simulation time 100266008533 ps
CPU time 43.82 seconds
Started Jun 06 01:01:41 PM PDT 24
Finished Jun 06 01:02:26 PM PDT 24
Peak memory 200236 kb
Host smart-28f45237-0a30-4148-b823-65b6e1c587c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858755356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.858755356
Directory /workspace/47.uart_tx_rx/latest

Test location /workspace/coverage/default/48.uart_alert_test.978004343
Short name T960
Test name
Test status
Simulation time 33347816 ps
CPU time 0.54 seconds
Started Jun 06 01:01:52 PM PDT 24
Finished Jun 06 01:01:54 PM PDT 24
Peak memory 194600 kb
Host smart-b0361cb3-944f-404a-bb86-b09b97a69e35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978004343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.978004343
Directory /workspace/48.uart_alert_test/latest

Test location /workspace/coverage/default/48.uart_fifo_full.4126287698
Short name T147
Test name
Test status
Simulation time 73603660662 ps
CPU time 52.84 seconds
Started Jun 06 01:01:42 PM PDT 24
Finished Jun 06 01:02:36 PM PDT 24
Peak memory 200320 kb
Host smart-9a6ba797-6723-4930-8494-0ca298835d18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126287698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.4126287698
Directory /workspace/48.uart_fifo_full/latest

Test location /workspace/coverage/default/48.uart_fifo_overflow.3034348034
Short name T1056
Test name
Test status
Simulation time 24264586856 ps
CPU time 51.31 seconds
Started Jun 06 01:01:40 PM PDT 24
Finished Jun 06 01:02:32 PM PDT 24
Peak memory 200376 kb
Host smart-8db951bd-7660-4102-bc3d-519fdfb03cd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034348034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.3034348034
Directory /workspace/48.uart_fifo_overflow/latest

Test location /workspace/coverage/default/48.uart_fifo_reset.1566452183
Short name T554
Test name
Test status
Simulation time 327815557251 ps
CPU time 26.56 seconds
Started Jun 06 01:01:41 PM PDT 24
Finished Jun 06 01:02:09 PM PDT 24
Peak memory 200368 kb
Host smart-24411ed2-b2d9-4b4f-b5be-710d4bd52b77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566452183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.1566452183
Directory /workspace/48.uart_fifo_reset/latest

Test location /workspace/coverage/default/48.uart_intr.1613000357
Short name T1005
Test name
Test status
Simulation time 47948002315 ps
CPU time 86.79 seconds
Started Jun 06 01:01:39 PM PDT 24
Finished Jun 06 01:03:07 PM PDT 24
Peak memory 200096 kb
Host smart-8f916569-493e-42d4-bf48-9fd5b77bbccd
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613000357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.1613000357
Directory /workspace/48.uart_intr/latest

Test location /workspace/coverage/default/48.uart_loopback.1571823816
Short name T22
Test name
Test status
Simulation time 6079216049 ps
CPU time 11.69 seconds
Started Jun 06 01:01:50 PM PDT 24
Finished Jun 06 01:02:03 PM PDT 24
Peak memory 198160 kb
Host smart-b15b11b8-ba00-4498-85f4-0d9642a18206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571823816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_loopback.1571823816
Directory /workspace/48.uart_loopback/latest

Test location /workspace/coverage/default/48.uart_noise_filter.3721273245
Short name T994
Test name
Test status
Simulation time 202685675796 ps
CPU time 127 seconds
Started Jun 06 01:01:42 PM PDT 24
Finished Jun 06 01:03:50 PM PDT 24
Peak memory 200548 kb
Host smart-54f127ed-1852-4379-bb44-7e4e683987ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721273245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_noise_filter.3721273245
Directory /workspace/48.uart_noise_filter/latest

Test location /workspace/coverage/default/48.uart_perf.3596202647
Short name T984
Test name
Test status
Simulation time 19470317283 ps
CPU time 1149.24 seconds
Started Jun 06 01:01:50 PM PDT 24
Finished Jun 06 01:21:00 PM PDT 24
Peak memory 200260 kb
Host smart-4af7476c-f05a-4855-b90e-4dc00a7c9794
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3596202647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.3596202647
Directory /workspace/48.uart_perf/latest

Test location /workspace/coverage/default/48.uart_rx_oversample.2990080163
Short name T737
Test name
Test status
Simulation time 7419334150 ps
CPU time 3.96 seconds
Started Jun 06 01:01:41 PM PDT 24
Finished Jun 06 01:01:46 PM PDT 24
Peak memory 199532 kb
Host smart-318591a2-7b5c-4d1e-8cdf-a734e35df8ac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2990080163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.2990080163
Directory /workspace/48.uart_rx_oversample/latest

Test location /workspace/coverage/default/48.uart_rx_parity_err.2330287040
Short name T809
Test name
Test status
Simulation time 33374929707 ps
CPU time 14.25 seconds
Started Jun 06 01:01:51 PM PDT 24
Finished Jun 06 01:02:06 PM PDT 24
Peak memory 200076 kb
Host smart-9c3b388a-6206-4874-a7ed-0694005d31ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330287040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.2330287040
Directory /workspace/48.uart_rx_parity_err/latest

Test location /workspace/coverage/default/48.uart_rx_start_bit_filter.2568949340
Short name T1102
Test name
Test status
Simulation time 4325259335 ps
CPU time 6.89 seconds
Started Jun 06 01:01:39 PM PDT 24
Finished Jun 06 01:01:47 PM PDT 24
Peak memory 196644 kb
Host smart-3b3a7335-8885-4df6-aa4d-638d32d7ce7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568949340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.2568949340
Directory /workspace/48.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/48.uart_smoke.1266481990
Short name T549
Test name
Test status
Simulation time 6210259580 ps
CPU time 12.45 seconds
Started Jun 06 01:01:38 PM PDT 24
Finished Jun 06 01:01:51 PM PDT 24
Peak memory 199720 kb
Host smart-d96d495b-6c7a-4073-ad1f-789ddc6f10f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266481990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_smoke.1266481990
Directory /workspace/48.uart_smoke/latest

Test location /workspace/coverage/default/48.uart_stress_all.2832488693
Short name T766
Test name
Test status
Simulation time 124641645933 ps
CPU time 111.91 seconds
Started Jun 06 01:01:48 PM PDT 24
Finished Jun 06 01:03:41 PM PDT 24
Peak memory 208732 kb
Host smart-c1281ea6-8999-46b9-9074-ee28104d3200
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832488693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.2832488693
Directory /workspace/48.uart_stress_all/latest

Test location /workspace/coverage/default/48.uart_stress_all_with_rand_reset.1410977806
Short name T321
Test name
Test status
Simulation time 46140658189 ps
CPU time 130.11 seconds
Started Jun 06 01:01:52 PM PDT 24
Finished Jun 06 01:04:03 PM PDT 24
Peak memory 215992 kb
Host smart-457f11aa-26a6-46e3-ba11-b7d568678c6b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410977806 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 48.uart_stress_all_with_rand_reset.1410977806
Directory /workspace/48.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.uart_tx_ovrd.134563765
Short name T516
Test name
Test status
Simulation time 1140865942 ps
CPU time 3.09 seconds
Started Jun 06 01:01:52 PM PDT 24
Finished Jun 06 01:01:56 PM PDT 24
Peak memory 198748 kb
Host smart-26fb99e3-f36f-4f76-a630-f2bdb1d4c16e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134563765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.134563765
Directory /workspace/48.uart_tx_ovrd/latest

Test location /workspace/coverage/default/48.uart_tx_rx.2604407666
Short name T278
Test name
Test status
Simulation time 38992403081 ps
CPU time 112.51 seconds
Started Jun 06 01:01:46 PM PDT 24
Finished Jun 06 01:03:40 PM PDT 24
Peak memory 200348 kb
Host smart-3455e28c-3614-443d-b47c-b306e5b7c5c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604407666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.2604407666
Directory /workspace/48.uart_tx_rx/latest

Test location /workspace/coverage/default/49.uart_alert_test.2203644973
Short name T484
Test name
Test status
Simulation time 11699794 ps
CPU time 0.56 seconds
Started Jun 06 01:01:59 PM PDT 24
Finished Jun 06 01:02:01 PM PDT 24
Peak memory 195936 kb
Host smart-9bbe018d-9803-4cc1-be3f-1bf84eb94c11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203644973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.2203644973
Directory /workspace/49.uart_alert_test/latest

Test location /workspace/coverage/default/49.uart_fifo_full.248426779
Short name T603
Test name
Test status
Simulation time 61468040679 ps
CPU time 27.32 seconds
Started Jun 06 01:01:48 PM PDT 24
Finished Jun 06 01:02:17 PM PDT 24
Peak memory 200356 kb
Host smart-2ba1f5f1-19a2-4108-a8bc-38eb14f47d27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248426779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.248426779
Directory /workspace/49.uart_fifo_full/latest

Test location /workspace/coverage/default/49.uart_fifo_overflow.3774348687
Short name T1156
Test name
Test status
Simulation time 120195932611 ps
CPU time 93.78 seconds
Started Jun 06 01:01:58 PM PDT 24
Finished Jun 06 01:03:32 PM PDT 24
Peak memory 200388 kb
Host smart-bda1ebcf-37e6-41cf-81e9-7e0216439e5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774348687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.3774348687
Directory /workspace/49.uart_fifo_overflow/latest

Test location /workspace/coverage/default/49.uart_fifo_reset.192328456
Short name T577
Test name
Test status
Simulation time 64697704635 ps
CPU time 36.66 seconds
Started Jun 06 01:01:49 PM PDT 24
Finished Jun 06 01:02:27 PM PDT 24
Peak memory 200348 kb
Host smart-63e24be3-c7fc-4fce-a034-3d50911e88c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192328456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.192328456
Directory /workspace/49.uart_fifo_reset/latest

Test location /workspace/coverage/default/49.uart_intr.3990845631
Short name T851
Test name
Test status
Simulation time 12106180943 ps
CPU time 21.27 seconds
Started Jun 06 01:01:49 PM PDT 24
Finished Jun 06 01:02:12 PM PDT 24
Peak memory 200208 kb
Host smart-d0515e06-baa2-48ee-9318-f5420dc68320
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990845631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.3990845631
Directory /workspace/49.uart_intr/latest

Test location /workspace/coverage/default/49.uart_long_xfer_wo_dly.482499679
Short name T391
Test name
Test status
Simulation time 61271865076 ps
CPU time 225.06 seconds
Started Jun 06 01:01:49 PM PDT 24
Finished Jun 06 01:05:36 PM PDT 24
Peak memory 200404 kb
Host smart-79cced70-4ae1-4fee-89cd-68b0c0c47e7a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=482499679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.482499679
Directory /workspace/49.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/49.uart_loopback.4280543919
Short name T868
Test name
Test status
Simulation time 2264761083 ps
CPU time 2.75 seconds
Started Jun 06 01:01:52 PM PDT 24
Finished Jun 06 01:01:56 PM PDT 24
Peak memory 199248 kb
Host smart-30b4e7d2-63fa-46bd-a90f-35d00616eaaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280543919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_loopback.4280543919
Directory /workspace/49.uart_loopback/latest

Test location /workspace/coverage/default/49.uart_noise_filter.3708682660
Short name T295
Test name
Test status
Simulation time 201005690933 ps
CPU time 87.81 seconds
Started Jun 06 01:01:55 PM PDT 24
Finished Jun 06 01:03:23 PM PDT 24
Peak memory 216112 kb
Host smart-772828a4-6a93-4a60-a70c-f4f8379391cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708682660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_noise_filter.3708682660
Directory /workspace/49.uart_noise_filter/latest

Test location /workspace/coverage/default/49.uart_perf.3364545111
Short name T1017
Test name
Test status
Simulation time 20172454487 ps
CPU time 1045.47 seconds
Started Jun 06 01:01:52 PM PDT 24
Finished Jun 06 01:19:18 PM PDT 24
Peak memory 200388 kb
Host smart-8665e7d1-99b6-4a41-a67a-b4b8647fbfbb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3364545111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.3364545111
Directory /workspace/49.uart_perf/latest

Test location /workspace/coverage/default/49.uart_rx_oversample.954831654
Short name T976
Test name
Test status
Simulation time 7318894501 ps
CPU time 62.82 seconds
Started Jun 06 01:01:52 PM PDT 24
Finished Jun 06 01:02:56 PM PDT 24
Peak memory 199260 kb
Host smart-55910255-2ab9-4104-873f-29ec08c4b243
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=954831654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.954831654
Directory /workspace/49.uart_rx_oversample/latest

Test location /workspace/coverage/default/49.uart_rx_parity_err.3090970673
Short name T296
Test name
Test status
Simulation time 123679818104 ps
CPU time 214.01 seconds
Started Jun 06 01:01:51 PM PDT 24
Finished Jun 06 01:05:26 PM PDT 24
Peak memory 200380 kb
Host smart-a5e0c8e6-f425-4b8a-91d5-d90d60d57fe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090970673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.3090970673
Directory /workspace/49.uart_rx_parity_err/latest

Test location /workspace/coverage/default/49.uart_rx_start_bit_filter.1237564380
Short name T530
Test name
Test status
Simulation time 4882327836 ps
CPU time 1.68 seconds
Started Jun 06 01:01:50 PM PDT 24
Finished Jun 06 01:01:53 PM PDT 24
Peak memory 196556 kb
Host smart-9462aee7-8eb7-4ec7-9653-072b943cad94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237564380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.1237564380
Directory /workspace/49.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/49.uart_smoke.3697192568
Short name T350
Test name
Test status
Simulation time 842151178 ps
CPU time 0.93 seconds
Started Jun 06 01:01:56 PM PDT 24
Finished Jun 06 01:01:57 PM PDT 24
Peak memory 199004 kb
Host smart-f5c31980-f66b-423a-a725-bcb50d32eaf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697192568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_smoke.3697192568
Directory /workspace/49.uart_smoke/latest

Test location /workspace/coverage/default/49.uart_stress_all.2403514003
Short name T412
Test name
Test status
Simulation time 83811817720 ps
CPU time 65.01 seconds
Started Jun 06 01:01:59 PM PDT 24
Finished Jun 06 01:03:05 PM PDT 24
Peak memory 200756 kb
Host smart-9755c636-5a62-4b9f-8b22-ae75cc026262
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403514003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.2403514003
Directory /workspace/49.uart_stress_all/latest

Test location /workspace/coverage/default/49.uart_stress_all_with_rand_reset.1795791197
Short name T738
Test name
Test status
Simulation time 60163242902 ps
CPU time 401.16 seconds
Started Jun 06 01:02:03 PM PDT 24
Finished Jun 06 01:08:45 PM PDT 24
Peak memory 215612 kb
Host smart-cd119a8f-729f-413e-8ecd-ab9bfeabd59b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795791197 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 49.uart_stress_all_with_rand_reset.1795791197
Directory /workspace/49.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.uart_tx_ovrd.3877077317
Short name T1006
Test name
Test status
Simulation time 900485897 ps
CPU time 2.86 seconds
Started Jun 06 01:01:51 PM PDT 24
Finished Jun 06 01:01:55 PM PDT 24
Peak memory 198664 kb
Host smart-52034481-adf2-4c2d-af3b-fd797b967baf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877077317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.3877077317
Directory /workspace/49.uart_tx_ovrd/latest

Test location /workspace/coverage/default/49.uart_tx_rx.2551210036
Short name T1122
Test name
Test status
Simulation time 120873167163 ps
CPU time 122.89 seconds
Started Jun 06 01:01:49 PM PDT 24
Finished Jun 06 01:03:53 PM PDT 24
Peak memory 200356 kb
Host smart-e8b41fe9-62b9-41e4-b6af-5f4c6f56e785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551210036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.2551210036
Directory /workspace/49.uart_tx_rx/latest

Test location /workspace/coverage/default/5.uart_alert_test.633385150
Short name T895
Test name
Test status
Simulation time 15262123 ps
CPU time 0.54 seconds
Started Jun 06 12:58:16 PM PDT 24
Finished Jun 06 12:58:18 PM PDT 24
Peak memory 195136 kb
Host smart-9747d0b5-42c0-43cf-98e6-42b537ab9a5c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633385150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.633385150
Directory /workspace/5.uart_alert_test/latest

Test location /workspace/coverage/default/5.uart_fifo_overflow.374803091
Short name T1129
Test name
Test status
Simulation time 16080316159 ps
CPU time 25.56 seconds
Started Jun 06 12:58:13 PM PDT 24
Finished Jun 06 12:58:40 PM PDT 24
Peak memory 200268 kb
Host smart-cc32b356-6d09-4c9b-b6e8-232cd63a34fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374803091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.374803091
Directory /workspace/5.uart_fifo_overflow/latest

Test location /workspace/coverage/default/5.uart_fifo_reset.3439774940
Short name T656
Test name
Test status
Simulation time 24372118896 ps
CPU time 17.37 seconds
Started Jun 06 12:58:13 PM PDT 24
Finished Jun 06 12:58:31 PM PDT 24
Peak memory 200288 kb
Host smart-74a45cc1-9d35-4179-ab8a-165a3baed86f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439774940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.3439774940
Directory /workspace/5.uart_fifo_reset/latest

Test location /workspace/coverage/default/5.uart_intr.2721683438
Short name T608
Test name
Test status
Simulation time 18471974132 ps
CPU time 18.4 seconds
Started Jun 06 12:58:16 PM PDT 24
Finished Jun 06 12:58:37 PM PDT 24
Peak memory 200340 kb
Host smart-97588489-5bc1-46af-81da-ef99dd1bbfac
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721683438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.2721683438
Directory /workspace/5.uart_intr/latest

Test location /workspace/coverage/default/5.uart_long_xfer_wo_dly.176000505
Short name T271
Test name
Test status
Simulation time 48088896183 ps
CPU time 357.61 seconds
Started Jun 06 12:58:14 PM PDT 24
Finished Jun 06 01:04:13 PM PDT 24
Peak memory 200208 kb
Host smart-9b03d235-607f-490a-9584-62a09f90d92a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=176000505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.176000505
Directory /workspace/5.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/5.uart_loopback.2362384648
Short name T783
Test name
Test status
Simulation time 11158829229 ps
CPU time 9.06 seconds
Started Jun 06 12:58:14 PM PDT 24
Finished Jun 06 12:58:24 PM PDT 24
Peak memory 200120 kb
Host smart-1095f3f8-0351-4c21-ab87-ecaf74915a03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362384648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_loopback.2362384648
Directory /workspace/5.uart_loopback/latest

Test location /workspace/coverage/default/5.uart_noise_filter.2839880863
Short name T79
Test name
Test status
Simulation time 197196588608 ps
CPU time 14.7 seconds
Started Jun 06 12:58:14 PM PDT 24
Finished Jun 06 12:58:30 PM PDT 24
Peak memory 197284 kb
Host smart-a0aca55e-c054-42aa-8b5f-ede43ae1ee69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839880863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_noise_filter.2839880863
Directory /workspace/5.uart_noise_filter/latest

Test location /workspace/coverage/default/5.uart_rx_oversample.340283428
Short name T721
Test name
Test status
Simulation time 2560940828 ps
CPU time 4.43 seconds
Started Jun 06 12:58:18 PM PDT 24
Finished Jun 06 12:58:24 PM PDT 24
Peak memory 199324 kb
Host smart-adb9bc79-df43-456d-b8be-59004ccb6444
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=340283428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.340283428
Directory /workspace/5.uart_rx_oversample/latest

Test location /workspace/coverage/default/5.uart_rx_parity_err.3451554305
Short name T918
Test name
Test status
Simulation time 59533646496 ps
CPU time 26.51 seconds
Started Jun 06 12:58:23 PM PDT 24
Finished Jun 06 12:58:50 PM PDT 24
Peak memory 200128 kb
Host smart-2d53fab8-8cbd-4812-b22f-85bdffe245b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451554305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.3451554305
Directory /workspace/5.uart_rx_parity_err/latest

Test location /workspace/coverage/default/5.uart_rx_start_bit_filter.192946424
Short name T1036
Test name
Test status
Simulation time 6635477482 ps
CPU time 6.41 seconds
Started Jun 06 12:58:12 PM PDT 24
Finished Jun 06 12:58:19 PM PDT 24
Peak memory 196440 kb
Host smart-b69fcc16-ecc3-4293-8c4a-572d02060dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192946424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.192946424
Directory /workspace/5.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/5.uart_smoke.2188663389
Short name T502
Test name
Test status
Simulation time 991604025 ps
CPU time 1.27 seconds
Started Jun 06 12:58:01 PM PDT 24
Finished Jun 06 12:58:04 PM PDT 24
Peak memory 198960 kb
Host smart-88d8c02f-ad91-4f85-96b2-5aebaf0417b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188663389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_smoke.2188663389
Directory /workspace/5.uart_smoke/latest

Test location /workspace/coverage/default/5.uart_stress_all.3725608762
Short name T905
Test name
Test status
Simulation time 372808188464 ps
CPU time 784.67 seconds
Started Jun 06 12:58:11 PM PDT 24
Finished Jun 06 01:11:17 PM PDT 24
Peak memory 200352 kb
Host smart-37acf286-2059-4e9d-a0cc-40a13e001e33
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725608762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.3725608762
Directory /workspace/5.uart_stress_all/latest

Test location /workspace/coverage/default/5.uart_stress_all_with_rand_reset.916633852
Short name T931
Test name
Test status
Simulation time 344832492197 ps
CPU time 1073.86 seconds
Started Jun 06 12:58:14 PM PDT 24
Finished Jun 06 01:16:09 PM PDT 24
Peak memory 216824 kb
Host smart-85d97782-f339-4447-ad08-ca6795b6f525
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916633852 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 5.uart_stress_all_with_rand_reset.916633852
Directory /workspace/5.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.uart_tx_ovrd.3151039189
Short name T310
Test name
Test status
Simulation time 831316592 ps
CPU time 2.97 seconds
Started Jun 06 12:58:13 PM PDT 24
Finished Jun 06 12:58:17 PM PDT 24
Peak memory 198604 kb
Host smart-4eabb9dc-68ec-45c9-8ee9-0a44ceb5d11c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151039189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.3151039189
Directory /workspace/5.uart_tx_ovrd/latest

Test location /workspace/coverage/default/5.uart_tx_rx.1364716304
Short name T1078
Test name
Test status
Simulation time 8571136937 ps
CPU time 12.27 seconds
Started Jun 06 12:58:05 PM PDT 24
Finished Jun 06 12:58:18 PM PDT 24
Peak memory 199808 kb
Host smart-4c7a85f3-5d5c-4ef9-a554-296c16803915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364716304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.1364716304
Directory /workspace/5.uart_tx_rx/latest

Test location /workspace/coverage/default/50.uart_fifo_reset.245116000
Short name T361
Test name
Test status
Simulation time 122472365416 ps
CPU time 197.98 seconds
Started Jun 06 01:02:00 PM PDT 24
Finished Jun 06 01:05:19 PM PDT 24
Peak memory 200352 kb
Host smart-41a64379-eb0f-403d-a35e-bbc88938f03c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245116000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.245116000
Directory /workspace/50.uart_fifo_reset/latest

Test location /workspace/coverage/default/50.uart_stress_all_with_rand_reset.83048071
Short name T1103
Test name
Test status
Simulation time 71665350252 ps
CPU time 961.12 seconds
Started Jun 06 01:02:00 PM PDT 24
Finished Jun 06 01:18:03 PM PDT 24
Peak memory 226676 kb
Host smart-7ab06708-0f2e-49b5-a2ca-072ca2ae553e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83048071 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 50.uart_stress_all_with_rand_reset.83048071
Directory /workspace/50.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/51.uart_stress_all_with_rand_reset.1998095834
Short name T1127
Test name
Test status
Simulation time 214681889286 ps
CPU time 328.71 seconds
Started Jun 06 01:02:00 PM PDT 24
Finished Jun 06 01:07:31 PM PDT 24
Peak memory 216888 kb
Host smart-d639b0e2-0122-4a52-abaa-db97baf77b0c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998095834 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 51.uart_stress_all_with_rand_reset.1998095834
Directory /workspace/51.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.uart_fifo_reset.2902963985
Short name T547
Test name
Test status
Simulation time 53581793702 ps
CPU time 47.76 seconds
Started Jun 06 01:01:57 PM PDT 24
Finished Jun 06 01:02:46 PM PDT 24
Peak memory 200336 kb
Host smart-eff6adff-f4df-4c56-b373-e0cf8c7079cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902963985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.2902963985
Directory /workspace/52.uart_fifo_reset/latest

Test location /workspace/coverage/default/52.uart_stress_all_with_rand_reset.566339868
Short name T624
Test name
Test status
Simulation time 271317498728 ps
CPU time 966.2 seconds
Started Jun 06 01:02:02 PM PDT 24
Finished Jun 06 01:18:10 PM PDT 24
Peak memory 225324 kb
Host smart-ceabfd80-f4d8-4747-8072-45ae524a280a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566339868 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 52.uart_stress_all_with_rand_reset.566339868
Directory /workspace/52.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.uart_fifo_reset.3044621984
Short name T546
Test name
Test status
Simulation time 62844854517 ps
CPU time 158.99 seconds
Started Jun 06 01:02:01 PM PDT 24
Finished Jun 06 01:04:41 PM PDT 24
Peak memory 200340 kb
Host smart-014a6adb-4f99-4e59-b1aa-b0033ab1ca1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044621984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.3044621984
Directory /workspace/54.uart_fifo_reset/latest

Test location /workspace/coverage/default/54.uart_stress_all_with_rand_reset.4063745619
Short name T436
Test name
Test status
Simulation time 33364368984 ps
CPU time 526.1 seconds
Started Jun 06 01:01:58 PM PDT 24
Finished Jun 06 01:10:45 PM PDT 24
Peak memory 215028 kb
Host smart-3c04b108-ed45-4732-bb14-475c5fd01a85
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063745619 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 54.uart_stress_all_with_rand_reset.4063745619
Directory /workspace/54.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.uart_fifo_reset.1225089962
Short name T279
Test name
Test status
Simulation time 12242851720 ps
CPU time 28.61 seconds
Started Jun 06 01:01:59 PM PDT 24
Finished Jun 06 01:02:29 PM PDT 24
Peak memory 200324 kb
Host smart-4a9531dd-5ab2-4af0-8d2e-9129a1f01b97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225089962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.1225089962
Directory /workspace/55.uart_fifo_reset/latest

Test location /workspace/coverage/default/55.uart_stress_all_with_rand_reset.3295834104
Short name T23
Test name
Test status
Simulation time 31561405491 ps
CPU time 271.47 seconds
Started Jun 06 01:01:59 PM PDT 24
Finished Jun 06 01:06:31 PM PDT 24
Peak memory 215672 kb
Host smart-b5ddd493-1f6a-400d-aa65-bab1d83be1d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295834104 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 55.uart_stress_all_with_rand_reset.3295834104
Directory /workspace/55.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/56.uart_fifo_reset.2014832407
Short name T1064
Test name
Test status
Simulation time 223763004622 ps
CPU time 286.34 seconds
Started Jun 06 01:02:00 PM PDT 24
Finished Jun 06 01:06:47 PM PDT 24
Peak memory 200376 kb
Host smart-1e9af49c-fcb3-4c19-ad8f-da1c91c6d914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014832407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.2014832407
Directory /workspace/56.uart_fifo_reset/latest

Test location /workspace/coverage/default/56.uart_stress_all_with_rand_reset.1118419827
Short name T871
Test name
Test status
Simulation time 244234547733 ps
CPU time 1071.53 seconds
Started Jun 06 01:02:00 PM PDT 24
Finished Jun 06 01:19:54 PM PDT 24
Peak memory 216900 kb
Host smart-592ca78d-4e67-405d-9f0d-f610b21feda7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118419827 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 56.uart_stress_all_with_rand_reset.1118419827
Directory /workspace/56.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.uart_stress_all_with_rand_reset.1160422155
Short name T60
Test name
Test status
Simulation time 174067589199 ps
CPU time 398.14 seconds
Started Jun 06 01:02:00 PM PDT 24
Finished Jun 06 01:08:39 PM PDT 24
Peak memory 225320 kb
Host smart-5d6257b3-b1b8-4e21-b01e-89266b985818
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160422155 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 57.uart_stress_all_with_rand_reset.1160422155
Directory /workspace/57.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/58.uart_fifo_reset.1308376665
Short name T1107
Test name
Test status
Simulation time 100423710228 ps
CPU time 81.55 seconds
Started Jun 06 01:02:02 PM PDT 24
Finished Jun 06 01:03:25 PM PDT 24
Peak memory 200364 kb
Host smart-0804ec24-d77d-49b3-a2bb-045f3dcff980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308376665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.1308376665
Directory /workspace/58.uart_fifo_reset/latest

Test location /workspace/coverage/default/58.uart_stress_all_with_rand_reset.2558533198
Short name T39
Test name
Test status
Simulation time 34541812863 ps
CPU time 299.84 seconds
Started Jun 06 01:02:00 PM PDT 24
Finished Jun 06 01:07:02 PM PDT 24
Peak memory 215832 kb
Host smart-e36ea52f-f55c-409e-bd9e-d7b3c3ffdf54
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558533198 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 58.uart_stress_all_with_rand_reset.2558533198
Directory /workspace/58.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/59.uart_fifo_reset.104314982
Short name T187
Test name
Test status
Simulation time 21597173554 ps
CPU time 35.3 seconds
Started Jun 06 01:02:00 PM PDT 24
Finished Jun 06 01:02:37 PM PDT 24
Peak memory 200376 kb
Host smart-08b85051-cfa7-48b6-97b4-12016a42495f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104314982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.104314982
Directory /workspace/59.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_alert_test.308281489
Short name T593
Test name
Test status
Simulation time 38876269 ps
CPU time 0.54 seconds
Started Jun 06 12:58:17 PM PDT 24
Finished Jun 06 12:58:20 PM PDT 24
Peak memory 194688 kb
Host smart-4967f640-9d30-4051-a5b4-f1330966ae64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308281489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.308281489
Directory /workspace/6.uart_alert_test/latest

Test location /workspace/coverage/default/6.uart_fifo_full.155193946
Short name T1130
Test name
Test status
Simulation time 89487482461 ps
CPU time 192.4 seconds
Started Jun 06 12:58:12 PM PDT 24
Finished Jun 06 01:01:26 PM PDT 24
Peak memory 200344 kb
Host smart-8ec890b0-0fa0-4d5a-821e-5bd360764329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155193946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.155193946
Directory /workspace/6.uart_fifo_full/latest

Test location /workspace/coverage/default/6.uart_fifo_overflow.58772077
Short name T915
Test name
Test status
Simulation time 119027027172 ps
CPU time 509.7 seconds
Started Jun 06 12:58:12 PM PDT 24
Finished Jun 06 01:06:44 PM PDT 24
Peak memory 200412 kb
Host smart-857a346a-9cee-4ef7-be28-655fd0e0c70d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58772077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.58772077
Directory /workspace/6.uart_fifo_overflow/latest

Test location /workspace/coverage/default/6.uart_intr.137260088
Short name T1097
Test name
Test status
Simulation time 28270880489 ps
CPU time 51.54 seconds
Started Jun 06 12:58:18 PM PDT 24
Finished Jun 06 12:59:11 PM PDT 24
Peak memory 200340 kb
Host smart-9971db1b-d4c9-48f4-b904-70fea9312397
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137260088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.137260088
Directory /workspace/6.uart_intr/latest

Test location /workspace/coverage/default/6.uart_long_xfer_wo_dly.1211995962
Short name T708
Test name
Test status
Simulation time 44678091964 ps
CPU time 365.75 seconds
Started Jun 06 12:58:14 PM PDT 24
Finished Jun 06 01:04:21 PM PDT 24
Peak memory 200296 kb
Host smart-d62e1931-c49c-41da-be0f-db4e090b3b55
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1211995962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.1211995962
Directory /workspace/6.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/6.uart_loopback.156527616
Short name T626
Test name
Test status
Simulation time 3633310321 ps
CPU time 3.86 seconds
Started Jun 06 12:58:12 PM PDT 24
Finished Jun 06 12:58:17 PM PDT 24
Peak memory 200068 kb
Host smart-9a36570e-ae3f-4d5c-a1e7-cb28e98768dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156527616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_loopback.156527616
Directory /workspace/6.uart_loopback/latest

Test location /workspace/coverage/default/6.uart_noise_filter.3194568863
Short name T1136
Test name
Test status
Simulation time 63688014599 ps
CPU time 141.52 seconds
Started Jun 06 12:58:17 PM PDT 24
Finished Jun 06 01:00:40 PM PDT 24
Peak memory 200580 kb
Host smart-34f12809-a94c-44da-b751-207912adca58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194568863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_noise_filter.3194568863
Directory /workspace/6.uart_noise_filter/latest

Test location /workspace/coverage/default/6.uart_perf.2035433659
Short name T730
Test name
Test status
Simulation time 15685235972 ps
CPU time 730.94 seconds
Started Jun 06 12:58:12 PM PDT 24
Finished Jun 06 01:10:24 PM PDT 24
Peak memory 200356 kb
Host smart-681951f1-8e49-466d-ad33-498e3ccd3ba9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2035433659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.2035433659
Directory /workspace/6.uart_perf/latest

Test location /workspace/coverage/default/6.uart_rx_oversample.1936117731
Short name T351
Test name
Test status
Simulation time 2305605234 ps
CPU time 12.07 seconds
Started Jun 06 12:58:12 PM PDT 24
Finished Jun 06 12:58:25 PM PDT 24
Peak memory 198620 kb
Host smart-65ce74fc-a392-41c5-b873-9023b4b8575b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1936117731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.1936117731
Directory /workspace/6.uart_rx_oversample/latest

Test location /workspace/coverage/default/6.uart_rx_parity_err.2707955785
Short name T417
Test name
Test status
Simulation time 99639983006 ps
CPU time 49.1 seconds
Started Jun 06 12:58:15 PM PDT 24
Finished Jun 06 12:59:05 PM PDT 24
Peak memory 200268 kb
Host smart-8704a320-b601-4435-a818-d27f4def6b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707955785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.2707955785
Directory /workspace/6.uart_rx_parity_err/latest

Test location /workspace/coverage/default/6.uart_rx_start_bit_filter.1850405036
Short name T807
Test name
Test status
Simulation time 1841931681 ps
CPU time 2.73 seconds
Started Jun 06 12:58:12 PM PDT 24
Finished Jun 06 12:58:17 PM PDT 24
Peak memory 195920 kb
Host smart-78374f51-3084-400d-a70e-6d89beaabe3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850405036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.1850405036
Directory /workspace/6.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/6.uart_smoke.3011559008
Short name T345
Test name
Test status
Simulation time 315118724 ps
CPU time 1.28 seconds
Started Jun 06 12:58:13 PM PDT 24
Finished Jun 06 12:58:15 PM PDT 24
Peak memory 198876 kb
Host smart-4cc2897f-e9d9-41cb-b667-29f0ee241357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011559008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_smoke.3011559008
Directory /workspace/6.uart_smoke/latest

Test location /workspace/coverage/default/6.uart_stress_all.283003003
Short name T579
Test name
Test status
Simulation time 58825343021 ps
CPU time 489.44 seconds
Started Jun 06 12:58:12 PM PDT 24
Finished Jun 06 01:06:23 PM PDT 24
Peak memory 200336 kb
Host smart-434362a2-04c2-46d7-a94e-dbd93b41099a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283003003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.283003003
Directory /workspace/6.uart_stress_all/latest

Test location /workspace/coverage/default/6.uart_stress_all_with_rand_reset.3821113501
Short name T815
Test name
Test status
Simulation time 16348624534 ps
CPU time 189.2 seconds
Started Jun 06 12:58:14 PM PDT 24
Finished Jun 06 01:01:25 PM PDT 24
Peak memory 216664 kb
Host smart-81692f6c-176d-4770-8bfc-7649fded1f7e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821113501 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 6.uart_stress_all_with_rand_reset.3821113501
Directory /workspace/6.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_tx_ovrd.965630430
Short name T617
Test name
Test status
Simulation time 611778299 ps
CPU time 2.58 seconds
Started Jun 06 12:58:12 PM PDT 24
Finished Jun 06 12:58:16 PM PDT 24
Peak memory 198872 kb
Host smart-b9fd3b2d-3d0c-43d2-9899-7a7cf3cd8426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965630430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.965630430
Directory /workspace/6.uart_tx_ovrd/latest

Test location /workspace/coverage/default/6.uart_tx_rx.4261424189
Short name T1099
Test name
Test status
Simulation time 24092734214 ps
CPU time 41.71 seconds
Started Jun 06 12:58:14 PM PDT 24
Finished Jun 06 12:58:57 PM PDT 24
Peak memory 200320 kb
Host smart-e4601f26-e036-4ed9-8126-f94ed0869034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261424189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.4261424189
Directory /workspace/6.uart_tx_rx/latest

Test location /workspace/coverage/default/60.uart_fifo_reset.2122430691
Short name T1120
Test name
Test status
Simulation time 138061603552 ps
CPU time 186.12 seconds
Started Jun 06 01:01:59 PM PDT 24
Finished Jun 06 01:05:07 PM PDT 24
Peak memory 200288 kb
Host smart-b5ca04c1-208c-4f5d-8e96-c9794e0f5b12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122430691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.2122430691
Directory /workspace/60.uart_fifo_reset/latest

Test location /workspace/coverage/default/60.uart_stress_all_with_rand_reset.602261439
Short name T767
Test name
Test status
Simulation time 14986747951 ps
CPU time 589.93 seconds
Started Jun 06 01:02:00 PM PDT 24
Finished Jun 06 01:11:52 PM PDT 24
Peak memory 208624 kb
Host smart-01847e8f-b620-4315-8497-9aa051d8cdbe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602261439 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 60.uart_stress_all_with_rand_reset.602261439
Directory /workspace/60.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/61.uart_fifo_reset.1820936167
Short name T249
Test name
Test status
Simulation time 52167921895 ps
CPU time 23.78 seconds
Started Jun 06 01:02:02 PM PDT 24
Finished Jun 06 01:02:27 PM PDT 24
Peak memory 200352 kb
Host smart-501305f1-555a-4f6b-bdb8-f59d222acca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820936167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.1820936167
Directory /workspace/61.uart_fifo_reset/latest

Test location /workspace/coverage/default/61.uart_stress_all_with_rand_reset.2528648946
Short name T119
Test name
Test status
Simulation time 78995623074 ps
CPU time 1013.36 seconds
Started Jun 06 01:02:01 PM PDT 24
Finished Jun 06 01:18:56 PM PDT 24
Peak memory 216712 kb
Host smart-8976aa95-04c8-4305-ba94-493d5bd30254
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528648946 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 61.uart_stress_all_with_rand_reset.2528648946
Directory /workspace/61.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.uart_fifo_reset.665866108
Short name T462
Test name
Test status
Simulation time 9797292372 ps
CPU time 16.22 seconds
Started Jun 06 01:02:01 PM PDT 24
Finished Jun 06 01:02:19 PM PDT 24
Peak memory 200328 kb
Host smart-5b7a2e77-600b-4d57-aadd-520bd0e97be5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665866108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.665866108
Directory /workspace/62.uart_fifo_reset/latest

Test location /workspace/coverage/default/63.uart_fifo_reset.3266601273
Short name T780
Test name
Test status
Simulation time 102997452797 ps
CPU time 161.21 seconds
Started Jun 06 01:02:01 PM PDT 24
Finished Jun 06 01:04:44 PM PDT 24
Peak memory 200244 kb
Host smart-1f982326-a2c4-4a70-8f04-bc02e10db7ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266601273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.3266601273
Directory /workspace/63.uart_fifo_reset/latest

Test location /workspace/coverage/default/63.uart_stress_all_with_rand_reset.2568757516
Short name T1060
Test name
Test status
Simulation time 191924481395 ps
CPU time 563.22 seconds
Started Jun 06 01:02:01 PM PDT 24
Finished Jun 06 01:11:25 PM PDT 24
Peak memory 229396 kb
Host smart-e0256128-7f60-48c9-8ed8-b1fbc3952ebb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568757516 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 63.uart_stress_all_with_rand_reset.2568757516
Directory /workspace/63.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/64.uart_fifo_reset.4101252432
Short name T224
Test name
Test status
Simulation time 58316880912 ps
CPU time 87.71 seconds
Started Jun 06 01:02:03 PM PDT 24
Finished Jun 06 01:03:32 PM PDT 24
Peak memory 200188 kb
Host smart-723a43dd-79e1-456a-90da-81c8819e8f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101252432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.4101252432
Directory /workspace/64.uart_fifo_reset/latest

Test location /workspace/coverage/default/64.uart_stress_all_with_rand_reset.2506415935
Short name T584
Test name
Test status
Simulation time 56136187696 ps
CPU time 357.82 seconds
Started Jun 06 01:02:12 PM PDT 24
Finished Jun 06 01:08:11 PM PDT 24
Peak memory 216688 kb
Host smart-675d8de0-156d-4c21-83b9-c1036634bed5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506415935 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 64.uart_stress_all_with_rand_reset.2506415935
Directory /workspace/64.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/65.uart_fifo_reset.1773429149
Short name T463
Test name
Test status
Simulation time 87238006157 ps
CPU time 103.15 seconds
Started Jun 06 01:02:11 PM PDT 24
Finished Jun 06 01:03:55 PM PDT 24
Peak memory 200264 kb
Host smart-d90fd28b-ce49-4d54-8b5a-5eb938125361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773429149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.1773429149
Directory /workspace/65.uart_fifo_reset/latest

Test location /workspace/coverage/default/65.uart_stress_all_with_rand_reset.190181867
Short name T221
Test name
Test status
Simulation time 298576028551 ps
CPU time 415.64 seconds
Started Jun 06 01:02:11 PM PDT 24
Finished Jun 06 01:09:08 PM PDT 24
Peak memory 229256 kb
Host smart-b81fc49d-2864-442c-9d9f-f726a5ec4da8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190181867 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 65.uart_stress_all_with_rand_reset.190181867
Directory /workspace/65.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/66.uart_fifo_reset.1089583952
Short name T614
Test name
Test status
Simulation time 35047872380 ps
CPU time 17.02 seconds
Started Jun 06 01:02:12 PM PDT 24
Finished Jun 06 01:02:30 PM PDT 24
Peak memory 200636 kb
Host smart-20eca2ad-a2ce-4e6a-925d-383c64fc0e6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089583952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.1089583952
Directory /workspace/66.uart_fifo_reset/latest

Test location /workspace/coverage/default/66.uart_stress_all_with_rand_reset.3338462538
Short name T189
Test name
Test status
Simulation time 492523641423 ps
CPU time 1027.87 seconds
Started Jun 06 01:02:14 PM PDT 24
Finished Jun 06 01:19:23 PM PDT 24
Peak memory 225300 kb
Host smart-6629cf05-f3f4-45a7-be32-cf2ee89030b6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338462538 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 66.uart_stress_all_with_rand_reset.3338462538
Directory /workspace/66.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.uart_fifo_reset.2303089265
Short name T467
Test name
Test status
Simulation time 14469809386 ps
CPU time 24.32 seconds
Started Jun 06 01:02:12 PM PDT 24
Finished Jun 06 01:02:37 PM PDT 24
Peak memory 200368 kb
Host smart-74ede386-7ebb-4d97-8478-2f5df0c4a942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303089265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.2303089265
Directory /workspace/67.uart_fifo_reset/latest

Test location /workspace/coverage/default/67.uart_stress_all_with_rand_reset.3124536156
Short name T620
Test name
Test status
Simulation time 319448480041 ps
CPU time 967.47 seconds
Started Jun 06 01:02:12 PM PDT 24
Finished Jun 06 01:18:20 PM PDT 24
Peak memory 217104 kb
Host smart-4bff2d80-0f0c-4d2a-8627-1c7a9d2aa7c3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124536156 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 67.uart_stress_all_with_rand_reset.3124536156
Directory /workspace/67.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/68.uart_fifo_reset.871764890
Short name T1121
Test name
Test status
Simulation time 119862731990 ps
CPU time 48.17 seconds
Started Jun 06 01:02:12 PM PDT 24
Finished Jun 06 01:03:01 PM PDT 24
Peak memory 200292 kb
Host smart-4855964a-81ff-4fd0-831d-ae4222a0321e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871764890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.871764890
Directory /workspace/68.uart_fifo_reset/latest

Test location /workspace/coverage/default/68.uart_stress_all_with_rand_reset.3639929413
Short name T867
Test name
Test status
Simulation time 101419995202 ps
CPU time 492.76 seconds
Started Jun 06 01:02:10 PM PDT 24
Finished Jun 06 01:10:23 PM PDT 24
Peak memory 216780 kb
Host smart-e0d6cb81-74bc-4933-9f26-e20f5de1ca00
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639929413 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 68.uart_stress_all_with_rand_reset.3639929413
Directory /workspace/68.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.uart_stress_all_with_rand_reset.3325882361
Short name T58
Test name
Test status
Simulation time 27333629953 ps
CPU time 250.43 seconds
Started Jun 06 01:02:12 PM PDT 24
Finished Jun 06 01:06:24 PM PDT 24
Peak memory 216584 kb
Host smart-1e49ddc2-05b8-4615-a115-52a8e0fc25a4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325882361 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 69.uart_stress_all_with_rand_reset.3325882361
Directory /workspace/69.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_alert_test.1869433443
Short name T795
Test name
Test status
Simulation time 15936451 ps
CPU time 0.56 seconds
Started Jun 06 12:58:13 PM PDT 24
Finished Jun 06 12:58:15 PM PDT 24
Peak memory 195716 kb
Host smart-5bfbaa60-aed6-4389-80ed-0b68a9e3d318
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869433443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.1869433443
Directory /workspace/7.uart_alert_test/latest

Test location /workspace/coverage/default/7.uart_fifo_full.1146782747
Short name T685
Test name
Test status
Simulation time 63458566391 ps
CPU time 37.55 seconds
Started Jun 06 12:58:15 PM PDT 24
Finished Jun 06 12:58:54 PM PDT 24
Peak memory 199936 kb
Host smart-ad66f89f-f838-4989-b80c-c53615639d08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146782747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.1146782747
Directory /workspace/7.uart_fifo_full/latest

Test location /workspace/coverage/default/7.uart_fifo_overflow.1147468162
Short name T880
Test name
Test status
Simulation time 93987771963 ps
CPU time 25.09 seconds
Started Jun 06 12:58:13 PM PDT 24
Finished Jun 06 12:58:39 PM PDT 24
Peak memory 200268 kb
Host smart-acf0de39-451d-4b12-adfa-fe01e15e8ff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147468162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.1147468162
Directory /workspace/7.uart_fifo_overflow/latest

Test location /workspace/coverage/default/7.uart_fifo_reset.2848987455
Short name T899
Test name
Test status
Simulation time 11464725238 ps
CPU time 24.78 seconds
Started Jun 06 12:58:11 PM PDT 24
Finished Jun 06 12:58:37 PM PDT 24
Peak memory 200268 kb
Host smart-56184a06-e5d2-4a6a-b343-216d4280ea40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848987455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.2848987455
Directory /workspace/7.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_intr.58594680
Short name T401
Test name
Test status
Simulation time 107743317922 ps
CPU time 39.68 seconds
Started Jun 06 12:58:15 PM PDT 24
Finished Jun 06 12:58:56 PM PDT 24
Peak memory 200252 kb
Host smart-073661f1-0088-4a81-b3b6-4df7b085d497
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58594680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.58594680
Directory /workspace/7.uart_intr/latest

Test location /workspace/coverage/default/7.uart_long_xfer_wo_dly.2404417042
Short name T540
Test name
Test status
Simulation time 124731176114 ps
CPU time 1102.61 seconds
Started Jun 06 12:58:12 PM PDT 24
Finished Jun 06 01:16:36 PM PDT 24
Peak memory 200304 kb
Host smart-d93324bf-2eb5-4147-bb01-414d4fa832a7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2404417042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.2404417042
Directory /workspace/7.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/7.uart_loopback.2494649856
Short name T1179
Test name
Test status
Simulation time 346622698 ps
CPU time 0.95 seconds
Started Jun 06 12:58:15 PM PDT 24
Finished Jun 06 12:58:17 PM PDT 24
Peak memory 198792 kb
Host smart-e0e52355-45fb-4ee3-bda4-b859c732ad05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494649856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_loopback.2494649856
Directory /workspace/7.uart_loopback/latest

Test location /workspace/coverage/default/7.uart_noise_filter.1859674973
Short name T949
Test name
Test status
Simulation time 19277293919 ps
CPU time 15.8 seconds
Started Jun 06 12:58:12 PM PDT 24
Finished Jun 06 12:58:30 PM PDT 24
Peak memory 198112 kb
Host smart-6ac27a71-8bd1-428a-b9da-159277f17aa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859674973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_noise_filter.1859674973
Directory /workspace/7.uart_noise_filter/latest

Test location /workspace/coverage/default/7.uart_perf.3382553769
Short name T265
Test name
Test status
Simulation time 15285803494 ps
CPU time 864.7 seconds
Started Jun 06 12:58:14 PM PDT 24
Finished Jun 06 01:12:40 PM PDT 24
Peak memory 200376 kb
Host smart-7b905955-769f-4311-b6a9-79f758829ebb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3382553769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.3382553769
Directory /workspace/7.uart_perf/latest

Test location /workspace/coverage/default/7.uart_rx_oversample.1166363055
Short name T1030
Test name
Test status
Simulation time 7307815301 ps
CPU time 17.15 seconds
Started Jun 06 12:58:12 PM PDT 24
Finished Jun 06 12:58:31 PM PDT 24
Peak memory 198532 kb
Host smart-2715b0eb-d380-479a-bc45-437867068227
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1166363055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.1166363055
Directory /workspace/7.uart_rx_oversample/latest

Test location /workspace/coverage/default/7.uart_rx_parity_err.3249001877
Short name T290
Test name
Test status
Simulation time 80600753492 ps
CPU time 21.73 seconds
Started Jun 06 12:58:12 PM PDT 24
Finished Jun 06 12:58:35 PM PDT 24
Peak memory 200116 kb
Host smart-b4cf2c7d-c58d-4aa4-adeb-178c8a29f892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249001877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.3249001877
Directory /workspace/7.uart_rx_parity_err/latest

Test location /workspace/coverage/default/7.uart_rx_start_bit_filter.3187173081
Short name T1128
Test name
Test status
Simulation time 50496440623 ps
CPU time 18.85 seconds
Started Jun 06 12:58:15 PM PDT 24
Finished Jun 06 12:58:36 PM PDT 24
Peak memory 196116 kb
Host smart-7d4d5d74-17fa-429c-983a-a78ffbf7ef53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187173081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.3187173081
Directory /workspace/7.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/7.uart_smoke.2020674231
Short name T78
Test name
Test status
Simulation time 6063642346 ps
CPU time 10.64 seconds
Started Jun 06 12:58:12 PM PDT 24
Finished Jun 06 12:58:24 PM PDT 24
Peak memory 200236 kb
Host smart-802a0853-b655-4954-804e-4536f8553e82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020674231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_smoke.2020674231
Directory /workspace/7.uart_smoke/latest

Test location /workspace/coverage/default/7.uart_stress_all.1303574848
Short name T166
Test name
Test status
Simulation time 366121731920 ps
CPU time 229.7 seconds
Started Jun 06 12:58:16 PM PDT 24
Finished Jun 06 01:02:08 PM PDT 24
Peak memory 200388 kb
Host smart-4096a0f2-92e1-4af8-a2c8-81e26ce464be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303574848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.1303574848
Directory /workspace/7.uart_stress_all/latest

Test location /workspace/coverage/default/7.uart_tx_ovrd.4053329904
Short name T806
Test name
Test status
Simulation time 3082730336 ps
CPU time 1.83 seconds
Started Jun 06 12:58:12 PM PDT 24
Finished Jun 06 12:58:16 PM PDT 24
Peak memory 198860 kb
Host smart-198b6127-8331-4d25-89f7-68ce225eb84a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053329904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.4053329904
Directory /workspace/7.uart_tx_ovrd/latest

Test location /workspace/coverage/default/7.uart_tx_rx.1450232348
Short name T879
Test name
Test status
Simulation time 6681096287 ps
CPU time 4.89 seconds
Started Jun 06 12:58:15 PM PDT 24
Finished Jun 06 12:58:21 PM PDT 24
Peak memory 197944 kb
Host smart-2234e59d-cc9c-4149-812c-76a7ceb4cb33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450232348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.1450232348
Directory /workspace/7.uart_tx_rx/latest

Test location /workspace/coverage/default/70.uart_fifo_reset.3708641703
Short name T242
Test name
Test status
Simulation time 63301462957 ps
CPU time 40.1 seconds
Started Jun 06 01:02:13 PM PDT 24
Finished Jun 06 01:02:55 PM PDT 24
Peak memory 200204 kb
Host smart-e356d228-c032-4c46-8a85-9f80fc432bda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708641703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.3708641703
Directory /workspace/70.uart_fifo_reset/latest

Test location /workspace/coverage/default/70.uart_stress_all_with_rand_reset.1019012809
Short name T1094
Test name
Test status
Simulation time 28211919668 ps
CPU time 560.68 seconds
Started Jun 06 01:02:13 PM PDT 24
Finished Jun 06 01:11:35 PM PDT 24
Peak memory 216808 kb
Host smart-cb66de1b-8e81-468d-93ee-90564936349b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019012809 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 70.uart_stress_all_with_rand_reset.1019012809
Directory /workspace/70.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/71.uart_fifo_reset.3965540962
Short name T398
Test name
Test status
Simulation time 22819452055 ps
CPU time 17.38 seconds
Started Jun 06 01:02:16 PM PDT 24
Finished Jun 06 01:02:34 PM PDT 24
Peak memory 200308 kb
Host smart-63412436-1c73-438f-88f4-5f1b15f1716b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965540962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.3965540962
Directory /workspace/71.uart_fifo_reset/latest

Test location /workspace/coverage/default/71.uart_stress_all_with_rand_reset.1644094930
Short name T684
Test name
Test status
Simulation time 50397365381 ps
CPU time 224.01 seconds
Started Jun 06 01:02:16 PM PDT 24
Finished Jun 06 01:06:01 PM PDT 24
Peak memory 216352 kb
Host smart-c34474ec-8aa4-4139-91b7-189ac2562890
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644094930 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 71.uart_stress_all_with_rand_reset.1644094930
Directory /workspace/71.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/72.uart_fifo_reset.3047114799
Short name T267
Test name
Test status
Simulation time 18266928630 ps
CPU time 28.86 seconds
Started Jun 06 01:02:13 PM PDT 24
Finished Jun 06 01:02:43 PM PDT 24
Peak memory 200032 kb
Host smart-dbf9e8a2-4a80-4549-bf2c-6a42fdd8dfdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047114799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.3047114799
Directory /workspace/72.uart_fifo_reset/latest

Test location /workspace/coverage/default/72.uart_stress_all_with_rand_reset.3420145923
Short name T805
Test name
Test status
Simulation time 50490825687 ps
CPU time 1026.92 seconds
Started Jun 06 01:02:15 PM PDT 24
Finished Jun 06 01:19:23 PM PDT 24
Peak memory 216812 kb
Host smart-acda822d-9b16-434a-afeb-47adb96d1761
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420145923 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 72.uart_stress_all_with_rand_reset.3420145923
Directory /workspace/72.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/73.uart_fifo_reset.1947668655
Short name T848
Test name
Test status
Simulation time 16762271637 ps
CPU time 12.67 seconds
Started Jun 06 01:02:15 PM PDT 24
Finished Jun 06 01:02:29 PM PDT 24
Peak memory 200284 kb
Host smart-4306aba3-982d-489a-a69d-b3f42958c2c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947668655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.1947668655
Directory /workspace/73.uart_fifo_reset/latest

Test location /workspace/coverage/default/73.uart_stress_all_with_rand_reset.3240439702
Short name T714
Test name
Test status
Simulation time 49076187138 ps
CPU time 434.76 seconds
Started Jun 06 01:02:14 PM PDT 24
Finished Jun 06 01:09:30 PM PDT 24
Peak memory 216792 kb
Host smart-d7881efd-4743-4930-8009-f5a62b3b4ae1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240439702 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 73.uart_stress_all_with_rand_reset.3240439702
Directory /workspace/73.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/74.uart_fifo_reset.399341678
Short name T1117
Test name
Test status
Simulation time 68567380089 ps
CPU time 55.25 seconds
Started Jun 06 01:02:14 PM PDT 24
Finished Jun 06 01:03:11 PM PDT 24
Peak memory 200264 kb
Host smart-47da8dce-893d-4c30-81a4-31e9cc6abacc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399341678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.399341678
Directory /workspace/74.uart_fifo_reset/latest

Test location /workspace/coverage/default/74.uart_stress_all_with_rand_reset.2748898068
Short name T118
Test name
Test status
Simulation time 47943835063 ps
CPU time 729.31 seconds
Started Jun 06 01:02:14 PM PDT 24
Finished Jun 06 01:14:25 PM PDT 24
Peak memory 227708 kb
Host smart-5f74d4ee-653c-476c-b505-0d823cb04e48
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748898068 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 74.uart_stress_all_with_rand_reset.2748898068
Directory /workspace/74.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/76.uart_fifo_reset.2617001003
Short name T219
Test name
Test status
Simulation time 52522090737 ps
CPU time 25.63 seconds
Started Jun 06 01:02:14 PM PDT 24
Finished Jun 06 01:02:41 PM PDT 24
Peak memory 200260 kb
Host smart-f114cd43-309c-4a4a-969f-eb7a5ad7c4f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617001003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.2617001003
Directory /workspace/76.uart_fifo_reset/latest

Test location /workspace/coverage/default/77.uart_fifo_reset.1809645563
Short name T939
Test name
Test status
Simulation time 66894881200 ps
CPU time 26.28 seconds
Started Jun 06 01:02:14 PM PDT 24
Finished Jun 06 01:02:42 PM PDT 24
Peak memory 200048 kb
Host smart-ce7eb26d-890b-432c-aa12-6fef2de5bcd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809645563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.1809645563
Directory /workspace/77.uart_fifo_reset/latest

Test location /workspace/coverage/default/77.uart_stress_all_with_rand_reset.2912324728
Short name T62
Test name
Test status
Simulation time 82932335738 ps
CPU time 631.94 seconds
Started Jun 06 01:02:16 PM PDT 24
Finished Jun 06 01:12:49 PM PDT 24
Peak memory 217140 kb
Host smart-bed593b9-c945-427f-b858-474f1417e728
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912324728 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 77.uart_stress_all_with_rand_reset.2912324728
Directory /workspace/77.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/78.uart_fifo_reset.3759487484
Short name T760
Test name
Test status
Simulation time 36317872173 ps
CPU time 14.44 seconds
Started Jun 06 01:02:16 PM PDT 24
Finished Jun 06 01:02:32 PM PDT 24
Peak memory 200344 kb
Host smart-caefc421-be2d-4909-ab0b-645db345f602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759487484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.3759487484
Directory /workspace/78.uart_fifo_reset/latest

Test location /workspace/coverage/default/78.uart_stress_all_with_rand_reset.4023653321
Short name T930
Test name
Test status
Simulation time 228112571554 ps
CPU time 302.66 seconds
Started Jun 06 01:02:22 PM PDT 24
Finished Jun 06 01:07:26 PM PDT 24
Peak memory 217072 kb
Host smart-22b2d425-0cc7-438f-8c7c-260040413ff6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023653321 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 78.uart_stress_all_with_rand_reset.4023653321
Directory /workspace/78.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.uart_fifo_reset.471906280
Short name T223
Test name
Test status
Simulation time 27450995920 ps
CPU time 49.63 seconds
Started Jun 06 01:02:20 PM PDT 24
Finished Jun 06 01:03:11 PM PDT 24
Peak memory 200332 kb
Host smart-45e38978-aa78-4678-9c54-c47c434f6d27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471906280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.471906280
Directory /workspace/79.uart_fifo_reset/latest

Test location /workspace/coverage/default/79.uart_stress_all_with_rand_reset.164421157
Short name T210
Test name
Test status
Simulation time 1842671961430 ps
CPU time 1638.97 seconds
Started Jun 06 01:02:23 PM PDT 24
Finished Jun 06 01:29:44 PM PDT 24
Peak memory 231920 kb
Host smart-77ee9605-13fb-4910-ac08-f73e7b41e293
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164421157 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 79.uart_stress_all_with_rand_reset.164421157
Directory /workspace/79.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_alert_test.2021102807
Short name T607
Test name
Test status
Simulation time 53875186 ps
CPU time 0.52 seconds
Started Jun 06 12:58:20 PM PDT 24
Finished Jun 06 12:58:21 PM PDT 24
Peak memory 195688 kb
Host smart-70827837-3da0-45a1-9a18-185030675cbf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021102807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.2021102807
Directory /workspace/8.uart_alert_test/latest

Test location /workspace/coverage/default/8.uart_fifo_full.3640414775
Short name T728
Test name
Test status
Simulation time 209423747831 ps
CPU time 566.96 seconds
Started Jun 06 12:58:17 PM PDT 24
Finished Jun 06 01:07:46 PM PDT 24
Peak memory 200228 kb
Host smart-c58dfdaa-6b21-4b5c-af3f-0193dc6870b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640414775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.3640414775
Directory /workspace/8.uart_fifo_full/latest

Test location /workspace/coverage/default/8.uart_fifo_overflow.36353577
Short name T40
Test name
Test status
Simulation time 23121926622 ps
CPU time 51.61 seconds
Started Jun 06 12:58:13 PM PDT 24
Finished Jun 06 12:59:06 PM PDT 24
Peak memory 200244 kb
Host smart-785b774c-2a79-4a9e-bc51-960438d15694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36353577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.36353577
Directory /workspace/8.uart_fifo_overflow/latest

Test location /workspace/coverage/default/8.uart_fifo_reset.2365009488
Short name T237
Test name
Test status
Simulation time 46908709075 ps
CPU time 19.67 seconds
Started Jun 06 12:58:13 PM PDT 24
Finished Jun 06 12:58:34 PM PDT 24
Peak memory 200364 kb
Host smart-f8bbca85-c0d6-4abc-9a6f-f8dfa6db5720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365009488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.2365009488
Directory /workspace/8.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_intr.1259978840
Short name T940
Test name
Test status
Simulation time 14278144684 ps
CPU time 5.62 seconds
Started Jun 06 12:58:16 PM PDT 24
Finished Jun 06 12:58:24 PM PDT 24
Peak memory 197952 kb
Host smart-f86cea16-3f22-40d9-b014-77a517571cea
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259978840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.1259978840
Directory /workspace/8.uart_intr/latest

Test location /workspace/coverage/default/8.uart_long_xfer_wo_dly.298151000
Short name T501
Test name
Test status
Simulation time 120795046682 ps
CPU time 580.46 seconds
Started Jun 06 12:58:23 PM PDT 24
Finished Jun 06 01:08:05 PM PDT 24
Peak memory 200380 kb
Host smart-5cf4ced2-1c62-43c2-9738-41c54e288b55
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=298151000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.298151000
Directory /workspace/8.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/8.uart_loopback.4293185510
Short name T996
Test name
Test status
Simulation time 9361253816 ps
CPU time 15.93 seconds
Started Jun 06 12:58:24 PM PDT 24
Finished Jun 06 12:58:41 PM PDT 24
Peak memory 200352 kb
Host smart-e9bf863c-b677-4bea-9ecd-33112b478dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293185510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_loopback.4293185510
Directory /workspace/8.uart_loopback/latest

Test location /workspace/coverage/default/8.uart_noise_filter.1865135845
Short name T682
Test name
Test status
Simulation time 34471660578 ps
CPU time 16.99 seconds
Started Jun 06 12:58:16 PM PDT 24
Finished Jun 06 12:58:35 PM PDT 24
Peak memory 199424 kb
Host smart-0be4bb6d-c516-4a38-9efa-1c040cbb664b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865135845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_noise_filter.1865135845
Directory /workspace/8.uart_noise_filter/latest

Test location /workspace/coverage/default/8.uart_perf.3225704789
Short name T964
Test name
Test status
Simulation time 11559560452 ps
CPU time 333.87 seconds
Started Jun 06 12:58:20 PM PDT 24
Finished Jun 06 01:03:55 PM PDT 24
Peak memory 200200 kb
Host smart-21d18e4a-fe3a-4239-8fc5-ff8490842364
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3225704789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.3225704789
Directory /workspace/8.uart_perf/latest

Test location /workspace/coverage/default/8.uart_rx_oversample.3113950127
Short name T407
Test name
Test status
Simulation time 5508577021 ps
CPU time 11.78 seconds
Started Jun 06 12:58:15 PM PDT 24
Finished Jun 06 12:58:28 PM PDT 24
Peak memory 198540 kb
Host smart-abaeaf46-4c7f-4b41-8b6c-73c0f2830258
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3113950127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.3113950127
Directory /workspace/8.uart_rx_oversample/latest

Test location /workspace/coverage/default/8.uart_rx_parity_err.489584257
Short name T1175
Test name
Test status
Simulation time 52322007303 ps
CPU time 45.11 seconds
Started Jun 06 12:58:16 PM PDT 24
Finished Jun 06 12:59:03 PM PDT 24
Peak memory 200392 kb
Host smart-5b35a85b-c22c-41e8-af86-104ffcd8cea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489584257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.489584257
Directory /workspace/8.uart_rx_parity_err/latest

Test location /workspace/coverage/default/8.uart_rx_start_bit_filter.1604561450
Short name T920
Test name
Test status
Simulation time 3670200514 ps
CPU time 7.13 seconds
Started Jun 06 12:58:16 PM PDT 24
Finished Jun 06 12:58:25 PM PDT 24
Peak memory 196384 kb
Host smart-3e0e2241-b3de-4310-bbb2-7e1d99c2cab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604561450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.1604561450
Directory /workspace/8.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/8.uart_smoke.412307515
Short name T497
Test name
Test status
Simulation time 248275157 ps
CPU time 1.63 seconds
Started Jun 06 12:58:17 PM PDT 24
Finished Jun 06 12:58:21 PM PDT 24
Peak memory 198536 kb
Host smart-71c0e7b4-1ea8-43b0-8a0c-ba00e8aad0ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412307515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_smoke.412307515
Directory /workspace/8.uart_smoke/latest

Test location /workspace/coverage/default/8.uart_stress_all.2139927133
Short name T1033
Test name
Test status
Simulation time 48257611057 ps
CPU time 469.7 seconds
Started Jun 06 12:58:22 PM PDT 24
Finished Jun 06 01:06:13 PM PDT 24
Peak memory 200356 kb
Host smart-91485284-0232-47b9-8102-a81fb7fb92fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139927133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.2139927133
Directory /workspace/8.uart_stress_all/latest

Test location /workspace/coverage/default/8.uart_stress_all_with_rand_reset.3860202816
Short name T958
Test name
Test status
Simulation time 46120860576 ps
CPU time 560.03 seconds
Started Jun 06 12:58:20 PM PDT 24
Finished Jun 06 01:07:42 PM PDT 24
Peak memory 228360 kb
Host smart-b31bb1ad-8842-45a1-9433-7489b4292e8f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860202816 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 8.uart_stress_all_with_rand_reset.3860202816
Directory /workspace/8.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_tx_ovrd.124881837
Short name T82
Test name
Test status
Simulation time 13679901556 ps
CPU time 5.75 seconds
Started Jun 06 12:58:15 PM PDT 24
Finished Jun 06 12:58:22 PM PDT 24
Peak memory 200140 kb
Host smart-2ae7b14f-476b-4afa-b984-474488e52876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124881837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.124881837
Directory /workspace/8.uart_tx_ovrd/latest

Test location /workspace/coverage/default/8.uart_tx_rx.3605682733
Short name T385
Test name
Test status
Simulation time 128523413974 ps
CPU time 261.9 seconds
Started Jun 06 12:58:17 PM PDT 24
Finished Jun 06 01:02:41 PM PDT 24
Peak memory 200352 kb
Host smart-6812dbb6-1a34-4f26-a538-50eb0a88fe05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605682733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.3605682733
Directory /workspace/8.uart_tx_rx/latest

Test location /workspace/coverage/default/80.uart_fifo_reset.3031976721
Short name T347
Test name
Test status
Simulation time 551909283868 ps
CPU time 58.14 seconds
Started Jun 06 01:02:20 PM PDT 24
Finished Jun 06 01:03:19 PM PDT 24
Peak memory 200388 kb
Host smart-27e60aa9-184d-412e-b19e-8a184f9c6a70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031976721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.3031976721
Directory /workspace/80.uart_fifo_reset/latest

Test location /workspace/coverage/default/80.uart_stress_all_with_rand_reset.1793677011
Short name T522
Test name
Test status
Simulation time 38723380046 ps
CPU time 202.8 seconds
Started Jun 06 01:02:23 PM PDT 24
Finished Jun 06 01:05:47 PM PDT 24
Peak memory 216896 kb
Host smart-7e1bbe79-726d-4fe4-ba2d-cd947bf86a4c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793677011 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 80.uart_stress_all_with_rand_reset.1793677011
Directory /workspace/80.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/81.uart_fifo_reset.2822590764
Short name T913
Test name
Test status
Simulation time 130118562001 ps
CPU time 122.02 seconds
Started Jun 06 01:02:22 PM PDT 24
Finished Jun 06 01:04:25 PM PDT 24
Peak memory 200388 kb
Host smart-6b10878b-d1d1-4f8a-b96c-ebff6862b1ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822590764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.2822590764
Directory /workspace/81.uart_fifo_reset/latest

Test location /workspace/coverage/default/81.uart_stress_all_with_rand_reset.1801106080
Short name T445
Test name
Test status
Simulation time 17072562150 ps
CPU time 81.52 seconds
Started Jun 06 01:02:23 PM PDT 24
Finished Jun 06 01:03:45 PM PDT 24
Peak memory 216172 kb
Host smart-64049cd2-ef4a-4929-a959-1b0605c55462
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801106080 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 81.uart_stress_all_with_rand_reset.1801106080
Directory /workspace/81.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.uart_fifo_reset.3671700031
Short name T1113
Test name
Test status
Simulation time 44207502685 ps
CPU time 11.16 seconds
Started Jun 06 01:02:22 PM PDT 24
Finished Jun 06 01:02:34 PM PDT 24
Peak memory 200364 kb
Host smart-cb8d63b4-1a89-443c-a990-cc9b85d21dbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671700031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.3671700031
Directory /workspace/82.uart_fifo_reset/latest

Test location /workspace/coverage/default/82.uart_stress_all_with_rand_reset.988831739
Short name T117
Test name
Test status
Simulation time 46184648672 ps
CPU time 660 seconds
Started Jun 06 01:02:23 PM PDT 24
Finished Jun 06 01:13:24 PM PDT 24
Peak memory 217016 kb
Host smart-4bf96268-0d2e-4157-baca-1579d426e836
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988831739 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 82.uart_stress_all_with_rand_reset.988831739
Directory /workspace/82.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/83.uart_fifo_reset.2010572369
Short name T839
Test name
Test status
Simulation time 42983130147 ps
CPU time 80.38 seconds
Started Jun 06 01:02:22 PM PDT 24
Finished Jun 06 01:03:44 PM PDT 24
Peak memory 200272 kb
Host smart-675bd042-01aa-4916-ae04-35d741567759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010572369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.2010572369
Directory /workspace/83.uart_fifo_reset/latest

Test location /workspace/coverage/default/83.uart_stress_all_with_rand_reset.2360863570
Short name T820
Test name
Test status
Simulation time 22879214275 ps
CPU time 343.55 seconds
Started Jun 06 01:02:22 PM PDT 24
Finished Jun 06 01:08:07 PM PDT 24
Peak memory 216684 kb
Host smart-4179f30a-b619-4da2-9952-75bf7bb3062b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360863570 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 83.uart_stress_all_with_rand_reset.2360863570
Directory /workspace/83.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/84.uart_fifo_reset.3648726713
Short name T1010
Test name
Test status
Simulation time 24376320593 ps
CPU time 20.86 seconds
Started Jun 06 01:02:22 PM PDT 24
Finished Jun 06 01:02:44 PM PDT 24
Peak memory 200340 kb
Host smart-6840b441-0c51-4f04-aac7-9061b57867f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648726713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.3648726713
Directory /workspace/84.uart_fifo_reset/latest

Test location /workspace/coverage/default/84.uart_stress_all_with_rand_reset.1025521942
Short name T167
Test name
Test status
Simulation time 336277811575 ps
CPU time 1057.14 seconds
Started Jun 06 01:02:23 PM PDT 24
Finished Jun 06 01:20:01 PM PDT 24
Peak memory 226556 kb
Host smart-05d17612-155d-4615-9c5f-db9d4f60d640
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025521942 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 84.uart_stress_all_with_rand_reset.1025521942
Directory /workspace/84.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.uart_fifo_reset.3722869398
Short name T203
Test name
Test status
Simulation time 22534219689 ps
CPU time 39.75 seconds
Started Jun 06 01:02:23 PM PDT 24
Finished Jun 06 01:03:04 PM PDT 24
Peak memory 200300 kb
Host smart-5913b011-fe06-45f7-8210-47993644eb68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722869398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.3722869398
Directory /workspace/85.uart_fifo_reset/latest

Test location /workspace/coverage/default/85.uart_stress_all_with_rand_reset.3573653885
Short name T1025
Test name
Test status
Simulation time 95682577193 ps
CPU time 380.81 seconds
Started Jun 06 01:02:22 PM PDT 24
Finished Jun 06 01:08:43 PM PDT 24
Peak memory 217124 kb
Host smart-3b557457-e51e-4af7-bb8d-c8a70eae9e1b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573653885 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 85.uart_stress_all_with_rand_reset.3573653885
Directory /workspace/85.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.uart_fifo_reset.3158292677
Short name T328
Test name
Test status
Simulation time 11596892814 ps
CPU time 20.56 seconds
Started Jun 06 01:02:21 PM PDT 24
Finished Jun 06 01:02:43 PM PDT 24
Peak memory 200312 kb
Host smart-769f6198-29b3-4d6b-917f-b1d938b67ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158292677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.3158292677
Directory /workspace/86.uart_fifo_reset/latest

Test location /workspace/coverage/default/86.uart_stress_all_with_rand_reset.4224485546
Short name T471
Test name
Test status
Simulation time 75636835584 ps
CPU time 387.35 seconds
Started Jun 06 01:02:24 PM PDT 24
Finished Jun 06 01:08:53 PM PDT 24
Peak memory 217020 kb
Host smart-15c5f06e-9bb7-4275-a7bb-4c43ee84b6a9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224485546 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 86.uart_stress_all_with_rand_reset.4224485546
Directory /workspace/86.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/87.uart_fifo_reset.3922316922
Short name T1131
Test name
Test status
Simulation time 109962132666 ps
CPU time 52.89 seconds
Started Jun 06 01:02:22 PM PDT 24
Finished Jun 06 01:03:16 PM PDT 24
Peak memory 200348 kb
Host smart-a1df6ef3-df43-442f-a7a9-b38aaafda7e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922316922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.3922316922
Directory /workspace/87.uart_fifo_reset/latest

Test location /workspace/coverage/default/87.uart_stress_all_with_rand_reset.3415958223
Short name T1176
Test name
Test status
Simulation time 707356011361 ps
CPU time 1192.12 seconds
Started Jun 06 01:02:23 PM PDT 24
Finished Jun 06 01:22:17 PM PDT 24
Peak memory 225308 kb
Host smart-d5c4dbd8-32b5-4e09-8a84-17075d1039c9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415958223 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 87.uart_stress_all_with_rand_reset.3415958223
Directory /workspace/87.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/88.uart_fifo_reset.2732500367
Short name T853
Test name
Test status
Simulation time 60808675329 ps
CPU time 57.92 seconds
Started Jun 06 01:02:25 PM PDT 24
Finished Jun 06 01:03:24 PM PDT 24
Peak memory 200324 kb
Host smart-ef67de77-3104-403d-9e7f-94911ade0a10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732500367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.2732500367
Directory /workspace/88.uart_fifo_reset/latest

Test location /workspace/coverage/default/88.uart_stress_all_with_rand_reset.3524606426
Short name T1073
Test name
Test status
Simulation time 237703659094 ps
CPU time 615.72 seconds
Started Jun 06 01:02:22 PM PDT 24
Finished Jun 06 01:12:38 PM PDT 24
Peak memory 229796 kb
Host smart-e8e002a4-ae1f-4711-88f2-e091532a1a71
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524606426 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 88.uart_stress_all_with_rand_reset.3524606426
Directory /workspace/88.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.uart_fifo_reset.2630837459
Short name T1029
Test name
Test status
Simulation time 67307352070 ps
CPU time 57.88 seconds
Started Jun 06 01:02:22 PM PDT 24
Finished Jun 06 01:03:21 PM PDT 24
Peak memory 200272 kb
Host smart-a4a7c59f-7de6-4704-936c-65dba6e33e69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630837459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.2630837459
Directory /workspace/89.uart_fifo_reset/latest

Test location /workspace/coverage/default/89.uart_stress_all_with_rand_reset.2932467077
Short name T65
Test name
Test status
Simulation time 51070587648 ps
CPU time 734.52 seconds
Started Jun 06 01:02:23 PM PDT 24
Finished Jun 06 01:14:39 PM PDT 24
Peak memory 216956 kb
Host smart-492a5fb5-fa12-4993-a2e4-f021b151cb6f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932467077 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 89.uart_stress_all_with_rand_reset.2932467077
Directory /workspace/89.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_alert_test.3420445002
Short name T478
Test name
Test status
Simulation time 18521476 ps
CPU time 0.59 seconds
Started Jun 06 12:58:23 PM PDT 24
Finished Jun 06 12:58:25 PM PDT 24
Peak memory 194980 kb
Host smart-cdc53efe-e79e-4750-94e3-c6a849a71d2a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420445002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.3420445002
Directory /workspace/9.uart_alert_test/latest

Test location /workspace/coverage/default/9.uart_fifo_full.3735289369
Short name T734
Test name
Test status
Simulation time 155698715481 ps
CPU time 125.43 seconds
Started Jun 06 12:58:23 PM PDT 24
Finished Jun 06 01:00:30 PM PDT 24
Peak memory 200336 kb
Host smart-da3b2c81-90f6-4b48-899c-d4e97838cb1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735289369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.3735289369
Directory /workspace/9.uart_fifo_full/latest

Test location /workspace/coverage/default/9.uart_fifo_overflow.727829156
Short name T646
Test name
Test status
Simulation time 69038413146 ps
CPU time 47.73 seconds
Started Jun 06 12:58:23 PM PDT 24
Finished Jun 06 12:59:13 PM PDT 24
Peak memory 200268 kb
Host smart-d811c76f-b960-4ae8-9afc-a64044bb4929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727829156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.727829156
Directory /workspace/9.uart_fifo_overflow/latest

Test location /workspace/coverage/default/9.uart_fifo_reset.1055877302
Short name T800
Test name
Test status
Simulation time 114484841822 ps
CPU time 144.2 seconds
Started Jun 06 12:58:21 PM PDT 24
Finished Jun 06 01:00:46 PM PDT 24
Peak memory 200332 kb
Host smart-720902b5-353b-49ba-970f-4082358e3661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055877302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.1055877302
Directory /workspace/9.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_intr.2976499278
Short name T359
Test name
Test status
Simulation time 427445742864 ps
CPU time 364.05 seconds
Started Jun 06 12:58:22 PM PDT 24
Finished Jun 06 01:04:27 PM PDT 24
Peak memory 199332 kb
Host smart-f4b0e9f8-2e50-48d6-9e2c-f5243e7f3370
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976499278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.2976499278
Directory /workspace/9.uart_intr/latest

Test location /workspace/coverage/default/9.uart_long_xfer_wo_dly.3580404604
Short name T988
Test name
Test status
Simulation time 63793535369 ps
CPU time 169.84 seconds
Started Jun 06 12:58:24 PM PDT 24
Finished Jun 06 01:01:15 PM PDT 24
Peak memory 200300 kb
Host smart-92f15bac-352e-44d0-a00f-ff3a2caee6c1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3580404604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.3580404604
Directory /workspace/9.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/9.uart_loopback.1298483922
Short name T526
Test name
Test status
Simulation time 137374542 ps
CPU time 0.62 seconds
Started Jun 06 12:58:25 PM PDT 24
Finished Jun 06 12:58:27 PM PDT 24
Peak memory 196224 kb
Host smart-da9b8a33-a8d1-4473-8752-a0e45d1b5f96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298483922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_loopback.1298483922
Directory /workspace/9.uart_loopback/latest

Test location /workspace/coverage/default/9.uart_noise_filter.491536957
Short name T1047
Test name
Test status
Simulation time 45775694272 ps
CPU time 21.04 seconds
Started Jun 06 12:58:22 PM PDT 24
Finished Jun 06 12:58:44 PM PDT 24
Peak memory 199184 kb
Host smart-ed5cc6ee-bf04-4f5f-9022-a6b3c9276960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491536957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.491536957
Directory /workspace/9.uart_noise_filter/latest

Test location /workspace/coverage/default/9.uart_perf.2378149812
Short name T372
Test name
Test status
Simulation time 12166693044 ps
CPU time 697.53 seconds
Started Jun 06 12:58:23 PM PDT 24
Finished Jun 06 01:10:02 PM PDT 24
Peak memory 200348 kb
Host smart-f6c8e616-5ff2-41c5-98bd-92b86fde2c17
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2378149812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.2378149812
Directory /workspace/9.uart_perf/latest

Test location /workspace/coverage/default/9.uart_rx_oversample.2402975936
Short name T652
Test name
Test status
Simulation time 1895888935 ps
CPU time 12.09 seconds
Started Jun 06 12:58:29 PM PDT 24
Finished Jun 06 12:58:42 PM PDT 24
Peak memory 198624 kb
Host smart-13ab39ac-5797-4390-b577-2b66656edb7f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2402975936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.2402975936
Directory /workspace/9.uart_rx_oversample/latest

Test location /workspace/coverage/default/9.uart_rx_parity_err.3737172939
Short name T945
Test name
Test status
Simulation time 29867939737 ps
CPU time 62.17 seconds
Started Jun 06 12:58:28 PM PDT 24
Finished Jun 06 12:59:31 PM PDT 24
Peak memory 200344 kb
Host smart-3860abc7-f3cd-4414-99cc-fe9d6c267699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737172939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.3737172939
Directory /workspace/9.uart_rx_parity_err/latest

Test location /workspace/coverage/default/9.uart_rx_start_bit_filter.3633420106
Short name T877
Test name
Test status
Simulation time 43260156702 ps
CPU time 46.55 seconds
Started Jun 06 12:58:20 PM PDT 24
Finished Jun 06 12:59:08 PM PDT 24
Peak memory 196408 kb
Host smart-5e3b6283-f468-4f7c-9605-003f66e9e232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633420106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.3633420106
Directory /workspace/9.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/9.uart_smoke.3199764387
Short name T937
Test name
Test status
Simulation time 5762039936 ps
CPU time 9.27 seconds
Started Jun 06 12:58:19 PM PDT 24
Finished Jun 06 12:58:30 PM PDT 24
Peak memory 200228 kb
Host smart-bd170b8e-667a-491c-86c1-750dbc105909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199764387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_smoke.3199764387
Directory /workspace/9.uart_smoke/latest

Test location /workspace/coverage/default/9.uart_stress_all.1970465546
Short name T753
Test name
Test status
Simulation time 933822159300 ps
CPU time 293.11 seconds
Started Jun 06 12:58:22 PM PDT 24
Finished Jun 06 01:03:16 PM PDT 24
Peak memory 208740 kb
Host smart-fd02eac2-4d3f-495e-9910-213b3ec3c302
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970465546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.1970465546
Directory /workspace/9.uart_stress_all/latest

Test location /workspace/coverage/default/9.uart_stress_all_with_rand_reset.3461312964
Short name T38
Test name
Test status
Simulation time 44121835145 ps
CPU time 554.39 seconds
Started Jun 06 12:58:25 PM PDT 24
Finished Jun 06 01:07:41 PM PDT 24
Peak memory 225204 kb
Host smart-0dae3faf-4d5a-4c62-b735-16fcdc84f3c3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461312964 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 9.uart_stress_all_with_rand_reset.3461312964
Directory /workspace/9.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_tx_ovrd.2558589113
Short name T678
Test name
Test status
Simulation time 6526188679 ps
CPU time 11.75 seconds
Started Jun 06 12:58:22 PM PDT 24
Finished Jun 06 12:58:35 PM PDT 24
Peak memory 200172 kb
Host smart-55a5b690-2dfc-42ff-abed-b36b5bc2bc5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558589113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.2558589113
Directory /workspace/9.uart_tx_ovrd/latest

Test location /workspace/coverage/default/9.uart_tx_rx.2126113922
Short name T1042
Test name
Test status
Simulation time 96243737982 ps
CPU time 76.48 seconds
Started Jun 06 12:58:21 PM PDT 24
Finished Jun 06 12:59:39 PM PDT 24
Peak memory 200268 kb
Host smart-4a2413cb-da0c-4380-833d-97e3c4587aa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126113922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.2126113922
Directory /workspace/9.uart_tx_rx/latest

Test location /workspace/coverage/default/90.uart_fifo_reset.3717767931
Short name T1091
Test name
Test status
Simulation time 27317715206 ps
CPU time 45.29 seconds
Started Jun 06 01:02:25 PM PDT 24
Finished Jun 06 01:03:11 PM PDT 24
Peak memory 200332 kb
Host smart-56ebea83-1859-4224-9c87-0ba74163332d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717767931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.3717767931
Directory /workspace/90.uart_fifo_reset/latest

Test location /workspace/coverage/default/90.uart_stress_all_with_rand_reset.1663563724
Short name T133
Test name
Test status
Simulation time 12939333366 ps
CPU time 146.52 seconds
Started Jun 06 01:02:23 PM PDT 24
Finished Jun 06 01:04:51 PM PDT 24
Peak memory 216264 kb
Host smart-a5ff7bea-9012-43d2-9ab2-89f64fc64c13
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663563724 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 90.uart_stress_all_with_rand_reset.1663563724
Directory /workspace/90.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.uart_fifo_reset.367119889
Short name T786
Test name
Test status
Simulation time 9778664440 ps
CPU time 17.64 seconds
Started Jun 06 01:02:24 PM PDT 24
Finished Jun 06 01:02:42 PM PDT 24
Peak memory 200068 kb
Host smart-72fd790d-3fd0-40e0-be33-ed85804a8ec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367119889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.367119889
Directory /workspace/91.uart_fifo_reset/latest

Test location /workspace/coverage/default/91.uart_stress_all_with_rand_reset.647666763
Short name T1075
Test name
Test status
Simulation time 14012044385 ps
CPU time 272.44 seconds
Started Jun 06 01:02:23 PM PDT 24
Finished Jun 06 01:06:57 PM PDT 24
Peak memory 208632 kb
Host smart-1d738135-370e-4422-9742-07da35718f3e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647666763 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 91.uart_stress_all_with_rand_reset.647666763
Directory /workspace/91.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.uart_fifo_reset.2145246567
Short name T883
Test name
Test status
Simulation time 31603781063 ps
CPU time 20.79 seconds
Started Jun 06 01:02:25 PM PDT 24
Finished Jun 06 01:02:47 PM PDT 24
Peak memory 200248 kb
Host smart-ae3fbbdb-fd6b-4977-861a-a6839814cbd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145246567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.2145246567
Directory /workspace/92.uart_fifo_reset/latest

Test location /workspace/coverage/default/92.uart_stress_all_with_rand_reset.3678208029
Short name T1046
Test name
Test status
Simulation time 99586753085 ps
CPU time 1440.67 seconds
Started Jun 06 01:02:24 PM PDT 24
Finished Jun 06 01:26:26 PM PDT 24
Peak memory 217140 kb
Host smart-0e9e2c3d-50a0-48ca-ba46-2e254f05887c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678208029 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 92.uart_stress_all_with_rand_reset.3678208029
Directory /workspace/92.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/93.uart_fifo_reset.1794627731
Short name T541
Test name
Test status
Simulation time 39788619189 ps
CPU time 18.37 seconds
Started Jun 06 01:02:26 PM PDT 24
Finished Jun 06 01:02:45 PM PDT 24
Peak memory 200368 kb
Host smart-b36e87b8-d99c-4fb6-98e1-067e083d2730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794627731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.1794627731
Directory /workspace/93.uart_fifo_reset/latest

Test location /workspace/coverage/default/94.uart_fifo_reset.704789974
Short name T897
Test name
Test status
Simulation time 86086039487 ps
CPU time 38.28 seconds
Started Jun 06 01:02:26 PM PDT 24
Finished Jun 06 01:03:05 PM PDT 24
Peak memory 200364 kb
Host smart-5b1e6feb-3ab2-4e0d-a69d-4ac617684341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704789974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.704789974
Directory /workspace/94.uart_fifo_reset/latest

Test location /workspace/coverage/default/94.uart_stress_all_with_rand_reset.3754923594
Short name T748
Test name
Test status
Simulation time 22990694890 ps
CPU time 285.3 seconds
Started Jun 06 01:02:22 PM PDT 24
Finished Jun 06 01:07:09 PM PDT 24
Peak memory 216112 kb
Host smart-68e4b93b-11c4-4deb-93ba-e2a39121eec5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754923594 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 94.uart_stress_all_with_rand_reset.3754923594
Directory /workspace/94.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/95.uart_fifo_reset.570548467
Short name T246
Test name
Test status
Simulation time 215741800013 ps
CPU time 35.59 seconds
Started Jun 06 01:02:25 PM PDT 24
Finished Jun 06 01:03:02 PM PDT 24
Peak memory 200372 kb
Host smart-ab791da1-0a61-448d-a78e-631f4e101cb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570548467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.570548467
Directory /workspace/95.uart_fifo_reset/latest

Test location /workspace/coverage/default/95.uart_stress_all_with_rand_reset.463796338
Short name T169
Test name
Test status
Simulation time 87859889205 ps
CPU time 1413.25 seconds
Started Jun 06 01:02:25 PM PDT 24
Finished Jun 06 01:26:00 PM PDT 24
Peak memory 226540 kb
Host smart-429644c3-8a56-4fcd-a58f-26edc947c19f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463796338 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 95.uart_stress_all_with_rand_reset.463796338
Directory /workspace/95.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/96.uart_fifo_reset.2484117242
Short name T699
Test name
Test status
Simulation time 39566540894 ps
CPU time 7.81 seconds
Started Jun 06 01:02:25 PM PDT 24
Finished Jun 06 01:02:34 PM PDT 24
Peak memory 200032 kb
Host smart-e854f9c2-1c0e-4b27-b480-5d4efeb0a693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484117242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.2484117242
Directory /workspace/96.uart_fifo_reset/latest

Test location /workspace/coverage/default/96.uart_stress_all_with_rand_reset.1728688111
Short name T671
Test name
Test status
Simulation time 102164745678 ps
CPU time 265.2 seconds
Started Jun 06 01:02:26 PM PDT 24
Finished Jun 06 01:06:52 PM PDT 24
Peak memory 216816 kb
Host smart-263dc345-0b8b-4ab6-ae1c-7bc28e2d39dc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728688111 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 96.uart_stress_all_with_rand_reset.1728688111
Directory /workspace/96.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.uart_fifo_reset.2981740331
Short name T543
Test name
Test status
Simulation time 9049279470 ps
CPU time 5.26 seconds
Started Jun 06 01:02:26 PM PDT 24
Finished Jun 06 01:02:33 PM PDT 24
Peak memory 200224 kb
Host smart-d13d907b-7cca-4ced-98e6-ede92d54bf33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981740331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.2981740331
Directory /workspace/97.uart_fifo_reset/latest

Test location /workspace/coverage/default/97.uart_stress_all_with_rand_reset.1213408627
Short name T966
Test name
Test status
Simulation time 213415399165 ps
CPU time 1078.18 seconds
Started Jun 06 01:02:25 PM PDT 24
Finished Jun 06 01:20:25 PM PDT 24
Peak memory 227192 kb
Host smart-db6c09fb-c8e4-4e52-8d03-a797d8e02ae4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213408627 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 97.uart_stress_all_with_rand_reset.1213408627
Directory /workspace/97.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/98.uart_fifo_reset.4266700081
Short name T756
Test name
Test status
Simulation time 17389798397 ps
CPU time 13.66 seconds
Started Jun 06 01:02:25 PM PDT 24
Finished Jun 06 01:02:40 PM PDT 24
Peak memory 200180 kb
Host smart-76a3a656-48ca-49fd-8897-9c31c4b39e9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266700081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.4266700081
Directory /workspace/98.uart_fifo_reset/latest

Test location /workspace/coverage/default/98.uart_stress_all_with_rand_reset.1416430045
Short name T61
Test name
Test status
Simulation time 90322113852 ps
CPU time 622.17 seconds
Started Jun 06 01:02:24 PM PDT 24
Finished Jun 06 01:12:48 PM PDT 24
Peak memory 216876 kb
Host smart-0f2eb5a7-8c9f-480a-b8e4-2bdae35b2b0a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416430045 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 98.uart_stress_all_with_rand_reset.1416430045
Directory /workspace/98.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/99.uart_fifo_reset.2172530813
Short name T254
Test name
Test status
Simulation time 102568683900 ps
CPU time 37.04 seconds
Started Jun 06 01:02:28 PM PDT 24
Finished Jun 06 01:03:06 PM PDT 24
Peak memory 200292 kb
Host smart-08436bf1-c0f0-43be-90b6-9dd6bf99e817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172530813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.2172530813
Directory /workspace/99.uart_fifo_reset/latest

Test location /workspace/coverage/default/99.uart_stress_all_with_rand_reset.727591380
Short name T595
Test name
Test status
Simulation time 120031202600 ps
CPU time 750.76 seconds
Started Jun 06 01:02:27 PM PDT 24
Finished Jun 06 01:14:59 PM PDT 24
Peak memory 216856 kb
Host smart-96aba9eb-2459-43a2-9974-4f39c260ad0d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727591380 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 99.uart_stress_all_with_rand_reset.727591380
Directory /workspace/99.uart_stress_all_with_rand_reset/latest
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