Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	98089	1			T1	11		T2	33		T3	46
all_values[1]	98089	1			T1	11		T2	33		T3	46
all_values[2]	98089	1			T1	11		T2	33		T3	46
all_values[3]	98089	1			T1	11		T2	33		T3	46
all_values[4]	98089	1			T1	11		T2	33		T3	46
all_values[5]	98089	1			T1	11		T2	33		T3	46
all_values[6]	98089	1			T1	11		T2	33		T3	46
all_values[7]	98089	1			T1	11		T2	33		T3	46
all_values[8]	98089	1			T1	11		T2	33		T3	46

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

444968

1

T1

71

T2

110

T3

157

auto[1]

437833

1

T1

28

T2

187

T3

257

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

802611

1

T1

82

T2

256

T3

366

auto[1]

80190

1

T1

17

T2

41

T3

48

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	29732	1			T1	3		T2	15		T3	1
all_values[0]	auto[0]	auto[1]	18501	1			T1	8		T2	9		T3	1
all_values[0]	auto[1]	auto[0]	29359	1			T3	25		T6	1		T10	11
all_values[0]	auto[1]	auto[1]	20497	1			T2	9		T3	19		T5	3
all_values[1]	auto[0]	auto[0]	48802	1			T1	4		T2	2		T3	17
all_values[1]	auto[0]	auto[1]	1420	1			T1	7		T3	1		T13	5
all_values[1]	auto[1]	auto[0]	46418	1			T2	31		T3	28		T5	6
all_values[1]	auto[1]	auto[1]	1449	1			T16	9		T118	1		T116	1
all_values[2]	auto[0]	auto[0]	51008	1			T1	10		T2	7		T3	2
all_values[2]	auto[0]	auto[1]	2244	1			T1	1		T2	2		T3	2
all_values[2]	auto[1]	auto[0]	42974	1			T2	22		T3	36		T5	3
all_values[2]	auto[1]	auto[1]	1863	1			T2	2		T3	6		T5	3
all_values[3]	auto[0]	auto[0]	52305	1			T1	3		T2	31		T3	45
all_values[3]	auto[0]	auto[1]	280	1			T13	1		T14	1		T15	1
all_values[3]	auto[1]	auto[0]	45228	1			T1	8		T2	2		T3	1
all_values[3]	auto[1]	auto[1]	276	1			T19	2		T46	1		T47	4
all_values[4]	auto[0]	auto[0]	45817	1			T1	11		T2	9		T3	28
all_values[4]	auto[0]	auto[1]	377	1			T16	3		T18	6		T84	2
all_values[4]	auto[1]	auto[0]	51558	1			T2	24		T3	18		T5	32
all_values[4]	auto[1]	auto[1]	337	1			T19	1		T84	1		T29	4
all_values[5]	auto[0]	auto[0]	48143	1			T1	8		T2	2		T4	2
all_values[5]	auto[0]	auto[1]	157	1			T84	6		T29	9		T36	3
all_values[5]	auto[1]	auto[0]	49628	1			T1	3		T2	31		T3	46
all_values[5]	auto[1]	auto[1]	161	1			T19	2		T84	1		T29	6
all_values[6]	auto[0]	auto[0]	48512	1			T2	31		T3	24		T4	2
all_values[6]	auto[0]	auto[1]	153	1			T19	2		T84	1		T29	7
all_values[6]	auto[1]	auto[0]	49303	1			T1	11		T2	2		T3	22
all_values[6]	auto[1]	auto[1]	121	1			T19	1		T84	3		T29	4
all_values[7]	auto[0]	auto[0]	49519	1			T1	8		T2	1		T3	27
all_values[7]	auto[0]	auto[1]	339	1			T2	1		T25	5		T84	1
all_values[7]	auto[1]	auto[0]	47928	1			T1	3		T2	31		T3	19
all_values[7]	auto[1]	auto[1]	303	1			T25	1		T19	2		T84	1
all_values[8]	auto[0]	auto[0]	31633	1			T1	7		T3	7		T5	3
all_values[8]	auto[0]	auto[1]	16026	1			T1	1		T3	2		T4	2
all_values[8]	auto[1]	auto[0]	34744	1			T1	3		T2	15		T3	20
all_values[8]	auto[1]	auto[1]	15686	1			T2	18		T3	17		T5	26