Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	1963	1			T2	2		T3	2		T5	2
auto[BaudRate115200]	1565	1			T1	1		T3	1		T5	1
auto[BaudRate230400]	1518	1			T1	2		T2	1		T3	1
auto[BaudRate128Kbps]	1545	1			T1	2		T2	1		T3	2
auto[BaudRate256Kbps]	1782	1			T1	3		T2	1		T3	2
auto[BaudRate1Mbps]	1414	1			T2	3		T3	1		T5	1
auto[BaudRate1p5Mbps]	1016	1			T1	1		T2	2		T3	1

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Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	1106	1			T115	7		T21	2		T288	5
freqs[25]	1037	1			T2	10		T16	3		T136	6
freqs[48]	196	1			T5	10		T116	8		T138	9
freqs[50]	488	1			T131	5		T296	2		T146	8
freqs[100]	798	1			T3	10		T8	7		T9	2

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Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	178	1			T115	1		T14	2		T272	1
auto[BaudRate9600]	freqs[25]	211	1			T2	2		T19	10		T266	1
auto[BaudRate9600]	freqs[48]	54	1			T5	2		T333	1		T269	1
auto[BaudRate9600]	freqs[50]	59	1			T146	1		T53	2		T279	1
auto[BaudRate9600]	freqs[100]	129	1			T3	2		T35	1		T133	1
auto[BaudRate115200]	freqs[24]	157	1			T115	1		T14	1		T140	4
auto[BaudRate115200]	freqs[25]	138	1			T16	1		T316	1		T19	2
auto[BaudRate115200]	freqs[48]	20	1			T5	1		T138	3		T346	2
auto[BaudRate115200]	freqs[50]	73	1			T131	1		T296	1		T53	2
auto[BaudRate115200]	freqs[100]	92	1			T3	1		T8	1		T9	1
auto[BaudRate230400]	freqs[24]	169	1			T288	2		T14	3		T290	1
auto[BaudRate230400]	freqs[25]	147	1			T2	1		T136	2		T277	1
auto[BaudRate230400]	freqs[48]	19	1			T5	1		T116	2		T138	2
auto[BaudRate230400]	freqs[50]	66	1			T146	1		T53	1		T274	2
auto[BaudRate230400]	freqs[100]	105	1			T3	1		T8	1		T9	1
auto[BaudRate128Kbps]	freqs[24]	159	1			T115	2		T21	1		T288	1
auto[BaudRate128Kbps]	freqs[25]	156	1			T2	1		T16	2		T136	2
auto[BaudRate128Kbps]	freqs[48]	24	1			T5	2		T116	1		T138	1
auto[BaudRate128Kbps]	freqs[50]	53	1			T131	1		T279	1		T196	1
auto[BaudRate128Kbps]	freqs[100]	112	1			T3	2		T282	2		T263	2
auto[BaudRate256Kbps]	freqs[24]	160	1			T115	1		T14	1		T140	1
auto[BaudRate256Kbps]	freqs[25]	166	1			T2	1		T136	1		T19	12
auto[BaudRate256Kbps]	freqs[48]	26	1			T116	2		T138	1		T269	2
auto[BaudRate256Kbps]	freqs[50]	73	1			T131	1		T296	1		T146	2
auto[BaudRate256Kbps]	freqs[100]	117	1			T3	2		T8	3		T282	1
auto[BaudRate1Mbps]	freqs[24]	192	1			T115	1		T21	1		T288	2
auto[BaudRate1Mbps]	freqs[25]	143	1			T2	3		T277	1		T19	8
auto[BaudRate1Mbps]	freqs[48]	27	1			T5	1		T116	2		T138	2
auto[BaudRate1Mbps]	freqs[50]	80	1			T131	1		T146	1		T279	1
auto[BaudRate1Mbps]	freqs[100]	136	1			T3	1		T8	2		T35	1
auto[BaudRate1p5Mbps]	freqs[25]	76	1			T2	2		T136	1		T316	1
auto[BaudRate1p5Mbps]	freqs[48]	26	1			T5	3		T116	1		T269	2
auto[BaudRate1p5Mbps]	freqs[50]	84	1			T131	1		T146	3		T53	2
auto[BaudRate1p5Mbps]	freqs[100]	107	1			T3	1		T133	1		T135	4

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded