Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	9	0	9	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	98089	1			T1	11		T2	33		T3	46
all_pins[1]	98089	1			T1	11		T2	33		T3	46
all_pins[2]	98089	1			T1	11		T2	33		T3	46
all_pins[3]	98089	1			T1	11		T2	33		T3	46
all_pins[4]	98089	1			T1	11		T2	33		T3	46
all_pins[5]	98089	1			T1	11		T2	33		T3	46
all_pins[6]	98089	1			T1	11		T2	33		T3	46
all_pins[7]	98089	1			T1	11		T2	33		T3	46
all_pins[8]	98089	1			T1	11		T2	33		T3	46

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	841290	1			T1	97		T2	267		T3	370
values[0x1]	41511	1			T1	2		T2	30		T3	44
transitions[0x0=>0x1]	33123	1			T1	2		T2	22		T3	27
transitions[0x1=>0x0]	32904	1			T1	2		T2	21		T3	27

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	77515	1			T1	11		T2	24		T3	27
all_pins[0]	values[0x1]	20574	1			T2	9		T3	19		T5	3
all_pins[0]	transitions[0x0=>0x1]	20047	1			T2	9		T3	19		T5	3
all_pins[0]	transitions[0x1=>0x0]	921	1			T16	9		T118	1		T116	1
all_pins[1]	values[0x0]	96641	1			T1	11		T2	33		T3	46
all_pins[1]	values[0x1]	1448	1			T16	9		T118	1		T116	1
all_pins[1]	transitions[0x0=>0x1]	1342	1			T16	9		T118	1		T116	1
all_pins[1]	transitions[0x1=>0x0]	1813	1			T2	2		T3	6		T5	3
all_pins[2]	values[0x0]	96170	1			T1	11		T2	31		T3	40
all_pins[2]	values[0x1]	1919	1			T2	2		T3	6		T5	3
all_pins[2]	transitions[0x0=>0x1]	1865	1			T2	2		T3	6		T5	3
all_pins[2]	transitions[0x1=>0x0]	222	1			T19	2		T46	1		T47	4
all_pins[3]	values[0x0]	97813	1			T1	11		T2	33		T3	46
all_pins[3]	values[0x1]	276	1			T19	2		T46	1		T47	4
all_pins[3]	transitions[0x0=>0x1]	237	1			T19	2		T46	1		T47	4
all_pins[3]	transitions[0x1=>0x0]	298	1			T19	1		T84	1		T29	4
all_pins[4]	values[0x0]	97752	1			T1	11		T2	33		T3	46
all_pins[4]	values[0x1]	337	1			T19	1		T84	1		T29	4
all_pins[4]	transitions[0x0=>0x1]	282	1			T19	1		T84	1		T29	4
all_pins[4]	transitions[0x1=>0x0]	147	1			T16	1		T18	1		T19	2
all_pins[5]	values[0x0]	97887	1			T1	11		T2	33		T3	46
all_pins[5]	values[0x1]	202	1			T16	1		T18	1		T19	2
all_pins[5]	transitions[0x0=>0x1]	168	1			T16	1		T18	1		T19	1
all_pins[5]	transitions[0x1=>0x0]	665	1			T1	2		T2	1		T3	2
all_pins[6]	values[0x0]	97390	1			T1	9		T2	32		T3	44
all_pins[6]	values[0x1]	699	1			T1	2		T2	1		T3	2
all_pins[6]	transitions[0x0=>0x1]	667	1			T1	2		T2	1		T3	2
all_pins[6]	transitions[0x1=>0x0]	271	1			T25	1		T19	1		T84	1
all_pins[7]	values[0x0]	97786	1			T1	11		T2	33		T3	46
all_pins[7]	values[0x1]	303	1			T25	1		T19	2		T84	1
all_pins[7]	transitions[0x0=>0x1]	175	1			T25	1		T19	2		T84	1
all_pins[7]	transitions[0x1=>0x0]	15625	1			T2	18		T3	17		T5	26
all_pins[8]	values[0x0]	82336	1			T1	11		T2	15		T3	29
all_pins[8]	values[0x1]	15753	1			T2	18		T3	17		T5	26
all_pins[8]	transitions[0x0=>0x1]	8340	1			T2	10		T5	26		T6	13
all_pins[8]	transitions[0x1=>0x0]	12942	1			T3	2		T5	2		T6	2