Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::tx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::tx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	35	0	35	100.00
Crosses	66	0	66	100.00

Variables for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	33	0	33	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tx_fifo_level_cg_cc	66	0	66	100.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	7739776	1			T2	13		T3	59		T5	69
all_levels[1]	1377358	1			T1	5		T3	15		T5	2
all_levels[2]	207217	1			T5	4		T6	3		T10	44
all_levels[3]	286977	1			T2	5		T6	2		T10	42
all_levels[4]	219500	1			T2	1		T6	3		T8	1
all_levels[5]	190744	1			T2	4		T10	46		T267	1217
all_levels[6]	394174	1			T2	7		T6	1		T10	36
all_levels[7]	170124	1			T2	7		T6	2		T10	43
all_levels[8]	303060	1			T2	6		T5	8		T6	2
all_levels[9]	182996	1			T2	10		T10	40		T115	2
all_levels[10]	196237	1			T1	5		T2	12		T6	3
all_levels[11]	194034	1			T2	8		T6	1		T10	43
all_levels[12]	207028	1			T2	6		T6	1		T10	37
all_levels[13]	378495	1			T2	1		T5	3		T6	1
all_levels[14]	162593	1			T2	2		T3	6		T10	41
all_levels[15]	156956	1			T2	1		T6	4		T10	42
all_levels[16]	347914	1			T2	2		T10	50		T13	3
all_levels[17]	232171	1			T2	5		T6	1		T10	45
all_levels[18]	180289	1			T3	2		T10	41		T13	4
all_levels[19]	185045	1			T2	3		T3	2		T6	2
all_levels[20]	169391	1			T10	37		T115	1		T130	18
all_levels[21]	184655	1			T10	42		T130	28		T267	1800
all_levels[22]	301203	1			T2	1		T5	2		T10	45
all_levels[23]	239909	1			T2	2		T10	46		T130	18
all_levels[24]	165927	1			T10	39		T13	6		T130	27
all_levels[25]	426049	1			T3	2		T10	43		T13	2
all_levels[26]	207232	1			T2	1		T3	1		T6	2
all_levels[27]	140927	1			T2	2		T10	38		T115	1
all_levels[28]	146784	1			T6	1		T10	32		T115	1
all_levels[29]	136517	1			T6	2		T10	48		T130	27
all_levels[30]	160477	1			T1	8		T3	2		T6	1
all_levels[31]	431773	1			T10	1056		T267	6252		T116	2185
all_levels[32]	13155212	1			T1	8		T3	72		T6	2

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29174682

1

T1

18

T2

98

T3

151

auto[1]

4062

1

T1

8

T2

1

T3

10

---

Summary for Cross tx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	66	0	66	100.00

Automatically Generated Cross Bins for tx_fifo_level_cg_cc

Bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	7737410	1			T2	13		T3	58		T5	67
all_levels[0]	auto[1]	2366	1			T3	1		T5	2		T6	5
all_levels[1]	auto[0]	1377059	1			T1	3		T3	13		T5	1
all_levels[1]	auto[1]	299	1			T1	2		T3	2		T5	1
all_levels[2]	auto[0]	207189	1			T5	2		T6	3		T10	44
all_levels[2]	auto[1]	28	1			T5	2		T282	1		T138	1
all_levels[3]	auto[0]	286851	1			T2	5		T6	2		T10	42
all_levels[3]	auto[1]	126	1			T271	18		T38	1		T41	1
all_levels[4]	auto[0]	219483	1			T2	1		T6	2		T8	1
all_levels[4]	auto[1]	17	1			T6	1		T138	1		T139	2
all_levels[5]	auto[0]	190726	1			T2	4		T10	46		T267	1217
all_levels[5]	auto[1]	18	1			T150	3		T172	1		T297	1
all_levels[6]	auto[0]	394147	1			T2	7		T6	1		T10	36
all_levels[6]	auto[1]	27	1			T142	1		T45	1		T270	3
all_levels[7]	auto[0]	170003	1			T2	7		T6	2		T10	43
all_levels[7]	auto[1]	121	1			T18	6		T95	3		T145	1
all_levels[8]	auto[0]	303034	1			T2	6		T5	7		T6	2
all_levels[8]	auto[1]	26	1			T5	1		T51	1		T303	1
all_levels[9]	auto[0]	182956	1			T2	10		T10	40		T115	2
all_levels[9]	auto[1]	40	1			T304	1		T166	4		T203	4
all_levels[10]	auto[0]	196220	1			T1	2		T2	12		T6	3
all_levels[10]	auto[1]	17	1			T1	3		T164	2		T347	1
all_levels[11]	auto[0]	194025	1			T2	8		T6	1		T10	43
all_levels[11]	auto[1]	9	1			T130	1		T233	1		T158	1
all_levels[12]	auto[0]	206999	1			T2	6		T6	1		T10	37
all_levels[12]	auto[1]	29	1			T264	1		T164	2		T197	2
all_levels[13]	auto[0]	378476	1			T2	1		T5	1		T6	1
all_levels[13]	auto[1]	19	1			T5	2		T207	1		T338	1
all_levels[14]	auto[0]	162565	1			T2	2		T3	2		T10	41
all_levels[14]	auto[1]	28	1			T3	4		T53	1		T45	1
all_levels[15]	auto[0]	156870	1			T2	1		T6	4		T10	42
all_levels[15]	auto[1]	86	1			T292	1		T263	1		T45	1
all_levels[16]	auto[0]	347900	1			T2	2		T10	50		T13	3
all_levels[16]	auto[1]	14	1			T233	1		T148	2		T307	1
all_levels[17]	auto[0]	232151	1			T2	4		T6	1		T10	45
all_levels[17]	auto[1]	20	1			T2	1		T117	1		T233	1
all_levels[18]	auto[0]	180278	1			T3	2		T10	41		T13	4
all_levels[18]	auto[1]	11	1			T95	1		T304	1		T348	1
all_levels[19]	auto[0]	185033	1			T2	3		T3	2		T6	2
all_levels[19]	auto[1]	12	1			T349	2		T105	1		T232	1
all_levels[20]	auto[0]	169360	1			T10	37		T115	1		T130	18
all_levels[20]	auto[1]	31	1			T155	4		T149	1		T206	2
all_levels[21]	auto[0]	184638	1			T10	42		T130	28		T267	1800
all_levels[21]	auto[1]	17	1			T132	1		T45	1		T181	2
all_levels[22]	auto[0]	301190	1			T2	1		T5	1		T10	45
all_levels[22]	auto[1]	13	1			T5	1		T288	1		T150	1
all_levels[23]	auto[0]	239898	1			T2	2		T10	46		T130	18
all_levels[23]	auto[1]	11	1			T150	1		T350	1		T214	1
all_levels[24]	auto[0]	165910	1			T10	39		T13	2		T130	27
all_levels[24]	auto[1]	17	1			T13	4		T150	1		T46	1
all_levels[25]	auto[0]	426024	1			T3	1		T10	43		T13	2
all_levels[25]	auto[1]	25	1			T3	1		T19	3		T207	1
all_levels[26]	auto[0]	207218	1			T2	1		T3	1		T6	2
all_levels[26]	auto[1]	14	1			T276	1		T317	3		T351	1
all_levels[27]	auto[0]	140907	1			T2	2		T10	38		T115	1
all_levels[27]	auto[1]	20	1			T263	3		T233	1		T264	1
all_levels[28]	auto[0]	146765	1			T6	1		T10	32		T115	1
all_levels[28]	auto[1]	19	1			T274	3		T190	1		T163	2
all_levels[29]	auto[0]	136490	1			T6	2		T10	48		T130	27
all_levels[29]	auto[1]	27	1			T133	1		T150	1		T100	1
all_levels[30]	auto[0]	160473	1			T1	7		T3	2		T6	1
all_levels[30]	auto[1]	4	1			T1	1		T232	1		T352	1
all_levels[31]	auto[0]	431755	1			T10	1056		T267	6252		T116	2185
all_levels[31]	auto[1]	18	1			T142	2		T28	1		T204	1
all_levels[32]	auto[0]	13154679	1			T1	6		T3	70		T6	2
all_levels[32]	auto[1]	533	1			T1	2		T3	2		T8	8