Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.30	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	54	6	48	88.89

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	54	6	48	88.89	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	675	1			T19	7		T84	7		T29	22
all_values[1]	675	1			T19	7		T84	7		T29	22
all_values[2]	675	1			T19	7		T84	7		T29	22
all_values[3]	675	1			T19	7		T84	7		T29	22
all_values[4]	675	1			T19	7		T84	7		T29	22
all_values[5]	675	1			T19	7		T84	7		T29	22
all_values[6]	675	1			T19	7		T84	7		T29	22
all_values[7]	675	1			T19	7		T84	7		T29	22
all_values[8]	675	1			T19	7		T84	7		T29	22

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3287

1

T19

37

T84

44

T29

85

auto[1]

2788

1

T19

26

T84

19

T29

113

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2042

1

T19

22

T84

23

T29

64

auto[1]

4033

1

T19

41

T84

40

T29

134

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3638

1

T19

38

T84

39

T29

119

auto[1]

2437

1

T19

25

T84

24

T29

79

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	54	6	48	88.89	6
Automatically Generated Cross Bins	54	6	48	88.89	6
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	*	[auto[0]]	--	--	2
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2
[all_values[8]]	[auto[0]]	*	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	209	1			T19	3		T84	2		T29	10
all_values[0]	auto[0]	auto[1]	auto[1]	184	1			T19	2		T84	1		T29	4
all_values[0]	auto[1]	auto[0]	auto[1]	146	1			T84	3		T29	2		T109	3
all_values[0]	auto[1]	auto[1]	auto[1]	136	1			T19	2		T84	1		T29	6
all_values[1]	auto[0]	auto[0]	auto[0]	211	1			T19	1		T84	3		T29	1
all_values[1]	auto[0]	auto[1]	auto[0]	175	1			T19	2		T84	1		T29	10
all_values[1]	auto[1]	auto[0]	auto[1]	148	1			T19	3		T84	2		T29	2
all_values[1]	auto[1]	auto[1]	auto[1]	141	1			T19	1		T84	1		T29	9
all_values[2]	auto[0]	auto[0]	auto[0]	152	1			T19	1		T84	1		T29	2
all_values[2]	auto[0]	auto[0]	auto[1]	72	1			T84	2		T29	2		T37	2
all_values[2]	auto[0]	auto[1]	auto[0]	138	1			T19	2		T29	5		T36	2
all_values[2]	auto[0]	auto[1]	auto[1]	65	1			T19	1		T29	1		T109	2
all_values[2]	auto[1]	auto[0]	auto[1]	135	1			T19	2		T84	4		T29	3
all_values[2]	auto[1]	auto[1]	auto[1]	113	1			T19	1		T29	9		T109	1
all_values[3]	auto[0]	auto[0]	auto[0]	154	1			T19	1		T84	5		T29	5
all_values[3]	auto[0]	auto[0]	auto[1]	69	1			T19	1		T29	2		T37	2
all_values[3]	auto[0]	auto[1]	auto[0]	116	1			T84	1		T29	4		T36	1
all_values[3]	auto[0]	auto[1]	auto[1]	71	1			T19	1		T29	1		T109	1
all_values[3]	auto[1]	auto[0]	auto[1]	142	1			T19	2		T84	1		T29	6
all_values[3]	auto[1]	auto[1]	auto[1]	123	1			T19	2		T29	4		T109	2
all_values[4]	auto[0]	auto[0]	auto[0]	148	1			T19	4		T84	4		T29	4
all_values[4]	auto[0]	auto[0]	auto[1]	71	1			T29	1		T109	1		T39	1
all_values[4]	auto[0]	auto[1]	auto[0]	125	1			T19	1		T29	8		T37	3
all_values[4]	auto[0]	auto[1]	auto[1]	57	1			T19	1		T84	1		T29	3
all_values[4]	auto[1]	auto[0]	auto[1]	155	1			T84	2		T29	2		T109	2
all_values[4]	auto[1]	auto[1]	auto[1]	119	1			T19	1		T29	4		T109	1
all_values[5]	auto[0]	auto[0]	auto[0]	150	1			T19	3		T29	3		T109	4
all_values[5]	auto[0]	auto[0]	auto[1]	71	1			T84	4		T29	5		T36	1
all_values[5]	auto[0]	auto[1]	auto[0]	122	1			T19	1		T29	2		T109	1
all_values[5]	auto[0]	auto[1]	auto[1]	66	1			T19	1		T29	2		T37	1
all_values[5]	auto[1]	auto[0]	auto[1]	147	1			T19	1		T84	2		T29	6
all_values[5]	auto[1]	auto[1]	auto[1]	119	1			T19	1		T84	1		T29	4
all_values[6]	auto[0]	auto[0]	auto[0]	174	1			T19	3		T84	1		T29	7
all_values[6]	auto[0]	auto[0]	auto[1]	60	1			T19	1		T29	3		T36	1
all_values[6]	auto[0]	auto[1]	auto[0]	129	1			T19	1		T84	2		T109	4
all_values[6]	auto[0]	auto[1]	auto[1]	44	1			T84	2		T29	1		T39	2
all_values[6]	auto[1]	auto[0]	auto[1]	154	1			T19	1		T84	1		T29	6
all_values[6]	auto[1]	auto[1]	auto[1]	114	1			T19	1		T84	1		T29	5
all_values[7]	auto[0]	auto[0]	auto[0]	114	1			T84	1		T29	3		T36	3
all_values[7]	auto[0]	auto[0]	auto[1]	76	1			T19	1		T36	1		T39	2
all_values[7]	auto[0]	auto[1]	auto[0]	134	1			T19	2		T84	4		T29	10
all_values[7]	auto[0]	auto[1]	auto[1]	66	1			T84	1		T29	3		T36	1
all_values[7]	auto[1]	auto[0]	auto[1]	147	1			T19	2		T29	2		T109	2
all_values[7]	auto[1]	auto[1]	auto[1]	138	1			T19	2		T84	1		T29	4
all_values[8]	auto[0]	auto[0]	auto[1]	238	1			T19	4		T84	3		T29	7
all_values[8]	auto[0]	auto[1]	auto[1]	177	1			T29	10		T109	2		T36	1
all_values[8]	auto[1]	auto[0]	auto[1]	144	1			T19	3		T84	3		T29	1
all_values[8]	auto[1]	auto[1]	auto[1]	116	1			T84	1		T29	4		T37	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal