Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.11 99.10 97.65 100.00 98.38 100.00 99.55


Total test records in report: 1222
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T1032 /workspace/coverage/default/48.uart_rx_parity_err.368452106 Jun 07 07:25:36 PM PDT 24 Jun 07 07:26:42 PM PDT 24 126704646885 ps
T1033 /workspace/coverage/default/27.uart_rx_start_bit_filter.69380949 Jun 07 07:23:07 PM PDT 24 Jun 07 07:23:39 PM PDT 24 46578246747 ps
T1034 /workspace/coverage/default/15.uart_fifo_reset.62439518 Jun 07 07:21:26 PM PDT 24 Jun 07 07:22:59 PM PDT 24 191159646651 ps
T1035 /workspace/coverage/default/10.uart_fifo_full.493319477 Jun 07 07:20:41 PM PDT 24 Jun 07 07:22:09 PM PDT 24 196945638131 ps
T1036 /workspace/coverage/default/7.uart_rx_start_bit_filter.103792758 Jun 07 07:20:18 PM PDT 24 Jun 07 07:20:44 PM PDT 24 3769188853 ps
T1037 /workspace/coverage/default/42.uart_alert_test.16354815 Jun 07 07:25:00 PM PDT 24 Jun 07 07:25:04 PM PDT 24 78852574 ps
T1038 /workspace/coverage/default/20.uart_tx_rx.3887833617 Jun 07 07:21:53 PM PDT 24 Jun 07 07:22:58 PM PDT 24 95556004453 ps
T1039 /workspace/coverage/default/110.uart_fifo_reset.963185623 Jun 07 07:26:22 PM PDT 24 Jun 07 07:26:50 PM PDT 24 46986501857 ps
T1040 /workspace/coverage/default/40.uart_rx_parity_err.2963877093 Jun 07 07:24:39 PM PDT 24 Jun 07 07:30:09 PM PDT 24 126150512771 ps
T1041 /workspace/coverage/default/5.uart_rx_parity_err.369085438 Jun 07 07:20:07 PM PDT 24 Jun 07 07:21:03 PM PDT 24 90223330185 ps
T1042 /workspace/coverage/default/29.uart_alert_test.3454726800 Jun 07 07:23:14 PM PDT 24 Jun 07 07:23:27 PM PDT 24 14621125 ps
T1043 /workspace/coverage/default/49.uart_smoke.411430606 Jun 07 07:25:33 PM PDT 24 Jun 07 07:25:40 PM PDT 24 629958467 ps
T1044 /workspace/coverage/default/32.uart_tx_ovrd.3897552727 Jun 07 07:23:43 PM PDT 24 Jun 07 07:23:55 PM PDT 24 736706924 ps
T1045 /workspace/coverage/default/44.uart_stress_all.2623896745 Jun 07 07:25:08 PM PDT 24 Jun 07 07:29:07 PM PDT 24 142657170659 ps
T1046 /workspace/coverage/default/125.uart_fifo_reset.3894478887 Jun 07 07:26:24 PM PDT 24 Jun 07 07:29:46 PM PDT 24 117333928269 ps
T1047 /workspace/coverage/default/35.uart_tx_ovrd.4038776924 Jun 07 07:24:10 PM PDT 24 Jun 07 07:24:19 PM PDT 24 1258004536 ps
T1048 /workspace/coverage/default/40.uart_stress_all_with_rand_reset.3874039939 Jun 07 07:24:40 PM PDT 24 Jun 07 07:30:56 PM PDT 24 32103072638 ps
T1049 /workspace/coverage/default/42.uart_intr.2450539728 Jun 07 07:24:49 PM PDT 24 Jun 07 07:25:13 PM PDT 24 21509201638 ps
T1050 /workspace/coverage/default/66.uart_stress_all_with_rand_reset.2937480898 Jun 07 07:25:48 PM PDT 24 Jun 07 07:33:55 PM PDT 24 56788057608 ps
T228 /workspace/coverage/default/244.uart_fifo_reset.2173385823 Jun 07 07:27:41 PM PDT 24 Jun 07 07:28:52 PM PDT 24 79802635068 ps
T1051 /workspace/coverage/default/77.uart_fifo_reset.2919485104 Jun 07 07:25:57 PM PDT 24 Jun 07 07:26:52 PM PDT 24 30754429945 ps
T1052 /workspace/coverage/default/152.uart_fifo_reset.2431417727 Jun 07 07:26:38 PM PDT 24 Jun 07 07:27:28 PM PDT 24 150021459667 ps
T1053 /workspace/coverage/default/24.uart_smoke.3701432479 Jun 07 07:22:48 PM PDT 24 Jun 07 07:22:55 PM PDT 24 438624520 ps
T1054 /workspace/coverage/default/34.uart_perf.573739293 Jun 07 07:24:05 PM PDT 24 Jun 07 07:36:27 PM PDT 24 15449751222 ps
T1055 /workspace/coverage/default/40.uart_fifo_overflow.100971107 Jun 07 07:24:42 PM PDT 24 Jun 07 07:26:09 PM PDT 24 106584263808 ps
T1056 /workspace/coverage/default/0.uart_fifo_overflow.302499940 Jun 07 07:19:28 PM PDT 24 Jun 07 07:20:01 PM PDT 24 29492784016 ps
T1057 /workspace/coverage/default/25.uart_loopback.3054995309 Jun 07 07:22:50 PM PDT 24 Jun 07 07:23:03 PM PDT 24 2532927973 ps
T1058 /workspace/coverage/default/38.uart_long_xfer_wo_dly.2342676381 Jun 07 07:24:22 PM PDT 24 Jun 07 07:27:31 PM PDT 24 156779265892 ps
T1059 /workspace/coverage/default/26.uart_rx_oversample.3011281472 Jun 07 07:23:01 PM PDT 24 Jun 07 07:23:24 PM PDT 24 3075905297 ps
T1060 /workspace/coverage/default/1.uart_long_xfer_wo_dly.3525657249 Jun 07 07:19:42 PM PDT 24 Jun 07 07:31:57 PM PDT 24 82313136193 ps
T1061 /workspace/coverage/default/4.uart_fifo_overflow.468360977 Jun 07 07:19:59 PM PDT 24 Jun 07 07:24:15 PM PDT 24 209233279744 ps
T250 /workspace/coverage/default/47.uart_fifo_reset.469170708 Jun 07 07:25:25 PM PDT 24 Jun 07 07:26:37 PM PDT 24 160609682000 ps
T1062 /workspace/coverage/default/12.uart_fifo_full.2198635746 Jun 07 07:20:51 PM PDT 24 Jun 07 07:22:23 PM PDT 24 232035635942 ps
T231 /workspace/coverage/default/48.uart_stress_all_with_rand_reset.1465040983 Jun 07 07:25:34 PM PDT 24 Jun 07 07:46:18 PM PDT 24 1818998996518 ps
T1063 /workspace/coverage/default/27.uart_rx_parity_err.955181840 Jun 07 07:23:02 PM PDT 24 Jun 07 07:23:50 PM PDT 24 95262512890 ps
T1064 /workspace/coverage/default/39.uart_tx_rx.3563525143 Jun 07 07:24:23 PM PDT 24 Jun 07 07:24:30 PM PDT 24 3430837407 ps
T1065 /workspace/coverage/default/5.uart_fifo_full.770420357 Jun 07 07:20:10 PM PDT 24 Jun 07 07:21:22 PM PDT 24 69734937663 ps
T1066 /workspace/coverage/default/198.uart_fifo_reset.968854488 Jun 07 07:27:06 PM PDT 24 Jun 07 07:29:15 PM PDT 24 82889337413 ps
T1067 /workspace/coverage/default/31.uart_long_xfer_wo_dly.331233600 Jun 07 07:23:42 PM PDT 24 Jun 07 07:27:36 PM PDT 24 70592796164 ps
T1068 /workspace/coverage/default/121.uart_fifo_reset.3477186428 Jun 07 07:26:22 PM PDT 24 Jun 07 07:27:18 PM PDT 24 8951052607 ps
T1069 /workspace/coverage/default/37.uart_alert_test.111985491 Jun 07 07:24:22 PM PDT 24 Jun 07 07:24:28 PM PDT 24 13236484 ps
T1070 /workspace/coverage/default/27.uart_tx_rx.1571461856 Jun 07 07:23:05 PM PDT 24 Jun 07 07:23:37 PM PDT 24 38986517514 ps
T1071 /workspace/coverage/default/28.uart_rx_start_bit_filter.2865798687 Jun 07 07:23:10 PM PDT 24 Jun 07 07:23:24 PM PDT 24 2692348770 ps
T1072 /workspace/coverage/default/31.uart_tx_rx.2938340700 Jun 07 07:23:25 PM PDT 24 Jun 07 07:23:54 PM PDT 24 11290817005 ps
T1073 /workspace/coverage/default/190.uart_fifo_reset.1539547885 Jun 07 07:27:05 PM PDT 24 Jun 07 07:31:20 PM PDT 24 132857787164 ps
T1074 /workspace/coverage/default/237.uart_fifo_reset.854119174 Jun 07 07:27:40 PM PDT 24 Jun 07 07:28:26 PM PDT 24 18134565074 ps
T1075 /workspace/coverage/default/45.uart_smoke.2347859504 Jun 07 07:25:08 PM PDT 24 Jun 07 07:25:15 PM PDT 24 497978564 ps
T1076 /workspace/coverage/default/36.uart_loopback.588212348 Jun 07 07:24:15 PM PDT 24 Jun 07 07:24:25 PM PDT 24 1370801913 ps
T1077 /workspace/coverage/default/69.uart_fifo_reset.4145242043 Jun 07 07:25:53 PM PDT 24 Jun 07 07:26:16 PM PDT 24 30948663645 ps
T1078 /workspace/coverage/default/44.uart_smoke.3416454015 Jun 07 07:25:10 PM PDT 24 Jun 07 07:25:36 PM PDT 24 6174402872 ps
T1079 /workspace/coverage/default/22.uart_fifo_reset.210051375 Jun 07 07:22:49 PM PDT 24 Jun 07 07:23:15 PM PDT 24 50091130815 ps
T1080 /workspace/coverage/default/21.uart_smoke.2850598341 Jun 07 07:21:59 PM PDT 24 Jun 07 07:22:27 PM PDT 24 5546038265 ps
T1081 /workspace/coverage/default/41.uart_loopback.414463413 Jun 07 07:24:51 PM PDT 24 Jun 07 07:25:01 PM PDT 24 3198699927 ps
T1082 /workspace/coverage/default/31.uart_stress_all.2958832694 Jun 07 07:23:40 PM PDT 24 Jun 07 07:26:45 PM PDT 24 176444726774 ps
T1083 /workspace/coverage/default/35.uart_smoke.1177490835 Jun 07 07:24:03 PM PDT 24 Jun 07 07:24:15 PM PDT 24 5812804599 ps
T1084 /workspace/coverage/default/36.uart_perf.1770742239 Jun 07 07:24:13 PM PDT 24 Jun 07 07:26:18 PM PDT 24 1871111751 ps
T1085 /workspace/coverage/default/48.uart_long_xfer_wo_dly.4136398744 Jun 07 07:25:34 PM PDT 24 Jun 07 07:32:55 PM PDT 24 200176107500 ps
T1086 /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.2196586411 Jun 07 07:11:27 PM PDT 24 Jun 07 07:11:38 PM PDT 24 23014023 ps
T1087 /workspace/coverage/cover_reg_top/8.uart_tl_errors.2797020712 Jun 07 07:11:25 PM PDT 24 Jun 07 07:11:37 PM PDT 24 90701103 ps
T1088 /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.2004748733 Jun 07 07:11:18 PM PDT 24 Jun 07 07:11:29 PM PDT 24 72276053 ps
T76 /workspace/coverage/cover_reg_top/2.uart_csr_rw.2176180309 Jun 07 07:11:18 PM PDT 24 Jun 07 07:11:29 PM PDT 24 11635513 ps
T59 /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.3182635376 Jun 07 07:11:21 PM PDT 24 Jun 07 07:11:32 PM PDT 24 14483641 ps
T77 /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.3437514237 Jun 07 07:11:37 PM PDT 24 Jun 07 07:11:49 PM PDT 24 78943036 ps
T78 /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.1950339872 Jun 07 07:11:19 PM PDT 24 Jun 07 07:11:30 PM PDT 24 44845089 ps
T1089 /workspace/coverage/cover_reg_top/41.uart_intr_test.998091846 Jun 07 07:11:53 PM PDT 24 Jun 07 07:12:10 PM PDT 24 13615439 ps
T1090 /workspace/coverage/cover_reg_top/40.uart_intr_test.3189490047 Jun 07 07:11:44 PM PDT 24 Jun 07 07:11:59 PM PDT 24 16162929 ps
T79 /workspace/coverage/cover_reg_top/4.uart_csr_rw.703109308 Jun 07 07:11:19 PM PDT 24 Jun 07 07:11:30 PM PDT 24 110000609 ps
T1091 /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.3996135113 Jun 07 07:11:26 PM PDT 24 Jun 07 07:11:38 PM PDT 24 56760207 ps
T1092 /workspace/coverage/cover_reg_top/5.uart_csr_rw.2009973045 Jun 07 07:11:26 PM PDT 24 Jun 07 07:11:36 PM PDT 24 118009874 ps
T1093 /workspace/coverage/cover_reg_top/0.uart_intr_test.901601145 Jun 07 07:11:10 PM PDT 24 Jun 07 07:11:20 PM PDT 24 10875847 ps
T60 /workspace/coverage/cover_reg_top/3.uart_csr_rw.296893524 Jun 07 07:11:17 PM PDT 24 Jun 07 07:11:28 PM PDT 24 13912078 ps
T1094 /workspace/coverage/cover_reg_top/39.uart_intr_test.4117939754 Jun 07 07:11:44 PM PDT 24 Jun 07 07:11:59 PM PDT 24 143975488 ps
T80 /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.2754642421 Jun 07 07:11:35 PM PDT 24 Jun 07 07:11:46 PM PDT 24 14096128 ps
T1095 /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.1122459604 Jun 07 07:11:10 PM PDT 24 Jun 07 07:11:21 PM PDT 24 30643988 ps
T1096 /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.2910756209 Jun 07 07:11:26 PM PDT 24 Jun 07 07:11:37 PM PDT 24 55679609 ps
T1097 /workspace/coverage/cover_reg_top/23.uart_intr_test.3204809034 Jun 07 07:11:37 PM PDT 24 Jun 07 07:11:49 PM PDT 24 15957415 ps
T1098 /workspace/coverage/cover_reg_top/18.uart_intr_test.2880432527 Jun 07 07:11:36 PM PDT 24 Jun 07 07:11:47 PM PDT 24 22531112 ps
T1099 /workspace/coverage/cover_reg_top/13.uart_tl_errors.4204658719 Jun 07 07:11:36 PM PDT 24 Jun 07 07:11:48 PM PDT 24 178715543 ps
T1100 /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.3731119376 Jun 07 07:11:17 PM PDT 24 Jun 07 07:11:28 PM PDT 24 40188910 ps
T86 /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.1878826689 Jun 07 07:11:36 PM PDT 24 Jun 07 07:11:48 PM PDT 24 304166074 ps
T1101 /workspace/coverage/cover_reg_top/30.uart_intr_test.2759179467 Jun 07 07:11:44 PM PDT 24 Jun 07 07:11:59 PM PDT 24 11528315 ps
T1102 /workspace/coverage/cover_reg_top/7.uart_intr_test.1382717832 Jun 07 07:11:26 PM PDT 24 Jun 07 07:11:36 PM PDT 24 10236400 ps
T1103 /workspace/coverage/cover_reg_top/16.uart_tl_errors.3596042929 Jun 07 07:11:37 PM PDT 24 Jun 07 07:11:50 PM PDT 24 286171680 ps
T1104 /workspace/coverage/cover_reg_top/43.uart_intr_test.1584852848 Jun 07 07:11:46 PM PDT 24 Jun 07 07:12:02 PM PDT 24 50287084 ps
T1105 /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.4257637762 Jun 07 07:11:33 PM PDT 24 Jun 07 07:11:44 PM PDT 24 90079563 ps
T87 /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.1156879827 Jun 07 07:11:26 PM PDT 24 Jun 07 07:11:38 PM PDT 24 435251054 ps
T1106 /workspace/coverage/cover_reg_top/4.uart_intr_test.3809676508 Jun 07 07:11:18 PM PDT 24 Jun 07 07:11:29 PM PDT 24 27318331 ps
T81 /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.3782395677 Jun 07 07:11:38 PM PDT 24 Jun 07 07:11:50 PM PDT 24 96770520 ps
T1107 /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.2490044681 Jun 07 07:11:26 PM PDT 24 Jun 07 07:11:37 PM PDT 24 32618142 ps
T1108 /workspace/coverage/cover_reg_top/1.uart_csr_rw.683031209 Jun 07 07:11:19 PM PDT 24 Jun 07 07:11:30 PM PDT 24 101881015 ps
T1109 /workspace/coverage/cover_reg_top/7.uart_tl_errors.2015857332 Jun 07 07:11:27 PM PDT 24 Jun 07 07:11:39 PM PDT 24 247645426 ps
T88 /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.1848257608 Jun 07 07:11:18 PM PDT 24 Jun 07 07:11:29 PM PDT 24 619419640 ps
T1110 /workspace/coverage/cover_reg_top/47.uart_intr_test.210294913 Jun 07 07:11:44 PM PDT 24 Jun 07 07:11:58 PM PDT 24 20243771 ps
T1111 /workspace/coverage/cover_reg_top/36.uart_intr_test.2486766239 Jun 07 07:11:42 PM PDT 24 Jun 07 07:11:55 PM PDT 24 27866402 ps
T1112 /workspace/coverage/cover_reg_top/11.uart_csr_rw.338407163 Jun 07 07:11:39 PM PDT 24 Jun 07 07:11:51 PM PDT 24 46253557 ps
T1113 /workspace/coverage/cover_reg_top/19.uart_intr_test.306908955 Jun 07 07:11:35 PM PDT 24 Jun 07 07:11:45 PM PDT 24 47329737 ps
T1114 /workspace/coverage/cover_reg_top/26.uart_intr_test.461132708 Jun 07 07:11:44 PM PDT 24 Jun 07 07:11:59 PM PDT 24 15349060 ps
T1115 /workspace/coverage/cover_reg_top/6.uart_tl_errors.2068452738 Jun 07 07:11:26 PM PDT 24 Jun 07 07:11:38 PM PDT 24 153123843 ps
T61 /workspace/coverage/cover_reg_top/7.uart_csr_rw.1092696853 Jun 07 07:11:29 PM PDT 24 Jun 07 07:11:41 PM PDT 24 12291680 ps
T1116 /workspace/coverage/cover_reg_top/9.uart_csr_rw.3101760083 Jun 07 07:11:28 PM PDT 24 Jun 07 07:11:38 PM PDT 24 30927916 ps
T1117 /workspace/coverage/cover_reg_top/49.uart_intr_test.2088446757 Jun 07 07:11:43 PM PDT 24 Jun 07 07:11:57 PM PDT 24 27735096 ps
T91 /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.3419473257 Jun 07 07:11:18 PM PDT 24 Jun 07 07:11:29 PM PDT 24 104042619 ps
T1118 /workspace/coverage/cover_reg_top/14.uart_tl_errors.1953377615 Jun 07 07:11:35 PM PDT 24 Jun 07 07:11:48 PM PDT 24 112870219 ps
T125 /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.3381050271 Jun 07 07:11:36 PM PDT 24 Jun 07 07:11:47 PM PDT 24 241159625 ps
T1119 /workspace/coverage/cover_reg_top/14.uart_intr_test.42230877 Jun 07 07:11:35 PM PDT 24 Jun 07 07:11:45 PM PDT 24 12268791 ps
T1120 /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.177967199 Jun 07 07:11:28 PM PDT 24 Jun 07 07:11:39 PM PDT 24 217962373 ps
T82 /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.4279731091 Jun 07 07:11:26 PM PDT 24 Jun 07 07:11:37 PM PDT 24 17984496 ps
T89 /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.257532000 Jun 07 07:11:39 PM PDT 24 Jun 07 07:11:52 PM PDT 24 168408963 ps
T83 /workspace/coverage/cover_reg_top/19.uart_csr_rw.1577073916 Jun 07 07:11:37 PM PDT 24 Jun 07 07:11:48 PM PDT 24 16030310 ps
T1121 /workspace/coverage/cover_reg_top/21.uart_intr_test.2200952013 Jun 07 07:11:32 PM PDT 24 Jun 07 07:11:43 PM PDT 24 47425232 ps
T62 /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.3317424254 Jun 07 07:11:26 PM PDT 24 Jun 07 07:11:37 PM PDT 24 16475221 ps
T90 /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.1646115499 Jun 07 07:11:36 PM PDT 24 Jun 07 07:11:48 PM PDT 24 54790877 ps
T1122 /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.1471646673 Jun 07 07:11:28 PM PDT 24 Jun 07 07:11:39 PM PDT 24 88278936 ps
T1123 /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.1400455847 Jun 07 07:11:17 PM PDT 24 Jun 07 07:11:28 PM PDT 24 37943337 ps
T1124 /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.3496995106 Jun 07 07:11:36 PM PDT 24 Jun 07 07:11:48 PM PDT 24 79585109 ps
T1125 /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.3491151835 Jun 07 07:11:35 PM PDT 24 Jun 07 07:11:46 PM PDT 24 74476132 ps
T1126 /workspace/coverage/cover_reg_top/3.uart_tl_errors.2971720718 Jun 07 07:11:18 PM PDT 24 Jun 07 07:11:31 PM PDT 24 88903895 ps
T92 /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.456819022 Jun 07 07:11:34 PM PDT 24 Jun 07 07:11:45 PM PDT 24 160455086 ps
T1127 /workspace/coverage/cover_reg_top/13.uart_csr_rw.806192312 Jun 07 07:11:34 PM PDT 24 Jun 07 07:11:44 PM PDT 24 43613094 ps
T1128 /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.73095047 Jun 07 07:11:16 PM PDT 24 Jun 07 07:11:27 PM PDT 24 19604518 ps
T1129 /workspace/coverage/cover_reg_top/16.uart_intr_test.137174894 Jun 07 07:11:35 PM PDT 24 Jun 07 07:11:46 PM PDT 24 47606855 ps
T1130 /workspace/coverage/cover_reg_top/24.uart_intr_test.3095534942 Jun 07 07:11:38 PM PDT 24 Jun 07 07:11:49 PM PDT 24 14058038 ps
T1131 /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.4168186786 Jun 07 07:11:26 PM PDT 24 Jun 07 07:11:37 PM PDT 24 66636567 ps
T1132 /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.1420229919 Jun 07 07:11:21 PM PDT 24 Jun 07 07:11:34 PM PDT 24 806688217 ps
T126 /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.3027105279 Jun 07 07:11:24 PM PDT 24 Jun 07 07:11:36 PM PDT 24 198320188 ps
T1133 /workspace/coverage/cover_reg_top/45.uart_intr_test.3733554535 Jun 07 07:11:43 PM PDT 24 Jun 07 07:11:57 PM PDT 24 15394230 ps
T1134 /workspace/coverage/cover_reg_top/12.uart_intr_test.1857390113 Jun 07 07:11:35 PM PDT 24 Jun 07 07:11:46 PM PDT 24 12303565 ps
T1135 /workspace/coverage/cover_reg_top/10.uart_csr_rw.3515218681 Jun 07 07:11:25 PM PDT 24 Jun 07 07:11:36 PM PDT 24 15667535 ps
T1136 /workspace/coverage/cover_reg_top/5.uart_intr_test.156849366 Jun 07 07:11:27 PM PDT 24 Jun 07 07:11:37 PM PDT 24 73329198 ps
T1137 /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.3319005452 Jun 07 07:11:18 PM PDT 24 Jun 07 07:11:29 PM PDT 24 92264636 ps
T1138 /workspace/coverage/cover_reg_top/33.uart_intr_test.3240621897 Jun 07 07:11:46 PM PDT 24 Jun 07 07:12:02 PM PDT 24 16901652 ps
T1139 /workspace/coverage/cover_reg_top/15.uart_csr_rw.3033315744 Jun 07 07:11:34 PM PDT 24 Jun 07 07:11:45 PM PDT 24 27919469 ps
T1140 /workspace/coverage/cover_reg_top/9.uart_tl_errors.1224279364 Jun 07 07:11:28 PM PDT 24 Jun 07 07:11:39 PM PDT 24 34161924 ps
T1141 /workspace/coverage/cover_reg_top/27.uart_intr_test.3674435182 Jun 07 07:11:43 PM PDT 24 Jun 07 07:11:56 PM PDT 24 28489789 ps
T1142 /workspace/coverage/cover_reg_top/38.uart_intr_test.2786363309 Jun 07 07:11:52 PM PDT 24 Jun 07 07:12:09 PM PDT 24 21993746 ps
T1143 /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.994036382 Jun 07 07:11:26 PM PDT 24 Jun 07 07:11:37 PM PDT 24 44937812 ps
T1144 /workspace/coverage/cover_reg_top/15.uart_intr_test.3457427748 Jun 07 07:11:34 PM PDT 24 Jun 07 07:11:45 PM PDT 24 13780002 ps
T127 /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.4128225377 Jun 07 07:11:27 PM PDT 24 Jun 07 07:11:38 PM PDT 24 43046662 ps
T1145 /workspace/coverage/cover_reg_top/18.uart_tl_errors.1144606243 Jun 07 07:11:39 PM PDT 24 Jun 07 07:11:53 PM PDT 24 73271232 ps
T1146 /workspace/coverage/cover_reg_top/37.uart_intr_test.2329937253 Jun 07 07:11:44 PM PDT 24 Jun 07 07:11:59 PM PDT 24 21537950 ps
T1147 /workspace/coverage/cover_reg_top/6.uart_intr_test.2815839701 Jun 07 07:11:25 PM PDT 24 Jun 07 07:11:36 PM PDT 24 17030148 ps
T1148 /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.3514905787 Jun 07 07:11:25 PM PDT 24 Jun 07 07:11:37 PM PDT 24 252768702 ps
T1149 /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.840827591 Jun 07 07:11:24 PM PDT 24 Jun 07 07:11:35 PM PDT 24 19745134 ps
T1150 /workspace/coverage/cover_reg_top/17.uart_tl_errors.859466541 Jun 07 07:11:37 PM PDT 24 Jun 07 07:11:49 PM PDT 24 68488998 ps
T1151 /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.2092711262 Jun 07 07:11:35 PM PDT 24 Jun 07 07:11:46 PM PDT 24 101432922 ps
T1152 /workspace/coverage/cover_reg_top/12.uart_tl_errors.2671178350 Jun 07 07:11:39 PM PDT 24 Jun 07 07:11:53 PM PDT 24 88172079 ps
T1153 /workspace/coverage/cover_reg_top/18.uart_csr_rw.1355304435 Jun 07 07:11:39 PM PDT 24 Jun 07 07:11:51 PM PDT 24 40270866 ps
T1154 /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.3872470917 Jun 07 07:11:36 PM PDT 24 Jun 07 07:11:47 PM PDT 24 176981444 ps
T1155 /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.4240082234 Jun 07 07:11:26 PM PDT 24 Jun 07 07:11:36 PM PDT 24 23678422 ps
T1156 /workspace/coverage/cover_reg_top/17.uart_intr_test.821324630 Jun 07 07:11:36 PM PDT 24 Jun 07 07:11:47 PM PDT 24 18019185 ps
T1157 /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.3868166555 Jun 07 07:11:18 PM PDT 24 Jun 07 07:11:29 PM PDT 24 52183602 ps
T1158 /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.4287075383 Jun 07 07:11:27 PM PDT 24 Jun 07 07:11:38 PM PDT 24 54195359 ps
T1159 /workspace/coverage/cover_reg_top/11.uart_tl_errors.614663492 Jun 07 07:11:24 PM PDT 24 Jun 07 07:11:35 PM PDT 24 261295641 ps
T1160 /workspace/coverage/cover_reg_top/8.uart_intr_test.805410131 Jun 07 07:11:25 PM PDT 24 Jun 07 07:11:36 PM PDT 24 14316724 ps
T1161 /workspace/coverage/cover_reg_top/28.uart_intr_test.2138555551 Jun 07 07:11:44 PM PDT 24 Jun 07 07:11:58 PM PDT 24 65336385 ps
T1162 /workspace/coverage/cover_reg_top/29.uart_intr_test.2238153551 Jun 07 07:11:48 PM PDT 24 Jun 07 07:12:03 PM PDT 24 54591171 ps
T128 /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.703282487 Jun 07 07:11:39 PM PDT 24 Jun 07 07:11:52 PM PDT 24 164113010 ps
T1163 /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.159033986 Jun 07 07:11:34 PM PDT 24 Jun 07 07:11:44 PM PDT 24 139723657 ps
T1164 /workspace/coverage/cover_reg_top/17.uart_csr_rw.2710827939 Jun 07 07:11:37 PM PDT 24 Jun 07 07:11:49 PM PDT 24 40749345 ps
T1165 /workspace/coverage/cover_reg_top/1.uart_intr_test.2611383061 Jun 07 07:11:26 PM PDT 24 Jun 07 07:11:37 PM PDT 24 13197280 ps
T1166 /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.1644645238 Jun 07 07:11:29 PM PDT 24 Jun 07 07:11:39 PM PDT 24 62258564 ps
T1167 /workspace/coverage/cover_reg_top/5.uart_tl_errors.3987701683 Jun 07 07:11:27 PM PDT 24 Jun 07 07:11:38 PM PDT 24 57180759 ps
T1168 /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.3819217564 Jun 07 07:11:18 PM PDT 24 Jun 07 07:11:29 PM PDT 24 18819366 ps
T1169 /workspace/coverage/cover_reg_top/20.uart_intr_test.388706587 Jun 07 07:11:36 PM PDT 24 Jun 07 07:11:48 PM PDT 24 102084670 ps
T63 /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.679620617 Jun 07 07:11:17 PM PDT 24 Jun 07 07:11:28 PM PDT 24 37074346 ps
T1170 /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.1644303158 Jun 07 07:11:35 PM PDT 24 Jun 07 07:11:46 PM PDT 24 20397726 ps
T1171 /workspace/coverage/cover_reg_top/44.uart_intr_test.2589149643 Jun 07 07:11:46 PM PDT 24 Jun 07 07:12:02 PM PDT 24 13036509 ps
T1172 /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.94341016 Jun 07 07:11:27 PM PDT 24 Jun 07 07:11:38 PM PDT 24 87216827 ps
T1173 /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.3712236075 Jun 07 07:11:28 PM PDT 24 Jun 07 07:11:39 PM PDT 24 90100982 ps
T1174 /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.1405790709 Jun 07 07:11:38 PM PDT 24 Jun 07 07:11:51 PM PDT 24 47146062 ps
T1175 /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.1391308135 Jun 07 07:11:38 PM PDT 24 Jun 07 07:11:50 PM PDT 24 27080984 ps
T1176 /workspace/coverage/cover_reg_top/14.uart_csr_rw.2445475078 Jun 07 07:11:36 PM PDT 24 Jun 07 07:11:48 PM PDT 24 24522210 ps
T1177 /workspace/coverage/cover_reg_top/42.uart_intr_test.1852424948 Jun 07 07:11:44 PM PDT 24 Jun 07 07:11:59 PM PDT 24 13773267 ps
T1178 /workspace/coverage/cover_reg_top/16.uart_csr_rw.3905716033 Jun 07 07:11:39 PM PDT 24 Jun 07 07:11:51 PM PDT 24 44512789 ps
T1179 /workspace/coverage/cover_reg_top/46.uart_intr_test.1692291803 Jun 07 07:11:42 PM PDT 24 Jun 07 07:11:56 PM PDT 24 16087314 ps
T129 /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.1613468050 Jun 07 07:11:37 PM PDT 24 Jun 07 07:11:50 PM PDT 24 146143304 ps
T1180 /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.631358859 Jun 07 07:11:39 PM PDT 24 Jun 07 07:11:52 PM PDT 24 293677191 ps
T1181 /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.3396217843 Jun 07 07:11:23 PM PDT 24 Jun 07 07:11:34 PM PDT 24 30000431 ps
T1182 /workspace/coverage/cover_reg_top/34.uart_intr_test.166154215 Jun 07 07:11:50 PM PDT 24 Jun 07 07:12:06 PM PDT 24 36242153 ps
T1183 /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.3429034547 Jun 07 07:11:35 PM PDT 24 Jun 07 07:11:46 PM PDT 24 29387027 ps
T1184 /workspace/coverage/cover_reg_top/25.uart_intr_test.2547126245 Jun 07 07:11:41 PM PDT 24 Jun 07 07:11:54 PM PDT 24 53537187 ps
T1185 /workspace/coverage/cover_reg_top/0.uart_tl_errors.447498296 Jun 07 07:11:10 PM PDT 24 Jun 07 07:11:22 PM PDT 24 117133661 ps
T1186 /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.1258703423 Jun 07 07:11:39 PM PDT 24 Jun 07 07:11:51 PM PDT 24 43959234 ps
T1187 /workspace/coverage/cover_reg_top/22.uart_intr_test.2373568626 Jun 07 07:11:41 PM PDT 24 Jun 07 07:11:54 PM PDT 24 86459497 ps
T65 /workspace/coverage/cover_reg_top/8.uart_csr_rw.11165023 Jun 07 07:11:26 PM PDT 24 Jun 07 07:11:37 PM PDT 24 64109318 ps
T64 /workspace/coverage/cover_reg_top/0.uart_csr_rw.377193121 Jun 07 07:11:18 PM PDT 24 Jun 07 07:11:29 PM PDT 24 48796212 ps
T1188 /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.1799589811 Jun 07 07:11:39 PM PDT 24 Jun 07 07:11:52 PM PDT 24 30475153 ps
T1189 /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.933440588 Jun 07 07:11:29 PM PDT 24 Jun 07 07:11:40 PM PDT 24 229004987 ps
T1190 /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.3541595832 Jun 07 07:11:24 PM PDT 24 Jun 07 07:11:35 PM PDT 24 62450051 ps
T1191 /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.2874199784 Jun 07 07:11:34 PM PDT 24 Jun 07 07:11:45 PM PDT 24 22732823 ps
T1192 /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.1046436172 Jun 07 07:11:16 PM PDT 24 Jun 07 07:11:28 PM PDT 24 101921732 ps
T66 /workspace/coverage/cover_reg_top/6.uart_csr_rw.678238518 Jun 07 07:11:27 PM PDT 24 Jun 07 07:11:38 PM PDT 24 15201533 ps
T1193 /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.1053486080 Jun 07 07:11:26 PM PDT 24 Jun 07 07:11:37 PM PDT 24 334242067 ps
T1194 /workspace/coverage/cover_reg_top/15.uart_tl_errors.425334787 Jun 07 07:11:36 PM PDT 24 Jun 07 07:11:49 PM PDT 24 158598648 ps
T1195 /workspace/coverage/cover_reg_top/19.uart_tl_errors.2477362994 Jun 07 07:11:36 PM PDT 24 Jun 07 07:11:48 PM PDT 24 338239701 ps
T1196 /workspace/coverage/cover_reg_top/2.uart_intr_test.3115825321 Jun 07 07:11:17 PM PDT 24 Jun 07 07:11:28 PM PDT 24 54304815 ps
T1197 /workspace/coverage/cover_reg_top/13.uart_intr_test.601184712 Jun 07 07:11:34 PM PDT 24 Jun 07 07:11:44 PM PDT 24 14064200 ps
T1198 /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.3852412858 Jun 07 07:11:36 PM PDT 24 Jun 07 07:11:48 PM PDT 24 30782279 ps
T1199 /workspace/coverage/cover_reg_top/35.uart_intr_test.3874211489 Jun 07 07:11:43 PM PDT 24 Jun 07 07:11:56 PM PDT 24 17377315 ps
T1200 /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.733231271 Jun 07 07:11:26 PM PDT 24 Jun 07 07:11:37 PM PDT 24 74527580 ps
T1201 /workspace/coverage/cover_reg_top/10.uart_tl_errors.891168373 Jun 07 07:11:27 PM PDT 24 Jun 07 07:11:39 PM PDT 24 35398582 ps
T1202 /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.315830548 Jun 07 07:11:35 PM PDT 24 Jun 07 07:11:45 PM PDT 24 84703996 ps
T1203 /workspace/coverage/cover_reg_top/48.uart_intr_test.1667930080 Jun 07 07:11:46 PM PDT 24 Jun 07 07:12:01 PM PDT 24 36325872 ps
T1204 /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.918827955 Jun 07 07:11:19 PM PDT 24 Jun 07 07:11:31 PM PDT 24 102602850 ps
T1205 /workspace/coverage/cover_reg_top/32.uart_intr_test.4232437532 Jun 07 07:11:46 PM PDT 24 Jun 07 07:12:02 PM PDT 24 41758003 ps
T1206 /workspace/coverage/cover_reg_top/1.uart_tl_errors.1147146256 Jun 07 07:11:16 PM PDT 24 Jun 07 07:11:28 PM PDT 24 73255372 ps
T1207 /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.3705417613 Jun 07 07:11:19 PM PDT 24 Jun 07 07:11:30 PM PDT 24 22613972 ps
T1208 /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.3568428125 Jun 07 07:11:17 PM PDT 24 Jun 07 07:11:29 PM PDT 24 405588528 ps
T1209 /workspace/coverage/cover_reg_top/9.uart_intr_test.2082734706 Jun 07 07:11:26 PM PDT 24 Jun 07 07:11:37 PM PDT 24 64308344 ps
T1210 /workspace/coverage/cover_reg_top/31.uart_intr_test.2439481346 Jun 07 07:11:44 PM PDT 24 Jun 07 07:11:58 PM PDT 24 17559185 ps
T1211 /workspace/coverage/cover_reg_top/10.uart_intr_test.295872413 Jun 07 07:11:29 PM PDT 24 Jun 07 07:11:40 PM PDT 24 43060808 ps
T1212 /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.3346581243 Jun 07 07:11:19 PM PDT 24 Jun 07 07:11:31 PM PDT 24 175859650 ps
T1213 /workspace/coverage/cover_reg_top/3.uart_intr_test.3026011666 Jun 07 07:11:15 PM PDT 24 Jun 07 07:11:26 PM PDT 24 39355911 ps
T1214 /workspace/coverage/cover_reg_top/4.uart_tl_errors.3967621866 Jun 07 07:11:19 PM PDT 24 Jun 07 07:11:32 PM PDT 24 184631047 ps
T1215 /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.738396904 Jun 07 07:11:16 PM PDT 24 Jun 07 07:11:27 PM PDT 24 15540558 ps
T1216 /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.2859806832 Jun 07 07:11:17 PM PDT 24 Jun 07 07:11:29 PM PDT 24 91764291 ps
T1217 /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.4179682725 Jun 07 07:11:10 PM PDT 24 Jun 07 07:11:21 PM PDT 24 340553549 ps
T1218 /workspace/coverage/cover_reg_top/11.uart_intr_test.3186986123 Jun 07 07:11:35 PM PDT 24 Jun 07 07:11:46 PM PDT 24 14953555 ps
T1219 /workspace/coverage/cover_reg_top/2.uart_tl_errors.3384686690 Jun 07 07:11:19 PM PDT 24 Jun 07 07:11:30 PM PDT 24 32830926 ps
T1220 /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.365585516 Jun 07 07:11:36 PM PDT 24 Jun 07 07:11:47 PM PDT 24 260678126 ps
T1221 /workspace/coverage/cover_reg_top/12.uart_csr_rw.3055559706 Jun 07 07:11:38 PM PDT 24 Jun 07 07:11:49 PM PDT 24 14178114 ps
T1222 /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.3241339637 Jun 07 07:11:18 PM PDT 24 Jun 07 07:11:29 PM PDT 24 27923545 ps

Test location /workspace/coverage/default/29.uart_long_xfer_wo_dly.1123474325
Short name T10
Test name
Test status
Simulation time 151149293121 ps
CPU time 344.24 seconds
Started Jun 07 07:23:15 PM PDT 24
Finished Jun 07 07:29:12 PM PDT 24
Peak memory 200420 kb
Host smart-e777cc4d-8959-44b1-a1fa-556f8ae62cad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1123474325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.1123474325
Directory /workspace/29.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/19.uart_intr.1719572533
Short name T16
Test name
Test status
Simulation time 27861796853 ps
CPU time 12.46 seconds
Started Jun 07 07:21:44 PM PDT 24
Finished Jun 07 07:22:08 PM PDT 24
Peak memory 199936 kb
Host smart-82512140-1b26-471e-8445-52d8fc77f1f0
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719572533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.1719572533
Directory /workspace/19.uart_intr/latest

Test location /workspace/coverage/default/59.uart_stress_all_with_rand_reset.3152431085
Short name T27
Test name
Test status
Simulation time 120687976377 ps
CPU time 1510.99 seconds
Started Jun 07 07:25:49 PM PDT 24
Finished Jun 07 07:51:05 PM PDT 24
Peak memory 229048 kb
Host smart-2feedb69-d7a6-4830-8bd0-7b303fb5ad98
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152431085 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 59.uart_stress_all_with_rand_reset.3152431085
Directory /workspace/59.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.uart_stress_all_with_rand_reset.4005490561
Short name T28
Test name
Test status
Simulation time 517038067264 ps
CPU time 695.81 seconds
Started Jun 07 07:23:41 PM PDT 24
Finished Jun 07 07:35:26 PM PDT 24
Peak memory 213520 kb
Host smart-94f57d22-65cb-47e0-8e42-208d3935c926
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005490561 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 31.uart_stress_all_with_rand_reset.4005490561
Directory /workspace/31.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.uart_stress_all.4033093562
Short name T19
Test name
Test status
Simulation time 236296589135 ps
CPU time 224.37 seconds
Started Jun 07 07:23:42 PM PDT 24
Finished Jun 07 07:27:37 PM PDT 24
Peak memory 200424 kb
Host smart-281d6aea-096e-4741-910d-11e26d6d4391
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033093562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.4033093562
Directory /workspace/32.uart_stress_all/latest

Test location /workspace/coverage/default/33.uart_fifo_full.3345362743
Short name T118
Test name
Test status
Simulation time 123956658298 ps
CPU time 42.75 seconds
Started Jun 07 07:23:50 PM PDT 24
Finished Jun 07 07:24:42 PM PDT 24
Peak memory 200388 kb
Host smart-bda5ded3-0cc6-4ca6-b759-304050d23f15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345362743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.3345362743
Directory /workspace/33.uart_fifo_full/latest

Test location /workspace/coverage/default/2.uart_stress_all_with_rand_reset.49483505
Short name T40
Test name
Test status
Simulation time 157189281440 ps
CPU time 952.11 seconds
Started Jun 07 07:19:48 PM PDT 24
Finished Jun 07 07:36:04 PM PDT 24
Peak memory 217008 kb
Host smart-7d6e872d-39d9-4dfe-b92e-6ab1ae78628f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49483505 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 2.uart_stress_all_with_rand_reset.49483505
Directory /workspace/2.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.uart_stress_all.871286905
Short name T221
Test name
Test status
Simulation time 402633764652 ps
CPU time 1082.18 seconds
Started Jun 07 07:25:24 PM PDT 24
Finished Jun 07 07:43:31 PM PDT 24
Peak memory 200364 kb
Host smart-c6bdd533-fffb-4f60-ab9d-c44d45979012
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871286905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.871286905
Directory /workspace/47.uart_stress_all/latest

Test location /workspace/coverage/default/37.uart_fifo_overflow.96769398
Short name T152
Test name
Test status
Simulation time 45898933172 ps
CPU time 72.8 seconds
Started Jun 07 07:24:12 PM PDT 24
Finished Jun 07 07:25:31 PM PDT 24
Peak memory 200396 kb
Host smart-603b72ba-45b2-4c7d-a379-3dc0a1041bb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96769398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.96769398
Directory /workspace/37.uart_fifo_overflow/latest

Test location /workspace/coverage/default/3.uart_sec_cm.2652167923
Short name T30
Test name
Test status
Simulation time 59345166 ps
CPU time 0.87 seconds
Started Jun 07 07:20:00 PM PDT 24
Finished Jun 07 07:20:25 PM PDT 24
Peak memory 218704 kb
Host smart-9c95be2d-038e-4b62-9a6b-20a7e6d7cefc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652167923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.2652167923
Directory /workspace/3.uart_sec_cm/latest

Test location /workspace/coverage/default/11.uart_intr.4054695275
Short name T280
Test name
Test status
Simulation time 55384475066 ps
CPU time 31.87 seconds
Started Jun 07 07:20:52 PM PDT 24
Finished Jun 07 07:21:35 PM PDT 24
Peak memory 200348 kb
Host smart-8dcda5eb-db56-47e3-a13c-2a208507bc80
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054695275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.4054695275
Directory /workspace/11.uart_intr/latest

Test location /workspace/coverage/default/46.uart_stress_all.887170547
Short name T72
Test name
Test status
Simulation time 275662263016 ps
CPU time 367.83 seconds
Started Jun 07 07:25:19 PM PDT 24
Finished Jun 07 07:31:34 PM PDT 24
Peak memory 200368 kb
Host smart-9aabae53-1065-4f76-a3e4-47fd07ce2b85
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887170547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.887170547
Directory /workspace/46.uart_stress_all/latest

Test location /workspace/coverage/default/17.uart_fifo_reset.2411543644
Short name T5
Test name
Test status
Simulation time 74382472702 ps
CPU time 63.96 seconds
Started Jun 07 07:21:37 PM PDT 24
Finished Jun 07 07:22:52 PM PDT 24
Peak memory 200300 kb
Host smart-531be9fb-b5e0-4aa2-9451-4b36858e8e11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411543644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.2411543644
Directory /workspace/17.uart_fifo_reset/latest

Test location /workspace/coverage/default/71.uart_stress_all_with_rand_reset.3039586173
Short name T337
Test name
Test status
Simulation time 561840580886 ps
CPU time 679.95 seconds
Started Jun 07 07:25:57 PM PDT 24
Finished Jun 07 07:37:21 PM PDT 24
Peak memory 216528 kb
Host smart-d0ad02b0-fbdf-4dca-8631-4b1fb759da2b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039586173 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 71.uart_stress_all_with_rand_reset.3039586173
Directory /workspace/71.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.uart_intr.1953254368
Short name T123
Test name
Test status
Simulation time 34154840472 ps
CPU time 33.19 seconds
Started Jun 07 07:22:59 PM PDT 24
Finished Jun 07 07:23:42 PM PDT 24
Peak memory 200324 kb
Host smart-835fcf10-eba1-44c2-976e-3e594aeb8fe1
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953254368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.1953254368
Directory /workspace/26.uart_intr/latest

Test location /workspace/coverage/default/59.uart_fifo_reset.3546825870
Short name T181
Test name
Test status
Simulation time 165815743505 ps
CPU time 271.6 seconds
Started Jun 07 07:25:48 PM PDT 24
Finished Jun 07 07:30:25 PM PDT 24
Peak memory 200340 kb
Host smart-c67772b3-d55f-49d7-b598-2d149903ec6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546825870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.3546825870
Directory /workspace/59.uart_fifo_reset/latest

Test location /workspace/coverage/default/77.uart_stress_all_with_rand_reset.3371328823
Short name T36
Test name
Test status
Simulation time 57222633292 ps
CPU time 297.51 seconds
Started Jun 07 07:26:06 PM PDT 24
Finished Jun 07 07:31:08 PM PDT 24
Peak memory 216996 kb
Host smart-a9fd4c36-7cea-4d85-bea3-c07ac38eb066
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371328823 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 77.uart_stress_all_with_rand_reset.3371328823
Directory /workspace/77.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.uart_long_xfer_wo_dly.2185681363
Short name T326
Test name
Test status
Simulation time 89953058315 ps
CPU time 446.65 seconds
Started Jun 07 07:23:47 PM PDT 24
Finished Jun 07 07:31:24 PM PDT 24
Peak memory 200328 kb
Host smart-928e7335-011a-4658-bda4-23ac2a4dbabd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2185681363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.2185681363
Directory /workspace/33.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/15.uart_fifo_full.2932454111
Short name T140
Test name
Test status
Simulation time 105006608458 ps
CPU time 45.71 seconds
Started Jun 07 07:21:25 PM PDT 24
Finished Jun 07 07:22:19 PM PDT 24
Peak memory 200308 kb
Host smart-4424047b-e4a7-4019-b2b6-eb123e73ead0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932454111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.2932454111
Directory /workspace/15.uart_fifo_full/latest

Test location /workspace/coverage/default/33.uart_fifo_reset.2848773203
Short name T47
Test name
Test status
Simulation time 126669457636 ps
CPU time 58.01 seconds
Started Jun 07 07:23:48 PM PDT 24
Finished Jun 07 07:24:55 PM PDT 24
Peak memory 200332 kb
Host smart-970db721-ae99-49c9-871e-ab408ff5a58c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848773203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.2848773203
Directory /workspace/33.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.1848257608
Short name T88
Test name
Test status
Simulation time 619419640 ps
CPU time 1.01 seconds
Started Jun 07 07:11:18 PM PDT 24
Finished Jun 07 07:11:29 PM PDT 24
Peak memory 199960 kb
Host smart-0bc5b645-5a78-4c3a-a19f-a6f59087f942
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848257608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.1848257608
Directory /workspace/4.uart_tl_intg_err/latest

Test location /workspace/coverage/default/44.uart_rx_parity_err.1918735285
Short name T149
Test name
Test status
Simulation time 180480180580 ps
CPU time 38.78 seconds
Started Jun 07 07:25:14 PM PDT 24
Finished Jun 07 07:26:00 PM PDT 24
Peak memory 200320 kb
Host smart-30215fcc-a6f9-4ecc-b1f6-a1a638b867fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918735285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.1918735285
Directory /workspace/44.uart_rx_parity_err/latest

Test location /workspace/coverage/default/85.uart_fifo_reset.2629935318
Short name T274
Test name
Test status
Simulation time 215835054151 ps
CPU time 515.53 seconds
Started Jun 07 07:26:06 PM PDT 24
Finished Jun 07 07:34:46 PM PDT 24
Peak memory 200404 kb
Host smart-26ad03bb-1ef8-4e6c-927c-7cc929343ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629935318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.2629935318
Directory /workspace/85.uart_fifo_reset/latest

Test location /workspace/coverage/default/1.uart_alert_test.295452105
Short name T32
Test name
Test status
Simulation time 21143579 ps
CPU time 0.59 seconds
Started Jun 07 07:19:42 PM PDT 24
Finished Jun 07 07:20:04 PM PDT 24
Peak memory 196024 kb
Host smart-08dc23d2-96b1-4094-bb53-60efec8358dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295452105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.295452105
Directory /workspace/1.uart_alert_test/latest

Test location /workspace/coverage/default/120.uart_fifo_reset.2016998931
Short name T45
Test name
Test status
Simulation time 53222749176 ps
CPU time 136.69 seconds
Started Jun 07 07:26:22 PM PDT 24
Finished Jun 07 07:28:45 PM PDT 24
Peak memory 200400 kb
Host smart-2522c8a5-d685-4eaf-a294-ec360c9f122e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016998931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.2016998931
Directory /workspace/120.uart_fifo_reset/latest

Test location /workspace/coverage/default/67.uart_stress_all_with_rand_reset.3296812337
Short name T42
Test name
Test status
Simulation time 241400528385 ps
CPU time 651.87 seconds
Started Jun 07 07:25:49 PM PDT 24
Finished Jun 07 07:36:47 PM PDT 24
Peak memory 216824 kb
Host smart-4058a542-0a70-491b-92dc-2fe64482c8ac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296812337 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 67.uart_stress_all_with_rand_reset.3296812337
Directory /workspace/67.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.uart_fifo_reset.2358429850
Short name T164
Test name
Test status
Simulation time 143466475812 ps
CPU time 94.93 seconds
Started Jun 07 07:21:46 PM PDT 24
Finished Jun 07 07:23:33 PM PDT 24
Peak memory 200368 kb
Host smart-16d19f20-d23b-40dc-89e3-8005d649fb4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358429850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.2358429850
Directory /workspace/19.uart_fifo_reset/latest

Test location /workspace/coverage/default/42.uart_fifo_overflow.136534001
Short name T136
Test name
Test status
Simulation time 35331889100 ps
CPU time 19.21 seconds
Started Jun 07 07:24:52 PM PDT 24
Finished Jun 07 07:25:17 PM PDT 24
Peak memory 200240 kb
Host smart-79e64e39-4f2a-4706-a8fc-77e24a5412b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136534001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.136534001
Directory /workspace/42.uart_fifo_overflow/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_rw.377193121
Short name T64
Test name
Test status
Simulation time 48796212 ps
CPU time 0.6 seconds
Started Jun 07 07:11:18 PM PDT 24
Finished Jun 07 07:11:29 PM PDT 24
Peak memory 196120 kb
Host smart-e34fa3b0-beb6-4fbc-b7dd-56fc33a7cee1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377193121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.377193121
Directory /workspace/0.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.1950339872
Short name T78
Test name
Test status
Simulation time 44845089 ps
CPU time 0.77 seconds
Started Jun 07 07:11:19 PM PDT 24
Finished Jun 07 07:11:30 PM PDT 24
Peak memory 197760 kb
Host smart-c77c93bc-ca15-4a0e-9676-7007d7146027
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950339872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr
_outstanding.1950339872
Directory /workspace/0.uart_same_csr_outstanding/latest

Test location /workspace/coverage/default/60.uart_fifo_reset.2989706143
Short name T150
Test name
Test status
Simulation time 57641725023 ps
CPU time 100.71 seconds
Started Jun 07 07:25:50 PM PDT 24
Finished Jun 07 07:27:36 PM PDT 24
Peak memory 200296 kb
Host smart-fd64237c-5c39-4e3d-9566-54b17425bc76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989706143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.2989706143
Directory /workspace/60.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.1053486080
Short name T1193
Test name
Test status
Simulation time 334242067 ps
CPU time 1.34 seconds
Started Jun 07 07:11:26 PM PDT 24
Finished Jun 07 07:11:37 PM PDT 24
Peak memory 200064 kb
Host smart-e5c6924a-26bc-4374-99c5-e8ea76fab1b3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053486080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.1053486080
Directory /workspace/6.uart_tl_intg_err/latest

Test location /workspace/coverage/default/1.uart_rx_parity_err.99856259
Short name T100
Test name
Test status
Simulation time 198879122503 ps
CPU time 18.51 seconds
Started Jun 07 07:19:40 PM PDT 24
Finished Jun 07 07:20:22 PM PDT 24
Peak memory 200176 kb
Host smart-4a450fed-d440-4799-8df6-c22bb8856044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99856259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.99856259
Directory /workspace/1.uart_rx_parity_err/latest

Test location /workspace/coverage/default/40.uart_perf.3142845305
Short name T96
Test name
Test status
Simulation time 26614318712 ps
CPU time 540.55 seconds
Started Jun 07 07:24:40 PM PDT 24
Finished Jun 07 07:33:46 PM PDT 24
Peak memory 200296 kb
Host smart-dbd4448e-bd5a-41a9-be2b-b12b400f2256
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3142845305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.3142845305
Directory /workspace/40.uart_perf/latest

Test location /workspace/coverage/default/263.uart_fifo_reset.3072893578
Short name T270
Test name
Test status
Simulation time 456932523531 ps
CPU time 85.91 seconds
Started Jun 07 07:27:50 PM PDT 24
Finished Jun 07 07:29:21 PM PDT 24
Peak memory 200420 kb
Host smart-55b1c666-ab15-4ca7-a410-7f813ada3ca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072893578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.3072893578
Directory /workspace/263.uart_fifo_reset/latest

Test location /workspace/coverage/default/280.uart_fifo_reset.2695750555
Short name T8
Test name
Test status
Simulation time 9195666404 ps
CPU time 26.3 seconds
Started Jun 07 07:27:52 PM PDT 24
Finished Jun 07 07:28:24 PM PDT 24
Peak memory 200336 kb
Host smart-4e69b59e-e114-4ac9-9909-cf4a15f2c94f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695750555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.2695750555
Directory /workspace/280.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_stress_all.650474015
Short name T232
Test name
Test status
Simulation time 130978869949 ps
CPU time 232.98 seconds
Started Jun 07 07:20:39 PM PDT 24
Finished Jun 07 07:24:49 PM PDT 24
Peak memory 200304 kb
Host smart-7cc6493d-4aba-4989-80a0-25be1413d583
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650474015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.650474015
Directory /workspace/9.uart_stress_all/latest

Test location /workspace/coverage/default/109.uart_fifo_reset.3330287670
Short name T183
Test name
Test status
Simulation time 10254367053 ps
CPU time 21.76 seconds
Started Jun 07 07:26:23 PM PDT 24
Finished Jun 07 07:26:51 PM PDT 24
Peak memory 200344 kb
Host smart-3dde3a83-70de-46a7-8380-dfa82c76e1a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330287670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.3330287670
Directory /workspace/109.uart_fifo_reset/latest

Test location /workspace/coverage/default/117.uart_fifo_reset.1382163927
Short name T166
Test name
Test status
Simulation time 63050649137 ps
CPU time 47.13 seconds
Started Jun 07 07:26:24 PM PDT 24
Finished Jun 07 07:27:17 PM PDT 24
Peak memory 200176 kb
Host smart-c87b92b0-4401-4b74-a1a9-92bff9985832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382163927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.1382163927
Directory /workspace/117.uart_fifo_reset/latest

Test location /workspace/coverage/default/147.uart_fifo_reset.2506113523
Short name T253
Test name
Test status
Simulation time 25792283885 ps
CPU time 33.7 seconds
Started Jun 07 07:26:37 PM PDT 24
Finished Jun 07 07:27:13 PM PDT 24
Peak memory 200220 kb
Host smart-81f9b6a8-d06c-493a-af28-429194a96136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506113523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.2506113523
Directory /workspace/147.uart_fifo_reset/latest

Test location /workspace/coverage/default/288.uart_fifo_reset.1230072200
Short name T233
Test name
Test status
Simulation time 131873385161 ps
CPU time 219.85 seconds
Started Jun 07 07:27:57 PM PDT 24
Finished Jun 07 07:31:42 PM PDT 24
Peak memory 200320 kb
Host smart-915d6e00-1eb7-46b7-aa48-46c2ed138f49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230072200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.1230072200
Directory /workspace/288.uart_fifo_reset/latest

Test location /workspace/coverage/default/47.uart_stress_all_with_rand_reset.2532923674
Short name T163
Test name
Test status
Simulation time 1336627957750 ps
CPU time 704.27 seconds
Started Jun 07 07:25:26 PM PDT 24
Finished Jun 07 07:37:15 PM PDT 24
Peak memory 216992 kb
Host smart-b7f01c7d-9a53-4043-b69d-f2734b976e87
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532923674 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 47.uart_stress_all_with_rand_reset.2532923674
Directory /workspace/47.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_fifo_reset.3384948409
Short name T208
Test name
Test status
Simulation time 288837776872 ps
CPU time 404.19 seconds
Started Jun 07 07:20:29 PM PDT 24
Finished Jun 07 07:27:35 PM PDT 24
Peak memory 200440 kb
Host smart-b2c4075f-8d7d-45b8-b3b2-0be7da88873d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384948409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.3384948409
Directory /workspace/8.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_stress_all.3749451294
Short name T180
Test name
Test status
Simulation time 1289207204066 ps
CPU time 163.5 seconds
Started Jun 07 07:21:04 PM PDT 24
Finished Jun 07 07:23:52 PM PDT 24
Peak memory 200396 kb
Host smart-253c6a48-bc2e-43ac-b68b-9cda870a9540
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749451294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.3749451294
Directory /workspace/13.uart_stress_all/latest

Test location /workspace/coverage/default/7.uart_fifo_overflow.3791736226
Short name T14
Test name
Test status
Simulation time 58381276618 ps
CPU time 24.46 seconds
Started Jun 07 07:20:16 PM PDT 24
Finished Jun 07 07:21:04 PM PDT 24
Peak memory 200336 kb
Host smart-6384f374-ba19-4852-8cb9-c98959d34422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791736226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.3791736226
Directory /workspace/7.uart_fifo_overflow/latest

Test location /workspace/coverage/default/11.uart_fifo_reset.2983703628
Short name T247
Test name
Test status
Simulation time 64870448667 ps
CPU time 106.54 seconds
Started Jun 07 07:20:42 PM PDT 24
Finished Jun 07 07:22:44 PM PDT 24
Peak memory 200208 kb
Host smart-de9bb848-769e-421e-893d-e7aee08b1e47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983703628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.2983703628
Directory /workspace/11.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_fifo_reset.2527623560
Short name T172
Test name
Test status
Simulation time 116308316984 ps
CPU time 61.28 seconds
Started Jun 07 07:19:40 PM PDT 24
Finished Jun 07 07:21:04 PM PDT 24
Peak memory 200316 kb
Host smart-fa7ddd47-4f99-49b6-b7bc-29410ff4c43b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527623560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.2527623560
Directory /workspace/2.uart_fifo_reset/latest

Test location /workspace/coverage/default/219.uart_fifo_reset.93995351
Short name T284
Test name
Test status
Simulation time 57746417219 ps
CPU time 44.14 seconds
Started Jun 07 07:27:29 PM PDT 24
Finished Jun 07 07:28:18 PM PDT 24
Peak memory 200320 kb
Host smart-10058fde-9b5d-41eb-ba9e-6a59e4bcac6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93995351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.93995351
Directory /workspace/219.uart_fifo_reset/latest

Test location /workspace/coverage/default/233.uart_fifo_reset.1960581868
Short name T198
Test name
Test status
Simulation time 131463447174 ps
CPU time 264.78 seconds
Started Jun 07 07:27:39 PM PDT 24
Finished Jun 07 07:32:07 PM PDT 24
Peak memory 200316 kb
Host smart-3d5ebec6-1f9d-4a44-9096-de29f2fee358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960581868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.1960581868
Directory /workspace/233.uart_fifo_reset/latest

Test location /workspace/coverage/default/35.uart_fifo_reset.137476659
Short name T155
Test name
Test status
Simulation time 90038550954 ps
CPU time 44.63 seconds
Started Jun 07 07:24:08 PM PDT 24
Finished Jun 07 07:24:59 PM PDT 24
Peak memory 200452 kb
Host smart-505d980f-f5d7-4e7f-8f24-74ea46d34571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137476659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.137476659
Directory /workspace/35.uart_fifo_reset/latest

Test location /workspace/coverage/default/38.uart_tx_rx.2749356172
Short name T273
Test name
Test status
Simulation time 90716686442 ps
CPU time 142.62 seconds
Started Jun 07 07:24:23 PM PDT 24
Finished Jun 07 07:26:51 PM PDT 24
Peak memory 200384 kb
Host smart-b09951fd-bb1d-4841-86b1-86b90e6cbfbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749356172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.2749356172
Directory /workspace/38.uart_tx_rx/latest

Test location /workspace/coverage/default/73.uart_fifo_reset.3503011074
Short name T148
Test name
Test status
Simulation time 75532735339 ps
CPU time 51.56 seconds
Started Jun 07 07:25:59 PM PDT 24
Finished Jun 07 07:26:54 PM PDT 24
Peak memory 200452 kb
Host smart-95c40f8e-2aa6-4adf-b491-edceb3ff2288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503011074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.3503011074
Directory /workspace/73.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_stress_all.4243593042
Short name T171
Test name
Test status
Simulation time 270642242245 ps
CPU time 886.94 seconds
Started Jun 07 07:20:52 PM PDT 24
Finished Jun 07 07:35:50 PM PDT 24
Peak memory 200412 kb
Host smart-461de6ed-07f2-455c-a0ef-278e29c349d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243593042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.4243593042
Directory /workspace/11.uart_stress_all/latest

Test location /workspace/coverage/default/136.uart_fifo_reset.676302209
Short name T227
Test name
Test status
Simulation time 31911912320 ps
CPU time 14.24 seconds
Started Jun 07 07:26:33 PM PDT 24
Finished Jun 07 07:26:50 PM PDT 24
Peak memory 200384 kb
Host smart-8f891997-dc09-48a2-afc7-c893256182da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676302209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.676302209
Directory /workspace/136.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_stress_all_with_rand_reset.431162974
Short name T733
Test name
Test status
Simulation time 78368377286 ps
CPU time 758.77 seconds
Started Jun 07 07:21:54 PM PDT 24
Finished Jun 07 07:34:45 PM PDT 24
Peak memory 216792 kb
Host smart-b154451f-115b-4ecc-a73e-9197a19e91de
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431162974 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 19.uart_stress_all_with_rand_reset.431162974
Directory /workspace/19.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/192.uart_fifo_reset.2323723858
Short name T249
Test name
Test status
Simulation time 24186272228 ps
CPU time 34.67 seconds
Started Jun 07 07:27:05 PM PDT 24
Finished Jun 07 07:27:42 PM PDT 24
Peak memory 200416 kb
Host smart-5ae8aec3-5c09-465f-a3f3-c00dc5d13a98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323723858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.2323723858
Directory /workspace/192.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_fifo_reset.210051375
Short name T1079
Test name
Test status
Simulation time 50091130815 ps
CPU time 20.19 seconds
Started Jun 07 07:22:49 PM PDT 24
Finished Jun 07 07:23:15 PM PDT 24
Peak memory 200392 kb
Host smart-d14fbcfa-ded3-4a45-912e-08e40b20a965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210051375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.210051375
Directory /workspace/22.uart_fifo_reset/latest

Test location /workspace/coverage/default/229.uart_fifo_reset.2723232857
Short name T237
Test name
Test status
Simulation time 60717311881 ps
CPU time 56.97 seconds
Started Jun 07 07:27:28 PM PDT 24
Finished Jun 07 07:28:29 PM PDT 24
Peak memory 200404 kb
Host smart-ce2a3432-11e2-4cbe-8817-59c127853420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723232857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.2723232857
Directory /workspace/229.uart_fifo_reset/latest

Test location /workspace/coverage/default/230.uart_fifo_reset.493583191
Short name T891
Test name
Test status
Simulation time 82278158890 ps
CPU time 13.09 seconds
Started Jun 07 07:27:28 PM PDT 24
Finished Jun 07 07:27:46 PM PDT 24
Peak memory 200424 kb
Host smart-8db7e242-3d08-45ec-a4e6-266546294559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493583191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.493583191
Directory /workspace/230.uart_fifo_reset/latest

Test location /workspace/coverage/default/47.uart_fifo_reset.469170708
Short name T250
Test name
Test status
Simulation time 160609682000 ps
CPU time 67.3 seconds
Started Jun 07 07:25:25 PM PDT 24
Finished Jun 07 07:26:37 PM PDT 24
Peak memory 200432 kb
Host smart-e98b3d45-078f-4f04-9fe0-c1a8358f4d6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469170708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.469170708
Directory /workspace/47.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.4179682725
Short name T1217
Test name
Test status
Simulation time 340553549 ps
CPU time 1.26 seconds
Started Jun 07 07:11:10 PM PDT 24
Finished Jun 07 07:11:21 PM PDT 24
Peak memory 199984 kb
Host smart-62d32a54-8631-4430-a2d5-0e7e91ea525c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179682725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.4179682725
Directory /workspace/0.uart_tl_intg_err/latest

Test location /workspace/coverage/default/0.uart_fifo_reset.343983717
Short name T239
Test name
Test status
Simulation time 129519621931 ps
CPU time 65.44 seconds
Started Jun 07 07:19:29 PM PDT 24
Finished Jun 07 07:20:54 PM PDT 24
Peak memory 200404 kb
Host smart-19b81978-633a-4a37-b57a-278c24da405b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343983717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.343983717
Directory /workspace/0.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_stress_all_with_rand_reset.1270642996
Short name T226
Test name
Test status
Simulation time 308529280981 ps
CPU time 304.36 seconds
Started Jun 07 07:19:33 PM PDT 24
Finished Jun 07 07:24:57 PM PDT 24
Peak memory 216972 kb
Host smart-09e29488-4ce2-4336-982f-a1f095b62d6d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270642996 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.uart_stress_all_with_rand_reset.1270642996
Directory /workspace/0.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/112.uart_fifo_reset.322373050
Short name T147
Test name
Test status
Simulation time 96094150747 ps
CPU time 159 seconds
Started Jun 07 07:26:21 PM PDT 24
Finished Jun 07 07:29:05 PM PDT 24
Peak memory 200352 kb
Host smart-116c6be5-45ff-49b2-9741-ec3b99c4a1be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322373050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.322373050
Directory /workspace/112.uart_fifo_reset/latest

Test location /workspace/coverage/default/113.uart_fifo_reset.2304931670
Short name T229
Test name
Test status
Simulation time 36513588037 ps
CPU time 53.89 seconds
Started Jun 07 07:26:23 PM PDT 24
Finished Jun 07 07:27:23 PM PDT 24
Peak memory 200256 kb
Host smart-578f897d-1710-4f81-b2a8-a8c7863fca13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304931670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.2304931670
Directory /workspace/113.uart_fifo_reset/latest

Test location /workspace/coverage/default/122.uart_fifo_reset.3176532381
Short name T191
Test name
Test status
Simulation time 86506729201 ps
CPU time 81.4 seconds
Started Jun 07 07:26:22 PM PDT 24
Finished Jun 07 07:27:49 PM PDT 24
Peak memory 200404 kb
Host smart-a4b96eb2-b76e-4bb7-af24-c4ff7edbc166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176532381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.3176532381
Directory /workspace/122.uart_fifo_reset/latest

Test location /workspace/coverage/default/140.uart_fifo_reset.2384385326
Short name T259
Test name
Test status
Simulation time 197089918483 ps
CPU time 165.09 seconds
Started Jun 07 07:26:32 PM PDT 24
Finished Jun 07 07:29:20 PM PDT 24
Peak memory 200396 kb
Host smart-4394ea84-ac49-4652-ae7e-c7d0873efa23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384385326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.2384385326
Directory /workspace/140.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_stress_all_with_rand_reset.2483859055
Short name T102
Test name
Test status
Simulation time 135070516869 ps
CPU time 414.77 seconds
Started Jun 07 07:21:28 PM PDT 24
Finished Jun 07 07:28:33 PM PDT 24
Peak memory 216812 kb
Host smart-433b4772-da87-4845-beca-48b20c984af8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483859055 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 15.uart_stress_all_with_rand_reset.2483859055
Directory /workspace/15.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.uart_rx_parity_err.766505843
Short name T269
Test name
Test status
Simulation time 93438136064 ps
CPU time 122.02 seconds
Started Jun 07 07:21:28 PM PDT 24
Finished Jun 07 07:23:40 PM PDT 24
Peak memory 200388 kb
Host smart-94e9aac5-87bb-4f90-b009-e306e11618bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766505843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.766505843
Directory /workspace/16.uart_rx_parity_err/latest

Test location /workspace/coverage/default/166.uart_fifo_reset.1152759589
Short name T133
Test name
Test status
Simulation time 35045142874 ps
CPU time 57.47 seconds
Started Jun 07 07:27:21 PM PDT 24
Finished Jun 07 07:28:22 PM PDT 24
Peak memory 200088 kb
Host smart-aa2fed66-bb4b-4ae6-b493-6ab154962f6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152759589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.1152759589
Directory /workspace/166.uart_fifo_reset/latest

Test location /workspace/coverage/default/174.uart_fifo_reset.2260513066
Short name T189
Test name
Test status
Simulation time 45570131236 ps
CPU time 20.22 seconds
Started Jun 07 07:27:22 PM PDT 24
Finished Jun 07 07:27:46 PM PDT 24
Peak memory 200236 kb
Host smart-ca1a5ecb-4f5e-4814-8d30-9401c41a4ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260513066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.2260513066
Directory /workspace/174.uart_fifo_reset/latest

Test location /workspace/coverage/default/176.uart_fifo_reset.1884001744
Short name T218
Test name
Test status
Simulation time 121627099040 ps
CPU time 300.2 seconds
Started Jun 07 07:27:23 PM PDT 24
Finished Jun 07 07:32:28 PM PDT 24
Peak memory 200404 kb
Host smart-eb81da93-4653-46ea-930d-037bc99599cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884001744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.1884001744
Directory /workspace/176.uart_fifo_reset/latest

Test location /workspace/coverage/default/178.uart_fifo_reset.1434144750
Short name T254
Test name
Test status
Simulation time 145594574965 ps
CPU time 44.5 seconds
Started Jun 07 07:27:25 PM PDT 24
Finished Jun 07 07:28:14 PM PDT 24
Peak memory 200340 kb
Host smart-83ea1870-7741-403d-8c37-4c12dcbfc89a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434144750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.1434144750
Directory /workspace/178.uart_fifo_reset/latest

Test location /workspace/coverage/default/184.uart_fifo_reset.4085379317
Short name T257
Test name
Test status
Simulation time 13746613108 ps
CPU time 28.61 seconds
Started Jun 07 07:27:05 PM PDT 24
Finished Jun 07 07:27:35 PM PDT 24
Peak memory 200244 kb
Host smart-e40d0e10-b909-4d70-b696-ff91df8a5965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085379317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.4085379317
Directory /workspace/184.uart_fifo_reset/latest

Test location /workspace/coverage/default/189.uart_fifo_reset.387891257
Short name T217
Test name
Test status
Simulation time 50734656022 ps
CPU time 114.98 seconds
Started Jun 07 07:27:06 PM PDT 24
Finished Jun 07 07:29:03 PM PDT 24
Peak memory 200228 kb
Host smart-a74840a7-cff2-4c54-91f1-d1c785051d6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387891257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.387891257
Directory /workspace/189.uart_fifo_reset/latest

Test location /workspace/coverage/default/250.uart_fifo_reset.4046078952
Short name T242
Test name
Test status
Simulation time 37365597049 ps
CPU time 20.43 seconds
Started Jun 07 07:27:41 PM PDT 24
Finished Jun 07 07:28:07 PM PDT 24
Peak memory 200380 kb
Host smart-77dfe558-f626-4510-953d-e3720da2059b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046078952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.4046078952
Directory /workspace/250.uart_fifo_reset/latest

Test location /workspace/coverage/default/251.uart_fifo_reset.1333736723
Short name T252
Test name
Test status
Simulation time 139613460608 ps
CPU time 111.51 seconds
Started Jun 07 07:27:39 PM PDT 24
Finished Jun 07 07:29:35 PM PDT 24
Peak memory 200424 kb
Host smart-2e138325-49f8-4c27-bb5a-4e9a475de80a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333736723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.1333736723
Directory /workspace/251.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_stress_all_with_rand_reset.2361400365
Short name T314
Test name
Test status
Simulation time 45882656741 ps
CPU time 100.15 seconds
Started Jun 07 07:23:02 PM PDT 24
Finished Jun 07 07:24:53 PM PDT 24
Peak memory 209084 kb
Host smart-f4712015-c9b1-4b07-ab6d-ae168b383861
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361400365 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 27.uart_stress_all_with_rand_reset.2361400365
Directory /workspace/27.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/275.uart_fifo_reset.2170425989
Short name T251
Test name
Test status
Simulation time 7783004094 ps
CPU time 4.59 seconds
Started Jun 07 07:27:50 PM PDT 24
Finished Jun 07 07:28:00 PM PDT 24
Peak memory 200264 kb
Host smart-9080086a-1fd9-4412-bccd-dacc4ea74355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170425989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.2170425989
Directory /workspace/275.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_fifo_reset.2192223583
Short name T167
Test name
Test status
Simulation time 54690062531 ps
CPU time 23.71 seconds
Started Jun 07 07:24:42 PM PDT 24
Finished Jun 07 07:25:13 PM PDT 24
Peak memory 199852 kb
Host smart-535cbcd1-e7fb-4b1f-8b50-b5e8817204b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192223583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.2192223583
Directory /workspace/41.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.3705417613
Short name T1207
Test name
Test status
Simulation time 22613972 ps
CPU time 0.68 seconds
Started Jun 07 07:11:19 PM PDT 24
Finished Jun 07 07:11:30 PM PDT 24
Peak memory 195584 kb
Host smart-dbc6bff6-a8cd-40c1-bf46-cc4b1fbbe9c0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705417613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.3705417613
Directory /workspace/0.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.3319005452
Short name T1137
Test name
Test status
Simulation time 92264636 ps
CPU time 1.52 seconds
Started Jun 07 07:11:18 PM PDT 24
Finished Jun 07 07:11:29 PM PDT 24
Peak memory 198624 kb
Host smart-2dc99506-d59e-418d-899b-80a88809bbfa
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319005452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.3319005452
Directory /workspace/0.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.1122459604
Short name T1095
Test name
Test status
Simulation time 30643988 ps
CPU time 0.6 seconds
Started Jun 07 07:11:10 PM PDT 24
Finished Jun 07 07:11:21 PM PDT 24
Peak memory 196060 kb
Host smart-76c06e83-5e75-4c9b-972c-bde7f1f40dde
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122459604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.1122459604
Directory /workspace/0.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.3241339637
Short name T1222
Test name
Test status
Simulation time 27923545 ps
CPU time 0.77 seconds
Started Jun 07 07:11:18 PM PDT 24
Finished Jun 07 07:11:29 PM PDT 24
Peak memory 198792 kb
Host smart-6f52ff79-6ce3-4ebf-a19f-e0cc7cf3d158
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241339637 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.3241339637
Directory /workspace/0.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_intr_test.901601145
Short name T1093
Test name
Test status
Simulation time 10875847 ps
CPU time 0.55 seconds
Started Jun 07 07:11:10 PM PDT 24
Finished Jun 07 07:11:20 PM PDT 24
Peak memory 195096 kb
Host smart-20de4102-3af6-47df-a333-e8ede13d47d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901601145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.901601145
Directory /workspace/0.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_errors.447498296
Short name T1185
Test name
Test status
Simulation time 117133661 ps
CPU time 2.07 seconds
Started Jun 07 07:11:10 PM PDT 24
Finished Jun 07 07:11:22 PM PDT 24
Peak memory 200808 kb
Host smart-872ad672-7189-493f-be7d-7a86b3ed5ac4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447498296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.447498296
Directory /workspace/0.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.3182635376
Short name T59
Test name
Test status
Simulation time 14483641 ps
CPU time 0.68 seconds
Started Jun 07 07:11:21 PM PDT 24
Finished Jun 07 07:11:32 PM PDT 24
Peak memory 195484 kb
Host smart-d5b13fce-ef9a-432e-a145-078679207e72
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182635376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.3182635376
Directory /workspace/1.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.3996135113
Short name T1091
Test name
Test status
Simulation time 56760207 ps
CPU time 2.23 seconds
Started Jun 07 07:11:26 PM PDT 24
Finished Jun 07 07:11:38 PM PDT 24
Peak memory 198448 kb
Host smart-20af50d9-5ce5-46c2-90ee-a27b4aaab89c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996135113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.3996135113
Directory /workspace/1.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.2004748733
Short name T1088
Test name
Test status
Simulation time 72276053 ps
CPU time 0.57 seconds
Started Jun 07 07:11:18 PM PDT 24
Finished Jun 07 07:11:29 PM PDT 24
Peak memory 196132 kb
Host smart-dacd8c0e-40c9-4f01-ad11-5f156fd72fd8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004748733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.2004748733
Directory /workspace/1.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.73095047
Short name T1128
Test name
Test status
Simulation time 19604518 ps
CPU time 0.69 seconds
Started Jun 07 07:11:16 PM PDT 24
Finished Jun 07 07:11:27 PM PDT 24
Peak memory 199224 kb
Host smart-a6cc7186-83f5-43a8-94ed-75deef813e3f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73095047 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.73095047
Directory /workspace/1.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_rw.683031209
Short name T1108
Test name
Test status
Simulation time 101881015 ps
CPU time 0.57 seconds
Started Jun 07 07:11:19 PM PDT 24
Finished Jun 07 07:11:30 PM PDT 24
Peak memory 196072 kb
Host smart-679fdd98-06f4-45dd-83dd-6739536439cc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683031209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.683031209
Directory /workspace/1.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.uart_intr_test.2611383061
Short name T1165
Test name
Test status
Simulation time 13197280 ps
CPU time 0.57 seconds
Started Jun 07 07:11:26 PM PDT 24
Finished Jun 07 07:11:37 PM PDT 24
Peak memory 195184 kb
Host smart-fc359f31-8414-4184-b717-2c5d026621ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611383061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.2611383061
Directory /workspace/1.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.3541595832
Short name T1190
Test name
Test status
Simulation time 62450051 ps
CPU time 0.78 seconds
Started Jun 07 07:11:24 PM PDT 24
Finished Jun 07 07:11:35 PM PDT 24
Peak memory 198448 kb
Host smart-8b79549d-351c-4255-8640-bf7f9932b777
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541595832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr
_outstanding.3541595832
Directory /workspace/1.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_errors.1147146256
Short name T1206
Test name
Test status
Simulation time 73255372 ps
CPU time 1.72 seconds
Started Jun 07 07:11:16 PM PDT 24
Finished Jun 07 07:11:28 PM PDT 24
Peak memory 200784 kb
Host smart-a81f6327-880e-434f-9880-49e70d4a27d6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147146256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.1147146256
Directory /workspace/1.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.3346581243
Short name T1212
Test name
Test status
Simulation time 175859650 ps
CPU time 1.39 seconds
Started Jun 07 07:11:19 PM PDT 24
Finished Jun 07 07:11:31 PM PDT 24
Peak memory 200120 kb
Host smart-834a0bf1-6d0f-4d55-bb3c-ea05083fa971
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346581243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.3346581243
Directory /workspace/1.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.2910756209
Short name T1096
Test name
Test status
Simulation time 55679609 ps
CPU time 1.03 seconds
Started Jun 07 07:11:26 PM PDT 24
Finished Jun 07 07:11:37 PM PDT 24
Peak memory 200592 kb
Host smart-0df25a3a-089e-4cfa-a9c9-c79c1c9b5236
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910756209 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.2910756209
Directory /workspace/10.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_rw.3515218681
Short name T1135
Test name
Test status
Simulation time 15667535 ps
CPU time 0.59 seconds
Started Jun 07 07:11:25 PM PDT 24
Finished Jun 07 07:11:36 PM PDT 24
Peak memory 196120 kb
Host smart-a6cc9eef-6324-41a2-8fab-d968933dc2c8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515218681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.3515218681
Directory /workspace/10.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.uart_intr_test.295872413
Short name T1211
Test name
Test status
Simulation time 43060808 ps
CPU time 0.58 seconds
Started Jun 07 07:11:29 PM PDT 24
Finished Jun 07 07:11:40 PM PDT 24
Peak memory 195072 kb
Host smart-a91e38ac-19ae-4810-ae6a-a01197c90f40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295872413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.295872413
Directory /workspace/10.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.1644645238
Short name T1166
Test name
Test status
Simulation time 62258564 ps
CPU time 0.64 seconds
Started Jun 07 07:11:29 PM PDT 24
Finished Jun 07 07:11:39 PM PDT 24
Peak memory 196324 kb
Host smart-879778e9-2dcf-4892-8a78-577fca3f6a1d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644645238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_cs
r_outstanding.1644645238
Directory /workspace/10.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_errors.891168373
Short name T1201
Test name
Test status
Simulation time 35398582 ps
CPU time 1.86 seconds
Started Jun 07 07:11:27 PM PDT 24
Finished Jun 07 07:11:39 PM PDT 24
Peak memory 200808 kb
Host smart-083310e6-8fec-4cce-a5f5-c03b0842b743
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891168373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.891168373
Directory /workspace/10.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.94341016
Short name T1172
Test name
Test status
Simulation time 87216827 ps
CPU time 1.37 seconds
Started Jun 07 07:11:27 PM PDT 24
Finished Jun 07 07:11:38 PM PDT 24
Peak memory 200168 kb
Host smart-2bba3b98-ed2b-474f-ba7e-f55cfcd33f45
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94341016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.94341016
Directory /workspace/10.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.3496995106
Short name T1124
Test name
Test status
Simulation time 79585109 ps
CPU time 1.04 seconds
Started Jun 07 07:11:36 PM PDT 24
Finished Jun 07 07:11:48 PM PDT 24
Peak memory 200812 kb
Host smart-3f868fad-14bb-4346-a410-843457ce355f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496995106 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.3496995106
Directory /workspace/11.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_rw.338407163
Short name T1112
Test name
Test status
Simulation time 46253557 ps
CPU time 0.61 seconds
Started Jun 07 07:11:39 PM PDT 24
Finished Jun 07 07:11:51 PM PDT 24
Peak memory 196164 kb
Host smart-c9b02c54-f61d-40c1-a653-20de4c9a9556
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338407163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.338407163
Directory /workspace/11.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.uart_intr_test.3186986123
Short name T1218
Test name
Test status
Simulation time 14953555 ps
CPU time 0.57 seconds
Started Jun 07 07:11:35 PM PDT 24
Finished Jun 07 07:11:46 PM PDT 24
Peak memory 195076 kb
Host smart-5b2fb8df-d123-4956-b7c0-d60ae74549de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186986123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.3186986123
Directory /workspace/11.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.1405790709
Short name T1174
Test name
Test status
Simulation time 47146062 ps
CPU time 0.72 seconds
Started Jun 07 07:11:38 PM PDT 24
Finished Jun 07 07:11:51 PM PDT 24
Peak memory 196788 kb
Host smart-c1409994-82bf-4e48-ad68-a0adc2de5053
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405790709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_cs
r_outstanding.1405790709
Directory /workspace/11.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_errors.614663492
Short name T1159
Test name
Test status
Simulation time 261295641 ps
CPU time 1.41 seconds
Started Jun 07 07:11:24 PM PDT 24
Finished Jun 07 07:11:35 PM PDT 24
Peak memory 200784 kb
Host smart-f926a9b0-f2ed-4520-b383-12ed162af206
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614663492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.614663492
Directory /workspace/11.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.1878826689
Short name T86
Test name
Test status
Simulation time 304166074 ps
CPU time 0.92 seconds
Started Jun 07 07:11:36 PM PDT 24
Finished Jun 07 07:11:48 PM PDT 24
Peak memory 199656 kb
Host smart-2c7fac4d-1517-4e17-8bae-3abf3cc9401d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878826689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.1878826689
Directory /workspace/11.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.2092711262
Short name T1151
Test name
Test status
Simulation time 101432922 ps
CPU time 0.78 seconds
Started Jun 07 07:11:35 PM PDT 24
Finished Jun 07 07:11:46 PM PDT 24
Peak memory 199192 kb
Host smart-d503b78c-d60e-4e95-b8e9-720432b86a7a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092711262 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.2092711262
Directory /workspace/12.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_rw.3055559706
Short name T1221
Test name
Test status
Simulation time 14178114 ps
CPU time 0.61 seconds
Started Jun 07 07:11:38 PM PDT 24
Finished Jun 07 07:11:49 PM PDT 24
Peak memory 196228 kb
Host smart-3abd6b4f-e11d-446e-9005-17d5647b41ff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055559706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.3055559706
Directory /workspace/12.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.uart_intr_test.1857390113
Short name T1134
Test name
Test status
Simulation time 12303565 ps
CPU time 0.58 seconds
Started Jun 07 07:11:35 PM PDT 24
Finished Jun 07 07:11:46 PM PDT 24
Peak memory 195084 kb
Host smart-591684bf-046b-4cfc-a207-c17e4bbabc42
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857390113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.1857390113
Directory /workspace/12.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.365585516
Short name T1220
Test name
Test status
Simulation time 260678126 ps
CPU time 0.79 seconds
Started Jun 07 07:11:36 PM PDT 24
Finished Jun 07 07:11:47 PM PDT 24
Peak memory 197340 kb
Host smart-b1c23841-1446-4b78-9595-d3db07081bde
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365585516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_csr
_outstanding.365585516
Directory /workspace/12.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_errors.2671178350
Short name T1152
Test name
Test status
Simulation time 88172079 ps
CPU time 1.8 seconds
Started Jun 07 07:11:39 PM PDT 24
Finished Jun 07 07:11:53 PM PDT 24
Peak memory 200716 kb
Host smart-a7291708-41ca-496e-98b9-6a06a87052a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671178350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.2671178350
Directory /workspace/12.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.456819022
Short name T92
Test name
Test status
Simulation time 160455086 ps
CPU time 0.91 seconds
Started Jun 07 07:11:34 PM PDT 24
Finished Jun 07 07:11:45 PM PDT 24
Peak memory 199720 kb
Host smart-3565bd84-43a0-4428-a711-b23909654cef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456819022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.456819022
Directory /workspace/12.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.3491151835
Short name T1125
Test name
Test status
Simulation time 74476132 ps
CPU time 0.82 seconds
Started Jun 07 07:11:35 PM PDT 24
Finished Jun 07 07:11:46 PM PDT 24
Peak memory 199264 kb
Host smart-76a21be2-51c6-4662-be22-613aa8c9cb77
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491151835 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.3491151835
Directory /workspace/13.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_rw.806192312
Short name T1127
Test name
Test status
Simulation time 43613094 ps
CPU time 0.62 seconds
Started Jun 07 07:11:34 PM PDT 24
Finished Jun 07 07:11:44 PM PDT 24
Peak memory 196280 kb
Host smart-04c732af-883e-4bd0-80b5-a0dfa6359750
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806192312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.806192312
Directory /workspace/13.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.uart_intr_test.601184712
Short name T1197
Test name
Test status
Simulation time 14064200 ps
CPU time 0.59 seconds
Started Jun 07 07:11:34 PM PDT 24
Finished Jun 07 07:11:44 PM PDT 24
Peak memory 195132 kb
Host smart-7424bcf6-d28f-440b-84c6-64c74e795eb2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601184712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.601184712
Directory /workspace/13.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.3782395677
Short name T81
Test name
Test status
Simulation time 96770520 ps
CPU time 0.67 seconds
Started Jun 07 07:11:38 PM PDT 24
Finished Jun 07 07:11:50 PM PDT 24
Peak memory 196332 kb
Host smart-ec85b85e-848b-45be-9132-08480410370d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782395677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_cs
r_outstanding.3782395677
Directory /workspace/13.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_errors.4204658719
Short name T1099
Test name
Test status
Simulation time 178715543 ps
CPU time 1.57 seconds
Started Jun 07 07:11:36 PM PDT 24
Finished Jun 07 07:11:48 PM PDT 24
Peak memory 200788 kb
Host smart-c83d4d5e-2d96-4b58-8546-455ea90c83d0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204658719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.4204658719
Directory /workspace/13.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.315830548
Short name T1202
Test name
Test status
Simulation time 84703996 ps
CPU time 0.87 seconds
Started Jun 07 07:11:35 PM PDT 24
Finished Jun 07 07:11:45 PM PDT 24
Peak memory 199264 kb
Host smart-9d9fbbb4-0d18-4038-976e-6958ba4510c2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315830548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.315830548
Directory /workspace/13.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.1258703423
Short name T1186
Test name
Test status
Simulation time 43959234 ps
CPU time 0.8 seconds
Started Jun 07 07:11:39 PM PDT 24
Finished Jun 07 07:11:51 PM PDT 24
Peak memory 199216 kb
Host smart-bab3e81b-61bf-4a8f-bfeb-84bb91c71e8f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258703423 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.1258703423
Directory /workspace/14.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_rw.2445475078
Short name T1176
Test name
Test status
Simulation time 24522210 ps
CPU time 0.62 seconds
Started Jun 07 07:11:36 PM PDT 24
Finished Jun 07 07:11:48 PM PDT 24
Peak memory 196108 kb
Host smart-6eadf6f9-6628-40e3-9d2d-c604d8d053df
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445475078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.2445475078
Directory /workspace/14.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.uart_intr_test.42230877
Short name T1119
Test name
Test status
Simulation time 12268791 ps
CPU time 0.6 seconds
Started Jun 07 07:11:35 PM PDT 24
Finished Jun 07 07:11:45 PM PDT 24
Peak memory 195152 kb
Host smart-b551224a-b489-4f11-8842-168e80e36f44
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42230877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.42230877
Directory /workspace/14.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.2754642421
Short name T80
Test name
Test status
Simulation time 14096128 ps
CPU time 0.65 seconds
Started Jun 07 07:11:35 PM PDT 24
Finished Jun 07 07:11:46 PM PDT 24
Peak memory 195268 kb
Host smart-e1cd8e22-55ef-4fce-bb76-b9eb0459cd66
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754642421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_cs
r_outstanding.2754642421
Directory /workspace/14.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_errors.1953377615
Short name T1118
Test name
Test status
Simulation time 112870219 ps
CPU time 2.38 seconds
Started Jun 07 07:11:35 PM PDT 24
Finished Jun 07 07:11:48 PM PDT 24
Peak memory 200828 kb
Host smart-6e9eb5cb-9414-41be-aed4-51897f82e2e9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953377615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.1953377615
Directory /workspace/14.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.1646115499
Short name T90
Test name
Test status
Simulation time 54790877 ps
CPU time 1.04 seconds
Started Jun 07 07:11:36 PM PDT 24
Finished Jun 07 07:11:48 PM PDT 24
Peak memory 199540 kb
Host smart-4c4e4e86-dcb5-4114-8d83-4b5ee2d2cebe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646115499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.1646115499
Directory /workspace/14.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.1391308135
Short name T1175
Test name
Test status
Simulation time 27080984 ps
CPU time 0.8 seconds
Started Jun 07 07:11:38 PM PDT 24
Finished Jun 07 07:11:50 PM PDT 24
Peak memory 200608 kb
Host smart-ca0b1d3c-419e-43ae-b750-8257c4e1e4c4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391308135 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.1391308135
Directory /workspace/15.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_rw.3033315744
Short name T1139
Test name
Test status
Simulation time 27919469 ps
CPU time 0.57 seconds
Started Jun 07 07:11:34 PM PDT 24
Finished Jun 07 07:11:45 PM PDT 24
Peak memory 196136 kb
Host smart-f19a25c9-d1c2-48ed-aafa-cf1ffbd4cb8e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033315744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.3033315744
Directory /workspace/15.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.uart_intr_test.3457427748
Short name T1144
Test name
Test status
Simulation time 13780002 ps
CPU time 0.59 seconds
Started Jun 07 07:11:34 PM PDT 24
Finished Jun 07 07:11:45 PM PDT 24
Peak memory 195176 kb
Host smart-ba784c41-eec1-4194-a4fd-180e2fb3745e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457427748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.3457427748
Directory /workspace/15.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.3437514237
Short name T77
Test name
Test status
Simulation time 78943036 ps
CPU time 0.69 seconds
Started Jun 07 07:11:37 PM PDT 24
Finished Jun 07 07:11:49 PM PDT 24
Peak memory 195720 kb
Host smart-d2c54bc2-b7c1-4eb1-8752-1bf6a66eceb7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437514237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_cs
r_outstanding.3437514237
Directory /workspace/15.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_errors.425334787
Short name T1194
Test name
Test status
Simulation time 158598648 ps
CPU time 2.02 seconds
Started Jun 07 07:11:36 PM PDT 24
Finished Jun 07 07:11:49 PM PDT 24
Peak memory 200696 kb
Host smart-c7099251-21a1-4462-bb92-4695e3f5dbfb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425334787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.425334787
Directory /workspace/15.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.631358859
Short name T1180
Test name
Test status
Simulation time 293677191 ps
CPU time 1.34 seconds
Started Jun 07 07:11:39 PM PDT 24
Finished Jun 07 07:11:52 PM PDT 24
Peak memory 199916 kb
Host smart-4abde89b-1e2c-4db4-913d-f3359e881d93
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631358859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.631358859
Directory /workspace/15.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.4257637762
Short name T1105
Test name
Test status
Simulation time 90079563 ps
CPU time 0.99 seconds
Started Jun 07 07:11:33 PM PDT 24
Finished Jun 07 07:11:44 PM PDT 24
Peak memory 200584 kb
Host smart-b1f3faaa-e3c9-438c-8957-cab61ee27f43
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257637762 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.4257637762
Directory /workspace/16.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_rw.3905716033
Short name T1178
Test name
Test status
Simulation time 44512789 ps
CPU time 0.62 seconds
Started Jun 07 07:11:39 PM PDT 24
Finished Jun 07 07:11:51 PM PDT 24
Peak memory 196200 kb
Host smart-660502a7-6e67-4b95-854d-afcb0cc2a7fd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905716033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.3905716033
Directory /workspace/16.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.uart_intr_test.137174894
Short name T1129
Test name
Test status
Simulation time 47606855 ps
CPU time 0.58 seconds
Started Jun 07 07:11:35 PM PDT 24
Finished Jun 07 07:11:46 PM PDT 24
Peak memory 195204 kb
Host smart-1162bc50-bf61-423f-bc9e-138c1f06b664
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137174894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.137174894
Directory /workspace/16.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.3852412858
Short name T1198
Test name
Test status
Simulation time 30782279 ps
CPU time 0.74 seconds
Started Jun 07 07:11:36 PM PDT 24
Finished Jun 07 07:11:48 PM PDT 24
Peak memory 197708 kb
Host smart-c07e7556-ae34-48d5-8ea6-97751bb1dd8e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852412858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_cs
r_outstanding.3852412858
Directory /workspace/16.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_errors.3596042929
Short name T1103
Test name
Test status
Simulation time 286171680 ps
CPU time 1.53 seconds
Started Jun 07 07:11:37 PM PDT 24
Finished Jun 07 07:11:50 PM PDT 24
Peak memory 200852 kb
Host smart-c496b1d4-2509-4883-8930-875b2960f705
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596042929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.3596042929
Directory /workspace/16.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.703282487
Short name T128
Test name
Test status
Simulation time 164113010 ps
CPU time 1.24 seconds
Started Jun 07 07:11:39 PM PDT 24
Finished Jun 07 07:11:52 PM PDT 24
Peak memory 199876 kb
Host smart-f2f16a1c-d33d-4ca8-90ec-c4145fc0df6a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703282487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.703282487
Directory /workspace/16.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.3872470917
Short name T1154
Test name
Test status
Simulation time 176981444 ps
CPU time 1.19 seconds
Started Jun 07 07:11:36 PM PDT 24
Finished Jun 07 07:11:47 PM PDT 24
Peak memory 200788 kb
Host smart-d53373b5-a420-4c70-bc86-c7a0508b7b66
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872470917 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.3872470917
Directory /workspace/17.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_rw.2710827939
Short name T1164
Test name
Test status
Simulation time 40749345 ps
CPU time 0.57 seconds
Started Jun 07 07:11:37 PM PDT 24
Finished Jun 07 07:11:49 PM PDT 24
Peak memory 196108 kb
Host smart-4ffc59e5-3ebc-4e1c-9303-d8876057a806
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710827939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.2710827939
Directory /workspace/17.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.uart_intr_test.821324630
Short name T1156
Test name
Test status
Simulation time 18019185 ps
CPU time 0.59 seconds
Started Jun 07 07:11:36 PM PDT 24
Finished Jun 07 07:11:47 PM PDT 24
Peak memory 195140 kb
Host smart-2baf06bd-7968-41cd-9467-50aae9f1e94d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821324630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.821324630
Directory /workspace/17.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.159033986
Short name T1163
Test name
Test status
Simulation time 139723657 ps
CPU time 0.7 seconds
Started Jun 07 07:11:34 PM PDT 24
Finished Jun 07 07:11:44 PM PDT 24
Peak memory 196320 kb
Host smart-6cae6cdd-6666-49bf-b022-a692ae43e9d8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159033986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_csr
_outstanding.159033986
Directory /workspace/17.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_errors.859466541
Short name T1150
Test name
Test status
Simulation time 68488998 ps
CPU time 1.01 seconds
Started Jun 07 07:11:37 PM PDT 24
Finished Jun 07 07:11:49 PM PDT 24
Peak memory 200692 kb
Host smart-7af9daef-9593-4fe2-b502-d216d924850f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859466541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.859466541
Directory /workspace/17.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.257532000
Short name T89
Test name
Test status
Simulation time 168408963 ps
CPU time 1 seconds
Started Jun 07 07:11:39 PM PDT 24
Finished Jun 07 07:11:52 PM PDT 24
Peak memory 199780 kb
Host smart-80867861-2786-40c2-9ce0-a75f5e20ecfb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257532000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.257532000
Directory /workspace/17.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.3429034547
Short name T1183
Test name
Test status
Simulation time 29387027 ps
CPU time 0.92 seconds
Started Jun 07 07:11:35 PM PDT 24
Finished Jun 07 07:11:46 PM PDT 24
Peak memory 200556 kb
Host smart-2d56c106-7c49-4cb6-abc3-f7a19dfb3967
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429034547 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.3429034547
Directory /workspace/18.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_rw.1355304435
Short name T1153
Test name
Test status
Simulation time 40270866 ps
CPU time 0.63 seconds
Started Jun 07 07:11:39 PM PDT 24
Finished Jun 07 07:11:51 PM PDT 24
Peak memory 196152 kb
Host smart-5e584108-a3a3-434b-8929-4dd53ed5621b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355304435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.1355304435
Directory /workspace/18.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.uart_intr_test.2880432527
Short name T1098
Test name
Test status
Simulation time 22531112 ps
CPU time 0.59 seconds
Started Jun 07 07:11:36 PM PDT 24
Finished Jun 07 07:11:47 PM PDT 24
Peak memory 195200 kb
Host smart-b181d9de-8fa6-42f8-b604-c260599d0544
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880432527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.2880432527
Directory /workspace/18.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.2874199784
Short name T1191
Test name
Test status
Simulation time 22732823 ps
CPU time 0.75 seconds
Started Jun 07 07:11:34 PM PDT 24
Finished Jun 07 07:11:45 PM PDT 24
Peak memory 197700 kb
Host smart-0851b94e-702a-487b-b86f-6b903d07341f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874199784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_cs
r_outstanding.2874199784
Directory /workspace/18.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_errors.1144606243
Short name T1145
Test name
Test status
Simulation time 73271232 ps
CPU time 1.52 seconds
Started Jun 07 07:11:39 PM PDT 24
Finished Jun 07 07:11:53 PM PDT 24
Peak memory 200820 kb
Host smart-06b7455a-9afc-46c8-b004-33d10feb4bdb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144606243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.1144606243
Directory /workspace/18.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.1613468050
Short name T129
Test name
Test status
Simulation time 146143304 ps
CPU time 0.93 seconds
Started Jun 07 07:11:37 PM PDT 24
Finished Jun 07 07:11:50 PM PDT 24
Peak memory 199432 kb
Host smart-11e06624-32e0-4b7d-90d1-bf8501ad6caa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613468050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.1613468050
Directory /workspace/18.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.1799589811
Short name T1188
Test name
Test status
Simulation time 30475153 ps
CPU time 0.8 seconds
Started Jun 07 07:11:39 PM PDT 24
Finished Jun 07 07:11:52 PM PDT 24
Peak memory 200512 kb
Host smart-6503dbc5-7773-4436-a489-e0db303618b8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799589811 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.1799589811
Directory /workspace/19.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_rw.1577073916
Short name T83
Test name
Test status
Simulation time 16030310 ps
CPU time 0.62 seconds
Started Jun 07 07:11:37 PM PDT 24
Finished Jun 07 07:11:48 PM PDT 24
Peak memory 196096 kb
Host smart-31f916e9-9b3e-4b62-944d-56608311b523
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577073916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.1577073916
Directory /workspace/19.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.uart_intr_test.306908955
Short name T1113
Test name
Test status
Simulation time 47329737 ps
CPU time 0.58 seconds
Started Jun 07 07:11:35 PM PDT 24
Finished Jun 07 07:11:45 PM PDT 24
Peak memory 195164 kb
Host smart-06d2c3be-7b7c-44a7-baf3-ddf051fd0d40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306908955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.306908955
Directory /workspace/19.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.1644303158
Short name T1170
Test name
Test status
Simulation time 20397726 ps
CPU time 0.65 seconds
Started Jun 07 07:11:35 PM PDT 24
Finished Jun 07 07:11:46 PM PDT 24
Peak memory 197388 kb
Host smart-b83cb865-20c7-4168-a49f-002a5c16e826
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644303158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_cs
r_outstanding.1644303158
Directory /workspace/19.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_errors.2477362994
Short name T1195
Test name
Test status
Simulation time 338239701 ps
CPU time 1.78 seconds
Started Jun 07 07:11:36 PM PDT 24
Finished Jun 07 07:11:48 PM PDT 24
Peak memory 200800 kb
Host smart-b5b09bae-7886-4059-92c8-fce0e9287986
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477362994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.2477362994
Directory /workspace/19.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.3381050271
Short name T125
Test name
Test status
Simulation time 241159625 ps
CPU time 0.93 seconds
Started Jun 07 07:11:36 PM PDT 24
Finished Jun 07 07:11:47 PM PDT 24
Peak memory 199620 kb
Host smart-7f09216c-9893-4da3-9c6a-fe7f9b04d7f2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381050271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.3381050271
Directory /workspace/19.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.679620617
Short name T63
Test name
Test status
Simulation time 37074346 ps
CPU time 0.69 seconds
Started Jun 07 07:11:17 PM PDT 24
Finished Jun 07 07:11:28 PM PDT 24
Peak memory 196100 kb
Host smart-254687af-8e13-4ebe-a299-c01fad8d8e9d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679620617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.679620617
Directory /workspace/2.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.3514905787
Short name T1148
Test name
Test status
Simulation time 252768702 ps
CPU time 2.55 seconds
Started Jun 07 07:11:25 PM PDT 24
Finished Jun 07 07:11:37 PM PDT 24
Peak memory 198248 kb
Host smart-b80bcc56-a7b9-47dc-9521-040202c3c6a3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514905787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.3514905787
Directory /workspace/2.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.3731119376
Short name T1100
Test name
Test status
Simulation time 40188910 ps
CPU time 0.59 seconds
Started Jun 07 07:11:17 PM PDT 24
Finished Jun 07 07:11:28 PM PDT 24
Peak memory 196136 kb
Host smart-dedde883-cf9f-4e8d-94ee-00a5233a5b02
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731119376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.3731119376
Directory /workspace/2.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.1046436172
Short name T1192
Test name
Test status
Simulation time 101921732 ps
CPU time 1.41 seconds
Started Jun 07 07:11:16 PM PDT 24
Finished Jun 07 07:11:28 PM PDT 24
Peak memory 200856 kb
Host smart-05372737-fbfc-4a89-9334-3aaf0b24832b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046436172 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.1046436172
Directory /workspace/2.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_rw.2176180309
Short name T76
Test name
Test status
Simulation time 11635513 ps
CPU time 0.58 seconds
Started Jun 07 07:11:18 PM PDT 24
Finished Jun 07 07:11:29 PM PDT 24
Peak memory 196108 kb
Host smart-63d966ea-8343-4ccf-b7a5-11d32add8f88
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176180309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.2176180309
Directory /workspace/2.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.uart_intr_test.3115825321
Short name T1196
Test name
Test status
Simulation time 54304815 ps
CPU time 0.6 seconds
Started Jun 07 07:11:17 PM PDT 24
Finished Jun 07 07:11:28 PM PDT 24
Peak memory 195132 kb
Host smart-3ee2ff7f-acae-44ec-85eb-eae11f6e7797
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115825321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.3115825321
Directory /workspace/2.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.738396904
Short name T1215
Test name
Test status
Simulation time 15540558 ps
CPU time 0.61 seconds
Started Jun 07 07:11:16 PM PDT 24
Finished Jun 07 07:11:27 PM PDT 24
Peak memory 195228 kb
Host smart-3c68a4db-2279-4229-8138-af6a25e0d6c9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738396904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr_
outstanding.738396904
Directory /workspace/2.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_errors.3384686690
Short name T1219
Test name
Test status
Simulation time 32830926 ps
CPU time 1.52 seconds
Started Jun 07 07:11:19 PM PDT 24
Finished Jun 07 07:11:30 PM PDT 24
Peak memory 200820 kb
Host smart-77960691-a230-436b-8df4-8f32299c6a32
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384686690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.3384686690
Directory /workspace/2.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.2859806832
Short name T1216
Test name
Test status
Simulation time 91764291 ps
CPU time 1.37 seconds
Started Jun 07 07:11:17 PM PDT 24
Finished Jun 07 07:11:29 PM PDT 24
Peak memory 199968 kb
Host smart-c5fb49df-d719-47d5-a831-c16bc1aa1f31
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859806832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.2859806832
Directory /workspace/2.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.uart_intr_test.388706587
Short name T1169
Test name
Test status
Simulation time 102084670 ps
CPU time 0.62 seconds
Started Jun 07 07:11:36 PM PDT 24
Finished Jun 07 07:11:48 PM PDT 24
Peak memory 195192 kb
Host smart-a12420e1-b112-4c17-8f5d-7318c16fd25c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388706587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.388706587
Directory /workspace/20.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.uart_intr_test.2200952013
Short name T1121
Test name
Test status
Simulation time 47425232 ps
CPU time 0.58 seconds
Started Jun 07 07:11:32 PM PDT 24
Finished Jun 07 07:11:43 PM PDT 24
Peak memory 195188 kb
Host smart-4a680c12-8896-4313-949b-f629bb529f92
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200952013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.2200952013
Directory /workspace/21.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.uart_intr_test.2373568626
Short name T1187
Test name
Test status
Simulation time 86459497 ps
CPU time 0.57 seconds
Started Jun 07 07:11:41 PM PDT 24
Finished Jun 07 07:11:54 PM PDT 24
Peak memory 195112 kb
Host smart-abc0ad76-b8a5-449c-8183-3122e9422bb8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373568626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.2373568626
Directory /workspace/22.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.uart_intr_test.3204809034
Short name T1097
Test name
Test status
Simulation time 15957415 ps
CPU time 0.59 seconds
Started Jun 07 07:11:37 PM PDT 24
Finished Jun 07 07:11:49 PM PDT 24
Peak memory 195100 kb
Host smart-b28325b1-216e-4839-bd58-51b1f4812067
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204809034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.3204809034
Directory /workspace/23.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.uart_intr_test.3095534942
Short name T1130
Test name
Test status
Simulation time 14058038 ps
CPU time 0.57 seconds
Started Jun 07 07:11:38 PM PDT 24
Finished Jun 07 07:11:49 PM PDT 24
Peak memory 195204 kb
Host smart-b4e81e75-9796-4a66-a13d-6cf25c09d38d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095534942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.3095534942
Directory /workspace/24.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.uart_intr_test.2547126245
Short name T1184
Test name
Test status
Simulation time 53537187 ps
CPU time 0.56 seconds
Started Jun 07 07:11:41 PM PDT 24
Finished Jun 07 07:11:54 PM PDT 24
Peak memory 195172 kb
Host smart-4889900b-8655-468f-92e1-ecf217aedd91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547126245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.2547126245
Directory /workspace/25.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.uart_intr_test.461132708
Short name T1114
Test name
Test status
Simulation time 15349060 ps
CPU time 0.56 seconds
Started Jun 07 07:11:44 PM PDT 24
Finished Jun 07 07:11:59 PM PDT 24
Peak memory 195052 kb
Host smart-05868c52-8f98-4b6d-9ea8-471678611bf1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461132708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.461132708
Directory /workspace/26.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.uart_intr_test.3674435182
Short name T1141
Test name
Test status
Simulation time 28489789 ps
CPU time 0.57 seconds
Started Jun 07 07:11:43 PM PDT 24
Finished Jun 07 07:11:56 PM PDT 24
Peak memory 195192 kb
Host smart-b1a2f223-19ac-4251-b386-385b2250dbf4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674435182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.3674435182
Directory /workspace/27.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.uart_intr_test.2138555551
Short name T1161
Test name
Test status
Simulation time 65336385 ps
CPU time 0.55 seconds
Started Jun 07 07:11:44 PM PDT 24
Finished Jun 07 07:11:58 PM PDT 24
Peak memory 195168 kb
Host smart-7c5f917b-e5a4-4708-871e-dad51205e11e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138555551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.2138555551
Directory /workspace/28.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.uart_intr_test.2238153551
Short name T1162
Test name
Test status
Simulation time 54591171 ps
CPU time 0.58 seconds
Started Jun 07 07:11:48 PM PDT 24
Finished Jun 07 07:12:03 PM PDT 24
Peak memory 195104 kb
Host smart-73943e95-c2a8-45e6-b7f9-da3cf75ea28a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238153551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.2238153551
Directory /workspace/29.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.1400455847
Short name T1123
Test name
Test status
Simulation time 37943337 ps
CPU time 0.68 seconds
Started Jun 07 07:11:17 PM PDT 24
Finished Jun 07 07:11:28 PM PDT 24
Peak memory 195988 kb
Host smart-3bf7a071-bced-487e-911a-35554668081d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400455847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.1400455847
Directory /workspace/3.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.3568428125
Short name T1208
Test name
Test status
Simulation time 405588528 ps
CPU time 1.52 seconds
Started Jun 07 07:11:17 PM PDT 24
Finished Jun 07 07:11:29 PM PDT 24
Peak memory 198344 kb
Host smart-6f1f7744-934d-49e7-9673-be3d371850d2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568428125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.3568428125
Directory /workspace/3.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.3868166555
Short name T1157
Test name
Test status
Simulation time 52183602 ps
CPU time 0.58 seconds
Started Jun 07 07:11:18 PM PDT 24
Finished Jun 07 07:11:29 PM PDT 24
Peak memory 196104 kb
Host smart-2f4609d3-a29c-4e9b-b07f-d595a40feb10
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868166555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.3868166555
Directory /workspace/3.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.918827955
Short name T1204
Test name
Test status
Simulation time 102602850 ps
CPU time 0.9 seconds
Started Jun 07 07:11:19 PM PDT 24
Finished Jun 07 07:11:31 PM PDT 24
Peak memory 200648 kb
Host smart-d1d5393c-1d06-4126-9d50-bcf86ee3fbda
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918827955 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.918827955
Directory /workspace/3.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_rw.296893524
Short name T60
Test name
Test status
Simulation time 13912078 ps
CPU time 0.59 seconds
Started Jun 07 07:11:17 PM PDT 24
Finished Jun 07 07:11:28 PM PDT 24
Peak memory 196212 kb
Host smart-cf1376a4-7b0e-445b-b6df-173e7c05336a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296893524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.296893524
Directory /workspace/3.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.uart_intr_test.3026011666
Short name T1213
Test name
Test status
Simulation time 39355911 ps
CPU time 0.58 seconds
Started Jun 07 07:11:15 PM PDT 24
Finished Jun 07 07:11:26 PM PDT 24
Peak memory 195120 kb
Host smart-66589603-9e43-45f7-a3bd-5880e23a1110
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026011666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.3026011666
Directory /workspace/3.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.4168186786
Short name T1131
Test name
Test status
Simulation time 66636567 ps
CPU time 0.65 seconds
Started Jun 07 07:11:26 PM PDT 24
Finished Jun 07 07:11:37 PM PDT 24
Peak memory 196388 kb
Host smart-0f2afa99-2a9b-46b7-8d0b-becfa4a234c5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168186786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr
_outstanding.4168186786
Directory /workspace/3.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_errors.2971720718
Short name T1126
Test name
Test status
Simulation time 88903895 ps
CPU time 2.34 seconds
Started Jun 07 07:11:18 PM PDT 24
Finished Jun 07 07:11:31 PM PDT 24
Peak memory 200820 kb
Host smart-e2aa8269-c03c-4f2c-ab7d-d663741aeed1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971720718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.2971720718
Directory /workspace/3.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.3419473257
Short name T91
Test name
Test status
Simulation time 104042619 ps
CPU time 0.96 seconds
Started Jun 07 07:11:18 PM PDT 24
Finished Jun 07 07:11:29 PM PDT 24
Peak memory 199656 kb
Host smart-328a9303-78f2-4ea5-b619-f3ccac0b8ac7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419473257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.3419473257
Directory /workspace/3.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.uart_intr_test.2759179467
Short name T1101
Test name
Test status
Simulation time 11528315 ps
CPU time 0.63 seconds
Started Jun 07 07:11:44 PM PDT 24
Finished Jun 07 07:11:59 PM PDT 24
Peak memory 195144 kb
Host smart-9f8d7642-56ef-43c2-ac70-4bd7f501c5d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759179467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.2759179467
Directory /workspace/30.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.uart_intr_test.2439481346
Short name T1210
Test name
Test status
Simulation time 17559185 ps
CPU time 0.59 seconds
Started Jun 07 07:11:44 PM PDT 24
Finished Jun 07 07:11:58 PM PDT 24
Peak memory 195164 kb
Host smart-20d2bef5-2cf9-43a9-bef0-379b7f13e724
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439481346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.2439481346
Directory /workspace/31.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.uart_intr_test.4232437532
Short name T1205
Test name
Test status
Simulation time 41758003 ps
CPU time 0.62 seconds
Started Jun 07 07:11:46 PM PDT 24
Finished Jun 07 07:12:02 PM PDT 24
Peak memory 195128 kb
Host smart-fad410e2-48e0-4931-9a98-72dc165a561b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232437532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.4232437532
Directory /workspace/32.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.uart_intr_test.3240621897
Short name T1138
Test name
Test status
Simulation time 16901652 ps
CPU time 0.59 seconds
Started Jun 07 07:11:46 PM PDT 24
Finished Jun 07 07:12:02 PM PDT 24
Peak memory 195152 kb
Host smart-23971e72-4e8b-4539-911a-6f3baaa56f16
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240621897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.3240621897
Directory /workspace/33.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.uart_intr_test.166154215
Short name T1182
Test name
Test status
Simulation time 36242153 ps
CPU time 0.58 seconds
Started Jun 07 07:11:50 PM PDT 24
Finished Jun 07 07:12:06 PM PDT 24
Peak memory 195180 kb
Host smart-9b0c2056-5592-4c8b-b01f-d2c706eb8d08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166154215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.166154215
Directory /workspace/34.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.uart_intr_test.3874211489
Short name T1199
Test name
Test status
Simulation time 17377315 ps
CPU time 0.57 seconds
Started Jun 07 07:11:43 PM PDT 24
Finished Jun 07 07:11:56 PM PDT 24
Peak memory 195152 kb
Host smart-7e2031c6-2ce8-45b1-bb16-fae827143a28
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874211489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.3874211489
Directory /workspace/35.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.uart_intr_test.2486766239
Short name T1111
Test name
Test status
Simulation time 27866402 ps
CPU time 0.58 seconds
Started Jun 07 07:11:42 PM PDT 24
Finished Jun 07 07:11:55 PM PDT 24
Peak memory 195168 kb
Host smart-e48a81ed-3936-48db-9338-255e2c83beab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486766239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.2486766239
Directory /workspace/36.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.uart_intr_test.2329937253
Short name T1146
Test name
Test status
Simulation time 21537950 ps
CPU time 0.59 seconds
Started Jun 07 07:11:44 PM PDT 24
Finished Jun 07 07:11:59 PM PDT 24
Peak memory 195184 kb
Host smart-85a11dad-9798-48c0-9d57-354430e8c5a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329937253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.2329937253
Directory /workspace/37.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.uart_intr_test.2786363309
Short name T1142
Test name
Test status
Simulation time 21993746 ps
CPU time 0.56 seconds
Started Jun 07 07:11:52 PM PDT 24
Finished Jun 07 07:12:09 PM PDT 24
Peak memory 195064 kb
Host smart-0d74a015-0e64-4bae-835a-aec133e14101
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786363309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.2786363309
Directory /workspace/38.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.uart_intr_test.4117939754
Short name T1094
Test name
Test status
Simulation time 143975488 ps
CPU time 0.58 seconds
Started Jun 07 07:11:44 PM PDT 24
Finished Jun 07 07:11:59 PM PDT 24
Peak memory 195144 kb
Host smart-618c7deb-cdd5-4d99-a9b4-f8f7622287ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117939754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.4117939754
Directory /workspace/39.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.3317424254
Short name T62
Test name
Test status
Simulation time 16475221 ps
CPU time 0.66 seconds
Started Jun 07 07:11:26 PM PDT 24
Finished Jun 07 07:11:37 PM PDT 24
Peak memory 195492 kb
Host smart-ec36e0ce-f261-4039-9a9d-f279f00add1e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317424254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.3317424254
Directory /workspace/4.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.1420229919
Short name T1132
Test name
Test status
Simulation time 806688217 ps
CPU time 2.59 seconds
Started Jun 07 07:11:21 PM PDT 24
Finished Jun 07 07:11:34 PM PDT 24
Peak memory 198704 kb
Host smart-c9157a30-4b21-4c7b-98ad-d6479b6ba6bd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420229919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.1420229919
Directory /workspace/4.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.3819217564
Short name T1168
Test name
Test status
Simulation time 18819366 ps
CPU time 0.6 seconds
Started Jun 07 07:11:18 PM PDT 24
Finished Jun 07 07:11:29 PM PDT 24
Peak memory 196164 kb
Host smart-32ae78a9-a11f-41c6-9289-80c5f6f2cdcf
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819217564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.3819217564
Directory /workspace/4.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.994036382
Short name T1143
Test name
Test status
Simulation time 44937812 ps
CPU time 0.66 seconds
Started Jun 07 07:11:26 PM PDT 24
Finished Jun 07 07:11:37 PM PDT 24
Peak memory 197688 kb
Host smart-fb1c35ff-7aac-402b-9a92-821612263b78
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994036382 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.994036382
Directory /workspace/4.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_rw.703109308
Short name T79
Test name
Test status
Simulation time 110000609 ps
CPU time 0.63 seconds
Started Jun 07 07:11:19 PM PDT 24
Finished Jun 07 07:11:30 PM PDT 24
Peak memory 196480 kb
Host smart-e7d5ef66-ba63-41bf-8438-080046098c24
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703109308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.703109308
Directory /workspace/4.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.uart_intr_test.3809676508
Short name T1106
Test name
Test status
Simulation time 27318331 ps
CPU time 0.64 seconds
Started Jun 07 07:11:18 PM PDT 24
Finished Jun 07 07:11:29 PM PDT 24
Peak memory 195172 kb
Host smart-473885fb-2921-4a80-9a3f-71ba380c0b65
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809676508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.3809676508
Directory /workspace/4.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.840827591
Short name T1149
Test name
Test status
Simulation time 19745134 ps
CPU time 0.63 seconds
Started Jun 07 07:11:24 PM PDT 24
Finished Jun 07 07:11:35 PM PDT 24
Peak memory 195360 kb
Host smart-89b2050f-5f15-4bc5-948c-a4fa464c53d2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840827591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr_
outstanding.840827591
Directory /workspace/4.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_errors.3967621866
Short name T1214
Test name
Test status
Simulation time 184631047 ps
CPU time 2.08 seconds
Started Jun 07 07:11:19 PM PDT 24
Finished Jun 07 07:11:32 PM PDT 24
Peak memory 200748 kb
Host smart-485c88e7-6f9f-4abd-a7dd-d6a8fb3e9d74
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967621866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.3967621866
Directory /workspace/4.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.uart_intr_test.3189490047
Short name T1090
Test name
Test status
Simulation time 16162929 ps
CPU time 0.62 seconds
Started Jun 07 07:11:44 PM PDT 24
Finished Jun 07 07:11:59 PM PDT 24
Peak memory 195120 kb
Host smart-f9b7fbd4-4ac5-4b34-aa2a-4f11cf1163d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189490047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.3189490047
Directory /workspace/40.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.uart_intr_test.998091846
Short name T1089
Test name
Test status
Simulation time 13615439 ps
CPU time 0.57 seconds
Started Jun 07 07:11:53 PM PDT 24
Finished Jun 07 07:12:10 PM PDT 24
Peak memory 195144 kb
Host smart-727b90d2-735b-45b4-aedb-5814485e1aee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998091846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.998091846
Directory /workspace/41.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.uart_intr_test.1852424948
Short name T1177
Test name
Test status
Simulation time 13773267 ps
CPU time 0.55 seconds
Started Jun 07 07:11:44 PM PDT 24
Finished Jun 07 07:11:59 PM PDT 24
Peak memory 195080 kb
Host smart-137425f4-6f48-4fb2-b8ee-69bce5fb90e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852424948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.1852424948
Directory /workspace/42.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.uart_intr_test.1584852848
Short name T1104
Test name
Test status
Simulation time 50287084 ps
CPU time 0.59 seconds
Started Jun 07 07:11:46 PM PDT 24
Finished Jun 07 07:12:02 PM PDT 24
Peak memory 195168 kb
Host smart-c4f66837-73c6-4a61-92ed-36ca1f6829aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584852848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.1584852848
Directory /workspace/43.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.uart_intr_test.2589149643
Short name T1171
Test name
Test status
Simulation time 13036509 ps
CPU time 0.57 seconds
Started Jun 07 07:11:46 PM PDT 24
Finished Jun 07 07:12:02 PM PDT 24
Peak memory 195160 kb
Host smart-aaf79929-64a0-4a97-96fa-a426fb2697d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589149643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.2589149643
Directory /workspace/44.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.uart_intr_test.3733554535
Short name T1133
Test name
Test status
Simulation time 15394230 ps
CPU time 0.62 seconds
Started Jun 07 07:11:43 PM PDT 24
Finished Jun 07 07:11:57 PM PDT 24
Peak memory 195188 kb
Host smart-1ebb6426-46cb-416f-9f6e-d8b75833d065
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733554535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.3733554535
Directory /workspace/45.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.uart_intr_test.1692291803
Short name T1179
Test name
Test status
Simulation time 16087314 ps
CPU time 0.57 seconds
Started Jun 07 07:11:42 PM PDT 24
Finished Jun 07 07:11:56 PM PDT 24
Peak memory 195112 kb
Host smart-e5ca6fd9-70a1-482c-8739-5c58e4acd590
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692291803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.1692291803
Directory /workspace/46.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.uart_intr_test.210294913
Short name T1110
Test name
Test status
Simulation time 20243771 ps
CPU time 0.55 seconds
Started Jun 07 07:11:44 PM PDT 24
Finished Jun 07 07:11:58 PM PDT 24
Peak memory 195180 kb
Host smart-7a0a0f1d-47a4-47df-9310-e92084545ea7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210294913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.210294913
Directory /workspace/47.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.uart_intr_test.1667930080
Short name T1203
Test name
Test status
Simulation time 36325872 ps
CPU time 0.57 seconds
Started Jun 07 07:11:46 PM PDT 24
Finished Jun 07 07:12:01 PM PDT 24
Peak memory 195124 kb
Host smart-c42ca49b-2f8d-4031-a236-985224468124
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667930080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.1667930080
Directory /workspace/48.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.uart_intr_test.2088446757
Short name T1117
Test name
Test status
Simulation time 27735096 ps
CPU time 0.59 seconds
Started Jun 07 07:11:43 PM PDT 24
Finished Jun 07 07:11:57 PM PDT 24
Peak memory 195140 kb
Host smart-c16718d6-988c-4c04-afb8-986e0f5a689a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088446757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.2088446757
Directory /workspace/49.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.2196586411
Short name T1086
Test name
Test status
Simulation time 23014023 ps
CPU time 0.75 seconds
Started Jun 07 07:11:27 PM PDT 24
Finished Jun 07 07:11:38 PM PDT 24
Peak memory 199136 kb
Host smart-28d8befa-3c20-4c5e-83c3-3b11ca925177
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196586411 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.2196586411
Directory /workspace/5.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_rw.2009973045
Short name T1092
Test name
Test status
Simulation time 118009874 ps
CPU time 0.6 seconds
Started Jun 07 07:11:26 PM PDT 24
Finished Jun 07 07:11:36 PM PDT 24
Peak memory 196212 kb
Host smart-6b2fc552-fb0d-4971-bc7e-74528b9fdb80
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009973045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.2009973045
Directory /workspace/5.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.uart_intr_test.156849366
Short name T1136
Test name
Test status
Simulation time 73329198 ps
CPU time 0.59 seconds
Started Jun 07 07:11:27 PM PDT 24
Finished Jun 07 07:11:37 PM PDT 24
Peak memory 195128 kb
Host smart-ca8ff836-e6e2-4471-a64b-852325bc82bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156849366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.156849366
Directory /workspace/5.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.3396217843
Short name T1181
Test name
Test status
Simulation time 30000431 ps
CPU time 0.61 seconds
Started Jun 07 07:11:23 PM PDT 24
Finished Jun 07 07:11:34 PM PDT 24
Peak memory 196240 kb
Host smart-c76f0253-7555-4a2a-94fb-c399a8520806
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396217843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr
_outstanding.3396217843
Directory /workspace/5.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_errors.3987701683
Short name T1167
Test name
Test status
Simulation time 57180759 ps
CPU time 1.24 seconds
Started Jun 07 07:11:27 PM PDT 24
Finished Jun 07 07:11:38 PM PDT 24
Peak memory 200840 kb
Host smart-4387e1ab-c6ba-40ce-9438-0b620ff0a8d0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987701683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.3987701683
Directory /workspace/5.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.4128225377
Short name T127
Test name
Test status
Simulation time 43046662 ps
CPU time 1 seconds
Started Jun 07 07:11:27 PM PDT 24
Finished Jun 07 07:11:38 PM PDT 24
Peak memory 200116 kb
Host smart-fa038d0e-6992-4d4f-90b0-b09c28f8e483
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128225377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.4128225377
Directory /workspace/5.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.4240082234
Short name T1155
Test name
Test status
Simulation time 23678422 ps
CPU time 0.81 seconds
Started Jun 07 07:11:26 PM PDT 24
Finished Jun 07 07:11:36 PM PDT 24
Peak memory 199184 kb
Host smart-2b5e4a58-d9d5-4ac2-aba4-c522a19245a0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240082234 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.4240082234
Directory /workspace/6.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_rw.678238518
Short name T66
Test name
Test status
Simulation time 15201533 ps
CPU time 0.59 seconds
Started Jun 07 07:11:27 PM PDT 24
Finished Jun 07 07:11:38 PM PDT 24
Peak memory 196164 kb
Host smart-ddf510fe-46c1-47c7-8516-bae7115b6076
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678238518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.678238518
Directory /workspace/6.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.uart_intr_test.2815839701
Short name T1147
Test name
Test status
Simulation time 17030148 ps
CPU time 0.67 seconds
Started Jun 07 07:11:25 PM PDT 24
Finished Jun 07 07:11:36 PM PDT 24
Peak memory 195152 kb
Host smart-71170555-23e0-4b97-994a-1eeaa961062d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815839701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.2815839701
Directory /workspace/6.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.1471646673
Short name T1122
Test name
Test status
Simulation time 88278936 ps
CPU time 0.66 seconds
Started Jun 07 07:11:28 PM PDT 24
Finished Jun 07 07:11:39 PM PDT 24
Peak memory 197536 kb
Host smart-ff260e53-1274-48e7-a15d-ae850ae5bc9d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471646673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr
_outstanding.1471646673
Directory /workspace/6.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_errors.2068452738
Short name T1115
Test name
Test status
Simulation time 153123843 ps
CPU time 2.09 seconds
Started Jun 07 07:11:26 PM PDT 24
Finished Jun 07 07:11:38 PM PDT 24
Peak memory 200780 kb
Host smart-64584ce4-c7df-420d-888f-be2fdf8c21a6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068452738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.2068452738
Directory /workspace/6.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.933440588
Short name T1189
Test name
Test status
Simulation time 229004987 ps
CPU time 0.92 seconds
Started Jun 07 07:11:29 PM PDT 24
Finished Jun 07 07:11:40 PM PDT 24
Peak memory 200568 kb
Host smart-0506ac7f-9105-4562-adae-5f9a3ada5f74
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933440588 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.933440588
Directory /workspace/7.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_rw.1092696853
Short name T61
Test name
Test status
Simulation time 12291680 ps
CPU time 0.63 seconds
Started Jun 07 07:11:29 PM PDT 24
Finished Jun 07 07:11:41 PM PDT 24
Peak memory 196240 kb
Host smart-5941afad-bada-4e7f-8089-f661047f55ad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092696853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.1092696853
Directory /workspace/7.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.uart_intr_test.1382717832
Short name T1102
Test name
Test status
Simulation time 10236400 ps
CPU time 0.55 seconds
Started Jun 07 07:11:26 PM PDT 24
Finished Jun 07 07:11:36 PM PDT 24
Peak memory 195124 kb
Host smart-cdd7ee3b-fd4b-4b1d-96b0-b7a28dbc53b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382717832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.1382717832
Directory /workspace/7.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.3712236075
Short name T1173
Test name
Test status
Simulation time 90100982 ps
CPU time 0.76 seconds
Started Jun 07 07:11:28 PM PDT 24
Finished Jun 07 07:11:39 PM PDT 24
Peak memory 198464 kb
Host smart-7f65cc74-e733-4681-8b1e-ed37b963cd98
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712236075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr
_outstanding.3712236075
Directory /workspace/7.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_errors.2015857332
Short name T1109
Test name
Test status
Simulation time 247645426 ps
CPU time 1.7 seconds
Started Jun 07 07:11:27 PM PDT 24
Finished Jun 07 07:11:39 PM PDT 24
Peak memory 200848 kb
Host smart-9a18ee1c-0e76-4f1c-9c2c-809873a68cf6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015857332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.2015857332
Directory /workspace/7.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.733231271
Short name T1200
Test name
Test status
Simulation time 74527580 ps
CPU time 1.35 seconds
Started Jun 07 07:11:26 PM PDT 24
Finished Jun 07 07:11:37 PM PDT 24
Peak memory 200388 kb
Host smart-6c3f1b83-bbf6-4d43-a67f-b8f96f985fc7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733231271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.733231271
Directory /workspace/7.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.2490044681
Short name T1107
Test name
Test status
Simulation time 32618142 ps
CPU time 0.93 seconds
Started Jun 07 07:11:26 PM PDT 24
Finished Jun 07 07:11:37 PM PDT 24
Peak memory 200628 kb
Host smart-034e2fff-ac44-4b58-8a73-adb401c3cfc0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490044681 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.2490044681
Directory /workspace/8.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_rw.11165023
Short name T65
Test name
Test status
Simulation time 64109318 ps
CPU time 0.56 seconds
Started Jun 07 07:11:26 PM PDT 24
Finished Jun 07 07:11:37 PM PDT 24
Peak memory 196124 kb
Host smart-c74692d4-6bce-4d53-a083-528f7a3106c2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11165023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.11165023
Directory /workspace/8.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.uart_intr_test.805410131
Short name T1160
Test name
Test status
Simulation time 14316724 ps
CPU time 0.56 seconds
Started Jun 07 07:11:25 PM PDT 24
Finished Jun 07 07:11:36 PM PDT 24
Peak memory 195220 kb
Host smart-a59c2ee9-4dd5-40a9-89b8-d70b7dee6ea5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805410131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.805410131
Directory /workspace/8.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.4287075383
Short name T1158
Test name
Test status
Simulation time 54195359 ps
CPU time 0.74 seconds
Started Jun 07 07:11:27 PM PDT 24
Finished Jun 07 07:11:38 PM PDT 24
Peak memory 197596 kb
Host smart-481fe768-736c-45f3-8a93-3a93a9c0ea60
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287075383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr
_outstanding.4287075383
Directory /workspace/8.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_errors.2797020712
Short name T1087
Test name
Test status
Simulation time 90701103 ps
CPU time 1.9 seconds
Started Jun 07 07:11:25 PM PDT 24
Finished Jun 07 07:11:37 PM PDT 24
Peak memory 200764 kb
Host smart-b14cd659-21c5-47a1-99bf-f41e1f7af804
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797020712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.2797020712
Directory /workspace/8.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.3027105279
Short name T126
Test name
Test status
Simulation time 198320188 ps
CPU time 1.27 seconds
Started Jun 07 07:11:24 PM PDT 24
Finished Jun 07 07:11:36 PM PDT 24
Peak memory 200044 kb
Host smart-0c4f81e2-a454-4ede-820e-de95e4fbb444
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027105279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.3027105279
Directory /workspace/8.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.177967199
Short name T1120
Test name
Test status
Simulation time 217962373 ps
CPU time 0.83 seconds
Started Jun 07 07:11:28 PM PDT 24
Finished Jun 07 07:11:39 PM PDT 24
Peak memory 200624 kb
Host smart-7896a3ad-87d7-45b6-adde-02bf984fee4a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177967199 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.177967199
Directory /workspace/9.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_rw.3101760083
Short name T1116
Test name
Test status
Simulation time 30927916 ps
CPU time 0.6 seconds
Started Jun 07 07:11:28 PM PDT 24
Finished Jun 07 07:11:38 PM PDT 24
Peak memory 196136 kb
Host smart-ce216bd7-d909-4a2e-b41f-e1929bf2705b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101760083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.3101760083
Directory /workspace/9.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.uart_intr_test.2082734706
Short name T1209
Test name
Test status
Simulation time 64308344 ps
CPU time 0.58 seconds
Started Jun 07 07:11:26 PM PDT 24
Finished Jun 07 07:11:37 PM PDT 24
Peak memory 195192 kb
Host smart-49d96fd7-0a4b-4fec-a91e-f3e46fe934f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082734706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.2082734706
Directory /workspace/9.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.4279731091
Short name T82
Test name
Test status
Simulation time 17984496 ps
CPU time 0.76 seconds
Started Jun 07 07:11:26 PM PDT 24
Finished Jun 07 07:11:37 PM PDT 24
Peak memory 198380 kb
Host smart-aea2494f-4d74-40c3-8888-447f3cf05636
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279731091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr
_outstanding.4279731091
Directory /workspace/9.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_errors.1224279364
Short name T1140
Test name
Test status
Simulation time 34161924 ps
CPU time 1.03 seconds
Started Jun 07 07:11:28 PM PDT 24
Finished Jun 07 07:11:39 PM PDT 24
Peak memory 200592 kb
Host smart-5ea67457-f44b-43f6-92cf-8628bb9fb7ef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224279364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.1224279364
Directory /workspace/9.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.1156879827
Short name T87
Test name
Test status
Simulation time 435251054 ps
CPU time 1.45 seconds
Started Jun 07 07:11:26 PM PDT 24
Finished Jun 07 07:11:38 PM PDT 24
Peak memory 200164 kb
Host smart-3c9e86db-bb9a-4b02-90bd-920e6097118b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156879827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.1156879827
Directory /workspace/9.uart_tl_intg_err/latest

Test location /workspace/coverage/default/0.uart_alert_test.621749789
Short name T671
Test name
Test status
Simulation time 13383753 ps
CPU time 0.55 seconds
Started Jun 07 07:19:29 PM PDT 24
Finished Jun 07 07:19:49 PM PDT 24
Peak memory 194944 kb
Host smart-f5659086-b7d8-4b03-8052-eee3787ed5e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621749789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.621749789
Directory /workspace/0.uart_alert_test/latest

Test location /workspace/coverage/default/0.uart_fifo_full.1533733945
Short name T549
Test name
Test status
Simulation time 38768840248 ps
CPU time 16.41 seconds
Started Jun 07 07:19:29 PM PDT 24
Finished Jun 07 07:20:05 PM PDT 24
Peak memory 200308 kb
Host smart-9b5bd05e-666e-4e11-bcd9-c98acc575135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533733945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.1533733945
Directory /workspace/0.uart_fifo_full/latest

Test location /workspace/coverage/default/0.uart_fifo_overflow.302499940
Short name T1056
Test name
Test status
Simulation time 29492784016 ps
CPU time 14.22 seconds
Started Jun 07 07:19:28 PM PDT 24
Finished Jun 07 07:20:01 PM PDT 24
Peak memory 200032 kb
Host smart-62b3807b-2ca2-4d7b-9f9c-5728ffc375cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302499940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.302499940
Directory /workspace/0.uart_fifo_overflow/latest

Test location /workspace/coverage/default/0.uart_intr.3110782982
Short name T647
Test name
Test status
Simulation time 18756806169 ps
CPU time 8.79 seconds
Started Jun 07 07:19:31 PM PDT 24
Finished Jun 07 07:19:59 PM PDT 24
Peak memory 198216 kb
Host smart-c9669187-7ce8-4e11-bf53-cb2e8ebf245a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110782982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.3110782982
Directory /workspace/0.uart_intr/latest

Test location /workspace/coverage/default/0.uart_long_xfer_wo_dly.808231690
Short name T946
Test name
Test status
Simulation time 163914492562 ps
CPU time 344.42 seconds
Started Jun 07 07:19:31 PM PDT 24
Finished Jun 07 07:25:35 PM PDT 24
Peak memory 200488 kb
Host smart-b26266a0-ce03-474c-854a-a24b3f10f2ed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=808231690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.808231690
Directory /workspace/0.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/0.uart_loopback.2545260260
Short name T767
Test name
Test status
Simulation time 7735628986 ps
CPU time 4.24 seconds
Started Jun 07 07:19:33 PM PDT 24
Finished Jun 07 07:19:58 PM PDT 24
Peak memory 199800 kb
Host smart-0dc7cf7c-f09b-43c2-b23b-551209473ecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545260260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_loopback.2545260260
Directory /workspace/0.uart_loopback/latest

Test location /workspace/coverage/default/0.uart_noise_filter.4162999947
Short name T348
Test name
Test status
Simulation time 77001433017 ps
CPU time 60.62 seconds
Started Jun 07 07:19:31 PM PDT 24
Finished Jun 07 07:20:51 PM PDT 24
Peak memory 200360 kb
Host smart-b16de4a8-e069-4293-bb8c-539551ee2520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162999947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_noise_filter.4162999947
Directory /workspace/0.uart_noise_filter/latest

Test location /workspace/coverage/default/0.uart_perf.3528515263
Short name T398
Test name
Test status
Simulation time 5917599087 ps
CPU time 294.98 seconds
Started Jun 07 07:19:29 PM PDT 24
Finished Jun 07 07:24:44 PM PDT 24
Peak memory 200344 kb
Host smart-2a8acb28-9bcc-477e-85db-4b1b1a71ea8e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3528515263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.3528515263
Directory /workspace/0.uart_perf/latest

Test location /workspace/coverage/default/0.uart_rx_oversample.1506024403
Short name T17
Test name
Test status
Simulation time 6181693047 ps
CPU time 20.11 seconds
Started Jun 07 07:19:33 PM PDT 24
Finished Jun 07 07:20:14 PM PDT 24
Peak memory 198652 kb
Host smart-54c3e6c0-8094-46d3-b561-8a3f919e2a4d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1506024403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.1506024403
Directory /workspace/0.uart_rx_oversample/latest

Test location /workspace/coverage/default/0.uart_rx_parity_err.473812102
Short name T594
Test name
Test status
Simulation time 22006980121 ps
CPU time 22.19 seconds
Started Jun 07 07:19:30 PM PDT 24
Finished Jun 07 07:20:13 PM PDT 24
Peak memory 200412 kb
Host smart-f997db22-fa67-4d18-b486-331315cbf232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473812102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.473812102
Directory /workspace/0.uart_rx_parity_err/latest

Test location /workspace/coverage/default/0.uart_rx_start_bit_filter.2828969914
Short name T603
Test name
Test status
Simulation time 2507525676 ps
CPU time 1.52 seconds
Started Jun 07 07:19:34 PM PDT 24
Finished Jun 07 07:19:56 PM PDT 24
Peak memory 195992 kb
Host smart-451600c3-c68c-4022-adf2-df1884550972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828969914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.2828969914
Directory /workspace/0.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/0.uart_sec_cm.2516565879
Short name T34
Test name
Test status
Simulation time 107165842 ps
CPU time 0.78 seconds
Started Jun 07 07:19:31 PM PDT 24
Finished Jun 07 07:19:51 PM PDT 24
Peak memory 218744 kb
Host smart-2adabe92-c7e7-44a8-88b2-3556af72def1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516565879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.2516565879
Directory /workspace/0.uart_sec_cm/latest

Test location /workspace/coverage/default/0.uart_smoke.1113079427
Short name T758
Test name
Test status
Simulation time 5371341199 ps
CPU time 10.26 seconds
Started Jun 07 07:19:31 PM PDT 24
Finished Jun 07 07:20:01 PM PDT 24
Peak memory 200100 kb
Host smart-f3563fea-e325-48d1-ad8a-918854167f26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113079427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_smoke.1113079427
Directory /workspace/0.uart_smoke/latest

Test location /workspace/coverage/default/0.uart_stress_all.2988615611
Short name T110
Test name
Test status
Simulation time 330629605798 ps
CPU time 1860.5 seconds
Started Jun 07 07:19:34 PM PDT 24
Finished Jun 07 07:50:55 PM PDT 24
Peak memory 200228 kb
Host smart-d5c7edf7-ff9a-403e-aa29-ecf1c7f981c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988615611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.2988615611
Directory /workspace/0.uart_stress_all/latest

Test location /workspace/coverage/default/0.uart_tx_ovrd.690689179
Short name T705
Test name
Test status
Simulation time 2182455026 ps
CPU time 2 seconds
Started Jun 07 07:19:35 PM PDT 24
Finished Jun 07 07:19:58 PM PDT 24
Peak memory 199228 kb
Host smart-59d6a45d-e089-48a3-b8ff-b40090238302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690689179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.690689179
Directory /workspace/0.uart_tx_ovrd/latest

Test location /workspace/coverage/default/0.uart_tx_rx.1617866233
Short name T351
Test name
Test status
Simulation time 10338701941 ps
CPU time 18.27 seconds
Started Jun 07 07:19:31 PM PDT 24
Finished Jun 07 07:20:09 PM PDT 24
Peak memory 199300 kb
Host smart-2cd48607-57bc-4920-9038-d3da1a3d61a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617866233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.1617866233
Directory /workspace/0.uart_tx_rx/latest

Test location /workspace/coverage/default/1.uart_fifo_full.1750118464
Short name T715
Test name
Test status
Simulation time 18196757388 ps
CPU time 17.29 seconds
Started Jun 07 07:19:33 PM PDT 24
Finished Jun 07 07:20:11 PM PDT 24
Peak memory 200268 kb
Host smart-915bb4b3-4ca0-45bf-ae46-226f6e37c5db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750118464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.1750118464
Directory /workspace/1.uart_fifo_full/latest

Test location /workspace/coverage/default/1.uart_fifo_overflow.3578165310
Short name T278
Test name
Test status
Simulation time 39931883283 ps
CPU time 13.51 seconds
Started Jun 07 07:19:34 PM PDT 24
Finished Jun 07 07:20:08 PM PDT 24
Peak memory 200220 kb
Host smart-da0d3004-d4ec-4c26-8c92-eb9772dfcb3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578165310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.3578165310
Directory /workspace/1.uart_fifo_overflow/latest

Test location /workspace/coverage/default/1.uart_fifo_reset.4278358976
Short name T240
Test name
Test status
Simulation time 25849287619 ps
CPU time 35.02 seconds
Started Jun 07 07:19:41 PM PDT 24
Finished Jun 07 07:20:38 PM PDT 24
Peak memory 200420 kb
Host smart-93eb6198-c1eb-4974-9424-19b5d47f35ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278358976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.4278358976
Directory /workspace/1.uart_fifo_reset/latest

Test location /workspace/coverage/default/1.uart_intr.373602075
Short name T885
Test name
Test status
Simulation time 98618611324 ps
CPU time 150.25 seconds
Started Jun 07 07:19:45 PM PDT 24
Finished Jun 07 07:22:40 PM PDT 24
Peak memory 198264 kb
Host smart-2d080c68-6854-4227-9f6d-0633bd6a3f2e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373602075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.373602075
Directory /workspace/1.uart_intr/latest

Test location /workspace/coverage/default/1.uart_long_xfer_wo_dly.3525657249
Short name T1060
Test name
Test status
Simulation time 82313136193 ps
CPU time 711.59 seconds
Started Jun 07 07:19:42 PM PDT 24
Finished Jun 07 07:31:57 PM PDT 24
Peak memory 200432 kb
Host smart-b27d6618-108f-41d2-be77-ac845056e386
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3525657249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.3525657249
Directory /workspace/1.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/1.uart_loopback.3574875734
Short name T833
Test name
Test status
Simulation time 8644028898 ps
CPU time 15.42 seconds
Started Jun 07 07:19:43 PM PDT 24
Finished Jun 07 07:20:21 PM PDT 24
Peak memory 200196 kb
Host smart-0fd34be3-9d37-474b-b870-af6c64969050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574875734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_loopback.3574875734
Directory /workspace/1.uart_loopback/latest

Test location /workspace/coverage/default/1.uart_perf.2103779341
Short name T402
Test name
Test status
Simulation time 25451041893 ps
CPU time 1153.38 seconds
Started Jun 07 07:19:40 PM PDT 24
Finished Jun 07 07:39:17 PM PDT 24
Peak memory 200388 kb
Host smart-b4426441-5811-40e0-9c06-700a903a8319
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2103779341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.2103779341
Directory /workspace/1.uart_perf/latest

Test location /workspace/coverage/default/1.uart_rx_oversample.2727892139
Short name T365
Test name
Test status
Simulation time 4108573423 ps
CPU time 18.69 seconds
Started Jun 07 07:19:41 PM PDT 24
Finished Jun 07 07:20:22 PM PDT 24
Peak memory 199388 kb
Host smart-680440ed-4809-43c8-b3ee-1147e11a1a1c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2727892139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.2727892139
Directory /workspace/1.uart_rx_oversample/latest

Test location /workspace/coverage/default/1.uart_rx_start_bit_filter.587627018
Short name T846
Test name
Test status
Simulation time 2126041286 ps
CPU time 4.43 seconds
Started Jun 07 07:19:40 PM PDT 24
Finished Jun 07 07:20:08 PM PDT 24
Peak memory 196012 kb
Host smart-3cecd114-ea8a-4622-b33d-b84e64787692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587627018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.587627018
Directory /workspace/1.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/1.uart_sec_cm.1888823202
Short name T33
Test name
Test status
Simulation time 220739508 ps
CPU time 0.86 seconds
Started Jun 07 07:19:41 PM PDT 24
Finished Jun 07 07:20:05 PM PDT 24
Peak memory 218672 kb
Host smart-57ac56c0-51b1-47b2-9d0f-be97e67de144
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888823202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.1888823202
Directory /workspace/1.uart_sec_cm/latest

Test location /workspace/coverage/default/1.uart_smoke.2235441205
Short name T994
Test name
Test status
Simulation time 452901879 ps
CPU time 1.92 seconds
Started Jun 07 07:19:29 PM PDT 24
Finished Jun 07 07:19:51 PM PDT 24
Peak memory 198672 kb
Host smart-b029a719-7ae2-4445-a935-d524b9cb01fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235441205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_smoke.2235441205
Directory /workspace/1.uart_smoke/latest

Test location /workspace/coverage/default/1.uart_stress_all.1675320051
Short name T716
Test name
Test status
Simulation time 71747276221 ps
CPU time 119.01 seconds
Started Jun 07 07:19:42 PM PDT 24
Finished Jun 07 07:22:04 PM PDT 24
Peak memory 200428 kb
Host smart-7eee2cd2-8704-4584-88db-7dc10a4063da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675320051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.1675320051
Directory /workspace/1.uart_stress_all/latest

Test location /workspace/coverage/default/1.uart_tx_ovrd.719928887
Short name T932
Test name
Test status
Simulation time 1312409638 ps
CPU time 2.9 seconds
Started Jun 07 07:19:42 PM PDT 24
Finished Jun 07 07:20:08 PM PDT 24
Peak memory 199976 kb
Host smart-7c63d692-5829-446a-b74c-464d824d43a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719928887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.719928887
Directory /workspace/1.uart_tx_ovrd/latest

Test location /workspace/coverage/default/1.uart_tx_rx.988080861
Short name T691
Test name
Test status
Simulation time 27712245889 ps
CPU time 45.07 seconds
Started Jun 07 07:19:29 PM PDT 24
Finished Jun 07 07:20:34 PM PDT 24
Peak memory 200380 kb
Host smart-281edf9b-a87e-4e1b-8f64-e64f102a28a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988080861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.988080861
Directory /workspace/1.uart_tx_rx/latest

Test location /workspace/coverage/default/10.uart_alert_test.3879048142
Short name T609
Test name
Test status
Simulation time 50383129 ps
CPU time 0.57 seconds
Started Jun 07 07:20:39 PM PDT 24
Finished Jun 07 07:20:57 PM PDT 24
Peak memory 196020 kb
Host smart-7258345f-6af0-485e-9c0f-96f374df41dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879048142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.3879048142
Directory /workspace/10.uart_alert_test/latest

Test location /workspace/coverage/default/10.uart_fifo_full.493319477
Short name T1035
Test name
Test status
Simulation time 196945638131 ps
CPU time 72.59 seconds
Started Jun 07 07:20:41 PM PDT 24
Finished Jun 07 07:22:09 PM PDT 24
Peak memory 200352 kb
Host smart-378be014-0148-4395-8125-7528db3a68d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493319477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.493319477
Directory /workspace/10.uart_fifo_full/latest

Test location /workspace/coverage/default/10.uart_fifo_overflow.3975811838
Short name T645
Test name
Test status
Simulation time 89324460281 ps
CPU time 78.58 seconds
Started Jun 07 07:20:39 PM PDT 24
Finished Jun 07 07:22:15 PM PDT 24
Peak memory 200288 kb
Host smart-4bc459e0-762c-476d-8c61-1cd3b8c5c616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975811838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.3975811838
Directory /workspace/10.uart_fifo_overflow/latest

Test location /workspace/coverage/default/10.uart_fifo_reset.476094455
Short name T173
Test name
Test status
Simulation time 53326125755 ps
CPU time 10.42 seconds
Started Jun 07 07:20:41 PM PDT 24
Finished Jun 07 07:21:07 PM PDT 24
Peak memory 200060 kb
Host smart-5017dc1a-3c8d-4e91-88c0-fa37805d0dc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476094455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.476094455
Directory /workspace/10.uart_fifo_reset/latest

Test location /workspace/coverage/default/10.uart_intr.3590089556
Short name T878
Test name
Test status
Simulation time 26091580585 ps
CPU time 11.65 seconds
Started Jun 07 07:20:40 PM PDT 24
Finished Jun 07 07:21:08 PM PDT 24
Peak memory 200388 kb
Host smart-0d7cd25e-f647-4583-8b1f-487860781863
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590089556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.3590089556
Directory /workspace/10.uart_intr/latest

Test location /workspace/coverage/default/10.uart_long_xfer_wo_dly.2893131385
Short name T924
Test name
Test status
Simulation time 42254505594 ps
CPU time 263.36 seconds
Started Jun 07 07:20:41 PM PDT 24
Finished Jun 07 07:25:20 PM PDT 24
Peak memory 200304 kb
Host smart-b4d6b2eb-bc45-490f-a2b0-e84f9ba7de0f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2893131385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.2893131385
Directory /workspace/10.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/10.uart_loopback.3319500587
Short name T415
Test name
Test status
Simulation time 2469507624 ps
CPU time 1.89 seconds
Started Jun 07 07:20:40 PM PDT 24
Finished Jun 07 07:20:58 PM PDT 24
Peak memory 197576 kb
Host smart-b5f9d6f7-dd2c-4b7d-9341-e45d8ef4f9c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319500587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_loopback.3319500587
Directory /workspace/10.uart_loopback/latest

Test location /workspace/coverage/default/10.uart_perf.4192508247
Short name T434
Test name
Test status
Simulation time 20184098663 ps
CPU time 1036.73 seconds
Started Jun 07 07:20:42 PM PDT 24
Finished Jun 07 07:38:14 PM PDT 24
Peak memory 200356 kb
Host smart-22cba022-5799-4dda-9dde-9a91c1ffb41b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4192508247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.4192508247
Directory /workspace/10.uart_perf/latest

Test location /workspace/coverage/default/10.uart_rx_oversample.1892785887
Short name T842
Test name
Test status
Simulation time 4213861052 ps
CPU time 19.95 seconds
Started Jun 07 07:20:40 PM PDT 24
Finished Jun 07 07:21:16 PM PDT 24
Peak memory 199772 kb
Host smart-f8dda8c9-37e2-4449-8772-e7a0331149a5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1892785887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.1892785887
Directory /workspace/10.uart_rx_oversample/latest

Test location /workspace/coverage/default/10.uart_rx_parity_err.2930007603
Short name T766
Test name
Test status
Simulation time 44769979034 ps
CPU time 15.98 seconds
Started Jun 07 07:20:44 PM PDT 24
Finished Jun 07 07:21:15 PM PDT 24
Peak memory 200300 kb
Host smart-0e4873d3-0c46-4f57-9dfe-a501089abb89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930007603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.2930007603
Directory /workspace/10.uart_rx_parity_err/latest

Test location /workspace/coverage/default/10.uart_rx_start_bit_filter.219722155
Short name T762
Test name
Test status
Simulation time 3074438571 ps
CPU time 3.66 seconds
Started Jun 07 07:20:40 PM PDT 24
Finished Jun 07 07:21:00 PM PDT 24
Peak memory 196616 kb
Host smart-2118898f-6503-4000-93fd-80f4db589a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219722155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.219722155
Directory /workspace/10.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/10.uart_smoke.349727715
Short name T548
Test name
Test status
Simulation time 270012919 ps
CPU time 1.3 seconds
Started Jun 07 07:20:40 PM PDT 24
Finished Jun 07 07:20:57 PM PDT 24
Peak memory 198632 kb
Host smart-0d1c6f58-d8a1-400b-8f75-901520a234e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349727715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_smoke.349727715
Directory /workspace/10.uart_smoke/latest

Test location /workspace/coverage/default/10.uart_stress_all_with_rand_reset.3984628872
Short name T107
Test name
Test status
Simulation time 54947210132 ps
CPU time 464.04 seconds
Started Jun 07 07:20:42 PM PDT 24
Finished Jun 07 07:28:42 PM PDT 24
Peak memory 216980 kb
Host smart-3a569438-b29c-4ecc-90a3-c6cae3ef133d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984628872 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 10.uart_stress_all_with_rand_reset.3984628872
Directory /workspace/10.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.uart_tx_ovrd.2563396845
Short name T778
Test name
Test status
Simulation time 1505352697 ps
CPU time 2.88 seconds
Started Jun 07 07:20:41 PM PDT 24
Finished Jun 07 07:21:00 PM PDT 24
Peak memory 198612 kb
Host smart-c4fcece9-ce68-477c-832e-00b762f4c8f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563396845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.2563396845
Directory /workspace/10.uart_tx_ovrd/latest

Test location /workspace/coverage/default/10.uart_tx_rx.855714913
Short name T303
Test name
Test status
Simulation time 80566237501 ps
CPU time 82.8 seconds
Started Jun 07 07:20:38 PM PDT 24
Finished Jun 07 07:22:18 PM PDT 24
Peak memory 200320 kb
Host smart-207cdbe3-dcb3-47e6-aee9-f4a84d42190e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855714913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.855714913
Directory /workspace/10.uart_tx_rx/latest

Test location /workspace/coverage/default/100.uart_fifo_reset.3143468374
Short name T48
Test name
Test status
Simulation time 40002429011 ps
CPU time 17.21 seconds
Started Jun 07 07:26:14 PM PDT 24
Finished Jun 07 07:26:36 PM PDT 24
Peak memory 200312 kb
Host smart-f6c86e8f-ec0a-4a15-a4da-d8c5d305f8a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143468374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.3143468374
Directory /workspace/100.uart_fifo_reset/latest

Test location /workspace/coverage/default/101.uart_fifo_reset.2205973847
Short name T978
Test name
Test status
Simulation time 132260358733 ps
CPU time 55.63 seconds
Started Jun 07 07:26:12 PM PDT 24
Finished Jun 07 07:27:13 PM PDT 24
Peak memory 200084 kb
Host smart-af1b4cf8-37d0-4259-ac08-6d6c8645771f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205973847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.2205973847
Directory /workspace/101.uart_fifo_reset/latest

Test location /workspace/coverage/default/102.uart_fifo_reset.3447652589
Short name T817
Test name
Test status
Simulation time 14240991606 ps
CPU time 7.71 seconds
Started Jun 07 07:26:15 PM PDT 24
Finished Jun 07 07:26:28 PM PDT 24
Peak memory 200380 kb
Host smart-dc4831aa-f071-4613-b6fe-0c60ef27d788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447652589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.3447652589
Directory /workspace/102.uart_fifo_reset/latest

Test location /workspace/coverage/default/103.uart_fifo_reset.2606317060
Short name T234
Test name
Test status
Simulation time 15502654719 ps
CPU time 12.8 seconds
Started Jun 07 07:26:12 PM PDT 24
Finished Jun 07 07:26:31 PM PDT 24
Peak memory 199404 kb
Host smart-ef9f1aa7-52a7-40c7-893c-86e5012d763e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606317060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.2606317060
Directory /workspace/103.uart_fifo_reset/latest

Test location /workspace/coverage/default/104.uart_fifo_reset.430614688
Short name T798
Test name
Test status
Simulation time 28846682298 ps
CPU time 28.78 seconds
Started Jun 07 07:26:16 PM PDT 24
Finished Jun 07 07:26:51 PM PDT 24
Peak memory 200432 kb
Host smart-5f6335c0-3030-4914-a46e-3395c1e04ba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430614688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.430614688
Directory /workspace/104.uart_fifo_reset/latest

Test location /workspace/coverage/default/105.uart_fifo_reset.3600588822
Short name T204
Test name
Test status
Simulation time 28210739124 ps
CPU time 66.14 seconds
Started Jun 07 07:26:22 PM PDT 24
Finished Jun 07 07:27:35 PM PDT 24
Peak memory 200336 kb
Host smart-618bad2a-3ad4-4961-8739-e8bcaf26e8e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600588822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.3600588822
Directory /workspace/105.uart_fifo_reset/latest

Test location /workspace/coverage/default/106.uart_fifo_reset.1236027185
Short name T263
Test name
Test status
Simulation time 20187557895 ps
CPU time 36.09 seconds
Started Jun 07 07:26:21 PM PDT 24
Finished Jun 07 07:27:03 PM PDT 24
Peak memory 200380 kb
Host smart-f93deb0d-38ec-4ac3-8af5-89df9acdec5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236027185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.1236027185
Directory /workspace/106.uart_fifo_reset/latest

Test location /workspace/coverage/default/107.uart_fifo_reset.1922466768
Short name T952
Test name
Test status
Simulation time 169380671101 ps
CPU time 60.62 seconds
Started Jun 07 07:26:23 PM PDT 24
Finished Jun 07 07:27:29 PM PDT 24
Peak memory 200288 kb
Host smart-f132c149-4c70-42f0-8de6-b5a466fcdd17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922466768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.1922466768
Directory /workspace/107.uart_fifo_reset/latest

Test location /workspace/coverage/default/108.uart_fifo_reset.3965684217
Short name T499
Test name
Test status
Simulation time 33613764638 ps
CPU time 10.79 seconds
Started Jun 07 07:26:23 PM PDT 24
Finished Jun 07 07:26:40 PM PDT 24
Peak memory 200404 kb
Host smart-f102f51a-7442-45ab-a809-0919cf589377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965684217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.3965684217
Directory /workspace/108.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_alert_test.2473602240
Short name T1021
Test name
Test status
Simulation time 14789691 ps
CPU time 0.54 seconds
Started Jun 07 07:20:47 PM PDT 24
Finished Jun 07 07:21:01 PM PDT 24
Peak memory 195436 kb
Host smart-85c212ad-8b23-43a9-9b9c-555293286668
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473602240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.2473602240
Directory /workspace/11.uart_alert_test/latest

Test location /workspace/coverage/default/11.uart_fifo_full.1286849819
Short name T953
Test name
Test status
Simulation time 122480994913 ps
CPU time 59.35 seconds
Started Jun 07 07:20:45 PM PDT 24
Finished Jun 07 07:21:59 PM PDT 24
Peak memory 200352 kb
Host smart-1459842b-2e81-467c-bc08-e00faf1dbba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286849819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.1286849819
Directory /workspace/11.uart_fifo_full/latest

Test location /workspace/coverage/default/11.uart_fifo_overflow.2241102527
Short name T579
Test name
Test status
Simulation time 55012768758 ps
CPU time 22.78 seconds
Started Jun 07 07:20:38 PM PDT 24
Finished Jun 07 07:21:18 PM PDT 24
Peak memory 200348 kb
Host smart-5408fe06-8ea2-462b-8312-25f360d9a3ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241102527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.2241102527
Directory /workspace/11.uart_fifo_overflow/latest

Test location /workspace/coverage/default/11.uart_long_xfer_wo_dly.2552151461
Short name T912
Test name
Test status
Simulation time 169709724346 ps
CPU time 406.14 seconds
Started Jun 07 07:20:51 PM PDT 24
Finished Jun 07 07:27:48 PM PDT 24
Peak memory 200372 kb
Host smart-b74828b6-31e5-4fec-899b-16553c71989a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2552151461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.2552151461
Directory /workspace/11.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/11.uart_loopback.1887532988
Short name T851
Test name
Test status
Simulation time 6502458181 ps
CPU time 3.44 seconds
Started Jun 07 07:20:49 PM PDT 24
Finished Jun 07 07:21:05 PM PDT 24
Peak memory 199092 kb
Host smart-80766cbd-9f4a-4717-9319-726c63e3ce8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887532988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_loopback.1887532988
Directory /workspace/11.uart_loopback/latest

Test location /workspace/coverage/default/11.uart_perf.1961361301
Short name T844
Test name
Test status
Simulation time 7690615261 ps
CPU time 106.39 seconds
Started Jun 07 07:20:51 PM PDT 24
Finished Jun 07 07:22:48 PM PDT 24
Peak memory 200136 kb
Host smart-9cf865fc-7fa3-40e5-b5a2-ff1cd94af3b4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1961361301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.1961361301
Directory /workspace/11.uart_perf/latest

Test location /workspace/coverage/default/11.uart_rx_oversample.1528856588
Short name T368
Test name
Test status
Simulation time 5959912249 ps
CPU time 2.99 seconds
Started Jun 07 07:20:44 PM PDT 24
Finished Jun 07 07:21:02 PM PDT 24
Peak memory 199696 kb
Host smart-0c977509-c125-4cbf-9c7c-784b1ddcf603
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1528856588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.1528856588
Directory /workspace/11.uart_rx_oversample/latest

Test location /workspace/coverage/default/11.uart_rx_parity_err.3464264113
Short name T575
Test name
Test status
Simulation time 83263449723 ps
CPU time 36.18 seconds
Started Jun 07 07:20:47 PM PDT 24
Finished Jun 07 07:21:36 PM PDT 24
Peak memory 200356 kb
Host smart-1bb072d5-652a-4e4d-b5f7-2067c096c6d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464264113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.3464264113
Directory /workspace/11.uart_rx_parity_err/latest

Test location /workspace/coverage/default/11.uart_rx_start_bit_filter.3055515769
Short name T729
Test name
Test status
Simulation time 5289040524 ps
CPU time 8.37 seconds
Started Jun 07 07:20:51 PM PDT 24
Finished Jun 07 07:21:10 PM PDT 24
Peak memory 196676 kb
Host smart-49ec37e3-0005-43a1-b32a-db0407f474a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055515769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.3055515769
Directory /workspace/11.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/11.uart_smoke.2920844994
Short name T1030
Test name
Test status
Simulation time 734728461 ps
CPU time 3.12 seconds
Started Jun 07 07:20:43 PM PDT 24
Finished Jun 07 07:21:02 PM PDT 24
Peak memory 199132 kb
Host smart-d3f76c86-419b-4856-99a2-928de22bf78e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920844994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_smoke.2920844994
Directory /workspace/11.uart_smoke/latest

Test location /workspace/coverage/default/11.uart_stress_all_with_rand_reset.122366292
Short name T617
Test name
Test status
Simulation time 124733377951 ps
CPU time 292.4 seconds
Started Jun 07 07:20:47 PM PDT 24
Finished Jun 07 07:25:53 PM PDT 24
Peak memory 209868 kb
Host smart-102bb028-2ab6-4206-b006-f66d83ea43b4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122366292 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 11.uart_stress_all_with_rand_reset.122366292
Directory /workspace/11.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.uart_tx_ovrd.262221133
Short name T385
Test name
Test status
Simulation time 1448081065 ps
CPU time 3.15 seconds
Started Jun 07 07:20:44 PM PDT 24
Finished Jun 07 07:21:02 PM PDT 24
Peak memory 199720 kb
Host smart-7da2cde0-1c9e-4cc1-9554-ea89553c6dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262221133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.262221133
Directory /workspace/11.uart_tx_ovrd/latest

Test location /workspace/coverage/default/11.uart_tx_rx.125599746
Short name T843
Test name
Test status
Simulation time 72045433245 ps
CPU time 74.17 seconds
Started Jun 07 07:20:44 PM PDT 24
Finished Jun 07 07:22:13 PM PDT 24
Peak memory 200364 kb
Host smart-33210134-2762-4954-9e3b-dad48321986d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125599746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.125599746
Directory /workspace/11.uart_tx_rx/latest

Test location /workspace/coverage/default/110.uart_fifo_reset.963185623
Short name T1039
Test name
Test status
Simulation time 46986501857 ps
CPU time 21.66 seconds
Started Jun 07 07:26:22 PM PDT 24
Finished Jun 07 07:26:50 PM PDT 24
Peak memory 200344 kb
Host smart-b6685480-00b2-41a6-906f-ec71cfbe2cc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963185623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.963185623
Directory /workspace/110.uart_fifo_reset/latest

Test location /workspace/coverage/default/111.uart_fifo_reset.1337319389
Short name T308
Test name
Test status
Simulation time 81255175164 ps
CPU time 175.76 seconds
Started Jun 07 07:26:21 PM PDT 24
Finished Jun 07 07:29:23 PM PDT 24
Peak memory 200280 kb
Host smart-6adbc3ef-3f54-42e7-9c7a-c763422a4509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337319389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.1337319389
Directory /workspace/111.uart_fifo_reset/latest

Test location /workspace/coverage/default/114.uart_fifo_reset.4112916578
Short name T139
Test name
Test status
Simulation time 113564247169 ps
CPU time 56.78 seconds
Started Jun 07 07:26:24 PM PDT 24
Finished Jun 07 07:27:26 PM PDT 24
Peak memory 200448 kb
Host smart-2f7a9f7b-5ba9-4a88-b6e1-57ca01c4b8ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112916578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.4112916578
Directory /workspace/114.uart_fifo_reset/latest

Test location /workspace/coverage/default/115.uart_fifo_reset.1287368339
Short name T1004
Test name
Test status
Simulation time 118685219154 ps
CPU time 41.26 seconds
Started Jun 07 07:26:24 PM PDT 24
Finished Jun 07 07:27:11 PM PDT 24
Peak memory 200200 kb
Host smart-33d6d144-2501-46bf-a830-59587fee1b60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287368339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.1287368339
Directory /workspace/115.uart_fifo_reset/latest

Test location /workspace/coverage/default/116.uart_fifo_reset.806363803
Short name T820
Test name
Test status
Simulation time 148391071031 ps
CPU time 66.21 seconds
Started Jun 07 07:26:23 PM PDT 24
Finished Jun 07 07:27:35 PM PDT 24
Peak memory 200272 kb
Host smart-ea9aa21d-7213-47e9-b2ba-1ebc29a6cf0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806363803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.806363803
Directory /workspace/116.uart_fifo_reset/latest

Test location /workspace/coverage/default/118.uart_fifo_reset.1849373330
Short name T246
Test name
Test status
Simulation time 13655731758 ps
CPU time 22.92 seconds
Started Jun 07 07:26:22 PM PDT 24
Finished Jun 07 07:26:50 PM PDT 24
Peak memory 200272 kb
Host smart-dcf6c092-551e-485e-b625-772ae1b1c452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849373330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.1849373330
Directory /workspace/118.uart_fifo_reset/latest

Test location /workspace/coverage/default/119.uart_fifo_reset.1798809863
Short name T122
Test name
Test status
Simulation time 61374616748 ps
CPU time 28.29 seconds
Started Jun 07 07:26:22 PM PDT 24
Finished Jun 07 07:26:56 PM PDT 24
Peak memory 200388 kb
Host smart-526cd781-9d3b-4048-acb4-f5739431e509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798809863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.1798809863
Directory /workspace/119.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_alert_test.54789665
Short name T360
Test name
Test status
Simulation time 26650754 ps
CPU time 0.57 seconds
Started Jun 07 07:20:55 PM PDT 24
Finished Jun 07 07:21:05 PM PDT 24
Peak memory 195972 kb
Host smart-154d6604-6d5e-44fd-b2a2-7f724f2b3fdd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54789665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.54789665
Directory /workspace/12.uart_alert_test/latest

Test location /workspace/coverage/default/12.uart_fifo_full.2198635746
Short name T1062
Test name
Test status
Simulation time 232035635942 ps
CPU time 81.49 seconds
Started Jun 07 07:20:51 PM PDT 24
Finished Jun 07 07:22:23 PM PDT 24
Peak memory 200180 kb
Host smart-b3529d0d-0830-4b00-9633-ae8806b5c5bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198635746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.2198635746
Directory /workspace/12.uart_fifo_full/latest

Test location /workspace/coverage/default/12.uart_fifo_overflow.4243191557
Short name T174
Test name
Test status
Simulation time 104341555753 ps
CPU time 10.4 seconds
Started Jun 07 07:20:53 PM PDT 24
Finished Jun 07 07:21:14 PM PDT 24
Peak memory 200404 kb
Host smart-e93e0721-17ff-4dca-9262-1988cb319dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243191557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.4243191557
Directory /workspace/12.uart_fifo_overflow/latest

Test location /workspace/coverage/default/12.uart_fifo_reset.3408911113
Short name T813
Test name
Test status
Simulation time 61019101761 ps
CPU time 79.16 seconds
Started Jun 07 07:20:46 PM PDT 24
Finished Jun 07 07:22:19 PM PDT 24
Peak memory 200340 kb
Host smart-9db88234-de0e-4e8e-a300-9d80c140558a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408911113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.3408911113
Directory /workspace/12.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_intr.532958861
Short name T580
Test name
Test status
Simulation time 272161876237 ps
CPU time 528.89 seconds
Started Jun 07 07:20:58 PM PDT 24
Finished Jun 07 07:29:55 PM PDT 24
Peak memory 200344 kb
Host smart-5c94b0c4-6c07-45ef-8976-033b9eb7d868
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532958861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.532958861
Directory /workspace/12.uart_intr/latest

Test location /workspace/coverage/default/12.uart_long_xfer_wo_dly.3587951499
Short name T471
Test name
Test status
Simulation time 239713320374 ps
CPU time 383.58 seconds
Started Jun 07 07:21:04 PM PDT 24
Finished Jun 07 07:27:32 PM PDT 24
Peak memory 200292 kb
Host smart-73ee9694-9bc2-4723-b372-37b34ca9f179
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3587951499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.3587951499
Directory /workspace/12.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/12.uart_loopback.4059271646
Short name T874
Test name
Test status
Simulation time 487155126 ps
CPU time 0.93 seconds
Started Jun 07 07:20:55 PM PDT 24
Finished Jun 07 07:21:05 PM PDT 24
Peak memory 195720 kb
Host smart-ad07aa39-e3f7-46a9-a4d6-a84b9d7be66f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059271646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_loopback.4059271646
Directory /workspace/12.uart_loopback/latest

Test location /workspace/coverage/default/12.uart_perf.567534578
Short name T678
Test name
Test status
Simulation time 10029822896 ps
CPU time 479.39 seconds
Started Jun 07 07:20:54 PM PDT 24
Finished Jun 07 07:29:03 PM PDT 24
Peak memory 200380 kb
Host smart-1952e6fb-7cd9-443a-af3e-832339161e66
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=567534578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.567534578
Directory /workspace/12.uart_perf/latest

Test location /workspace/coverage/default/12.uart_rx_oversample.45637685
Short name T788
Test name
Test status
Simulation time 5280269065 ps
CPU time 47.03 seconds
Started Jun 07 07:20:55 PM PDT 24
Finished Jun 07 07:21:51 PM PDT 24
Peak memory 198460 kb
Host smart-45b6e168-ee2f-4429-b572-08d6ed727aa2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=45637685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.45637685
Directory /workspace/12.uart_rx_oversample/latest

Test location /workspace/coverage/default/12.uart_rx_parity_err.2339828451
Short name T1006
Test name
Test status
Simulation time 140453711164 ps
CPU time 292.97 seconds
Started Jun 07 07:21:04 PM PDT 24
Finished Jun 07 07:26:02 PM PDT 24
Peak memory 200296 kb
Host smart-f04d0b83-e7b5-45d0-b1b9-d23154eb0bb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339828451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.2339828451
Directory /workspace/12.uart_rx_parity_err/latest

Test location /workspace/coverage/default/12.uart_rx_start_bit_filter.1342099332
Short name T460
Test name
Test status
Simulation time 509838312 ps
CPU time 0.85 seconds
Started Jun 07 07:20:55 PM PDT 24
Finished Jun 07 07:21:05 PM PDT 24
Peak memory 195700 kb
Host smart-1f8093e4-d3e5-4ce8-9aba-4978a710a335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342099332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.1342099332
Directory /workspace/12.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/12.uart_smoke.524909084
Short name T1005
Test name
Test status
Simulation time 5893602049 ps
CPU time 10.38 seconds
Started Jun 07 07:20:45 PM PDT 24
Finished Jun 07 07:21:10 PM PDT 24
Peak memory 200300 kb
Host smart-c8407387-d109-4961-b86c-4d081a49c8c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524909084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_smoke.524909084
Directory /workspace/12.uart_smoke/latest

Test location /workspace/coverage/default/12.uart_stress_all.2785508307
Short name T223
Test name
Test status
Simulation time 26379059017 ps
CPU time 48.58 seconds
Started Jun 07 07:20:57 PM PDT 24
Finished Jun 07 07:21:54 PM PDT 24
Peak memory 200328 kb
Host smart-5ce53cf9-6d13-4e60-b19e-8cbc68c5ec98
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785508307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.2785508307
Directory /workspace/12.uart_stress_all/latest

Test location /workspace/coverage/default/12.uart_stress_all_with_rand_reset.369033740
Short name T58
Test name
Test status
Simulation time 118521683842 ps
CPU time 647.67 seconds
Started Jun 07 07:20:55 PM PDT 24
Finished Jun 07 07:31:52 PM PDT 24
Peak memory 214316 kb
Host smart-56bbc85c-17c8-486c-87f4-d255a88997d8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369033740 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 12.uart_stress_all_with_rand_reset.369033740
Directory /workspace/12.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.uart_tx_ovrd.2365970106
Short name T718
Test name
Test status
Simulation time 5944636734 ps
CPU time 15.15 seconds
Started Jun 07 07:20:56 PM PDT 24
Finished Jun 07 07:21:20 PM PDT 24
Peak memory 199704 kb
Host smart-fe4b435a-adb8-41db-9843-b9b668c497a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365970106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.2365970106
Directory /workspace/12.uart_tx_ovrd/latest

Test location /workspace/coverage/default/12.uart_tx_rx.2169036242
Short name T305
Test name
Test status
Simulation time 81712905332 ps
CPU time 144.38 seconds
Started Jun 07 07:20:48 PM PDT 24
Finished Jun 07 07:23:25 PM PDT 24
Peak memory 200348 kb
Host smart-c6bad219-09ba-40db-8099-002d2fb9f0e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169036242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.2169036242
Directory /workspace/12.uart_tx_rx/latest

Test location /workspace/coverage/default/121.uart_fifo_reset.3477186428
Short name T1068
Test name
Test status
Simulation time 8951052607 ps
CPU time 49.72 seconds
Started Jun 07 07:26:22 PM PDT 24
Finished Jun 07 07:27:18 PM PDT 24
Peak memory 200380 kb
Host smart-26fde372-97e5-46b6-b76b-11c3d41d3564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477186428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.3477186428
Directory /workspace/121.uart_fifo_reset/latest

Test location /workspace/coverage/default/123.uart_fifo_reset.1423220858
Short name T6
Test name
Test status
Simulation time 26168373604 ps
CPU time 52.19 seconds
Started Jun 07 07:26:26 PM PDT 24
Finished Jun 07 07:27:23 PM PDT 24
Peak memory 200360 kb
Host smart-499384cc-00e4-4b6b-a124-2e34c42c3ec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423220858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.1423220858
Directory /workspace/123.uart_fifo_reset/latest

Test location /workspace/coverage/default/124.uart_fifo_reset.3517671876
Short name T350
Test name
Test status
Simulation time 12465301287 ps
CPU time 22.16 seconds
Started Jun 07 07:26:24 PM PDT 24
Finished Jun 07 07:26:52 PM PDT 24
Peak memory 200320 kb
Host smart-5fe8d8ec-99b0-4437-8074-5c80c13a29a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517671876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.3517671876
Directory /workspace/124.uart_fifo_reset/latest

Test location /workspace/coverage/default/125.uart_fifo_reset.3894478887
Short name T1046
Test name
Test status
Simulation time 117333928269 ps
CPU time 196.01 seconds
Started Jun 07 07:26:24 PM PDT 24
Finished Jun 07 07:29:46 PM PDT 24
Peak memory 200424 kb
Host smart-affb2d5b-d8c4-4ffd-a9ae-2d02b896130c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894478887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.3894478887
Directory /workspace/125.uart_fifo_reset/latest

Test location /workspace/coverage/default/126.uart_fifo_reset.1035035766
Short name T534
Test name
Test status
Simulation time 15544458489 ps
CPU time 53.84 seconds
Started Jun 07 07:26:25 PM PDT 24
Finished Jun 07 07:27:24 PM PDT 24
Peak memory 200308 kb
Host smart-607be188-a89e-4ab0-84d7-5b9328c0bfcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035035766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.1035035766
Directory /workspace/126.uart_fifo_reset/latest

Test location /workspace/coverage/default/127.uart_fifo_reset.1757086728
Short name T909
Test name
Test status
Simulation time 90585038559 ps
CPU time 19.53 seconds
Started Jun 07 07:26:21 PM PDT 24
Finished Jun 07 07:26:46 PM PDT 24
Peak memory 200364 kb
Host smart-cb327e4c-7cec-410a-80f4-fe62d7d4261f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757086728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.1757086728
Directory /workspace/127.uart_fifo_reset/latest

Test location /workspace/coverage/default/128.uart_fifo_reset.3396975536
Short name T876
Test name
Test status
Simulation time 162814336894 ps
CPU time 128.29 seconds
Started Jun 07 07:26:33 PM PDT 24
Finished Jun 07 07:28:44 PM PDT 24
Peak memory 199896 kb
Host smart-4197d563-3b11-4e55-acc9-86b37cff1258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396975536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.3396975536
Directory /workspace/128.uart_fifo_reset/latest

Test location /workspace/coverage/default/129.uart_fifo_reset.2838027240
Short name T683
Test name
Test status
Simulation time 160111881975 ps
CPU time 124.16 seconds
Started Jun 07 07:26:32 PM PDT 24
Finished Jun 07 07:28:39 PM PDT 24
Peak memory 200276 kb
Host smart-e65b8b6c-2560-40fa-9788-11d334786fdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838027240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.2838027240
Directory /workspace/129.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_alert_test.4225305303
Short name T7
Test name
Test status
Simulation time 14524615 ps
CPU time 0.57 seconds
Started Jun 07 07:21:02 PM PDT 24
Finished Jun 07 07:21:08 PM PDT 24
Peak memory 196080 kb
Host smart-a34900c0-1b62-46cd-9112-6fa58e55207d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225305303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.4225305303
Directory /workspace/13.uart_alert_test/latest

Test location /workspace/coverage/default/13.uart_fifo_full.2861538634
Short name T1001
Test name
Test status
Simulation time 119902613475 ps
CPU time 104.03 seconds
Started Jun 07 07:21:04 PM PDT 24
Finished Jun 07 07:22:53 PM PDT 24
Peak memory 200292 kb
Host smart-5d18d06c-1571-49df-83d9-9c18d2a943ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861538634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.2861538634
Directory /workspace/13.uart_fifo_full/latest

Test location /workspace/coverage/default/13.uart_fifo_overflow.1685758183
Short name T757
Test name
Test status
Simulation time 33589716023 ps
CPU time 37.15 seconds
Started Jun 07 07:20:58 PM PDT 24
Finished Jun 07 07:21:43 PM PDT 24
Peak memory 200348 kb
Host smart-7fce484d-2cae-4b43-99a1-84ec350f3eb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685758183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.1685758183
Directory /workspace/13.uart_fifo_overflow/latest

Test location /workspace/coverage/default/13.uart_fifo_reset.3825213807
Short name T589
Test name
Test status
Simulation time 118864604836 ps
CPU time 120.21 seconds
Started Jun 07 07:20:54 PM PDT 24
Finished Jun 07 07:23:04 PM PDT 24
Peak memory 200376 kb
Host smart-5143b30e-747b-4e18-a41e-cf0424c630f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825213807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.3825213807
Directory /workspace/13.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_intr.593814326
Short name T436
Test name
Test status
Simulation time 41094696054 ps
CPU time 83.54 seconds
Started Jun 07 07:21:04 PM PDT 24
Finished Jun 07 07:22:32 PM PDT 24
Peak memory 200380 kb
Host smart-27f3ff20-6d43-453d-93a5-4b0f3e85af70
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593814326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.593814326
Directory /workspace/13.uart_intr/latest

Test location /workspace/coverage/default/13.uart_long_xfer_wo_dly.254485609
Short name T54
Test name
Test status
Simulation time 83894543600 ps
CPU time 748.6 seconds
Started Jun 07 07:21:04 PM PDT 24
Finished Jun 07 07:33:37 PM PDT 24
Peak memory 200344 kb
Host smart-affeef52-37f7-4fa5-b3f3-2161c53ea46a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=254485609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.254485609
Directory /workspace/13.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/13.uart_loopback.319798107
Short name T782
Test name
Test status
Simulation time 1554332099 ps
CPU time 0.81 seconds
Started Jun 07 07:21:08 PM PDT 24
Finished Jun 07 07:21:11 PM PDT 24
Peak memory 195852 kb
Host smart-0511b552-ea23-4d7e-ab10-0d30a01c18f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319798107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_loopback.319798107
Directory /workspace/13.uart_loopback/latest

Test location /workspace/coverage/default/13.uart_perf.2058454502
Short name T101
Test name
Test status
Simulation time 10603008135 ps
CPU time 159.38 seconds
Started Jun 07 07:21:03 PM PDT 24
Finished Jun 07 07:23:47 PM PDT 24
Peak memory 200452 kb
Host smart-05732f22-8839-4cdc-b382-2fd66176df83
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2058454502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.2058454502
Directory /workspace/13.uart_perf/latest

Test location /workspace/coverage/default/13.uart_rx_oversample.1521458117
Short name T599
Test name
Test status
Simulation time 2549339110 ps
CPU time 8.65 seconds
Started Jun 07 07:21:04 PM PDT 24
Finished Jun 07 07:21:17 PM PDT 24
Peak memory 198520 kb
Host smart-0029bb95-6faf-4272-9833-ecadbaa3c83d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1521458117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.1521458117
Directory /workspace/13.uart_rx_oversample/latest

Test location /workspace/coverage/default/13.uart_rx_parity_err.2293119577
Short name T1014
Test name
Test status
Simulation time 46901391204 ps
CPU time 25.59 seconds
Started Jun 07 07:21:02 PM PDT 24
Finished Jun 07 07:21:33 PM PDT 24
Peak memory 200160 kb
Host smart-7b323e9e-1b76-46e8-9279-578635129697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293119577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.2293119577
Directory /workspace/13.uart_rx_parity_err/latest

Test location /workspace/coverage/default/13.uart_rx_start_bit_filter.1549650740
Short name T501
Test name
Test status
Simulation time 2220617951 ps
CPU time 3.72 seconds
Started Jun 07 07:21:10 PM PDT 24
Finished Jun 07 07:21:16 PM PDT 24
Peak memory 195932 kb
Host smart-522e5d81-492b-4478-88af-1d085fe420ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549650740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.1549650740
Directory /workspace/13.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/13.uart_smoke.1318234439
Short name T721
Test name
Test status
Simulation time 125786904 ps
CPU time 0.98 seconds
Started Jun 07 07:21:04 PM PDT 24
Finished Jun 07 07:21:10 PM PDT 24
Peak memory 199288 kb
Host smart-cdcd6d3e-c7d0-40e2-9a6d-7ea98152eea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318234439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_smoke.1318234439
Directory /workspace/13.uart_smoke/latest

Test location /workspace/coverage/default/13.uart_tx_ovrd.3021503728
Short name T378
Test name
Test status
Simulation time 2142822354 ps
CPU time 2.32 seconds
Started Jun 07 07:21:04 PM PDT 24
Finished Jun 07 07:21:11 PM PDT 24
Peak memory 199124 kb
Host smart-41499880-9818-45f5-8d5f-d859a3e0c4db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021503728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.3021503728
Directory /workspace/13.uart_tx_ovrd/latest

Test location /workspace/coverage/default/13.uart_tx_rx.3504728060
Short name T637
Test name
Test status
Simulation time 7560118265 ps
CPU time 12.45 seconds
Started Jun 07 07:20:55 PM PDT 24
Finished Jun 07 07:21:17 PM PDT 24
Peak memory 197356 kb
Host smart-837c5506-55a6-44a8-8f6a-f0f1e7463c03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504728060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.3504728060
Directory /workspace/13.uart_tx_rx/latest

Test location /workspace/coverage/default/130.uart_fifo_reset.4718535
Short name T680
Test name
Test status
Simulation time 38421903215 ps
CPU time 15.96 seconds
Started Jun 07 07:26:29 PM PDT 24
Finished Jun 07 07:26:49 PM PDT 24
Peak memory 200368 kb
Host smart-7268b961-23f1-46c2-8ea2-fb9e82c55ade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4718535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.4718535
Directory /workspace/130.uart_fifo_reset/latest

Test location /workspace/coverage/default/131.uart_fifo_reset.3338434097
Short name T194
Test name
Test status
Simulation time 32582221840 ps
CPU time 16.83 seconds
Started Jun 07 07:26:33 PM PDT 24
Finished Jun 07 07:26:53 PM PDT 24
Peak memory 200236 kb
Host smart-933f2c81-e3a3-45b2-b6a0-ccd9c1b4e315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338434097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.3338434097
Directory /workspace/131.uart_fifo_reset/latest

Test location /workspace/coverage/default/132.uart_fifo_reset.4149267085
Short name T142
Test name
Test status
Simulation time 47958727754 ps
CPU time 52.06 seconds
Started Jun 07 07:26:33 PM PDT 24
Finished Jun 07 07:27:27 PM PDT 24
Peak memory 200396 kb
Host smart-ffdddaf4-f5b5-40ef-907a-d6b8db43c45d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149267085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.4149267085
Directory /workspace/132.uart_fifo_reset/latest

Test location /workspace/coverage/default/133.uart_fifo_reset.3359155603
Short name T888
Test name
Test status
Simulation time 13458899670 ps
CPU time 6.29 seconds
Started Jun 07 07:26:31 PM PDT 24
Finished Jun 07 07:26:41 PM PDT 24
Peak memory 200364 kb
Host smart-5bd4d1fb-9ecd-491e-8b4e-37294d5c5c6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359155603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.3359155603
Directory /workspace/133.uart_fifo_reset/latest

Test location /workspace/coverage/default/134.uart_fifo_reset.3703716636
Short name T304
Test name
Test status
Simulation time 113085695870 ps
CPU time 212.58 seconds
Started Jun 07 07:26:33 PM PDT 24
Finished Jun 07 07:30:09 PM PDT 24
Peak memory 200360 kb
Host smart-de305f0a-19b4-445d-ad5b-4304a3091909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703716636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.3703716636
Directory /workspace/134.uart_fifo_reset/latest

Test location /workspace/coverage/default/135.uart_fifo_reset.898924854
Short name T261
Test name
Test status
Simulation time 45795334050 ps
CPU time 42.01 seconds
Started Jun 07 07:26:30 PM PDT 24
Finished Jun 07 07:27:16 PM PDT 24
Peak memory 200364 kb
Host smart-f7d74eaf-0575-4eb3-a81a-cf0d4a2cd5e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898924854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.898924854
Directory /workspace/135.uart_fifo_reset/latest

Test location /workspace/coverage/default/137.uart_fifo_reset.2070192366
Short name T243
Test name
Test status
Simulation time 35552384684 ps
CPU time 16.52 seconds
Started Jun 07 07:26:30 PM PDT 24
Finished Jun 07 07:26:51 PM PDT 24
Peak memory 200408 kb
Host smart-9ae0f9e1-6986-440d-8983-5556981b2326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070192366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.2070192366
Directory /workspace/137.uart_fifo_reset/latest

Test location /workspace/coverage/default/138.uart_fifo_reset.2870096967
Short name T971
Test name
Test status
Simulation time 58037327708 ps
CPU time 31.18 seconds
Started Jun 07 07:26:32 PM PDT 24
Finished Jun 07 07:27:06 PM PDT 24
Peak memory 200404 kb
Host smart-908a7997-b665-44c1-befe-768167045c1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870096967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.2870096967
Directory /workspace/138.uart_fifo_reset/latest

Test location /workspace/coverage/default/139.uart_fifo_reset.1151687322
Short name T929
Test name
Test status
Simulation time 259075469606 ps
CPU time 33.72 seconds
Started Jun 07 07:26:31 PM PDT 24
Finished Jun 07 07:27:08 PM PDT 24
Peak memory 200396 kb
Host smart-0d8cdd5e-6641-46ee-8d4c-d7eba08f20b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151687322 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.1151687322
Directory /workspace/139.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_alert_test.2795886417
Short name T968
Test name
Test status
Simulation time 12827995 ps
CPU time 0.57 seconds
Started Jun 07 07:21:20 PM PDT 24
Finished Jun 07 07:21:26 PM PDT 24
Peak memory 196032 kb
Host smart-992b93e5-77cf-47d6-9a8a-e9c0d1b61625
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795886417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.2795886417
Directory /workspace/14.uart_alert_test/latest

Test location /workspace/coverage/default/14.uart_fifo_full.3078700176
Short name T176
Test name
Test status
Simulation time 107791367413 ps
CPU time 58.96 seconds
Started Jun 07 07:21:12 PM PDT 24
Finished Jun 07 07:22:13 PM PDT 24
Peak memory 200408 kb
Host smart-787ca56d-747f-48be-a4d8-3ae5b55552c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078700176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.3078700176
Directory /workspace/14.uart_fifo_full/latest

Test location /workspace/coverage/default/14.uart_fifo_overflow.3756912119
Short name T406
Test name
Test status
Simulation time 23074294318 ps
CPU time 20.22 seconds
Started Jun 07 07:21:10 PM PDT 24
Finished Jun 07 07:21:34 PM PDT 24
Peak memory 200084 kb
Host smart-0e246223-aec9-418d-aa5a-dab5418aec56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756912119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.3756912119
Directory /workspace/14.uart_fifo_overflow/latest

Test location /workspace/coverage/default/14.uart_fifo_reset.320390199
Short name T948
Test name
Test status
Simulation time 66511245744 ps
CPU time 117.06 seconds
Started Jun 07 07:21:11 PM PDT 24
Finished Jun 07 07:23:11 PM PDT 24
Peak memory 200356 kb
Host smart-2af70b26-3b9b-437f-b495-f05049c7415f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320390199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.320390199
Directory /workspace/14.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_intr.2052049072
Short name T887
Test name
Test status
Simulation time 47168838427 ps
CPU time 23.75 seconds
Started Jun 07 07:21:11 PM PDT 24
Finished Jun 07 07:21:38 PM PDT 24
Peak memory 200360 kb
Host smart-ab2e18d6-b4b4-4d06-aa8b-c931f0312a52
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052049072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.2052049072
Directory /workspace/14.uart_intr/latest

Test location /workspace/coverage/default/14.uart_long_xfer_wo_dly.3272915274
Short name T114
Test name
Test status
Simulation time 158160434620 ps
CPU time 1085.5 seconds
Started Jun 07 07:21:19 PM PDT 24
Finished Jun 07 07:39:30 PM PDT 24
Peak memory 200392 kb
Host smart-5c555951-8827-4889-ab8d-c3b5fcbd5252
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3272915274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.3272915274
Directory /workspace/14.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/14.uart_loopback.3078044190
Short name T399
Test name
Test status
Simulation time 5529109449 ps
CPU time 3.16 seconds
Started Jun 07 07:21:11 PM PDT 24
Finished Jun 07 07:21:17 PM PDT 24
Peak memory 198816 kb
Host smart-e142cb56-336a-4d7b-bb74-96074ac2498f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078044190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_loopback.3078044190
Directory /workspace/14.uart_loopback/latest

Test location /workspace/coverage/default/14.uart_noise_filter.1547370317
Short name T752
Test name
Test status
Simulation time 29223939635 ps
CPU time 46.6 seconds
Started Jun 07 07:21:14 PM PDT 24
Finished Jun 07 07:22:04 PM PDT 24
Peak memory 200436 kb
Host smart-edb1caa2-858b-45f1-aeaa-878ec8b9a1a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547370317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_noise_filter.1547370317
Directory /workspace/14.uart_noise_filter/latest

Test location /workspace/coverage/default/14.uart_perf.4257866710
Short name T815
Test name
Test status
Simulation time 20924761881 ps
CPU time 1139.98 seconds
Started Jun 07 07:21:19 PM PDT 24
Finished Jun 07 07:40:25 PM PDT 24
Peak memory 200304 kb
Host smart-dcb1546d-7446-40f9-8cde-3720ded5a303
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4257866710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.4257866710
Directory /workspace/14.uart_perf/latest

Test location /workspace/coverage/default/14.uart_rx_oversample.2077961860
Short name T50
Test name
Test status
Simulation time 5687337655 ps
CPU time 48.73 seconds
Started Jun 07 07:21:11 PM PDT 24
Finished Jun 07 07:22:03 PM PDT 24
Peak memory 199776 kb
Host smart-3f2ad36d-101c-4407-aff1-0083863e3aaa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2077961860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.2077961860
Directory /workspace/14.uart_rx_oversample/latest

Test location /workspace/coverage/default/14.uart_rx_parity_err.743395745
Short name T776
Test name
Test status
Simulation time 33634156383 ps
CPU time 27.78 seconds
Started Jun 07 07:21:13 PM PDT 24
Finished Jun 07 07:21:44 PM PDT 24
Peak memory 200444 kb
Host smart-ccf27a68-880d-4555-9b09-657c3f30f042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743395745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.743395745
Directory /workspace/14.uart_rx_parity_err/latest

Test location /workspace/coverage/default/14.uart_rx_start_bit_filter.1587081542
Short name T593
Test name
Test status
Simulation time 3237063225 ps
CPU time 1.93 seconds
Started Jun 07 07:21:14 PM PDT 24
Finished Jun 07 07:21:19 PM PDT 24
Peak memory 196348 kb
Host smart-3cd628d2-a2ba-4234-bbbd-f216fd11e804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587081542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.1587081542
Directory /workspace/14.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/14.uart_smoke.3537185627
Short name T319
Test name
Test status
Simulation time 6159515651 ps
CPU time 4.96 seconds
Started Jun 07 07:21:04 PM PDT 24
Finished Jun 07 07:21:14 PM PDT 24
Peak memory 200336 kb
Host smart-29e3655e-10bd-4468-abfb-36967f94a9cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537185627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_smoke.3537185627
Directory /workspace/14.uart_smoke/latest

Test location /workspace/coverage/default/14.uart_stress_all.81017968
Short name T271
Test name
Test status
Simulation time 167622097366 ps
CPU time 310.56 seconds
Started Jun 07 07:21:19 PM PDT 24
Finished Jun 07 07:26:34 PM PDT 24
Peak memory 200372 kb
Host smart-687b1953-b1a0-46b3-9d2b-2b30f069f48e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81017968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.81017968
Directory /workspace/14.uart_stress_all/latest

Test location /workspace/coverage/default/14.uart_tx_ovrd.3092848986
Short name T283
Test name
Test status
Simulation time 13301123144 ps
CPU time 5 seconds
Started Jun 07 07:21:11 PM PDT 24
Finished Jun 07 07:21:19 PM PDT 24
Peak memory 200500 kb
Host smart-b74658f0-005a-435a-a1de-f9a59d679e18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092848986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.3092848986
Directory /workspace/14.uart_tx_ovrd/latest

Test location /workspace/coverage/default/14.uart_tx_rx.729961436
Short name T564
Test name
Test status
Simulation time 6375242260 ps
CPU time 3.51 seconds
Started Jun 07 07:21:05 PM PDT 24
Finished Jun 07 07:21:12 PM PDT 24
Peak memory 199796 kb
Host smart-25e44ae3-cff8-4475-9ea3-73d2ddf5baf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729961436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.729961436
Directory /workspace/14.uart_tx_rx/latest

Test location /workspace/coverage/default/141.uart_fifo_reset.1924067301
Short name T933
Test name
Test status
Simulation time 229644394283 ps
CPU time 66.96 seconds
Started Jun 07 07:26:31 PM PDT 24
Finished Jun 07 07:27:41 PM PDT 24
Peak memory 200424 kb
Host smart-201fb0aa-cc23-4a3a-90c0-28fc489d2a61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924067301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.1924067301
Directory /workspace/141.uart_fifo_reset/latest

Test location /workspace/coverage/default/142.uart_fifo_reset.445582492
Short name T700
Test name
Test status
Simulation time 4185758765 ps
CPU time 9.53 seconds
Started Jun 07 07:26:38 PM PDT 24
Finished Jun 07 07:26:49 PM PDT 24
Peak memory 200372 kb
Host smart-3516ccec-d2dc-4a62-a908-cff99c559322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445582492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.445582492
Directory /workspace/142.uart_fifo_reset/latest

Test location /workspace/coverage/default/143.uart_fifo_reset.3258202711
Short name T827
Test name
Test status
Simulation time 6647276522 ps
CPU time 11.07 seconds
Started Jun 07 07:26:37 PM PDT 24
Finished Jun 07 07:26:50 PM PDT 24
Peak memory 200312 kb
Host smart-dc6ee658-2c9b-4511-b7bc-720d08610f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258202711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.3258202711
Directory /workspace/143.uart_fifo_reset/latest

Test location /workspace/coverage/default/144.uart_fifo_reset.1107558811
Short name T858
Test name
Test status
Simulation time 166611567472 ps
CPU time 450.1 seconds
Started Jun 07 07:26:38 PM PDT 24
Finished Jun 07 07:34:10 PM PDT 24
Peak memory 200292 kb
Host smart-5ae96c37-10f7-4202-b4b7-100ea733ccb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107558811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.1107558811
Directory /workspace/144.uart_fifo_reset/latest

Test location /workspace/coverage/default/145.uart_fifo_reset.2915249422
Short name T904
Test name
Test status
Simulation time 60365323011 ps
CPU time 126.78 seconds
Started Jun 07 07:26:39 PM PDT 24
Finished Jun 07 07:28:48 PM PDT 24
Peak memory 200392 kb
Host smart-8532dc45-65c4-46a6-9f9c-71fdefc1eb81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915249422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.2915249422
Directory /workspace/145.uart_fifo_reset/latest

Test location /workspace/coverage/default/146.uart_fifo_reset.2787058715
Short name T196
Test name
Test status
Simulation time 32455333690 ps
CPU time 28.9 seconds
Started Jun 07 07:26:38 PM PDT 24
Finished Jun 07 07:27:08 PM PDT 24
Peak memory 200268 kb
Host smart-a0cf0a5b-419d-40e1-ab52-359582e9e0da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787058715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.2787058715
Directory /workspace/146.uart_fifo_reset/latest

Test location /workspace/coverage/default/148.uart_fifo_reset.3414236140
Short name T666
Test name
Test status
Simulation time 107384622784 ps
CPU time 152.14 seconds
Started Jun 07 07:26:39 PM PDT 24
Finished Jun 07 07:29:12 PM PDT 24
Peak memory 200352 kb
Host smart-48f9b8b5-6bfa-42e2-9c7b-3fba93c6044d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414236140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.3414236140
Directory /workspace/148.uart_fifo_reset/latest

Test location /workspace/coverage/default/149.uart_fifo_reset.1766469453
Short name T731
Test name
Test status
Simulation time 107954936189 ps
CPU time 162.41 seconds
Started Jun 07 07:26:39 PM PDT 24
Finished Jun 07 07:29:23 PM PDT 24
Peak memory 200320 kb
Host smart-169c8cb3-4b89-4b8d-97d0-cc64787379f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766469453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.1766469453
Directory /workspace/149.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_alert_test.227479162
Short name T444
Test name
Test status
Simulation time 36219983 ps
CPU time 0.57 seconds
Started Jun 07 07:21:31 PM PDT 24
Finished Jun 07 07:21:41 PM PDT 24
Peak memory 195768 kb
Host smart-c6956196-b34a-44fc-a6d8-4319c14ed753
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227479162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.227479162
Directory /workspace/15.uart_alert_test/latest

Test location /workspace/coverage/default/15.uart_fifo_overflow.2850501764
Short name T595
Test name
Test status
Simulation time 29819995368 ps
CPU time 13.19 seconds
Started Jun 07 07:21:20 PM PDT 24
Finished Jun 07 07:21:39 PM PDT 24
Peak memory 199868 kb
Host smart-fc13d6f2-96ca-4dc7-b2e0-de579ca95c6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850501764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.2850501764
Directory /workspace/15.uart_fifo_overflow/latest

Test location /workspace/coverage/default/15.uart_fifo_reset.62439518
Short name T1034
Test name
Test status
Simulation time 191159646651 ps
CPU time 84.99 seconds
Started Jun 07 07:21:26 PM PDT 24
Finished Jun 07 07:22:59 PM PDT 24
Peak memory 200140 kb
Host smart-c0d8522f-c6ce-4cb3-88ba-044431889d36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62439518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.62439518
Directory /workspace/15.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_intr.1561171278
Short name T897
Test name
Test status
Simulation time 110595856460 ps
CPU time 40.64 seconds
Started Jun 07 07:21:19 PM PDT 24
Finished Jun 07 07:22:05 PM PDT 24
Peak memory 200164 kb
Host smart-a6ab77ae-c280-4e6f-9aa9-f4d1c2c9175e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561171278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.1561171278
Directory /workspace/15.uart_intr/latest

Test location /workspace/coverage/default/15.uart_long_xfer_wo_dly.4165944794
Short name T745
Test name
Test status
Simulation time 110550487669 ps
CPU time 377.52 seconds
Started Jun 07 07:21:28 PM PDT 24
Finished Jun 07 07:27:55 PM PDT 24
Peak memory 200392 kb
Host smart-dc5f7fb0-97e7-4c3c-b498-f16bb10797bb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4165944794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.4165944794
Directory /workspace/15.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/15.uart_loopback.1423664414
Short name T473
Test name
Test status
Simulation time 8721923714 ps
CPU time 8.62 seconds
Started Jun 07 07:21:19 PM PDT 24
Finished Jun 07 07:21:32 PM PDT 24
Peak memory 199796 kb
Host smart-c06c6f7b-32e4-46f8-9907-b975557021e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423664414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_loopback.1423664414
Directory /workspace/15.uart_loopback/latest

Test location /workspace/coverage/default/15.uart_noise_filter.3082343210
Short name T113
Test name
Test status
Simulation time 18877912118 ps
CPU time 10.88 seconds
Started Jun 07 07:21:21 PM PDT 24
Finished Jun 07 07:21:38 PM PDT 24
Peak memory 199068 kb
Host smart-92d3821f-65ac-4543-8103-1c3ca4caaac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082343210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_noise_filter.3082343210
Directory /workspace/15.uart_noise_filter/latest

Test location /workspace/coverage/default/15.uart_perf.1942105685
Short name T900
Test name
Test status
Simulation time 40624541635 ps
CPU time 306.97 seconds
Started Jun 07 07:21:19 PM PDT 24
Finished Jun 07 07:26:31 PM PDT 24
Peak memory 200392 kb
Host smart-4af7ac4b-e374-4cd1-ab87-1669e0189cd7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1942105685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.1942105685
Directory /workspace/15.uart_perf/latest

Test location /workspace/coverage/default/15.uart_rx_oversample.2495462434
Short name T756
Test name
Test status
Simulation time 4479855680 ps
CPU time 9.38 seconds
Started Jun 07 07:21:19 PM PDT 24
Finished Jun 07 07:21:34 PM PDT 24
Peak memory 199376 kb
Host smart-35d150a6-0651-44d4-9681-80ad93a3bec8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2495462434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.2495462434
Directory /workspace/15.uart_rx_oversample/latest

Test location /workspace/coverage/default/15.uart_rx_parity_err.3380798079
Short name T538
Test name
Test status
Simulation time 109621676409 ps
CPU time 198.77 seconds
Started Jun 07 07:21:19 PM PDT 24
Finished Jun 07 07:24:44 PM PDT 24
Peak memory 200356 kb
Host smart-15817d1a-f7f1-431f-b36e-bd4e6cb6caa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380798079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.3380798079
Directory /workspace/15.uart_rx_parity_err/latest

Test location /workspace/coverage/default/15.uart_rx_start_bit_filter.2103448690
Short name T334
Test name
Test status
Simulation time 4094679170 ps
CPU time 3.93 seconds
Started Jun 07 07:21:19 PM PDT 24
Finished Jun 07 07:21:28 PM PDT 24
Peak memory 196384 kb
Host smart-ccd337c4-a530-4c7b-9bf3-54160d219a14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103448690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.2103448690
Directory /workspace/15.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/15.uart_smoke.805797956
Short name T419
Test name
Test status
Simulation time 473063410 ps
CPU time 1.94 seconds
Started Jun 07 07:21:23 PM PDT 24
Finished Jun 07 07:21:31 PM PDT 24
Peak memory 199780 kb
Host smart-9150dea4-fdf9-478c-aa77-16e431f1c21d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805797956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_smoke.805797956
Directory /workspace/15.uart_smoke/latest

Test location /workspace/coverage/default/15.uart_stress_all.1364776887
Short name T740
Test name
Test status
Simulation time 374964321125 ps
CPU time 622.85 seconds
Started Jun 07 07:21:27 PM PDT 24
Finished Jun 07 07:31:59 PM PDT 24
Peak memory 200436 kb
Host smart-b9715046-87c2-4759-be5a-ac9f230b1120
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364776887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.1364776887
Directory /workspace/15.uart_stress_all/latest

Test location /workspace/coverage/default/15.uart_tx_ovrd.1777251338
Short name T677
Test name
Test status
Simulation time 1552288468 ps
CPU time 1.78 seconds
Started Jun 07 07:21:25 PM PDT 24
Finished Jun 07 07:21:35 PM PDT 24
Peak memory 199388 kb
Host smart-64e485f6-c166-4d0a-96dc-ea3e4bfc4eec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777251338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.1777251338
Directory /workspace/15.uart_tx_ovrd/latest

Test location /workspace/coverage/default/15.uart_tx_rx.616498668
Short name T134
Test name
Test status
Simulation time 79387626765 ps
CPU time 31.84 seconds
Started Jun 07 07:21:19 PM PDT 24
Finished Jun 07 07:21:57 PM PDT 24
Peak memory 200264 kb
Host smart-3360eec7-8c89-4b13-b804-a7c8a701e5ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616498668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.616498668
Directory /workspace/15.uart_tx_rx/latest

Test location /workspace/coverage/default/150.uart_fifo_reset.3285979452
Short name T13
Test name
Test status
Simulation time 162789515556 ps
CPU time 50.24 seconds
Started Jun 07 07:26:39 PM PDT 24
Finished Jun 07 07:27:31 PM PDT 24
Peak memory 200412 kb
Host smart-1673f77c-cac6-4c9a-986f-13bb85e374ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285979452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.3285979452
Directory /workspace/150.uart_fifo_reset/latest

Test location /workspace/coverage/default/151.uart_fifo_reset.2065197281
Short name T872
Test name
Test status
Simulation time 205245095633 ps
CPU time 175.09 seconds
Started Jun 07 07:26:38 PM PDT 24
Finished Jun 07 07:29:34 PM PDT 24
Peak memory 200308 kb
Host smart-56943cd3-cdc3-45c4-ac60-d22ec71d0960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065197281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.2065197281
Directory /workspace/151.uart_fifo_reset/latest

Test location /workspace/coverage/default/152.uart_fifo_reset.2431417727
Short name T1052
Test name
Test status
Simulation time 150021459667 ps
CPU time 47.95 seconds
Started Jun 07 07:26:38 PM PDT 24
Finished Jun 07 07:27:28 PM PDT 24
Peak memory 200372 kb
Host smart-4a382bac-93a2-425e-b086-5ac463ae7236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431417727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.2431417727
Directory /workspace/152.uart_fifo_reset/latest

Test location /workspace/coverage/default/153.uart_fifo_reset.2641683995
Short name T429
Test name
Test status
Simulation time 11205197802 ps
CPU time 17.88 seconds
Started Jun 07 07:26:39 PM PDT 24
Finished Jun 07 07:26:59 PM PDT 24
Peak memory 200396 kb
Host smart-c0105a19-1fcd-4e4f-91c9-7602fbfc0fc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641683995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.2641683995
Directory /workspace/153.uart_fifo_reset/latest

Test location /workspace/coverage/default/154.uart_fifo_reset.523631020
Short name T537
Test name
Test status
Simulation time 31445285580 ps
CPU time 17.8 seconds
Started Jun 07 07:26:49 PM PDT 24
Finished Jun 07 07:27:08 PM PDT 24
Peak memory 200304 kb
Host smart-096f31c5-3ddb-40f6-b28e-5569f6463054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523631020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.523631020
Directory /workspace/154.uart_fifo_reset/latest

Test location /workspace/coverage/default/155.uart_fifo_reset.100890811
Short name T551
Test name
Test status
Simulation time 159915309911 ps
CPU time 60.28 seconds
Started Jun 07 07:27:18 PM PDT 24
Finished Jun 07 07:28:20 PM PDT 24
Peak memory 200316 kb
Host smart-9b5f5e9d-591c-4397-817a-7266964322a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100890811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.100890811
Directory /workspace/155.uart_fifo_reset/latest

Test location /workspace/coverage/default/156.uart_fifo_reset.4169774943
Short name T698
Test name
Test status
Simulation time 64616803828 ps
CPU time 17.2 seconds
Started Jun 07 07:27:18 PM PDT 24
Finished Jun 07 07:27:37 PM PDT 24
Peak memory 200380 kb
Host smart-7c38014c-1514-46d8-8049-f2a45cbecaac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169774943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.4169774943
Directory /workspace/156.uart_fifo_reset/latest

Test location /workspace/coverage/default/157.uart_fifo_reset.1739095181
Short name T199
Test name
Test status
Simulation time 39857068287 ps
CPU time 90.66 seconds
Started Jun 07 07:27:18 PM PDT 24
Finished Jun 07 07:28:51 PM PDT 24
Peak memory 200400 kb
Host smart-ed2d7f70-2bce-4227-bdf1-67603750db72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739095181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.1739095181
Directory /workspace/157.uart_fifo_reset/latest

Test location /workspace/coverage/default/158.uart_fifo_reset.615743344
Short name T162
Test name
Test status
Simulation time 16244881166 ps
CPU time 17.11 seconds
Started Jun 07 07:27:21 PM PDT 24
Finished Jun 07 07:27:41 PM PDT 24
Peak memory 200380 kb
Host smart-c419f68f-642f-42c2-8e16-3a2533aa4833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615743344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.615743344
Directory /workspace/158.uart_fifo_reset/latest

Test location /workspace/coverage/default/159.uart_fifo_reset.4289873123
Short name T286
Test name
Test status
Simulation time 22353098250 ps
CPU time 43.69 seconds
Started Jun 07 07:27:19 PM PDT 24
Finished Jun 07 07:28:04 PM PDT 24
Peak memory 200336 kb
Host smart-7ed45a13-2bc4-4eb7-8978-5f155f07d16a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289873123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.4289873123
Directory /workspace/159.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_alert_test.3645059772
Short name T792
Test name
Test status
Simulation time 14192808 ps
CPU time 0.6 seconds
Started Jun 07 07:21:38 PM PDT 24
Finished Jun 07 07:21:49 PM PDT 24
Peak memory 195764 kb
Host smart-99acf4f3-a911-45d2-870a-be1037f00b2a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645059772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.3645059772
Directory /workspace/16.uart_alert_test/latest

Test location /workspace/coverage/default/16.uart_fifo_full.1218144495
Short name T922
Test name
Test status
Simulation time 79584066826 ps
CPU time 25.55 seconds
Started Jun 07 07:21:31 PM PDT 24
Finished Jun 07 07:22:07 PM PDT 24
Peak memory 200272 kb
Host smart-22726e82-ab18-4f98-be7b-395cde467007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218144495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.1218144495
Directory /workspace/16.uart_fifo_full/latest

Test location /workspace/coverage/default/16.uart_fifo_overflow.1932165601
Short name T98
Test name
Test status
Simulation time 34581907001 ps
CPU time 7.02 seconds
Started Jun 07 07:21:28 PM PDT 24
Finished Jun 07 07:21:45 PM PDT 24
Peak memory 200348 kb
Host smart-377f9820-3951-4418-8cd1-addeb955422f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932165601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.1932165601
Directory /workspace/16.uart_fifo_overflow/latest

Test location /workspace/coverage/default/16.uart_fifo_reset.449492112
Short name T605
Test name
Test status
Simulation time 76286123400 ps
CPU time 57.62 seconds
Started Jun 07 07:21:27 PM PDT 24
Finished Jun 07 07:22:34 PM PDT 24
Peak memory 200380 kb
Host smart-71c59b47-a667-4339-85f5-d10c62b30fa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449492112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.449492112
Directory /workspace/16.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_intr.1723375535
Short name T513
Test name
Test status
Simulation time 75077160372 ps
CPU time 33.08 seconds
Started Jun 07 07:21:28 PM PDT 24
Finished Jun 07 07:22:11 PM PDT 24
Peak memory 199764 kb
Host smart-bd4d9552-bad4-41ce-b976-9735edd0e5c5
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723375535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.1723375535
Directory /workspace/16.uart_intr/latest

Test location /workspace/coverage/default/16.uart_long_xfer_wo_dly.1477316627
Short name T387
Test name
Test status
Simulation time 138750914253 ps
CPU time 348.26 seconds
Started Jun 07 07:21:36 PM PDT 24
Finished Jun 07 07:27:34 PM PDT 24
Peak memory 200412 kb
Host smart-1896734a-d4f8-457a-8d8e-8acfb938f99c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1477316627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.1477316627
Directory /workspace/16.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/16.uart_loopback.226205950
Short name T586
Test name
Test status
Simulation time 8248408085 ps
CPU time 15.65 seconds
Started Jun 07 07:21:37 PM PDT 24
Finished Jun 07 07:22:03 PM PDT 24
Peak memory 199984 kb
Host smart-a4f9c108-9e8a-4e2a-b5bf-c19f6de36600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226205950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_loopback.226205950
Directory /workspace/16.uart_loopback/latest

Test location /workspace/coverage/default/16.uart_perf.4051846551
Short name T332
Test name
Test status
Simulation time 13739961566 ps
CPU time 761.7 seconds
Started Jun 07 07:21:37 PM PDT 24
Finished Jun 07 07:34:29 PM PDT 24
Peak memory 200268 kb
Host smart-f4615ed1-aa40-4a3f-8245-4a0221680248
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4051846551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.4051846551
Directory /workspace/16.uart_perf/latest

Test location /workspace/coverage/default/16.uart_rx_oversample.3557629487
Short name T544
Test name
Test status
Simulation time 4297519959 ps
CPU time 35.14 seconds
Started Jun 07 07:21:27 PM PDT 24
Finished Jun 07 07:22:11 PM PDT 24
Peak memory 199364 kb
Host smart-7fd4686b-54df-452c-bcbc-0eced2574295
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3557629487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.3557629487
Directory /workspace/16.uart_rx_oversample/latest

Test location /workspace/coverage/default/16.uart_rx_start_bit_filter.4250250933
Short name T576
Test name
Test status
Simulation time 5235048300 ps
CPU time 5.17 seconds
Started Jun 07 07:21:30 PM PDT 24
Finished Jun 07 07:21:45 PM PDT 24
Peak memory 196420 kb
Host smart-8a120e0c-ac18-48d1-a1b2-1973529ce871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250250933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.4250250933
Directory /workspace/16.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/16.uart_smoke.3337025968
Short name T391
Test name
Test status
Simulation time 10551994056 ps
CPU time 19.61 seconds
Started Jun 07 07:21:29 PM PDT 24
Finished Jun 07 07:21:59 PM PDT 24
Peak memory 200192 kb
Host smart-5bfc6e45-16cc-45c5-8900-9b27b63cec28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337025968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_smoke.3337025968
Directory /workspace/16.uart_smoke/latest

Test location /workspace/coverage/default/16.uart_stress_all.1234992259
Short name T109
Test name
Test status
Simulation time 175318072915 ps
CPU time 63.45 seconds
Started Jun 07 07:21:36 PM PDT 24
Finished Jun 07 07:22:50 PM PDT 24
Peak memory 200356 kb
Host smart-2fc9cc89-cb31-4017-a2a6-410d85a2a1db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234992259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.1234992259
Directory /workspace/16.uart_stress_all/latest

Test location /workspace/coverage/default/16.uart_stress_all_with_rand_reset.760082121
Short name T881
Test name
Test status
Simulation time 30144002499 ps
CPU time 300.7 seconds
Started Jun 07 07:21:41 PM PDT 24
Finished Jun 07 07:26:53 PM PDT 24
Peak memory 216060 kb
Host smart-9439cccf-bb6a-4adc-9954-789a8705dfd1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760082121 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 16.uart_stress_all_with_rand_reset.760082121
Directory /workspace/16.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.uart_tx_ovrd.3404371367
Short name T759
Test name
Test status
Simulation time 1058094889 ps
CPU time 2.42 seconds
Started Jun 07 07:21:37 PM PDT 24
Finished Jun 07 07:21:50 PM PDT 24
Peak memory 199164 kb
Host smart-adc6ade7-d1a8-409b-a586-de8da56dab4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404371367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.3404371367
Directory /workspace/16.uart_tx_ovrd/latest

Test location /workspace/coverage/default/16.uart_tx_rx.4071065697
Short name T1013
Test name
Test status
Simulation time 35757628545 ps
CPU time 146.53 seconds
Started Jun 07 07:21:29 PM PDT 24
Finished Jun 07 07:24:06 PM PDT 24
Peak memory 200376 kb
Host smart-02cc53ae-6faf-4ede-9303-ba130ba33274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071065697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.4071065697
Directory /workspace/16.uart_tx_rx/latest

Test location /workspace/coverage/default/160.uart_fifo_reset.4055600880
Short name T866
Test name
Test status
Simulation time 16554259604 ps
CPU time 25.5 seconds
Started Jun 07 07:27:19 PM PDT 24
Finished Jun 07 07:27:47 PM PDT 24
Peak memory 200404 kb
Host smart-0b2bef90-f309-465a-acb5-4165d93bc474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055600880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.4055600880
Directory /workspace/160.uart_fifo_reset/latest

Test location /workspace/coverage/default/161.uart_fifo_reset.2325053346
Short name T320
Test name
Test status
Simulation time 33132838557 ps
CPU time 10.1 seconds
Started Jun 07 07:27:19 PM PDT 24
Finished Jun 07 07:27:31 PM PDT 24
Peak memory 200408 kb
Host smart-f3035137-dfa1-4f09-82d2-0bbf8cbde3ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325053346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.2325053346
Directory /workspace/161.uart_fifo_reset/latest

Test location /workspace/coverage/default/162.uart_fifo_reset.2020734978
Short name T207
Test name
Test status
Simulation time 22080270933 ps
CPU time 34.97 seconds
Started Jun 07 07:27:16 PM PDT 24
Finished Jun 07 07:27:53 PM PDT 24
Peak memory 200388 kb
Host smart-7fcc3aef-b2ad-4b39-a136-3c1809580e15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020734978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.2020734978
Directory /workspace/162.uart_fifo_reset/latest

Test location /workspace/coverage/default/163.uart_fifo_reset.4060155443
Short name T264
Test name
Test status
Simulation time 125268198317 ps
CPU time 13.39 seconds
Started Jun 07 07:27:18 PM PDT 24
Finished Jun 07 07:27:34 PM PDT 24
Peak memory 200284 kb
Host smart-6eb04fde-5fb6-4dff-9b53-a0ffd69c1b37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060155443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.4060155443
Directory /workspace/163.uart_fifo_reset/latest

Test location /workspace/coverage/default/164.uart_fifo_reset.3216469028
Short name T1028
Test name
Test status
Simulation time 78871189402 ps
CPU time 33 seconds
Started Jun 07 07:27:09 PM PDT 24
Finished Jun 07 07:27:43 PM PDT 24
Peak memory 200320 kb
Host smart-f5b7ceb7-06f9-46ba-bc86-4cbf9fd6ce5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216469028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.3216469028
Directory /workspace/164.uart_fifo_reset/latest

Test location /workspace/coverage/default/165.uart_fifo_reset.1543359501
Short name T790
Test name
Test status
Simulation time 315706990098 ps
CPU time 121.18 seconds
Started Jun 07 07:27:19 PM PDT 24
Finished Jun 07 07:29:22 PM PDT 24
Peak memory 200368 kb
Host smart-df363537-25a3-4db1-a158-aa268d63929a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543359501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.1543359501
Directory /workspace/165.uart_fifo_reset/latest

Test location /workspace/coverage/default/167.uart_fifo_reset.3136578304
Short name T193
Test name
Test status
Simulation time 51189009734 ps
CPU time 88.99 seconds
Started Jun 07 07:27:20 PM PDT 24
Finished Jun 07 07:28:52 PM PDT 24
Peak memory 200372 kb
Host smart-d13a78e6-d602-4da3-a159-3394c8d2b90d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136578304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.3136578304
Directory /workspace/167.uart_fifo_reset/latest

Test location /workspace/coverage/default/168.uart_fifo_reset.3246232144
Short name T463
Test name
Test status
Simulation time 83664918832 ps
CPU time 132.27 seconds
Started Jun 07 07:27:19 PM PDT 24
Finished Jun 07 07:29:33 PM PDT 24
Peak memory 200324 kb
Host smart-c732f739-980d-44c2-b39d-8112d7fd1e95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246232144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.3246232144
Directory /workspace/168.uart_fifo_reset/latest

Test location /workspace/coverage/default/169.uart_fifo_reset.269378518
Short name T819
Test name
Test status
Simulation time 64631746778 ps
CPU time 107.73 seconds
Started Jun 07 07:27:22 PM PDT 24
Finished Jun 07 07:29:13 PM PDT 24
Peak memory 200372 kb
Host smart-fe324e1b-ea2b-4387-93f4-bb96290ab22e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269378518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.269378518
Directory /workspace/169.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_alert_test.3083226290
Short name T528
Test name
Test status
Simulation time 36176083 ps
CPU time 0.56 seconds
Started Jun 07 07:21:46 PM PDT 24
Finished Jun 07 07:21:59 PM PDT 24
Peak memory 195760 kb
Host smart-2af18301-a7de-4854-91e5-49a9c09bd4b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083226290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.3083226290
Directory /workspace/17.uart_alert_test/latest

Test location /workspace/coverage/default/17.uart_fifo_full.92539408
Short name T135
Test name
Test status
Simulation time 20377795167 ps
CPU time 42.05 seconds
Started Jun 07 07:21:41 PM PDT 24
Finished Jun 07 07:22:34 PM PDT 24
Peak memory 200344 kb
Host smart-190e5ee2-0fb4-4163-987f-2fc3b5b64ac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92539408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.92539408
Directory /workspace/17.uart_fifo_full/latest

Test location /workspace/coverage/default/17.uart_fifo_overflow.2336492934
Short name T439
Test name
Test status
Simulation time 105019952342 ps
CPU time 228.19 seconds
Started Jun 07 07:21:41 PM PDT 24
Finished Jun 07 07:25:40 PM PDT 24
Peak memory 200360 kb
Host smart-4de65c20-e818-4118-a631-4e0704f33612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336492934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.2336492934
Directory /workspace/17.uart_fifo_overflow/latest

Test location /workspace/coverage/default/17.uart_intr.3986589514
Short name T374
Test name
Test status
Simulation time 12522310643 ps
CPU time 19.39 seconds
Started Jun 07 07:21:41 PM PDT 24
Finished Jun 07 07:22:11 PM PDT 24
Peak memory 196792 kb
Host smart-517821f2-8cb8-40cb-b264-a9333f657f6c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986589514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.3986589514
Directory /workspace/17.uart_intr/latest

Test location /workspace/coverage/default/17.uart_long_xfer_wo_dly.3860258100
Short name T667
Test name
Test status
Simulation time 273153157978 ps
CPU time 350.96 seconds
Started Jun 07 07:21:38 PM PDT 24
Finished Jun 07 07:27:40 PM PDT 24
Peak memory 200344 kb
Host smart-8695d579-d90f-4a6f-a650-40c773dfd20d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3860258100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.3860258100
Directory /workspace/17.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/17.uart_loopback.2257888479
Short name T543
Test name
Test status
Simulation time 10178967428 ps
CPU time 6.81 seconds
Started Jun 07 07:21:38 PM PDT 24
Finished Jun 07 07:21:56 PM PDT 24
Peak memory 200308 kb
Host smart-f50c929d-d320-467e-ab37-1d6b2f74f463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257888479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_loopback.2257888479
Directory /workspace/17.uart_loopback/latest

Test location /workspace/coverage/default/17.uart_noise_filter.1190999977
Short name T754
Test name
Test status
Simulation time 4410000172 ps
CPU time 1.74 seconds
Started Jun 07 07:21:36 PM PDT 24
Finished Jun 07 07:21:48 PM PDT 24
Peak memory 200388 kb
Host smart-f20ff891-26f5-4e8e-b8da-c6a276326c74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190999977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_noise_filter.1190999977
Directory /workspace/17.uart_noise_filter/latest

Test location /workspace/coverage/default/17.uart_perf.4147154885
Short name T276
Test name
Test status
Simulation time 13316662188 ps
CPU time 130.73 seconds
Started Jun 07 07:21:41 PM PDT 24
Finished Jun 07 07:24:03 PM PDT 24
Peak memory 200384 kb
Host smart-af863939-beff-4533-8f22-64c25c38db9f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4147154885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.4147154885
Directory /workspace/17.uart_perf/latest

Test location /workspace/coverage/default/17.uart_rx_oversample.3202658764
Short name T407
Test name
Test status
Simulation time 4349362508 ps
CPU time 8.39 seconds
Started Jun 07 07:21:41 PM PDT 24
Finished Jun 07 07:22:01 PM PDT 24
Peak memory 199284 kb
Host smart-1e0e75a5-c0f3-4815-b15c-0a0ac8a2d99e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3202658764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.3202658764
Directory /workspace/17.uart_rx_oversample/latest

Test location /workspace/coverage/default/17.uart_rx_parity_err.2195806769
Short name T177
Test name
Test status
Simulation time 55208545476 ps
CPU time 49.73 seconds
Started Jun 07 07:21:36 PM PDT 24
Finished Jun 07 07:22:36 PM PDT 24
Peak memory 200376 kb
Host smart-470667b6-4df4-4c83-94e5-7f8f4c62d25a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195806769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.2195806769
Directory /workspace/17.uart_rx_parity_err/latest

Test location /workspace/coverage/default/17.uart_rx_start_bit_filter.4232857960
Short name T293
Test name
Test status
Simulation time 2020348676 ps
CPU time 3.43 seconds
Started Jun 07 07:21:38 PM PDT 24
Finished Jun 07 07:21:52 PM PDT 24
Peak memory 195952 kb
Host smart-e3fffdde-363f-49dd-a301-44d3ae1a7def
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232857960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.4232857960
Directory /workspace/17.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/17.uart_smoke.4262450166
Short name T979
Test name
Test status
Simulation time 976249795 ps
CPU time 3.72 seconds
Started Jun 07 07:21:38 PM PDT 24
Finished Jun 07 07:21:52 PM PDT 24
Peak memory 198836 kb
Host smart-ded3a490-eafc-401b-b90a-fb587d725e91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262450166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_smoke.4262450166
Directory /workspace/17.uart_smoke/latest

Test location /workspace/coverage/default/17.uart_tx_ovrd.1522515405
Short name T803
Test name
Test status
Simulation time 934056236 ps
CPU time 1.37 seconds
Started Jun 07 07:21:37 PM PDT 24
Finished Jun 07 07:21:49 PM PDT 24
Peak memory 198448 kb
Host smart-26a03423-0045-47f7-8a7f-58054bc09ce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522515405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.1522515405
Directory /workspace/17.uart_tx_ovrd/latest

Test location /workspace/coverage/default/17.uart_tx_rx.3118222051
Short name T673
Test name
Test status
Simulation time 111136059847 ps
CPU time 231.49 seconds
Started Jun 07 07:21:35 PM PDT 24
Finished Jun 07 07:25:37 PM PDT 24
Peak memory 200496 kb
Host smart-b708bc1c-2261-42e7-a7f8-7319d3493ff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118222051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.3118222051
Directory /workspace/17.uart_tx_rx/latest

Test location /workspace/coverage/default/170.uart_fifo_reset.1127070495
Short name T966
Test name
Test status
Simulation time 170029961527 ps
CPU time 275.62 seconds
Started Jun 07 07:27:22 PM PDT 24
Finished Jun 07 07:32:01 PM PDT 24
Peak memory 200408 kb
Host smart-7a3fdc9c-a537-4683-b20b-7357bb5e3eca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127070495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.1127070495
Directory /workspace/170.uart_fifo_reset/latest

Test location /workspace/coverage/default/171.uart_fifo_reset.630284738
Short name T613
Test name
Test status
Simulation time 37432603587 ps
CPU time 15.79 seconds
Started Jun 07 07:27:22 PM PDT 24
Finished Jun 07 07:27:41 PM PDT 24
Peak memory 200388 kb
Host smart-81bf240b-7037-46b1-9886-0c8e8b82b3a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630284738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.630284738
Directory /workspace/171.uart_fifo_reset/latest

Test location /workspace/coverage/default/172.uart_fifo_reset.213179790
Short name T913
Test name
Test status
Simulation time 90460864409 ps
CPU time 42.74 seconds
Started Jun 07 07:27:22 PM PDT 24
Finished Jun 07 07:28:09 PM PDT 24
Peak memory 200412 kb
Host smart-dd93c7b5-fc5d-4895-bd26-bb6de00d74d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213179790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.213179790
Directory /workspace/172.uart_fifo_reset/latest

Test location /workspace/coverage/default/173.uart_fifo_reset.2387473816
Short name T735
Test name
Test status
Simulation time 149564824390 ps
CPU time 230.17 seconds
Started Jun 07 07:27:20 PM PDT 24
Finished Jun 07 07:31:12 PM PDT 24
Peak memory 200412 kb
Host smart-ced95494-f438-4f34-bc4e-792c55c165ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387473816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.2387473816
Directory /workspace/173.uart_fifo_reset/latest

Test location /workspace/coverage/default/175.uart_fifo_reset.2922248361
Short name T219
Test name
Test status
Simulation time 38001128561 ps
CPU time 52.85 seconds
Started Jun 07 07:27:20 PM PDT 24
Finished Jun 07 07:28:16 PM PDT 24
Peak memory 200372 kb
Host smart-9d73657d-7467-42ad-b885-084d62ef8223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922248361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.2922248361
Directory /workspace/175.uart_fifo_reset/latest

Test location /workspace/coverage/default/177.uart_fifo_reset.2073320395
Short name T454
Test name
Test status
Simulation time 73874793028 ps
CPU time 30.53 seconds
Started Jun 07 07:27:21 PM PDT 24
Finished Jun 07 07:27:54 PM PDT 24
Peak memory 200396 kb
Host smart-1adbd7c6-1b2a-4e30-aee2-7fe8245872f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073320395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.2073320395
Directory /workspace/177.uart_fifo_reset/latest

Test location /workspace/coverage/default/179.uart_fifo_reset.92217493
Short name T970
Test name
Test status
Simulation time 28327707845 ps
CPU time 51.04 seconds
Started Jun 07 07:27:22 PM PDT 24
Finished Jun 07 07:28:18 PM PDT 24
Peak memory 200404 kb
Host smart-0133a9bf-0fd5-4604-87e4-8938412aa53d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92217493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.92217493
Directory /workspace/179.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_alert_test.1144005662
Short name T825
Test name
Test status
Simulation time 101036733 ps
CPU time 0.56 seconds
Started Jun 07 07:21:45 PM PDT 24
Finished Jun 07 07:21:58 PM PDT 24
Peak memory 195684 kb
Host smart-1e273870-85de-4cdc-ae5c-ec929bac3a75
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144005662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.1144005662
Directory /workspace/18.uart_alert_test/latest

Test location /workspace/coverage/default/18.uart_fifo_full.53656660
Short name T310
Test name
Test status
Simulation time 31240121002 ps
CPU time 54.52 seconds
Started Jun 07 07:21:46 PM PDT 24
Finished Jun 07 07:22:53 PM PDT 24
Peak memory 200356 kb
Host smart-418c49c9-1e00-403c-b471-4c76012c7f99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53656660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.53656660
Directory /workspace/18.uart_fifo_full/latest

Test location /workspace/coverage/default/18.uart_fifo_overflow.1951601742
Short name T751
Test name
Test status
Simulation time 52241037955 ps
CPU time 57.59 seconds
Started Jun 07 07:21:45 PM PDT 24
Finished Jun 07 07:22:55 PM PDT 24
Peak memory 200332 kb
Host smart-10f0aabc-4579-4967-ad6e-034675235beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951601742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.1951601742
Directory /workspace/18.uart_fifo_overflow/latest

Test location /workspace/coverage/default/18.uart_fifo_reset.4049288029
Short name T668
Test name
Test status
Simulation time 44227943546 ps
CPU time 61.67 seconds
Started Jun 07 07:21:48 PM PDT 24
Finished Jun 07 07:23:02 PM PDT 24
Peak memory 200304 kb
Host smart-8a8f342e-57bc-47d4-9358-5fbe202e0ffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049288029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.4049288029
Directory /workspace/18.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_intr.3200198015
Short name T341
Test name
Test status
Simulation time 18914540347 ps
CPU time 6.24 seconds
Started Jun 07 07:21:47 PM PDT 24
Finished Jun 07 07:22:05 PM PDT 24
Peak memory 199692 kb
Host smart-5b57868d-d8d4-478f-8e0d-3294504a8fb4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200198015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.3200198015
Directory /workspace/18.uart_intr/latest

Test location /workspace/coverage/default/18.uart_long_xfer_wo_dly.3977250442
Short name T847
Test name
Test status
Simulation time 124691627933 ps
CPU time 1000.66 seconds
Started Jun 07 07:21:47 PM PDT 24
Finished Jun 07 07:38:40 PM PDT 24
Peak memory 200428 kb
Host smart-60ebc4c5-17be-4092-892c-13b67db590f3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3977250442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.3977250442
Directory /workspace/18.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/18.uart_loopback.2055252653
Short name T354
Test name
Test status
Simulation time 4119925688 ps
CPU time 2.45 seconds
Started Jun 07 07:21:44 PM PDT 24
Finished Jun 07 07:21:58 PM PDT 24
Peak memory 196556 kb
Host smart-43846436-ea44-4fda-a24c-4968019141b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055252653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_loopback.2055252653
Directory /workspace/18.uart_loopback/latest

Test location /workspace/coverage/default/18.uart_perf.4200971322
Short name T696
Test name
Test status
Simulation time 19513061019 ps
CPU time 564.02 seconds
Started Jun 07 07:21:46 PM PDT 24
Finished Jun 07 07:31:22 PM PDT 24
Peak memory 200300 kb
Host smart-80cf8645-c0e4-43bd-89c8-2bbd8526357e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4200971322 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.4200971322
Directory /workspace/18.uart_perf/latest

Test location /workspace/coverage/default/18.uart_rx_oversample.2949987902
Short name T74
Test name
Test status
Simulation time 5027353701 ps
CPU time 14.11 seconds
Started Jun 07 07:21:46 PM PDT 24
Finished Jun 07 07:22:12 PM PDT 24
Peak memory 198460 kb
Host smart-8f6ed946-e93c-4a51-8101-d3c630d71e46
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2949987902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.2949987902
Directory /workspace/18.uart_rx_oversample/latest

Test location /workspace/coverage/default/18.uart_rx_parity_err.1614771590
Short name T487
Test name
Test status
Simulation time 134098132440 ps
CPU time 95.73 seconds
Started Jun 07 07:21:47 PM PDT 24
Finished Jun 07 07:23:35 PM PDT 24
Peak memory 200400 kb
Host smart-ac9cc376-0546-47fa-a6eb-cfd6ccc81e18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614771590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.1614771590
Directory /workspace/18.uart_rx_parity_err/latest

Test location /workspace/coverage/default/18.uart_rx_start_bit_filter.1812006637
Short name T713
Test name
Test status
Simulation time 29831440739 ps
CPU time 25.1 seconds
Started Jun 07 07:21:45 PM PDT 24
Finished Jun 07 07:22:22 PM PDT 24
Peak memory 196352 kb
Host smart-e1f0df55-83c0-4af8-a509-b7eecee7d0e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812006637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.1812006637
Directory /workspace/18.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/18.uart_smoke.1537732406
Short name T629
Test name
Test status
Simulation time 569066635 ps
CPU time 0.85 seconds
Started Jun 07 07:21:46 PM PDT 24
Finished Jun 07 07:22:00 PM PDT 24
Peak memory 199968 kb
Host smart-fc9c18f5-d653-478f-8e21-fbb05030dbbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537732406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_smoke.1537732406
Directory /workspace/18.uart_smoke/latest

Test location /workspace/coverage/default/18.uart_stress_all.3414784661
Short name T552
Test name
Test status
Simulation time 158500522659 ps
CPU time 1981.3 seconds
Started Jun 07 07:21:45 PM PDT 24
Finished Jun 07 07:54:58 PM PDT 24
Peak memory 200316 kb
Host smart-cbe24fd0-d138-4c39-a4fc-8ead72d9f3ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414784661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.3414784661
Directory /workspace/18.uart_stress_all/latest

Test location /workspace/coverage/default/18.uart_tx_ovrd.1433864849
Short name T35
Test name
Test status
Simulation time 6206426116 ps
CPU time 23.41 seconds
Started Jun 07 07:21:44 PM PDT 24
Finished Jun 07 07:22:19 PM PDT 24
Peak memory 200216 kb
Host smart-e9627421-139b-4001-af49-142114cc8080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433864849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.1433864849
Directory /workspace/18.uart_tx_ovrd/latest

Test location /workspace/coverage/default/18.uart_tx_rx.698382700
Short name T441
Test name
Test status
Simulation time 44638056354 ps
CPU time 84.55 seconds
Started Jun 07 07:21:44 PM PDT 24
Finished Jun 07 07:23:21 PM PDT 24
Peak memory 200392 kb
Host smart-bddc4a15-ba17-4e71-be05-eb75809d128e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698382700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.698382700
Directory /workspace/18.uart_tx_rx/latest

Test location /workspace/coverage/default/180.uart_fifo_reset.92698661
Short name T869
Test name
Test status
Simulation time 48284071005 ps
CPU time 56.89 seconds
Started Jun 07 07:27:21 PM PDT 24
Finished Jun 07 07:28:21 PM PDT 24
Peak memory 200340 kb
Host smart-fd29b1d5-0621-4d34-9e60-80d23f84864e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92698661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.92698661
Directory /workspace/180.uart_fifo_reset/latest

Test location /workspace/coverage/default/181.uart_fifo_reset.1572537368
Short name T145
Test name
Test status
Simulation time 33137048612 ps
CPU time 27.97 seconds
Started Jun 07 07:27:21 PM PDT 24
Finished Jun 07 07:27:52 PM PDT 24
Peak memory 200304 kb
Host smart-738927cd-debf-4005-8fc0-e0f9644d221d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572537368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.1572537368
Directory /workspace/181.uart_fifo_reset/latest

Test location /workspace/coverage/default/182.uart_fifo_reset.1089623369
Short name T516
Test name
Test status
Simulation time 86154912501 ps
CPU time 29.65 seconds
Started Jun 07 07:27:22 PM PDT 24
Finished Jun 07 07:27:55 PM PDT 24
Peak memory 200084 kb
Host smart-38f4a9eb-1c84-4704-b1eb-05d7bf9d9ccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089623369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.1089623369
Directory /workspace/182.uart_fifo_reset/latest

Test location /workspace/coverage/default/183.uart_fifo_reset.1505403565
Short name T829
Test name
Test status
Simulation time 237929579044 ps
CPU time 113.74 seconds
Started Jun 07 07:27:05 PM PDT 24
Finished Jun 07 07:29:01 PM PDT 24
Peak memory 200316 kb
Host smart-e39f7ec7-030f-4b91-b7b9-312907e244e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505403565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.1505403565
Directory /workspace/183.uart_fifo_reset/latest

Test location /workspace/coverage/default/185.uart_fifo_reset.2529614208
Short name T236
Test name
Test status
Simulation time 63112598089 ps
CPU time 28.85 seconds
Started Jun 07 07:27:04 PM PDT 24
Finished Jun 07 07:27:34 PM PDT 24
Peak memory 200392 kb
Host smart-0dfab67f-fac0-4377-8aa2-d73c1f00a2d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529614208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.2529614208
Directory /workspace/185.uart_fifo_reset/latest

Test location /workspace/coverage/default/186.uart_fifo_reset.3776347476
Short name T566
Test name
Test status
Simulation time 9374959525 ps
CPU time 16.87 seconds
Started Jun 07 07:27:05 PM PDT 24
Finished Jun 07 07:27:24 PM PDT 24
Peak memory 200396 kb
Host smart-8af5161b-bbab-4120-a453-e659a8fba480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776347476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.3776347476
Directory /workspace/186.uart_fifo_reset/latest

Test location /workspace/coverage/default/187.uart_fifo_reset.3748350652
Short name T939
Test name
Test status
Simulation time 29872516427 ps
CPU time 43.1 seconds
Started Jun 07 07:27:06 PM PDT 24
Finished Jun 07 07:27:51 PM PDT 24
Peak memory 200440 kb
Host smart-39ecbf86-489b-426d-a071-36d915ce7839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748350652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.3748350652
Directory /workspace/187.uart_fifo_reset/latest

Test location /workspace/coverage/default/188.uart_fifo_reset.466016654
Short name T414
Test name
Test status
Simulation time 13032022320 ps
CPU time 13.73 seconds
Started Jun 07 07:27:04 PM PDT 24
Finished Jun 07 07:27:19 PM PDT 24
Peak memory 200412 kb
Host smart-4d5b8bfc-4901-4541-b844-14326191c4db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466016654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.466016654
Directory /workspace/188.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_alert_test.983286232
Short name T559
Test name
Test status
Simulation time 13448830 ps
CPU time 0.57 seconds
Started Jun 07 07:21:51 PM PDT 24
Finished Jun 07 07:22:04 PM PDT 24
Peak memory 196052 kb
Host smart-360fae96-b4c9-472f-9ecd-36ee0b8cfd7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983286232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.983286232
Directory /workspace/19.uart_alert_test/latest

Test location /workspace/coverage/default/19.uart_fifo_full.460692048
Short name T832
Test name
Test status
Simulation time 74023033359 ps
CPU time 120.81 seconds
Started Jun 07 07:21:45 PM PDT 24
Finished Jun 07 07:23:58 PM PDT 24
Peak memory 200392 kb
Host smart-72fa856d-0f08-465f-80e4-e5b0e6ad5a5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460692048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.460692048
Directory /workspace/19.uart_fifo_full/latest

Test location /workspace/coverage/default/19.uart_fifo_overflow.2851716729
Short name T996
Test name
Test status
Simulation time 72352273927 ps
CPU time 68.96 seconds
Started Jun 07 07:21:48 PM PDT 24
Finished Jun 07 07:23:09 PM PDT 24
Peak memory 200240 kb
Host smart-b539f6e1-82d2-429f-a9a8-cd1a8ec420ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851716729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.2851716729
Directory /workspace/19.uart_fifo_overflow/latest

Test location /workspace/coverage/default/19.uart_long_xfer_wo_dly.1434186868
Short name T967
Test name
Test status
Simulation time 79403930772 ps
CPU time 188.72 seconds
Started Jun 07 07:21:47 PM PDT 24
Finished Jun 07 07:25:07 PM PDT 24
Peak memory 200380 kb
Host smart-675586d6-bab1-4682-bb7a-051cc75c9a98
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1434186868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.1434186868
Directory /workspace/19.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/19.uart_loopback.2183312959
Short name T868
Test name
Test status
Simulation time 4700318106 ps
CPU time 3.14 seconds
Started Jun 07 07:21:45 PM PDT 24
Finished Jun 07 07:22:00 PM PDT 24
Peak memory 198428 kb
Host smart-2eb0a944-66a2-4ce2-bd2f-1752ec2e25a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183312959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_loopback.2183312959
Directory /workspace/19.uart_loopback/latest

Test location /workspace/coverage/default/19.uart_perf.3804731686
Short name T584
Test name
Test status
Simulation time 7019438289 ps
CPU time 211.35 seconds
Started Jun 07 07:21:45 PM PDT 24
Finished Jun 07 07:25:28 PM PDT 24
Peak memory 200396 kb
Host smart-19be4113-610c-4714-85f5-3d158c68a46c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3804731686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.3804731686
Directory /workspace/19.uart_perf/latest

Test location /workspace/coverage/default/19.uart_rx_oversample.2220172008
Short name T395
Test name
Test status
Simulation time 3362329702 ps
CPU time 7 seconds
Started Jun 07 07:21:44 PM PDT 24
Finished Jun 07 07:22:03 PM PDT 24
Peak memory 199292 kb
Host smart-1ca3ac9d-ec47-48ba-b34c-4f81fbf93aff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2220172008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.2220172008
Directory /workspace/19.uart_rx_oversample/latest

Test location /workspace/coverage/default/19.uart_rx_parity_err.593895308
Short name T984
Test name
Test status
Simulation time 97537865524 ps
CPU time 178.74 seconds
Started Jun 07 07:21:45 PM PDT 24
Finished Jun 07 07:24:55 PM PDT 24
Peak memory 200336 kb
Host smart-32ffe17a-41a6-44d5-9ac0-cef46a0937c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593895308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.593895308
Directory /workspace/19.uart_rx_parity_err/latest

Test location /workspace/coverage/default/19.uart_rx_start_bit_filter.3659805217
Short name T627
Test name
Test status
Simulation time 28289130816 ps
CPU time 30.4 seconds
Started Jun 07 07:21:46 PM PDT 24
Finished Jun 07 07:22:29 PM PDT 24
Peak memory 196672 kb
Host smart-ffd58ed5-9d81-48da-a671-ec812f2730b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659805217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.3659805217
Directory /workspace/19.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/19.uart_smoke.1952146726
Short name T355
Test name
Test status
Simulation time 702273473 ps
CPU time 2.19 seconds
Started Jun 07 07:21:46 PM PDT 24
Finished Jun 07 07:22:01 PM PDT 24
Peak memory 199900 kb
Host smart-e0412d83-f506-463c-b451-caeddf81f7bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952146726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_smoke.1952146726
Directory /workspace/19.uart_smoke/latest

Test location /workspace/coverage/default/19.uart_stress_all.2145916348
Short name T710
Test name
Test status
Simulation time 237717099774 ps
CPU time 178.14 seconds
Started Jun 07 07:21:51 PM PDT 24
Finished Jun 07 07:25:02 PM PDT 24
Peak memory 200380 kb
Host smart-8c848be1-40f6-4598-82af-c234f724a823
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145916348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.2145916348
Directory /workspace/19.uart_stress_all/latest

Test location /workspace/coverage/default/19.uart_tx_ovrd.1141805171
Short name T854
Test name
Test status
Simulation time 7474996223 ps
CPU time 13.88 seconds
Started Jun 07 07:21:45 PM PDT 24
Finished Jun 07 07:22:10 PM PDT 24
Peak memory 200356 kb
Host smart-84610c3d-4814-468c-83f3-39df161e1c5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141805171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.1141805171
Directory /workspace/19.uart_tx_ovrd/latest

Test location /workspace/coverage/default/19.uart_tx_rx.3224382870
Short name T295
Test name
Test status
Simulation time 75748222091 ps
CPU time 49.08 seconds
Started Jun 07 07:21:45 PM PDT 24
Finished Jun 07 07:22:46 PM PDT 24
Peak memory 200420 kb
Host smart-449ee638-35a7-4976-8749-e02487a3f1a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224382870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.3224382870
Directory /workspace/19.uart_tx_rx/latest

Test location /workspace/coverage/default/190.uart_fifo_reset.1539547885
Short name T1073
Test name
Test status
Simulation time 132857787164 ps
CPU time 253.12 seconds
Started Jun 07 07:27:05 PM PDT 24
Finished Jun 07 07:31:20 PM PDT 24
Peak memory 200384 kb
Host smart-078bcab8-4581-4e6a-b6fc-345c7ea226c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539547885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.1539547885
Directory /workspace/190.uart_fifo_reset/latest

Test location /workspace/coverage/default/191.uart_fifo_reset.438634943
Short name T636
Test name
Test status
Simulation time 84781674520 ps
CPU time 38.42 seconds
Started Jun 07 07:27:04 PM PDT 24
Finished Jun 07 07:27:44 PM PDT 24
Peak memory 200388 kb
Host smart-51a65960-891b-47fc-bf47-7c242423de87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438634943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.438634943
Directory /workspace/191.uart_fifo_reset/latest

Test location /workspace/coverage/default/193.uart_fifo_reset.856866602
Short name T215
Test name
Test status
Simulation time 41457692519 ps
CPU time 75.07 seconds
Started Jun 07 07:27:06 PM PDT 24
Finished Jun 07 07:28:23 PM PDT 24
Peak memory 200352 kb
Host smart-d90dc4e2-cb88-4195-aa17-fcf0d399398d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856866602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.856866602
Directory /workspace/193.uart_fifo_reset/latest

Test location /workspace/coverage/default/194.uart_fifo_reset.340059153
Short name T969
Test name
Test status
Simulation time 32881657756 ps
CPU time 33.95 seconds
Started Jun 07 07:27:06 PM PDT 24
Finished Jun 07 07:27:42 PM PDT 24
Peak memory 200404 kb
Host smart-2a61005d-af1e-4cfe-a251-76d0fe92e328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340059153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.340059153
Directory /workspace/194.uart_fifo_reset/latest

Test location /workspace/coverage/default/195.uart_fifo_reset.14084211
Short name T299
Test name
Test status
Simulation time 150137042570 ps
CPU time 57.54 seconds
Started Jun 07 07:27:07 PM PDT 24
Finished Jun 07 07:28:06 PM PDT 24
Peak memory 200320 kb
Host smart-effd919b-e939-42ed-8a7b-577bfcbc44d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14084211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.14084211
Directory /workspace/195.uart_fifo_reset/latest

Test location /workspace/coverage/default/196.uart_fifo_reset.304129027
Short name T855
Test name
Test status
Simulation time 37052242122 ps
CPU time 20.72 seconds
Started Jun 07 07:27:06 PM PDT 24
Finished Jun 07 07:27:28 PM PDT 24
Peak memory 200284 kb
Host smart-675ead73-d19f-476a-9f7b-2236a59f60e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304129027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.304129027
Directory /workspace/196.uart_fifo_reset/latest

Test location /workspace/coverage/default/197.uart_fifo_reset.2857344544
Short name T768
Test name
Test status
Simulation time 20072396487 ps
CPU time 39.63 seconds
Started Jun 07 07:27:06 PM PDT 24
Finished Jun 07 07:27:47 PM PDT 24
Peak memory 200264 kb
Host smart-fceb211d-4020-4846-974d-dcb933384b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857344544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.2857344544
Directory /workspace/197.uart_fifo_reset/latest

Test location /workspace/coverage/default/198.uart_fifo_reset.968854488
Short name T1066
Test name
Test status
Simulation time 82889337413 ps
CPU time 127.09 seconds
Started Jun 07 07:27:06 PM PDT 24
Finished Jun 07 07:29:15 PM PDT 24
Peak memory 200432 kb
Host smart-17946648-17e3-438f-9019-b7f2aeee27b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968854488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.968854488
Directory /workspace/198.uart_fifo_reset/latest

Test location /workspace/coverage/default/199.uart_fifo_reset.2994239501
Short name T882
Test name
Test status
Simulation time 30788962393 ps
CPU time 28.35 seconds
Started Jun 07 07:27:21 PM PDT 24
Finished Jun 07 07:27:52 PM PDT 24
Peak memory 200336 kb
Host smart-26c55e38-264e-48b8-98c0-fee367399107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994239501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.2994239501
Directory /workspace/199.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_alert_test.2097068031
Short name T373
Test name
Test status
Simulation time 12893980 ps
CPU time 0.54 seconds
Started Jun 07 07:19:47 PM PDT 24
Finished Jun 07 07:20:12 PM PDT 24
Peak memory 195992 kb
Host smart-489b8ced-c063-4077-aef0-f23cdfdc1d08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097068031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.2097068031
Directory /workspace/2.uart_alert_test/latest

Test location /workspace/coverage/default/2.uart_fifo_full.3868407418
Short name T1012
Test name
Test status
Simulation time 27977581745 ps
CPU time 12.61 seconds
Started Jun 07 07:19:42 PM PDT 24
Finished Jun 07 07:20:16 PM PDT 24
Peak memory 200404 kb
Host smart-98461cfa-d794-4975-a7c0-6be49283d999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868407418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.3868407418
Directory /workspace/2.uart_fifo_full/latest

Test location /workspace/coverage/default/2.uart_fifo_overflow.3791049775
Short name T137
Test name
Test status
Simulation time 112596543728 ps
CPU time 133.67 seconds
Started Jun 07 07:19:41 PM PDT 24
Finished Jun 07 07:22:17 PM PDT 24
Peak memory 200424 kb
Host smart-484e5ca6-d25c-44e9-9aad-1b91b2f96863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791049775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.3791049775
Directory /workspace/2.uart_fifo_overflow/latest

Test location /workspace/coverage/default/2.uart_intr.1409538296
Short name T522
Test name
Test status
Simulation time 6971948977 ps
CPU time 15.25 seconds
Started Jun 07 07:19:41 PM PDT 24
Finished Jun 07 07:20:19 PM PDT 24
Peak memory 200312 kb
Host smart-bfbcda66-63f4-4741-b234-753579be0110
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409538296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.1409538296
Directory /workspace/2.uart_intr/latest

Test location /workspace/coverage/default/2.uart_long_xfer_wo_dly.574353242
Short name T1020
Test name
Test status
Simulation time 118230264536 ps
CPU time 231.07 seconds
Started Jun 07 07:19:48 PM PDT 24
Finished Jun 07 07:24:03 PM PDT 24
Peak memory 200376 kb
Host smart-f6349a03-a584-4b07-9f12-d651ec543137
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=574353242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.574353242
Directory /workspace/2.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/2.uart_loopback.3940834384
Short name T443
Test name
Test status
Simulation time 12418445877 ps
CPU time 5.33 seconds
Started Jun 07 07:19:40 PM PDT 24
Finished Jun 07 07:20:08 PM PDT 24
Peak memory 199988 kb
Host smart-9e131f9c-302b-414a-8469-d648bdb98f38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940834384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_loopback.3940834384
Directory /workspace/2.uart_loopback/latest

Test location /workspace/coverage/default/2.uart_perf.2686865387
Short name T476
Test name
Test status
Simulation time 20234684973 ps
CPU time 63.57 seconds
Started Jun 07 07:19:42 PM PDT 24
Finished Jun 07 07:21:09 PM PDT 24
Peak memory 200388 kb
Host smart-88a0a0e5-2dda-49b5-950a-bc27068d2e83
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2686865387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.2686865387
Directory /workspace/2.uart_perf/latest

Test location /workspace/coverage/default/2.uart_rx_oversample.2881322644
Short name T976
Test name
Test status
Simulation time 6233135919 ps
CPU time 54.76 seconds
Started Jun 07 07:19:41 PM PDT 24
Finished Jun 07 07:20:58 PM PDT 24
Peak memory 200280 kb
Host smart-64510f97-5010-4be8-9559-bc585e05ee2c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2881322644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.2881322644
Directory /workspace/2.uart_rx_oversample/latest

Test location /workspace/coverage/default/2.uart_rx_parity_err.14012372
Short name T791
Test name
Test status
Simulation time 89529940186 ps
CPU time 18.92 seconds
Started Jun 07 07:19:45 PM PDT 24
Finished Jun 07 07:20:28 PM PDT 24
Peak memory 200264 kb
Host smart-ccc858d9-8a08-4f92-bb3a-797ca803cfe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14012372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.14012372
Directory /workspace/2.uart_rx_parity_err/latest

Test location /workspace/coverage/default/2.uart_rx_start_bit_filter.640117638
Short name T981
Test name
Test status
Simulation time 5660368361 ps
CPU time 1.57 seconds
Started Jun 07 07:19:41 PM PDT 24
Finished Jun 07 07:20:05 PM PDT 24
Peak memory 196508 kb
Host smart-1ccd605e-b677-477b-ba72-8e740c18562d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640117638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.640117638
Directory /workspace/2.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/2.uart_sec_cm.268653039
Short name T93
Test name
Test status
Simulation time 117513654 ps
CPU time 0.86 seconds
Started Jun 07 07:19:51 PM PDT 24
Finished Jun 07 07:20:17 PM PDT 24
Peak memory 218976 kb
Host smart-7bd39a54-8da1-4ba0-a361-d6463fd86933
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268653039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.268653039
Directory /workspace/2.uart_sec_cm/latest

Test location /workspace/coverage/default/2.uart_smoke.2566152161
Short name T604
Test name
Test status
Simulation time 631517970 ps
CPU time 1.81 seconds
Started Jun 07 07:19:42 PM PDT 24
Finished Jun 07 07:20:07 PM PDT 24
Peak memory 198680 kb
Host smart-91731ddc-346b-4111-87b5-5fdd118a1e4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566152161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_smoke.2566152161
Directory /workspace/2.uart_smoke/latest

Test location /workspace/coverage/default/2.uart_tx_ovrd.1039940692
Short name T681
Test name
Test status
Simulation time 1603597602 ps
CPU time 5.23 seconds
Started Jun 07 07:19:43 PM PDT 24
Finished Jun 07 07:20:12 PM PDT 24
Peak memory 199184 kb
Host smart-1a993f38-523c-4286-8b0a-c0030b1e79e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039940692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.1039940692
Directory /workspace/2.uart_tx_ovrd/latest

Test location /workspace/coverage/default/2.uart_tx_rx.3071012253
Short name T265
Test name
Test status
Simulation time 154985080972 ps
CPU time 71.44 seconds
Started Jun 07 07:19:41 PM PDT 24
Finished Jun 07 07:21:15 PM PDT 24
Peak memory 200324 kb
Host smart-d9ae6337-2764-486b-b852-edcd26ec96e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071012253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.3071012253
Directory /workspace/2.uart_tx_rx/latest

Test location /workspace/coverage/default/20.uart_alert_test.593021955
Short name T692
Test name
Test status
Simulation time 55371763 ps
CPU time 0.54 seconds
Started Jun 07 07:21:58 PM PDT 24
Finished Jun 07 07:22:10 PM PDT 24
Peak memory 195772 kb
Host smart-bfeb2d27-ef1e-4b71-b79c-b87c26b1a7bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593021955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.593021955
Directory /workspace/20.uart_alert_test/latest

Test location /workspace/coverage/default/20.uart_fifo_full.3550116004
Short name T896
Test name
Test status
Simulation time 107852941521 ps
CPU time 90.13 seconds
Started Jun 07 07:21:54 PM PDT 24
Finished Jun 07 07:23:36 PM PDT 24
Peak memory 200420 kb
Host smart-4f0802a5-327a-43c2-9b68-a1e266f57a79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550116004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.3550116004
Directory /workspace/20.uart_fifo_full/latest

Test location /workspace/coverage/default/20.uart_fifo_overflow.1706092403
Short name T956
Test name
Test status
Simulation time 25249016922 ps
CPU time 11.63 seconds
Started Jun 07 07:21:51 PM PDT 24
Finished Jun 07 07:22:15 PM PDT 24
Peak memory 200392 kb
Host smart-7507049a-4483-4278-ae71-59996a0b999d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706092403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.1706092403
Directory /workspace/20.uart_fifo_overflow/latest

Test location /workspace/coverage/default/20.uart_fifo_reset.3460144076
Short name T526
Test name
Test status
Simulation time 12357006105 ps
CPU time 22.08 seconds
Started Jun 07 07:21:51 PM PDT 24
Finished Jun 07 07:22:26 PM PDT 24
Peak memory 200364 kb
Host smart-413aa335-8f6a-4e5a-8218-5d004e53d86a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460144076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.3460144076
Directory /workspace/20.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_intr.1567454733
Short name T69
Test name
Test status
Simulation time 49025657360 ps
CPU time 108.53 seconds
Started Jun 07 07:21:54 PM PDT 24
Finished Jun 07 07:23:55 PM PDT 24
Peak memory 200392 kb
Host smart-2c80f94e-ec4c-45d2-a274-bc947e90bc5a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567454733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.1567454733
Directory /workspace/20.uart_intr/latest

Test location /workspace/coverage/default/20.uart_long_xfer_wo_dly.1379396173
Short name T73
Test name
Test status
Simulation time 43574436717 ps
CPU time 194.66 seconds
Started Jun 07 07:21:52 PM PDT 24
Finished Jun 07 07:25:19 PM PDT 24
Peak memory 200368 kb
Host smart-e500b582-92ae-450b-bd76-af17b0507f0d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1379396173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.1379396173
Directory /workspace/20.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/20.uart_loopback.3028668691
Short name T518
Test name
Test status
Simulation time 252566117 ps
CPU time 0.99 seconds
Started Jun 07 07:21:54 PM PDT 24
Finished Jun 07 07:22:07 PM PDT 24
Peak memory 195736 kb
Host smart-67fc42e2-da0a-42ac-8106-b346a5ddd88d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028668691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_loopback.3028668691
Directory /workspace/20.uart_loopback/latest

Test location /workspace/coverage/default/20.uart_perf.2676647791
Short name T336
Test name
Test status
Simulation time 16151004580 ps
CPU time 223.53 seconds
Started Jun 07 07:21:51 PM PDT 24
Finished Jun 07 07:25:47 PM PDT 24
Peak memory 200356 kb
Host smart-f07b7ac8-4827-436b-bfa8-dead6b1ff91a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2676647791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.2676647791
Directory /workspace/20.uart_perf/latest

Test location /workspace/coverage/default/20.uart_rx_oversample.706762830
Short name T764
Test name
Test status
Simulation time 1411915314 ps
CPU time 0.94 seconds
Started Jun 07 07:21:51 PM PDT 24
Finished Jun 07 07:22:04 PM PDT 24
Peak memory 195972 kb
Host smart-3c59c796-4ec5-4b40-b7d6-1c5a99df5760
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=706762830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.706762830
Directory /workspace/20.uart_rx_oversample/latest

Test location /workspace/coverage/default/20.uart_rx_parity_err.1438354722
Short name T938
Test name
Test status
Simulation time 335514098494 ps
CPU time 31.53 seconds
Started Jun 07 07:21:53 PM PDT 24
Finished Jun 07 07:22:37 PM PDT 24
Peak memory 200320 kb
Host smart-d04c984b-e3b4-462b-9621-93498aafd175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438354722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.1438354722
Directory /workspace/20.uart_rx_parity_err/latest

Test location /workspace/coverage/default/20.uart_rx_start_bit_filter.744355541
Short name T491
Test name
Test status
Simulation time 4110442789 ps
CPU time 1.8 seconds
Started Jun 07 07:21:51 PM PDT 24
Finished Jun 07 07:22:04 PM PDT 24
Peak memory 196436 kb
Host smart-2cb921f2-0b76-48c9-9346-b6abca9e646b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744355541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.744355541
Directory /workspace/20.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/20.uart_smoke.1222201716
Short name T652
Test name
Test status
Simulation time 766739784 ps
CPU time 1.24 seconds
Started Jun 07 07:21:51 PM PDT 24
Finished Jun 07 07:22:05 PM PDT 24
Peak memory 198728 kb
Host smart-ce0f33e1-fa78-4d52-8351-cb28dec3f48f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222201716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_smoke.1222201716
Directory /workspace/20.uart_smoke/latest

Test location /workspace/coverage/default/20.uart_stress_all.915595929
Short name T456
Test name
Test status
Simulation time 156053967262 ps
CPU time 332.26 seconds
Started Jun 07 07:21:51 PM PDT 24
Finished Jun 07 07:27:36 PM PDT 24
Peak memory 200276 kb
Host smart-d3deb4e8-3c8b-40e0-b822-6c411a5435bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915595929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.915595929
Directory /workspace/20.uart_stress_all/latest

Test location /workspace/coverage/default/20.uart_tx_ovrd.1202226992
Short name T799
Test name
Test status
Simulation time 7830736159 ps
CPU time 7.34 seconds
Started Jun 07 07:21:51 PM PDT 24
Finished Jun 07 07:22:11 PM PDT 24
Peak memory 200400 kb
Host smart-24415822-efe9-4181-9b45-d150241533dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202226992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.1202226992
Directory /workspace/20.uart_tx_ovrd/latest

Test location /workspace/coverage/default/20.uart_tx_rx.3887833617
Short name T1038
Test name
Test status
Simulation time 95556004453 ps
CPU time 52.63 seconds
Started Jun 07 07:21:53 PM PDT 24
Finished Jun 07 07:22:58 PM PDT 24
Peak memory 200432 kb
Host smart-f8e0490c-2160-43dd-96ca-ae45eb8d9a69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887833617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.3887833617
Directory /workspace/20.uart_tx_rx/latest

Test location /workspace/coverage/default/200.uart_fifo_reset.3283471413
Short name T963
Test name
Test status
Simulation time 183609425473 ps
CPU time 39.41 seconds
Started Jun 07 07:27:25 PM PDT 24
Finished Jun 07 07:28:09 PM PDT 24
Peak memory 200360 kb
Host smart-b0aa8c0d-8307-4bc6-99dd-0fcfcd987024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283471413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.3283471413
Directory /workspace/200.uart_fifo_reset/latest

Test location /workspace/coverage/default/201.uart_fifo_reset.1666819045
Short name T178
Test name
Test status
Simulation time 13979189496 ps
CPU time 11.45 seconds
Started Jun 07 07:27:22 PM PDT 24
Finished Jun 07 07:27:37 PM PDT 24
Peak memory 200276 kb
Host smart-e1e84f68-0a62-4b0a-92dd-d09307ec6e82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666819045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.1666819045
Directory /workspace/201.uart_fifo_reset/latest

Test location /workspace/coverage/default/202.uart_fifo_reset.851907099
Short name T728
Test name
Test status
Simulation time 5367723153 ps
CPU time 9.32 seconds
Started Jun 07 07:27:23 PM PDT 24
Finished Jun 07 07:27:37 PM PDT 24
Peak memory 200356 kb
Host smart-ee485959-5c75-48e2-bc1b-8407198f84af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851907099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.851907099
Directory /workspace/202.uart_fifo_reset/latest

Test location /workspace/coverage/default/203.uart_fifo_reset.952171618
Short name T823
Test name
Test status
Simulation time 13618110054 ps
CPU time 28.8 seconds
Started Jun 07 07:27:24 PM PDT 24
Finished Jun 07 07:27:57 PM PDT 24
Peak memory 200388 kb
Host smart-bbe57b04-c75d-4a32-80c8-91077cd2688f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952171618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.952171618
Directory /workspace/203.uart_fifo_reset/latest

Test location /workspace/coverage/default/204.uart_fifo_reset.2780217772
Short name T165
Test name
Test status
Simulation time 149118842208 ps
CPU time 311.24 seconds
Started Jun 07 07:27:21 PM PDT 24
Finished Jun 07 07:32:35 PM PDT 24
Peak memory 200324 kb
Host smart-0b738c3e-1742-48d7-8001-35d9d83a37cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780217772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.2780217772
Directory /workspace/204.uart_fifo_reset/latest

Test location /workspace/coverage/default/205.uart_fifo_reset.681615720
Short name T216
Test name
Test status
Simulation time 85959628796 ps
CPU time 36.95 seconds
Started Jun 07 07:27:23 PM PDT 24
Finished Jun 07 07:28:05 PM PDT 24
Peak memory 200452 kb
Host smart-621bf73a-d2e1-4612-b226-0e7c880f23fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681615720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.681615720
Directory /workspace/205.uart_fifo_reset/latest

Test location /workspace/coverage/default/206.uart_fifo_reset.2286987419
Short name T615
Test name
Test status
Simulation time 110375941006 ps
CPU time 20.84 seconds
Started Jun 07 07:27:23 PM PDT 24
Finished Jun 07 07:27:47 PM PDT 24
Peak memory 200356 kb
Host smart-76cb19b8-5657-4edb-8c4f-eadaacec41b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286987419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.2286987419
Directory /workspace/206.uart_fifo_reset/latest

Test location /workspace/coverage/default/207.uart_fifo_reset.2457131011
Short name T447
Test name
Test status
Simulation time 26780948841 ps
CPU time 63.26 seconds
Started Jun 07 07:27:24 PM PDT 24
Finished Jun 07 07:28:32 PM PDT 24
Peak memory 200272 kb
Host smart-f92bd48b-7b60-4e81-9e7a-d54ae761bfbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457131011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.2457131011
Directory /workspace/207.uart_fifo_reset/latest

Test location /workspace/coverage/default/208.uart_fifo_reset.4175063355
Short name T651
Test name
Test status
Simulation time 104237595697 ps
CPU time 45.33 seconds
Started Jun 07 07:27:22 PM PDT 24
Finished Jun 07 07:28:12 PM PDT 24
Peak memory 200480 kb
Host smart-cef96989-186e-4f0d-be80-a00a021eb090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175063355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.4175063355
Directory /workspace/208.uart_fifo_reset/latest

Test location /workspace/coverage/default/209.uart_fifo_reset.4041022924
Short name T222
Test name
Test status
Simulation time 132302909759 ps
CPU time 58.38 seconds
Started Jun 07 07:27:23 PM PDT 24
Finished Jun 07 07:28:27 PM PDT 24
Peak memory 200236 kb
Host smart-b7760db0-6060-445a-8e67-835f2acce057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041022924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.4041022924
Directory /workspace/209.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_alert_test.3339128152
Short name T31
Test name
Test status
Simulation time 168763289 ps
CPU time 0.55 seconds
Started Jun 07 07:21:58 PM PDT 24
Finished Jun 07 07:22:10 PM PDT 24
Peak memory 195652 kb
Host smart-12116dc6-e06a-4dc1-a016-54f21a387e0d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339128152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.3339128152
Directory /workspace/21.uart_alert_test/latest

Test location /workspace/coverage/default/21.uart_fifo_full.3971892654
Short name T632
Test name
Test status
Simulation time 30546476653 ps
CPU time 11.47 seconds
Started Jun 07 07:22:00 PM PDT 24
Finished Jun 07 07:22:23 PM PDT 24
Peak memory 199976 kb
Host smart-4e175b36-7c48-4a91-a7a4-78aa6fd3a58b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971892654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.3971892654
Directory /workspace/21.uart_fifo_full/latest

Test location /workspace/coverage/default/21.uart_fifo_overflow.1088036053
Short name T926
Test name
Test status
Simulation time 61241631194 ps
CPU time 48.75 seconds
Started Jun 07 07:22:01 PM PDT 24
Finished Jun 07 07:23:01 PM PDT 24
Peak memory 200076 kb
Host smart-ce41632a-0def-4f26-b488-a94dd416ce40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088036053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.1088036053
Directory /workspace/21.uart_fifo_overflow/latest

Test location /workspace/coverage/default/21.uart_fifo_reset.825122017
Short name T478
Test name
Test status
Simulation time 44402351278 ps
CPU time 63.77 seconds
Started Jun 07 07:22:00 PM PDT 24
Finished Jun 07 07:23:15 PM PDT 24
Peak memory 200420 kb
Host smart-d4ad9410-96fd-4ae9-8c0b-797cb3adea5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825122017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.825122017
Directory /workspace/21.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_intr.665673873
Short name T124
Test name
Test status
Simulation time 37927747809 ps
CPU time 79.53 seconds
Started Jun 07 07:21:58 PM PDT 24
Finished Jun 07 07:23:29 PM PDT 24
Peak memory 200348 kb
Host smart-23cc424a-90e4-4645-b6d6-151dca2848ab
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665673873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.665673873
Directory /workspace/21.uart_intr/latest

Test location /workspace/coverage/default/21.uart_long_xfer_wo_dly.4120619321
Short name T633
Test name
Test status
Simulation time 203967564052 ps
CPU time 1342.85 seconds
Started Jun 07 07:22:01 PM PDT 24
Finished Jun 07 07:44:36 PM PDT 24
Peak memory 200420 kb
Host smart-8a9cf807-d697-4f6a-805b-ef46baf781bb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4120619321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.4120619321
Directory /workspace/21.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/21.uart_loopback.2731147221
Short name T427
Test name
Test status
Simulation time 12721568058 ps
CPU time 11.41 seconds
Started Jun 07 07:21:59 PM PDT 24
Finished Jun 07 07:22:22 PM PDT 24
Peak memory 200284 kb
Host smart-4f07befa-ef58-4099-91f7-212978695d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731147221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_loopback.2731147221
Directory /workspace/21.uart_loopback/latest

Test location /workspace/coverage/default/21.uart_perf.1254865864
Short name T116
Test name
Test status
Simulation time 7948217788 ps
CPU time 225.73 seconds
Started Jun 07 07:21:59 PM PDT 24
Finished Jun 07 07:25:56 PM PDT 24
Peak memory 200308 kb
Host smart-102b0747-7b18-4a0f-b14c-dcb91a48ca3b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1254865864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.1254865864
Directory /workspace/21.uart_perf/latest

Test location /workspace/coverage/default/21.uart_rx_oversample.3989663869
Short name T749
Test name
Test status
Simulation time 5712674988 ps
CPU time 30.76 seconds
Started Jun 07 07:22:00 PM PDT 24
Finished Jun 07 07:22:42 PM PDT 24
Peak memory 199724 kb
Host smart-f6ad729c-dee2-4b1b-a802-d659ee52a090
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3989663869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.3989663869
Directory /workspace/21.uart_rx_oversample/latest

Test location /workspace/coverage/default/21.uart_rx_parity_err.436689338
Short name T512
Test name
Test status
Simulation time 171040233962 ps
CPU time 142.47 seconds
Started Jun 07 07:22:07 PM PDT 24
Finished Jun 07 07:24:38 PM PDT 24
Peak memory 200440 kb
Host smart-889c9cfd-bd32-4853-89d6-8a85ae5b2601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436689338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.436689338
Directory /workspace/21.uart_rx_parity_err/latest

Test location /workspace/coverage/default/21.uart_rx_start_bit_filter.1352957901
Short name T835
Test name
Test status
Simulation time 2848068931 ps
CPU time 4.46 seconds
Started Jun 07 07:22:01 PM PDT 24
Finished Jun 07 07:22:16 PM PDT 24
Peak memory 196116 kb
Host smart-efdbcf27-6f10-4e15-a7f6-0188834c980a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352957901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.1352957901
Directory /workspace/21.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/21.uart_smoke.2850598341
Short name T1080
Test name
Test status
Simulation time 5546038265 ps
CPU time 16.4 seconds
Started Jun 07 07:21:59 PM PDT 24
Finished Jun 07 07:22:27 PM PDT 24
Peak memory 199816 kb
Host smart-398073ed-dccd-43c6-a5f2-ec5804d279a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850598341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_smoke.2850598341
Directory /workspace/21.uart_smoke/latest

Test location /workspace/coverage/default/21.uart_stress_all.4235362264
Short name T883
Test name
Test status
Simulation time 222640729609 ps
CPU time 181.92 seconds
Started Jun 07 07:22:01 PM PDT 24
Finished Jun 07 07:25:15 PM PDT 24
Peak memory 200412 kb
Host smart-4975175c-5c9c-4999-be9c-284173faea54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235362264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.4235362264
Directory /workspace/21.uart_stress_all/latest

Test location /workspace/coverage/default/21.uart_stress_all_with_rand_reset.1915779815
Short name T852
Test name
Test status
Simulation time 119284887899 ps
CPU time 1380.44 seconds
Started Jun 07 07:21:59 PM PDT 24
Finished Jun 07 07:45:11 PM PDT 24
Peak memory 216920 kb
Host smart-c370e19c-135a-4def-8a6c-b5cb66d6ac9e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915779815 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 21.uart_stress_all_with_rand_reset.1915779815
Directory /workspace/21.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.uart_tx_ovrd.2576673973
Short name T492
Test name
Test status
Simulation time 6687146859 ps
CPU time 15.79 seconds
Started Jun 07 07:21:59 PM PDT 24
Finished Jun 07 07:22:26 PM PDT 24
Peak memory 200168 kb
Host smart-c6c01446-8e05-451e-b610-135d1079d262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576673973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.2576673973
Directory /workspace/21.uart_tx_ovrd/latest

Test location /workspace/coverage/default/21.uart_tx_rx.1848913423
Short name T97
Test name
Test status
Simulation time 64689324571 ps
CPU time 54.97 seconds
Started Jun 07 07:21:59 PM PDT 24
Finished Jun 07 07:23:06 PM PDT 24
Peak memory 200368 kb
Host smart-2e6dd91d-fbee-499c-bb2d-c5228a918970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848913423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.1848913423
Directory /workspace/21.uart_tx_rx/latest

Test location /workspace/coverage/default/210.uart_fifo_reset.218408428
Short name T517
Test name
Test status
Simulation time 15361486372 ps
CPU time 24.71 seconds
Started Jun 07 07:27:23 PM PDT 24
Finished Jun 07 07:27:53 PM PDT 24
Peak memory 200180 kb
Host smart-254b6e8a-3f3c-43e9-9aa7-265cd51589c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218408428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.218408428
Directory /workspace/210.uart_fifo_reset/latest

Test location /workspace/coverage/default/211.uart_fifo_reset.491890940
Short name T203
Test name
Test status
Simulation time 38783705587 ps
CPU time 14.25 seconds
Started Jun 07 07:27:23 PM PDT 24
Finished Jun 07 07:27:42 PM PDT 24
Peak memory 200324 kb
Host smart-c7722bef-5a13-4297-a217-e87b9d76eb1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491890940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.491890940
Directory /workspace/211.uart_fifo_reset/latest

Test location /workspace/coverage/default/212.uart_fifo_reset.2123291940
Short name T154
Test name
Test status
Simulation time 65350413178 ps
CPU time 21.48 seconds
Started Jun 07 07:27:23 PM PDT 24
Finished Jun 07 07:27:50 PM PDT 24
Peak memory 200336 kb
Host smart-9390e3f0-9dad-42b2-8254-3a7cc609e232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123291940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.2123291940
Directory /workspace/212.uart_fifo_reset/latest

Test location /workspace/coverage/default/213.uart_fifo_reset.2212177428
Short name T301
Test name
Test status
Simulation time 9136542528 ps
CPU time 16.32 seconds
Started Jun 07 07:27:23 PM PDT 24
Finished Jun 07 07:27:44 PM PDT 24
Peak memory 198512 kb
Host smart-33d45718-0be5-449e-a2ad-90c37658feb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212177428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.2212177428
Directory /workspace/213.uart_fifo_reset/latest

Test location /workspace/coverage/default/214.uart_fifo_reset.1550625325
Short name T755
Test name
Test status
Simulation time 67991409696 ps
CPU time 27.77 seconds
Started Jun 07 07:27:25 PM PDT 24
Finished Jun 07 07:27:58 PM PDT 24
Peak memory 200340 kb
Host smart-92668395-fe68-45ee-b142-781f2d472dd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550625325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.1550625325
Directory /workspace/214.uart_fifo_reset/latest

Test location /workspace/coverage/default/215.uart_fifo_reset.3789731231
Short name T390
Test name
Test status
Simulation time 34411087344 ps
CPU time 19.97 seconds
Started Jun 07 07:27:28 PM PDT 24
Finished Jun 07 07:27:52 PM PDT 24
Peak memory 200368 kb
Host smart-b46d6175-3d87-441e-bce3-0070e5cc0b65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789731231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.3789731231
Directory /workspace/215.uart_fifo_reset/latest

Test location /workspace/coverage/default/216.uart_fifo_reset.3288941624
Short name T660
Test name
Test status
Simulation time 33253347256 ps
CPU time 62.39 seconds
Started Jun 07 07:27:30 PM PDT 24
Finished Jun 07 07:28:37 PM PDT 24
Peak memory 200404 kb
Host smart-203b81cb-3225-483a-8f22-80eddf4662a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288941624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.3288941624
Directory /workspace/216.uart_fifo_reset/latest

Test location /workspace/coverage/default/217.uart_fifo_reset.4112882983
Short name T699
Test name
Test status
Simulation time 22545748064 ps
CPU time 34.17 seconds
Started Jun 07 07:27:26 PM PDT 24
Finished Jun 07 07:28:05 PM PDT 24
Peak memory 200388 kb
Host smart-f24a8b52-9e13-4b98-b050-997816b01dd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112882983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.4112882983
Directory /workspace/217.uart_fifo_reset/latest

Test location /workspace/coverage/default/218.uart_fifo_reset.3035942512
Short name T224
Test name
Test status
Simulation time 19726927476 ps
CPU time 35.61 seconds
Started Jun 07 07:27:29 PM PDT 24
Finished Jun 07 07:28:09 PM PDT 24
Peak memory 200408 kb
Host smart-8b4e21e5-c8bc-4131-a21a-917653d9b188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035942512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.3035942512
Directory /workspace/218.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_alert_test.1379571824
Short name T802
Test name
Test status
Simulation time 154997005 ps
CPU time 0.55 seconds
Started Jun 07 07:22:52 PM PDT 24
Finished Jun 07 07:22:59 PM PDT 24
Peak memory 195996 kb
Host smart-17c62ab9-6d3a-48e7-8349-10a6fe58a122
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379571824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.1379571824
Directory /workspace/22.uart_alert_test/latest

Test location /workspace/coverage/default/22.uart_fifo_full.4287282192
Short name T824
Test name
Test status
Simulation time 41864158026 ps
CPU time 75.02 seconds
Started Jun 07 07:22:50 PM PDT 24
Finished Jun 07 07:24:12 PM PDT 24
Peak memory 200492 kb
Host smart-033f1454-5c70-4764-97ad-7f2260a8271f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287282192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.4287282192
Directory /workspace/22.uart_fifo_full/latest

Test location /workspace/coverage/default/22.uart_fifo_overflow.3201894417
Short name T1026
Test name
Test status
Simulation time 4728769297 ps
CPU time 8.43 seconds
Started Jun 07 07:22:49 PM PDT 24
Finished Jun 07 07:23:03 PM PDT 24
Peak memory 199496 kb
Host smart-0b23dc06-50d7-4bb3-83ab-dcdbc30173cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201894417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.3201894417
Directory /workspace/22.uart_fifo_overflow/latest

Test location /workspace/coverage/default/22.uart_intr.1566746844
Short name T18
Test name
Test status
Simulation time 8950486475 ps
CPU time 4.97 seconds
Started Jun 07 07:22:44 PM PDT 24
Finished Jun 07 07:22:52 PM PDT 24
Peak memory 199820 kb
Host smart-cf280cbf-27eb-421c-9a7e-1c9e70f5ee8e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566746844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.1566746844
Directory /workspace/22.uart_intr/latest

Test location /workspace/coverage/default/22.uart_long_xfer_wo_dly.4262969145
Short name T777
Test name
Test status
Simulation time 73416691280 ps
CPU time 370.88 seconds
Started Jun 07 07:22:52 PM PDT 24
Finished Jun 07 07:29:10 PM PDT 24
Peak memory 200288 kb
Host smart-ea137512-dd23-43d8-8629-981c22c62c00
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4262969145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.4262969145
Directory /workspace/22.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/22.uart_loopback.1051419087
Short name T525
Test name
Test status
Simulation time 8478105628 ps
CPU time 7.61 seconds
Started Jun 07 07:22:51 PM PDT 24
Finished Jun 07 07:23:05 PM PDT 24
Peak memory 199208 kb
Host smart-393f42fa-03da-42b3-9439-1c97e0424679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051419087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_loopback.1051419087
Directory /workspace/22.uart_loopback/latest

Test location /workspace/coverage/default/22.uart_perf.2020595983
Short name T503
Test name
Test status
Simulation time 3362458873 ps
CPU time 59.14 seconds
Started Jun 07 07:22:49 PM PDT 24
Finished Jun 07 07:23:54 PM PDT 24
Peak memory 200296 kb
Host smart-155721a2-acbc-4e75-8a38-d2ad7d4f9335
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2020595983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.2020595983
Directory /workspace/22.uart_perf/latest

Test location /workspace/coverage/default/22.uart_rx_oversample.3712940673
Short name T405
Test name
Test status
Simulation time 6452937177 ps
CPU time 58.5 seconds
Started Jun 07 07:22:48 PM PDT 24
Finished Jun 07 07:23:52 PM PDT 24
Peak memory 198508 kb
Host smart-35d16783-1554-4ffc-9875-1e6f36721940
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3712940673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.3712940673
Directory /workspace/22.uart_rx_oversample/latest

Test location /workspace/coverage/default/22.uart_rx_parity_err.2730315426
Short name T328
Test name
Test status
Simulation time 193099062060 ps
CPU time 20.76 seconds
Started Jun 07 07:22:51 PM PDT 24
Finished Jun 07 07:23:19 PM PDT 24
Peak memory 200340 kb
Host smart-70d540aa-77b3-4229-b19d-dcb91f1c2ab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730315426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.2730315426
Directory /workspace/22.uart_rx_parity_err/latest

Test location /workspace/coverage/default/22.uart_rx_start_bit_filter.1652670952
Short name T738
Test name
Test status
Simulation time 4968647035 ps
CPU time 5.08 seconds
Started Jun 07 07:22:50 PM PDT 24
Finished Jun 07 07:23:01 PM PDT 24
Peak memory 196444 kb
Host smart-7897714e-86bf-4e3f-a9fa-3c214abb6a06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652670952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.1652670952
Directory /workspace/22.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/22.uart_smoke.3763701659
Short name T388
Test name
Test status
Simulation time 898980303 ps
CPU time 2.43 seconds
Started Jun 07 07:22:07 PM PDT 24
Finished Jun 07 07:22:18 PM PDT 24
Peak memory 199280 kb
Host smart-5a7cfcb2-77bd-414a-a56a-1c32d48c6120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763701659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_smoke.3763701659
Directory /workspace/22.uart_smoke/latest

Test location /workspace/coverage/default/22.uart_stress_all.3149414135
Short name T746
Test name
Test status
Simulation time 11368693790 ps
CPU time 10.21 seconds
Started Jun 07 07:22:54 PM PDT 24
Finished Jun 07 07:23:12 PM PDT 24
Peak memory 200352 kb
Host smart-4e558041-a90e-46de-adbb-58eb63387759
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149414135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.3149414135
Directory /workspace/22.uart_stress_all/latest

Test location /workspace/coverage/default/22.uart_tx_ovrd.1563694420
Short name T71
Test name
Test status
Simulation time 911509409 ps
CPU time 2.47 seconds
Started Jun 07 07:22:48 PM PDT 24
Finished Jun 07 07:22:56 PM PDT 24
Peak memory 199000 kb
Host smart-88366af8-8266-4c35-a53e-bb0aa90afa29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563694420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.1563694420
Directory /workspace/22.uart_tx_ovrd/latest

Test location /workspace/coverage/default/22.uart_tx_rx.4151600317
Short name T474
Test name
Test status
Simulation time 37266461380 ps
CPU time 24.87 seconds
Started Jun 07 07:21:59 PM PDT 24
Finished Jun 07 07:22:35 PM PDT 24
Peak memory 200472 kb
Host smart-9716df8e-6908-4529-8e2b-cd44161f61af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151600317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.4151600317
Directory /workspace/22.uart_tx_rx/latest

Test location /workspace/coverage/default/220.uart_fifo_reset.863173026
Short name T1027
Test name
Test status
Simulation time 60392925350 ps
CPU time 96.57 seconds
Started Jun 07 07:27:28 PM PDT 24
Finished Jun 07 07:29:08 PM PDT 24
Peak memory 200396 kb
Host smart-9aef1fa8-2440-46c9-b4e4-f837049aa05f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863173026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.863173026
Directory /workspace/220.uart_fifo_reset/latest

Test location /workspace/coverage/default/221.uart_fifo_reset.992986966
Short name T245
Test name
Test status
Simulation time 123278631008 ps
CPU time 35.43 seconds
Started Jun 07 07:27:28 PM PDT 24
Finished Jun 07 07:28:08 PM PDT 24
Peak memory 200360 kb
Host smart-1846ba77-b94d-4fc7-b264-bc908538efd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992986966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.992986966
Directory /workspace/221.uart_fifo_reset/latest

Test location /workspace/coverage/default/222.uart_fifo_reset.832965637
Short name T220
Test name
Test status
Simulation time 82316967565 ps
CPU time 46.91 seconds
Started Jun 07 07:27:27 PM PDT 24
Finished Jun 07 07:28:18 PM PDT 24
Peak memory 200460 kb
Host smart-54f9f82f-5e62-4673-ad0f-59675f700a10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832965637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.832965637
Directory /workspace/222.uart_fifo_reset/latest

Test location /workspace/coverage/default/223.uart_fifo_reset.1506011068
Short name T720
Test name
Test status
Simulation time 155632207844 ps
CPU time 56.17 seconds
Started Jun 07 07:27:30 PM PDT 24
Finished Jun 07 07:28:31 PM PDT 24
Peak memory 200340 kb
Host smart-af7c55ee-fa05-48a7-8ff3-0a8f9a9d7851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506011068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.1506011068
Directory /workspace/223.uart_fifo_reset/latest

Test location /workspace/coverage/default/224.uart_fifo_reset.4025274540
Short name T553
Test name
Test status
Simulation time 39527096468 ps
CPU time 59.27 seconds
Started Jun 07 07:27:25 PM PDT 24
Finished Jun 07 07:28:29 PM PDT 24
Peak memory 200232 kb
Host smart-c218d156-7161-4db2-9f16-ecaa2532b168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025274540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.4025274540
Directory /workspace/224.uart_fifo_reset/latest

Test location /workspace/coverage/default/225.uart_fifo_reset.2047764387
Short name T523
Test name
Test status
Simulation time 40712415347 ps
CPU time 31.91 seconds
Started Jun 07 07:27:30 PM PDT 24
Finished Jun 07 07:28:06 PM PDT 24
Peak memory 200404 kb
Host smart-99ba013e-2cf3-4e32-bbbf-2fc24f130824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047764387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.2047764387
Directory /workspace/225.uart_fifo_reset/latest

Test location /workspace/coverage/default/226.uart_fifo_reset.2568906098
Short name T654
Test name
Test status
Simulation time 48756292260 ps
CPU time 20.22 seconds
Started Jun 07 07:27:28 PM PDT 24
Finished Jun 07 07:27:52 PM PDT 24
Peak memory 200396 kb
Host smart-d3856647-3f75-4dda-aa26-c9d18c9b9082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568906098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.2568906098
Directory /workspace/226.uart_fifo_reset/latest

Test location /workspace/coverage/default/227.uart_fifo_reset.3153511575
Short name T431
Test name
Test status
Simulation time 44074525179 ps
CPU time 12.25 seconds
Started Jun 07 07:27:29 PM PDT 24
Finished Jun 07 07:27:46 PM PDT 24
Peak memory 200388 kb
Host smart-68e2734d-f783-4abb-81a0-8cc8b418630d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153511575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.3153511575
Directory /workspace/227.uart_fifo_reset/latest

Test location /workspace/coverage/default/228.uart_fifo_reset.3484645370
Short name T890
Test name
Test status
Simulation time 63913746697 ps
CPU time 104.41 seconds
Started Jun 07 07:27:25 PM PDT 24
Finished Jun 07 07:29:14 PM PDT 24
Peak memory 200416 kb
Host smart-000ba3d5-d87f-4067-8305-62c67261605f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484645370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.3484645370
Directory /workspace/228.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_alert_test.507036156
Short name T734
Test name
Test status
Simulation time 21357542 ps
CPU time 0.55 seconds
Started Jun 07 07:22:49 PM PDT 24
Finished Jun 07 07:22:55 PM PDT 24
Peak memory 196056 kb
Host smart-d164a349-1a3f-4b22-aa97-38a94016603f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507036156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.507036156
Directory /workspace/23.uart_alert_test/latest

Test location /workspace/coverage/default/23.uart_fifo_full.3030663909
Short name T282
Test name
Test status
Simulation time 40673691018 ps
CPU time 74.44 seconds
Started Jun 07 07:22:53 PM PDT 24
Finished Jun 07 07:24:15 PM PDT 24
Peak memory 200332 kb
Host smart-d4902075-bbe8-4da9-8b47-7c06b0f65951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030663909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.3030663909
Directory /workspace/23.uart_fifo_full/latest

Test location /workspace/coverage/default/23.uart_fifo_overflow.1672265979
Short name T760
Test name
Test status
Simulation time 65221867719 ps
CPU time 18.95 seconds
Started Jun 07 07:22:54 PM PDT 24
Finished Jun 07 07:23:21 PM PDT 24
Peak memory 200404 kb
Host smart-6a1a26b3-2be7-4b98-9cef-f45ccc320357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672265979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.1672265979
Directory /workspace/23.uart_fifo_overflow/latest

Test location /workspace/coverage/default/23.uart_fifo_reset.3385589935
Short name T331
Test name
Test status
Simulation time 150944726317 ps
CPU time 135.5 seconds
Started Jun 07 07:22:52 PM PDT 24
Finished Jun 07 07:25:15 PM PDT 24
Peak memory 200396 kb
Host smart-10f9bd71-b2ae-47ab-85c8-810d44192243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385589935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.3385589935
Directory /workspace/23.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_intr.134296487
Short name T1008
Test name
Test status
Simulation time 63024841198 ps
CPU time 16.55 seconds
Started Jun 07 07:22:55 PM PDT 24
Finished Jun 07 07:23:21 PM PDT 24
Peak memory 200400 kb
Host smart-6ba95027-b319-4fbf-ae77-f773b5520380
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134296487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.134296487
Directory /workspace/23.uart_intr/latest

Test location /workspace/coverage/default/23.uart_long_xfer_wo_dly.1740661503
Short name T741
Test name
Test status
Simulation time 195912691049 ps
CPU time 772.24 seconds
Started Jun 07 07:22:48 PM PDT 24
Finished Jun 07 07:35:46 PM PDT 24
Peak memory 200384 kb
Host smart-75215079-be11-4344-8726-8916189965b4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1740661503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.1740661503
Directory /workspace/23.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/23.uart_loopback.1253653887
Short name T567
Test name
Test status
Simulation time 35650368 ps
CPU time 0.58 seconds
Started Jun 07 07:22:49 PM PDT 24
Finished Jun 07 07:22:55 PM PDT 24
Peak memory 196048 kb
Host smart-e2938367-6ecd-4a7b-8772-81505483c993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253653887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_loopback.1253653887
Directory /workspace/23.uart_loopback/latest

Test location /workspace/coverage/default/23.uart_perf.116739072
Short name T325
Test name
Test status
Simulation time 14230485319 ps
CPU time 193.35 seconds
Started Jun 07 07:22:51 PM PDT 24
Finished Jun 07 07:26:11 PM PDT 24
Peak memory 200332 kb
Host smart-222b3341-3e11-43f7-9ba7-d65d105c3bb1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=116739072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.116739072
Directory /workspace/23.uart_perf/latest

Test location /workspace/coverage/default/23.uart_rx_oversample.3686429850
Short name T367
Test name
Test status
Simulation time 5168383519 ps
CPU time 42.46 seconds
Started Jun 07 07:22:53 PM PDT 24
Finished Jun 07 07:23:42 PM PDT 24
Peak memory 199620 kb
Host smart-7ce328e7-b3f5-4de1-b7d5-c202bee6f398
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3686429850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.3686429850
Directory /workspace/23.uart_rx_oversample/latest

Test location /workspace/coverage/default/23.uart_rx_parity_err.3604515967
Short name T2
Test name
Test status
Simulation time 130371709575 ps
CPU time 103.75 seconds
Started Jun 07 07:22:53 PM PDT 24
Finished Jun 07 07:24:45 PM PDT 24
Peak memory 200212 kb
Host smart-cc28515e-81b5-4c8e-831f-a69099799f63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604515967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.3604515967
Directory /workspace/23.uart_rx_parity_err/latest

Test location /workspace/coverage/default/23.uart_rx_start_bit_filter.2745231791
Short name T401
Test name
Test status
Simulation time 3014886521 ps
CPU time 1.27 seconds
Started Jun 07 07:22:54 PM PDT 24
Finished Jun 07 07:23:03 PM PDT 24
Peak memory 196196 kb
Host smart-b419eca5-20d0-4d39-814b-305895e2155e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745231791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.2745231791
Directory /workspace/23.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/23.uart_smoke.653752945
Short name T688
Test name
Test status
Simulation time 504120108 ps
CPU time 2.08 seconds
Started Jun 07 07:22:52 PM PDT 24
Finished Jun 07 07:23:01 PM PDT 24
Peak memory 198696 kb
Host smart-64e125af-651f-4bd5-a19f-700d9f830339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653752945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_smoke.653752945
Directory /workspace/23.uart_smoke/latest

Test location /workspace/coverage/default/23.uart_stress_all.1473046224
Short name T643
Test name
Test status
Simulation time 157388992163 ps
CPU time 185.29 seconds
Started Jun 07 07:22:50 PM PDT 24
Finished Jun 07 07:26:01 PM PDT 24
Peak memory 200356 kb
Host smart-fdd053ea-1906-48b0-8d03-731f7f4a637d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473046224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.1473046224
Directory /workspace/23.uart_stress_all/latest

Test location /workspace/coverage/default/23.uart_tx_ovrd.4293440770
Short name T1011
Test name
Test status
Simulation time 1444264013 ps
CPU time 2.04 seconds
Started Jun 07 07:22:56 PM PDT 24
Finished Jun 07 07:23:07 PM PDT 24
Peak memory 199476 kb
Host smart-580ddad4-bd97-48d9-8538-e5c8d16b9621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293440770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.4293440770
Directory /workspace/23.uart_tx_ovrd/latest

Test location /workspace/coverage/default/23.uart_tx_rx.4153839747
Short name T614
Test name
Test status
Simulation time 33966775000 ps
CPU time 50.58 seconds
Started Jun 07 07:22:50 PM PDT 24
Finished Jun 07 07:23:47 PM PDT 24
Peak memory 200356 kb
Host smart-9e407466-5d11-4d37-8ced-8acfeeea200a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153839747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.4153839747
Directory /workspace/23.uart_tx_rx/latest

Test location /workspace/coverage/default/231.uart_fifo_reset.4179174143
Short name T151
Test name
Test status
Simulation time 120528698849 ps
CPU time 42.17 seconds
Started Jun 07 07:27:30 PM PDT 24
Finished Jun 07 07:28:17 PM PDT 24
Peak memory 199992 kb
Host smart-c2bfe29e-8f8e-4a0a-aaf4-d6e5134e10ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179174143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.4179174143
Directory /workspace/231.uart_fifo_reset/latest

Test location /workspace/coverage/default/232.uart_fifo_reset.3215652825
Short name T146
Test name
Test status
Simulation time 64065043650 ps
CPU time 49.58 seconds
Started Jun 07 07:27:41 PM PDT 24
Finished Jun 07 07:28:35 PM PDT 24
Peak memory 200392 kb
Host smart-936a3452-d897-402f-9ddf-739819ec6170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215652825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.3215652825
Directory /workspace/232.uart_fifo_reset/latest

Test location /workspace/coverage/default/234.uart_fifo_reset.2908489551
Short name T210
Test name
Test status
Simulation time 33198762827 ps
CPU time 26.6 seconds
Started Jun 07 07:27:41 PM PDT 24
Finished Jun 07 07:28:12 PM PDT 24
Peak memory 200364 kb
Host smart-cd2fb443-ddb9-4e90-9af9-efdf58bf2663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908489551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.2908489551
Directory /workspace/234.uart_fifo_reset/latest

Test location /workspace/coverage/default/235.uart_fifo_reset.3491792562
Short name T258
Test name
Test status
Simulation time 16367491250 ps
CPU time 29.05 seconds
Started Jun 07 07:27:40 PM PDT 24
Finished Jun 07 07:28:13 PM PDT 24
Peak memory 200336 kb
Host smart-3c277e9f-f4e4-47b7-9ea1-a0e414aeb710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491792562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.3491792562
Directory /workspace/235.uart_fifo_reset/latest

Test location /workspace/coverage/default/236.uart_fifo_reset.1744598388
Short name T839
Test name
Test status
Simulation time 241327575833 ps
CPU time 413.59 seconds
Started Jun 07 07:27:41 PM PDT 24
Finished Jun 07 07:34:40 PM PDT 24
Peak memory 200312 kb
Host smart-3ce74fc8-b4df-4d12-92a3-ab623f94cc2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744598388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.1744598388
Directory /workspace/236.uart_fifo_reset/latest

Test location /workspace/coverage/default/237.uart_fifo_reset.854119174
Short name T1074
Test name
Test status
Simulation time 18134565074 ps
CPU time 42.24 seconds
Started Jun 07 07:27:40 PM PDT 24
Finished Jun 07 07:28:26 PM PDT 24
Peak memory 200368 kb
Host smart-c57ecbf9-f518-4ccd-b196-0daa01d29294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854119174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.854119174
Directory /workspace/237.uart_fifo_reset/latest

Test location /workspace/coverage/default/238.uart_fifo_reset.423903756
Short name T961
Test name
Test status
Simulation time 20144907140 ps
CPU time 33.82 seconds
Started Jun 07 07:27:40 PM PDT 24
Finished Jun 07 07:28:18 PM PDT 24
Peak memory 200360 kb
Host smart-3ebbb493-21a6-41c0-91fb-e4e5f35daca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423903756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.423903756
Directory /workspace/238.uart_fifo_reset/latest

Test location /workspace/coverage/default/239.uart_fifo_reset.4138534806
Short name T489
Test name
Test status
Simulation time 35789867757 ps
CPU time 49.31 seconds
Started Jun 07 07:27:43 PM PDT 24
Finished Jun 07 07:28:37 PM PDT 24
Peak memory 200288 kb
Host smart-daa3d07a-a6da-4688-8cb7-95d474a39ef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138534806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.4138534806
Directory /workspace/239.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_alert_test.2106339463
Short name T727
Test name
Test status
Simulation time 11985600 ps
CPU time 0.57 seconds
Started Jun 07 07:22:53 PM PDT 24
Finished Jun 07 07:23:01 PM PDT 24
Peak memory 195764 kb
Host smart-a0cdf711-fc0a-4499-8db4-b4773d3907c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106339463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.2106339463
Directory /workspace/24.uart_alert_test/latest

Test location /workspace/coverage/default/24.uart_fifo_full.3505352359
Short name T160
Test name
Test status
Simulation time 52637227957 ps
CPU time 33.29 seconds
Started Jun 07 07:22:52 PM PDT 24
Finished Jun 07 07:23:33 PM PDT 24
Peak memory 200292 kb
Host smart-10aea74e-5ada-452f-ba4f-1893a4ddb922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505352359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.3505352359
Directory /workspace/24.uart_fifo_full/latest

Test location /workspace/coverage/default/24.uart_fifo_overflow.1071944697
Short name T192
Test name
Test status
Simulation time 146094498233 ps
CPU time 112.5 seconds
Started Jun 07 07:22:50 PM PDT 24
Finished Jun 07 07:24:49 PM PDT 24
Peak memory 200432 kb
Host smart-0469fe61-b541-46cb-8d1f-991ee0129e59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071944697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.1071944697
Directory /workspace/24.uart_fifo_overflow/latest

Test location /workspace/coverage/default/24.uart_fifo_reset.586513692
Short name T989
Test name
Test status
Simulation time 58415465530 ps
CPU time 48.22 seconds
Started Jun 07 07:22:51 PM PDT 24
Finished Jun 07 07:23:46 PM PDT 24
Peak memory 200432 kb
Host smart-7cc6e922-6b86-405d-9c5f-1458d72b76aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586513692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.586513692
Directory /workspace/24.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_intr.251966092
Short name T416
Test name
Test status
Simulation time 15355705507 ps
CPU time 25.38 seconds
Started Jun 07 07:22:52 PM PDT 24
Finished Jun 07 07:23:24 PM PDT 24
Peak memory 200292 kb
Host smart-ed595ac8-6e06-49d5-967b-ee3965a6dfc9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251966092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.251966092
Directory /workspace/24.uart_intr/latest

Test location /workspace/coverage/default/24.uart_long_xfer_wo_dly.1399765334
Short name T665
Test name
Test status
Simulation time 70457724259 ps
CPU time 607.98 seconds
Started Jun 07 07:22:52 PM PDT 24
Finished Jun 07 07:33:08 PM PDT 24
Peak memory 200336 kb
Host smart-c88eaa4c-19f1-4e86-84db-093717bc79b0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1399765334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.1399765334
Directory /workspace/24.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/24.uart_loopback.2782321228
Short name T75
Test name
Test status
Simulation time 10476738376 ps
CPU time 10.49 seconds
Started Jun 07 07:22:54 PM PDT 24
Finished Jun 07 07:23:13 PM PDT 24
Peak memory 198528 kb
Host smart-16cd8af0-effa-49f3-9adf-e5d65309d922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782321228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_loopback.2782321228
Directory /workspace/24.uart_loopback/latest

Test location /workspace/coverage/default/24.uart_perf.4180706055
Short name T1019
Test name
Test status
Simulation time 8066874995 ps
CPU time 219.52 seconds
Started Jun 07 07:22:39 PM PDT 24
Finished Jun 07 07:26:20 PM PDT 24
Peak memory 200380 kb
Host smart-5f9be00b-e145-43eb-8ff0-74944a91f0f4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4180706055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.4180706055
Directory /workspace/24.uart_perf/latest

Test location /workspace/coverage/default/24.uart_rx_oversample.51547784
Short name T364
Test name
Test status
Simulation time 4925377060 ps
CPU time 12.11 seconds
Started Jun 07 07:22:49 PM PDT 24
Finished Jun 07 07:23:06 PM PDT 24
Peak memory 198444 kb
Host smart-f412dfeb-99a1-44e8-8d95-481be278f100
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=51547784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.51547784
Directory /workspace/24.uart_rx_oversample/latest

Test location /workspace/coverage/default/24.uart_rx_parity_err.860073871
Short name T272
Test name
Test status
Simulation time 116198308679 ps
CPU time 58.87 seconds
Started Jun 07 07:22:53 PM PDT 24
Finished Jun 07 07:24:00 PM PDT 24
Peak memory 200312 kb
Host smart-106f6767-9b00-4778-a231-c664d30181e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860073871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.860073871
Directory /workspace/24.uart_rx_parity_err/latest

Test location /workspace/coverage/default/24.uart_rx_start_bit_filter.2101397214
Short name T861
Test name
Test status
Simulation time 2648786419 ps
CPU time 1.45 seconds
Started Jun 07 07:22:52 PM PDT 24
Finished Jun 07 07:23:01 PM PDT 24
Peak memory 196272 kb
Host smart-0b2953ea-7690-4456-b3f0-a10dcaff96eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101397214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.2101397214
Directory /workspace/24.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/24.uart_smoke.3701432479
Short name T1053
Test name
Test status
Simulation time 438624520 ps
CPU time 1.88 seconds
Started Jun 07 07:22:48 PM PDT 24
Finished Jun 07 07:22:55 PM PDT 24
Peak memory 199792 kb
Host smart-f523a1cb-afb4-4ba1-9881-9c327e3a3df1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701432479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_smoke.3701432479
Directory /workspace/24.uart_smoke/latest

Test location /workspace/coverage/default/24.uart_stress_all_with_rand_reset.667741681
Short name T750
Test name
Test status
Simulation time 38789695607 ps
CPU time 407.66 seconds
Started Jun 07 07:22:42 PM PDT 24
Finished Jun 07 07:29:33 PM PDT 24
Peak memory 208756 kb
Host smart-21e37ff7-2ac4-49d1-8cd9-31daa3c2a807
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667741681 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 24.uart_stress_all_with_rand_reset.667741681
Directory /workspace/24.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.uart_tx_ovrd.640840221
Short name T396
Test name
Test status
Simulation time 679227207 ps
CPU time 2.56 seconds
Started Jun 07 07:22:52 PM PDT 24
Finished Jun 07 07:23:02 PM PDT 24
Peak memory 199284 kb
Host smart-fc5785dd-e5cf-451a-b95b-dfe54b4b700d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640840221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.640840221
Directory /workspace/24.uart_tx_ovrd/latest

Test location /workspace/coverage/default/24.uart_tx_rx.109457294
Short name T446
Test name
Test status
Simulation time 25006999629 ps
CPU time 46.16 seconds
Started Jun 07 07:22:51 PM PDT 24
Finished Jun 07 07:23:43 PM PDT 24
Peak memory 200412 kb
Host smart-9ebc8da1-639f-413f-bebf-e9bf26d5b7a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109457294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.109457294
Directory /workspace/24.uart_tx_rx/latest

Test location /workspace/coverage/default/240.uart_fifo_reset.3789866654
Short name T568
Test name
Test status
Simulation time 32115609032 ps
CPU time 7.16 seconds
Started Jun 07 07:27:39 PM PDT 24
Finished Jun 07 07:27:51 PM PDT 24
Peak memory 200044 kb
Host smart-720a9f4f-e5fc-412c-b64b-d593b3ef932b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789866654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.3789866654
Directory /workspace/240.uart_fifo_reset/latest

Test location /workspace/coverage/default/241.uart_fifo_reset.1167499656
Short name T711
Test name
Test status
Simulation time 15328341315 ps
CPU time 23.03 seconds
Started Jun 07 07:27:39 PM PDT 24
Finished Jun 07 07:28:06 PM PDT 24
Peak memory 200216 kb
Host smart-f831bae5-bd35-4f8a-8650-f1cbdd51c47c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167499656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.1167499656
Directory /workspace/241.uart_fifo_reset/latest

Test location /workspace/coverage/default/242.uart_fifo_reset.3098319141
Short name T941
Test name
Test status
Simulation time 27321138549 ps
CPU time 22.29 seconds
Started Jun 07 07:27:42 PM PDT 24
Finished Jun 07 07:28:09 PM PDT 24
Peak memory 200392 kb
Host smart-fff795d0-c36f-4169-9d03-4f449fb710f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098319141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.3098319141
Directory /workspace/242.uart_fifo_reset/latest

Test location /workspace/coverage/default/243.uart_fifo_reset.2452955681
Short name T297
Test name
Test status
Simulation time 81355373669 ps
CPU time 130.41 seconds
Started Jun 07 07:27:41 PM PDT 24
Finished Jun 07 07:29:57 PM PDT 24
Peak memory 200344 kb
Host smart-68378058-2646-4fc6-81aa-75e08158e2d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452955681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.2452955681
Directory /workspace/243.uart_fifo_reset/latest

Test location /workspace/coverage/default/244.uart_fifo_reset.2173385823
Short name T228
Test name
Test status
Simulation time 79802635068 ps
CPU time 66.18 seconds
Started Jun 07 07:27:41 PM PDT 24
Finished Jun 07 07:28:52 PM PDT 24
Peak memory 200332 kb
Host smart-ffb110cb-3b4f-48cb-9b34-5f3752dd61a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173385823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.2173385823
Directory /workspace/244.uart_fifo_reset/latest

Test location /workspace/coverage/default/245.uart_fifo_reset.2987861884
Short name T899
Test name
Test status
Simulation time 291891206401 ps
CPU time 58.4 seconds
Started Jun 07 07:27:39 PM PDT 24
Finished Jun 07 07:28:42 PM PDT 24
Peak memory 200304 kb
Host smart-9c5dd04f-7d22-4e64-9def-5f7811b7ce81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987861884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.2987861884
Directory /workspace/245.uart_fifo_reset/latest

Test location /workspace/coverage/default/246.uart_fifo_reset.3675844269
Short name T235
Test name
Test status
Simulation time 48077447205 ps
CPU time 13.48 seconds
Started Jun 07 07:27:40 PM PDT 24
Finished Jun 07 07:27:58 PM PDT 24
Peak memory 200388 kb
Host smart-40471d19-ccf1-4149-9ff4-c7bf3de6fca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675844269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.3675844269
Directory /workspace/246.uart_fifo_reset/latest

Test location /workspace/coverage/default/247.uart_fifo_reset.2135137787
Short name T597
Test name
Test status
Simulation time 66428976640 ps
CPU time 18.94 seconds
Started Jun 07 07:27:39 PM PDT 24
Finished Jun 07 07:28:03 PM PDT 24
Peak memory 200404 kb
Host smart-65dfd13e-4848-47ac-802e-507174a91510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135137787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.2135137787
Directory /workspace/247.uart_fifo_reset/latest

Test location /workspace/coverage/default/248.uart_fifo_reset.2249414398
Short name T717
Test name
Test status
Simulation time 59688293062 ps
CPU time 23.85 seconds
Started Jun 07 07:27:38 PM PDT 24
Finished Jun 07 07:28:06 PM PDT 24
Peak memory 200280 kb
Host smart-8095288e-34a1-431f-a836-f29816fe07f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249414398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.2249414398
Directory /workspace/248.uart_fifo_reset/latest

Test location /workspace/coverage/default/249.uart_fifo_reset.2488154327
Short name T437
Test name
Test status
Simulation time 195684670896 ps
CPU time 78.58 seconds
Started Jun 07 07:27:39 PM PDT 24
Finished Jun 07 07:29:02 PM PDT 24
Peak memory 200300 kb
Host smart-13be46b6-0a2a-45dd-ac77-17001c049f44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488154327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.2488154327
Directory /workspace/249.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_alert_test.1501924094
Short name T585
Test name
Test status
Simulation time 146928139 ps
CPU time 0.54 seconds
Started Jun 07 07:22:49 PM PDT 24
Finished Jun 07 07:22:56 PM PDT 24
Peak memory 194704 kb
Host smart-963a6bab-1fa7-4ce5-9682-3701939e9700
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501924094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.1501924094
Directory /workspace/25.uart_alert_test/latest

Test location /workspace/coverage/default/25.uart_fifo_full.3870902307
Short name T342
Test name
Test status
Simulation time 22424291652 ps
CPU time 35.09 seconds
Started Jun 07 07:22:53 PM PDT 24
Finished Jun 07 07:23:35 PM PDT 24
Peak memory 200432 kb
Host smart-a9bf63d6-8567-440e-be7d-880dc4983139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870902307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.3870902307
Directory /workspace/25.uart_fifo_full/latest

Test location /workspace/coverage/default/25.uart_fifo_overflow.2212165347
Short name T1018
Test name
Test status
Simulation time 150978361060 ps
CPU time 171.66 seconds
Started Jun 07 07:22:48 PM PDT 24
Finished Jun 07 07:25:44 PM PDT 24
Peak memory 200372 kb
Host smart-33b8d702-bf07-4481-81b8-6feedb794ddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212165347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.2212165347
Directory /workspace/25.uart_fifo_overflow/latest

Test location /workspace/coverage/default/25.uart_fifo_reset.1642502008
Short name T765
Test name
Test status
Simulation time 114502468798 ps
CPU time 48.52 seconds
Started Jun 07 07:22:54 PM PDT 24
Finished Jun 07 07:23:50 PM PDT 24
Peak memory 200380 kb
Host smart-257a4ce0-cb96-409e-b894-bf4a350a7459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642502008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.1642502008
Directory /workspace/25.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_intr.3300713452
Short name T506
Test name
Test status
Simulation time 46982643603 ps
CPU time 19.26 seconds
Started Jun 07 07:22:55 PM PDT 24
Finished Jun 07 07:23:23 PM PDT 24
Peak memory 200376 kb
Host smart-980837bc-3d4f-40c2-9667-43fef075b6da
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300713452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.3300713452
Directory /workspace/25.uart_intr/latest

Test location /workspace/coverage/default/25.uart_long_xfer_wo_dly.867132151
Short name T725
Test name
Test status
Simulation time 198324135194 ps
CPU time 216.75 seconds
Started Jun 07 07:22:50 PM PDT 24
Finished Jun 07 07:26:33 PM PDT 24
Peak memory 200328 kb
Host smart-d8609961-aeff-4120-a4d7-6e457f16891e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=867132151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.867132151
Directory /workspace/25.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/25.uart_loopback.3054995309
Short name T1057
Test name
Test status
Simulation time 2532927973 ps
CPU time 6.81 seconds
Started Jun 07 07:22:50 PM PDT 24
Finished Jun 07 07:23:03 PM PDT 24
Peak memory 199560 kb
Host smart-36b1a17b-3f7a-440a-96bb-8aedc3e8ad3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054995309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_loopback.3054995309
Directory /workspace/25.uart_loopback/latest

Test location /workspace/coverage/default/25.uart_perf.2765463723
Short name T112
Test name
Test status
Simulation time 16420720613 ps
CPU time 863.96 seconds
Started Jun 07 07:22:51 PM PDT 24
Finished Jun 07 07:37:21 PM PDT 24
Peak memory 200400 kb
Host smart-df376fa2-9a14-41d2-8427-e6e6303b75ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2765463723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.2765463723
Directory /workspace/25.uart_perf/latest

Test location /workspace/coverage/default/25.uart_rx_oversample.3735996123
Short name T359
Test name
Test status
Simulation time 3455854534 ps
CPU time 25.86 seconds
Started Jun 07 07:22:53 PM PDT 24
Finished Jun 07 07:23:27 PM PDT 24
Peak memory 198416 kb
Host smart-d7713b3a-2bde-43e6-8823-a10e50fbca5e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3735996123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.3735996123
Directory /workspace/25.uart_rx_oversample/latest

Test location /workspace/coverage/default/25.uart_rx_parity_err.1196872267
Short name T573
Test name
Test status
Simulation time 143426484887 ps
CPU time 232.56 seconds
Started Jun 07 07:22:50 PM PDT 24
Finished Jun 07 07:26:49 PM PDT 24
Peak memory 200416 kb
Host smart-d91852b8-358f-4c8b-a78c-572b8dd233b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196872267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.1196872267
Directory /workspace/25.uart_rx_parity_err/latest

Test location /workspace/coverage/default/25.uart_rx_start_bit_filter.4287494921
Short name T894
Test name
Test status
Simulation time 837703684 ps
CPU time 1.03 seconds
Started Jun 07 07:22:53 PM PDT 24
Finished Jun 07 07:23:01 PM PDT 24
Peak memory 195804 kb
Host smart-762fc5ed-2932-423d-a5a4-f6c833df657f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287494921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.4287494921
Directory /workspace/25.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/25.uart_smoke.180031192
Short name T333
Test name
Test status
Simulation time 5372068321 ps
CPU time 23.71 seconds
Started Jun 07 07:22:53 PM PDT 24
Finished Jun 07 07:23:24 PM PDT 24
Peak memory 199636 kb
Host smart-b0f9202b-48fe-4ab9-8fbf-206f08bd187b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180031192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_smoke.180031192
Directory /workspace/25.uart_smoke/latest

Test location /workspace/coverage/default/25.uart_stress_all.331290731
Short name T682
Test name
Test status
Simulation time 82851448398 ps
CPU time 739.43 seconds
Started Jun 07 07:22:46 PM PDT 24
Finished Jun 07 07:35:08 PM PDT 24
Peak memory 200332 kb
Host smart-5ff876c0-07f5-48cb-87a8-bf2585a75ddb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331290731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.331290731
Directory /workspace/25.uart_stress_all/latest

Test location /workspace/coverage/default/25.uart_stress_all_with_rand_reset.1009590971
Short name T980
Test name
Test status
Simulation time 74758831225 ps
CPU time 858.73 seconds
Started Jun 07 07:22:51 PM PDT 24
Finished Jun 07 07:37:16 PM PDT 24
Peak memory 216960 kb
Host smart-d10ee2eb-0460-4664-90ee-86587306fc4e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009590971 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 25.uart_stress_all_with_rand_reset.1009590971
Directory /workspace/25.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.uart_tx_ovrd.409969514
Short name T578
Test name
Test status
Simulation time 984126868 ps
CPU time 3.28 seconds
Started Jun 07 07:22:51 PM PDT 24
Finished Jun 07 07:23:01 PM PDT 24
Peak memory 198968 kb
Host smart-9f3bf778-7f6e-4011-b6b0-97250ab17550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409969514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.409969514
Directory /workspace/25.uart_tx_ovrd/latest

Test location /workspace/coverage/default/25.uart_tx_rx.2936281843
Short name T450
Test name
Test status
Simulation time 21618676829 ps
CPU time 38.39 seconds
Started Jun 07 07:22:55 PM PDT 24
Finished Jun 07 07:23:42 PM PDT 24
Peak memory 200412 kb
Host smart-bafd4c79-e293-4f6b-9188-006e5d3ce395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936281843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.2936281843
Directory /workspace/25.uart_tx_rx/latest

Test location /workspace/coverage/default/252.uart_fifo_reset.2271973996
Short name T307
Test name
Test status
Simulation time 183347558764 ps
CPU time 221.13 seconds
Started Jun 07 07:27:40 PM PDT 24
Finished Jun 07 07:31:26 PM PDT 24
Peak memory 200272 kb
Host smart-79096da0-99a0-4147-ac56-68b01b4fe560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271973996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.2271973996
Directory /workspace/252.uart_fifo_reset/latest

Test location /workspace/coverage/default/253.uart_fifo_reset.287426008
Short name T440
Test name
Test status
Simulation time 61652225630 ps
CPU time 35.06 seconds
Started Jun 07 07:27:42 PM PDT 24
Finished Jun 07 07:28:22 PM PDT 24
Peak memory 200364 kb
Host smart-9d1f58e4-048f-4dbc-a2ff-563997a9defd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287426008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.287426008
Directory /workspace/253.uart_fifo_reset/latest

Test location /workspace/coverage/default/254.uart_fifo_reset.2358123536
Short name T483
Test name
Test status
Simulation time 69334479457 ps
CPU time 118.27 seconds
Started Jun 07 07:27:39 PM PDT 24
Finished Jun 07 07:29:42 PM PDT 24
Peak memory 200280 kb
Host smart-57943b4f-7546-4f4e-9814-dc07091ef478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358123536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.2358123536
Directory /workspace/254.uart_fifo_reset/latest

Test location /workspace/coverage/default/255.uart_fifo_reset.3283257062
Short name T206
Test name
Test status
Simulation time 29828266737 ps
CPU time 27.33 seconds
Started Jun 07 07:27:40 PM PDT 24
Finished Jun 07 07:28:12 PM PDT 24
Peak memory 199980 kb
Host smart-f690fa42-5135-41c0-89b2-75f809c69f59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283257062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.3283257062
Directory /workspace/255.uart_fifo_reset/latest

Test location /workspace/coverage/default/256.uart_fifo_reset.2872655556
Short name T46
Test name
Test status
Simulation time 41888836717 ps
CPU time 18.92 seconds
Started Jun 07 07:27:39 PM PDT 24
Finished Jun 07 07:28:02 PM PDT 24
Peak memory 199988 kb
Host smart-f3626122-7fa7-460c-b28c-9d97b756e605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872655556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.2872655556
Directory /workspace/256.uart_fifo_reset/latest

Test location /workspace/coverage/default/257.uart_fifo_reset.2059109974
Short name T346
Test name
Test status
Simulation time 27192817201 ps
CPU time 24.23 seconds
Started Jun 07 07:27:39 PM PDT 24
Finished Jun 07 07:28:07 PM PDT 24
Peak memory 200312 kb
Host smart-8280c0c8-80d0-4d7b-a895-e2ededabce53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059109974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.2059109974
Directory /workspace/257.uart_fifo_reset/latest

Test location /workspace/coverage/default/258.uart_fifo_reset.626989252
Short name T949
Test name
Test status
Simulation time 88335288199 ps
CPU time 150.88 seconds
Started Jun 07 07:27:40 PM PDT 24
Finished Jun 07 07:30:16 PM PDT 24
Peak memory 200312 kb
Host smart-18ca8a42-520e-4d5b-91d0-dc0bad9b7922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626989252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.626989252
Directory /workspace/258.uart_fifo_reset/latest

Test location /workspace/coverage/default/259.uart_fifo_reset.1347622132
Short name T808
Test name
Test status
Simulation time 97475362888 ps
CPU time 220.91 seconds
Started Jun 07 07:27:44 PM PDT 24
Finished Jun 07 07:31:29 PM PDT 24
Peak memory 200308 kb
Host smart-0495cd7e-4312-424d-ad2c-f5049f4827b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347622132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.1347622132
Directory /workspace/259.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_alert_test.1197654120
Short name T369
Test name
Test status
Simulation time 26081689 ps
CPU time 0.58 seconds
Started Jun 07 07:23:01 PM PDT 24
Finished Jun 07 07:23:12 PM PDT 24
Peak memory 195684 kb
Host smart-5b3566b5-1faa-495a-b31a-bca00e118e13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197654120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.1197654120
Directory /workspace/26.uart_alert_test/latest

Test location /workspace/coverage/default/26.uart_fifo_full.1093127922
Short name T719
Test name
Test status
Simulation time 72872267209 ps
CPU time 117.95 seconds
Started Jun 07 07:22:59 PM PDT 24
Finished Jun 07 07:25:06 PM PDT 24
Peak memory 200448 kb
Host smart-f895b2ae-cc91-4fe6-a4b9-dabb18a2b25a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093127922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.1093127922
Directory /workspace/26.uart_fifo_full/latest

Test location /workspace/coverage/default/26.uart_fifo_overflow.3607246983
Short name T936
Test name
Test status
Simulation time 18220572296 ps
CPU time 17.11 seconds
Started Jun 07 07:23:02 PM PDT 24
Finished Jun 07 07:23:31 PM PDT 24
Peak memory 200292 kb
Host smart-0d2cdae4-a4db-44a5-a0e2-501b9578cce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607246983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.3607246983
Directory /workspace/26.uart_fifo_overflow/latest

Test location /workspace/coverage/default/26.uart_fifo_reset.3534985676
Short name T540
Test name
Test status
Simulation time 88566505587 ps
CPU time 134.07 seconds
Started Jun 07 07:22:58 PM PDT 24
Finished Jun 07 07:25:21 PM PDT 24
Peak memory 200448 kb
Host smart-21a99bcf-9dd9-455a-bab4-59aea4044a2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534985676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.3534985676
Directory /workspace/26.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_long_xfer_wo_dly.4283730570
Short name T797
Test name
Test status
Simulation time 147183176282 ps
CPU time 1241.53 seconds
Started Jun 07 07:23:05 PM PDT 24
Finished Jun 07 07:43:59 PM PDT 24
Peak memory 200504 kb
Host smart-35e3e6a9-6252-482e-9acb-90d504a6c25c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4283730570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.4283730570
Directory /workspace/26.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/26.uart_loopback.1314952774
Short name T689
Test name
Test status
Simulation time 7804850749 ps
CPU time 10.69 seconds
Started Jun 07 07:23:04 PM PDT 24
Finished Jun 07 07:23:27 PM PDT 24
Peak memory 200080 kb
Host smart-81b40eb5-9ac2-492a-bafb-61b646feccae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314952774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_loopback.1314952774
Directory /workspace/26.uart_loopback/latest

Test location /workspace/coverage/default/26.uart_perf.932024115
Short name T704
Test name
Test status
Simulation time 15399439219 ps
CPU time 852.32 seconds
Started Jun 07 07:22:59 PM PDT 24
Finished Jun 07 07:37:21 PM PDT 24
Peak memory 200340 kb
Host smart-b2456fb3-85c2-45e4-bd46-219def8f4649
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=932024115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.932024115
Directory /workspace/26.uart_perf/latest

Test location /workspace/coverage/default/26.uart_rx_oversample.3011281472
Short name T1059
Test name
Test status
Simulation time 3075905297 ps
CPU time 11.93 seconds
Started Jun 07 07:23:01 PM PDT 24
Finished Jun 07 07:23:24 PM PDT 24
Peak memory 198548 kb
Host smart-15de572e-849a-4d3f-b649-bf786ed89e7f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3011281472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.3011281472
Directory /workspace/26.uart_rx_oversample/latest

Test location /workspace/coverage/default/26.uart_rx_parity_err.2893768198
Short name T781
Test name
Test status
Simulation time 60035853244 ps
CPU time 115.43 seconds
Started Jun 07 07:23:02 PM PDT 24
Finished Jun 07 07:25:08 PM PDT 24
Peak memory 200316 kb
Host smart-eef8919e-0747-478a-84e5-cae3a81ddc24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893768198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.2893768198
Directory /workspace/26.uart_rx_parity_err/latest

Test location /workspace/coverage/default/26.uart_rx_start_bit_filter.383683591
Short name T4
Test name
Test status
Simulation time 3359126648 ps
CPU time 1.51 seconds
Started Jun 07 07:23:01 PM PDT 24
Finished Jun 07 07:23:13 PM PDT 24
Peak memory 196148 kb
Host smart-c4398c85-6ad5-48a9-b6a1-4037b2ffbd5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383683591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.383683591
Directory /workspace/26.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/26.uart_smoke.2152297131
Short name T486
Test name
Test status
Simulation time 442334140 ps
CPU time 2.43 seconds
Started Jun 07 07:22:53 PM PDT 24
Finished Jun 07 07:23:03 PM PDT 24
Peak memory 198720 kb
Host smart-e7b091e7-3f28-4d08-ac58-c90fcedb29ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152297131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_smoke.2152297131
Directory /workspace/26.uart_smoke/latest

Test location /workspace/coverage/default/26.uart_stress_all_with_rand_reset.4241102900
Short name T747
Test name
Test status
Simulation time 103313665368 ps
CPU time 534.87 seconds
Started Jun 07 07:23:00 PM PDT 24
Finished Jun 07 07:32:05 PM PDT 24
Peak memory 216700 kb
Host smart-f6ade28c-2246-4cde-99af-5cbd7ebc392f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241102900 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 26.uart_stress_all_with_rand_reset.4241102900
Directory /workspace/26.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.uart_tx_ovrd.1688651108
Short name T784
Test name
Test status
Simulation time 6206832385 ps
CPU time 15.27 seconds
Started Jun 07 07:23:03 PM PDT 24
Finished Jun 07 07:23:30 PM PDT 24
Peak memory 200364 kb
Host smart-922e26d8-b345-49c6-bab4-077d4d07dd35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688651108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.1688651108
Directory /workspace/26.uart_tx_ovrd/latest

Test location /workspace/coverage/default/26.uart_tx_rx.1138535429
Short name T889
Test name
Test status
Simulation time 17196899570 ps
CPU time 13.79 seconds
Started Jun 07 07:22:50 PM PDT 24
Finished Jun 07 07:23:10 PM PDT 24
Peak memory 197544 kb
Host smart-3b6bb4cf-61d9-41f7-a19b-52dbc42a8890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138535429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.1138535429
Directory /workspace/26.uart_tx_rx/latest

Test location /workspace/coverage/default/260.uart_fifo_reset.1372862522
Short name T213
Test name
Test status
Simulation time 89063562113 ps
CPU time 29.77 seconds
Started Jun 07 07:27:43 PM PDT 24
Finished Jun 07 07:28:17 PM PDT 24
Peak memory 200224 kb
Host smart-982f64a0-6df2-498b-93b3-22703fbb9164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372862522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.1372862522
Directory /workspace/260.uart_fifo_reset/latest

Test location /workspace/coverage/default/261.uart_fifo_reset.2497904880
Short name T623
Test name
Test status
Simulation time 16879582221 ps
CPU time 10.91 seconds
Started Jun 07 07:27:50 PM PDT 24
Finished Jun 07 07:28:06 PM PDT 24
Peak memory 200332 kb
Host smart-2e95ef25-277f-4243-b265-950f725abf53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497904880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.2497904880
Directory /workspace/261.uart_fifo_reset/latest

Test location /workspace/coverage/default/262.uart_fifo_reset.2187190249
Short name T347
Test name
Test status
Simulation time 104972906522 ps
CPU time 52.45 seconds
Started Jun 07 07:27:48 PM PDT 24
Finished Jun 07 07:28:43 PM PDT 24
Peak memory 200316 kb
Host smart-a87589da-6b43-4ed5-89f0-8a4315f53dc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187190249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.2187190249
Directory /workspace/262.uart_fifo_reset/latest

Test location /workspace/coverage/default/264.uart_fifo_reset.3635152443
Short name T1007
Test name
Test status
Simulation time 22858325843 ps
CPU time 39 seconds
Started Jun 07 07:27:51 PM PDT 24
Finished Jun 07 07:28:35 PM PDT 24
Peak memory 200440 kb
Host smart-bca7b8e2-00ed-45f6-b226-6fd72abf7fac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635152443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.3635152443
Directory /workspace/264.uart_fifo_reset/latest

Test location /workspace/coverage/default/265.uart_fifo_reset.3448511141
Short name T628
Test name
Test status
Simulation time 12638946091 ps
CPU time 29.85 seconds
Started Jun 07 07:27:51 PM PDT 24
Finished Jun 07 07:28:27 PM PDT 24
Peak memory 200360 kb
Host smart-c9247591-8a73-4dd3-a8c2-a1a6229e61cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448511141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.3448511141
Directory /workspace/265.uart_fifo_reset/latest

Test location /workspace/coverage/default/266.uart_fifo_reset.2732887988
Short name T85
Test name
Test status
Simulation time 33605999554 ps
CPU time 15.2 seconds
Started Jun 07 07:27:49 PM PDT 24
Finished Jun 07 07:28:09 PM PDT 24
Peak memory 200376 kb
Host smart-600efd90-5ea1-42f1-99ef-23ace7916b92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732887988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.2732887988
Directory /workspace/266.uart_fifo_reset/latest

Test location /workspace/coverage/default/267.uart_fifo_reset.2423304085
Short name T555
Test name
Test status
Simulation time 155963334069 ps
CPU time 63.68 seconds
Started Jun 07 07:27:51 PM PDT 24
Finished Jun 07 07:29:00 PM PDT 24
Peak memory 200172 kb
Host smart-1f0d4098-11ef-4428-8bf1-75631b0b7f6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423304085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.2423304085
Directory /workspace/267.uart_fifo_reset/latest

Test location /workspace/coverage/default/268.uart_fifo_reset.4267805195
Short name T554
Test name
Test status
Simulation time 82475098845 ps
CPU time 64.44 seconds
Started Jun 07 07:27:52 PM PDT 24
Finished Jun 07 07:29:02 PM PDT 24
Peak memory 200232 kb
Host smart-30455198-54ae-45e6-98b3-f61ee3441fc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267805195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.4267805195
Directory /workspace/268.uart_fifo_reset/latest

Test location /workspace/coverage/default/269.uart_fifo_reset.3081563429
Short name T205
Test name
Test status
Simulation time 69697493572 ps
CPU time 20.88 seconds
Started Jun 07 07:27:49 PM PDT 24
Finished Jun 07 07:28:15 PM PDT 24
Peak memory 200404 kb
Host smart-c4686ddf-2371-48cf-b9ec-6bb9400f2211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081563429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.3081563429
Directory /workspace/269.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_alert_test.4266206639
Short name T927
Test name
Test status
Simulation time 17329961 ps
CPU time 0.57 seconds
Started Jun 07 07:23:03 PM PDT 24
Finished Jun 07 07:23:16 PM PDT 24
Peak memory 195648 kb
Host smart-60f8a39a-3610-451b-a024-7218e86f4800
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266206639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.4266206639
Directory /workspace/27.uart_alert_test/latest

Test location /workspace/coverage/default/27.uart_fifo_full.1857330994
Short name T484
Test name
Test status
Simulation time 193409003108 ps
CPU time 69.65 seconds
Started Jun 07 07:23:01 PM PDT 24
Finished Jun 07 07:24:22 PM PDT 24
Peak memory 200400 kb
Host smart-93234c52-39f1-4a5b-91db-b930833f3bf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857330994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.1857330994
Directory /workspace/27.uart_fifo_full/latest

Test location /workspace/coverage/default/27.uart_fifo_overflow.2801552804
Short name T590
Test name
Test status
Simulation time 10232473676 ps
CPU time 18.32 seconds
Started Jun 07 07:23:02 PM PDT 24
Finished Jun 07 07:23:32 PM PDT 24
Peak memory 200352 kb
Host smart-7126fdf7-158e-4cce-befd-df60c5354cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801552804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.2801552804
Directory /workspace/27.uart_fifo_overflow/latest

Test location /workspace/coverage/default/27.uart_fifo_reset.2061220560
Short name T805
Test name
Test status
Simulation time 142264295965 ps
CPU time 207.67 seconds
Started Jun 07 07:23:04 PM PDT 24
Finished Jun 07 07:26:43 PM PDT 24
Peak memory 200492 kb
Host smart-0fe9c072-fc0d-4465-86a0-f2af447dd797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061220560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.2061220560
Directory /workspace/27.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_intr.297679391
Short name T340
Test name
Test status
Simulation time 43694964059 ps
CPU time 68.09 seconds
Started Jun 07 07:23:07 PM PDT 24
Finished Jun 07 07:24:27 PM PDT 24
Peak memory 199356 kb
Host smart-5e8c47d7-bcf2-4155-a8ff-d618a159c429
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297679391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.297679391
Directory /workspace/27.uart_intr/latest

Test location /workspace/coverage/default/27.uart_long_xfer_wo_dly.806418043
Short name T428
Test name
Test status
Simulation time 46585204689 ps
CPU time 162.03 seconds
Started Jun 07 07:23:01 PM PDT 24
Finished Jun 07 07:25:55 PM PDT 24
Peak memory 200416 kb
Host smart-a253bc22-e4af-41ff-9729-002f25aa74f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=806418043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.806418043
Directory /workspace/27.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/27.uart_loopback.1337089726
Short name T353
Test name
Test status
Simulation time 6195338434 ps
CPU time 3.17 seconds
Started Jun 07 07:23:06 PM PDT 24
Finished Jun 07 07:23:22 PM PDT 24
Peak memory 198212 kb
Host smart-e6cab16e-19d5-4c0f-a789-7f80b6beac18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337089726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_loopback.1337089726
Directory /workspace/27.uart_loopback/latest

Test location /workspace/coverage/default/27.uart_perf.386458858
Short name T679
Test name
Test status
Simulation time 17631078623 ps
CPU time 1027.8 seconds
Started Jun 07 07:23:02 PM PDT 24
Finished Jun 07 07:40:21 PM PDT 24
Peak memory 200388 kb
Host smart-88e6233e-0932-4edd-bd41-13538d446b26
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=386458858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.386458858
Directory /workspace/27.uart_perf/latest

Test location /workspace/coverage/default/27.uart_rx_oversample.922422080
Short name T739
Test name
Test status
Simulation time 2884637650 ps
CPU time 5.48 seconds
Started Jun 07 07:23:02 PM PDT 24
Finished Jun 07 07:23:19 PM PDT 24
Peak memory 199360 kb
Host smart-14f03b51-c2a1-4da4-ba29-f4b47fc35513
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=922422080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.922422080
Directory /workspace/27.uart_rx_oversample/latest

Test location /workspace/coverage/default/27.uart_rx_parity_err.955181840
Short name T1063
Test name
Test status
Simulation time 95262512890 ps
CPU time 37.15 seconds
Started Jun 07 07:23:02 PM PDT 24
Finished Jun 07 07:23:50 PM PDT 24
Peak memory 200280 kb
Host smart-86636ead-eca7-4f6c-a9cf-d7287570f5a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955181840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.955181840
Directory /workspace/27.uart_rx_parity_err/latest

Test location /workspace/coverage/default/27.uart_rx_start_bit_filter.69380949
Short name T1033
Test name
Test status
Simulation time 46578246747 ps
CPU time 19.51 seconds
Started Jun 07 07:23:07 PM PDT 24
Finished Jun 07 07:23:39 PM PDT 24
Peak memory 196188 kb
Host smart-9beecff8-dc50-4e94-9e98-26d06df23b43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69380949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.69380949
Directory /workspace/27.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/27.uart_smoke.1960619730
Short name T672
Test name
Test status
Simulation time 5733352818 ps
CPU time 7.67 seconds
Started Jun 07 07:23:01 PM PDT 24
Finished Jun 07 07:23:19 PM PDT 24
Peak memory 200228 kb
Host smart-3c473fef-43c9-43ce-977d-c8eafb02de52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960619730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_smoke.1960619730
Directory /workspace/27.uart_smoke/latest

Test location /workspace/coverage/default/27.uart_stress_all.4113970884
Short name T84
Test name
Test status
Simulation time 9264019065 ps
CPU time 11.03 seconds
Started Jun 07 07:23:01 PM PDT 24
Finished Jun 07 07:23:23 PM PDT 24
Peak memory 200364 kb
Host smart-28cce23e-1ebe-410d-ac70-c32d1a0fca73
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113970884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.4113970884
Directory /workspace/27.uart_stress_all/latest

Test location /workspace/coverage/default/27.uart_tx_ovrd.1939081705
Short name T591
Test name
Test status
Simulation time 7089379750 ps
CPU time 17.76 seconds
Started Jun 07 07:23:02 PM PDT 24
Finished Jun 07 07:23:32 PM PDT 24
Peak memory 199676 kb
Host smart-34d7bf2e-5fe9-437b-9117-0205e1add73f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939081705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.1939081705
Directory /workspace/27.uart_tx_ovrd/latest

Test location /workspace/coverage/default/27.uart_tx_rx.1571461856
Short name T1070
Test name
Test status
Simulation time 38986517514 ps
CPU time 19.88 seconds
Started Jun 07 07:23:05 PM PDT 24
Finished Jun 07 07:23:37 PM PDT 24
Peak memory 200460 kb
Host smart-aeee89d6-641b-4237-a4c5-466efc762e03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571461856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.1571461856
Directory /workspace/27.uart_tx_rx/latest

Test location /workspace/coverage/default/270.uart_fifo_reset.1004649326
Short name T857
Test name
Test status
Simulation time 337555040317 ps
CPU time 27.34 seconds
Started Jun 07 07:27:51 PM PDT 24
Finished Jun 07 07:28:23 PM PDT 24
Peak memory 200360 kb
Host smart-3ae72099-8fc2-4e98-a77e-fd32fc4a342b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004649326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.1004649326
Directory /workspace/270.uart_fifo_reset/latest

Test location /workspace/coverage/default/271.uart_fifo_reset.1807643351
Short name T958
Test name
Test status
Simulation time 115630473348 ps
CPU time 192.29 seconds
Started Jun 07 07:27:48 PM PDT 24
Finished Jun 07 07:31:03 PM PDT 24
Peak memory 200348 kb
Host smart-2253ad8f-22f8-40c1-b07f-fcc3dff539b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807643351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.1807643351
Directory /workspace/271.uart_fifo_reset/latest

Test location /workspace/coverage/default/272.uart_fifo_reset.3028803471
Short name T241
Test name
Test status
Simulation time 82701492653 ps
CPU time 125.13 seconds
Started Jun 07 07:27:50 PM PDT 24
Finished Jun 07 07:29:59 PM PDT 24
Peak memory 200340 kb
Host smart-c9312434-0163-4e3a-84ad-4f206dd03c37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028803471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.3028803471
Directory /workspace/272.uart_fifo_reset/latest

Test location /workspace/coverage/default/273.uart_fifo_reset.2641896420
Short name T859
Test name
Test status
Simulation time 17865916690 ps
CPU time 27.82 seconds
Started Jun 07 07:27:49 PM PDT 24
Finished Jun 07 07:28:22 PM PDT 24
Peak memory 200388 kb
Host smart-ecb59193-32d5-48c8-b634-ac9a28049414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641896420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.2641896420
Directory /workspace/273.uart_fifo_reset/latest

Test location /workspace/coverage/default/274.uart_fifo_reset.475863099
Short name T214
Test name
Test status
Simulation time 136562611589 ps
CPU time 215.21 seconds
Started Jun 07 07:27:50 PM PDT 24
Finished Jun 07 07:31:30 PM PDT 24
Peak memory 200420 kb
Host smart-30e2f9db-2476-43de-bf39-b8777ada6e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475863099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.475863099
Directory /workspace/274.uart_fifo_reset/latest

Test location /workspace/coverage/default/276.uart_fifo_reset.1320719219
Short name T195
Test name
Test status
Simulation time 95366767539 ps
CPU time 127.46 seconds
Started Jun 07 07:27:48 PM PDT 24
Finished Jun 07 07:30:00 PM PDT 24
Peak memory 200304 kb
Host smart-4e13afff-e470-4fd4-9971-81e4abb9b69c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320719219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.1320719219
Directory /workspace/276.uart_fifo_reset/latest

Test location /workspace/coverage/default/277.uart_fifo_reset.1904537573
Short name T212
Test name
Test status
Simulation time 12996211298 ps
CPU time 20.02 seconds
Started Jun 07 07:27:49 PM PDT 24
Finished Jun 07 07:28:14 PM PDT 24
Peak memory 200340 kb
Host smart-0cf7386b-4a34-460b-964c-51bd413a1556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904537573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.1904537573
Directory /workspace/277.uart_fifo_reset/latest

Test location /workspace/coverage/default/278.uart_fifo_reset.1238373839
Short name T707
Test name
Test status
Simulation time 103137403236 ps
CPU time 170.81 seconds
Started Jun 07 07:27:51 PM PDT 24
Finished Jun 07 07:30:47 PM PDT 24
Peak memory 200440 kb
Host smart-4bed8a33-4bc9-4868-98ea-954ed8a757b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238373839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.1238373839
Directory /workspace/278.uart_fifo_reset/latest

Test location /workspace/coverage/default/279.uart_fifo_reset.1635138196
Short name T412
Test name
Test status
Simulation time 28493250158 ps
CPU time 11.18 seconds
Started Jun 07 07:27:50 PM PDT 24
Finished Jun 07 07:28:06 PM PDT 24
Peak memory 200276 kb
Host smart-e260a04e-2f3e-453e-9456-53677aa8112e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635138196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.1635138196
Directory /workspace/279.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_alert_test.2348593381
Short name T409
Test name
Test status
Simulation time 13893670 ps
CPU time 0.56 seconds
Started Jun 07 07:23:10 PM PDT 24
Finished Jun 07 07:23:24 PM PDT 24
Peak memory 195792 kb
Host smart-44349100-b829-4857-84d1-cb38a0c270bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348593381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.2348593381
Directory /workspace/28.uart_alert_test/latest

Test location /workspace/coverage/default/28.uart_fifo_full.2560559170
Short name T937
Test name
Test status
Simulation time 25531156633 ps
CPU time 45.54 seconds
Started Jun 07 07:23:02 PM PDT 24
Finished Jun 07 07:23:59 PM PDT 24
Peak memory 200224 kb
Host smart-3fc09bb4-028b-4cee-834d-12cd7ddf2a7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560559170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.2560559170
Directory /workspace/28.uart_fifo_full/latest

Test location /workspace/coverage/default/28.uart_fifo_overflow.1917904506
Short name T481
Test name
Test status
Simulation time 14405642892 ps
CPU time 9.54 seconds
Started Jun 07 07:23:07 PM PDT 24
Finished Jun 07 07:23:29 PM PDT 24
Peak memory 200416 kb
Host smart-20ea28d4-403b-4dda-b798-de7a1203ec19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917904506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.1917904506
Directory /workspace/28.uart_fifo_overflow/latest

Test location /workspace/coverage/default/28.uart_fifo_reset.3127436009
Short name T785
Test name
Test status
Simulation time 37736333603 ps
CPU time 67.25 seconds
Started Jun 07 07:23:03 PM PDT 24
Finished Jun 07 07:24:23 PM PDT 24
Peak memory 199632 kb
Host smart-261ffa51-b76a-4e87-b232-dfe5d3d80918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127436009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.3127436009
Directory /workspace/28.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_intr.3819829934
Short name T417
Test name
Test status
Simulation time 4670145151 ps
CPU time 5.31 seconds
Started Jun 07 07:23:06 PM PDT 24
Finished Jun 07 07:23:23 PM PDT 24
Peak memory 200300 kb
Host smart-9b808326-98a1-465f-86f2-a030e675932c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819829934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.3819829934
Directory /workspace/28.uart_intr/latest

Test location /workspace/coverage/default/28.uart_long_xfer_wo_dly.2156369065
Short name T459
Test name
Test status
Simulation time 195874711260 ps
CPU time 308.31 seconds
Started Jun 07 07:23:08 PM PDT 24
Finished Jun 07 07:28:28 PM PDT 24
Peak memory 200432 kb
Host smart-08b76a4e-b9a2-424e-8308-d46c7b5e6309
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2156369065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.2156369065
Directory /workspace/28.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/28.uart_loopback.4260907580
Short name T670
Test name
Test status
Simulation time 9533208976 ps
CPU time 6.58 seconds
Started Jun 07 07:23:10 PM PDT 24
Finished Jun 07 07:23:30 PM PDT 24
Peak memory 199960 kb
Host smart-65788d4e-0186-4d45-aff2-aea86157c043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260907580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_loopback.4260907580
Directory /workspace/28.uart_loopback/latest

Test location /workspace/coverage/default/28.uart_perf.1155567955
Short name T288
Test name
Test status
Simulation time 6010302908 ps
CPU time 87.43 seconds
Started Jun 07 07:23:07 PM PDT 24
Finished Jun 07 07:24:48 PM PDT 24
Peak memory 200376 kb
Host smart-e92d4eee-f1c5-44b3-888a-b2c46f376a34
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1155567955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.1155567955
Directory /workspace/28.uart_perf/latest

Test location /workspace/coverage/default/28.uart_rx_oversample.3333156343
Short name T482
Test name
Test status
Simulation time 7370787867 ps
CPU time 17.85 seconds
Started Jun 07 07:23:06 PM PDT 24
Finished Jun 07 07:23:35 PM PDT 24
Peak memory 199648 kb
Host smart-e26ce2ea-e8cf-42d2-820f-c0f9281c9069
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3333156343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.3333156343
Directory /workspace/28.uart_rx_oversample/latest

Test location /workspace/coverage/default/28.uart_rx_parity_err.954474312
Short name T376
Test name
Test status
Simulation time 126941187052 ps
CPU time 101.69 seconds
Started Jun 07 07:23:11 PM PDT 24
Finished Jun 07 07:25:06 PM PDT 24
Peak memory 200404 kb
Host smart-c325c485-2227-4944-beb5-8fec6b7707da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954474312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.954474312
Directory /workspace/28.uart_rx_parity_err/latest

Test location /workspace/coverage/default/28.uart_rx_start_bit_filter.2865798687
Short name T1071
Test name
Test status
Simulation time 2692348770 ps
CPU time 0.86 seconds
Started Jun 07 07:23:10 PM PDT 24
Finished Jun 07 07:23:24 PM PDT 24
Peak memory 196136 kb
Host smart-5d752283-e98b-4598-a8ee-aa239fafdc54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865798687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.2865798687
Directory /workspace/28.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/28.uart_smoke.4079460559
Short name T602
Test name
Test status
Simulation time 700253228 ps
CPU time 1.69 seconds
Started Jun 07 07:23:02 PM PDT 24
Finished Jun 07 07:23:15 PM PDT 24
Peak memory 199204 kb
Host smart-b131e48e-9390-4cf9-b9e8-c9689206f3ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079460559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_smoke.4079460559
Directory /workspace/28.uart_smoke/latest

Test location /workspace/coverage/default/28.uart_stress_all_with_rand_reset.575932997
Short name T997
Test name
Test status
Simulation time 58646464044 ps
CPU time 587.46 seconds
Started Jun 07 07:23:10 PM PDT 24
Finished Jun 07 07:33:11 PM PDT 24
Peak memory 216680 kb
Host smart-62e4ab55-b50f-4a01-aa77-3afbe121dc40
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575932997 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 28.uart_stress_all_with_rand_reset.575932997
Directory /workspace/28.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.uart_tx_ovrd.1872614285
Short name T886
Test name
Test status
Simulation time 791428007 ps
CPU time 4.5 seconds
Started Jun 07 07:23:08 PM PDT 24
Finished Jun 07 07:23:26 PM PDT 24
Peak memory 199252 kb
Host smart-35954652-b8cf-4523-8606-befa397a99ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872614285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.1872614285
Directory /workspace/28.uart_tx_ovrd/latest

Test location /workspace/coverage/default/28.uart_tx_rx.115892274
Short name T1000
Test name
Test status
Simulation time 128607331817 ps
CPU time 47.09 seconds
Started Jun 07 07:23:00 PM PDT 24
Finished Jun 07 07:23:58 PM PDT 24
Peak memory 200372 kb
Host smart-4066c2ed-e19e-4bd3-9fc6-150b663f16b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115892274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.115892274
Directory /workspace/28.uart_tx_rx/latest

Test location /workspace/coverage/default/281.uart_fifo_reset.1893736380
Short name T690
Test name
Test status
Simulation time 76725495559 ps
CPU time 120.25 seconds
Started Jun 07 07:27:59 PM PDT 24
Finished Jun 07 07:30:04 PM PDT 24
Peak memory 200176 kb
Host smart-472e4722-a2b2-43fd-aae3-0f458238de73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893736380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.1893736380
Directory /workspace/281.uart_fifo_reset/latest

Test location /workspace/coverage/default/282.uart_fifo_reset.1501030441
Short name T621
Test name
Test status
Simulation time 16715282041 ps
CPU time 24.69 seconds
Started Jun 07 07:28:00 PM PDT 24
Finished Jun 07 07:28:30 PM PDT 24
Peak memory 200340 kb
Host smart-f94283a9-3ded-4f93-8df8-81adc64f95c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501030441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.1501030441
Directory /workspace/282.uart_fifo_reset/latest

Test location /workspace/coverage/default/283.uart_fifo_reset.1001877978
Short name T625
Test name
Test status
Simulation time 34895628293 ps
CPU time 17.49 seconds
Started Jun 07 07:28:02 PM PDT 24
Finished Jun 07 07:28:24 PM PDT 24
Peak memory 200060 kb
Host smart-9aafd8b5-5750-4b25-a1d0-5dd956e1fd17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001877978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.1001877978
Directory /workspace/283.uart_fifo_reset/latest

Test location /workspace/coverage/default/284.uart_fifo_reset.4015786573
Short name T630
Test name
Test status
Simulation time 30815161158 ps
CPU time 13.46 seconds
Started Jun 07 07:28:00 PM PDT 24
Finished Jun 07 07:28:18 PM PDT 24
Peak memory 200300 kb
Host smart-9ee414be-c021-4519-83ed-2c3c91122d55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015786573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.4015786573
Directory /workspace/284.uart_fifo_reset/latest

Test location /workspace/coverage/default/285.uart_fifo_reset.3717566596
Short name T531
Test name
Test status
Simulation time 60707284227 ps
CPU time 26.68 seconds
Started Jun 07 07:27:59 PM PDT 24
Finished Jun 07 07:28:31 PM PDT 24
Peak memory 200304 kb
Host smart-a0e0f7f4-d0c1-44b2-8c43-5dc95344adc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717566596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.3717566596
Directory /workspace/285.uart_fifo_reset/latest

Test location /workspace/coverage/default/286.uart_fifo_reset.716549574
Short name T95
Test name
Test status
Simulation time 5171138775 ps
CPU time 11.04 seconds
Started Jun 07 07:28:00 PM PDT 24
Finished Jun 07 07:28:15 PM PDT 24
Peak memory 200420 kb
Host smart-77a4798c-eb8e-484c-aff2-4f5ab4571197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716549574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.716549574
Directory /workspace/286.uart_fifo_reset/latest

Test location /workspace/coverage/default/287.uart_fifo_reset.1549217548
Short name T244
Test name
Test status
Simulation time 38449305172 ps
CPU time 16.17 seconds
Started Jun 07 07:28:00 PM PDT 24
Finished Jun 07 07:28:21 PM PDT 24
Peak memory 199104 kb
Host smart-86c4ae7c-ac52-4532-95ca-47c81cea1662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549217548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.1549217548
Directory /workspace/287.uart_fifo_reset/latest

Test location /workspace/coverage/default/289.uart_fifo_reset.3413286054
Short name T190
Test name
Test status
Simulation time 61503380525 ps
CPU time 98.64 seconds
Started Jun 07 07:27:58 PM PDT 24
Finished Jun 07 07:29:42 PM PDT 24
Peak memory 200280 kb
Host smart-cacb3e46-aa09-48c8-b4b6-c3575bd2531d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413286054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.3413286054
Directory /workspace/289.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_alert_test.3454726800
Short name T1042
Test name
Test status
Simulation time 14621125 ps
CPU time 0.54 seconds
Started Jun 07 07:23:14 PM PDT 24
Finished Jun 07 07:23:27 PM PDT 24
Peak memory 195704 kb
Host smart-523f8020-bb18-492c-a1ff-c99a6908fe1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454726800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.3454726800
Directory /workspace/29.uart_alert_test/latest

Test location /workspace/coverage/default/29.uart_fifo_full.4222211446
Short name T571
Test name
Test status
Simulation time 357881050764 ps
CPU time 403.88 seconds
Started Jun 07 07:23:10 PM PDT 24
Finished Jun 07 07:30:06 PM PDT 24
Peak memory 200448 kb
Host smart-88b6e138-ddfb-4430-8d47-0097a74012b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222211446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.4222211446
Directory /workspace/29.uart_fifo_full/latest

Test location /workspace/coverage/default/29.uart_fifo_overflow.2492055797
Short name T519
Test name
Test status
Simulation time 77188423471 ps
CPU time 34.49 seconds
Started Jun 07 07:23:09 PM PDT 24
Finished Jun 07 07:23:56 PM PDT 24
Peak memory 200408 kb
Host smart-58561939-9af9-414f-9e66-05494cf27da9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492055797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.2492055797
Directory /workspace/29.uart_fifo_overflow/latest

Test location /workspace/coverage/default/29.uart_fifo_reset.2713359765
Short name T1
Test name
Test status
Simulation time 25724515416 ps
CPU time 17.4 seconds
Started Jun 07 07:23:11 PM PDT 24
Finished Jun 07 07:23:42 PM PDT 24
Peak memory 200244 kb
Host smart-35ffbcc0-bbd1-45eb-992a-7081b95fda98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713359765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.2713359765
Directory /workspace/29.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_intr.4279488307
Short name T530
Test name
Test status
Simulation time 35169975432 ps
CPU time 10.84 seconds
Started Jun 07 07:23:10 PM PDT 24
Finished Jun 07 07:23:34 PM PDT 24
Peak memory 200400 kb
Host smart-175287fa-e6fa-4191-bbaf-0ef3bdce4c67
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279488307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.4279488307
Directory /workspace/29.uart_intr/latest

Test location /workspace/coverage/default/29.uart_loopback.2240820558
Short name T430
Test name
Test status
Simulation time 3314744042 ps
CPU time 6.2 seconds
Started Jun 07 07:23:09 PM PDT 24
Finished Jun 07 07:23:28 PM PDT 24
Peak memory 199404 kb
Host smart-1ee9bc83-e33b-48b0-a25e-c84afa28d02c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240820558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_loopback.2240820558
Directory /workspace/29.uart_loopback/latest

Test location /workspace/coverage/default/29.uart_perf.1795433659
Short name T117
Test name
Test status
Simulation time 20444353554 ps
CPU time 1104.76 seconds
Started Jun 07 07:23:15 PM PDT 24
Finished Jun 07 07:41:53 PM PDT 24
Peak memory 200356 kb
Host smart-7bf327ac-4bca-461f-9be5-d4f274de9bd8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1795433659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.1795433659
Directory /workspace/29.uart_perf/latest

Test location /workspace/coverage/default/29.uart_rx_oversample.737257572
Short name T510
Test name
Test status
Simulation time 5809212072 ps
CPU time 5.53 seconds
Started Jun 07 07:23:08 PM PDT 24
Finished Jun 07 07:23:26 PM PDT 24
Peak memory 198792 kb
Host smart-e9f61808-5003-45e5-a99e-d302acf27d42
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=737257572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.737257572
Directory /workspace/29.uart_rx_oversample/latest

Test location /workspace/coverage/default/29.uart_rx_parity_err.2355107314
Short name T697
Test name
Test status
Simulation time 168987150472 ps
CPU time 266.52 seconds
Started Jun 07 07:23:13 PM PDT 24
Finished Jun 07 07:27:52 PM PDT 24
Peak memory 200380 kb
Host smart-760686c3-ef46-4ac8-a7a7-78e201320126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355107314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.2355107314
Directory /workspace/29.uart_rx_parity_err/latest

Test location /workspace/coverage/default/29.uart_rx_start_bit_filter.4172697892
Short name T850
Test name
Test status
Simulation time 1563975941 ps
CPU time 3.11 seconds
Started Jun 07 07:23:14 PM PDT 24
Finished Jun 07 07:23:29 PM PDT 24
Peak memory 195796 kb
Host smart-ddc8699e-d98f-4a8c-a502-867f02d9c587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172697892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.4172697892
Directory /workspace/29.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/29.uart_smoke.441532125
Short name T816
Test name
Test status
Simulation time 518585701 ps
CPU time 1.16 seconds
Started Jun 07 07:23:09 PM PDT 24
Finished Jun 07 07:23:23 PM PDT 24
Peak memory 198600 kb
Host smart-e8e7984c-eedf-4a44-a8b6-cf2a6ae3c353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441532125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_smoke.441532125
Directory /workspace/29.uart_smoke/latest

Test location /workspace/coverage/default/29.uart_stress_all_with_rand_reset.1609027280
Short name T831
Test name
Test status
Simulation time 29745230949 ps
CPU time 526.77 seconds
Started Jun 07 07:23:18 PM PDT 24
Finished Jun 07 07:32:17 PM PDT 24
Peak memory 215928 kb
Host smart-d938d0bb-4a85-4210-8d31-fa2391557c86
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609027280 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 29.uart_stress_all_with_rand_reset.1609027280
Directory /workspace/29.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.uart_tx_ovrd.4041570756
Short name T527
Test name
Test status
Simulation time 1535351503 ps
CPU time 3.29 seconds
Started Jun 07 07:23:07 PM PDT 24
Finished Jun 07 07:23:22 PM PDT 24
Peak memory 200100 kb
Host smart-1e775014-2fab-4d5f-b385-a27bff873cf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041570756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.4041570756
Directory /workspace/29.uart_tx_ovrd/latest

Test location /workspace/coverage/default/29.uart_tx_rx.3823512168
Short name T780
Test name
Test status
Simulation time 85565521741 ps
CPU time 38.37 seconds
Started Jun 07 07:23:10 PM PDT 24
Finished Jun 07 07:24:02 PM PDT 24
Peak memory 200336 kb
Host smart-44920680-a31d-4710-89a6-a38ccf83f9e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823512168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.3823512168
Directory /workspace/29.uart_tx_rx/latest

Test location /workspace/coverage/default/290.uart_fifo_reset.3059983947
Short name T770
Test name
Test status
Simulation time 23172022409 ps
CPU time 13.56 seconds
Started Jun 07 07:27:59 PM PDT 24
Finished Jun 07 07:28:18 PM PDT 24
Peak memory 200340 kb
Host smart-40dada82-158b-4037-824c-0e0f31b2059c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059983947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.3059983947
Directory /workspace/290.uart_fifo_reset/latest

Test location /workspace/coverage/default/291.uart_fifo_reset.4151763065
Short name T919
Test name
Test status
Simulation time 70302793284 ps
CPU time 141.92 seconds
Started Jun 07 07:27:57 PM PDT 24
Finished Jun 07 07:30:24 PM PDT 24
Peak memory 200416 kb
Host smart-572b309c-23fe-4479-875d-a129ea48106a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151763065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.4151763065
Directory /workspace/291.uart_fifo_reset/latest

Test location /workspace/coverage/default/292.uart_fifo_reset.1662217696
Short name T914
Test name
Test status
Simulation time 33353086546 ps
CPU time 17.67 seconds
Started Jun 07 07:27:57 PM PDT 24
Finished Jun 07 07:28:20 PM PDT 24
Peak memory 200344 kb
Host smart-327a332f-e7c8-4c2c-9263-7a64180e1c76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662217696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.1662217696
Directory /workspace/292.uart_fifo_reset/latest

Test location /workspace/coverage/default/293.uart_fifo_reset.3158417672
Short name T1022
Test name
Test status
Simulation time 84404969779 ps
CPU time 147.06 seconds
Started Jun 07 07:28:01 PM PDT 24
Finished Jun 07 07:30:33 PM PDT 24
Peak memory 200420 kb
Host smart-0543f2cb-bef4-4c30-a0fb-7ec0ea870023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158417672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.3158417672
Directory /workspace/293.uart_fifo_reset/latest

Test location /workspace/coverage/default/294.uart_fifo_reset.1501824763
Short name T225
Test name
Test status
Simulation time 48177551544 ps
CPU time 40.98 seconds
Started Jun 07 07:27:59 PM PDT 24
Finished Jun 07 07:28:45 PM PDT 24
Peak memory 200456 kb
Host smart-1bb2999e-95fa-4c3a-8095-4301ee1aa88b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501824763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.1501824763
Directory /workspace/294.uart_fifo_reset/latest

Test location /workspace/coverage/default/295.uart_fifo_reset.632701643
Short name T908
Test name
Test status
Simulation time 78215572941 ps
CPU time 87.6 seconds
Started Jun 07 07:28:00 PM PDT 24
Finished Jun 07 07:29:33 PM PDT 24
Peak memory 200436 kb
Host smart-fa1fdc63-23b6-41c2-8680-d4a1e1b408e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632701643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.632701643
Directory /workspace/295.uart_fifo_reset/latest

Test location /workspace/coverage/default/296.uart_fifo_reset.1338662945
Short name T931
Test name
Test status
Simulation time 13784356010 ps
CPU time 13.05 seconds
Started Jun 07 07:27:58 PM PDT 24
Finished Jun 07 07:28:16 PM PDT 24
Peak memory 200400 kb
Host smart-f3d056cd-9f30-49a2-a4fe-41ea9376d8f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338662945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.1338662945
Directory /workspace/296.uart_fifo_reset/latest

Test location /workspace/coverage/default/297.uart_fifo_reset.44737430
Short name T821
Test name
Test status
Simulation time 11508358507 ps
CPU time 5.88 seconds
Started Jun 07 07:27:59 PM PDT 24
Finished Jun 07 07:28:10 PM PDT 24
Peak memory 200284 kb
Host smart-af2f411c-e872-4c57-9520-1df5eacc301e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44737430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.44737430
Directory /workspace/297.uart_fifo_reset/latest

Test location /workspace/coverage/default/298.uart_fifo_reset.4132452872
Short name T977
Test name
Test status
Simulation time 119513192201 ps
CPU time 129.22 seconds
Started Jun 07 07:28:00 PM PDT 24
Finished Jun 07 07:30:15 PM PDT 24
Peak memory 200368 kb
Host smart-9e1eba5b-c5b9-4f05-9895-db0cafa4f93e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132452872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.4132452872
Directory /workspace/298.uart_fifo_reset/latest

Test location /workspace/coverage/default/299.uart_fifo_reset.2590834952
Short name T763
Test name
Test status
Simulation time 20031715774 ps
CPU time 20.6 seconds
Started Jun 07 07:28:00 PM PDT 24
Finished Jun 07 07:28:26 PM PDT 24
Peak memory 200236 kb
Host smart-8e4aa90c-6504-424d-a62b-147e07ddacd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590834952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.2590834952
Directory /workspace/299.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_alert_test.3757815261
Short name T449
Test name
Test status
Simulation time 14713922 ps
CPU time 0.58 seconds
Started Jun 07 07:19:59 PM PDT 24
Finished Jun 07 07:20:25 PM PDT 24
Peak memory 196060 kb
Host smart-aee9d81b-3e6a-4bcc-805c-3c208ac67492
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757815261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.3757815261
Directory /workspace/3.uart_alert_test/latest

Test location /workspace/coverage/default/3.uart_fifo_full.2611894243
Short name T170
Test name
Test status
Simulation time 63504802129 ps
CPU time 29.43 seconds
Started Jun 07 07:19:47 PM PDT 24
Finished Jun 07 07:20:41 PM PDT 24
Peak memory 200332 kb
Host smart-b35ee0e3-e2b5-44d1-b9b7-e341fe928480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611894243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.2611894243
Directory /workspace/3.uart_fifo_full/latest

Test location /workspace/coverage/default/3.uart_fifo_overflow.646808183
Short name T68
Test name
Test status
Simulation time 66105037116 ps
CPU time 25.35 seconds
Started Jun 07 07:19:48 PM PDT 24
Finished Jun 07 07:20:37 PM PDT 24
Peak memory 200388 kb
Host smart-c0a57b78-8bf4-4624-9b8d-904f36e59606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646808183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.646808183
Directory /workspace/3.uart_fifo_overflow/latest

Test location /workspace/coverage/default/3.uart_fifo_reset.3220050895
Short name T649
Test name
Test status
Simulation time 22486801998 ps
CPU time 40.79 seconds
Started Jun 07 07:19:49 PM PDT 24
Finished Jun 07 07:20:55 PM PDT 24
Peak memory 200468 kb
Host smart-aca1a04a-d6e1-492f-985c-57643c89a7cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220050895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.3220050895
Directory /workspace/3.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_intr.3425885362
Short name T381
Test name
Test status
Simulation time 40408176118 ps
CPU time 64.27 seconds
Started Jun 07 07:19:48 PM PDT 24
Finished Jun 07 07:21:16 PM PDT 24
Peak memory 199260 kb
Host smart-b31cece5-a561-4d77-832b-65d5b83f65f6
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425885362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.3425885362
Directory /workspace/3.uart_intr/latest

Test location /workspace/coverage/default/3.uart_long_xfer_wo_dly.2206165705
Short name T324
Test name
Test status
Simulation time 94479575255 ps
CPU time 755.68 seconds
Started Jun 07 07:19:52 PM PDT 24
Finished Jun 07 07:32:52 PM PDT 24
Peak memory 200348 kb
Host smart-c8420514-8316-4450-b326-465b0100be3b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2206165705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.2206165705
Directory /workspace/3.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/3.uart_loopback.1585232187
Short name T49
Test name
Test status
Simulation time 1731239963 ps
CPU time 1.73 seconds
Started Jun 07 07:19:49 PM PDT 24
Finished Jun 07 07:20:16 PM PDT 24
Peak memory 197716 kb
Host smart-81f466fb-3ec4-43a5-b99e-f28e3af0d0fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585232187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_loopback.1585232187
Directory /workspace/3.uart_loopback/latest

Test location /workspace/coverage/default/3.uart_perf.2994218066
Short name T641
Test name
Test status
Simulation time 16888179276 ps
CPU time 963.66 seconds
Started Jun 07 07:19:52 PM PDT 24
Finished Jun 07 07:36:20 PM PDT 24
Peak memory 200328 kb
Host smart-4ceee1c8-be1b-432c-a42a-b13b771b17e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2994218066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.2994218066
Directory /workspace/3.uart_perf/latest

Test location /workspace/coverage/default/3.uart_rx_oversample.2464974456
Short name T461
Test name
Test status
Simulation time 7335002705 ps
CPU time 52.49 seconds
Started Jun 07 07:19:47 PM PDT 24
Finished Jun 07 07:21:04 PM PDT 24
Peak memory 198704 kb
Host smart-1f64ca6d-8621-4579-af23-856511613ba9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2464974456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.2464974456
Directory /workspace/3.uart_rx_oversample/latest

Test location /workspace/coverage/default/3.uart_rx_parity_err.3349670056
Short name T723
Test name
Test status
Simulation time 348432740785 ps
CPU time 264.31 seconds
Started Jun 07 07:19:51 PM PDT 24
Finished Jun 07 07:24:40 PM PDT 24
Peak memory 200348 kb
Host smart-d2e3f997-a2ef-4161-a4cb-57a789fa1a4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349670056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.3349670056
Directory /workspace/3.uart_rx_parity_err/latest

Test location /workspace/coverage/default/3.uart_rx_start_bit_filter.2646808787
Short name T511
Test name
Test status
Simulation time 47927850924 ps
CPU time 22.57 seconds
Started Jun 07 07:19:48 PM PDT 24
Finished Jun 07 07:20:36 PM PDT 24
Peak memory 196456 kb
Host smart-a878ce30-0030-4112-aa83-117070f04245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646808787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.2646808787
Directory /workspace/3.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/3.uart_smoke.2072627943
Short name T400
Test name
Test status
Simulation time 942948820 ps
CPU time 2.71 seconds
Started Jun 07 07:19:48 PM PDT 24
Finished Jun 07 07:20:15 PM PDT 24
Peak memory 199952 kb
Host smart-02c56a7b-ee31-484a-bb46-304f630e2c2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072627943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_smoke.2072627943
Directory /workspace/3.uart_smoke/latest

Test location /workspace/coverage/default/3.uart_tx_ovrd.4223902976
Short name T863
Test name
Test status
Simulation time 7891005372 ps
CPU time 6.9 seconds
Started Jun 07 07:19:47 PM PDT 24
Finished Jun 07 07:20:18 PM PDT 24
Peak memory 200136 kb
Host smart-c3497b0f-721e-42a3-be1c-4607781dde72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223902976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.4223902976
Directory /workspace/3.uart_tx_ovrd/latest

Test location /workspace/coverage/default/3.uart_tx_rx.14427795
Short name T477
Test name
Test status
Simulation time 90203903570 ps
CPU time 114.88 seconds
Started Jun 07 07:19:50 PM PDT 24
Finished Jun 07 07:22:09 PM PDT 24
Peak memory 200364 kb
Host smart-b98341a2-f747-42cb-b8ff-ca07ae08e974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14427795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.14427795
Directory /workspace/3.uart_tx_rx/latest

Test location /workspace/coverage/default/30.uart_alert_test.1763857232
Short name T860
Test name
Test status
Simulation time 18198912 ps
CPU time 0.57 seconds
Started Jun 07 07:23:23 PM PDT 24
Finished Jun 07 07:23:35 PM PDT 24
Peak memory 196060 kb
Host smart-9e13f24d-84a3-4aa5-b07f-694bf50d1dd7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763857232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.1763857232
Directory /workspace/30.uart_alert_test/latest

Test location /workspace/coverage/default/30.uart_fifo_full.2982624134
Short name T557
Test name
Test status
Simulation time 315124568371 ps
CPU time 102.58 seconds
Started Jun 07 07:23:16 PM PDT 24
Finished Jun 07 07:25:11 PM PDT 24
Peak memory 200256 kb
Host smart-e9ce1113-da2d-45bb-bfb2-0f0a0fafac77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982624134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.2982624134
Directory /workspace/30.uart_fifo_full/latest

Test location /workspace/coverage/default/30.uart_fifo_overflow.1683684807
Short name T561
Test name
Test status
Simulation time 128673032971 ps
CPU time 176.94 seconds
Started Jun 07 07:23:14 PM PDT 24
Finished Jun 07 07:26:24 PM PDT 24
Peak memory 200372 kb
Host smart-3a61cbf4-f055-41d6-ac36-0e6637a19741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683684807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.1683684807
Directory /workspace/30.uart_fifo_overflow/latest

Test location /workspace/coverage/default/30.uart_fifo_reset.819394081
Short name T132
Test name
Test status
Simulation time 85015630883 ps
CPU time 70.43 seconds
Started Jun 07 07:23:16 PM PDT 24
Finished Jun 07 07:24:39 PM PDT 24
Peak memory 200340 kb
Host smart-75963b47-b638-4445-b70b-062163e4db42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819394081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.819394081
Directory /workspace/30.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_intr.4157964840
Short name T985
Test name
Test status
Simulation time 28072271514 ps
CPU time 50.64 seconds
Started Jun 07 07:23:18 PM PDT 24
Finished Jun 07 07:24:20 PM PDT 24
Peak memory 200328 kb
Host smart-e0cb6436-ded1-405b-a068-559d41f353ca
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157964840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.4157964840
Directory /workspace/30.uart_intr/latest

Test location /workspace/coverage/default/30.uart_long_xfer_wo_dly.1434701881
Short name T686
Test name
Test status
Simulation time 307554974890 ps
CPU time 171.81 seconds
Started Jun 07 07:23:25 PM PDT 24
Finished Jun 07 07:26:27 PM PDT 24
Peak memory 200460 kb
Host smart-027fbed5-8d9d-4133-8fdc-cee6154aa8d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1434701881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.1434701881
Directory /workspace/30.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/30.uart_loopback.2401986068
Short name T583
Test name
Test status
Simulation time 7976508252 ps
CPU time 19.52 seconds
Started Jun 07 07:23:24 PM PDT 24
Finished Jun 07 07:23:54 PM PDT 24
Peak memory 199540 kb
Host smart-47750d5a-c083-4e87-822b-60a30d40ab7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401986068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_loopback.2401986068
Directory /workspace/30.uart_loopback/latest

Test location /workspace/coverage/default/30.uart_perf.4231244906
Short name T424
Test name
Test status
Simulation time 9576628442 ps
CPU time 212.11 seconds
Started Jun 07 07:23:25 PM PDT 24
Finished Jun 07 07:27:07 PM PDT 24
Peak memory 200356 kb
Host smart-c9fc15e7-d347-4bd2-b77d-586f5750d71f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4231244906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.4231244906
Directory /workspace/30.uart_perf/latest

Test location /workspace/coverage/default/30.uart_rx_oversample.431510790
Short name T612
Test name
Test status
Simulation time 5676985879 ps
CPU time 12.73 seconds
Started Jun 07 07:23:17 PM PDT 24
Finished Jun 07 07:23:42 PM PDT 24
Peak memory 198568 kb
Host smart-ba64ebe9-fde1-4282-8ac5-8989043e67f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=431510790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.431510790
Directory /workspace/30.uart_rx_oversample/latest

Test location /workspace/coverage/default/30.uart_rx_parity_err.3002889506
Short name T25
Test name
Test status
Simulation time 19147118213 ps
CPU time 27.89 seconds
Started Jun 07 07:23:27 PM PDT 24
Finished Jun 07 07:24:05 PM PDT 24
Peak memory 200336 kb
Host smart-6308f51e-2ab8-405f-83f9-c3708fd60c46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002889506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.3002889506
Directory /workspace/30.uart_rx_parity_err/latest

Test location /workspace/coverage/default/30.uart_rx_start_bit_filter.2958394130
Short name T316
Test name
Test status
Simulation time 2146477714 ps
CPU time 1.48 seconds
Started Jun 07 07:23:18 PM PDT 24
Finished Jun 07 07:23:32 PM PDT 24
Peak memory 195968 kb
Host smart-215b64a0-a1d1-4481-a0a9-a4ce10e90af2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958394130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.2958394130
Directory /workspace/30.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/30.uart_smoke.3098169890
Short name T598
Test name
Test status
Simulation time 290544670 ps
CPU time 1.03 seconds
Started Jun 07 07:23:14 PM PDT 24
Finished Jun 07 07:23:28 PM PDT 24
Peak memory 199552 kb
Host smart-5afd2979-a852-4bc1-8b5c-411aa2c286d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098169890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_smoke.3098169890
Directory /workspace/30.uart_smoke/latest

Test location /workspace/coverage/default/30.uart_stress_all.1820880942
Short name T744
Test name
Test status
Simulation time 603361152911 ps
CPU time 651.98 seconds
Started Jun 07 07:23:23 PM PDT 24
Finished Jun 07 07:34:26 PM PDT 24
Peak memory 200200 kb
Host smart-c5f0367b-6056-4be6-8bb7-9ddbabb50fc2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820880942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.1820880942
Directory /workspace/30.uart_stress_all/latest

Test location /workspace/coverage/default/30.uart_stress_all_with_rand_reset.361052447
Short name T648
Test name
Test status
Simulation time 46708744148 ps
CPU time 96.2 seconds
Started Jun 07 07:23:24 PM PDT 24
Finished Jun 07 07:25:10 PM PDT 24
Peak memory 208628 kb
Host smart-ef6275eb-d434-4dc9-aee2-dcee4605d609
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361052447 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 30.uart_stress_all_with_rand_reset.361052447
Directory /workspace/30.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.uart_tx_ovrd.1545127505
Short name T581
Test name
Test status
Simulation time 6876917513 ps
CPU time 18.01 seconds
Started Jun 07 07:23:23 PM PDT 24
Finished Jun 07 07:23:52 PM PDT 24
Peak memory 200248 kb
Host smart-765e7b75-4d91-4ef5-b92b-d56d352a1397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545127505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.1545127505
Directory /workspace/30.uart_tx_ovrd/latest

Test location /workspace/coverage/default/30.uart_tx_rx.3264070216
Short name T266
Test name
Test status
Simulation time 13032654786 ps
CPU time 6.71 seconds
Started Jun 07 07:23:13 PM PDT 24
Finished Jun 07 07:23:33 PM PDT 24
Peak memory 200344 kb
Host smart-826fce47-df7a-4b0f-ab6c-df4e4c0b6b3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264070216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.3264070216
Directory /workspace/30.uart_tx_rx/latest

Test location /workspace/coverage/default/31.uart_alert_test.2981574791
Short name T563
Test name
Test status
Simulation time 18940843 ps
CPU time 0.57 seconds
Started Jun 07 07:23:41 PM PDT 24
Finished Jun 07 07:23:50 PM PDT 24
Peak memory 195792 kb
Host smart-d4c41b50-c9e2-4c6c-b915-ef15d813d881
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981574791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.2981574791
Directory /workspace/31.uart_alert_test/latest

Test location /workspace/coverage/default/31.uart_fifo_full.2581564286
Short name T175
Test name
Test status
Simulation time 93184474073 ps
CPU time 33.61 seconds
Started Jun 07 07:23:23 PM PDT 24
Finished Jun 07 07:24:08 PM PDT 24
Peak memory 200348 kb
Host smart-d446deba-d727-464c-82ed-093e975a5c10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581564286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.2581564286
Directory /workspace/31.uart_fifo_full/latest

Test location /workspace/coverage/default/31.uart_fifo_overflow.2141288175
Short name T809
Test name
Test status
Simulation time 60851209256 ps
CPU time 105.17 seconds
Started Jun 07 07:23:31 PM PDT 24
Finished Jun 07 07:25:24 PM PDT 24
Peak memory 200344 kb
Host smart-9ddbaf4d-ae7a-46ba-9be3-2de5d87a6323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141288175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.2141288175
Directory /workspace/31.uart_fifo_overflow/latest

Test location /workspace/coverage/default/31.uart_fifo_reset.652627656
Short name T871
Test name
Test status
Simulation time 39399742079 ps
CPU time 19.76 seconds
Started Jun 07 07:23:34 PM PDT 24
Finished Jun 07 07:24:01 PM PDT 24
Peak memory 200420 kb
Host smart-26dee8a0-cd51-415c-a701-5cf8a5ba0b22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652627656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.652627656
Directory /workspace/31.uart_fifo_reset/latest

Test location /workspace/coverage/default/31.uart_intr.2547907165
Short name T907
Test name
Test status
Simulation time 42748794004 ps
CPU time 70.84 seconds
Started Jun 07 07:23:32 PM PDT 24
Finished Jun 07 07:24:51 PM PDT 24
Peak memory 200396 kb
Host smart-8de0e397-e9af-477e-9e29-170e677f5fef
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547907165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.2547907165
Directory /workspace/31.uart_intr/latest

Test location /workspace/coverage/default/31.uart_long_xfer_wo_dly.331233600
Short name T1067
Test name
Test status
Simulation time 70592796164 ps
CPU time 224.9 seconds
Started Jun 07 07:23:42 PM PDT 24
Finished Jun 07 07:27:36 PM PDT 24
Peak memory 200304 kb
Host smart-33698f02-b791-4d00-9dbd-3ce93bac38bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=331233600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.331233600
Directory /workspace/31.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/31.uart_loopback.1192307173
Short name T421
Test name
Test status
Simulation time 2558320088 ps
CPU time 6.69 seconds
Started Jun 07 07:23:33 PM PDT 24
Finished Jun 07 07:23:48 PM PDT 24
Peak memory 199216 kb
Host smart-f5aedcc9-7d10-4a0f-bc5e-729baf4dcd81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192307173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_loopback.1192307173
Directory /workspace/31.uart_loopback/latest

Test location /workspace/coverage/default/31.uart_perf.2322650456
Short name T577
Test name
Test status
Simulation time 7832954322 ps
CPU time 331.21 seconds
Started Jun 07 07:23:40 PM PDT 24
Finished Jun 07 07:29:20 PM PDT 24
Peak memory 200268 kb
Host smart-b390bb38-e9e2-4e64-91c4-b840b6e1cad1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2322650456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.2322650456
Directory /workspace/31.uart_perf/latest

Test location /workspace/coverage/default/31.uart_rx_oversample.569726687
Short name T818
Test name
Test status
Simulation time 6494446650 ps
CPU time 58.87 seconds
Started Jun 07 07:23:31 PM PDT 24
Finished Jun 07 07:24:38 PM PDT 24
Peak memory 198612 kb
Host smart-12ffa02b-cd20-4a3d-a91b-1f2062be4b24
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=569726687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.569726687
Directory /workspace/31.uart_rx_oversample/latest

Test location /workspace/coverage/default/31.uart_rx_parity_err.1162467878
Short name T556
Test name
Test status
Simulation time 79601683814 ps
CPU time 122.7 seconds
Started Jun 07 07:23:31 PM PDT 24
Finished Jun 07 07:25:42 PM PDT 24
Peak memory 200284 kb
Host smart-2c4d5478-0e89-43e5-b664-79b2a297e7ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162467878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.1162467878
Directory /workspace/31.uart_rx_parity_err/latest

Test location /workspace/coverage/default/31.uart_rx_start_bit_filter.2954347500
Short name T911
Test name
Test status
Simulation time 607811388 ps
CPU time 0.93 seconds
Started Jun 07 07:23:29 PM PDT 24
Finished Jun 07 07:23:39 PM PDT 24
Peak memory 196012 kb
Host smart-3a1b183a-7414-48d5-bff3-c832dca63c9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954347500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.2954347500
Directory /workspace/31.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/31.uart_smoke.3043784198
Short name T942
Test name
Test status
Simulation time 490528455 ps
CPU time 2.04 seconds
Started Jun 07 07:23:25 PM PDT 24
Finished Jun 07 07:23:37 PM PDT 24
Peak memory 198604 kb
Host smart-68f884ea-8eb2-4f9d-8148-a5f3ae51052b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043784198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_smoke.3043784198
Directory /workspace/31.uart_smoke/latest

Test location /workspace/coverage/default/31.uart_stress_all.2958832694
Short name T1082
Test name
Test status
Simulation time 176444726774 ps
CPU time 175.32 seconds
Started Jun 07 07:23:40 PM PDT 24
Finished Jun 07 07:26:45 PM PDT 24
Peak memory 200348 kb
Host smart-b60aae56-0da8-4c4a-8f03-c57cad4b2b23
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958832694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.2958832694
Directory /workspace/31.uart_stress_all/latest

Test location /workspace/coverage/default/31.uart_tx_ovrd.2100612034
Short name T329
Test name
Test status
Simulation time 2231993380 ps
CPU time 2.47 seconds
Started Jun 07 07:23:32 PM PDT 24
Finished Jun 07 07:23:42 PM PDT 24
Peak memory 199256 kb
Host smart-9838b47d-8f26-451e-879b-3e893a40b4ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100612034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.2100612034
Directory /workspace/31.uart_tx_ovrd/latest

Test location /workspace/coverage/default/31.uart_tx_rx.2938340700
Short name T1072
Test name
Test status
Simulation time 11290817005 ps
CPU time 18.77 seconds
Started Jun 07 07:23:25 PM PDT 24
Finished Jun 07 07:23:54 PM PDT 24
Peak memory 200432 kb
Host smart-ab7039dd-6d93-4267-83ce-064d424a425b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938340700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.2938340700
Directory /workspace/31.uart_tx_rx/latest

Test location /workspace/coverage/default/32.uart_alert_test.4196214491
Short name T418
Test name
Test status
Simulation time 29893738 ps
CPU time 0.58 seconds
Started Jun 07 07:23:49 PM PDT 24
Finished Jun 07 07:23:59 PM PDT 24
Peak memory 195760 kb
Host smart-edac6881-87bf-4d7f-81d7-5e91d0858e9e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196214491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.4196214491
Directory /workspace/32.uart_alert_test/latest

Test location /workspace/coverage/default/32.uart_fifo_full.84705422
Short name T810
Test name
Test status
Simulation time 142946782260 ps
CPU time 51.41 seconds
Started Jun 07 07:23:42 PM PDT 24
Finished Jun 07 07:24:43 PM PDT 24
Peak memory 200400 kb
Host smart-879a40c8-fac3-407e-8f15-8d1515caf65a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84705422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.84705422
Directory /workspace/32.uart_fifo_full/latest

Test location /workspace/coverage/default/32.uart_fifo_overflow.1308859059
Short name T509
Test name
Test status
Simulation time 106936865287 ps
CPU time 31.03 seconds
Started Jun 07 07:23:41 PM PDT 24
Finished Jun 07 07:24:21 PM PDT 24
Peak memory 200352 kb
Host smart-42c51dbd-34b3-4c57-8c82-d773df4546f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308859059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.1308859059
Directory /workspace/32.uart_fifo_overflow/latest

Test location /workspace/coverage/default/32.uart_fifo_reset.1806006875
Short name T1010
Test name
Test status
Simulation time 21760060809 ps
CPU time 19.96 seconds
Started Jun 07 07:23:41 PM PDT 24
Finished Jun 07 07:24:10 PM PDT 24
Peak memory 200368 kb
Host smart-82ffe626-fee3-42d3-91f2-4b3bcf03b5df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806006875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.1806006875
Directory /workspace/32.uart_fifo_reset/latest

Test location /workspace/coverage/default/32.uart_intr.1099348265
Short name T520
Test name
Test status
Simulation time 68995134168 ps
CPU time 34 seconds
Started Jun 07 07:23:41 PM PDT 24
Finished Jun 07 07:24:24 PM PDT 24
Peak memory 200264 kb
Host smart-0ef038a5-5435-4514-933c-2f2f70de33bf
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099348265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.1099348265
Directory /workspace/32.uart_intr/latest

Test location /workspace/coverage/default/32.uart_long_xfer_wo_dly.2145977654
Short name T822
Test name
Test status
Simulation time 58583022358 ps
CPU time 219.22 seconds
Started Jun 07 07:23:41 PM PDT 24
Finished Jun 07 07:27:29 PM PDT 24
Peak memory 200296 kb
Host smart-4e10a9c0-a124-44ae-9909-0d2cd2a3476c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2145977654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.2145977654
Directory /workspace/32.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/32.uart_loopback.87841693
Short name T44
Test name
Test status
Simulation time 3089539271 ps
CPU time 3.18 seconds
Started Jun 07 07:23:42 PM PDT 24
Finished Jun 07 07:23:55 PM PDT 24
Peak memory 199704 kb
Host smart-5390ec1d-51b3-4af3-af27-0ee75cce7cd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87841693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_loopback.87841693
Directory /workspace/32.uart_loopback/latest

Test location /workspace/coverage/default/32.uart_perf.1985592125
Short name T267
Test name
Test status
Simulation time 10480034857 ps
CPU time 577.26 seconds
Started Jun 07 07:23:40 PM PDT 24
Finished Jun 07 07:33:25 PM PDT 24
Peak memory 200152 kb
Host smart-4e3a238d-812c-4286-9ba6-00878bcc8849
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1985592125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.1985592125
Directory /workspace/32.uart_perf/latest

Test location /workspace/coverage/default/32.uart_rx_oversample.190528555
Short name T11
Test name
Test status
Simulation time 5281547452 ps
CPU time 40.61 seconds
Started Jun 07 07:23:42 PM PDT 24
Finished Jun 07 07:24:32 PM PDT 24
Peak memory 199148 kb
Host smart-a4ac69db-4cda-4bb0-ad9d-f9eda3de58fd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=190528555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.190528555
Directory /workspace/32.uart_rx_oversample/latest

Test location /workspace/coverage/default/32.uart_rx_parity_err.4038130222
Short name T156
Test name
Test status
Simulation time 52385792174 ps
CPU time 25.06 seconds
Started Jun 07 07:23:41 PM PDT 24
Finished Jun 07 07:24:15 PM PDT 24
Peak memory 200332 kb
Host smart-e7f9b261-a155-49d4-96a6-3bd034a88107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038130222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.4038130222
Directory /workspace/32.uart_rx_parity_err/latest

Test location /workspace/coverage/default/32.uart_rx_start_bit_filter.816280997
Short name T622
Test name
Test status
Simulation time 639287799 ps
CPU time 1.12 seconds
Started Jun 07 07:23:42 PM PDT 24
Finished Jun 07 07:23:52 PM PDT 24
Peak memory 195968 kb
Host smart-69835b2d-25d4-49ff-9598-e9ab32cee6d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816280997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.816280997
Directory /workspace/32.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/32.uart_smoke.513426244
Short name T921
Test name
Test status
Simulation time 462136671 ps
CPU time 1.34 seconds
Started Jun 07 07:23:41 PM PDT 24
Finished Jun 07 07:23:51 PM PDT 24
Peak memory 200204 kb
Host smart-76594ff4-9ae9-4c79-87b5-ce2024d46c26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513426244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_smoke.513426244
Directory /workspace/32.uart_smoke/latest

Test location /workspace/coverage/default/32.uart_stress_all_with_rand_reset.1955341100
Short name T826
Test name
Test status
Simulation time 136780543263 ps
CPU time 636.22 seconds
Started Jun 07 07:23:41 PM PDT 24
Finished Jun 07 07:34:26 PM PDT 24
Peak memory 216948 kb
Host smart-6c030c02-998b-421f-abb9-d56f27bb6714
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955341100 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 32.uart_stress_all_with_rand_reset.1955341100
Directory /workspace/32.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.uart_tx_ovrd.3897552727
Short name T1044
Test name
Test status
Simulation time 736706924 ps
CPU time 2.99 seconds
Started Jun 07 07:23:43 PM PDT 24
Finished Jun 07 07:23:55 PM PDT 24
Peak memory 200276 kb
Host smart-8fa03e78-1594-4ffc-bbc2-2132942332f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897552727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.3897552727
Directory /workspace/32.uart_tx_ovrd/latest

Test location /workspace/coverage/default/32.uart_tx_rx.3054420966
Short name T990
Test name
Test status
Simulation time 128175052996 ps
CPU time 52.02 seconds
Started Jun 07 07:23:41 PM PDT 24
Finished Jun 07 07:24:43 PM PDT 24
Peak memory 200320 kb
Host smart-cfc52587-a2ca-4f17-985c-38f31a31fc5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054420966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.3054420966
Directory /workspace/32.uart_tx_rx/latest

Test location /workspace/coverage/default/33.uart_alert_test.872015498
Short name T773
Test name
Test status
Simulation time 34448222 ps
CPU time 0.54 seconds
Started Jun 07 07:23:57 PM PDT 24
Finished Jun 07 07:24:05 PM PDT 24
Peak memory 195772 kb
Host smart-9081414d-4ddb-4ebc-afb8-25a47db0150c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872015498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.872015498
Directory /workspace/33.uart_alert_test/latest

Test location /workspace/coverage/default/33.uart_fifo_overflow.707929850
Short name T793
Test name
Test status
Simulation time 130103563999 ps
CPU time 22.62 seconds
Started Jun 07 07:23:48 PM PDT 24
Finished Jun 07 07:24:20 PM PDT 24
Peak memory 200224 kb
Host smart-6814a357-89e7-4d79-be70-ffebebb84d3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707929850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.707929850
Directory /workspace/33.uart_fifo_overflow/latest

Test location /workspace/coverage/default/33.uart_intr.4041880702
Short name T120
Test name
Test status
Simulation time 53622229190 ps
CPU time 19.22 seconds
Started Jun 07 07:23:50 PM PDT 24
Finished Jun 07 07:24:18 PM PDT 24
Peak memory 200412 kb
Host smart-a2c3bf87-011a-4fa1-bb31-7f8b3fcae1b9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041880702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.4041880702
Directory /workspace/33.uart_intr/latest

Test location /workspace/coverage/default/33.uart_loopback.217856703
Short name T934
Test name
Test status
Simulation time 2930424292 ps
CPU time 5.26 seconds
Started Jun 07 07:23:49 PM PDT 24
Finished Jun 07 07:24:04 PM PDT 24
Peak memory 198164 kb
Host smart-b424248f-852c-4b16-b4e4-a34ee8249904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217856703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_loopback.217856703
Directory /workspace/33.uart_loopback/latest

Test location /workspace/coverage/default/33.uart_perf.3869129006
Short name T43
Test name
Test status
Simulation time 23312741866 ps
CPU time 1375.3 seconds
Started Jun 07 07:23:50 PM PDT 24
Finished Jun 07 07:46:55 PM PDT 24
Peak memory 200392 kb
Host smart-558719e0-dd43-40ae-858b-f723078ec95c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3869129006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.3869129006
Directory /workspace/33.uart_perf/latest

Test location /workspace/coverage/default/33.uart_rx_oversample.372989259
Short name T26
Test name
Test status
Simulation time 1594140097 ps
CPU time 9.33 seconds
Started Jun 07 07:23:51 PM PDT 24
Finished Jun 07 07:24:09 PM PDT 24
Peak memory 199616 kb
Host smart-36668662-2107-4ead-816f-1dfda1c03aa5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=372989259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.372989259
Directory /workspace/33.uart_rx_oversample/latest

Test location /workspace/coverage/default/33.uart_rx_parity_err.3014810882
Short name T143
Test name
Test status
Simulation time 81712843109 ps
CPU time 36.32 seconds
Started Jun 07 07:23:49 PM PDT 24
Finished Jun 07 07:24:35 PM PDT 24
Peak memory 200408 kb
Host smart-37199a6f-2cd4-4cc0-aab3-07811d184a2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014810882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.3014810882
Directory /workspace/33.uart_rx_parity_err/latest

Test location /workspace/coverage/default/33.uart_rx_start_bit_filter.3651557849
Short name T640
Test name
Test status
Simulation time 36689084627 ps
CPU time 14.83 seconds
Started Jun 07 07:23:47 PM PDT 24
Finished Jun 07 07:24:12 PM PDT 24
Peak memory 196464 kb
Host smart-77990fd2-3f05-48a6-ae10-5ef7282bb2e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651557849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.3651557849
Directory /workspace/33.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/33.uart_smoke.1159109033
Short name T779
Test name
Test status
Simulation time 5313948036 ps
CPU time 20.99 seconds
Started Jun 07 07:23:49 PM PDT 24
Finished Jun 07 07:24:19 PM PDT 24
Peak memory 200104 kb
Host smart-57d4fd34-b01f-44c5-9380-eda0263b2e74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159109033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_smoke.1159109033
Directory /workspace/33.uart_smoke/latest

Test location /workspace/coverage/default/33.uart_tx_ovrd.2431365129
Short name T928
Test name
Test status
Simulation time 7158466314 ps
CPU time 12.24 seconds
Started Jun 07 07:23:50 PM PDT 24
Finished Jun 07 07:24:11 PM PDT 24
Peak memory 200404 kb
Host smart-a24a3fb0-98e2-4786-80f7-15b0e456509b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431365129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.2431365129
Directory /workspace/33.uart_tx_ovrd/latest

Test location /workspace/coverage/default/33.uart_tx_rx.3448331440
Short name T812
Test name
Test status
Simulation time 46597843027 ps
CPU time 81.13 seconds
Started Jun 07 07:23:48 PM PDT 24
Finished Jun 07 07:25:19 PM PDT 24
Peak memory 200308 kb
Host smart-9ef3cf49-1023-4730-9c4c-8eb83100e354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448331440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.3448331440
Directory /workspace/33.uart_tx_rx/latest

Test location /workspace/coverage/default/34.uart_alert_test.3367614086
Short name T923
Test name
Test status
Simulation time 26160538 ps
CPU time 0.57 seconds
Started Jun 07 07:24:05 PM PDT 24
Finished Jun 07 07:24:11 PM PDT 24
Peak memory 195772 kb
Host smart-8d224c61-aef9-43a6-82cf-73dce8b96df2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367614086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.3367614086
Directory /workspace/34.uart_alert_test/latest

Test location /workspace/coverage/default/34.uart_fifo_full.1119207671
Short name T870
Test name
Test status
Simulation time 55118195005 ps
CPU time 87.74 seconds
Started Jun 07 07:24:00 PM PDT 24
Finished Jun 07 07:25:34 PM PDT 24
Peak memory 200340 kb
Host smart-cbbb326a-795e-45bc-a457-56daacc3fa27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119207671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.1119207671
Directory /workspace/34.uart_fifo_full/latest

Test location /workspace/coverage/default/34.uart_fifo_overflow.3087338560
Short name T480
Test name
Test status
Simulation time 24307819601 ps
CPU time 47.12 seconds
Started Jun 07 07:23:57 PM PDT 24
Finished Jun 07 07:24:51 PM PDT 24
Peak memory 200348 kb
Host smart-c46e6142-70b2-48d2-821f-5e71f35cc5a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087338560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.3087338560
Directory /workspace/34.uart_fifo_overflow/latest

Test location /workspace/coverage/default/34.uart_fifo_reset.2845799747
Short name T248
Test name
Test status
Simulation time 25461429668 ps
CPU time 11.29 seconds
Started Jun 07 07:23:57 PM PDT 24
Finished Jun 07 07:24:16 PM PDT 24
Peak memory 200280 kb
Host smart-f6e27c59-d250-4602-b60f-b3244bf5c4f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845799747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.2845799747
Directory /workspace/34.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_intr.1539933350
Short name T121
Test name
Test status
Simulation time 108896588929 ps
CPU time 98.03 seconds
Started Jun 07 07:23:58 PM PDT 24
Finished Jun 07 07:25:43 PM PDT 24
Peak memory 200260 kb
Host smart-01daa71b-eadb-4489-8930-6fa728c398bd
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539933350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.1539933350
Directory /workspace/34.uart_intr/latest

Test location /workspace/coverage/default/34.uart_long_xfer_wo_dly.1536773248
Short name T380
Test name
Test status
Simulation time 94030536479 ps
CPU time 267.74 seconds
Started Jun 07 07:24:06 PM PDT 24
Finished Jun 07 07:28:39 PM PDT 24
Peak memory 200436 kb
Host smart-7e1f8603-52c3-4057-bd5d-3bc513b113cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1536773248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.1536773248
Directory /workspace/34.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/34.uart_loopback.1654686886
Short name T905
Test name
Test status
Simulation time 11114934291 ps
CPU time 29.46 seconds
Started Jun 07 07:23:57 PM PDT 24
Finished Jun 07 07:24:34 PM PDT 24
Peak memory 199632 kb
Host smart-35b49eb4-7710-424b-8015-3c054faa3427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654686886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_loopback.1654686886
Directory /workspace/34.uart_loopback/latest

Test location /workspace/coverage/default/34.uart_perf.573739293
Short name T1054
Test name
Test status
Simulation time 15449751222 ps
CPU time 737.1 seconds
Started Jun 07 07:24:05 PM PDT 24
Finished Jun 07 07:36:27 PM PDT 24
Peak memory 200316 kb
Host smart-8bcb0e43-af67-4a19-b2bc-e001a82eb82a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=573739293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.573739293
Directory /workspace/34.uart_perf/latest

Test location /workspace/coverage/default/34.uart_rx_oversample.502504341
Short name T674
Test name
Test status
Simulation time 6236318100 ps
CPU time 14.72 seconds
Started Jun 07 07:24:00 PM PDT 24
Finished Jun 07 07:24:21 PM PDT 24
Peak memory 199580 kb
Host smart-261b5bb5-3d20-4d0a-abe1-caf1e5e6049e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=502504341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.502504341
Directory /workspace/34.uart_rx_oversample/latest

Test location /workspace/coverage/default/34.uart_rx_parity_err.2752752821
Short name T661
Test name
Test status
Simulation time 76490811661 ps
CPU time 134.76 seconds
Started Jun 07 07:23:56 PM PDT 24
Finished Jun 07 07:26:18 PM PDT 24
Peak memory 200156 kb
Host smart-a8b894e9-e296-44a3-a1d4-3a7684eb5a5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752752821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.2752752821
Directory /workspace/34.uart_rx_parity_err/latest

Test location /workspace/coverage/default/34.uart_rx_start_bit_filter.4077173271
Short name T358
Test name
Test status
Simulation time 33424038227 ps
CPU time 14.26 seconds
Started Jun 07 07:24:00 PM PDT 24
Finished Jun 07 07:24:20 PM PDT 24
Peak memory 196436 kb
Host smart-4253000f-ef39-4ba5-9f61-1a7732425303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077173271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.4077173271
Directory /workspace/34.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/34.uart_smoke.1649080849
Short name T507
Test name
Test status
Simulation time 5640496234 ps
CPU time 11.05 seconds
Started Jun 07 07:23:56 PM PDT 24
Finished Jun 07 07:24:15 PM PDT 24
Peak memory 199428 kb
Host smart-b9338873-c977-4baf-a595-2c2622228486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649080849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_smoke.1649080849
Directory /workspace/34.uart_smoke/latest

Test location /workspace/coverage/default/34.uart_stress_all.295957597
Short name T306
Test name
Test status
Simulation time 33058437687 ps
CPU time 15.31 seconds
Started Jun 07 07:24:05 PM PDT 24
Finished Jun 07 07:24:26 PM PDT 24
Peak memory 200332 kb
Host smart-2cdeac53-ad51-4d7e-a483-bf2751802fc1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295957597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.295957597
Directory /workspace/34.uart_stress_all/latest

Test location /workspace/coverage/default/34.uart_tx_ovrd.1163209814
Short name T524
Test name
Test status
Simulation time 734765433 ps
CPU time 2.8 seconds
Started Jun 07 07:23:56 PM PDT 24
Finished Jun 07 07:24:06 PM PDT 24
Peak memory 199208 kb
Host smart-1c6ef317-a831-42ef-85d1-a2609a43c346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163209814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.1163209814
Directory /workspace/34.uart_tx_ovrd/latest

Test location /workspace/coverage/default/34.uart_tx_rx.3511561759
Short name T498
Test name
Test status
Simulation time 8461008405 ps
CPU time 15.41 seconds
Started Jun 07 07:23:56 PM PDT 24
Finished Jun 07 07:24:19 PM PDT 24
Peak memory 200320 kb
Host smart-b177e7b8-6839-46ab-b429-55da6a2383b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511561759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.3511561759
Directory /workspace/34.uart_tx_rx/latest

Test location /workspace/coverage/default/35.uart_alert_test.2423460454
Short name T893
Test name
Test status
Simulation time 13207925 ps
CPU time 0.57 seconds
Started Jun 07 07:24:08 PM PDT 24
Finished Jun 07 07:24:14 PM PDT 24
Peak memory 195736 kb
Host smart-d74f7fe8-c2dd-4d4a-9fd8-4213b2e33a7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423460454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.2423460454
Directory /workspace/35.uart_alert_test/latest

Test location /workspace/coverage/default/35.uart_fifo_full.2815999964
Short name T529
Test name
Test status
Simulation time 150085625954 ps
CPU time 220.7 seconds
Started Jun 07 07:24:04 PM PDT 24
Finished Jun 07 07:27:50 PM PDT 24
Peak memory 200392 kb
Host smart-dab02058-fd2b-416d-83d0-805e452534f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815999964 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.2815999964
Directory /workspace/35.uart_fifo_full/latest

Test location /workspace/coverage/default/35.uart_fifo_overflow.2420261887
Short name T275
Test name
Test status
Simulation time 63210742148 ps
CPU time 26.12 seconds
Started Jun 07 07:24:08 PM PDT 24
Finished Jun 07 07:24:40 PM PDT 24
Peak memory 200060 kb
Host smart-2458e28c-4e6f-4cd7-b883-93384c7f70d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420261887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.2420261887
Directory /workspace/35.uart_fifo_overflow/latest

Test location /workspace/coverage/default/35.uart_intr.2535907570
Short name T281
Test name
Test status
Simulation time 13602110440 ps
CPU time 9.61 seconds
Started Jun 07 07:24:05 PM PDT 24
Finished Jun 07 07:24:20 PM PDT 24
Peak memory 199292 kb
Host smart-92a4d6cd-c67f-45e2-a09f-1a8bfb3760e3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535907570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.2535907570
Directory /workspace/35.uart_intr/latest

Test location /workspace/coverage/default/35.uart_long_xfer_wo_dly.1942964432
Short name T384
Test name
Test status
Simulation time 98957641496 ps
CPU time 217.22 seconds
Started Jun 07 07:24:08 PM PDT 24
Finished Jun 07 07:27:50 PM PDT 24
Peak memory 200360 kb
Host smart-13fe4cde-9aee-4b8d-a04d-4bc0b09e2278
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1942964432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.1942964432
Directory /workspace/35.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/35.uart_loopback.1837797670
Short name T356
Test name
Test status
Simulation time 13474762963 ps
CPU time 12.43 seconds
Started Jun 07 07:24:05 PM PDT 24
Finished Jun 07 07:24:22 PM PDT 24
Peak memory 200064 kb
Host smart-c82e7e4a-e3c9-4759-bf11-f413fd6c9959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837797670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_loopback.1837797670
Directory /workspace/35.uart_loopback/latest

Test location /workspace/coverage/default/35.uart_noise_filter.2500464618
Short name T130
Test name
Test status
Simulation time 43168639179 ps
CPU time 71.12 seconds
Started Jun 07 07:24:10 PM PDT 24
Finished Jun 07 07:25:27 PM PDT 24
Peak memory 200400 kb
Host smart-68738648-2dd6-4ccf-abec-aa7c70c4d928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500464618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_noise_filter.2500464618
Directory /workspace/35.uart_noise_filter/latest

Test location /workspace/coverage/default/35.uart_perf.2715691758
Short name T321
Test name
Test status
Simulation time 16059057274 ps
CPU time 894.5 seconds
Started Jun 07 07:24:08 PM PDT 24
Finished Jun 07 07:39:08 PM PDT 24
Peak memory 200340 kb
Host smart-9309f810-bd95-44f8-aa78-104b448ed36a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2715691758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.2715691758
Directory /workspace/35.uart_perf/latest

Test location /workspace/coverage/default/35.uart_rx_oversample.3607458690
Short name T975
Test name
Test status
Simulation time 2390171270 ps
CPU time 9.11 seconds
Started Jun 07 07:24:06 PM PDT 24
Finished Jun 07 07:24:20 PM PDT 24
Peak memory 198376 kb
Host smart-6e1e80f6-c0ed-40e6-af37-2684b1e0c017
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3607458690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.3607458690
Directory /workspace/35.uart_rx_oversample/latest

Test location /workspace/coverage/default/35.uart_rx_parity_err.3971504504
Short name T570
Test name
Test status
Simulation time 150526225538 ps
CPU time 144.91 seconds
Started Jun 07 07:24:07 PM PDT 24
Finished Jun 07 07:26:37 PM PDT 24
Peak memory 200376 kb
Host smart-6bd207a6-0f54-438d-b59c-5dd14730fb6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971504504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.3971504504
Directory /workspace/35.uart_rx_parity_err/latest

Test location /workspace/coverage/default/35.uart_rx_start_bit_filter.1206866351
Short name T495
Test name
Test status
Simulation time 3594047924 ps
CPU time 5.55 seconds
Started Jun 07 07:24:06 PM PDT 24
Finished Jun 07 07:24:16 PM PDT 24
Peak memory 197184 kb
Host smart-a94828b0-353a-4d86-844b-f92eb5c2c345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206866351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.1206866351
Directory /workspace/35.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/35.uart_smoke.1177490835
Short name T1083
Test name
Test status
Simulation time 5812804599 ps
CPU time 6.89 seconds
Started Jun 07 07:24:03 PM PDT 24
Finished Jun 07 07:24:15 PM PDT 24
Peak memory 200408 kb
Host smart-f945675f-3ebc-4295-9392-61401ba7503c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177490835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_smoke.1177490835
Directory /workspace/35.uart_smoke/latest

Test location /workspace/coverage/default/35.uart_stress_all.3157039826
Short name T1025
Test name
Test status
Simulation time 463181443736 ps
CPU time 1759.03 seconds
Started Jun 07 07:24:08 PM PDT 24
Finished Jun 07 07:53:33 PM PDT 24
Peak memory 200420 kb
Host smart-0ef0a32e-c0e4-4e25-9f3d-033e4a10d521
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157039826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.3157039826
Directory /workspace/35.uart_stress_all/latest

Test location /workspace/coverage/default/35.uart_stress_all_with_rand_reset.1208886081
Short name T104
Test name
Test status
Simulation time 42142964892 ps
CPU time 307.46 seconds
Started Jun 07 07:24:07 PM PDT 24
Finished Jun 07 07:29:20 PM PDT 24
Peak memory 216380 kb
Host smart-b62cf3a3-6079-4c8b-984c-742d8d399199
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208886081 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 35.uart_stress_all_with_rand_reset.1208886081
Directory /workspace/35.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.uart_tx_ovrd.4038776924
Short name T1047
Test name
Test status
Simulation time 1258004536 ps
CPU time 3.01 seconds
Started Jun 07 07:24:10 PM PDT 24
Finished Jun 07 07:24:19 PM PDT 24
Peak memory 199168 kb
Host smart-02eadbe7-e639-40c9-9719-010287780234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038776924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.4038776924
Directory /workspace/35.uart_tx_ovrd/latest

Test location /workspace/coverage/default/35.uart_tx_rx.132165834
Short name T959
Test name
Test status
Simulation time 2084588689 ps
CPU time 3.81 seconds
Started Jun 07 07:24:04 PM PDT 24
Finished Jun 07 07:24:13 PM PDT 24
Peak memory 197416 kb
Host smart-33c09e2a-7516-4ca1-b969-f8381d33adc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132165834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.132165834
Directory /workspace/35.uart_tx_rx/latest

Test location /workspace/coverage/default/36.uart_alert_test.3993226239
Short name T363
Test name
Test status
Simulation time 13825242 ps
CPU time 0.56 seconds
Started Jun 07 07:24:13 PM PDT 24
Finished Jun 07 07:24:19 PM PDT 24
Peak memory 195816 kb
Host smart-9913c6b3-f43e-447b-8ac1-dc781076d54c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993226239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.3993226239
Directory /workspace/36.uart_alert_test/latest

Test location /workspace/coverage/default/36.uart_fifo_full.2709036726
Short name T634
Test name
Test status
Simulation time 260325543324 ps
CPU time 95.73 seconds
Started Jun 07 07:24:08 PM PDT 24
Finished Jun 07 07:25:49 PM PDT 24
Peak memory 200388 kb
Host smart-0115fb2e-d6bf-4bb4-99c2-3b2536c5e235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709036726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.2709036726
Directory /workspace/36.uart_fifo_full/latest

Test location /workspace/coverage/default/36.uart_fifo_overflow.3555047732
Short name T435
Test name
Test status
Simulation time 22660779053 ps
CPU time 11.23 seconds
Started Jun 07 07:24:07 PM PDT 24
Finished Jun 07 07:24:24 PM PDT 24
Peak memory 199816 kb
Host smart-21618a62-48d5-494c-abe5-1df72bf10376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555047732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.3555047732
Directory /workspace/36.uart_fifo_overflow/latest

Test location /workspace/coverage/default/36.uart_fifo_reset.2486308846
Short name T724
Test name
Test status
Simulation time 23651818981 ps
CPU time 10.19 seconds
Started Jun 07 07:24:08 PM PDT 24
Finished Jun 07 07:24:24 PM PDT 24
Peak memory 200152 kb
Host smart-4db63b11-e4df-439a-b470-e766a8778ea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486308846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.2486308846
Directory /workspace/36.uart_fifo_reset/latest

Test location /workspace/coverage/default/36.uart_intr.3144303777
Short name T736
Test name
Test status
Simulation time 30263012034 ps
CPU time 26.19 seconds
Started Jun 07 07:24:13 PM PDT 24
Finished Jun 07 07:24:45 PM PDT 24
Peak memory 200392 kb
Host smart-bd8efafe-b684-4b96-bd27-835c5ea429d9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144303777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.3144303777
Directory /workspace/36.uart_intr/latest

Test location /workspace/coverage/default/36.uart_long_xfer_wo_dly.457975993
Short name T494
Test name
Test status
Simulation time 96154162365 ps
CPU time 426.17 seconds
Started Jun 07 07:24:15 PM PDT 24
Finished Jun 07 07:31:27 PM PDT 24
Peak memory 200436 kb
Host smart-66d8f60e-c6f6-4ec4-baa8-2dd12a6af812
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=457975993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.457975993
Directory /workspace/36.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/36.uart_loopback.588212348
Short name T1076
Test name
Test status
Simulation time 1370801913 ps
CPU time 3.63 seconds
Started Jun 07 07:24:15 PM PDT 24
Finished Jun 07 07:24:25 PM PDT 24
Peak memory 199060 kb
Host smart-31aa5a1c-5e0a-4e82-baff-d76b2c74489f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588212348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_loopback.588212348
Directory /workspace/36.uart_loopback/latest

Test location /workspace/coverage/default/36.uart_perf.1770742239
Short name T1084
Test name
Test status
Simulation time 1871111751 ps
CPU time 119.5 seconds
Started Jun 07 07:24:13 PM PDT 24
Finished Jun 07 07:26:18 PM PDT 24
Peak memory 200072 kb
Host smart-51469a07-08ef-4948-8c6f-8d96f5b82126
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1770742239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.1770742239
Directory /workspace/36.uart_perf/latest

Test location /workspace/coverage/default/36.uart_rx_oversample.283040410
Short name T865
Test name
Test status
Simulation time 4338462232 ps
CPU time 36.16 seconds
Started Jun 07 07:24:12 PM PDT 24
Finished Jun 07 07:24:54 PM PDT 24
Peak memory 199120 kb
Host smart-bd52df09-98e0-4dc0-82d8-9cb03f108413
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=283040410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.283040410
Directory /workspace/36.uart_rx_oversample/latest

Test location /workspace/coverage/default/36.uart_rx_parity_err.1073621233
Short name T311
Test name
Test status
Simulation time 85895374784 ps
CPU time 15.11 seconds
Started Jun 07 07:24:14 PM PDT 24
Finished Jun 07 07:24:35 PM PDT 24
Peak memory 199944 kb
Host smart-34ecb79e-6638-44d9-9f76-df6c378ef599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073621233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.1073621233
Directory /workspace/36.uart_rx_parity_err/latest

Test location /workspace/coverage/default/36.uart_rx_start_bit_filter.1945584214
Short name T1024
Test name
Test status
Simulation time 34782498173 ps
CPU time 58.4 seconds
Started Jun 07 07:24:12 PM PDT 24
Finished Jun 07 07:25:16 PM PDT 24
Peak memory 196396 kb
Host smart-14579aa4-1065-4d83-9c2b-e58d5f937f8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945584214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.1945584214
Directory /workspace/36.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/36.uart_smoke.1671019016
Short name T663
Test name
Test status
Simulation time 487462418 ps
CPU time 2.2 seconds
Started Jun 07 07:24:10 PM PDT 24
Finished Jun 07 07:24:18 PM PDT 24
Peak memory 199064 kb
Host smart-f45b1612-1985-4d6d-a0e9-11aeededbdbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671019016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_smoke.1671019016
Directory /workspace/36.uart_smoke/latest

Test location /workspace/coverage/default/36.uart_stress_all_with_rand_reset.4035353413
Short name T186
Test name
Test status
Simulation time 87892927601 ps
CPU time 267.7 seconds
Started Jun 07 07:24:16 PM PDT 24
Finished Jun 07 07:28:50 PM PDT 24
Peak memory 216836 kb
Host smart-de75d01d-359a-4895-a715-7ed1c31e6cc0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035353413 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 36.uart_stress_all_with_rand_reset.4035353413
Directory /workspace/36.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.uart_tx_ovrd.69828285
Short name T327
Test name
Test status
Simulation time 1812970136 ps
CPU time 2.94 seconds
Started Jun 07 07:24:16 PM PDT 24
Finished Jun 07 07:24:25 PM PDT 24
Peak memory 198848 kb
Host smart-211d6cb2-543a-4694-bbfa-f63420d7ba28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69828285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.69828285
Directory /workspace/36.uart_tx_ovrd/latest

Test location /workspace/coverage/default/36.uart_tx_rx.3264968413
Short name T392
Test name
Test status
Simulation time 10550616501 ps
CPU time 10.41 seconds
Started Jun 07 07:24:08 PM PDT 24
Finished Jun 07 07:24:23 PM PDT 24
Peak memory 200416 kb
Host smart-e726d760-b7c3-4c03-9e89-bc4367847116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264968413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.3264968413
Directory /workspace/36.uart_tx_rx/latest

Test location /workspace/coverage/default/37.uart_alert_test.111985491
Short name T1069
Test name
Test status
Simulation time 13236484 ps
CPU time 0.56 seconds
Started Jun 07 07:24:22 PM PDT 24
Finished Jun 07 07:24:28 PM PDT 24
Peak memory 196060 kb
Host smart-41955a56-fb61-47e5-9b83-567aae8ed228
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111985491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.111985491
Directory /workspace/37.uart_alert_test/latest

Test location /workspace/coverage/default/37.uart_fifo_full.2051812684
Short name T771
Test name
Test status
Simulation time 62008969514 ps
CPU time 97.33 seconds
Started Jun 07 07:24:14 PM PDT 24
Finished Jun 07 07:25:57 PM PDT 24
Peak memory 200244 kb
Host smart-235bca90-8641-4964-af55-48692c7bca6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051812684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.2051812684
Directory /workspace/37.uart_fifo_full/latest

Test location /workspace/coverage/default/37.uart_fifo_reset.1786045155
Short name T184
Test name
Test status
Simulation time 40150277255 ps
CPU time 22.84 seconds
Started Jun 07 07:24:14 PM PDT 24
Finished Jun 07 07:24:43 PM PDT 24
Peak memory 200356 kb
Host smart-205b246d-9a3a-421d-a214-5f4ae676919e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786045155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.1786045155
Directory /workspace/37.uart_fifo_reset/latest

Test location /workspace/coverage/default/37.uart_intr.1240362150
Short name T458
Test name
Test status
Simulation time 35637806174 ps
CPU time 29.46 seconds
Started Jun 07 07:24:13 PM PDT 24
Finished Jun 07 07:24:48 PM PDT 24
Peak memory 200288 kb
Host smart-d822a163-4fd0-4bbe-939e-cd34075f9841
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240362150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.1240362150
Directory /workspace/37.uart_intr/latest

Test location /workspace/coverage/default/37.uart_long_xfer_wo_dly.534174794
Short name T383
Test name
Test status
Simulation time 44110292414 ps
CPU time 157.92 seconds
Started Jun 07 07:24:14 PM PDT 24
Finished Jun 07 07:26:58 PM PDT 24
Peak memory 200268 kb
Host smart-ee119fe2-2a11-445c-8840-f96deddb1a17
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=534174794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.534174794
Directory /workspace/37.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/37.uart_loopback.2040385416
Short name T362
Test name
Test status
Simulation time 8421224475 ps
CPU time 4.44 seconds
Started Jun 07 07:24:15 PM PDT 24
Finished Jun 07 07:24:25 PM PDT 24
Peak memory 198240 kb
Host smart-609bb621-64e0-4960-b75c-a1a8b3042379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040385416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_loopback.2040385416
Directory /workspace/37.uart_loopback/latest

Test location /workspace/coverage/default/37.uart_perf.38718066
Short name T601
Test name
Test status
Simulation time 11809280725 ps
CPU time 258.92 seconds
Started Jun 07 07:24:14 PM PDT 24
Finished Jun 07 07:28:38 PM PDT 24
Peak memory 200320 kb
Host smart-b3710ba6-4b6c-46ca-8359-c715ff805b7b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=38718066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.38718066
Directory /workspace/37.uart_perf/latest

Test location /workspace/coverage/default/37.uart_rx_oversample.2348726827
Short name T965
Test name
Test status
Simulation time 1294628220 ps
CPU time 1.91 seconds
Started Jun 07 07:24:14 PM PDT 24
Finished Jun 07 07:24:22 PM PDT 24
Peak memory 198188 kb
Host smart-430b3c21-444d-4344-9bc1-60738a9963c9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2348726827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.2348726827
Directory /workspace/37.uart_rx_oversample/latest

Test location /workspace/coverage/default/37.uart_rx_parity_err.3162278813
Short name T895
Test name
Test status
Simulation time 134967302151 ps
CPU time 59.36 seconds
Started Jun 07 07:24:16 PM PDT 24
Finished Jun 07 07:25:21 PM PDT 24
Peak memory 200344 kb
Host smart-5a7ca5de-d473-4893-b99f-2c60d74c858c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162278813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.3162278813
Directory /workspace/37.uart_rx_parity_err/latest

Test location /workspace/coverage/default/37.uart_rx_start_bit_filter.2218734225
Short name T834
Test name
Test status
Simulation time 5680727935 ps
CPU time 1.3 seconds
Started Jun 07 07:24:15 PM PDT 24
Finished Jun 07 07:24:22 PM PDT 24
Peak memory 196484 kb
Host smart-008a2d88-2b90-4ce4-9418-06f228d2df26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218734225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.2218734225
Directory /workspace/37.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/37.uart_smoke.1876400706
Short name T52
Test name
Test status
Simulation time 5894492998 ps
CPU time 25.71 seconds
Started Jun 07 07:24:15 PM PDT 24
Finished Jun 07 07:24:47 PM PDT 24
Peak memory 200368 kb
Host smart-c1cf00c4-2650-4f74-ac0a-5ef45dea149e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876400706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_smoke.1876400706
Directory /workspace/37.uart_smoke/latest

Test location /workspace/coverage/default/37.uart_stress_all_with_rand_reset.2718848092
Short name T726
Test name
Test status
Simulation time 61210598452 ps
CPU time 257.32 seconds
Started Jun 07 07:24:12 PM PDT 24
Finished Jun 07 07:28:35 PM PDT 24
Peak memory 208728 kb
Host smart-b1e002b1-7737-4af9-9e25-3c28aa72f184
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718848092 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 37.uart_stress_all_with_rand_reset.2718848092
Directory /workspace/37.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.uart_tx_ovrd.3881681880
Short name T901
Test name
Test status
Simulation time 1383488217 ps
CPU time 4.55 seconds
Started Jun 07 07:24:14 PM PDT 24
Finished Jun 07 07:24:25 PM PDT 24
Peak memory 200192 kb
Host smart-74639fdd-6def-4bb6-9c82-aadedac02036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881681880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.3881681880
Directory /workspace/37.uart_tx_ovrd/latest

Test location /workspace/coverage/default/37.uart_tx_rx.729005735
Short name T918
Test name
Test status
Simulation time 320009788897 ps
CPU time 142.4 seconds
Started Jun 07 07:24:14 PM PDT 24
Finished Jun 07 07:26:43 PM PDT 24
Peak memory 200332 kb
Host smart-c34440a9-fb18-4524-8284-0e9232a15037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729005735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.729005735
Directory /workspace/37.uart_tx_rx/latest

Test location /workspace/coverage/default/38.uart_alert_test.2804894001
Short name T382
Test name
Test status
Simulation time 21569683 ps
CPU time 0.6 seconds
Started Jun 07 07:24:22 PM PDT 24
Finished Jun 07 07:24:28 PM PDT 24
Peak memory 195772 kb
Host smart-7c5568c3-bc6b-4b2c-903b-86a061d75be0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804894001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.2804894001
Directory /workspace/38.uart_alert_test/latest

Test location /workspace/coverage/default/38.uart_fifo_full.2359738801
Short name T131
Test name
Test status
Simulation time 19585024547 ps
CPU time 17.67 seconds
Started Jun 07 07:24:22 PM PDT 24
Finished Jun 07 07:24:46 PM PDT 24
Peak memory 200352 kb
Host smart-53157528-ca39-43bb-b3cc-115cff4ebf20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359738801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.2359738801
Directory /workspace/38.uart_fifo_full/latest

Test location /workspace/coverage/default/38.uart_fifo_overflow.3668113138
Short name T806
Test name
Test status
Simulation time 70458526121 ps
CPU time 98.47 seconds
Started Jun 07 07:24:23 PM PDT 24
Finished Jun 07 07:26:07 PM PDT 24
Peak memory 200420 kb
Host smart-8404e836-9cb1-4454-a2d9-d58f2a6f77d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668113138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.3668113138
Directory /workspace/38.uart_fifo_overflow/latest

Test location /workspace/coverage/default/38.uart_fifo_reset.2075544078
Short name T789
Test name
Test status
Simulation time 15098344854 ps
CPU time 24.99 seconds
Started Jun 07 07:24:22 PM PDT 24
Finished Jun 07 07:24:53 PM PDT 24
Peak memory 200320 kb
Host smart-a00f45dc-47cc-412a-a5e4-46062f801ed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075544078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.2075544078
Directory /workspace/38.uart_fifo_reset/latest

Test location /workspace/coverage/default/38.uart_intr.1575275884
Short name T22
Test name
Test status
Simulation time 199274382792 ps
CPU time 309.03 seconds
Started Jun 07 07:24:22 PM PDT 24
Finished Jun 07 07:29:37 PM PDT 24
Peak memory 200304 kb
Host smart-366d1251-643c-403e-8de3-752804f9e459
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575275884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.1575275884
Directory /workspace/38.uart_intr/latest

Test location /workspace/coverage/default/38.uart_long_xfer_wo_dly.2342676381
Short name T1058
Test name
Test status
Simulation time 156779265892 ps
CPU time 183.33 seconds
Started Jun 07 07:24:22 PM PDT 24
Finished Jun 07 07:27:31 PM PDT 24
Peak memory 200292 kb
Host smart-abd90c64-07ae-4174-9e35-69d46fa9c37d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2342676381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.2342676381
Directory /workspace/38.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/38.uart_loopback.4141610057
Short name T462
Test name
Test status
Simulation time 2003888735 ps
CPU time 1.41 seconds
Started Jun 07 07:24:23 PM PDT 24
Finished Jun 07 07:24:30 PM PDT 24
Peak memory 196220 kb
Host smart-38ef9284-9859-4cd8-b284-a49428ca906f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141610057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_loopback.4141610057
Directory /workspace/38.uart_loopback/latest

Test location /workspace/coverage/default/38.uart_perf.1974015269
Short name T774
Test name
Test status
Simulation time 17366184103 ps
CPU time 193.19 seconds
Started Jun 07 07:24:23 PM PDT 24
Finished Jun 07 07:27:42 PM PDT 24
Peak memory 200248 kb
Host smart-a7eebb46-6ed6-4ed8-98a4-d4bf4edca7c5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1974015269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.1974015269
Directory /workspace/38.uart_perf/latest

Test location /workspace/coverage/default/38.uart_rx_oversample.467010194
Short name T875
Test name
Test status
Simulation time 5025542525 ps
CPU time 12.04 seconds
Started Jun 07 07:24:23 PM PDT 24
Finished Jun 07 07:24:40 PM PDT 24
Peak memory 199120 kb
Host smart-133fd252-1a0b-4ef7-8324-87de5aa5e07e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=467010194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.467010194
Directory /workspace/38.uart_rx_oversample/latest

Test location /workspace/coverage/default/38.uart_rx_parity_err.2649172858
Short name T185
Test name
Test status
Simulation time 82886026182 ps
CPU time 31.26 seconds
Started Jun 07 07:24:26 PM PDT 24
Finished Jun 07 07:25:02 PM PDT 24
Peak memory 200436 kb
Host smart-d88efddb-c6ad-41e3-aaef-9eb69acd8aca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649172858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.2649172858
Directory /workspace/38.uart_rx_parity_err/latest

Test location /workspace/coverage/default/38.uart_rx_start_bit_filter.1541782437
Short name T664
Test name
Test status
Simulation time 1911404566 ps
CPU time 3.44 seconds
Started Jun 07 07:24:22 PM PDT 24
Finished Jun 07 07:24:31 PM PDT 24
Peak memory 195756 kb
Host smart-5ed38881-9edb-4f8e-8e56-2022d8eb4604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541782437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.1541782437
Directory /workspace/38.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/38.uart_smoke.3170613
Short name T572
Test name
Test status
Simulation time 696090327 ps
CPU time 2.99 seconds
Started Jun 07 07:24:22 PM PDT 24
Finished Jun 07 07:24:31 PM PDT 24
Peak memory 199976 kb
Host smart-868b03b2-515a-4386-a607-276aa82468d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_smoke.3170613
Directory /workspace/38.uart_smoke/latest

Test location /workspace/coverage/default/38.uart_stress_all.3413979780
Short name T485
Test name
Test status
Simulation time 203256402547 ps
CPU time 377.28 seconds
Started Jun 07 07:24:23 PM PDT 24
Finished Jun 07 07:30:46 PM PDT 24
Peak memory 200324 kb
Host smart-294958c8-ac84-401a-8946-aab0801b2576
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413979780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.3413979780
Directory /workspace/38.uart_stress_all/latest

Test location /workspace/coverage/default/38.uart_tx_ovrd.103937814
Short name T562
Test name
Test status
Simulation time 576055071 ps
CPU time 2.16 seconds
Started Jun 07 07:24:23 PM PDT 24
Finished Jun 07 07:24:31 PM PDT 24
Peak memory 199892 kb
Host smart-ac677808-a6bd-4e83-b1cf-6beb5644fa45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103937814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.103937814
Directory /workspace/38.uart_tx_ovrd/latest

Test location /workspace/coverage/default/39.uart_alert_test.4136132390
Short name T646
Test name
Test status
Simulation time 47900556 ps
CPU time 0.55 seconds
Started Jun 07 07:24:41 PM PDT 24
Finished Jun 07 07:24:47 PM PDT 24
Peak memory 195792 kb
Host smart-5e89357d-7ba3-42c5-94c2-4476bf7b3849
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136132390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.4136132390
Directory /workspace/39.uart_alert_test/latest

Test location /workspace/coverage/default/39.uart_fifo_full.1923896971
Short name T864
Test name
Test status
Simulation time 122086862887 ps
CPU time 190.48 seconds
Started Jun 07 07:24:25 PM PDT 24
Finished Jun 07 07:27:40 PM PDT 24
Peak memory 200448 kb
Host smart-f4a8ebc4-8dd5-479f-aec9-7e2820841435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923896971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.1923896971
Directory /workspace/39.uart_fifo_full/latest

Test location /workspace/coverage/default/39.uart_fifo_overflow.1657701415
Short name T943
Test name
Test status
Simulation time 66689706304 ps
CPU time 28.22 seconds
Started Jun 07 07:24:32 PM PDT 24
Finished Jun 07 07:25:05 PM PDT 24
Peak memory 200396 kb
Host smart-4f6b072a-44fc-4740-aeda-767f02dbaa8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657701415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.1657701415
Directory /workspace/39.uart_fifo_overflow/latest

Test location /workspace/coverage/default/39.uart_fifo_reset.1596218020
Short name T201
Test name
Test status
Simulation time 18473697883 ps
CPU time 33.75 seconds
Started Jun 07 07:24:33 PM PDT 24
Finished Jun 07 07:25:11 PM PDT 24
Peak memory 200372 kb
Host smart-68b81922-4631-42b3-b98d-c2a638e2fe32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596218020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.1596218020
Directory /workspace/39.uart_fifo_reset/latest

Test location /workspace/coverage/default/39.uart_intr.644732544
Short name T433
Test name
Test status
Simulation time 37483205087 ps
CPU time 19.11 seconds
Started Jun 07 07:24:32 PM PDT 24
Finished Jun 07 07:24:55 PM PDT 24
Peak memory 200340 kb
Host smart-96e7a755-d798-4c94-bf77-6cdba341abfe
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644732544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.644732544
Directory /workspace/39.uart_intr/latest

Test location /workspace/coverage/default/39.uart_long_xfer_wo_dly.209362007
Short name T379
Test name
Test status
Simulation time 59969672230 ps
CPU time 404.5 seconds
Started Jun 07 07:24:36 PM PDT 24
Finished Jun 07 07:31:25 PM PDT 24
Peak memory 200280 kb
Host smart-786c2c02-3257-49af-bc83-91d43a8b1604
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=209362007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.209362007
Directory /workspace/39.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/39.uart_loopback.3810567034
Short name T67
Test name
Test status
Simulation time 2625828317 ps
CPU time 5.36 seconds
Started Jun 07 07:24:31 PM PDT 24
Finished Jun 07 07:24:41 PM PDT 24
Peak memory 196484 kb
Host smart-202931e6-b701-4bc3-820b-ad8a6b3d65e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810567034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_loopback.3810567034
Directory /workspace/39.uart_loopback/latest

Test location /workspace/coverage/default/39.uart_perf.2892336521
Short name T55
Test name
Test status
Simulation time 4172717181 ps
CPU time 254.93 seconds
Started Jun 07 07:24:32 PM PDT 24
Finished Jun 07 07:28:50 PM PDT 24
Peak memory 200276 kb
Host smart-0372c9a9-6970-4112-9456-f128d99579d4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2892336521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.2892336521
Directory /workspace/39.uart_perf/latest

Test location /workspace/coverage/default/39.uart_rx_oversample.3889598798
Short name T70
Test name
Test status
Simulation time 1919010901 ps
CPU time 3.25 seconds
Started Jun 07 07:24:32 PM PDT 24
Finished Jun 07 07:24:39 PM PDT 24
Peak memory 198444 kb
Host smart-c5ef262c-cd5a-43dc-af3e-ba2a56f9fb4c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3889598798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.3889598798
Directory /workspace/39.uart_rx_oversample/latest

Test location /workspace/coverage/default/39.uart_rx_parity_err.210000633
Short name T608
Test name
Test status
Simulation time 36091123525 ps
CPU time 41.06 seconds
Started Jun 07 07:24:36 PM PDT 24
Finished Jun 07 07:25:21 PM PDT 24
Peak memory 200252 kb
Host smart-e68b21c3-f545-4db4-9354-43dd04129b3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210000633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.210000633
Directory /workspace/39.uart_rx_parity_err/latest

Test location /workspace/coverage/default/39.uart_rx_start_bit_filter.1331874171
Short name T706
Test name
Test status
Simulation time 1824939849 ps
CPU time 3.53 seconds
Started Jun 07 07:24:33 PM PDT 24
Finished Jun 07 07:24:41 PM PDT 24
Peak memory 195800 kb
Host smart-fae82c35-4789-47cf-806f-b7eeea20789a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331874171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.1331874171
Directory /workspace/39.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/39.uart_smoke.1510894897
Short name T902
Test name
Test status
Simulation time 778654007 ps
CPU time 1.08 seconds
Started Jun 07 07:24:25 PM PDT 24
Finished Jun 07 07:24:31 PM PDT 24
Peak memory 199092 kb
Host smart-9b4d9bc1-c304-4162-92b5-06fe44d8b168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510894897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_smoke.1510894897
Directory /workspace/39.uart_smoke/latest

Test location /workspace/coverage/default/39.uart_stress_all.1357144248
Short name T179
Test name
Test status
Simulation time 210711430310 ps
CPU time 111.89 seconds
Started Jun 07 07:24:30 PM PDT 24
Finished Jun 07 07:26:26 PM PDT 24
Peak memory 200352 kb
Host smart-3fffd188-5fb6-4fe2-a77d-3518c22376ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357144248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.1357144248
Directory /workspace/39.uart_stress_all/latest

Test location /workspace/coverage/default/39.uart_stress_all_with_rand_reset.3163936721
Short name T106
Test name
Test status
Simulation time 13534905837 ps
CPU time 143.12 seconds
Started Jun 07 07:24:30 PM PDT 24
Finished Jun 07 07:26:58 PM PDT 24
Peak memory 216028 kb
Host smart-b33b2059-84d8-413d-aa73-1ea0251a90e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163936721 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 39.uart_stress_all_with_rand_reset.3163936721
Directory /workspace/39.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.uart_tx_ovrd.1870462497
Short name T12
Test name
Test status
Simulation time 9832841898 ps
CPU time 6.05 seconds
Started Jun 07 07:24:31 PM PDT 24
Finished Jun 07 07:24:41 PM PDT 24
Peak memory 200172 kb
Host smart-6ca041ba-8160-4553-9e9d-3779e580cdf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870462497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.1870462497
Directory /workspace/39.uart_tx_ovrd/latest

Test location /workspace/coverage/default/39.uart_tx_rx.3563525143
Short name T1064
Test name
Test status
Simulation time 3430837407 ps
CPU time 2.2 seconds
Started Jun 07 07:24:23 PM PDT 24
Finished Jun 07 07:24:30 PM PDT 24
Peak memory 197604 kb
Host smart-77ceb2d1-fefe-4a0d-8d6b-2465e9722feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563525143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.3563525143
Directory /workspace/39.uart_tx_rx/latest

Test location /workspace/coverage/default/4.uart_alert_test.1718472463
Short name T987
Test name
Test status
Simulation time 37564509 ps
CPU time 0.57 seconds
Started Jun 07 07:20:09 PM PDT 24
Finished Jun 07 07:20:35 PM PDT 24
Peak memory 196072 kb
Host smart-86194bc0-c808-4475-931f-681584a845fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718472463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.1718472463
Directory /workspace/4.uart_alert_test/latest

Test location /workspace/coverage/default/4.uart_fifo_full.2928257957
Short name T115
Test name
Test status
Simulation time 112244051324 ps
CPU time 49.52 seconds
Started Jun 07 07:19:59 PM PDT 24
Finished Jun 07 07:21:14 PM PDT 24
Peak memory 200380 kb
Host smart-dee98808-c6e3-4004-89e2-9c3e98384209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928257957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.2928257957
Directory /workspace/4.uart_fifo_full/latest

Test location /workspace/coverage/default/4.uart_fifo_overflow.468360977
Short name T1061
Test name
Test status
Simulation time 209233279744 ps
CPU time 230.49 seconds
Started Jun 07 07:19:59 PM PDT 24
Finished Jun 07 07:24:15 PM PDT 24
Peak memory 200376 kb
Host smart-25087a66-e346-49aa-b305-5b3f98be3354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468360977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.468360977
Directory /workspace/4.uart_fifo_overflow/latest

Test location /workspace/coverage/default/4.uart_fifo_reset.1835683581
Short name T840
Test name
Test status
Simulation time 119648711627 ps
CPU time 17 seconds
Started Jun 07 07:19:59 PM PDT 24
Finished Jun 07 07:20:41 PM PDT 24
Peak memory 200280 kb
Host smart-14a72c97-09c0-4369-a300-aaa191afdde8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835683581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.1835683581
Directory /workspace/4.uart_fifo_reset/latest

Test location /workspace/coverage/default/4.uart_intr.644040318
Short name T285
Test name
Test status
Simulation time 51792346310 ps
CPU time 79.49 seconds
Started Jun 07 07:20:00 PM PDT 24
Finished Jun 07 07:21:44 PM PDT 24
Peak memory 200412 kb
Host smart-d3747622-7f63-4d52-be91-518b3c70d99f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644040318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.644040318
Directory /workspace/4.uart_intr/latest

Test location /workspace/coverage/default/4.uart_long_xfer_wo_dly.2220131027
Short name T1002
Test name
Test status
Simulation time 50903728239 ps
CPU time 189.09 seconds
Started Jun 07 07:20:00 PM PDT 24
Finished Jun 07 07:23:35 PM PDT 24
Peak memory 200324 kb
Host smart-1a3f6327-cd45-411c-8c89-c6664302c691
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2220131027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.2220131027
Directory /workspace/4.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/4.uart_loopback.4221666875
Short name T709
Test name
Test status
Simulation time 3926092917 ps
CPU time 2.31 seconds
Started Jun 07 07:19:59 PM PDT 24
Finished Jun 07 07:20:27 PM PDT 24
Peak memory 196928 kb
Host smart-d4d18256-af3e-4745-b5ac-aec8ab3d2fad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221666875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_loopback.4221666875
Directory /workspace/4.uart_loopback/latest

Test location /workspace/coverage/default/4.uart_perf.829210704
Short name T339
Test name
Test status
Simulation time 10027014718 ps
CPU time 276.17 seconds
Started Jun 07 07:19:55 PM PDT 24
Finished Jun 07 07:24:56 PM PDT 24
Peak memory 200340 kb
Host smart-0e94aadd-f453-463a-a6a3-6738571462a9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=829210704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.829210704
Directory /workspace/4.uart_perf/latest

Test location /workspace/coverage/default/4.uart_rx_oversample.1907983185
Short name T545
Test name
Test status
Simulation time 6935476912 ps
CPU time 29.74 seconds
Started Jun 07 07:19:59 PM PDT 24
Finished Jun 07 07:20:54 PM PDT 24
Peak memory 199412 kb
Host smart-09ff407a-3195-4a76-a196-bda69e19e1c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1907983185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.1907983185
Directory /workspace/4.uart_rx_oversample/latest

Test location /workspace/coverage/default/4.uart_rx_parity_err.558617814
Short name T877
Test name
Test status
Simulation time 181511034603 ps
CPU time 90.9 seconds
Started Jun 07 07:19:57 PM PDT 24
Finished Jun 07 07:21:53 PM PDT 24
Peak memory 200404 kb
Host smart-664f222a-ad0a-438b-930c-10abd032ae8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558617814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.558617814
Directory /workspace/4.uart_rx_parity_err/latest

Test location /workspace/coverage/default/4.uart_rx_start_bit_filter.1668900433
Short name T111
Test name
Test status
Simulation time 74824191301 ps
CPU time 31.45 seconds
Started Jun 07 07:20:02 PM PDT 24
Finished Jun 07 07:20:59 PM PDT 24
Peak memory 196596 kb
Host smart-1075acfa-dcc2-4096-be0c-50f4c72b1611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668900433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.1668900433
Directory /workspace/4.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/4.uart_sec_cm.2247974561
Short name T94
Test name
Test status
Simulation time 299763987 ps
CPU time 1.16 seconds
Started Jun 07 07:20:14 PM PDT 24
Finished Jun 07 07:20:39 PM PDT 24
Peak memory 218644 kb
Host smart-0c249e0c-dd75-4cd9-83de-8de90a9d2e8d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247974561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.2247974561
Directory /workspace/4.uart_sec_cm/latest

Test location /workspace/coverage/default/4.uart_smoke.2479906133
Short name T587
Test name
Test status
Simulation time 272064544 ps
CPU time 1.46 seconds
Started Jun 07 07:19:58 PM PDT 24
Finished Jun 07 07:20:24 PM PDT 24
Peak memory 198896 kb
Host smart-04fb776f-e20f-463e-a5e4-6800a544c3ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479906133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_smoke.2479906133
Directory /workspace/4.uart_smoke/latest

Test location /workspace/coverage/default/4.uart_stress_all_with_rand_reset.864809705
Short name T103
Test name
Test status
Simulation time 76688322301 ps
CPU time 731.36 seconds
Started Jun 07 07:19:59 PM PDT 24
Finished Jun 07 07:32:36 PM PDT 24
Peak memory 216784 kb
Host smart-c40388ce-fb8d-4434-821f-4066bab19296
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864809705 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 4.uart_stress_all_with_rand_reset.864809705
Directory /workspace/4.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.uart_tx_ovrd.2434070421
Short name T302
Test name
Test status
Simulation time 1156687024 ps
CPU time 2.99 seconds
Started Jun 07 07:19:58 PM PDT 24
Finished Jun 07 07:20:25 PM PDT 24
Peak memory 198760 kb
Host smart-9a2fa9f2-4924-4794-b4b0-99b29b22f54d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434070421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.2434070421
Directory /workspace/4.uart_tx_ovrd/latest

Test location /workspace/coverage/default/4.uart_tx_rx.2048884586
Short name T693
Test name
Test status
Simulation time 9185715905 ps
CPU time 13.23 seconds
Started Jun 07 07:20:02 PM PDT 24
Finished Jun 07 07:20:41 PM PDT 24
Peak memory 197452 kb
Host smart-c0f7053d-9071-4309-8a20-927e0be60651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048884586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.2048884586
Directory /workspace/4.uart_tx_rx/latest

Test location /workspace/coverage/default/40.uart_alert_test.2677727349
Short name T714
Test name
Test status
Simulation time 15191143 ps
CPU time 0.56 seconds
Started Jun 07 07:24:42 PM PDT 24
Finished Jun 07 07:24:49 PM PDT 24
Peak memory 195744 kb
Host smart-3e612760-cbd4-492d-be07-0dc14609658f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677727349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.2677727349
Directory /workspace/40.uart_alert_test/latest

Test location /workspace/coverage/default/40.uart_fifo_full.1007770206
Short name T99
Test name
Test status
Simulation time 191717889500 ps
CPU time 21.82 seconds
Started Jun 07 07:24:41 PM PDT 24
Finished Jun 07 07:25:08 PM PDT 24
Peak memory 200344 kb
Host smart-0829cab2-1a48-41e5-8604-4f024f1f70a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007770206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.1007770206
Directory /workspace/40.uart_fifo_full/latest

Test location /workspace/coverage/default/40.uart_fifo_overflow.100971107
Short name T1055
Test name
Test status
Simulation time 106584263808 ps
CPU time 79.94 seconds
Started Jun 07 07:24:42 PM PDT 24
Finished Jun 07 07:26:09 PM PDT 24
Peak memory 200200 kb
Host smart-9cbea3ef-98fb-45d1-a90b-481fe704de09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100971107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.100971107
Directory /workspace/40.uart_fifo_overflow/latest

Test location /workspace/coverage/default/40.uart_fifo_reset.65464150
Short name T200
Test name
Test status
Simulation time 44428364436 ps
CPU time 37.48 seconds
Started Jun 07 07:24:40 PM PDT 24
Finished Jun 07 07:25:22 PM PDT 24
Peak memory 200364 kb
Host smart-50f31dc5-1dd4-4670-a04e-084bbe45ca31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65464150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.65464150
Directory /workspace/40.uart_fifo_reset/latest

Test location /workspace/coverage/default/40.uart_intr.1175396513
Short name T836
Test name
Test status
Simulation time 144770877111 ps
CPU time 203.2 seconds
Started Jun 07 07:24:42 PM PDT 24
Finished Jun 07 07:28:11 PM PDT 24
Peak memory 200156 kb
Host smart-2a759ecc-ef14-4779-beca-0c4dee731a8e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175396513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.1175396513
Directory /workspace/40.uart_intr/latest

Test location /workspace/coverage/default/40.uart_long_xfer_wo_dly.3254255619
Short name T992
Test name
Test status
Simulation time 40028014288 ps
CPU time 190.82 seconds
Started Jun 07 07:24:42 PM PDT 24
Finished Jun 07 07:28:00 PM PDT 24
Peak memory 200320 kb
Host smart-1ded61f8-d9e7-4d06-aac9-77f3d0af9d10
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3254255619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.3254255619
Directory /workspace/40.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/40.uart_loopback.3468048685
Short name T903
Test name
Test status
Simulation time 12593727403 ps
CPU time 13.15 seconds
Started Jun 07 07:24:42 PM PDT 24
Finished Jun 07 07:25:01 PM PDT 24
Peak memory 200048 kb
Host smart-7ca5f924-2d01-42f0-90b4-d9f59511d625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468048685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_loopback.3468048685
Directory /workspace/40.uart_loopback/latest

Test location /workspace/coverage/default/40.uart_rx_oversample.539617517
Short name T635
Test name
Test status
Simulation time 5338860766 ps
CPU time 35.45 seconds
Started Jun 07 07:24:40 PM PDT 24
Finished Jun 07 07:25:20 PM PDT 24
Peak memory 200324 kb
Host smart-dedf5697-4537-44a6-905c-8348f5a1689f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=539617517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.539617517
Directory /workspace/40.uart_rx_oversample/latest

Test location /workspace/coverage/default/40.uart_rx_parity_err.2963877093
Short name T1040
Test name
Test status
Simulation time 126150512771 ps
CPU time 325.06 seconds
Started Jun 07 07:24:39 PM PDT 24
Finished Jun 07 07:30:09 PM PDT 24
Peak memory 200304 kb
Host smart-a34220d5-526c-41f1-8fb9-bcbe4431b854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963877093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.2963877093
Directory /workspace/40.uart_rx_parity_err/latest

Test location /workspace/coverage/default/40.uart_rx_start_bit_filter.3848032404
Short name T607
Test name
Test status
Simulation time 2191009894 ps
CPU time 2.16 seconds
Started Jun 07 07:24:41 PM PDT 24
Finished Jun 07 07:24:49 PM PDT 24
Peak memory 195896 kb
Host smart-f62863a6-7d66-4191-931e-c68ac82e71dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848032404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.3848032404
Directory /workspace/40.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/40.uart_smoke.643724202
Short name T426
Test name
Test status
Simulation time 625242880 ps
CPU time 3.41 seconds
Started Jun 07 07:24:39 PM PDT 24
Finished Jun 07 07:24:46 PM PDT 24
Peak memory 200020 kb
Host smart-76dfcfcc-33fd-43be-8122-9f6eab108e8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643724202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_smoke.643724202
Directory /workspace/40.uart_smoke/latest

Test location /workspace/coverage/default/40.uart_stress_all_with_rand_reset.3874039939
Short name T1048
Test name
Test status
Simulation time 32103072638 ps
CPU time 370.58 seconds
Started Jun 07 07:24:40 PM PDT 24
Finished Jun 07 07:30:56 PM PDT 24
Peak memory 216864 kb
Host smart-0b635c2f-1e31-4c68-9e7e-82b5fd3ac5ee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874039939 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 40.uart_stress_all_with_rand_reset.3874039939
Directory /workspace/40.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.uart_tx_ovrd.3120617543
Short name T20
Test name
Test status
Simulation time 1331413625 ps
CPU time 3.85 seconds
Started Jun 07 07:24:40 PM PDT 24
Finished Jun 07 07:24:49 PM PDT 24
Peak memory 200128 kb
Host smart-41263f8d-b14c-4d5a-95de-9afb35ba02c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120617543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.3120617543
Directory /workspace/40.uart_tx_ovrd/latest

Test location /workspace/coverage/default/40.uart_tx_rx.3607728483
Short name T490
Test name
Test status
Simulation time 46783664675 ps
CPU time 20 seconds
Started Jun 07 07:24:41 PM PDT 24
Finished Jun 07 07:25:06 PM PDT 24
Peak memory 200372 kb
Host smart-c95637b0-8bad-448b-be1d-0ad4a84bfee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607728483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.3607728483
Directory /workspace/40.uart_tx_rx/latest

Test location /workspace/coverage/default/41.uart_alert_test.3773773109
Short name T638
Test name
Test status
Simulation time 16372584 ps
CPU time 0.57 seconds
Started Jun 07 07:24:49 PM PDT 24
Finished Jun 07 07:24:56 PM PDT 24
Peak memory 196032 kb
Host smart-d331d135-12db-447f-b6f4-8a5f616e5995
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773773109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.3773773109
Directory /workspace/41.uart_alert_test/latest

Test location /workspace/coverage/default/41.uart_fifo_full.2149142853
Short name T708
Test name
Test status
Simulation time 67643253258 ps
CPU time 31.57 seconds
Started Jun 07 07:24:40 PM PDT 24
Finished Jun 07 07:25:17 PM PDT 24
Peak memory 200420 kb
Host smart-e4bc4052-a3d8-4d32-87aa-8b983ec9340e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149142853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.2149142853
Directory /workspace/41.uart_fifo_full/latest

Test location /workspace/coverage/default/41.uart_fifo_overflow.788943709
Short name T169
Test name
Test status
Simulation time 25407166734 ps
CPU time 38.4 seconds
Started Jun 07 07:24:41 PM PDT 24
Finished Jun 07 07:25:26 PM PDT 24
Peak memory 200388 kb
Host smart-b09d9141-1edd-4434-b9e6-2040b612b496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788943709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.788943709
Directory /workspace/41.uart_fifo_overflow/latest

Test location /workspace/coverage/default/41.uart_intr.947325738
Short name T389
Test name
Test status
Simulation time 75639180614 ps
CPU time 131.93 seconds
Started Jun 07 07:24:50 PM PDT 24
Finished Jun 07 07:27:08 PM PDT 24
Peak memory 196480 kb
Host smart-caa3105b-2eb5-4c82-a7e0-ff65d5a3c298
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947325738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.947325738
Directory /workspace/41.uart_intr/latest

Test location /workspace/coverage/default/41.uart_long_xfer_wo_dly.3015503616
Short name T951
Test name
Test status
Simulation time 107190879172 ps
CPU time 289.75 seconds
Started Jun 07 07:24:50 PM PDT 24
Finished Jun 07 07:29:45 PM PDT 24
Peak memory 200328 kb
Host smart-164980ca-aaa9-4926-8678-c6a4143d8335
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3015503616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.3015503616
Directory /workspace/41.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/41.uart_loopback.414463413
Short name T1081
Test name
Test status
Simulation time 3198699927 ps
CPU time 3.34 seconds
Started Jun 07 07:24:51 PM PDT 24
Finished Jun 07 07:25:01 PM PDT 24
Peak memory 198376 kb
Host smart-ab3c8872-ad95-42f7-82ec-7d4855c2c5fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414463413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_loopback.414463413
Directory /workspace/41.uart_loopback/latest

Test location /workspace/coverage/default/41.uart_perf.2476043129
Short name T432
Test name
Test status
Simulation time 17045728853 ps
CPU time 139.22 seconds
Started Jun 07 07:24:50 PM PDT 24
Finished Jun 07 07:27:15 PM PDT 24
Peak memory 200380 kb
Host smart-f07c8adb-7c3d-418a-8fda-e503bd0a74d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2476043129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.2476043129
Directory /workspace/41.uart_perf/latest

Test location /workspace/coverage/default/41.uart_rx_oversample.296078277
Short name T505
Test name
Test status
Simulation time 7216043148 ps
CPU time 58.85 seconds
Started Jun 07 07:24:40 PM PDT 24
Finished Jun 07 07:25:44 PM PDT 24
Peak memory 199080 kb
Host smart-82d9eaff-67ca-4566-9636-a01cfb0fe670
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=296078277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.296078277
Directory /workspace/41.uart_rx_oversample/latest

Test location /workspace/coverage/default/41.uart_rx_parity_err.2343854097
Short name T769
Test name
Test status
Simulation time 176782159957 ps
CPU time 88.98 seconds
Started Jun 07 07:24:48 PM PDT 24
Finished Jun 07 07:26:23 PM PDT 24
Peak memory 200292 kb
Host smart-445e1e73-d5cd-4359-8a4c-9818c685d523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343854097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.2343854097
Directory /workspace/41.uart_rx_parity_err/latest

Test location /workspace/coverage/default/41.uart_rx_start_bit_filter.2423004331
Short name T408
Test name
Test status
Simulation time 2682266562 ps
CPU time 1.82 seconds
Started Jun 07 07:24:49 PM PDT 24
Finished Jun 07 07:24:57 PM PDT 24
Peak memory 196124 kb
Host smart-8c255d41-b8da-4238-82de-63e79f0dfa47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423004331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.2423004331
Directory /workspace/41.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/41.uart_smoke.1059774879
Short name T472
Test name
Test status
Simulation time 483419452 ps
CPU time 2 seconds
Started Jun 07 07:24:38 PM PDT 24
Finished Jun 07 07:24:45 PM PDT 24
Peak memory 199880 kb
Host smart-ea29728a-b198-4832-a1ba-c0a03d140110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059774879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_smoke.1059774879
Directory /workspace/41.uart_smoke/latest

Test location /workspace/coverage/default/41.uart_tx_ovrd.3126069539
Short name T469
Test name
Test status
Simulation time 693001799 ps
CPU time 1.58 seconds
Started Jun 07 07:24:49 PM PDT 24
Finished Jun 07 07:24:57 PM PDT 24
Peak memory 198900 kb
Host smart-48a0330a-e1d0-4916-9a47-352dce7886d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126069539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.3126069539
Directory /workspace/41.uart_tx_ovrd/latest

Test location /workspace/coverage/default/41.uart_tx_rx.675695574
Short name T262
Test name
Test status
Simulation time 28996538088 ps
CPU time 33.04 seconds
Started Jun 07 07:24:42 PM PDT 24
Finished Jun 07 07:25:21 PM PDT 24
Peak memory 200404 kb
Host smart-c9f89893-4cb0-4311-9c6a-ea611a891975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675695574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.675695574
Directory /workspace/41.uart_tx_rx/latest

Test location /workspace/coverage/default/42.uart_alert_test.16354815
Short name T1037
Test name
Test status
Simulation time 78852574 ps
CPU time 0.55 seconds
Started Jun 07 07:25:00 PM PDT 24
Finished Jun 07 07:25:04 PM PDT 24
Peak memory 195752 kb
Host smart-b5179540-7e16-4139-bc5c-80db7fb8ef52
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16354815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.16354815
Directory /workspace/42.uart_alert_test/latest

Test location /workspace/coverage/default/42.uart_fifo_full.975899149
Short name T157
Test name
Test status
Simulation time 78355394198 ps
CPU time 63.19 seconds
Started Jun 07 07:24:52 PM PDT 24
Finished Jun 07 07:26:00 PM PDT 24
Peak memory 200340 kb
Host smart-039b93dc-c732-4054-b19f-cd2a8d836dca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975899149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.975899149
Directory /workspace/42.uart_fifo_full/latest

Test location /workspace/coverage/default/42.uart_fifo_reset.2855465060
Short name T256
Test name
Test status
Simulation time 38102407050 ps
CPU time 39.81 seconds
Started Jun 07 07:24:51 PM PDT 24
Finished Jun 07 07:25:36 PM PDT 24
Peak memory 200448 kb
Host smart-5f167bcf-86e5-4337-b98e-898a2fac355c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855465060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.2855465060
Directory /workspace/42.uart_fifo_reset/latest

Test location /workspace/coverage/default/42.uart_intr.2450539728
Short name T1049
Test name
Test status
Simulation time 21509201638 ps
CPU time 18 seconds
Started Jun 07 07:24:49 PM PDT 24
Finished Jun 07 07:25:13 PM PDT 24
Peak memory 200448 kb
Host smart-a9483e42-4316-43a7-a028-f898b26cca12
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450539728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.2450539728
Directory /workspace/42.uart_intr/latest

Test location /workspace/coverage/default/42.uart_long_xfer_wo_dly.2944227730
Short name T925
Test name
Test status
Simulation time 181152865535 ps
CPU time 226.7 seconds
Started Jun 07 07:25:00 PM PDT 24
Finished Jun 07 07:28:50 PM PDT 24
Peak memory 200376 kb
Host smart-ae83ed65-de5c-4e8f-b66e-7d991895cd19
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2944227730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.2944227730
Directory /workspace/42.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/42.uart_loopback.3407327830
Short name T470
Test name
Test status
Simulation time 96418826 ps
CPU time 0.74 seconds
Started Jun 07 07:25:00 PM PDT 24
Finished Jun 07 07:25:05 PM PDT 24
Peak memory 196248 kb
Host smart-b25e4e1c-f062-463d-ad2e-fc099469c767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407327830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_loopback.3407327830
Directory /workspace/42.uart_loopback/latest

Test location /workspace/coverage/default/42.uart_perf.495337122
Short name T618
Test name
Test status
Simulation time 19876494895 ps
CPU time 821.51 seconds
Started Jun 07 07:25:00 PM PDT 24
Finished Jun 07 07:38:45 PM PDT 24
Peak memory 200372 kb
Host smart-764b586d-9fe2-4ce8-9fac-7db327053e7c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=495337122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.495337122
Directory /workspace/42.uart_perf/latest

Test location /workspace/coverage/default/42.uart_rx_oversample.1972500697
Short name T972
Test name
Test status
Simulation time 2460586529 ps
CPU time 4.64 seconds
Started Jun 07 07:24:49 PM PDT 24
Finished Jun 07 07:25:00 PM PDT 24
Peak memory 198376 kb
Host smart-8325b17a-b042-4348-854e-2eaada80377d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1972500697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.1972500697
Directory /workspace/42.uart_rx_oversample/latest

Test location /workspace/coverage/default/42.uart_rx_parity_err.522723909
Short name T393
Test name
Test status
Simulation time 50066089446 ps
CPU time 23 seconds
Started Jun 07 07:25:00 PM PDT 24
Finished Jun 07 07:25:26 PM PDT 24
Peak memory 200416 kb
Host smart-3f7fd1eb-01ef-4b01-a5b5-e4dd891b055b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522723909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.522723909
Directory /workspace/42.uart_rx_parity_err/latest

Test location /workspace/coverage/default/42.uart_rx_start_bit_filter.3170330373
Short name T804
Test name
Test status
Simulation time 1600716838 ps
CPU time 3.03 seconds
Started Jun 07 07:24:51 PM PDT 24
Finished Jun 07 07:25:00 PM PDT 24
Peak memory 195808 kb
Host smart-b359889a-1820-4d53-bc1b-5a494883be2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170330373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.3170330373
Directory /workspace/42.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/42.uart_smoke.1120993156
Short name T811
Test name
Test status
Simulation time 5532557441 ps
CPU time 5.86 seconds
Started Jun 07 07:24:51 PM PDT 24
Finished Jun 07 07:25:03 PM PDT 24
Peak memory 200408 kb
Host smart-fb572c94-4c81-47ee-bd47-6021141dc834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120993156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_smoke.1120993156
Directory /workspace/42.uart_smoke/latest

Test location /workspace/coverage/default/42.uart_stress_all_with_rand_reset.1652150581
Short name T558
Test name
Test status
Simulation time 31523963447 ps
CPU time 401.59 seconds
Started Jun 07 07:25:01 PM PDT 24
Finished Jun 07 07:31:47 PM PDT 24
Peak memory 208644 kb
Host smart-125c017b-01d0-482a-a4a3-fa33c043a217
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652150581 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 42.uart_stress_all_with_rand_reset.1652150581
Directory /workspace/42.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.uart_tx_ovrd.1599561722
Short name T500
Test name
Test status
Simulation time 2339296806 ps
CPU time 1.91 seconds
Started Jun 07 07:25:00 PM PDT 24
Finished Jun 07 07:25:05 PM PDT 24
Peak memory 198768 kb
Host smart-a9544706-f677-4d56-96d7-58ee3b693a2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599561722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.1599561722
Directory /workspace/42.uart_tx_ovrd/latest

Test location /workspace/coverage/default/42.uart_tx_rx.2198427282
Short name T619
Test name
Test status
Simulation time 15109705259 ps
CPU time 17.41 seconds
Started Jun 07 07:24:54 PM PDT 24
Finished Jun 07 07:25:16 PM PDT 24
Peak memory 200344 kb
Host smart-900954b5-a453-4e29-8802-f8d849253bf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198427282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.2198427282
Directory /workspace/42.uart_tx_rx/latest

Test location /workspace/coverage/default/43.uart_alert_test.3921782588
Short name T542
Test name
Test status
Simulation time 39031739 ps
CPU time 0.55 seconds
Started Jun 07 07:25:07 PM PDT 24
Finished Jun 07 07:25:12 PM PDT 24
Peak memory 195364 kb
Host smart-9ee473e4-e16b-46c5-8366-062fb49a854f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921782588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.3921782588
Directory /workspace/43.uart_alert_test/latest

Test location /workspace/coverage/default/43.uart_fifo_full.278337401
Short name T502
Test name
Test status
Simulation time 35196848439 ps
CPU time 62.4 seconds
Started Jun 07 07:24:59 PM PDT 24
Finished Jun 07 07:26:04 PM PDT 24
Peak memory 200424 kb
Host smart-40682407-dfaf-4545-bfa7-4fe0032ac192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278337401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.278337401
Directory /workspace/43.uart_fifo_full/latest

Test location /workspace/coverage/default/43.uart_fifo_overflow.138271573
Short name T153
Test name
Test status
Simulation time 282991432928 ps
CPU time 66.64 seconds
Started Jun 07 07:24:59 PM PDT 24
Finished Jun 07 07:26:09 PM PDT 24
Peak memory 200364 kb
Host smart-51d76c1e-cedf-4b81-ae95-3fdc5ea6ea93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138271573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.138271573
Directory /workspace/43.uart_fifo_overflow/latest

Test location /workspace/coverage/default/43.uart_fifo_reset.4154244119
Short name T238
Test name
Test status
Simulation time 136036818997 ps
CPU time 62.28 seconds
Started Jun 07 07:25:01 PM PDT 24
Finished Jun 07 07:26:08 PM PDT 24
Peak memory 200408 kb
Host smart-df53d003-a33a-448a-9d39-8b8b663b5138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154244119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.4154244119
Directory /workspace/43.uart_fifo_reset/latest

Test location /workspace/coverage/default/43.uart_intr.3216221235
Short name T916
Test name
Test status
Simulation time 18807896502 ps
CPU time 8.38 seconds
Started Jun 07 07:24:59 PM PDT 24
Finished Jun 07 07:25:10 PM PDT 24
Peak memory 200312 kb
Host smart-7f0b7642-826f-429d-ac28-172cd5d52e44
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216221235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.3216221235
Directory /workspace/43.uart_intr/latest

Test location /workspace/coverage/default/43.uart_long_xfer_wo_dly.384649182
Short name T753
Test name
Test status
Simulation time 198115608730 ps
CPU time 264.78 seconds
Started Jun 07 07:25:03 PM PDT 24
Finished Jun 07 07:29:31 PM PDT 24
Peak memory 200336 kb
Host smart-0125e48b-eee5-401e-adb9-b7060282f18d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=384649182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.384649182
Directory /workspace/43.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/43.uart_loopback.880764282
Short name T377
Test name
Test status
Simulation time 1249730983 ps
CPU time 3.56 seconds
Started Jun 07 07:25:01 PM PDT 24
Finished Jun 07 07:25:08 PM PDT 24
Peak memory 197752 kb
Host smart-02c0598c-1b68-4be5-8446-5764b4452cf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880764282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_loopback.880764282
Directory /workspace/43.uart_loopback/latest

Test location /workspace/coverage/default/43.uart_perf.1919125016
Short name T411
Test name
Test status
Simulation time 18714342472 ps
CPU time 1105.52 seconds
Started Jun 07 07:25:00 PM PDT 24
Finished Jun 07 07:43:29 PM PDT 24
Peak memory 200312 kb
Host smart-b8e96614-07af-4516-ac31-305e07462aef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1919125016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.1919125016
Directory /workspace/43.uart_perf/latest

Test location /workspace/coverage/default/43.uart_rx_oversample.2523368285
Short name T515
Test name
Test status
Simulation time 6671414695 ps
CPU time 7.99 seconds
Started Jun 07 07:25:00 PM PDT 24
Finished Jun 07 07:25:11 PM PDT 24
Peak memory 198580 kb
Host smart-390b18de-c996-42c6-98e7-4b75c8b8c3de
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2523368285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.2523368285
Directory /workspace/43.uart_rx_oversample/latest

Test location /workspace/coverage/default/43.uart_rx_parity_err.1555002104
Short name T712
Test name
Test status
Simulation time 67270730420 ps
CPU time 125.86 seconds
Started Jun 07 07:25:00 PM PDT 24
Finished Jun 07 07:27:09 PM PDT 24
Peak memory 200356 kb
Host smart-0c6df87b-fe38-445f-a77c-2f0b6e75e326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555002104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.1555002104
Directory /workspace/43.uart_rx_parity_err/latest

Test location /workspace/coverage/default/43.uart_rx_start_bit_filter.3338135853
Short name T466
Test name
Test status
Simulation time 79818313288 ps
CPU time 33.43 seconds
Started Jun 07 07:25:01 PM PDT 24
Finished Jun 07 07:25:38 PM PDT 24
Peak memory 196332 kb
Host smart-eb633e7a-20e2-4257-adb9-56b6ca517404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338135853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.3338135853
Directory /workspace/43.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/43.uart_smoke.581090884
Short name T991
Test name
Test status
Simulation time 5528431956 ps
CPU time 25.25 seconds
Started Jun 07 07:25:00 PM PDT 24
Finished Jun 07 07:25:29 PM PDT 24
Peak memory 200216 kb
Host smart-e05fa4ac-3c3a-43c5-b326-dc1f2ff377fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581090884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_smoke.581090884
Directory /workspace/43.uart_smoke/latest

Test location /workspace/coverage/default/43.uart_stress_all.3248768273
Short name T338
Test name
Test status
Simulation time 35649934162 ps
CPU time 55.72 seconds
Started Jun 07 07:24:59 PM PDT 24
Finished Jun 07 07:25:58 PM PDT 24
Peak memory 200428 kb
Host smart-df637ae9-0aa7-4516-9d9e-02748b28673f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248768273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.3248768273
Directory /workspace/43.uart_stress_all/latest

Test location /workspace/coverage/default/43.uart_tx_ovrd.3411385212
Short name T313
Test name
Test status
Simulation time 889408916 ps
CPU time 3.3 seconds
Started Jun 07 07:25:00 PM PDT 24
Finished Jun 07 07:25:06 PM PDT 24
Peak memory 198832 kb
Host smart-acb0d1bd-f1e8-408d-ab94-e526885b116b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411385212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.3411385212
Directory /workspace/43.uart_tx_ovrd/latest

Test location /workspace/coverage/default/43.uart_tx_rx.2917331253
Short name T442
Test name
Test status
Simulation time 64611113588 ps
CPU time 35.33 seconds
Started Jun 07 07:25:01 PM PDT 24
Finished Jun 07 07:25:40 PM PDT 24
Peak memory 200388 kb
Host smart-218efb79-290c-48c6-9cbc-28a90330edf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917331253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.2917331253
Directory /workspace/43.uart_tx_rx/latest

Test location /workspace/coverage/default/44.uart_alert_test.1076016995
Short name T420
Test name
Test status
Simulation time 20756310 ps
CPU time 0.55 seconds
Started Jun 07 07:25:10 PM PDT 24
Finished Jun 07 07:25:16 PM PDT 24
Peak memory 194748 kb
Host smart-cafcc0c1-9d6a-427a-8f7b-18f9edac4983
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076016995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.1076016995
Directory /workspace/44.uart_alert_test/latest

Test location /workspace/coverage/default/44.uart_fifo_full.563044802
Short name T898
Test name
Test status
Simulation time 114961498001 ps
CPU time 169.22 seconds
Started Jun 07 07:25:09 PM PDT 24
Finished Jun 07 07:28:03 PM PDT 24
Peak memory 200412 kb
Host smart-6b9bb450-2c8e-47c0-b70a-31e9ccbf1133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563044802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.563044802
Directory /workspace/44.uart_fifo_full/latest

Test location /workspace/coverage/default/44.uart_fifo_overflow.793286095
Short name T182
Test name
Test status
Simulation time 143494738641 ps
CPU time 103.36 seconds
Started Jun 07 07:25:09 PM PDT 24
Finished Jun 07 07:26:58 PM PDT 24
Peak memory 200408 kb
Host smart-4797c567-587e-42a9-b0fc-4b0c2b22a765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793286095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.793286095
Directory /workspace/44.uart_fifo_overflow/latest

Test location /workspace/coverage/default/44.uart_fifo_reset.2367169906
Short name T687
Test name
Test status
Simulation time 92575292146 ps
CPU time 40.83 seconds
Started Jun 07 07:25:08 PM PDT 24
Finished Jun 07 07:25:54 PM PDT 24
Peak memory 200352 kb
Host smart-8c0881bb-61d2-4d37-930a-c36ece0ed16a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367169906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.2367169906
Directory /workspace/44.uart_fifo_reset/latest

Test location /workspace/coverage/default/44.uart_intr.940060320
Short name T532
Test name
Test status
Simulation time 25339427290 ps
CPU time 71.36 seconds
Started Jun 07 07:25:10 PM PDT 24
Finished Jun 07 07:26:27 PM PDT 24
Peak memory 200356 kb
Host smart-f275671a-f4a4-497d-ab17-b2c8f72d29be
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940060320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.940060320
Directory /workspace/44.uart_intr/latest

Test location /workspace/coverage/default/44.uart_long_xfer_wo_dly.2837537425
Short name T1017
Test name
Test status
Simulation time 107845874014 ps
CPU time 229.52 seconds
Started Jun 07 07:25:12 PM PDT 24
Finished Jun 07 07:29:08 PM PDT 24
Peak memory 200408 kb
Host smart-ff31dfe1-936e-468f-93ca-2d49cd5a872c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2837537425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.2837537425
Directory /workspace/44.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/44.uart_loopback.3879998665
Short name T24
Test name
Test status
Simulation time 8543324432 ps
CPU time 12 seconds
Started Jun 07 07:25:11 PM PDT 24
Finished Jun 07 07:25:30 PM PDT 24
Peak memory 200332 kb
Host smart-afbfbe7a-ba87-48c5-a623-35f6cfb2e2fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879998665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_loopback.3879998665
Directory /workspace/44.uart_loopback/latest

Test location /workspace/coverage/default/44.uart_perf.2671563978
Short name T796
Test name
Test status
Simulation time 13554295450 ps
CPU time 327.73 seconds
Started Jun 07 07:25:14 PM PDT 24
Finished Jun 07 07:30:48 PM PDT 24
Peak memory 200328 kb
Host smart-23d660e9-ca99-4849-a899-b06bf4076230
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2671563978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.2671563978
Directory /workspace/44.uart_perf/latest

Test location /workspace/coverage/default/44.uart_rx_oversample.611065627
Short name T920
Test name
Test status
Simulation time 3577839820 ps
CPU time 27.26 seconds
Started Jun 07 07:25:09 PM PDT 24
Finished Jun 07 07:25:41 PM PDT 24
Peak memory 198368 kb
Host smart-58f414e5-d5de-43c9-8820-d90b77818845
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=611065627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.611065627
Directory /workspace/44.uart_rx_oversample/latest

Test location /workspace/coverage/default/44.uart_rx_start_bit_filter.2485962015
Short name T880
Test name
Test status
Simulation time 768441377 ps
CPU time 1.6 seconds
Started Jun 07 07:25:09 PM PDT 24
Finished Jun 07 07:25:15 PM PDT 24
Peak memory 195760 kb
Host smart-ae9c85a4-8a5b-4687-a8b5-aaa825d3f744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485962015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.2485962015
Directory /workspace/44.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/44.uart_smoke.3416454015
Short name T1078
Test name
Test status
Simulation time 6174402872 ps
CPU time 19.99 seconds
Started Jun 07 07:25:10 PM PDT 24
Finished Jun 07 07:25:36 PM PDT 24
Peak memory 200172 kb
Host smart-366ddbf4-d1a1-454a-b504-7c9cd9e9cfc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416454015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_smoke.3416454015
Directory /workspace/44.uart_smoke/latest

Test location /workspace/coverage/default/44.uart_stress_all.2623896745
Short name T1045
Test name
Test status
Simulation time 142657170659 ps
CPU time 233.41 seconds
Started Jun 07 07:25:08 PM PDT 24
Finished Jun 07 07:29:07 PM PDT 24
Peak memory 200320 kb
Host smart-6a297a89-da04-45e5-b4e0-9424d4c00a8d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623896745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.2623896745
Directory /workspace/44.uart_stress_all/latest

Test location /workspace/coverage/default/44.uart_stress_all_with_rand_reset.519726870
Short name T41
Test name
Test status
Simulation time 57001125138 ps
CPU time 628.18 seconds
Started Jun 07 07:25:11 PM PDT 24
Finished Jun 07 07:35:46 PM PDT 24
Peak memory 216036 kb
Host smart-78244e2f-c64f-464c-86a3-9399da0bc054
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519726870 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 44.uart_stress_all_with_rand_reset.519726870
Directory /workspace/44.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.uart_tx_ovrd.2677424993
Short name T370
Test name
Test status
Simulation time 1535718413 ps
CPU time 2.42 seconds
Started Jun 07 07:25:09 PM PDT 24
Finished Jun 07 07:25:17 PM PDT 24
Peak memory 199328 kb
Host smart-7da823a5-b516-4abf-b0cf-b1911274c06e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677424993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.2677424993
Directory /workspace/44.uart_tx_ovrd/latest

Test location /workspace/coverage/default/44.uart_tx_rx.4221808935
Short name T845
Test name
Test status
Simulation time 162553905657 ps
CPU time 187.33 seconds
Started Jun 07 07:25:10 PM PDT 24
Finished Jun 07 07:28:23 PM PDT 24
Peak memory 200400 kb
Host smart-a27c04c3-c7dc-4f1e-98e0-c78747695940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221808935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.4221808935
Directory /workspace/44.uart_tx_rx/latest

Test location /workspace/coverage/default/45.uart_alert_test.2945317711
Short name T662
Test name
Test status
Simulation time 13753065 ps
CPU time 0.58 seconds
Started Jun 07 07:25:19 PM PDT 24
Finished Jun 07 07:25:27 PM PDT 24
Peak memory 195772 kb
Host smart-be8f14ca-6858-4482-bccf-d0294048db14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945317711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.2945317711
Directory /workspace/45.uart_alert_test/latest

Test location /workspace/coverage/default/45.uart_fifo_full.3199723391
Short name T268
Test name
Test status
Simulation time 15720324277 ps
CPU time 16.47 seconds
Started Jun 07 07:25:14 PM PDT 24
Finished Jun 07 07:25:38 PM PDT 24
Peak memory 200332 kb
Host smart-e05e0285-e4cd-4f03-80ae-73cdbb324739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199723391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.3199723391
Directory /workspace/45.uart_fifo_full/latest

Test location /workspace/coverage/default/45.uart_fifo_overflow.911613834
Short name T144
Test name
Test status
Simulation time 47801195705 ps
CPU time 26.02 seconds
Started Jun 07 07:25:09 PM PDT 24
Finished Jun 07 07:25:40 PM PDT 24
Peak memory 200376 kb
Host smart-df75229a-d8e1-4000-9a9d-841270d6a1cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911613834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.911613834
Directory /workspace/45.uart_fifo_overflow/latest

Test location /workspace/coverage/default/45.uart_fifo_reset.505839063
Short name T3
Test name
Test status
Simulation time 58025691131 ps
CPU time 104.51 seconds
Started Jun 07 07:25:08 PM PDT 24
Finished Jun 07 07:26:57 PM PDT 24
Peak memory 200380 kb
Host smart-94c0af6c-0a16-4cea-9e2f-e885da08ec3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505839063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.505839063
Directory /workspace/45.uart_fifo_reset/latest

Test location /workspace/coverage/default/45.uart_intr.897278560
Short name T457
Test name
Test status
Simulation time 34017459894 ps
CPU time 20.47 seconds
Started Jun 07 07:25:12 PM PDT 24
Finished Jun 07 07:25:38 PM PDT 24
Peak memory 200320 kb
Host smart-1ec4caf9-cc6b-4109-9840-86072c293640
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897278560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.897278560
Directory /workspace/45.uart_intr/latest

Test location /workspace/coverage/default/45.uart_long_xfer_wo_dly.1944881278
Short name T644
Test name
Test status
Simulation time 130228937671 ps
CPU time 1087.57 seconds
Started Jun 07 07:25:07 PM PDT 24
Finished Jun 07 07:43:20 PM PDT 24
Peak memory 200412 kb
Host smart-ad7d9722-ddd3-4f1b-8dab-5962b546ab39
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1944881278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.1944881278
Directory /workspace/45.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/45.uart_loopback.808749739
Short name T950
Test name
Test status
Simulation time 3291313423 ps
CPU time 3.55 seconds
Started Jun 07 07:25:12 PM PDT 24
Finished Jun 07 07:25:22 PM PDT 24
Peak memory 196988 kb
Host smart-13780c4a-a45a-4439-abd2-8f552f295a59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808749739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_loopback.808749739
Directory /workspace/45.uart_loopback/latest

Test location /workspace/coverage/default/45.uart_perf.3672083002
Short name T1016
Test name
Test status
Simulation time 31130322777 ps
CPU time 187.13 seconds
Started Jun 07 07:25:11 PM PDT 24
Finished Jun 07 07:28:24 PM PDT 24
Peak memory 200392 kb
Host smart-924dbd2a-3880-4927-a1c0-487f5a1069ec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3672083002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.3672083002
Directory /workspace/45.uart_perf/latest

Test location /workspace/coverage/default/45.uart_rx_oversample.196364717
Short name T653
Test name
Test status
Simulation time 2978109512 ps
CPU time 4.63 seconds
Started Jun 07 07:25:11 PM PDT 24
Finished Jun 07 07:25:22 PM PDT 24
Peak memory 198608 kb
Host smart-a14fbdc4-a24a-41db-bb10-99b525840c24
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=196364717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.196364717
Directory /workspace/45.uart_rx_oversample/latest

Test location /workspace/coverage/default/45.uart_rx_parity_err.2480752054
Short name T592
Test name
Test status
Simulation time 72166708970 ps
CPU time 14.17 seconds
Started Jun 07 07:25:08 PM PDT 24
Finished Jun 07 07:25:27 PM PDT 24
Peak memory 200236 kb
Host smart-7621dd03-d5c4-4c36-843a-f54ef327116f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480752054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.2480752054
Directory /workspace/45.uart_rx_parity_err/latest

Test location /workspace/coverage/default/45.uart_rx_start_bit_filter.1265826690
Short name T9
Test name
Test status
Simulation time 5372963540 ps
CPU time 9.76 seconds
Started Jun 07 07:25:10 PM PDT 24
Finished Jun 07 07:25:26 PM PDT 24
Peak memory 196428 kb
Host smart-a292a7ee-e41e-4dd2-97e6-98b05c2f41a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265826690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.1265826690
Directory /workspace/45.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/45.uart_smoke.2347859504
Short name T1075
Test name
Test status
Simulation time 497978564 ps
CPU time 2.54 seconds
Started Jun 07 07:25:08 PM PDT 24
Finished Jun 07 07:25:15 PM PDT 24
Peak memory 198752 kb
Host smart-70cdae79-9a97-4fbb-9d28-ddb6facd47c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347859504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_smoke.2347859504
Directory /workspace/45.uart_smoke/latest

Test location /workspace/coverage/default/45.uart_stress_all_with_rand_reset.2960066185
Short name T345
Test name
Test status
Simulation time 31421335604 ps
CPU time 389.3 seconds
Started Jun 07 07:25:14 PM PDT 24
Finished Jun 07 07:31:51 PM PDT 24
Peak memory 216920 kb
Host smart-686a36c1-5d94-4dea-b0c5-42be13325646
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960066185 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 45.uart_stress_all_with_rand_reset.2960066185
Directory /workspace/45.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.uart_tx_ovrd.1533361086
Short name T322
Test name
Test status
Simulation time 7204069709 ps
CPU time 5.54 seconds
Started Jun 07 07:25:10 PM PDT 24
Finished Jun 07 07:25:21 PM PDT 24
Peak memory 200356 kb
Host smart-c3b741d5-1a81-429e-bd17-231f4093d6a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533361086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.1533361086
Directory /workspace/45.uart_tx_ovrd/latest

Test location /workspace/coverage/default/45.uart_tx_rx.3287217432
Short name T853
Test name
Test status
Simulation time 84728619967 ps
CPU time 136.82 seconds
Started Jun 07 07:25:10 PM PDT 24
Finished Jun 07 07:27:32 PM PDT 24
Peak memory 200432 kb
Host smart-51713694-14cc-4350-a2d3-8f779098e377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287217432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.3287217432
Directory /workspace/45.uart_tx_rx/latest

Test location /workspace/coverage/default/46.uart_alert_test.2460818729
Short name T848
Test name
Test status
Simulation time 39826389 ps
CPU time 0.58 seconds
Started Jun 07 07:25:20 PM PDT 24
Finished Jun 07 07:25:27 PM PDT 24
Peak memory 195988 kb
Host smart-a5cc3f57-0ffa-4f48-b812-cc80bcd4b77f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460818729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.2460818729
Directory /workspace/46.uart_alert_test/latest

Test location /workspace/coverage/default/46.uart_fifo_full.2223196691
Short name T453
Test name
Test status
Simulation time 22315811983 ps
CPU time 48.03 seconds
Started Jun 07 07:25:17 PM PDT 24
Finished Jun 07 07:26:12 PM PDT 24
Peak memory 200392 kb
Host smart-6e37ce16-86ed-4f0f-8312-ec730732f6cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223196691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.2223196691
Directory /workspace/46.uart_fifo_full/latest

Test location /workspace/coverage/default/46.uart_fifo_overflow.583772870
Short name T119
Test name
Test status
Simulation time 109349939635 ps
CPU time 157.54 seconds
Started Jun 07 07:25:19 PM PDT 24
Finished Jun 07 07:28:03 PM PDT 24
Peak memory 200292 kb
Host smart-4a5ac3ea-cad5-4458-9d93-c9a1dc755406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583772870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.583772870
Directory /workspace/46.uart_fifo_overflow/latest

Test location /workspace/coverage/default/46.uart_fifo_reset.2278350662
Short name T930
Test name
Test status
Simulation time 91333984590 ps
CPU time 248.16 seconds
Started Jun 07 07:25:18 PM PDT 24
Finished Jun 07 07:29:32 PM PDT 24
Peak memory 200400 kb
Host smart-c803acd4-e9f0-4fb2-b404-e8201a3736ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278350662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.2278350662
Directory /workspace/46.uart_fifo_reset/latest

Test location /workspace/coverage/default/46.uart_intr.330343043
Short name T1003
Test name
Test status
Simulation time 10075896799 ps
CPU time 19.61 seconds
Started Jun 07 07:25:18 PM PDT 24
Finished Jun 07 07:25:44 PM PDT 24
Peak memory 200196 kb
Host smart-87ea8104-be0a-4802-8536-93ede4863228
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330343043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.330343043
Directory /workspace/46.uart_intr/latest

Test location /workspace/coverage/default/46.uart_long_xfer_wo_dly.3776220886
Short name T410
Test name
Test status
Simulation time 96927119318 ps
CPU time 247.17 seconds
Started Jun 07 07:25:21 PM PDT 24
Finished Jun 07 07:29:35 PM PDT 24
Peak memory 200420 kb
Host smart-19550095-f43d-4c86-9bd2-5af95f900bb5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3776220886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.3776220886
Directory /workspace/46.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/46.uart_loopback.4259570428
Short name T413
Test name
Test status
Simulation time 989324675 ps
CPU time 1.02 seconds
Started Jun 07 07:25:19 PM PDT 24
Finished Jun 07 07:25:26 PM PDT 24
Peak memory 196356 kb
Host smart-adc28b91-7e0b-4712-9b6c-abf449cf6b62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259570428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_loopback.4259570428
Directory /workspace/46.uart_loopback/latest

Test location /workspace/coverage/default/46.uart_noise_filter.284832503
Short name T445
Test name
Test status
Simulation time 18112689736 ps
CPU time 25.62 seconds
Started Jun 07 07:25:19 PM PDT 24
Finished Jun 07 07:25:51 PM PDT 24
Peak memory 200312 kb
Host smart-a56425ce-1bcd-4091-85fc-df1e448d07a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284832503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_noise_filter.284832503
Directory /workspace/46.uart_noise_filter/latest

Test location /workspace/coverage/default/46.uart_perf.2173653192
Short name T287
Test name
Test status
Simulation time 27355270250 ps
CPU time 1241.48 seconds
Started Jun 07 07:25:20 PM PDT 24
Finished Jun 07 07:46:09 PM PDT 24
Peak memory 200364 kb
Host smart-e78c0982-afc6-4add-8387-944f3993c663
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2173653192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.2173653192
Directory /workspace/46.uart_perf/latest

Test location /workspace/coverage/default/46.uart_rx_oversample.3386945990
Short name T879
Test name
Test status
Simulation time 4426663036 ps
CPU time 5.29 seconds
Started Jun 07 07:25:17 PM PDT 24
Finished Jun 07 07:25:29 PM PDT 24
Peak memory 198572 kb
Host smart-018547e2-72e9-44a6-9e19-d40b0bcff730
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3386945990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.3386945990
Directory /workspace/46.uart_rx_oversample/latest

Test location /workspace/coverage/default/46.uart_rx_parity_err.1519978482
Short name T464
Test name
Test status
Simulation time 193829290752 ps
CPU time 60.46 seconds
Started Jun 07 07:25:18 PM PDT 24
Finished Jun 07 07:26:26 PM PDT 24
Peak memory 200244 kb
Host smart-d056cff2-4801-4433-b51c-bed9db972e18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519978482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.1519978482
Directory /workspace/46.uart_rx_parity_err/latest

Test location /workspace/coverage/default/46.uart_rx_start_bit_filter.1484970378
Short name T955
Test name
Test status
Simulation time 44358262834 ps
CPU time 18.04 seconds
Started Jun 07 07:25:19 PM PDT 24
Finished Jun 07 07:25:44 PM PDT 24
Peak memory 196684 kb
Host smart-2394f471-2053-4e06-8295-9cab3cfa967a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484970378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.1484970378
Directory /workspace/46.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/46.uart_smoke.3232866169
Short name T533
Test name
Test status
Simulation time 294602097 ps
CPU time 1.14 seconds
Started Jun 07 07:25:17 PM PDT 24
Finished Jun 07 07:25:25 PM PDT 24
Peak memory 198828 kb
Host smart-60f46e29-3bd4-4787-b0f3-4adf59c4a421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232866169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_smoke.3232866169
Directory /workspace/46.uart_smoke/latest

Test location /workspace/coverage/default/46.uart_tx_ovrd.3952285657
Short name T375
Test name
Test status
Simulation time 343771731 ps
CPU time 1.8 seconds
Started Jun 07 07:25:21 PM PDT 24
Finished Jun 07 07:25:29 PM PDT 24
Peak memory 198848 kb
Host smart-babd7e26-ac6b-4d55-b224-4aa0b76e0659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952285657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.3952285657
Directory /workspace/46.uart_tx_ovrd/latest

Test location /workspace/coverage/default/46.uart_tx_rx.4038672265
Short name T656
Test name
Test status
Simulation time 115473553988 ps
CPU time 42.91 seconds
Started Jun 07 07:25:18 PM PDT 24
Finished Jun 07 07:26:08 PM PDT 24
Peak memory 200344 kb
Host smart-d5cbbe96-9059-4598-bd88-c65b7df74300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038672265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.4038672265
Directory /workspace/46.uart_tx_rx/latest

Test location /workspace/coverage/default/47.uart_alert_test.834526831
Short name T606
Test name
Test status
Simulation time 36718509 ps
CPU time 0.54 seconds
Started Jun 07 07:25:25 PM PDT 24
Finished Jun 07 07:25:31 PM PDT 24
Peak memory 195780 kb
Host smart-32acbd74-5d55-4fe5-be67-c0a12d4941b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834526831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.834526831
Directory /workspace/47.uart_alert_test/latest

Test location /workspace/coverage/default/47.uart_fifo_full.3973109456
Short name T514
Test name
Test status
Simulation time 27953320183 ps
CPU time 48.95 seconds
Started Jun 07 07:25:26 PM PDT 24
Finished Jun 07 07:26:20 PM PDT 24
Peak memory 200400 kb
Host smart-aca23f73-18f6-4704-9d53-c6303da49517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973109456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.3973109456
Directory /workspace/47.uart_fifo_full/latest

Test location /workspace/coverage/default/47.uart_fifo_overflow.3674146208
Short name T761
Test name
Test status
Simulation time 153107858524 ps
CPU time 111.68 seconds
Started Jun 07 07:25:27 PM PDT 24
Finished Jun 07 07:27:24 PM PDT 24
Peak memory 200184 kb
Host smart-79e490dc-e862-4568-a0c6-b80543eef3c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674146208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.3674146208
Directory /workspace/47.uart_fifo_overflow/latest

Test location /workspace/coverage/default/47.uart_intr.1393286936
Short name T639
Test name
Test status
Simulation time 35308052096 ps
CPU time 52.01 seconds
Started Jun 07 07:25:29 PM PDT 24
Finished Jun 07 07:26:26 PM PDT 24
Peak memory 199532 kb
Host smart-5f383900-ef51-43b7-8762-80e204d9989e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393286936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.1393286936
Directory /workspace/47.uart_intr/latest

Test location /workspace/coverage/default/47.uart_long_xfer_wo_dly.4263823320
Short name T684
Test name
Test status
Simulation time 261759812145 ps
CPU time 180.55 seconds
Started Jun 07 07:25:25 PM PDT 24
Finished Jun 07 07:28:31 PM PDT 24
Peak memory 200332 kb
Host smart-f20fcc37-c87a-4d36-988e-183359edac12
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4263823320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.4263823320
Directory /workspace/47.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/47.uart_loopback.2200440981
Short name T394
Test name
Test status
Simulation time 4469333657 ps
CPU time 3.63 seconds
Started Jun 07 07:25:25 PM PDT 24
Finished Jun 07 07:25:34 PM PDT 24
Peak memory 199120 kb
Host smart-c6b5e4dd-a29b-4d03-9d01-03066f603311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200440981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_loopback.2200440981
Directory /workspace/47.uart_loopback/latest

Test location /workspace/coverage/default/47.uart_perf.1820345050
Short name T830
Test name
Test status
Simulation time 23280260777 ps
CPU time 299.85 seconds
Started Jun 07 07:25:25 PM PDT 24
Finished Jun 07 07:30:31 PM PDT 24
Peak memory 200352 kb
Host smart-0e3a211c-edf4-4d45-91e0-57e2ff3b4bf4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1820345050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.1820345050
Directory /workspace/47.uart_perf/latest

Test location /workspace/coverage/default/47.uart_rx_oversample.647409979
Short name T620
Test name
Test status
Simulation time 6816271700 ps
CPU time 32.12 seconds
Started Jun 07 07:25:24 PM PDT 24
Finished Jun 07 07:26:02 PM PDT 24
Peak memory 199420 kb
Host smart-59dae623-67cd-493f-88c1-f3207a554c2d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=647409979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.647409979
Directory /workspace/47.uart_rx_oversample/latest

Test location /workspace/coverage/default/47.uart_rx_parity_err.1301946320
Short name T290
Test name
Test status
Simulation time 57745105394 ps
CPU time 20.18 seconds
Started Jun 07 07:25:26 PM PDT 24
Finished Jun 07 07:25:51 PM PDT 24
Peak memory 199112 kb
Host smart-1d5b7295-8964-46a9-83e7-90f7594ca80b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301946320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.1301946320
Directory /workspace/47.uart_rx_parity_err/latest

Test location /workspace/coverage/default/47.uart_rx_start_bit_filter.2248333580
Short name T650
Test name
Test status
Simulation time 34611658372 ps
CPU time 22.95 seconds
Started Jun 07 07:25:28 PM PDT 24
Finished Jun 07 07:25:55 PM PDT 24
Peak memory 196628 kb
Host smart-6592d926-5bef-4c43-8032-18b92d908b0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248333580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.2248333580
Directory /workspace/47.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/47.uart_smoke.2265840108
Short name T669
Test name
Test status
Simulation time 293341169 ps
CPU time 1.49 seconds
Started Jun 07 07:25:20 PM PDT 24
Finished Jun 07 07:25:28 PM PDT 24
Peak memory 198700 kb
Host smart-d395190d-98c8-4f4d-a32c-d8a510f5dd38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265840108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_smoke.2265840108
Directory /workspace/47.uart_smoke/latest

Test location /workspace/coverage/default/47.uart_tx_ovrd.3611892419
Short name T732
Test name
Test status
Simulation time 2753335700 ps
CPU time 2.84 seconds
Started Jun 07 07:25:25 PM PDT 24
Finished Jun 07 07:25:33 PM PDT 24
Peak memory 199476 kb
Host smart-8530f324-437a-4c05-b1bc-343f42f3a3ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611892419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.3611892419
Directory /workspace/47.uart_tx_ovrd/latest

Test location /workspace/coverage/default/47.uart_tx_rx.1860805321
Short name T465
Test name
Test status
Simulation time 34128165199 ps
CPU time 31.6 seconds
Started Jun 07 07:25:25 PM PDT 24
Finished Jun 07 07:26:02 PM PDT 24
Peak memory 200408 kb
Host smart-37d32a0c-a430-4dc4-ae94-89d20e199549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860805321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.1860805321
Directory /workspace/47.uart_tx_rx/latest

Test location /workspace/coverage/default/48.uart_alert_test.3606722795
Short name T947
Test name
Test status
Simulation time 19806173 ps
CPU time 0.54 seconds
Started Jun 07 07:25:34 PM PDT 24
Finished Jun 07 07:25:39 PM PDT 24
Peak memory 196044 kb
Host smart-0fa719c0-d226-4a82-8f78-ec969e13aec3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606722795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.3606722795
Directory /workspace/48.uart_alert_test/latest

Test location /workspace/coverage/default/48.uart_fifo_full.1713988268
Short name T610
Test name
Test status
Simulation time 87510977215 ps
CPU time 215.25 seconds
Started Jun 07 07:25:24 PM PDT 24
Finished Jun 07 07:29:04 PM PDT 24
Peak memory 200232 kb
Host smart-04ab5b55-97a4-4f4b-a964-80ef4ac3d82b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713988268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.1713988268
Directory /workspace/48.uart_fifo_full/latest

Test location /workspace/coverage/default/48.uart_fifo_overflow.2540103774
Short name T451
Test name
Test status
Simulation time 86147807088 ps
CPU time 139.92 seconds
Started Jun 07 07:25:28 PM PDT 24
Finished Jun 07 07:27:53 PM PDT 24
Peak memory 200360 kb
Host smart-d2cbea03-9e57-4c56-ac44-c8a510e1aed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540103774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.2540103774
Directory /workspace/48.uart_fifo_overflow/latest

Test location /workspace/coverage/default/48.uart_fifo_reset.1337004692
Short name T159
Test name
Test status
Simulation time 493289881747 ps
CPU time 79.48 seconds
Started Jun 07 07:25:26 PM PDT 24
Finished Jun 07 07:26:51 PM PDT 24
Peak memory 200348 kb
Host smart-d616e854-d93e-40ae-83ae-f3c7d874838f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337004692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.1337004692
Directory /workspace/48.uart_fifo_reset/latest

Test location /workspace/coverage/default/48.uart_intr.1882413547
Short name T988
Test name
Test status
Simulation time 26825432424 ps
CPU time 9.5 seconds
Started Jun 07 07:25:27 PM PDT 24
Finished Jun 07 07:25:42 PM PDT 24
Peak memory 198760 kb
Host smart-f5314a84-9e3c-41c5-8f78-36e3e95e4359
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882413547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.1882413547
Directory /workspace/48.uart_intr/latest

Test location /workspace/coverage/default/48.uart_long_xfer_wo_dly.4136398744
Short name T1085
Test name
Test status
Simulation time 200176107500 ps
CPU time 436.74 seconds
Started Jun 07 07:25:34 PM PDT 24
Finished Jun 07 07:32:55 PM PDT 24
Peak memory 200368 kb
Host smart-85304c22-4c38-4197-9fe3-2871c3461a09
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4136398744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.4136398744
Directory /workspace/48.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/48.uart_loopback.2556524578
Short name T694
Test name
Test status
Simulation time 11699491606 ps
CPU time 9.88 seconds
Started Jun 07 07:25:35 PM PDT 24
Finished Jun 07 07:25:50 PM PDT 24
Peak memory 200188 kb
Host smart-387604f6-8637-4922-90c2-56a960423c51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556524578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_loopback.2556524578
Directory /workspace/48.uart_loopback/latest

Test location /workspace/coverage/default/48.uart_noise_filter.305683542
Short name T655
Test name
Test status
Simulation time 155984427234 ps
CPU time 84.62 seconds
Started Jun 07 07:25:32 PM PDT 24
Finished Jun 07 07:27:01 PM PDT 24
Peak memory 200336 kb
Host smart-e0b1e76a-e419-46b6-8787-90f7d6749ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305683542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_noise_filter.305683542
Directory /workspace/48.uart_noise_filter/latest

Test location /workspace/coverage/default/48.uart_perf.492717010
Short name T999
Test name
Test status
Simulation time 16376887561 ps
CPU time 439.36 seconds
Started Jun 07 07:25:33 PM PDT 24
Finished Jun 07 07:32:56 PM PDT 24
Peak memory 200300 kb
Host smart-4bafa4a7-6b41-4a5c-9bc9-4f4ca26da17b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=492717010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.492717010
Directory /workspace/48.uart_perf/latest

Test location /workspace/coverage/default/48.uart_rx_oversample.2224388471
Short name T659
Test name
Test status
Simulation time 3364010816 ps
CPU time 6.54 seconds
Started Jun 07 07:25:29 PM PDT 24
Finished Jun 07 07:25:40 PM PDT 24
Peak memory 198760 kb
Host smart-7fa20556-8650-4704-8636-49e6d7e6245e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2224388471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.2224388471
Directory /workspace/48.uart_rx_oversample/latest

Test location /workspace/coverage/default/48.uart_rx_parity_err.368452106
Short name T1032
Test name
Test status
Simulation time 126704646885 ps
CPU time 61.98 seconds
Started Jun 07 07:25:36 PM PDT 24
Finished Jun 07 07:26:42 PM PDT 24
Peak memory 200312 kb
Host smart-2e539475-c914-4a7a-8d01-413950690f72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368452106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.368452106
Directory /workspace/48.uart_rx_parity_err/latest

Test location /workspace/coverage/default/48.uart_rx_start_bit_filter.1361354723
Short name T722
Test name
Test status
Simulation time 58328917232 ps
CPU time 24.1 seconds
Started Jun 07 07:25:35 PM PDT 24
Finished Jun 07 07:26:04 PM PDT 24
Peak memory 196124 kb
Host smart-334ca703-d3c1-44f0-965c-b32493d595e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361354723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.1361354723
Directory /workspace/48.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/48.uart_smoke.132967025
Short name T300
Test name
Test status
Simulation time 452416845 ps
CPU time 2.73 seconds
Started Jun 07 07:25:26 PM PDT 24
Finished Jun 07 07:25:34 PM PDT 24
Peak memory 199140 kb
Host smart-83351767-3b0e-4d14-96ee-7dfcd201e195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132967025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_smoke.132967025
Directory /workspace/48.uart_smoke/latest

Test location /workspace/coverage/default/48.uart_stress_all_with_rand_reset.1465040983
Short name T231
Test name
Test status
Simulation time 1818998996518 ps
CPU time 1238.61 seconds
Started Jun 07 07:25:34 PM PDT 24
Finished Jun 07 07:46:18 PM PDT 24
Peak memory 231744 kb
Host smart-3fc67d4c-fa05-4ad9-b6ee-75f9bd2ee5ba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465040983 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 48.uart_stress_all_with_rand_reset.1465040983
Directory /workspace/48.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.uart_tx_ovrd.4155712400
Short name T21
Test name
Test status
Simulation time 930722915 ps
CPU time 2.13 seconds
Started Jun 07 07:25:32 PM PDT 24
Finished Jun 07 07:25:38 PM PDT 24
Peak memory 198696 kb
Host smart-ca8f9353-208e-4db7-aff8-f7b1b24dc060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155712400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.4155712400
Directory /workspace/48.uart_tx_ovrd/latest

Test location /workspace/coverage/default/48.uart_tx_rx.3556057829
Short name T940
Test name
Test status
Simulation time 17364227806 ps
CPU time 11.74 seconds
Started Jun 07 07:25:24 PM PDT 24
Finished Jun 07 07:25:41 PM PDT 24
Peak memory 200364 kb
Host smart-b7da766e-3997-4995-95ee-08bf88e11805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556057829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.3556057829
Directory /workspace/48.uart_tx_rx/latest

Test location /workspace/coverage/default/49.uart_alert_test.3596387263
Short name T702
Test name
Test status
Simulation time 12491696 ps
CPU time 0.57 seconds
Started Jun 07 07:25:43 PM PDT 24
Finished Jun 07 07:25:49 PM PDT 24
Peak memory 195428 kb
Host smart-06f72503-68aa-468b-b14a-64e3c7cafaff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596387263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.3596387263
Directory /workspace/49.uart_alert_test/latest

Test location /workspace/coverage/default/49.uart_fifo_full.2528765760
Short name T425
Test name
Test status
Simulation time 21853602300 ps
CPU time 37.62 seconds
Started Jun 07 07:25:33 PM PDT 24
Finished Jun 07 07:26:15 PM PDT 24
Peak memory 200388 kb
Host smart-4fa5ed77-84e8-42c3-8d1f-c300243eb82b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528765760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.2528765760
Directory /workspace/49.uart_fifo_full/latest

Test location /workspace/coverage/default/49.uart_fifo_overflow.936782635
Short name T158
Test name
Test status
Simulation time 84147875783 ps
CPU time 69.75 seconds
Started Jun 07 07:25:32 PM PDT 24
Finished Jun 07 07:26:46 PM PDT 24
Peak memory 200340 kb
Host smart-6a5c25a4-ea06-47df-87fa-7f5180b9dba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936782635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.936782635
Directory /workspace/49.uart_fifo_overflow/latest

Test location /workspace/coverage/default/49.uart_fifo_reset.373984323
Short name T349
Test name
Test status
Simulation time 99008815055 ps
CPU time 46.38 seconds
Started Jun 07 07:25:32 PM PDT 24
Finished Jun 07 07:26:23 PM PDT 24
Peak memory 200344 kb
Host smart-fdf489a7-44e6-4213-9346-14da3d7945ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373984323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.373984323
Directory /workspace/49.uart_fifo_reset/latest

Test location /workspace/coverage/default/49.uart_intr.578747938
Short name T468
Test name
Test status
Simulation time 79739354266 ps
CPU time 74.84 seconds
Started Jun 07 07:25:32 PM PDT 24
Finished Jun 07 07:26:51 PM PDT 24
Peak memory 198892 kb
Host smart-b3224ea7-bfcc-4fff-9d0e-658392ea5181
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578747938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.578747938
Directory /workspace/49.uart_intr/latest

Test location /workspace/coverage/default/49.uart_long_xfer_wo_dly.1353126185
Short name T56
Test name
Test status
Simulation time 150203199960 ps
CPU time 298.15 seconds
Started Jun 07 07:25:41 PM PDT 24
Finished Jun 07 07:30:44 PM PDT 24
Peak memory 200392 kb
Host smart-a1f7e31e-8b25-4842-babd-a13db40b60cb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1353126185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.1353126185
Directory /workspace/49.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/49.uart_loopback.3267013993
Short name T361
Test name
Test status
Simulation time 8196650646 ps
CPU time 11.48 seconds
Started Jun 07 07:25:43 PM PDT 24
Finished Jun 07 07:26:00 PM PDT 24
Peak memory 200000 kb
Host smart-6226e36b-165d-41d7-8d58-5b155831452b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267013993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_loopback.3267013993
Directory /workspace/49.uart_loopback/latest

Test location /workspace/coverage/default/49.uart_perf.340896850
Short name T873
Test name
Test status
Simulation time 8117093413 ps
CPU time 409.34 seconds
Started Jun 07 07:25:42 PM PDT 24
Finished Jun 07 07:32:37 PM PDT 24
Peak memory 200320 kb
Host smart-911fe983-6247-416a-bf0f-fdaf442d48a1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=340896850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.340896850
Directory /workspace/49.uart_perf/latest

Test location /workspace/coverage/default/49.uart_rx_oversample.2352060010
Short name T357
Test name
Test status
Simulation time 4960463634 ps
CPU time 38.43 seconds
Started Jun 07 07:25:34 PM PDT 24
Finished Jun 07 07:26:17 PM PDT 24
Peak memory 199936 kb
Host smart-abde62ad-3965-4b9c-84ee-84cbd243116a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2352060010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.2352060010
Directory /workspace/49.uart_rx_oversample/latest

Test location /workspace/coverage/default/49.uart_rx_parity_err.3719365683
Short name T910
Test name
Test status
Simulation time 156864681069 ps
CPU time 262.43 seconds
Started Jun 07 07:25:33 PM PDT 24
Finished Jun 07 07:30:00 PM PDT 24
Peak memory 200352 kb
Host smart-94b6cda1-2589-4104-a645-e3fb31860cd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719365683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.3719365683
Directory /workspace/49.uart_rx_parity_err/latest

Test location /workspace/coverage/default/49.uart_rx_start_bit_filter.2147782585
Short name T547
Test name
Test status
Simulation time 33491724754 ps
CPU time 14.84 seconds
Started Jun 07 07:25:33 PM PDT 24
Finished Jun 07 07:25:52 PM PDT 24
Peak memory 196328 kb
Host smart-df6a1143-f199-430f-b9d8-8f5daeb25015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147782585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.2147782585
Directory /workspace/49.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/49.uart_smoke.411430606
Short name T1043
Test name
Test status
Simulation time 629958467 ps
CPU time 2.01 seconds
Started Jun 07 07:25:33 PM PDT 24
Finished Jun 07 07:25:40 PM PDT 24
Peak memory 199904 kb
Host smart-ddc48673-ee3e-45e8-94cd-5267c111589a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411430606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_smoke.411430606
Directory /workspace/49.uart_smoke/latest

Test location /workspace/coverage/default/49.uart_stress_all.1229484068
Short name T794
Test name
Test status
Simulation time 194841482214 ps
CPU time 429.3 seconds
Started Jun 07 07:25:41 PM PDT 24
Finished Jun 07 07:32:55 PM PDT 24
Peak memory 200332 kb
Host smart-80026517-34e3-481f-bda8-9d9e44e51bb6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229484068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.1229484068
Directory /workspace/49.uart_stress_all/latest

Test location /workspace/coverage/default/49.uart_tx_ovrd.1609223353
Short name T730
Test name
Test status
Simulation time 2094808547 ps
CPU time 2.52 seconds
Started Jun 07 07:25:42 PM PDT 24
Finished Jun 07 07:25:50 PM PDT 24
Peak memory 200204 kb
Host smart-60d5475a-e0b1-4640-bf15-fde5566eb62e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609223353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.1609223353
Directory /workspace/49.uart_tx_ovrd/latest

Test location /workspace/coverage/default/49.uart_tx_rx.1726932222
Short name T423
Test name
Test status
Simulation time 92702106584 ps
CPU time 79.06 seconds
Started Jun 07 07:25:35 PM PDT 24
Finished Jun 07 07:26:58 PM PDT 24
Peak memory 200288 kb
Host smart-8005f03a-5773-4b8e-8c8c-679c468d42b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726932222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.1726932222
Directory /workspace/49.uart_tx_rx/latest

Test location /workspace/coverage/default/5.uart_alert_test.2982133176
Short name T993
Test name
Test status
Simulation time 16624670 ps
CPU time 0.58 seconds
Started Jun 07 07:20:05 PM PDT 24
Finished Jun 07 07:20:30 PM PDT 24
Peak memory 194716 kb
Host smart-67ba7295-cdd9-4a2e-b43d-a26c712cbdd1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982133176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.2982133176
Directory /workspace/5.uart_alert_test/latest

Test location /workspace/coverage/default/5.uart_fifo_full.770420357
Short name T1065
Test name
Test status
Simulation time 69734937663 ps
CPU time 47.57 seconds
Started Jun 07 07:20:10 PM PDT 24
Finished Jun 07 07:21:22 PM PDT 24
Peak memory 200392 kb
Host smart-674a3095-c93e-4cb7-82fb-c75e057328a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770420357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.770420357
Directory /workspace/5.uart_fifo_full/latest

Test location /workspace/coverage/default/5.uart_fifo_overflow.1857900731
Short name T974
Test name
Test status
Simulation time 107282384388 ps
CPU time 46.36 seconds
Started Jun 07 07:20:15 PM PDT 24
Finished Jun 07 07:21:25 PM PDT 24
Peak memory 200404 kb
Host smart-122e2f35-9ffe-40b0-b829-9010bd09f5f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857900731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.1857900731
Directory /workspace/5.uart_fifo_overflow/latest

Test location /workspace/coverage/default/5.uart_fifo_reset.629546984
Short name T998
Test name
Test status
Simulation time 51742571262 ps
CPU time 47.72 seconds
Started Jun 07 07:20:07 PM PDT 24
Finished Jun 07 07:21:20 PM PDT 24
Peak memory 200368 kb
Host smart-505dbdfb-784c-47ee-a9c9-3e8b78c3b9d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629546984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.629546984
Directory /workspace/5.uart_fifo_reset/latest

Test location /workspace/coverage/default/5.uart_intr.2378153077
Short name T488
Test name
Test status
Simulation time 31031072007 ps
CPU time 33.2 seconds
Started Jun 07 07:20:06 PM PDT 24
Finished Jun 07 07:21:04 PM PDT 24
Peak memory 200432 kb
Host smart-ac06116b-c5f7-4a07-bef7-54b6ec99438d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378153077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.2378153077
Directory /workspace/5.uart_intr/latest

Test location /workspace/coverage/default/5.uart_long_xfer_wo_dly.3567073450
Short name T658
Test name
Test status
Simulation time 172751891463 ps
CPU time 125.85 seconds
Started Jun 07 07:20:08 PM PDT 24
Finished Jun 07 07:22:38 PM PDT 24
Peak memory 200380 kb
Host smart-ed25fb39-baa4-4663-84cc-a2eb1628154a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3567073450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.3567073450
Directory /workspace/5.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/5.uart_loopback.2822543836
Short name T944
Test name
Test status
Simulation time 2674674101 ps
CPU time 2.82 seconds
Started Jun 07 07:20:09 PM PDT 24
Finished Jun 07 07:20:35 PM PDT 24
Peak memory 196096 kb
Host smart-68af77c1-ec32-42c1-8641-8d1b5ce623f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822543836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_loopback.2822543836
Directory /workspace/5.uart_loopback/latest

Test location /workspace/coverage/default/5.uart_perf.3277929992
Short name T546
Test name
Test status
Simulation time 8381578578 ps
CPU time 494.21 seconds
Started Jun 07 07:20:08 PM PDT 24
Finished Jun 07 07:28:47 PM PDT 24
Peak memory 200360 kb
Host smart-c383a6ca-e1fe-4c41-becb-1251e3793eff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3277929992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.3277929992
Directory /workspace/5.uart_perf/latest

Test location /workspace/coverage/default/5.uart_rx_oversample.3436793190
Short name T973
Test name
Test status
Simulation time 3489597517 ps
CPU time 29.49 seconds
Started Jun 07 07:20:08 PM PDT 24
Finished Jun 07 07:21:02 PM PDT 24
Peak memory 199480 kb
Host smart-a6cb403c-c1b5-4fd7-8567-91caa74a9e2d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3436793190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.3436793190
Directory /workspace/5.uart_rx_oversample/latest

Test location /workspace/coverage/default/5.uart_rx_parity_err.369085438
Short name T1041
Test name
Test status
Simulation time 90223330185 ps
CPU time 31.78 seconds
Started Jun 07 07:20:07 PM PDT 24
Finished Jun 07 07:21:03 PM PDT 24
Peak memory 200224 kb
Host smart-4de106a4-a168-4a48-a76f-0b00d0cafba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369085438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.369085438
Directory /workspace/5.uart_rx_parity_err/latest

Test location /workspace/coverage/default/5.uart_rx_start_bit_filter.1449837946
Short name T366
Test name
Test status
Simulation time 4969619038 ps
CPU time 2.89 seconds
Started Jun 07 07:20:06 PM PDT 24
Finished Jun 07 07:20:34 PM PDT 24
Peak memory 196608 kb
Host smart-afbfb9d6-0c4f-4d34-b470-87daefcad3de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449837946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.1449837946
Directory /workspace/5.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/5.uart_smoke.3056172613
Short name T535
Test name
Test status
Simulation time 645636627 ps
CPU time 3.24 seconds
Started Jun 07 07:20:09 PM PDT 24
Finished Jun 07 07:20:37 PM PDT 24
Peak memory 199232 kb
Host smart-aed1153c-080d-4235-8529-9576695d4625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056172613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_smoke.3056172613
Directory /workspace/5.uart_smoke/latest

Test location /workspace/coverage/default/5.uart_stress_all.710905608
Short name T168
Test name
Test status
Simulation time 827240114230 ps
CPU time 172.31 seconds
Started Jun 07 07:20:10 PM PDT 24
Finished Jun 07 07:23:27 PM PDT 24
Peak memory 200404 kb
Host smart-d4f76747-f4f4-4b93-8ff1-4dd8252add3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710905608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.710905608
Directory /workspace/5.uart_stress_all/latest

Test location /workspace/coverage/default/5.uart_tx_ovrd.1662959969
Short name T536
Test name
Test status
Simulation time 8340838147 ps
CPU time 12.95 seconds
Started Jun 07 07:20:09 PM PDT 24
Finished Jun 07 07:20:46 PM PDT 24
Peak memory 200092 kb
Host smart-2c4dc1af-d166-4995-8816-79938a7a572a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662959969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.1662959969
Directory /workspace/5.uart_tx_ovrd/latest

Test location /workspace/coverage/default/5.uart_tx_rx.3041494854
Short name T565
Test name
Test status
Simulation time 72887645042 ps
CPU time 74.1 seconds
Started Jun 07 07:20:10 PM PDT 24
Finished Jun 07 07:21:48 PM PDT 24
Peak memory 200332 kb
Host smart-3bf54ffe-9299-4cd0-9910-dddb80231f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041494854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.3041494854
Directory /workspace/5.uart_tx_rx/latest

Test location /workspace/coverage/default/50.uart_fifo_reset.4282568929
Short name T323
Test name
Test status
Simulation time 13165728640 ps
CPU time 22.26 seconds
Started Jun 07 07:25:41 PM PDT 24
Finished Jun 07 07:26:09 PM PDT 24
Peak memory 200316 kb
Host smart-2f634ac5-c516-4f65-ab14-c5bfaa30284d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282568929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.4282568929
Directory /workspace/50.uart_fifo_reset/latest

Test location /workspace/coverage/default/51.uart_fifo_reset.1333799414
Short name T404
Test name
Test status
Simulation time 103166294001 ps
CPU time 43.91 seconds
Started Jun 07 07:25:40 PM PDT 24
Finished Jun 07 07:26:30 PM PDT 24
Peak memory 200268 kb
Host smart-5741745b-9f29-46e6-a58e-9aef37396df3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333799414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.1333799414
Directory /workspace/51.uart_fifo_reset/latest

Test location /workspace/coverage/default/52.uart_fifo_reset.2023945568
Short name T202
Test name
Test status
Simulation time 111806928521 ps
CPU time 187.82 seconds
Started Jun 07 07:25:41 PM PDT 24
Finished Jun 07 07:28:54 PM PDT 24
Peak memory 200324 kb
Host smart-5c86526e-5684-473a-942d-cbd2b9bc4f1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023945568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.2023945568
Directory /workspace/52.uart_fifo_reset/latest

Test location /workspace/coverage/default/52.uart_stress_all_with_rand_reset.4052013102
Short name T497
Test name
Test status
Simulation time 26463362536 ps
CPU time 227.73 seconds
Started Jun 07 07:25:44 PM PDT 24
Finished Jun 07 07:29:37 PM PDT 24
Peak memory 216244 kb
Host smart-f9bce0ce-bd1c-476b-bf44-5c26514a0820
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052013102 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 52.uart_stress_all_with_rand_reset.4052013102
Directory /workspace/52.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/53.uart_fifo_reset.3812054391
Short name T787
Test name
Test status
Simulation time 182531424177 ps
CPU time 593.43 seconds
Started Jun 07 07:25:44 PM PDT 24
Finished Jun 07 07:35:43 PM PDT 24
Peak memory 200352 kb
Host smart-0ee2b60d-45b8-48d1-982c-0fddfd7738df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812054391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.3812054391
Directory /workspace/53.uart_fifo_reset/latest

Test location /workspace/coverage/default/54.uart_fifo_reset.3694737301
Short name T884
Test name
Test status
Simulation time 19211617088 ps
CPU time 14.13 seconds
Started Jun 07 07:25:45 PM PDT 24
Finished Jun 07 07:26:05 PM PDT 24
Peak memory 200432 kb
Host smart-7ff72328-232f-48f0-bc09-77c99192b69a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694737301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.3694737301
Directory /workspace/54.uart_fifo_reset/latest

Test location /workspace/coverage/default/55.uart_fifo_reset.3803169468
Short name T748
Test name
Test status
Simulation time 117086997478 ps
CPU time 182.07 seconds
Started Jun 07 07:25:43 PM PDT 24
Finished Jun 07 07:28:51 PM PDT 24
Peak memory 200408 kb
Host smart-977f65b7-4d59-4583-bb34-3398a6e24e49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803169468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.3803169468
Directory /workspace/55.uart_fifo_reset/latest

Test location /workspace/coverage/default/56.uart_fifo_reset.602901929
Short name T945
Test name
Test status
Simulation time 105846802153 ps
CPU time 173.05 seconds
Started Jun 07 07:25:45 PM PDT 24
Finished Jun 07 07:28:44 PM PDT 24
Peak memory 200436 kb
Host smart-3a0f5c2a-585b-4804-8d60-f7f9f513104d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602901929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.602901929
Directory /workspace/56.uart_fifo_reset/latest

Test location /workspace/coverage/default/56.uart_stress_all_with_rand_reset.4210817181
Short name T108
Test name
Test status
Simulation time 32016297842 ps
CPU time 328.02 seconds
Started Jun 07 07:25:44 PM PDT 24
Finished Jun 07 07:31:17 PM PDT 24
Peak memory 215644 kb
Host smart-9f104812-476e-46c5-9066-f20db448a695
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210817181 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 56.uart_stress_all_with_rand_reset.4210817181
Directory /workspace/56.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.uart_fifo_reset.302887074
Short name T775
Test name
Test status
Simulation time 111571789240 ps
CPU time 156.02 seconds
Started Jun 07 07:25:44 PM PDT 24
Finished Jun 07 07:28:26 PM PDT 24
Peak memory 200360 kb
Host smart-829005ef-a501-4ae6-88ee-7c4c77524d3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302887074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.302887074
Directory /workspace/57.uart_fifo_reset/latest

Test location /workspace/coverage/default/57.uart_stress_all_with_rand_reset.4064872068
Short name T344
Test name
Test status
Simulation time 12999791183 ps
CPU time 371.82 seconds
Started Jun 07 07:25:44 PM PDT 24
Finished Jun 07 07:32:01 PM PDT 24
Peak memory 216252 kb
Host smart-d72caa9c-a237-47c4-9849-bc5796e9a9d4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064872068 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 57.uart_stress_all_with_rand_reset.4064872068
Directory /workspace/57.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/58.uart_fifo_reset.897999499
Short name T504
Test name
Test status
Simulation time 156209478625 ps
CPU time 102.3 seconds
Started Jun 07 07:25:44 PM PDT 24
Finished Jun 07 07:27:32 PM PDT 24
Peak memory 200484 kb
Host smart-7aaf2360-abda-4beb-85bc-4d3c87961557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897999499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.897999499
Directory /workspace/58.uart_fifo_reset/latest

Test location /workspace/coverage/default/58.uart_stress_all_with_rand_reset.3272057442
Short name T772
Test name
Test status
Simulation time 67870527524 ps
CPU time 81.1 seconds
Started Jun 07 07:25:40 PM PDT 24
Finished Jun 07 07:27:06 PM PDT 24
Peak memory 216928 kb
Host smart-b90b1e53-4414-49b2-8e04-bf18191fecc2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272057442 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 58.uart_stress_all_with_rand_reset.3272057442
Directory /workspace/58.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_alert_test.3006516560
Short name T841
Test name
Test status
Simulation time 15499715 ps
CPU time 0.61 seconds
Started Jun 07 07:20:17 PM PDT 24
Finished Jun 07 07:20:41 PM PDT 24
Peak memory 196044 kb
Host smart-af87c145-9c31-43d2-a38e-a13976163d96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006516560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.3006516560
Directory /workspace/6.uart_alert_test/latest

Test location /workspace/coverage/default/6.uart_fifo_full.1607809734
Short name T737
Test name
Test status
Simulation time 36897637435 ps
CPU time 12.32 seconds
Started Jun 07 07:20:10 PM PDT 24
Finished Jun 07 07:20:47 PM PDT 24
Peak memory 200392 kb
Host smart-c2154cd0-17eb-42be-a02c-0efcec3a0d53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607809734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.1607809734
Directory /workspace/6.uart_fifo_full/latest

Test location /workspace/coverage/default/6.uart_fifo_overflow.4254760903
Short name T856
Test name
Test status
Simulation time 162791925500 ps
CPU time 493.6 seconds
Started Jun 07 07:20:07 PM PDT 24
Finished Jun 07 07:28:46 PM PDT 24
Peak memory 200492 kb
Host smart-0c314a83-c04b-4862-867d-42b0e346f9b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254760903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.4254760903
Directory /workspace/6.uart_fifo_overflow/latest

Test location /workspace/coverage/default/6.uart_fifo_reset.4124941394
Short name T550
Test name
Test status
Simulation time 49051140136 ps
CPU time 18.44 seconds
Started Jun 07 07:20:14 PM PDT 24
Finished Jun 07 07:20:57 PM PDT 24
Peak memory 199864 kb
Host smart-9da81d2f-916b-412e-a18e-0850255f986f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124941394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.4124941394
Directory /workspace/6.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_intr.104689906
Short name T335
Test name
Test status
Simulation time 304053305163 ps
CPU time 166.06 seconds
Started Jun 07 07:20:09 PM PDT 24
Finished Jun 07 07:23:19 PM PDT 24
Peak memory 200252 kb
Host smart-cb99e452-cd42-4887-a34b-814d03366092
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104689906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.104689906
Directory /workspace/6.uart_intr/latest

Test location /workspace/coverage/default/6.uart_long_xfer_wo_dly.2732576740
Short name T906
Test name
Test status
Simulation time 110144295680 ps
CPU time 744.02 seconds
Started Jun 07 07:20:16 PM PDT 24
Finished Jun 07 07:33:04 PM PDT 24
Peak memory 200172 kb
Host smart-f28d032d-3259-4e96-ae1e-46aed1317752
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2732576740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.2732576740
Directory /workspace/6.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/6.uart_loopback.680983857
Short name T403
Test name
Test status
Simulation time 4766635343 ps
CPU time 5.22 seconds
Started Jun 07 07:20:07 PM PDT 24
Finished Jun 07 07:20:36 PM PDT 24
Peak memory 199240 kb
Host smart-e982d512-cdb1-4bca-9f2e-eb4e3e8cf845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680983857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_loopback.680983857
Directory /workspace/6.uart_loopback/latest

Test location /workspace/coverage/default/6.uart_perf.2365704694
Short name T291
Test name
Test status
Simulation time 13487878316 ps
CPU time 759.52 seconds
Started Jun 07 07:20:16 PM PDT 24
Finished Jun 07 07:33:20 PM PDT 24
Peak memory 200208 kb
Host smart-93c93b1f-541a-4ca7-a909-9ded3b928f7a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2365704694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.2365704694
Directory /workspace/6.uart_perf/latest

Test location /workspace/coverage/default/6.uart_rx_oversample.2249856
Short name T786
Test name
Test status
Simulation time 6143641230 ps
CPU time 13.45 seconds
Started Jun 07 07:20:10 PM PDT 24
Finished Jun 07 07:20:48 PM PDT 24
Peak memory 200364 kb
Host smart-292c0b40-8628-4991-b55a-82f55496c060
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2249856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.2249856
Directory /workspace/6.uart_rx_oversample/latest

Test location /workspace/coverage/default/6.uart_rx_parity_err.4050538734
Short name T960
Test name
Test status
Simulation time 37486045127 ps
CPU time 62.57 seconds
Started Jun 07 07:20:14 PM PDT 24
Finished Jun 07 07:21:41 PM PDT 24
Peak memory 200380 kb
Host smart-f2231a30-3c01-45ae-a3f1-c8eefa7936c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050538734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.4050538734
Directory /workspace/6.uart_rx_parity_err/latest

Test location /workspace/coverage/default/6.uart_rx_start_bit_filter.3526511007
Short name T867
Test name
Test status
Simulation time 508940099 ps
CPU time 1.39 seconds
Started Jun 07 07:20:07 PM PDT 24
Finished Jun 07 07:20:34 PM PDT 24
Peak memory 195832 kb
Host smart-d7ac0d8d-51c8-4806-a0fa-7051189f7cd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526511007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.3526511007
Directory /workspace/6.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/6.uart_smoke.3485508688
Short name T371
Test name
Test status
Simulation time 933748668 ps
CPU time 2.74 seconds
Started Jun 07 07:20:08 PM PDT 24
Finished Jun 07 07:20:35 PM PDT 24
Peak memory 198648 kb
Host smart-3f255982-19a4-4ccc-8b08-1adc14d83c2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485508688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_smoke.3485508688
Directory /workspace/6.uart_smoke/latest

Test location /workspace/coverage/default/6.uart_stress_all.2768268271
Short name T161
Test name
Test status
Simulation time 92091014104 ps
CPU time 56.94 seconds
Started Jun 07 07:20:15 PM PDT 24
Finished Jun 07 07:21:36 PM PDT 24
Peak memory 200292 kb
Host smart-de241ec3-100c-4321-8c79-61d5d8c49bf7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768268271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.2768268271
Directory /workspace/6.uart_stress_all/latest

Test location /workspace/coverage/default/6.uart_stress_all_with_rand_reset.3749554537
Short name T29
Test name
Test status
Simulation time 35518877794 ps
CPU time 164.96 seconds
Started Jun 07 07:20:15 PM PDT 24
Finished Jun 07 07:23:24 PM PDT 24
Peak memory 216768 kb
Host smart-4e462a6f-6d16-46d9-b177-d4699d9bc013
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749554537 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 6.uart_stress_all_with_rand_reset.3749554537
Directory /workspace/6.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_tx_ovrd.2239154994
Short name T296
Test name
Test status
Simulation time 1243630679 ps
CPU time 2.74 seconds
Started Jun 07 07:20:06 PM PDT 24
Finished Jun 07 07:20:34 PM PDT 24
Peak memory 199900 kb
Host smart-4c7b9aa7-8349-400c-9ea6-00ac2fbad1a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239154994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.2239154994
Directory /workspace/6.uart_tx_ovrd/latest

Test location /workspace/coverage/default/6.uart_tx_rx.3028273736
Short name T569
Test name
Test status
Simulation time 15381471372 ps
CPU time 14.75 seconds
Started Jun 07 07:20:06 PM PDT 24
Finished Jun 07 07:20:46 PM PDT 24
Peak memory 200392 kb
Host smart-b6e0a035-b747-49c5-ad34-5bf4bdd6f8b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028273736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.3028273736
Directory /workspace/6.uart_tx_rx/latest

Test location /workspace/coverage/default/61.uart_fifo_reset.2509486155
Short name T962
Test name
Test status
Simulation time 113878816248 ps
CPU time 90.5 seconds
Started Jun 07 07:25:51 PM PDT 24
Finished Jun 07 07:27:26 PM PDT 24
Peak memory 200368 kb
Host smart-cc187b8d-4f1e-4abf-bd5e-307d3b953fbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509486155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.2509486155
Directory /workspace/61.uart_fifo_reset/latest

Test location /workspace/coverage/default/61.uart_stress_all_with_rand_reset.282721951
Short name T1015
Test name
Test status
Simulation time 45804481566 ps
CPU time 844.46 seconds
Started Jun 07 07:25:49 PM PDT 24
Finished Jun 07 07:39:58 PM PDT 24
Peak memory 216924 kb
Host smart-4da828e8-aba7-4017-a796-3f46940c4d7b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282721951 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 61.uart_stress_all_with_rand_reset.282721951
Directory /workspace/61.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.uart_fifo_reset.3921469372
Short name T742
Test name
Test status
Simulation time 33103005186 ps
CPU time 66.06 seconds
Started Jun 07 07:25:49 PM PDT 24
Finished Jun 07 07:27:00 PM PDT 24
Peak memory 200404 kb
Host smart-6a1e7888-3545-4b2c-9a67-60918fe6d006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921469372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.3921469372
Directory /workspace/62.uart_fifo_reset/latest

Test location /workspace/coverage/default/62.uart_stress_all_with_rand_reset.4273553953
Short name T105
Test name
Test status
Simulation time 129198766365 ps
CPU time 281.8 seconds
Started Jun 07 07:25:50 PM PDT 24
Finished Jun 07 07:30:37 PM PDT 24
Peak memory 216828 kb
Host smart-74fd0432-159d-4adb-b19f-adb531d23318
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273553953 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 62.uart_stress_all_with_rand_reset.4273553953
Directory /workspace/62.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.uart_fifo_reset.1156914780
Short name T53
Test name
Test status
Simulation time 187135147886 ps
CPU time 146.05 seconds
Started Jun 07 07:25:48 PM PDT 24
Finished Jun 07 07:28:19 PM PDT 24
Peak memory 200344 kb
Host smart-17cdb933-a0a6-4d70-9ddb-77e416dd692d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156914780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.1156914780
Directory /workspace/63.uart_fifo_reset/latest

Test location /workspace/coverage/default/64.uart_fifo_reset.3736418590
Short name T892
Test name
Test status
Simulation time 107516793205 ps
CPU time 163.24 seconds
Started Jun 07 07:25:48 PM PDT 24
Finished Jun 07 07:28:36 PM PDT 24
Peak memory 200412 kb
Host smart-cb5e1a2b-2aee-445c-b4ba-6ec66ef8ff2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736418590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.3736418590
Directory /workspace/64.uart_fifo_reset/latest

Test location /workspace/coverage/default/65.uart_fifo_reset.831186141
Short name T352
Test name
Test status
Simulation time 110665479284 ps
CPU time 182.57 seconds
Started Jun 07 07:25:52 PM PDT 24
Finished Jun 07 07:28:59 PM PDT 24
Peak memory 200356 kb
Host smart-508a3c83-09c3-4219-a4cc-550da081c408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831186141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.831186141
Directory /workspace/65.uart_fifo_reset/latest

Test location /workspace/coverage/default/65.uart_stress_all_with_rand_reset.1448841199
Short name T188
Test name
Test status
Simulation time 221755662342 ps
CPU time 599.03 seconds
Started Jun 07 07:25:55 PM PDT 24
Finished Jun 07 07:35:58 PM PDT 24
Peak memory 217024 kb
Host smart-10d74668-d756-4165-a896-566021b3f76f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448841199 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 65.uart_stress_all_with_rand_reset.1448841199
Directory /workspace/65.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/66.uart_fifo_reset.4225779114
Short name T317
Test name
Test status
Simulation time 11144106067 ps
CPU time 17.66 seconds
Started Jun 07 07:25:49 PM PDT 24
Finished Jun 07 07:26:12 PM PDT 24
Peak memory 200360 kb
Host smart-596297ac-245d-4650-ad6b-4dd6544e9c4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225779114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.4225779114
Directory /workspace/66.uart_fifo_reset/latest

Test location /workspace/coverage/default/66.uart_stress_all_with_rand_reset.2937480898
Short name T1050
Test name
Test status
Simulation time 56788057608 ps
CPU time 482.05 seconds
Started Jun 07 07:25:48 PM PDT 24
Finished Jun 07 07:33:55 PM PDT 24
Peak memory 216896 kb
Host smart-a82dec1c-b4d7-42ad-b4e8-3c6022738c1c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937480898 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 66.uart_stress_all_with_rand_reset.2937480898
Directory /workspace/66.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.uart_fifo_reset.2538844635
Short name T986
Test name
Test status
Simulation time 42079975945 ps
CPU time 13.66 seconds
Started Jun 07 07:25:49 PM PDT 24
Finished Jun 07 07:26:08 PM PDT 24
Peak memory 200412 kb
Host smart-e32deed9-4901-4a1c-9c6a-dbc7322dc0a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538844635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.2538844635
Directory /workspace/67.uart_fifo_reset/latest

Test location /workspace/coverage/default/68.uart_fifo_reset.53462310
Short name T915
Test name
Test status
Simulation time 161935040622 ps
CPU time 70.93 seconds
Started Jun 07 07:25:49 PM PDT 24
Finished Jun 07 07:27:05 PM PDT 24
Peak memory 200376 kb
Host smart-97ff6f9a-0dd9-4566-9942-8bf96dcda4a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53462310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.53462310
Directory /workspace/68.uart_fifo_reset/latest

Test location /workspace/coverage/default/68.uart_stress_all_with_rand_reset.495449671
Short name T37
Test name
Test status
Simulation time 146828791860 ps
CPU time 121.17 seconds
Started Jun 07 07:25:51 PM PDT 24
Finished Jun 07 07:27:57 PM PDT 24
Peak memory 216928 kb
Host smart-de74986b-7730-426f-ba43-f87c4ce042ed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495449671 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 68.uart_stress_all_with_rand_reset.495449671
Directory /workspace/68.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.uart_fifo_reset.4145242043
Short name T1077
Test name
Test status
Simulation time 30948663645 ps
CPU time 18.27 seconds
Started Jun 07 07:25:53 PM PDT 24
Finished Jun 07 07:26:16 PM PDT 24
Peak memory 200408 kb
Host smart-79e07bf1-3156-4aeb-9eb9-c28a93eed93f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145242043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.4145242043
Directory /workspace/69.uart_fifo_reset/latest

Test location /workspace/coverage/default/69.uart_stress_all_with_rand_reset.619071138
Short name T39
Test name
Test status
Simulation time 81131120705 ps
CPU time 499.59 seconds
Started Jun 07 07:25:54 PM PDT 24
Finished Jun 07 07:34:18 PM PDT 24
Peak memory 217028 kb
Host smart-f0b7e4a2-bf29-4bf2-9ca4-00c10635e476
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619071138 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 69.uart_stress_all_with_rand_reset.619071138
Directory /workspace/69.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_alert_test.798229205
Short name T372
Test name
Test status
Simulation time 23044139 ps
CPU time 0.55 seconds
Started Jun 07 07:20:28 PM PDT 24
Finished Jun 07 07:20:50 PM PDT 24
Peak memory 195740 kb
Host smart-6662d4dd-0223-4b72-a295-425825c34325
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798229205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.798229205
Directory /workspace/7.uart_alert_test/latest

Test location /workspace/coverage/default/7.uart_fifo_full.3662227932
Short name T616
Test name
Test status
Simulation time 184410629807 ps
CPU time 122.02 seconds
Started Jun 07 07:20:15 PM PDT 24
Finished Jun 07 07:22:41 PM PDT 24
Peak memory 200336 kb
Host smart-53e97d55-2905-42ed-85d5-e20b59316479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662227932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.3662227932
Directory /workspace/7.uart_fifo_full/latest

Test location /workspace/coverage/default/7.uart_fifo_reset.2930457112
Short name T783
Test name
Test status
Simulation time 79703880298 ps
CPU time 128.53 seconds
Started Jun 07 07:20:17 PM PDT 24
Finished Jun 07 07:22:49 PM PDT 24
Peak memory 200236 kb
Host smart-a15c5e90-63b1-49a9-8c4a-92d2dc28096a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930457112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.2930457112
Directory /workspace/7.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_intr.2777143299
Short name T448
Test name
Test status
Simulation time 295026328365 ps
CPU time 173.4 seconds
Started Jun 07 07:20:17 PM PDT 24
Finished Jun 07 07:23:35 PM PDT 24
Peak memory 197552 kb
Host smart-33ce217e-9dad-4472-93ac-8af5d72bc051
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777143299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.2777143299
Directory /workspace/7.uart_intr/latest

Test location /workspace/coverage/default/7.uart_long_xfer_wo_dly.3927521149
Short name T582
Test name
Test status
Simulation time 304632119589 ps
CPU time 442.8 seconds
Started Jun 07 07:20:28 PM PDT 24
Finished Jun 07 07:28:12 PM PDT 24
Peak memory 200428 kb
Host smart-55dc8d56-3090-4689-9449-eff13dbee4f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3927521149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.3927521149
Directory /workspace/7.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/7.uart_loopback.2438405163
Short name T386
Test name
Test status
Simulation time 10364022832 ps
CPU time 7.91 seconds
Started Jun 07 07:20:28 PM PDT 24
Finished Jun 07 07:20:57 PM PDT 24
Peak memory 200184 kb
Host smart-f2e7289c-52ff-4a26-a2e0-722197c8cd98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438405163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_loopback.2438405163
Directory /workspace/7.uart_loopback/latest

Test location /workspace/coverage/default/7.uart_perf.2304372695
Short name T475
Test name
Test status
Simulation time 13572098045 ps
CPU time 729.18 seconds
Started Jun 07 07:20:28 PM PDT 24
Finished Jun 07 07:32:58 PM PDT 24
Peak memory 200360 kb
Host smart-75f4817a-d821-48c7-9f15-57f448af3b41
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2304372695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.2304372695
Directory /workspace/7.uart_perf/latest

Test location /workspace/coverage/default/7.uart_rx_oversample.259124796
Short name T479
Test name
Test status
Simulation time 3864304672 ps
CPU time 8.48 seconds
Started Jun 07 07:20:16 PM PDT 24
Finished Jun 07 07:20:48 PM PDT 24
Peak memory 198544 kb
Host smart-1cdc02ae-c3d9-41b3-a682-8215fbbadd33
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=259124796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.259124796
Directory /workspace/7.uart_rx_oversample/latest

Test location /workspace/coverage/default/7.uart_rx_parity_err.1882649474
Short name T312
Test name
Test status
Simulation time 26748432723 ps
CPU time 38.91 seconds
Started Jun 07 07:20:29 PM PDT 24
Finished Jun 07 07:21:29 PM PDT 24
Peak memory 200396 kb
Host smart-1c04a28c-fbb0-43ac-8786-45d71ea3d880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882649474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.1882649474
Directory /workspace/7.uart_rx_parity_err/latest

Test location /workspace/coverage/default/7.uart_rx_start_bit_filter.103792758
Short name T1036
Test name
Test status
Simulation time 3769188853 ps
CPU time 2.08 seconds
Started Jun 07 07:20:18 PM PDT 24
Finished Jun 07 07:20:44 PM PDT 24
Peak memory 196472 kb
Host smart-e83b3935-4066-426b-8fe9-fe3695fe04fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103792758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.103792758
Directory /workspace/7.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/7.uart_smoke.3157504083
Short name T467
Test name
Test status
Simulation time 712853091 ps
CPU time 2.14 seconds
Started Jun 07 07:20:16 PM PDT 24
Finished Jun 07 07:20:42 PM PDT 24
Peak memory 200200 kb
Host smart-5dd8d4f9-baac-4cc1-a09f-449e4557cc0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157504083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_smoke.3157504083
Directory /workspace/7.uart_smoke/latest

Test location /workspace/coverage/default/7.uart_stress_all.2116817533
Short name T703
Test name
Test status
Simulation time 399506608935 ps
CPU time 916.37 seconds
Started Jun 07 07:20:28 PM PDT 24
Finished Jun 07 07:36:06 PM PDT 24
Peak memory 200404 kb
Host smart-d25656e0-72a3-47e2-ada7-c578324c24d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116817533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.2116817533
Directory /workspace/7.uart_stress_all/latest

Test location /workspace/coverage/default/7.uart_tx_ovrd.2279429463
Short name T298
Test name
Test status
Simulation time 1827420968 ps
CPU time 1.53 seconds
Started Jun 07 07:20:29 PM PDT 24
Finished Jun 07 07:20:51 PM PDT 24
Peak memory 197092 kb
Host smart-b0c99acf-299a-474a-bc97-dfa9d2211de8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279429463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.2279429463
Directory /workspace/7.uart_tx_ovrd/latest

Test location /workspace/coverage/default/7.uart_tx_rx.1785960631
Short name T289
Test name
Test status
Simulation time 40870160910 ps
CPU time 65.77 seconds
Started Jun 07 07:20:17 PM PDT 24
Finished Jun 07 07:21:46 PM PDT 24
Peak memory 200364 kb
Host smart-e70a8739-7f2b-4a6b-8ce5-bb4f9d064fce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785960631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.1785960631
Directory /workspace/7.uart_tx_rx/latest

Test location /workspace/coverage/default/70.uart_fifo_reset.3158993422
Short name T954
Test name
Test status
Simulation time 60074565350 ps
CPU time 9.93 seconds
Started Jun 07 07:25:58 PM PDT 24
Finished Jun 07 07:26:12 PM PDT 24
Peak memory 200412 kb
Host smart-aefb3eda-c655-45ae-8d03-8f0236684b3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158993422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.3158993422
Directory /workspace/70.uart_fifo_reset/latest

Test location /workspace/coverage/default/71.uart_fifo_reset.4022990482
Short name T539
Test name
Test status
Simulation time 41748288037 ps
CPU time 47.47 seconds
Started Jun 07 07:25:59 PM PDT 24
Finished Jun 07 07:26:50 PM PDT 24
Peak memory 200368 kb
Host smart-ddd5ffba-6522-40e9-8be3-c5a9df3aedc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022990482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.4022990482
Directory /workspace/71.uart_fifo_reset/latest

Test location /workspace/coverage/default/72.uart_fifo_reset.3226834679
Short name T508
Test name
Test status
Simulation time 25421674314 ps
CPU time 31.02 seconds
Started Jun 07 07:25:56 PM PDT 24
Finished Jun 07 07:26:31 PM PDT 24
Peak memory 200380 kb
Host smart-33df6575-4efa-4eb8-a5a1-19743b2336a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226834679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.3226834679
Directory /workspace/72.uart_fifo_reset/latest

Test location /workspace/coverage/default/72.uart_stress_all_with_rand_reset.1432842025
Short name T397
Test name
Test status
Simulation time 9941659855 ps
CPU time 249.82 seconds
Started Jun 07 07:25:57 PM PDT 24
Finished Jun 07 07:30:11 PM PDT 24
Peak memory 200504 kb
Host smart-787fed30-c17c-42d6-96f2-25c257d158e7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432842025 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 72.uart_stress_all_with_rand_reset.1432842025
Directory /workspace/72.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/73.uart_stress_all_with_rand_reset.287748790
Short name T862
Test name
Test status
Simulation time 65038155391 ps
CPU time 241.7 seconds
Started Jun 07 07:25:57 PM PDT 24
Finished Jun 07 07:30:03 PM PDT 24
Peak memory 216836 kb
Host smart-f2fa0fe7-ad93-4d37-b3cb-59059878c397
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287748790 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 73.uart_stress_all_with_rand_reset.287748790
Directory /workspace/73.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/74.uart_fifo_reset.4186209632
Short name T695
Test name
Test status
Simulation time 129816321285 ps
CPU time 181.74 seconds
Started Jun 07 07:26:00 PM PDT 24
Finished Jun 07 07:29:05 PM PDT 24
Peak memory 200360 kb
Host smart-fe52864f-2855-46d9-8e39-b9ba86ef612d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186209632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.4186209632
Directory /workspace/74.uart_fifo_reset/latest

Test location /workspace/coverage/default/74.uart_stress_all_with_rand_reset.3048543713
Short name T422
Test name
Test status
Simulation time 13903054702 ps
CPU time 164.41 seconds
Started Jun 07 07:25:57 PM PDT 24
Finished Jun 07 07:28:46 PM PDT 24
Peak memory 216012 kb
Host smart-ab8f936a-172b-4ca3-be84-493f91f8bbad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048543713 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 74.uart_stress_all_with_rand_reset.3048543713
Directory /workspace/74.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.uart_fifo_reset.1739057449
Short name T814
Test name
Test status
Simulation time 10350425999 ps
CPU time 17.04 seconds
Started Jun 07 07:25:58 PM PDT 24
Finished Jun 07 07:26:19 PM PDT 24
Peak memory 200320 kb
Host smart-fd64233b-e7fd-4b8b-8ec0-e07fd714431a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739057449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.1739057449
Directory /workspace/75.uart_fifo_reset/latest

Test location /workspace/coverage/default/75.uart_stress_all_with_rand_reset.4240815422
Short name T596
Test name
Test status
Simulation time 70215465274 ps
CPU time 332.15 seconds
Started Jun 07 07:25:57 PM PDT 24
Finished Jun 07 07:31:33 PM PDT 24
Peak memory 216060 kb
Host smart-6a938fe3-a63e-461b-9aac-ea93641ed602
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240815422 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 75.uart_stress_all_with_rand_reset.4240815422
Directory /workspace/75.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/76.uart_fifo_reset.3324789335
Short name T255
Test name
Test status
Simulation time 48337077114 ps
CPU time 22.54 seconds
Started Jun 07 07:25:59 PM PDT 24
Finished Jun 07 07:26:25 PM PDT 24
Peak memory 200456 kb
Host smart-56aa1a0f-0d32-400d-892a-c14376673883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324789335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.3324789335
Directory /workspace/76.uart_fifo_reset/latest

Test location /workspace/coverage/default/76.uart_stress_all_with_rand_reset.1860345418
Short name T685
Test name
Test status
Simulation time 24014356879 ps
CPU time 91.18 seconds
Started Jun 07 07:26:03 PM PDT 24
Finished Jun 07 07:27:36 PM PDT 24
Peak memory 216876 kb
Host smart-149491e5-ea5e-4bcc-9e0a-e149cec325a7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860345418 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 76.uart_stress_all_with_rand_reset.1860345418
Directory /workspace/76.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/77.uart_fifo_reset.2919485104
Short name T1051
Test name
Test status
Simulation time 30754429945 ps
CPU time 51.09 seconds
Started Jun 07 07:25:57 PM PDT 24
Finished Jun 07 07:26:52 PM PDT 24
Peak memory 200360 kb
Host smart-221b8727-940c-4fce-ad4d-b6fdca1c04f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919485104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.2919485104
Directory /workspace/77.uart_fifo_reset/latest

Test location /workspace/coverage/default/78.uart_fifo_reset.2378722116
Short name T701
Test name
Test status
Simulation time 152499145071 ps
CPU time 53.99 seconds
Started Jun 07 07:26:10 PM PDT 24
Finished Jun 07 07:27:10 PM PDT 24
Peak memory 200368 kb
Host smart-99681ec7-158d-4e56-8ebe-de3a0057fcfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378722116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.2378722116
Directory /workspace/78.uart_fifo_reset/latest

Test location /workspace/coverage/default/78.uart_stress_all_with_rand_reset.1181945266
Short name T631
Test name
Test status
Simulation time 51516456524 ps
CPU time 485.96 seconds
Started Jun 07 07:26:06 PM PDT 24
Finished Jun 07 07:34:17 PM PDT 24
Peak memory 216892 kb
Host smart-916a361a-b46e-4cfa-bf76-0737a042c18e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181945266 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 78.uart_stress_all_with_rand_reset.1181945266
Directory /workspace/78.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.uart_fifo_reset.308271481
Short name T838
Test name
Test status
Simulation time 14513400869 ps
CPU time 6.97 seconds
Started Jun 07 07:26:09 PM PDT 24
Finished Jun 07 07:26:21 PM PDT 24
Peak memory 199984 kb
Host smart-2491b12a-66c2-41c7-8a12-7b71fbc1bde5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308271481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.308271481
Directory /workspace/79.uart_fifo_reset/latest

Test location /workspace/coverage/default/79.uart_stress_all_with_rand_reset.633777038
Short name T800
Test name
Test status
Simulation time 30006094800 ps
CPU time 384.95 seconds
Started Jun 07 07:26:07 PM PDT 24
Finished Jun 07 07:32:36 PM PDT 24
Peak memory 216824 kb
Host smart-568072bd-70be-48cb-b963-330f843c0561
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633777038 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 79.uart_stress_all_with_rand_reset.633777038
Directory /workspace/79.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_alert_test.198631949
Short name T624
Test name
Test status
Simulation time 13445997 ps
CPU time 0.55 seconds
Started Jun 07 07:20:28 PM PDT 24
Finished Jun 07 07:20:50 PM PDT 24
Peak memory 195980 kb
Host smart-edfc6c5a-0f7c-4b77-ba3a-ac6718f4bd19
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198631949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.198631949
Directory /workspace/8.uart_alert_test/latest

Test location /workspace/coverage/default/8.uart_fifo_full.3638766755
Short name T574
Test name
Test status
Simulation time 103599036398 ps
CPU time 36.52 seconds
Started Jun 07 07:20:29 PM PDT 24
Finished Jun 07 07:21:26 PM PDT 24
Peak memory 200444 kb
Host smart-20daf3fe-87c1-4982-8e91-a110d3fd8fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638766755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.3638766755
Directory /workspace/8.uart_fifo_full/latest

Test location /workspace/coverage/default/8.uart_fifo_overflow.2285557542
Short name T455
Test name
Test status
Simulation time 102910560771 ps
CPU time 41.72 seconds
Started Jun 07 07:20:27 PM PDT 24
Finished Jun 07 07:21:29 PM PDT 24
Peak memory 200072 kb
Host smart-296782ca-c251-4411-a62f-0addbca767b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285557542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.2285557542
Directory /workspace/8.uart_fifo_overflow/latest

Test location /workspace/coverage/default/8.uart_intr.2580003018
Short name T807
Test name
Test status
Simulation time 31911132464 ps
CPU time 61.87 seconds
Started Jun 07 07:20:28 PM PDT 24
Finished Jun 07 07:21:51 PM PDT 24
Peak memory 199808 kb
Host smart-81933d7b-d859-42f1-ab15-4de924a0d9f6
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580003018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.2580003018
Directory /workspace/8.uart_intr/latest

Test location /workspace/coverage/default/8.uart_long_xfer_wo_dly.1929111172
Short name T493
Test name
Test status
Simulation time 115306767755 ps
CPU time 846.98 seconds
Started Jun 07 07:20:31 PM PDT 24
Finished Jun 07 07:34:59 PM PDT 24
Peak memory 200376 kb
Host smart-c581befe-dce7-4980-bd11-ab64fb9e0b6a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1929111172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.1929111172
Directory /workspace/8.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/8.uart_loopback.1166086012
Short name T23
Test name
Test status
Simulation time 5627549411 ps
CPU time 1.8 seconds
Started Jun 07 07:20:27 PM PDT 24
Finished Jun 07 07:20:50 PM PDT 24
Peak memory 199824 kb
Host smart-0ad335ae-31cf-4008-9cf9-b1401f5a1cfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166086012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_loopback.1166086012
Directory /workspace/8.uart_loopback/latest

Test location /workspace/coverage/default/8.uart_perf.1957268535
Short name T496
Test name
Test status
Simulation time 12207140919 ps
CPU time 126.11 seconds
Started Jun 07 07:20:29 PM PDT 24
Finished Jun 07 07:22:56 PM PDT 24
Peak memory 200400 kb
Host smart-e815de93-cddc-4868-9a5e-5528dc7be75a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1957268535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.1957268535
Directory /workspace/8.uart_perf/latest

Test location /workspace/coverage/default/8.uart_rx_oversample.2676202391
Short name T611
Test name
Test status
Simulation time 4967612477 ps
CPU time 8.7 seconds
Started Jun 07 07:20:27 PM PDT 24
Finished Jun 07 07:20:56 PM PDT 24
Peak memory 198524 kb
Host smart-635a1978-c7e9-48ff-bcfe-7c9c31066a8b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2676202391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.2676202391
Directory /workspace/8.uart_rx_oversample/latest

Test location /workspace/coverage/default/8.uart_rx_parity_err.825805224
Short name T995
Test name
Test status
Simulation time 22801229300 ps
CPU time 40.05 seconds
Started Jun 07 07:20:27 PM PDT 24
Finished Jun 07 07:21:28 PM PDT 24
Peak memory 200416 kb
Host smart-27e8fddc-2841-464e-b808-ad1977e0ceb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825805224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.825805224
Directory /workspace/8.uart_rx_parity_err/latest

Test location /workspace/coverage/default/8.uart_rx_start_bit_filter.2410665016
Short name T318
Test name
Test status
Simulation time 39563768962 ps
CPU time 14.64 seconds
Started Jun 07 07:20:27 PM PDT 24
Finished Jun 07 07:21:02 PM PDT 24
Peak memory 196160 kb
Host smart-aafd6fdf-a995-4f2e-9168-985dafffb8b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410665016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.2410665016
Directory /workspace/8.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/8.uart_smoke.834713293
Short name T330
Test name
Test status
Simulation time 6017585528 ps
CPU time 10.32 seconds
Started Jun 07 07:20:29 PM PDT 24
Finished Jun 07 07:21:01 PM PDT 24
Peak memory 200328 kb
Host smart-c61ad318-fca9-4981-83b0-a722f27e12d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834713293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_smoke.834713293
Directory /workspace/8.uart_smoke/latest

Test location /workspace/coverage/default/8.uart_stress_all.3247829903
Short name T964
Test name
Test status
Simulation time 587696791831 ps
CPU time 924.51 seconds
Started Jun 07 07:20:29 PM PDT 24
Finished Jun 07 07:36:15 PM PDT 24
Peak memory 200412 kb
Host smart-c603fc4b-8a9f-4e80-97e2-d52fe886665c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247829903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.3247829903
Directory /workspace/8.uart_stress_all/latest

Test location /workspace/coverage/default/8.uart_stress_all_with_rand_reset.3431000625
Short name T917
Test name
Test status
Simulation time 30313075898 ps
CPU time 988.66 seconds
Started Jun 07 07:20:28 PM PDT 24
Finished Jun 07 07:37:18 PM PDT 24
Peak memory 208732 kb
Host smart-0cd4c9f7-6b70-461f-98dc-591b384d3655
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431000625 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 8.uart_stress_all_with_rand_reset.3431000625
Directory /workspace/8.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_tx_ovrd.70534997
Short name T309
Test name
Test status
Simulation time 6921829296 ps
CPU time 22.84 seconds
Started Jun 07 07:20:29 PM PDT 24
Finished Jun 07 07:21:13 PM PDT 24
Peak memory 199740 kb
Host smart-9dfbd7a0-8a24-4962-8059-a0dd77ef9d30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70534997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.70534997
Directory /workspace/8.uart_tx_ovrd/latest

Test location /workspace/coverage/default/8.uart_tx_rx.3551504678
Short name T935
Test name
Test status
Simulation time 91848707362 ps
CPU time 44.3 seconds
Started Jun 07 07:20:28 PM PDT 24
Finished Jun 07 07:21:33 PM PDT 24
Peak memory 200348 kb
Host smart-d87a1ed2-7441-47c2-8183-507f399e3485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551504678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.3551504678
Directory /workspace/8.uart_tx_rx/latest

Test location /workspace/coverage/default/80.uart_fifo_reset.2949889256
Short name T209
Test name
Test status
Simulation time 84461776163 ps
CPU time 31.82 seconds
Started Jun 07 07:26:08 PM PDT 24
Finished Jun 07 07:26:45 PM PDT 24
Peak memory 200388 kb
Host smart-78dd27d1-5742-49a3-8638-52b5bff7e727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949889256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.2949889256
Directory /workspace/80.uart_fifo_reset/latest

Test location /workspace/coverage/default/81.uart_fifo_reset.1794031502
Short name T197
Test name
Test status
Simulation time 10741709861 ps
CPU time 12.54 seconds
Started Jun 07 07:26:07 PM PDT 24
Finished Jun 07 07:26:24 PM PDT 24
Peak memory 200084 kb
Host smart-9c3a8ee1-7c4a-45b9-9ae8-92a00f23d9ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794031502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.1794031502
Directory /workspace/81.uart_fifo_reset/latest

Test location /workspace/coverage/default/82.uart_fifo_reset.851073127
Short name T837
Test name
Test status
Simulation time 17473290376 ps
CPU time 28.55 seconds
Started Jun 07 07:26:07 PM PDT 24
Finished Jun 07 07:26:41 PM PDT 24
Peak memory 200396 kb
Host smart-d6e9fd55-e731-4036-ab9a-31366bb2a397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851073127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.851073127
Directory /workspace/82.uart_fifo_reset/latest

Test location /workspace/coverage/default/83.uart_fifo_reset.1027218536
Short name T230
Test name
Test status
Simulation time 73838324900 ps
CPU time 28.37 seconds
Started Jun 07 07:26:07 PM PDT 24
Finished Jun 07 07:26:40 PM PDT 24
Peak memory 200368 kb
Host smart-daef7b6d-1fce-4932-931b-e953ece7aac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027218536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.1027218536
Directory /workspace/83.uart_fifo_reset/latest

Test location /workspace/coverage/default/84.uart_fifo_reset.1573448675
Short name T801
Test name
Test status
Simulation time 5648788928 ps
CPU time 6.99 seconds
Started Jun 07 07:26:06 PM PDT 24
Finished Jun 07 07:26:18 PM PDT 24
Peak memory 200260 kb
Host smart-577cb5e3-6876-4e61-a21c-5cd1102306db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573448675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.1573448675
Directory /workspace/84.uart_fifo_reset/latest

Test location /workspace/coverage/default/84.uart_stress_all_with_rand_reset.2465347911
Short name T849
Test name
Test status
Simulation time 93870822251 ps
CPU time 606.21 seconds
Started Jun 07 07:26:07 PM PDT 24
Finished Jun 07 07:36:19 PM PDT 24
Peak memory 216908 kb
Host smart-c1ecf282-8eff-4105-9f29-ea4f93f38ef2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465347911 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 84.uart_stress_all_with_rand_reset.2465347911
Directory /workspace/84.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.uart_stress_all_with_rand_reset.551265278
Short name T38
Test name
Test status
Simulation time 54825433049 ps
CPU time 974.89 seconds
Started Jun 07 07:26:05 PM PDT 24
Finished Jun 07 07:42:24 PM PDT 24
Peak memory 216924 kb
Host smart-32844792-7aa4-48b7-94c6-153918e9da6f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551265278 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 85.uart_stress_all_with_rand_reset.551265278
Directory /workspace/85.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.uart_fifo_reset.2070408292
Short name T211
Test name
Test status
Simulation time 7853763642 ps
CPU time 5.96 seconds
Started Jun 07 07:26:07 PM PDT 24
Finished Jun 07 07:26:18 PM PDT 24
Peak memory 199248 kb
Host smart-60878d7b-6b6e-4068-8dfd-158511333534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070408292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.2070408292
Directory /workspace/86.uart_fifo_reset/latest

Test location /workspace/coverage/default/86.uart_stress_all_with_rand_reset.1257338116
Short name T187
Test name
Test status
Simulation time 211435439443 ps
CPU time 461.82 seconds
Started Jun 07 07:26:06 PM PDT 24
Finished Jun 07 07:33:52 PM PDT 24
Peak memory 216924 kb
Host smart-67cd9454-a0ed-4f20-8eb7-1dfb2da7ad3e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257338116 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 86.uart_stress_all_with_rand_reset.1257338116
Directory /workspace/86.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/87.uart_fifo_reset.43128719
Short name T676
Test name
Test status
Simulation time 34549482831 ps
CPU time 15.04 seconds
Started Jun 07 07:26:06 PM PDT 24
Finished Jun 07 07:26:25 PM PDT 24
Peak memory 200448 kb
Host smart-4efdb0a5-5370-416f-9b65-bfb5fbf75801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43128719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.43128719
Directory /workspace/87.uart_fifo_reset/latest

Test location /workspace/coverage/default/88.uart_fifo_reset.2082530413
Short name T743
Test name
Test status
Simulation time 56971622352 ps
CPU time 77.32 seconds
Started Jun 07 07:26:08 PM PDT 24
Finished Jun 07 07:27:30 PM PDT 24
Peak memory 200364 kb
Host smart-c651eee1-1c17-43b0-8b74-183b2f2b7cb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082530413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.2082530413
Directory /workspace/88.uart_fifo_reset/latest

Test location /workspace/coverage/default/88.uart_stress_all_with_rand_reset.1021508419
Short name T675
Test name
Test status
Simulation time 203313073705 ps
CPU time 497.1 seconds
Started Jun 07 07:26:08 PM PDT 24
Finished Jun 07 07:34:30 PM PDT 24
Peak memory 216976 kb
Host smart-c7da91d3-c2c6-430a-9116-27ac2ef119eb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021508419 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 88.uart_stress_all_with_rand_reset.1021508419
Directory /workspace/88.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.uart_fifo_reset.2906464866
Short name T982
Test name
Test status
Simulation time 22384848919 ps
CPU time 63.14 seconds
Started Jun 07 07:26:05 PM PDT 24
Finished Jun 07 07:27:13 PM PDT 24
Peak memory 200376 kb
Host smart-f9fdcb9c-8774-47de-a0f0-5f188d4c03fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906464866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.2906464866
Directory /workspace/89.uart_fifo_reset/latest

Test location /workspace/coverage/default/89.uart_stress_all_with_rand_reset.1457338931
Short name T343
Test name
Test status
Simulation time 17552587327 ps
CPU time 199.54 seconds
Started Jun 07 07:26:10 PM PDT 24
Finished Jun 07 07:29:34 PM PDT 24
Peak memory 216828 kb
Host smart-8f56482e-757f-43d3-95c5-cae79fe51f35
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457338931 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 89.uart_stress_all_with_rand_reset.1457338931
Directory /workspace/89.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_alert_test.3850899125
Short name T588
Test name
Test status
Simulation time 63752489 ps
CPU time 0.56 seconds
Started Jun 07 07:20:37 PM PDT 24
Finished Jun 07 07:20:55 PM PDT 24
Peak memory 196004 kb
Host smart-5d019605-b309-4e87-acda-ad80ac49fa80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850899125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.3850899125
Directory /workspace/9.uart_alert_test/latest

Test location /workspace/coverage/default/9.uart_fifo_full.929694444
Short name T626
Test name
Test status
Simulation time 124758947879 ps
CPU time 91.16 seconds
Started Jun 07 07:20:30 PM PDT 24
Finished Jun 07 07:22:22 PM PDT 24
Peak memory 200324 kb
Host smart-98db3ff4-2735-47f9-b4f6-7fd4c28609b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929694444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.929694444
Directory /workspace/9.uart_fifo_full/latest

Test location /workspace/coverage/default/9.uart_fifo_overflow.4167753478
Short name T957
Test name
Test status
Simulation time 32376363060 ps
CPU time 63.66 seconds
Started Jun 07 07:20:28 PM PDT 24
Finished Jun 07 07:21:53 PM PDT 24
Peak memory 200416 kb
Host smart-332267be-e7d0-47d4-b64b-0d29c351b790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167753478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.4167753478
Directory /workspace/9.uart_fifo_overflow/latest

Test location /workspace/coverage/default/9.uart_fifo_reset.3051258750
Short name T138
Test name
Test status
Simulation time 45922922546 ps
CPU time 35.86 seconds
Started Jun 07 07:20:30 PM PDT 24
Finished Jun 07 07:21:27 PM PDT 24
Peak memory 200356 kb
Host smart-f2f5af0d-2817-4b62-9c89-6c66d1110d31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051258750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.3051258750
Directory /workspace/9.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_intr.196947305
Short name T315
Test name
Test status
Simulation time 48869238339 ps
CPU time 42.99 seconds
Started Jun 07 07:20:30 PM PDT 24
Finished Jun 07 07:21:34 PM PDT 24
Peak memory 200264 kb
Host smart-9298832b-61c6-4336-9375-cf85913b60c1
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196947305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.196947305
Directory /workspace/9.uart_intr/latest

Test location /workspace/coverage/default/9.uart_long_xfer_wo_dly.104889456
Short name T560
Test name
Test status
Simulation time 110299687777 ps
CPU time 952.37 seconds
Started Jun 07 07:20:40 PM PDT 24
Finished Jun 07 07:36:48 PM PDT 24
Peak memory 200420 kb
Host smart-8386bacf-0e5c-4da5-a6d0-e3d9507a5028
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=104889456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.104889456
Directory /workspace/9.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/9.uart_loopback.3757939284
Short name T657
Test name
Test status
Simulation time 11437629457 ps
CPU time 7.38 seconds
Started Jun 07 07:20:38 PM PDT 24
Finished Jun 07 07:21:03 PM PDT 24
Peak memory 200312 kb
Host smart-4d43ed0c-4fbc-4304-a5c9-1535bb7f7469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757939284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_loopback.3757939284
Directory /workspace/9.uart_loopback/latest

Test location /workspace/coverage/default/9.uart_noise_filter.521424793
Short name T279
Test name
Test status
Simulation time 83035148256 ps
CPU time 64.99 seconds
Started Jun 07 07:20:29 PM PDT 24
Finished Jun 07 07:21:56 PM PDT 24
Peak memory 200404 kb
Host smart-0a527462-7eef-4070-ae17-6371932c22cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521424793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.521424793
Directory /workspace/9.uart_noise_filter/latest

Test location /workspace/coverage/default/9.uart_perf.3947786046
Short name T452
Test name
Test status
Simulation time 10689307679 ps
CPU time 141.43 seconds
Started Jun 07 07:20:40 PM PDT 24
Finished Jun 07 07:23:18 PM PDT 24
Peak memory 200396 kb
Host smart-6ac7d0ed-48f2-4760-b9a3-2d97d4f7522e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3947786046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.3947786046
Directory /workspace/9.uart_perf/latest

Test location /workspace/coverage/default/9.uart_rx_oversample.576880075
Short name T600
Test name
Test status
Simulation time 5968772973 ps
CPU time 27.38 seconds
Started Jun 07 07:20:29 PM PDT 24
Finished Jun 07 07:21:18 PM PDT 24
Peak memory 200356 kb
Host smart-162e5f84-9a9c-4db7-804b-e04053a5cc94
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=576880075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.576880075
Directory /workspace/9.uart_rx_oversample/latest

Test location /workspace/coverage/default/9.uart_rx_parity_err.3640139113
Short name T1023
Test name
Test status
Simulation time 54700456573 ps
CPU time 17.6 seconds
Started Jun 07 07:20:30 PM PDT 24
Finished Jun 07 07:21:08 PM PDT 24
Peak memory 200420 kb
Host smart-841541c8-c49b-4d42-88d4-1e08be90d915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640139113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.3640139113
Directory /workspace/9.uart_rx_parity_err/latest

Test location /workspace/coverage/default/9.uart_rx_start_bit_filter.2740768030
Short name T277
Test name
Test status
Simulation time 1832651841 ps
CPU time 1.42 seconds
Started Jun 07 07:20:30 PM PDT 24
Finished Jun 07 07:20:52 PM PDT 24
Peak memory 195760 kb
Host smart-73b74ae4-28eb-4723-8854-10a834e1e275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740768030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.2740768030
Directory /workspace/9.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/9.uart_smoke.3267244038
Short name T828
Test name
Test status
Simulation time 678336408 ps
CPU time 2.03 seconds
Started Jun 07 07:20:27 PM PDT 24
Finished Jun 07 07:20:50 PM PDT 24
Peak memory 199224 kb
Host smart-5e075ae9-c329-48fe-84a5-09f29d728f21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267244038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_smoke.3267244038
Directory /workspace/9.uart_smoke/latest

Test location /workspace/coverage/default/9.uart_stress_all_with_rand_reset.458926609
Short name T57
Test name
Test status
Simulation time 17423117539 ps
CPU time 188.33 seconds
Started Jun 07 07:20:39 PM PDT 24
Finished Jun 07 07:24:04 PM PDT 24
Peak memory 215948 kb
Host smart-43b8dbf3-5dea-4bf4-95c3-92b131e27657
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458926609 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 9.uart_stress_all_with_rand_reset.458926609
Directory /workspace/9.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_tx_ovrd.2815435694
Short name T294
Test name
Test status
Simulation time 917276009 ps
CPU time 2.32 seconds
Started Jun 07 07:20:30 PM PDT 24
Finished Jun 07 07:20:53 PM PDT 24
Peak memory 198720 kb
Host smart-bff77ffa-49b3-4a28-979b-e467d8133386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815435694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.2815435694
Directory /workspace/9.uart_tx_ovrd/latest

Test location /workspace/coverage/default/9.uart_tx_rx.1787681594
Short name T438
Test name
Test status
Simulation time 29635110993 ps
CPU time 45.29 seconds
Started Jun 07 07:20:26 PM PDT 24
Finished Jun 07 07:21:31 PM PDT 24
Peak memory 200200 kb
Host smart-e0c8e953-9d2f-40d1-a8f2-8e83fd6a1882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787681594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.1787681594
Directory /workspace/9.uart_tx_rx/latest

Test location /workspace/coverage/default/90.uart_fifo_reset.1557223757
Short name T15
Test name
Test status
Simulation time 26865734227 ps
CPU time 23.31 seconds
Started Jun 07 07:26:08 PM PDT 24
Finished Jun 07 07:26:36 PM PDT 24
Peak memory 200324 kb
Host smart-9cf176f1-ec17-4197-909e-3b73b5c0fb35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557223757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.1557223757
Directory /workspace/90.uart_fifo_reset/latest

Test location /workspace/coverage/default/91.uart_fifo_reset.3115300950
Short name T141
Test name
Test status
Simulation time 13852889323 ps
CPU time 9.62 seconds
Started Jun 07 07:26:09 PM PDT 24
Finished Jun 07 07:26:23 PM PDT 24
Peak memory 200344 kb
Host smart-c9ffaf4e-445c-480d-bfcc-6df8c8053d56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115300950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.3115300950
Directory /workspace/91.uart_fifo_reset/latest

Test location /workspace/coverage/default/92.uart_fifo_reset.98434633
Short name T51
Test name
Test status
Simulation time 142690961483 ps
CPU time 212.2 seconds
Started Jun 07 07:26:08 PM PDT 24
Finished Jun 07 07:29:45 PM PDT 24
Peak memory 200256 kb
Host smart-c00de0fa-f901-4071-9b41-240ca638094f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98434633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.98434633
Directory /workspace/92.uart_fifo_reset/latest

Test location /workspace/coverage/default/93.uart_fifo_reset.1082375412
Short name T642
Test name
Test status
Simulation time 44883400395 ps
CPU time 75.17 seconds
Started Jun 07 07:26:07 PM PDT 24
Finished Jun 07 07:27:27 PM PDT 24
Peak memory 200368 kb
Host smart-8f56c408-b6c4-4f03-82f3-85813fec4a53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082375412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.1082375412
Directory /workspace/93.uart_fifo_reset/latest

Test location /workspace/coverage/default/93.uart_stress_all_with_rand_reset.3904234019
Short name T1009
Test name
Test status
Simulation time 184104399840 ps
CPU time 537.86 seconds
Started Jun 07 07:26:05 PM PDT 24
Finished Jun 07 07:35:07 PM PDT 24
Peak memory 214896 kb
Host smart-f099e3c8-cc5f-4f9b-a9da-e864fc66e61e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904234019 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 93.uart_stress_all_with_rand_reset.3904234019
Directory /workspace/93.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/94.uart_fifo_reset.1003900027
Short name T1031
Test name
Test status
Simulation time 24064599832 ps
CPU time 35.17 seconds
Started Jun 07 07:26:06 PM PDT 24
Finished Jun 07 07:26:46 PM PDT 24
Peak memory 200268 kb
Host smart-20fd54da-bee6-4438-a5e5-538222cd53eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003900027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.1003900027
Directory /workspace/94.uart_fifo_reset/latest

Test location /workspace/coverage/default/95.uart_fifo_reset.2093622113
Short name T541
Test name
Test status
Simulation time 48471534459 ps
CPU time 43.08 seconds
Started Jun 07 07:26:14 PM PDT 24
Finished Jun 07 07:27:03 PM PDT 24
Peak memory 200308 kb
Host smart-6d086a40-1bc0-4414-8afe-dc49535ff64a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093622113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.2093622113
Directory /workspace/95.uart_fifo_reset/latest

Test location /workspace/coverage/default/95.uart_stress_all_with_rand_reset.3206508224
Short name T1029
Test name
Test status
Simulation time 79689351441 ps
CPU time 193.49 seconds
Started Jun 07 07:26:12 PM PDT 24
Finished Jun 07 07:29:32 PM PDT 24
Peak memory 216924 kb
Host smart-17f2684e-5de0-4e71-95bd-1f5d04b50297
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206508224 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 95.uart_stress_all_with_rand_reset.3206508224
Directory /workspace/95.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/96.uart_fifo_reset.542090507
Short name T983
Test name
Test status
Simulation time 177934996431 ps
CPU time 44.42 seconds
Started Jun 07 07:26:15 PM PDT 24
Finished Jun 07 07:27:05 PM PDT 24
Peak memory 200332 kb
Host smart-36ec928a-6fac-4da0-a5c9-8fd502a5b232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542090507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.542090507
Directory /workspace/96.uart_fifo_reset/latest

Test location /workspace/coverage/default/97.uart_fifo_reset.2069121721
Short name T260
Test name
Test status
Simulation time 15320599677 ps
CPU time 3.78 seconds
Started Jun 07 07:26:13 PM PDT 24
Finished Jun 07 07:26:22 PM PDT 24
Peak memory 200080 kb
Host smart-80af6c53-3408-4d76-baf0-e2f1804508d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069121721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.2069121721
Directory /workspace/97.uart_fifo_reset/latest

Test location /workspace/coverage/default/98.uart_fifo_reset.804259316
Short name T795
Test name
Test status
Simulation time 11312735270 ps
CPU time 19.75 seconds
Started Jun 07 07:26:13 PM PDT 24
Finished Jun 07 07:26:39 PM PDT 24
Peak memory 200372 kb
Host smart-8207648e-2485-44f3-8f29-fa990f6242c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804259316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.804259316
Directory /workspace/98.uart_fifo_reset/latest

Test location /workspace/coverage/default/99.uart_fifo_reset.3697277553
Short name T292
Test name
Test status
Simulation time 76927771700 ps
CPU time 60.32 seconds
Started Jun 07 07:26:14 PM PDT 24
Finished Jun 07 07:27:21 PM PDT 24
Peak memory 200404 kb
Host smart-aec58f4c-d099-4af6-a028-d2b0cf0dc213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697277553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.3697277553
Directory /workspace/99.uart_fifo_reset/latest

Test location /workspace/coverage/default/99.uart_stress_all_with_rand_reset.1469889976
Short name T521
Test name
Test status
Simulation time 112603621369 ps
CPU time 218.71 seconds
Started Jun 07 07:26:13 PM PDT 24
Finished Jun 07 07:29:57 PM PDT 24
Peak memory 216960 kb
Host smart-96c00440-fd55-425e-94c8-45a233826cac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469889976 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 99.uart_stress_all_with_rand_reset.1469889976
Directory /workspace/99.uart_stress_all_with_rand_reset/latest
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