Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	76207	1			T1	7		T2	2		T3	9
all_values[1]	76207	1			T1	7		T2	2		T3	9
all_values[2]	76207	1			T1	7		T2	2		T3	9
all_values[3]	76207	1			T1	7		T2	2		T3	9
all_values[4]	76207	1			T1	7		T2	2		T3	9
all_values[5]	76207	1			T1	7		T2	2		T3	9
all_values[6]	76207	1			T1	7		T2	2		T3	9
all_values[7]	76207	1			T1	7		T2	2		T3	9
all_values[8]	76207	1			T1	7		T2	2		T3	9

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

346585

1

T1

38

T2

18

T3

55

auto[1]

339278

1

T1

25

T3

26

T5

611

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

619057

1

T1

48

T2

13

T3

62

auto[1]

66806

1

T1

15

T2

5

T3

19

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	22771	1			T1	2		T5	15		T7	96
all_values[0]	auto[0]	auto[1]	16847	1			T1	5		T2	2		T3	1
all_values[0]	auto[1]	auto[0]	20996	1			T3	1		T5	92		T7	205
all_values[0]	auto[1]	auto[1]	15593	1			T3	7		T5	14		T7	33
all_values[1]	auto[0]	auto[0]	36013	1			T1	2		T2	2		T3	8
all_values[1]	auto[0]	auto[1]	1607	1			T18	19		T114	10		T127	3
all_values[1]	auto[1]	auto[0]	37067	1			T1	4		T3	1		T5	54
all_values[1]	auto[1]	auto[1]	1520	1			T1	1		T7	28		T9	1
all_values[2]	auto[0]	auto[0]	31483	1			T1	3		T2	1		T3	6
all_values[2]	auto[0]	auto[1]	2168	1			T1	4		T2	1		T3	2
all_values[2]	auto[1]	auto[0]	40513	1			T5	100		T7	237		T8	99
all_values[2]	auto[1]	auto[1]	2043	1			T3	1		T5	5		T7	7
all_values[3]	auto[0]	auto[0]	39105	1			T1	5		T2	2		T3	4
all_values[3]	auto[0]	auto[1]	222	1			T12	2		T16	2		T22	3
all_values[3]	auto[1]	auto[0]	36547	1			T1	2		T3	5		T5	15
all_values[3]	auto[1]	auto[1]	333	1			T9	1		T13	1		T16	1
all_values[4]	auto[0]	auto[0]	41305	1			T1	2		T2	2		T3	5
all_values[4]	auto[0]	auto[1]	409	1			T13	6		T16	2		T22	1
all_values[4]	auto[1]	auto[0]	34080	1			T1	5		T3	4		T5	53
all_values[4]	auto[1]	auto[1]	413	1			T13	4		T16	9		T89	7
all_values[5]	auto[0]	auto[0]	38700	1			T1	2		T2	2		T3	9
all_values[5]	auto[0]	auto[1]	155	1			T16	4		T34	5		T46	1
all_values[5]	auto[1]	auto[0]	37218	1			T1	5		T5	61		T7	225
all_values[5]	auto[1]	auto[1]	134	1			T34	1		T46	2		T117	1
all_values[6]	auto[0]	auto[0]	38035	1			T1	2		T2	2		T3	6
all_values[6]	auto[0]	auto[1]	137	1			T16	1		T34	6		T111	3
all_values[6]	auto[1]	auto[0]	37909	1			T1	5		T3	3		T5	67
all_values[6]	auto[1]	auto[1]	126	1			T34	1		T46	3		T111	1
all_values[7]	auto[0]	auto[0]	39677	1			T1	4		T2	2		T3	8
all_values[7]	auto[0]	auto[1]	264	1			T18	2		T13	3		T22	2
all_values[7]	auto[1]	auto[0]	35972	1			T1	3		T3	1		T5	93
all_values[7]	auto[1]	auto[1]	294	1			T16	3		T136	7		T255	7
all_values[8]	auto[0]	auto[0]	25385	1			T1	2		T5	51		T7	150
all_values[8]	auto[0]	auto[1]	12302	1			T1	5		T2	2		T3	6
all_values[8]	auto[1]	auto[0]	26281	1			T3	1		T5	56		T7	167
all_values[8]	auto[1]	auto[1]	12239	1			T3	2		T5	1		T7	25