Unified Coverage Report :: Group :: uart_agent_pkg::uart_agent_cov::uart_reset_cg

Group : uart_agent_pkg::uart_agent_cov::uart_reset_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_agent_0.1/uart_agent_cov.sv

---

Summary for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	22	0	22	100.00

Variables for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	0
cp_rst_pos	11	0	11	100.00	100	1	1	0

Crosses for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
uart_reset_cg_cc	22	0	22	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[UartTx]

2142

1

T1

1

T2

1

T3

1

auto[UartRx]

2142

1

T1

1

T2

1

T3

1

---

Summary for Variable cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_rst_pos

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3916	1			T1	2		T2	2		T3	2
values[1]	27	1			T16	1		T32	2		T100	1
values[2]	35	1			T8	1		T16	2		T31	1
values[3]	35	1			T13	1		T30	1		T32	1
values[4]	41	1			T8	1		T30	1		T34	1
values[5]	27	1			T13	1		T16	1		T30	1
values[6]	30	1			T30	2		T34	1		T46	1
values[7]	33	1			T13	1		T33	2		T35	1
values[8]	31	1			T8	1		T34	1		T35	1
values[9]	42	1			T8	1		T13	1		T32	1
values[10]	39	1			T8	1		T16	1		T30	1

---

Summary for Cross uart_reset_cg_cc

Samples crossed: cp_dir cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	22	0	22	100.00

Automatically Generated Cross Bins for uart_reset_cg_cc

Bins

cp_dir	cp_rst_pos	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[UartTx]	values[0]	2023	1			T1	1		T2	1		T3	1
auto[UartTx]	values[1]	8	1			T122	1		T326	1		T68	1
auto[UartTx]	values[2]	9	1			T16	2		T102	1		T327	1
auto[UartTx]	values[3]	11	1			T13	1		T30	1		T46	1
auto[UartTx]	values[4]	12	1			T8	1		T35	2		T122	1
auto[UartTx]	values[5]	9	1			T101	1		T199	1		T57	1
auto[UartTx]	values[6]	10	1			T30	1		T103	1		T326	1
auto[UartTx]	values[7]	8	1			T33	1		T209	1		T328	1
auto[UartTx]	values[8]	15	1			T8	1		T35	1		T46	1
auto[UartTx]	values[9]	9	1			T32	1		T56	1		T329	1
auto[UartTx]	values[10]	16	1			T8	1		T100	1		T209	1
auto[UartRx]	values[0]	1893	1			T1	1		T2	1		T3	1
auto[UartRx]	values[1]	19	1			T16	1		T32	2		T100	1
auto[UartRx]	values[2]	26	1			T8	1		T31	1		T34	1
auto[UartRx]	values[3]	24	1			T32	1		T34	1		T46	1
auto[UartRx]	values[4]	29	1			T30	1		T34	1		T35	1
auto[UartRx]	values[5]	18	1			T13	1		T16	1		T30	1
auto[UartRx]	values[6]	20	1			T30	1		T34	1		T46	1
auto[UartRx]	values[7]	25	1			T13	1		T33	1		T35	1
auto[UartRx]	values[8]	16	1			T34	1		T36	1		T119	1
auto[UartRx]	values[9]	33	1			T8	1		T13	1		T34	2
auto[UartRx]	values[10]	23	1			T16	1		T30	1		T31	1