Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	2022	1			T2	1		T3	1		T6	1
auto[BaudRate115200]	1498	1			T2	1		T3	1		T7	7
auto[BaudRate230400]	1544	1			T1	4		T3	1		T7	4
auto[BaudRate128Kbps]	1525	1			T1	1		T6	1		T7	4
auto[BaudRate256Kbps]	1667	1			T5	3		T7	5		T8	4
auto[BaudRate1Mbps]	1446	1			T3	1		T5	2		T7	3
auto[BaudRate1p5Mbps]	1023	1			T5	3		T7	4		T10	1

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Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	939	1			T113	5		T24	2		T296	2
freqs[25]	960	1			T3	4		T39	1		T12	5
freqs[48]	486	1			T41	10		T285	2		T133	10
freqs[50]	490	1			T11	5		T15	4		T30	10
freqs[100]	602	1			T5	8		T6	2		T7	32

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Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	161	1			T189	2		T288	1		T265	3
auto[BaudRate9600]	freqs[25]	162	1			T3	1		T12	1		T108	2
auto[BaudRate9600]	freqs[48]	78	1			T133	1		T166	1		T330	3
auto[BaudRate9600]	freqs[50]	95	1			T11	1		T15	4		T30	2
auto[BaudRate9600]	freqs[100]	116	1			T6	1		T7	5		T128	2
auto[BaudRate115200]	freqs[24]	135	1			T113	2		T24	1		T189	1
auto[BaudRate115200]	freqs[25]	113	1			T3	1		T12	1		T40	1
auto[BaudRate115200]	freqs[48]	61	1			T285	1		T133	5		T166	2
auto[BaudRate115200]	freqs[50]	65	1			T11	1		T31	1		T131	3
auto[BaudRate115200]	freqs[100]	76	1			T7	7		T128	2		T33	1
auto[BaudRate230400]	freqs[24]	160	1			T113	2		T288	1		T89	3
auto[BaudRate230400]	freqs[25]	169	1			T3	1		T39	1		T12	1
auto[BaudRate230400]	freqs[48]	48	1			T166	1		T331	1		T330	6
auto[BaudRate230400]	freqs[50]	65	1			T30	1		T31	3		T131	1
auto[BaudRate230400]	freqs[100]	80	1			T7	4		T33	4		T256	1
auto[BaudRate128Kbps]	freqs[24]	148	1			T113	1		T24	1		T189	1
auto[BaudRate128Kbps]	freqs[25]	128	1			T22	3		T108	1		T281	2
auto[BaudRate128Kbps]	freqs[48]	55	1			T133	2		T331	1		T330	6
auto[BaudRate128Kbps]	freqs[50]	65	1			T11	1		T30	1		T31	2
auto[BaudRate128Kbps]	freqs[100]	84	1			T6	1		T7	4		T128	1
auto[BaudRate256Kbps]	freqs[24]	141	1			T296	1		T189	3		T303	2
auto[BaudRate256Kbps]	freqs[25]	135	1			T108	2		T264	2		T195	1
auto[BaudRate256Kbps]	freqs[48]	70	1			T41	4		T166	1		T331	1
auto[BaudRate256Kbps]	freqs[50]	75	1			T11	2		T30	2		T31	4
auto[BaudRate256Kbps]	freqs[100]	70	1			T5	3		T7	5		T128	2
auto[BaudRate1Mbps]	freqs[24]	128	1			T296	1		T269	5		T287	2
auto[BaudRate1Mbps]	freqs[25]	160	1			T3	1		T12	1		T264	3
auto[BaudRate1Mbps]	freqs[48]	92	1			T41	3		T133	1		T330	21
auto[BaudRate1Mbps]	freqs[50]	58	1			T30	3		T31	4		T298	1
auto[BaudRate1Mbps]	freqs[100]	89	1			T5	2		T7	3		T128	1
auto[BaudRate1p5Mbps]	freqs[25]	93	1			T12	1		T108	1		T195	1
auto[BaudRate1p5Mbps]	freqs[48]	82	1			T41	3		T285	1		T133	1
auto[BaudRate1p5Mbps]	freqs[50]	67	1			T30	1		T31	1		T298	2
auto[BaudRate1p5Mbps]	freqs[100]	87	1			T5	3		T7	4		T128	1

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded