Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::rx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::rx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
94.92	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	67	0	67	100.00
Crosses	130	10	120	92.31

Variables for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	65	0	65	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
rx_fifo_level_cg_cc	130	10	120	92.31	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	21577097	1			T1	21		T3	50		T5	168102
all_levels[1]	148407	1			T1	1		T3	9		T5	2726
all_levels[2]	1861	1			T7	22		T8	10		T113	3
all_levels[3]	797	1			T7	3		T8	12		T12	1
all_levels[4]	632	1			T1	3		T7	5		T8	6
all_levels[5]	463	1			T7	3		T8	5		T18	2
all_levels[6]	364	1			T1	3		T8	4		T113	1
all_levels[7]	315	1			T1	2		T7	5		T8	1
all_levels[8]	275	1			T1	4		T7	1		T127	1
all_levels[9]	228	1			T1	1		T7	2		T127	1
all_levels[10]	187	1			T1	1		T7	1		T13	1
all_levels[11]	166	1			T1	3		T7	4		T18	2
all_levels[12]	156	1			T1	1		T7	2		T105	1
all_levels[13]	146	1			T9	2		T18	2		T16	2
all_levels[14]	123	1			T1	1		T12	1		T128	1
all_levels[15]	125	1			T7	1		T16	1		T128	1
all_levels[16]	140	1			T1	1		T7	1		T128	2
all_levels[17]	83	1			T18	1		T13	1		T129	1
all_levels[18]	82	1			T7	2		T129	1		T32	1
all_levels[19]	64	1			T7	1		T129	1		T130	1
all_levels[20]	61	1			T31	1		T131	1		T130	1
all_levels[21]	68	1			T42	3		T109	4		T131	1
all_levels[22]	58	1			T7	1		T18	1		T128	2
all_levels[23]	42	1			T11	1		T128	1		T132	1
all_levels[24]	50	1			T128	1		T107	1		T109	3
all_levels[25]	37	1			T7	1		T107	1		T133	1
all_levels[26]	32	1			T31	1		T131	1		T133	1
all_levels[27]	46	1			T107	1		T134	2		T135	3
all_levels[28]	47	1			T107	1		T136	1		T133	1
all_levels[29]	38	1			T1	1		T16	1		T130	1
all_levels[30]	39	1			T7	2		T107	1		T137	1
all_levels[31]	31	1			T114	2		T131	1		T130	1
all_levels[32]	20	1			T138	1		T139	1		T137	1
all_levels[33]	30	1			T18	1		T16	1		T140	1
all_levels[34]	17	1			T140	1		T141	1		T142	1
all_levels[35]	22	1			T143	1		T144	1		T145	1
all_levels[36]	22	1			T11	3		T16	1		T137	1
all_levels[37]	24	1			T16	2		T138	1		T135	1
all_levels[38]	16	1			T146	1		T147	1		T148	1
all_levels[39]	20	1			T149	1		T111	2		T150	1
all_levels[40]	21	1			T136	1		T100	1		T147	1
all_levels[41]	22	1			T12	1		T129	1		T136	1
all_levels[42]	20	1			T108	1		T140	1		T147	1
all_levels[43]	19	1			T31	1		T151	1		T100	1
all_levels[44]	19	1			T149	1		T34	2		T142	1
all_levels[45]	10	1			T12	1		T137	1		T152	2
all_levels[46]	23	1			T140	2		T153	1		T111	2
all_levels[47]	15	1			T16	1		T154	2		T155	1
all_levels[48]	16	1			T148	1		T156	2		T157	1
all_levels[49]	16	1			T130	1		T158	1		T159	1
all_levels[50]	14	1			T111	1		T160	1		T161	1
all_levels[51]	12	1			T16	1		T162	1		T163	1
all_levels[52]	10	1			T32	1		T141	1		T162	1
all_levels[53]	7	1			T133	2		T139	1		T121	2
all_levels[54]	2	1			T164	1		T165	1		-	-
all_levels[55]	8	1			T166	1		T167	1		T168	1
all_levels[56]	6	1			T169	1		T170	1		T171	1
all_levels[57]	4	1			T172	1		T173	1		T174	2
all_levels[58]	14	1			T16	3		T47	1		T175	1
all_levels[59]	4	1			T176	1		T148	1		T177	1
all_levels[60]	7	1			T131	1		T175	1		T178	1
all_levels[61]	6	1			T143	1		T179	1		T57	1
all_levels[62]	9	1			T163	1		T180	2		T181	1
all_levels[63]	8	1			T176	1		T182	1		T183	1
all_levels[64]	118	1			T9	3		T12	3		T42	1

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21728250

1

T1

39

T3

59

T5

170828

auto[1]

4591

1

T1

4

T7

9

T9

7

---

Summary for Cross rx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	10	120	92.31	10

Automatically Generated Cross Bins for rx_fifo_level_cg_cc

Uncovered bins

cp_lvl	cp_rst	COUNT	AT LEAST	NUMBER	STATUS
[all_levels[32]]	[auto[1]]	0	1	1
[all_levels[34]]	[auto[1]]	0	1	1
[all_levels[51] , all_levels[52]]	[auto[1]]	--	--	2
[all_levels[54]]	[auto[1]]	0	1	1
[all_levels[56] , all_levels[57]]	[auto[1]]	--	--	2
[all_levels[59] , all_levels[60] , all_levels[61]]	[auto[1]]	--	--	3

Covered bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	21572977	1			T1	19		T3	50		T5	168102
all_levels[0]	auto[1]	4120	1			T1	2		T7	8		T9	4
all_levels[1]	auto[0]	148329	1			T1	1		T3	9		T5	2726
all_levels[1]	auto[1]	78	1			T7	1		T42	1		T105	1
all_levels[2]	auto[0]	1822	1			T7	22		T8	10		T113	3
all_levels[2]	auto[1]	39	1			T114	2		T184	1		T185	2
all_levels[3]	auto[0]	784	1			T7	3		T8	12		T12	1
all_levels[3]	auto[1]	13	1			T186	2		T187	1		T188	1
all_levels[4]	auto[0]	612	1			T1	3		T7	5		T8	6
all_levels[4]	auto[1]	20	1			T128	1		T189	1		T184	2
all_levels[5]	auto[0]	445	1			T7	3		T8	5		T18	2
all_levels[5]	auto[1]	18	1			T190	2		T191	3		T192	1
all_levels[6]	auto[0]	349	1			T1	3		T8	4		T113	1
all_levels[6]	auto[1]	15	1			T133	1		T193	3		T194	2
all_levels[7]	auto[0]	309	1			T1	1		T7	5		T8	1
all_levels[7]	auto[1]	6	1			T1	1		T114	1		T48	1
all_levels[8]	auto[0]	257	1			T1	4		T7	1		T127	1
all_levels[8]	auto[1]	18	1			T195	1		T196	2		T197	2
all_levels[9]	auto[0]	208	1			T1	1		T7	2		T127	1
all_levels[9]	auto[1]	20	1			T138	1		T198	2		T199	12
all_levels[10]	auto[0]	177	1			T1	1		T7	1		T13	1
all_levels[10]	auto[1]	10	1			T48	3		T200	1		T201	1
all_levels[11]	auto[0]	158	1			T1	2		T7	4		T18	2
all_levels[11]	auto[1]	8	1			T1	1		T202	1		T203	2
all_levels[12]	auto[0]	142	1			T1	1		T7	2		T105	1
all_levels[12]	auto[1]	14	1			T191	1		T204	2		T205	2
all_levels[13]	auto[0]	135	1			T9	1		T18	2		T16	2
all_levels[13]	auto[1]	11	1			T9	1		T206	2		T203	1
all_levels[14]	auto[0]	112	1			T1	1		T12	1		T128	1
all_levels[14]	auto[1]	11	1			T203	1		T57	1		T207	2
all_levels[15]	auto[0]	109	1			T7	1		T16	1		T128	1
all_levels[15]	auto[1]	16	1			T208	1		T209	1		T210	1
all_levels[16]	auto[0]	96	1			T1	1		T7	1		T128	2
all_levels[16]	auto[1]	44	1			T211	3		T156	1		T212	1
all_levels[17]	auto[0]	76	1			T18	1		T13	1		T129	1
all_levels[17]	auto[1]	7	1			T213	1		T214	1		T215	1
all_levels[18]	auto[0]	72	1			T7	2		T129	1		T32	1
all_levels[18]	auto[1]	10	1			T153	1		T216	5		T217	1
all_levels[19]	auto[0]	61	1			T7	1		T129	1		T130	1
all_levels[19]	auto[1]	3	1			T218	1		T219	1		T220	1
all_levels[20]	auto[0]	58	1			T31	1		T131	1		T130	1
all_levels[20]	auto[1]	3	1			T158	1		T221	1		T222	1
all_levels[21]	auto[0]	58	1			T42	1		T109	1		T131	1
all_levels[21]	auto[1]	10	1			T42	2		T109	3		T190	1
all_levels[22]	auto[0]	53	1			T7	1		T18	1		T128	2
all_levels[22]	auto[1]	5	1			T135	1		T199	1		T75	1
all_levels[23]	auto[0]	40	1			T11	1		T128	1		T132	1
all_levels[23]	auto[1]	2	1			T223	2		-	-		-	-
all_levels[24]	auto[0]	44	1			T128	1		T107	1		T109	1
all_levels[24]	auto[1]	6	1			T109	2		T216	1		T224	1
all_levels[25]	auto[0]	35	1			T7	1		T107	1		T133	1
all_levels[25]	auto[1]	2	1			T148	1		T198	1		-	-
all_levels[26]	auto[0]	29	1			T31	1		T131	1		T133	1
all_levels[26]	auto[1]	3	1			T225	2		T226	1		-	-
all_levels[27]	auto[0]	42	1			T107	1		T134	1		T135	1
all_levels[27]	auto[1]	4	1			T134	1		T135	2		T56	1
all_levels[28]	auto[0]	45	1			T107	1		T136	1		T133	1
all_levels[28]	auto[1]	2	1			T227	1		T228	1		-	-
all_levels[29]	auto[0]	37	1			T1	1		T16	1		T130	1
all_levels[29]	auto[1]	1	1			T229	1		-	-		-	-
all_levels[30]	auto[0]	37	1			T7	2		T107	1		T137	1
all_levels[30]	auto[1]	2	1			T230	2		-	-		-	-
all_levels[31]	auto[0]	29	1			T114	1		T131	1		T130	1
all_levels[31]	auto[1]	2	1			T114	1		T231	1		-	-
all_levels[32]	auto[0]	20	1			T138	1		T139	1		T137	1
all_levels[33]	auto[0]	28	1			T18	1		T16	1		T140	1
all_levels[33]	auto[1]	2	1			T232	2		-	-		-	-
all_levels[34]	auto[0]	17	1			T140	1		T141	1		T142	1
all_levels[35]	auto[0]	20	1			T143	1		T144	1		T145	1
all_levels[35]	auto[1]	2	1			T233	1		T234	1		-	-
all_levels[36]	auto[0]	18	1			T11	1		T16	1		T137	1
all_levels[36]	auto[1]	4	1			T11	2		T100	1		T235	1
all_levels[37]	auto[0]	23	1			T16	2		T138	1		T135	1
all_levels[37]	auto[1]	1	1			T236	1		-	-		-	-
all_levels[38]	auto[0]	15	1			T146	1		T147	1		T148	1
all_levels[38]	auto[1]	1	1			T237	1		-	-		-	-
all_levels[39]	auto[0]	18	1			T149	1		T111	1		T150	1
all_levels[39]	auto[1]	2	1			T111	1		T238	1		-	-
all_levels[40]	auto[0]	20	1			T136	1		T100	1		T147	1
all_levels[40]	auto[1]	1	1			T239	1		-	-		-	-
all_levels[41]	auto[0]	21	1			T12	1		T129	1		T136	1
all_levels[41]	auto[1]	1	1			T240	1		-	-		-	-
all_levels[42]	auto[0]	16	1			T108	1		T140	1		T147	1
all_levels[42]	auto[1]	4	1			T56	1		T241	3		-	-
all_levels[43]	auto[0]	18	1			T31	1		T151	1		T100	1
all_levels[43]	auto[1]	1	1			T242	1		-	-		-	-
all_levels[44]	auto[0]	18	1			T149	1		T34	2		T142	1
all_levels[44]	auto[1]	1	1			T243	1		-	-		-	-
all_levels[45]	auto[0]	8	1			T12	1		T137	1		T152	1
all_levels[45]	auto[1]	2	1			T152	1		T244	1		-	-
all_levels[46]	auto[0]	18	1			T140	2		T153	1		T111	1
all_levels[46]	auto[1]	5	1			T111	1		T155	1		T245	1
all_levels[47]	auto[0]	13	1			T16	1		T154	1		T155	1
all_levels[47]	auto[1]	2	1			T154	1		T246	1		-	-
all_levels[48]	auto[0]	13	1			T148	1		T156	2		T157	1
all_levels[48]	auto[1]	3	1			T247	2		T248	1		-	-
all_levels[49]	auto[0]	12	1			T130	1		T158	1		T159	1
all_levels[49]	auto[1]	4	1			T249	4		-	-		-	-
all_levels[50]	auto[0]	10	1			T111	1		T160	1		T161	1
all_levels[50]	auto[1]	4	1			T250	1		T242	1		T251	1
all_levels[51]	auto[0]	12	1			T16	1		T162	1		T163	1
all_levels[52]	auto[0]	10	1			T32	1		T141	1		T162	1
all_levels[53]	auto[0]	6	1			T133	1		T139	1		T121	2
all_levels[53]	auto[1]	1	1			T133	1		-	-		-	-
all_levels[54]	auto[0]	2	1			T164	1		T165	1		-	-
all_levels[55]	auto[0]	5	1			T166	1		T167	1		T168	1
all_levels[55]	auto[1]	3	1			T222	3		-	-		-	-
all_levels[56]	auto[0]	6	1			T169	1		T170	1		T171	1
all_levels[57]	auto[0]	4	1			T172	1		T173	1		T174	2
all_levels[58]	auto[0]	11	1			T16	1		T47	1		T175	1
all_levels[58]	auto[1]	3	1			T16	2		T252	1		-	-
all_levels[59]	auto[0]	4	1			T176	1		T148	1		T177	1
all_levels[60]	auto[0]	7	1			T131	1		T175	1		T178	1
all_levels[61]	auto[0]	6	1			T143	1		T179	1		T57	1
all_levels[62]	auto[0]	7	1			T163	1		T180	1		T181	1
all_levels[62]	auto[1]	2	1			T180	1		T253	1		-	-
all_levels[63]	auto[0]	6	1			T176	1		T182	1		T183	1
all_levels[63]	auto[1]	2	1			T226	1		T174	1		-	-
all_levels[64]	auto[0]	101	1			T9	1		T12	3		T42	1
all_levels[64]	auto[1]	17	1			T9	2		T197	1		T254	1