Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	9	0	9	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	76207	1			T1	7		T2	2		T3	9
all_pins[1]	76207	1			T1	7		T2	2		T3	9
all_pins[2]	76207	1			T1	7		T2	2		T3	9
all_pins[3]	76207	1			T1	7		T2	2		T3	9
all_pins[4]	76207	1			T1	7		T2	2		T3	9
all_pins[5]	76207	1			T1	7		T2	2		T3	9
all_pins[6]	76207	1			T1	7		T2	2		T3	9
all_pins[7]	76207	1			T1	7		T2	2		T3	9
all_pins[8]	76207	1			T1	7		T2	2		T3	9

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	652397	1			T1	62		T2	18		T3	69
values[0x1]	33466	1			T1	1		T3	12		T5	21
transitions[0x0=>0x1]	26433	1			T1	1		T3	11		T5	21
transitions[0x1=>0x0]	26220	1			T1	1		T3	10		T5	20

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	60545	1			T1	7		T2	2		T3	2
all_pins[0]	values[0x1]	15662	1			T3	7		T5	14		T7	33
all_pins[0]	transitions[0x0=>0x1]	15139	1			T3	7		T5	14		T7	8
all_pins[0]	transitions[0x1=>0x0]	997	1			T1	1		T7	3		T9	1
all_pins[1]	values[0x0]	74687	1			T1	6		T2	2		T3	9
all_pins[1]	values[0x1]	1520	1			T1	1		T7	28		T9	1
all_pins[1]	transitions[0x0=>0x1]	1404	1			T1	1		T7	28		T9	1
all_pins[1]	transitions[0x1=>0x0]	1990	1			T3	1		T5	5		T7	7
all_pins[2]	values[0x0]	74101	1			T1	7		T2	2		T3	8
all_pins[2]	values[0x1]	2106	1			T3	1		T5	5		T7	7
all_pins[2]	transitions[0x0=>0x1]	2034	1			T3	1		T5	5		T7	7
all_pins[2]	transitions[0x1=>0x0]	261	1			T13	1		T42	1		T32	2
all_pins[3]	values[0x0]	75874	1			T1	7		T2	2		T3	9
all_pins[3]	values[0x1]	333	1			T9	1		T13	1		T16	1
all_pins[3]	transitions[0x0=>0x1]	293	1			T9	1		T13	1		T16	1
all_pins[3]	transitions[0x1=>0x0]	373	1			T13	4		T16	9		T89	7
all_pins[4]	values[0x0]	75794	1			T1	7		T2	2		T3	9
all_pins[4]	values[0x1]	413	1			T13	4		T16	9		T89	7
all_pins[4]	transitions[0x0=>0x1]	361	1			T13	4		T16	9		T89	5
all_pins[4]	transitions[0x1=>0x0]	137	1			T13	1		T17	1		T256	1
all_pins[5]	values[0x0]	76018	1			T1	7		T2	2		T3	9
all_pins[5]	values[0x1]	189	1			T13	1		T17	1		T89	2
all_pins[5]	transitions[0x0=>0x1]	164	1			T13	1		T17	1		T89	2
all_pins[5]	transitions[0x1=>0x0]	618	1			T3	2		T5	1		T7	5
all_pins[6]	values[0x0]	75564	1			T1	7		T2	2		T3	7
all_pins[6]	values[0x1]	643	1			T3	2		T5	1		T7	5
all_pins[6]	transitions[0x0=>0x1]	606	1			T3	2		T5	1		T7	5
all_pins[6]	transitions[0x1=>0x0]	257	1			T16	2		T136	7		T255	7
all_pins[7]	values[0x0]	75913	1			T1	7		T2	2		T3	9
all_pins[7]	values[0x1]	294	1			T16	3		T136	7		T255	7
all_pins[7]	transitions[0x0=>0x1]	168	1			T16	2		T136	7		T255	7
all_pins[7]	transitions[0x1=>0x0]	12180	1			T3	2		T5	1		T7	25
all_pins[8]	values[0x0]	63901	1			T1	7		T2	2		T3	7
all_pins[8]	values[0x1]	12306	1			T3	2		T5	1		T7	25
all_pins[8]	transitions[0x0=>0x1]	6264	1			T3	1		T5	1		T7	9
all_pins[8]	transitions[0x1=>0x0]	9407	1			T3	5		T5	13		T7	16