Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::tx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::tx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	35	0	35	100.00
Crosses	66	0	66	100.00

Variables for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	33	0	33	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tx_fifo_level_cg_cc	66	0	66	100.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	4880650	1			T1	29		T3	12		T5	5698
all_levels[1]	1097979	1			T1	1		T3	8		T5	205
all_levels[2]	259999	1			T1	1		T5	200		T7	5
all_levels[3]	172866	1			T5	187		T7	304		T8	1354
all_levels[4]	193390	1			T3	5		T5	196		T7	7
all_levels[5]	414682	1			T3	9		T5	208		T7	3
all_levels[6]	190162	1			T1	2		T3	8		T5	193
all_levels[7]	327970	1			T3	4		T5	197		T7	12
all_levels[8]	198384	1			T1	6		T3	5		T5	196
all_levels[9]	162902	1			T3	4		T5	187		T7	2
all_levels[10]	180929	1			T1	1		T3	2		T5	198
all_levels[11]	157245	1			T5	194		T7	6		T8	309
all_levels[12]	137175	1			T5	204		T7	13		T8	685
all_levels[13]	177920	1			T1	1		T5	193		T7	7
all_levels[14]	131457	1			T5	207		T7	25		T8	1428
all_levels[15]	217658	1			T5	198		T7	1		T8	959
all_levels[16]	259247	1			T1	1		T5	187		T7	8
all_levels[17]	159954	1			T5	199		T7	9		T8	1412
all_levels[18]	272630	1			T5	203		T7	5		T8	1287
all_levels[19]	136941	1			T3	3		T5	215		T7	9
all_levels[20]	233539	1			T5	194		T7	9		T8	1229
all_levels[21]	119741	1			T5	179		T7	5		T8	1552
all_levels[22]	120241	1			T5	213		T7	4		T8	1544
all_levels[23]	120032	1			T5	204		T7	1		T8	1102
all_levels[24]	117037	1			T5	207		T7	9		T8	1097
all_levels[25]	161846	1			T5	203		T7	8		T8	1531
all_levels[26]	107873	1			T5	193		T7	6		T8	1440
all_levels[27]	236960	1			T5	226		T7	4		T8	1386
all_levels[28]	109115	1			T5	183		T7	5		T8	949
all_levels[29]	104220	1			T5	212		T7	6		T8	1299
all_levels[30]	98735	1			T5	193		T7	9		T8	1457
all_levels[31]	423001	1			T5	5542		T7	16		T8	2981
all_levels[32]	10050009	1			T5	153615		T7	227		T8	17269

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21728250

1

T1

39

T3

59

T5

170828

auto[1]

4239

1

T1

3

T3

1

T5

1

---

Summary for Cross tx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	66	0	66	100.00

Automatically Generated Cross Bins for tx_fifo_level_cg_cc

Bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	4878232	1			T1	27		T3	12		T5	5698
all_levels[0]	auto[1]	2418	1			T1	2		T7	6		T9	5
all_levels[1]	auto[0]	1097679	1			T1	1		T3	8		T5	205
all_levels[1]	auto[1]	300	1			T9	3		T38	2		T16	3
all_levels[2]	auto[0]	259965	1			T1	1		T5	200		T7	5
all_levels[2]	auto[1]	34	1			T113	1		T135	1		T290	1
all_levels[3]	auto[0]	172701	1			T5	187		T7	302		T8	1354
all_levels[3]	auto[1]	165	1			T7	2		T16	4		T128	1
all_levels[4]	auto[0]	193366	1			T3	5		T5	196		T7	7
all_levels[4]	auto[1]	24	1			T208	2		T134	1		T193	3
all_levels[5]	auto[0]	414659	1			T3	9		T5	208		T7	3
all_levels[5]	auto[1]	23	1			T271	1		T257	2		T134	1
all_levels[6]	auto[0]	190141	1			T1	2		T3	8		T5	193
all_levels[6]	auto[1]	21	1			T134	1		T152	2		T324	1
all_levels[7]	auto[0]	327855	1			T3	4		T5	197		T7	12
all_levels[7]	auto[1]	115	1			T277	1		T317	2		T54	1
all_levels[8]	auto[0]	198355	1			T1	5		T3	5		T5	196
all_levels[8]	auto[1]	29	1			T1	1		T16	1		T271	2
all_levels[9]	auto[0]	162887	1			T3	4		T5	187		T7	2
all_levels[9]	auto[1]	15	1			T114	1		T135	1		T180	2
all_levels[10]	auto[0]	180895	1			T1	1		T3	2		T5	198
all_levels[10]	auto[1]	34	1			T48	1		T206	2		T236	1
all_levels[11]	auto[0]	157214	1			T5	194		T7	6		T8	309
all_levels[11]	auto[1]	31	1			T184	1		T208	1		T185	2
all_levels[12]	auto[0]	137153	1			T5	204		T7	13		T8	685
all_levels[12]	auto[1]	22	1			T190	2		T139	1		T318	1
all_levels[13]	auto[0]	177896	1			T1	1		T5	193		T7	7
all_levels[13]	auto[1]	24	1			T42	1		T138	1		T48	3
all_levels[14]	auto[0]	131424	1			T5	207		T7	25		T8	1428
all_levels[14]	auto[1]	33	1			T108	2		T332	1		T324	1
all_levels[15]	auto[0]	217494	1			T5	198		T7	1		T8	959
all_levels[15]	auto[1]	164	1			T37	1		T13	29		T88	4
all_levels[16]	auto[0]	259230	1			T1	1		T5	187		T7	8
all_levels[16]	auto[1]	17	1			T184	2		T191	1		T196	3
all_levels[17]	auto[0]	159934	1			T5	199		T7	9		T8	1412
all_levels[17]	auto[1]	20	1			T310	1		T333	2		T334	1
all_levels[18]	auto[0]	272609	1			T5	203		T7	5		T8	1287
all_levels[18]	auto[1]	21	1			T108	1		T56	1		T335	1
all_levels[19]	auto[0]	136918	1			T3	2		T5	215		T7	9
all_levels[19]	auto[1]	23	1			T3	1		T114	1		T189	1
all_levels[20]	auto[0]	233525	1			T5	194		T7	9		T8	1229
all_levels[20]	auto[1]	14	1			T38	2		T287	1		T218	1
all_levels[21]	auto[0]	119730	1			T5	179		T7	4		T8	1552
all_levels[21]	auto[1]	11	1			T7	1		T11	1		T275	1
all_levels[22]	auto[0]	120180	1			T5	213		T7	4		T8	1544
all_levels[22]	auto[1]	61	1			T208	1		T266	3		T48	1
all_levels[23]	auto[0]	120015	1			T5	204		T7	1		T8	1102
all_levels[23]	auto[1]	17	1			T281	1		T197	1		T147	1
all_levels[24]	auto[0]	117028	1			T5	207		T7	9		T8	1097
all_levels[24]	auto[1]	9	1			T109	2		T299	1		T336	1
all_levels[25]	auto[0]	161834	1			T5	203		T7	8		T8	1531
all_levels[25]	auto[1]	12	1			T11	1		T317	2		T48	1
all_levels[26]	auto[0]	107862	1			T5	193		T7	6		T8	1440
all_levels[26]	auto[1]	11	1			T190	1		T337	2		T338	1
all_levels[27]	auto[0]	236950	1			T5	226		T7	4		T8	1386
all_levels[27]	auto[1]	10	1			T131	1		T145	2		T339	1
all_levels[28]	auto[0]	109085	1			T5	183		T7	5		T8	949
all_levels[28]	auto[1]	30	1			T186	2		T151	1		T218	2
all_levels[29]	auto[0]	104214	1			T5	212		T7	6		T8	1299
all_levels[29]	auto[1]	6	1			T47	1		T340	1		T112	1
all_levels[30]	auto[0]	98708	1			T5	193		T7	9		T8	1457
all_levels[30]	auto[1]	27	1			T257	4		T134	1		T186	3
all_levels[31]	auto[0]	422984	1			T5	5542		T7	16		T8	2981
all_levels[31]	auto[1]	17	1			T133	2		T138	1		T202	3
all_levels[32]	auto[0]	10049528	1			T5	153614		T7	223		T8	17269
all_levels[32]	auto[1]	481	1			T5	1		T7	4		T11	3