Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.30	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	54	6	48	88.89

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	54	6	48	88.89	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	579	1			T16	4		T34	15		T46	4
all_values[1]	579	1			T16	4		T34	15		T46	4
all_values[2]	579	1			T16	4		T34	15		T46	4
all_values[3]	579	1			T16	4		T34	15		T46	4
all_values[4]	579	1			T16	4		T34	15		T46	4
all_values[5]	579	1			T16	4		T34	15		T46	4
all_values[6]	579	1			T16	4		T34	15		T46	4
all_values[7]	579	1			T16	4		T34	15		T46	4
all_values[8]	579	1			T16	4		T34	15		T46	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2798

1

T16

24

T34

82

T46

19

auto[1]

2413

1

T16

12

T34

53

T46

17

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1696

1

T16

9

T34

40

T46

12

auto[1]

3515

1

T16

27

T34

95

T46

24

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3070

1

T16

23

T34

70

T46

19

auto[1]

2141

1

T16

13

T34

65

T46

17

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	54	6	48	88.89	6
Automatically Generated Cross Bins	54	6	48	88.89	6
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	*	[auto[0]]	--	--	2
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2
[all_values[8]]	[auto[0]]	*	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	193	1			T16	1		T34	3		T117	1
all_values[0]	auto[0]	auto[1]	auto[1]	147	1			T16	2		T34	4		T46	1
all_values[0]	auto[1]	auto[0]	auto[1]	132	1			T34	4		T46	3		T111	1
all_values[0]	auto[1]	auto[1]	auto[1]	107	1			T16	1		T34	4		T117	2
all_values[1]	auto[0]	auto[0]	auto[0]	195	1			T16	2		T34	3		T46	2
all_values[1]	auto[0]	auto[1]	auto[0]	148	1			T34	6		T117	1		T111	3
all_values[1]	auto[1]	auto[0]	auto[1]	119	1			T16	1		T34	4		T117	1
all_values[1]	auto[1]	auto[1]	auto[1]	117	1			T16	1		T34	2		T46	2
all_values[2]	auto[0]	auto[0]	auto[0]	108	1			T16	1		T34	4		T46	1
all_values[2]	auto[0]	auto[0]	auto[1]	69	1			T34	3		T46	1		T117	1
all_values[2]	auto[0]	auto[1]	auto[0]	87	1			T118	5		T119	1		T120	2
all_values[2]	auto[0]	auto[1]	auto[1]	66	1			T16	2		T34	1		T118	1
all_values[2]	auto[1]	auto[0]	auto[1]	135	1			T34	4		T46	1		T117	1
all_values[2]	auto[1]	auto[1]	auto[1]	114	1			T16	1		T34	3		T46	1
all_values[3]	auto[0]	auto[0]	auto[0]	112	1			T16	1		T34	1		T46	2
all_values[3]	auto[0]	auto[0]	auto[1]	39	1			T16	2		T34	1		T118	1
all_values[3]	auto[0]	auto[1]	auto[0]	97	1			T34	3		T117	2		T118	5
all_values[3]	auto[0]	auto[1]	auto[1]	81	1			T34	1		T46	1		T118	1
all_values[3]	auto[1]	auto[0]	auto[1]	122	1			T34	6		T46	1		T111	1
all_values[3]	auto[1]	auto[1]	auto[1]	128	1			T16	1		T34	3		T111	2
all_values[4]	auto[0]	auto[0]	auto[0]	137	1			T34	1		T46	2		T118	4
all_values[4]	auto[0]	auto[0]	auto[1]	53	1			T34	1		T117	1		T111	2
all_values[4]	auto[0]	auto[1]	auto[0]	111	1			T34	4		T46	1		T117	2
all_values[4]	auto[0]	auto[1]	auto[1]	51	1			T16	1		T102	1		T121	1
all_values[4]	auto[1]	auto[0]	auto[1]	137	1			T16	2		T34	7		T111	1
all_values[4]	auto[1]	auto[1]	auto[1]	90	1			T16	1		T34	2		T46	1
all_values[5]	auto[0]	auto[0]	auto[0]	114	1			T34	3		T117	2		T111	4
all_values[5]	auto[0]	auto[0]	auto[1]	61	1			T16	1		T34	2		T118	1
all_values[5]	auto[0]	auto[1]	auto[0]	98	1			T34	2		T46	1		T118	3
all_values[5]	auto[0]	auto[1]	auto[1]	59	1			T46	1		T118	1		T119	1
all_values[5]	auto[1]	auto[0]	auto[1]	147	1			T16	3		T34	6		T46	1
all_values[5]	auto[1]	auto[1]	auto[1]	100	1			T34	2		T46	1		T117	1
all_values[6]	auto[0]	auto[0]	auto[0]	136	1			T16	2		T34	7		T46	1
all_values[6]	auto[0]	auto[0]	auto[1]	56	1			T16	1		T34	2		T111	1
all_values[6]	auto[0]	auto[1]	auto[0]	101	1			T34	1		T117	1		T122	1
all_values[6]	auto[0]	auto[1]	auto[1]	51	1			T46	1		T118	2		T122	1
all_values[6]	auto[1]	auto[0]	auto[1]	131	1			T16	1		T34	4		T46	1
all_values[6]	auto[1]	auto[1]	auto[1]	104	1			T34	1		T46	1		T111	1
all_values[7]	auto[0]	auto[0]	auto[0]	123	1			T16	1		T34	1		T46	1
all_values[7]	auto[0]	auto[0]	auto[1]	43	1			T34	1		T120	1		T123	1
all_values[7]	auto[0]	auto[1]	auto[0]	129	1			T16	2		T34	4		T46	1
all_values[7]	auto[0]	auto[1]	auto[1]	55	1			T34	1		T117	1		T118	2
all_values[7]	auto[1]	auto[0]	auto[1]	128	1			T16	1		T34	4		T46	2
all_values[7]	auto[1]	auto[1]	auto[1]	101	1			T34	4		T117	2		T118	2
all_values[8]	auto[0]	auto[0]	auto[1]	174	1			T16	4		T34	7		T117	1
all_values[8]	auto[0]	auto[1]	auto[1]	176	1			T34	3		T46	2		T111	2
all_values[8]	auto[1]	auto[0]	auto[1]	134	1			T34	3		T111	1		T118	5
all_values[8]	auto[1]	auto[1]	auto[1]	95	1			T34	2		T46	2		T117	3

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal