Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.11 99.10 97.65 100.00 98.38 100.00 99.55


Total test records in report: 1222
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html
T1033 /workspace/coverage/default/23.uart_long_xfer_wo_dly.621869982 Jun 09 02:16:20 PM PDT 24 Jun 09 02:34:58 PM PDT 24 165829024333 ps
T1034 /workspace/coverage/default/32.uart_fifo_reset.1195239593 Jun 09 02:17:12 PM PDT 24 Jun 09 02:17:51 PM PDT 24 19865985949 ps
T1035 /workspace/coverage/default/292.uart_fifo_reset.3480809735 Jun 09 02:21:27 PM PDT 24 Jun 09 02:21:40 PM PDT 24 30470824044 ps
T1036 /workspace/coverage/default/286.uart_fifo_reset.3482935827 Jun 09 02:21:21 PM PDT 24 Jun 09 02:21:49 PM PDT 24 14803096590 ps
T1037 /workspace/coverage/default/34.uart_tx_ovrd.1090863436 Jun 09 02:17:35 PM PDT 24 Jun 09 02:17:52 PM PDT 24 6856620283 ps
T1038 /workspace/coverage/default/15.uart_alert_test.4237780166 Jun 09 02:15:19 PM PDT 24 Jun 09 02:15:20 PM PDT 24 40149257 ps
T1039 /workspace/coverage/default/21.uart_smoke.969567482 Jun 09 02:15:59 PM PDT 24 Jun 09 02:16:01 PM PDT 24 493209227 ps
T1040 /workspace/coverage/default/25.uart_rx_parity_err.2466530501 Jun 09 02:16:31 PM PDT 24 Jun 09 02:16:36 PM PDT 24 8994430986 ps
T1041 /workspace/coverage/default/36.uart_fifo_reset.4206428747 Jun 09 02:17:46 PM PDT 24 Jun 09 02:18:12 PM PDT 24 55925916698 ps
T1042 /workspace/coverage/default/45.uart_alert_test.3898303885 Jun 09 02:18:44 PM PDT 24 Jun 09 02:18:44 PM PDT 24 60856824 ps
T1043 /workspace/coverage/default/10.uart_stress_all_with_rand_reset.1713859281 Jun 09 02:14:30 PM PDT 24 Jun 09 02:17:04 PM PDT 24 12373709486 ps
T1044 /workspace/coverage/default/3.uart_stress_all.2570368225 Jun 09 02:13:26 PM PDT 24 Jun 09 02:14:36 PM PDT 24 30153165344 ps
T1045 /workspace/coverage/default/24.uart_stress_all_with_rand_reset.3275421871 Jun 09 02:16:22 PM PDT 24 Jun 09 02:33:28 PM PDT 24 83678536043 ps
T1046 /workspace/coverage/default/42.uart_fifo_full.2484435897 Jun 09 02:18:22 PM PDT 24 Jun 09 02:19:27 PM PDT 24 35403321127 ps
T1047 /workspace/coverage/default/14.uart_fifo_overflow.623694232 Jun 09 02:14:59 PM PDT 24 Jun 09 02:17:47 PM PDT 24 137692736763 ps
T1048 /workspace/coverage/default/14.uart_rx_parity_err.1204173945 Jun 09 02:15:05 PM PDT 24 Jun 09 02:15:42 PM PDT 24 36467245724 ps
T1049 /workspace/coverage/default/26.uart_long_xfer_wo_dly.3095290115 Jun 09 02:16:37 PM PDT 24 Jun 09 02:20:43 PM PDT 24 182953178616 ps
T1050 /workspace/coverage/default/25.uart_long_xfer_wo_dly.1717488815 Jun 09 02:16:31 PM PDT 24 Jun 09 02:21:18 PM PDT 24 117505760118 ps
T1051 /workspace/coverage/default/20.uart_smoke.3445932188 Jun 09 02:15:55 PM PDT 24 Jun 09 02:15:57 PM PDT 24 912538027 ps
T1052 /workspace/coverage/default/77.uart_fifo_reset.582359042 Jun 09 02:19:39 PM PDT 24 Jun 09 02:20:27 PM PDT 24 96225813600 ps
T1053 /workspace/coverage/default/7.uart_smoke.3240813352 Jun 09 02:13:57 PM PDT 24 Jun 09 02:14:01 PM PDT 24 624961079 ps
T1054 /workspace/coverage/default/41.uart_smoke.1424401100 Jun 09 02:18:15 PM PDT 24 Jun 09 02:18:17 PM PDT 24 488739257 ps
T1055 /workspace/coverage/default/40.uart_perf.1678224662 Jun 09 02:18:17 PM PDT 24 Jun 09 02:20:00 PM PDT 24 11443801730 ps
T252 /workspace/coverage/default/93.uart_fifo_reset.3488242360 Jun 09 02:19:45 PM PDT 24 Jun 09 02:20:16 PM PDT 24 64648785004 ps
T1056 /workspace/coverage/default/27.uart_loopback.405856847 Jun 09 02:16:41 PM PDT 24 Jun 09 02:16:44 PM PDT 24 6665702731 ps
T1057 /workspace/coverage/default/48.uart_rx_oversample.1500520786 Jun 09 02:18:59 PM PDT 24 Jun 09 02:19:05 PM PDT 24 3371435411 ps
T1058 /workspace/coverage/default/41.uart_stress_all.1976297927 Jun 09 02:18:21 PM PDT 24 Jun 09 02:20:08 PM PDT 24 445425904596 ps
T1059 /workspace/coverage/default/1.uart_intr.1325675729 Jun 09 02:12:58 PM PDT 24 Jun 09 02:13:59 PM PDT 24 35574236543 ps
T1060 /workspace/coverage/default/42.uart_long_xfer_wo_dly.4117435263 Jun 09 02:18:25 PM PDT 24 Jun 09 02:20:54 PM PDT 24 74534701349 ps
T1061 /workspace/coverage/default/13.uart_long_xfer_wo_dly.3756114781 Jun 09 02:15:01 PM PDT 24 Jun 09 02:22:54 PM PDT 24 60741008144 ps
T1062 /workspace/coverage/default/263.uart_fifo_reset.1419190844 Jun 09 02:21:15 PM PDT 24 Jun 09 02:22:04 PM PDT 24 24073697881 ps
T1063 /workspace/coverage/default/22.uart_fifo_reset.3074898299 Jun 09 02:16:06 PM PDT 24 Jun 09 02:16:36 PM PDT 24 79015180891 ps
T1064 /workspace/coverage/default/20.uart_intr.959655671 Jun 09 02:15:54 PM PDT 24 Jun 09 02:16:34 PM PDT 24 40898294684 ps
T241 /workspace/coverage/default/34.uart_fifo_reset.3832028404 Jun 09 02:17:26 PM PDT 24 Jun 09 02:19:21 PM PDT 24 128551341148 ps
T1065 /workspace/coverage/default/29.uart_long_xfer_wo_dly.1242202217 Jun 09 02:16:57 PM PDT 24 Jun 09 02:22:45 PM PDT 24 48566936202 ps
T1066 /workspace/coverage/default/252.uart_fifo_reset.2200504787 Jun 09 02:21:06 PM PDT 24 Jun 09 02:23:09 PM PDT 24 120571284470 ps
T1067 /workspace/coverage/default/57.uart_stress_all_with_rand_reset.2194319050 Jun 09 02:19:19 PM PDT 24 Jun 09 02:33:12 PM PDT 24 191314200264 ps
T1068 /workspace/coverage/default/18.uart_fifo_overflow.3602716781 Jun 09 02:15:37 PM PDT 24 Jun 09 02:16:38 PM PDT 24 73828226966 ps
T1069 /workspace/coverage/default/38.uart_loopback.107096338 Jun 09 02:18:03 PM PDT 24 Jun 09 02:18:24 PM PDT 24 11049278809 ps
T1070 /workspace/coverage/default/29.uart_fifo_full.4125923796 Jun 09 02:16:52 PM PDT 24 Jun 09 02:17:28 PM PDT 24 77065573672 ps
T1071 /workspace/coverage/default/234.uart_fifo_reset.3954250408 Jun 09 02:21:01 PM PDT 24 Jun 09 02:21:28 PM PDT 24 54922386625 ps
T1072 /workspace/coverage/default/6.uart_smoke.3823116875 Jun 09 02:13:51 PM PDT 24 Jun 09 02:13:53 PM PDT 24 427704005 ps
T1073 /workspace/coverage/default/94.uart_stress_all_with_rand_reset.3207090531 Jun 09 02:19:47 PM PDT 24 Jun 09 02:50:49 PM PDT 24 91060321310 ps
T1074 /workspace/coverage/default/14.uart_loopback.1687521535 Jun 09 02:15:05 PM PDT 24 Jun 09 02:15:13 PM PDT 24 5270706811 ps
T1075 /workspace/coverage/default/26.uart_fifo_full.2568338760 Jun 09 02:16:35 PM PDT 24 Jun 09 02:18:31 PM PDT 24 70893389258 ps
T1076 /workspace/coverage/default/127.uart_fifo_reset.2947332388 Jun 09 02:20:09 PM PDT 24 Jun 09 02:33:36 PM PDT 24 98464332643 ps
T1077 /workspace/coverage/default/27.uart_tx_ovrd.3124033667 Jun 09 02:16:43 PM PDT 24 Jun 09 02:17:04 PM PDT 24 6639220537 ps
T1078 /workspace/coverage/default/34.uart_intr.2234512036 Jun 09 02:17:30 PM PDT 24 Jun 09 02:17:56 PM PDT 24 29909161529 ps
T1079 /workspace/coverage/default/30.uart_tx_ovrd.693805357 Jun 09 02:17:01 PM PDT 24 Jun 09 02:17:03 PM PDT 24 325398457 ps
T1080 /workspace/coverage/default/46.uart_rx_parity_err.3329395404 Jun 09 02:18:48 PM PDT 24 Jun 09 02:20:05 PM PDT 24 42613644059 ps
T1081 /workspace/coverage/default/149.uart_fifo_reset.1669710084 Jun 09 02:20:19 PM PDT 24 Jun 09 02:20:50 PM PDT 24 293620410663 ps
T1082 /workspace/coverage/default/46.uart_intr.851245751 Jun 09 02:18:52 PM PDT 24 Jun 09 02:19:47 PM PDT 24 29906875266 ps
T1083 /workspace/coverage/default/4.uart_rx_oversample.651206716 Jun 09 02:13:30 PM PDT 24 Jun 09 02:13:36 PM PDT 24 1802267853 ps
T1084 /workspace/coverage/default/9.uart_long_xfer_wo_dly.2110742785 Jun 09 02:14:21 PM PDT 24 Jun 09 02:25:40 PM PDT 24 63890725377 ps
T1085 /workspace/coverage/default/64.uart_fifo_reset.745050315 Jun 09 02:19:23 PM PDT 24 Jun 09 02:20:59 PM PDT 24 64050823946 ps
T1086 /workspace/coverage/default/155.uart_fifo_reset.2691209821 Jun 09 02:20:25 PM PDT 24 Jun 09 02:21:18 PM PDT 24 144802245472 ps
T1087 /workspace/coverage/default/17.uart_stress_all.1516757217 Jun 09 02:15:34 PM PDT 24 Jun 09 02:22:04 PM PDT 24 220603287938 ps
T79 /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.2603392276 Jun 09 12:35:48 PM PDT 24 Jun 09 12:35:49 PM PDT 24 90015494 ps
T1088 /workspace/coverage/cover_reg_top/13.uart_tl_errors.3633302514 Jun 09 12:35:57 PM PDT 24 Jun 09 12:36:00 PM PDT 24 235104071 ps
T90 /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.1917402894 Jun 09 12:35:56 PM PDT 24 Jun 09 12:35:58 PM PDT 24 90068674 ps
T91 /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.2880344075 Jun 09 12:35:51 PM PDT 24 Jun 09 12:35:53 PM PDT 24 365167162 ps
T1089 /workspace/coverage/cover_reg_top/19.uart_tl_errors.146375280 Jun 09 12:35:59 PM PDT 24 Jun 09 12:36:02 PM PDT 24 113249345 ps
T92 /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.2105780507 Jun 09 12:35:44 PM PDT 24 Jun 09 12:35:45 PM PDT 24 53867646 ps
T1090 /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.1683213420 Jun 09 12:35:53 PM PDT 24 Jun 09 12:35:54 PM PDT 24 74693402 ps
T1091 /workspace/coverage/cover_reg_top/19.uart_csr_rw.1481366761 Jun 09 12:35:50 PM PDT 24 Jun 09 12:35:52 PM PDT 24 11648236 ps
T1092 /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.701052065 Jun 09 12:35:49 PM PDT 24 Jun 09 12:35:50 PM PDT 24 439119283 ps
T124 /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.3946827592 Jun 09 12:35:51 PM PDT 24 Jun 09 12:35:53 PM PDT 24 51357478 ps
T1093 /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.3965015971 Jun 09 12:35:58 PM PDT 24 Jun 09 12:36:00 PM PDT 24 28698174 ps
T1094 /workspace/coverage/cover_reg_top/5.uart_tl_errors.1502877900 Jun 09 12:35:56 PM PDT 24 Jun 09 12:35:57 PM PDT 24 68233937 ps
T1095 /workspace/coverage/cover_reg_top/37.uart_intr_test.1360078036 Jun 09 12:35:56 PM PDT 24 Jun 09 12:35:57 PM PDT 24 12847092 ps
T80 /workspace/coverage/cover_reg_top/11.uart_csr_rw.1017037841 Jun 09 12:35:51 PM PDT 24 Jun 09 12:35:52 PM PDT 24 13410647 ps
T1096 /workspace/coverage/cover_reg_top/45.uart_intr_test.3147823487 Jun 09 12:36:03 PM PDT 24 Jun 09 12:36:03 PM PDT 24 13550413 ps
T1097 /workspace/coverage/cover_reg_top/4.uart_tl_errors.2518776809 Jun 09 12:36:03 PM PDT 24 Jun 09 12:36:04 PM PDT 24 48721906 ps
T1098 /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.3943928061 Jun 09 12:35:49 PM PDT 24 Jun 09 12:35:51 PM PDT 24 51105686 ps
T1099 /workspace/coverage/cover_reg_top/42.uart_intr_test.3408725431 Jun 09 12:35:55 PM PDT 24 Jun 09 12:35:56 PM PDT 24 74480558 ps
T1100 /workspace/coverage/cover_reg_top/40.uart_intr_test.165701661 Jun 09 12:35:56 PM PDT 24 Jun 09 12:35:57 PM PDT 24 11536201 ps
T1101 /workspace/coverage/cover_reg_top/2.uart_tl_errors.2406002554 Jun 09 12:35:49 PM PDT 24 Jun 09 12:35:50 PM PDT 24 48222540 ps
T60 /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.4151659253 Jun 09 12:35:49 PM PDT 24 Jun 09 12:35:50 PM PDT 24 14474590 ps
T1102 /workspace/coverage/cover_reg_top/48.uart_intr_test.282256910 Jun 09 12:36:09 PM PDT 24 Jun 09 12:36:10 PM PDT 24 13728632 ps
T81 /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.2852412150 Jun 09 12:35:48 PM PDT 24 Jun 09 12:35:49 PM PDT 24 16677609 ps
T1103 /workspace/coverage/cover_reg_top/4.uart_intr_test.345993763 Jun 09 12:35:53 PM PDT 24 Jun 09 12:35:54 PM PDT 24 42314519 ps
T93 /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.1696828586 Jun 09 12:35:54 PM PDT 24 Jun 09 12:35:55 PM PDT 24 330972929 ps
T1104 /workspace/coverage/cover_reg_top/38.uart_intr_test.682580142 Jun 09 12:35:49 PM PDT 24 Jun 09 12:35:55 PM PDT 24 20245789 ps
T1105 /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.626881104 Jun 09 12:36:29 PM PDT 24 Jun 09 12:36:31 PM PDT 24 72032964 ps
T1106 /workspace/coverage/cover_reg_top/0.uart_intr_test.1248440219 Jun 09 12:35:47 PM PDT 24 Jun 09 12:35:49 PM PDT 24 15569374 ps
T61 /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.3018359101 Jun 09 12:35:48 PM PDT 24 Jun 09 12:35:49 PM PDT 24 13849864 ps
T1107 /workspace/coverage/cover_reg_top/7.uart_tl_errors.2257222790 Jun 09 12:35:44 PM PDT 24 Jun 09 12:35:46 PM PDT 24 25927269 ps
T1108 /workspace/coverage/cover_reg_top/5.uart_csr_rw.1639698636 Jun 09 12:35:57 PM PDT 24 Jun 09 12:35:59 PM PDT 24 80993086 ps
T82 /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.3156005252 Jun 09 12:35:57 PM PDT 24 Jun 09 12:35:59 PM PDT 24 49899144 ps
T62 /workspace/coverage/cover_reg_top/13.uart_csr_rw.4049923358 Jun 09 12:35:57 PM PDT 24 Jun 09 12:35:59 PM PDT 24 48753158 ps
T63 /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.1845709489 Jun 09 12:35:50 PM PDT 24 Jun 09 12:35:51 PM PDT 24 47102657 ps
T83 /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.1388214763 Jun 09 12:35:47 PM PDT 24 Jun 09 12:35:48 PM PDT 24 58328243 ps
T1109 /workspace/coverage/cover_reg_top/20.uart_intr_test.780272863 Jun 09 12:35:56 PM PDT 24 Jun 09 12:35:57 PM PDT 24 13873973 ps
T84 /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.424096038 Jun 09 12:35:59 PM PDT 24 Jun 09 12:36:01 PM PDT 24 110020154 ps
T1110 /workspace/coverage/cover_reg_top/25.uart_intr_test.2112947033 Jun 09 12:36:07 PM PDT 24 Jun 09 12:36:08 PM PDT 24 17319246 ps
T1111 /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.1952527348 Jun 09 12:35:57 PM PDT 24 Jun 09 12:35:59 PM PDT 24 37292340 ps
T1112 /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.2705872982 Jun 09 12:35:44 PM PDT 24 Jun 09 12:35:46 PM PDT 24 178818812 ps
T1113 /workspace/coverage/cover_reg_top/6.uart_intr_test.272230793 Jun 09 12:35:55 PM PDT 24 Jun 09 12:35:56 PM PDT 24 15607869 ps
T1114 /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.1083693668 Jun 09 12:35:57 PM PDT 24 Jun 09 12:35:59 PM PDT 24 28748702 ps
T85 /workspace/coverage/cover_reg_top/7.uart_csr_rw.900852202 Jun 09 12:35:59 PM PDT 24 Jun 09 12:36:01 PM PDT 24 43251411 ps
T1115 /workspace/coverage/cover_reg_top/36.uart_intr_test.2670941790 Jun 09 12:35:50 PM PDT 24 Jun 09 12:35:51 PM PDT 24 78471249 ps
T1116 /workspace/coverage/cover_reg_top/18.uart_intr_test.3138540960 Jun 09 12:35:59 PM PDT 24 Jun 09 12:36:01 PM PDT 24 22165884 ps
T1117 /workspace/coverage/cover_reg_top/26.uart_intr_test.1432071337 Jun 09 12:35:57 PM PDT 24 Jun 09 12:35:59 PM PDT 24 11310823 ps
T1118 /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.1058678289 Jun 09 12:35:49 PM PDT 24 Jun 09 12:35:51 PM PDT 24 48978356 ps
T125 /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.2475565656 Jun 09 12:35:56 PM PDT 24 Jun 09 12:35:58 PM PDT 24 185866454 ps
T1119 /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.2644394362 Jun 09 12:35:51 PM PDT 24 Jun 09 12:35:52 PM PDT 24 164067149 ps
T1120 /workspace/coverage/cover_reg_top/29.uart_intr_test.3127405164 Jun 09 12:35:51 PM PDT 24 Jun 09 12:35:53 PM PDT 24 25844694 ps
T1121 /workspace/coverage/cover_reg_top/32.uart_intr_test.4146994950 Jun 09 12:35:54 PM PDT 24 Jun 09 12:35:55 PM PDT 24 44126230 ps
T64 /workspace/coverage/cover_reg_top/15.uart_csr_rw.1575880781 Jun 09 12:36:05 PM PDT 24 Jun 09 12:36:06 PM PDT 24 16386669 ps
T86 /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.1249008548 Jun 09 12:36:00 PM PDT 24 Jun 09 12:36:02 PM PDT 24 90497900 ps
T1122 /workspace/coverage/cover_reg_top/8.uart_intr_test.1027879969 Jun 09 12:36:01 PM PDT 24 Jun 09 12:36:02 PM PDT 24 24192252 ps
T1123 /workspace/coverage/cover_reg_top/21.uart_intr_test.4254432174 Jun 09 12:35:58 PM PDT 24 Jun 09 12:36:00 PM PDT 24 108946363 ps
T87 /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.923122082 Jun 09 12:35:57 PM PDT 24 Jun 09 12:35:59 PM PDT 24 23947253 ps
T1124 /workspace/coverage/cover_reg_top/30.uart_intr_test.609248098 Jun 09 12:35:59 PM PDT 24 Jun 09 12:36:01 PM PDT 24 106578730 ps
T1125 /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.3152462587 Jun 09 12:35:48 PM PDT 24 Jun 09 12:35:50 PM PDT 24 84020481 ps
T1126 /workspace/coverage/cover_reg_top/46.uart_intr_test.2879319979 Jun 09 12:35:50 PM PDT 24 Jun 09 12:35:51 PM PDT 24 44763893 ps
T65 /workspace/coverage/cover_reg_top/9.uart_csr_rw.3704058515 Jun 09 12:35:50 PM PDT 24 Jun 09 12:35:51 PM PDT 24 49093597 ps
T1127 /workspace/coverage/cover_reg_top/16.uart_tl_errors.999080198 Jun 09 12:36:00 PM PDT 24 Jun 09 12:36:02 PM PDT 24 222337271 ps
T1128 /workspace/coverage/cover_reg_top/8.uart_csr_rw.1534745466 Jun 09 12:35:59 PM PDT 24 Jun 09 12:36:01 PM PDT 24 14921974 ps
T1129 /workspace/coverage/cover_reg_top/15.uart_tl_errors.3335974122 Jun 09 12:36:17 PM PDT 24 Jun 09 12:36:20 PM PDT 24 73556609 ps
T1130 /workspace/coverage/cover_reg_top/11.uart_tl_errors.3423309555 Jun 09 12:35:49 PM PDT 24 Jun 09 12:35:51 PM PDT 24 203027292 ps
T1131 /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.678448928 Jun 09 12:35:53 PM PDT 24 Jun 09 12:35:54 PM PDT 24 35881967 ps
T1132 /workspace/coverage/cover_reg_top/18.uart_tl_errors.1730932081 Jun 09 12:35:53 PM PDT 24 Jun 09 12:35:56 PM PDT 24 283962862 ps
T1133 /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.2220883088 Jun 09 12:35:57 PM PDT 24 Jun 09 12:36:00 PM PDT 24 102681081 ps
T1134 /workspace/coverage/cover_reg_top/2.uart_csr_rw.1099918258 Jun 09 12:35:48 PM PDT 24 Jun 09 12:35:49 PM PDT 24 41505498 ps
T1135 /workspace/coverage/cover_reg_top/27.uart_intr_test.4137048264 Jun 09 12:35:58 PM PDT 24 Jun 09 12:36:00 PM PDT 24 38067350 ps
T1136 /workspace/coverage/cover_reg_top/14.uart_tl_errors.126254468 Jun 09 12:35:48 PM PDT 24 Jun 09 12:35:50 PM PDT 24 241996314 ps
T1137 /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.894897505 Jun 09 12:35:55 PM PDT 24 Jun 09 12:35:56 PM PDT 24 24019567 ps
T1138 /workspace/coverage/cover_reg_top/17.uart_tl_errors.1509056798 Jun 09 12:35:49 PM PDT 24 Jun 09 12:35:52 PM PDT 24 115023806 ps
T1139 /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.2669772321 Jun 09 12:35:50 PM PDT 24 Jun 09 12:35:53 PM PDT 24 262559534 ps
T1140 /workspace/coverage/cover_reg_top/33.uart_intr_test.134269113 Jun 09 12:35:53 PM PDT 24 Jun 09 12:35:54 PM PDT 24 23666953 ps
T1141 /workspace/coverage/cover_reg_top/0.uart_tl_errors.4240073309 Jun 09 12:35:53 PM PDT 24 Jun 09 12:35:55 PM PDT 24 26660599 ps
T96 /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.2700899608 Jun 09 12:35:59 PM PDT 24 Jun 09 12:36:01 PM PDT 24 176605079 ps
T1142 /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.863342274 Jun 09 12:35:48 PM PDT 24 Jun 09 12:35:49 PM PDT 24 53893733 ps
T126 /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.2123034541 Jun 09 12:35:51 PM PDT 24 Jun 09 12:35:53 PM PDT 24 296018790 ps
T1143 /workspace/coverage/cover_reg_top/18.uart_csr_rw.329531859 Jun 09 12:35:49 PM PDT 24 Jun 09 12:35:50 PM PDT 24 53399915 ps
T1144 /workspace/coverage/cover_reg_top/10.uart_tl_errors.1795569046 Jun 09 12:35:55 PM PDT 24 Jun 09 12:35:57 PM PDT 24 110625924 ps
T1145 /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.2355136450 Jun 09 12:35:48 PM PDT 24 Jun 09 12:35:49 PM PDT 24 34336622 ps
T1146 /workspace/coverage/cover_reg_top/16.uart_csr_rw.403381876 Jun 09 12:35:47 PM PDT 24 Jun 09 12:35:48 PM PDT 24 21142065 ps
T1147 /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.2117850465 Jun 09 12:35:56 PM PDT 24 Jun 09 12:35:58 PM PDT 24 20144299 ps
T1148 /workspace/coverage/cover_reg_top/15.uart_intr_test.38626278 Jun 09 12:36:26 PM PDT 24 Jun 09 12:36:27 PM PDT 24 56047938 ps
T94 /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.1158138390 Jun 09 12:35:59 PM PDT 24 Jun 09 12:36:02 PM PDT 24 82767802 ps
T66 /workspace/coverage/cover_reg_top/12.uart_csr_rw.2910019022 Jun 09 12:35:47 PM PDT 24 Jun 09 12:35:48 PM PDT 24 14396300 ps
T1149 /workspace/coverage/cover_reg_top/1.uart_tl_errors.672871016 Jun 09 12:35:48 PM PDT 24 Jun 09 12:35:50 PM PDT 24 467565655 ps
T1150 /workspace/coverage/cover_reg_top/43.uart_intr_test.1713407703 Jun 09 12:35:59 PM PDT 24 Jun 09 12:36:01 PM PDT 24 47327442 ps
T1151 /workspace/coverage/cover_reg_top/14.uart_csr_rw.1418292689 Jun 09 12:35:56 PM PDT 24 Jun 09 12:35:57 PM PDT 24 15808477 ps
T1152 /workspace/coverage/cover_reg_top/14.uart_intr_test.220899367 Jun 09 12:35:53 PM PDT 24 Jun 09 12:35:54 PM PDT 24 21065318 ps
T1153 /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.359024802 Jun 09 12:35:56 PM PDT 24 Jun 09 12:35:58 PM PDT 24 269186357 ps
T1154 /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.3070231376 Jun 09 12:35:51 PM PDT 24 Jun 09 12:35:52 PM PDT 24 18021215 ps
T1155 /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.2136437213 Jun 09 12:36:00 PM PDT 24 Jun 09 12:36:02 PM PDT 24 64264475 ps
T1156 /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.1535090683 Jun 09 12:35:57 PM PDT 24 Jun 09 12:35:59 PM PDT 24 31819458 ps
T1157 /workspace/coverage/cover_reg_top/3.uart_csr_rw.3825398643 Jun 09 12:35:52 PM PDT 24 Jun 09 12:35:53 PM PDT 24 78969508 ps
T77 /workspace/coverage/cover_reg_top/1.uart_csr_rw.1561850208 Jun 09 12:35:51 PM PDT 24 Jun 09 12:35:53 PM PDT 24 25390673 ps
T1158 /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.2769485623 Jun 09 12:35:44 PM PDT 24 Jun 09 12:35:45 PM PDT 24 18964649 ps
T1159 /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.1777589470 Jun 09 12:35:51 PM PDT 24 Jun 09 12:35:53 PM PDT 24 52490125 ps
T1160 /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.629565948 Jun 09 12:35:56 PM PDT 24 Jun 09 12:35:58 PM PDT 24 114309148 ps
T1161 /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.2669468267 Jun 09 12:36:26 PM PDT 24 Jun 09 12:36:27 PM PDT 24 102596720 ps
T1162 /workspace/coverage/cover_reg_top/47.uart_intr_test.3781206958 Jun 09 12:35:49 PM PDT 24 Jun 09 12:35:50 PM PDT 24 65820225 ps
T1163 /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.1724098258 Jun 09 12:36:02 PM PDT 24 Jun 09 12:36:04 PM PDT 24 145190370 ps
T1164 /workspace/coverage/cover_reg_top/6.uart_csr_rw.1258152486 Jun 09 12:35:59 PM PDT 24 Jun 09 12:36:01 PM PDT 24 34456467 ps
T1165 /workspace/coverage/cover_reg_top/10.uart_intr_test.2967260448 Jun 09 12:35:58 PM PDT 24 Jun 09 12:36:00 PM PDT 24 19536223 ps
T1166 /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.3080474615 Jun 09 12:35:50 PM PDT 24 Jun 09 12:35:52 PM PDT 24 78231089 ps
T1167 /workspace/coverage/cover_reg_top/16.uart_intr_test.2416123021 Jun 09 12:35:50 PM PDT 24 Jun 09 12:35:52 PM PDT 24 48520387 ps
T1168 /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.3687898588 Jun 09 12:35:51 PM PDT 24 Jun 09 12:35:52 PM PDT 24 101431109 ps
T1169 /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.3560194259 Jun 09 12:35:50 PM PDT 24 Jun 09 12:35:51 PM PDT 24 20582072 ps
T1170 /workspace/coverage/cover_reg_top/10.uart_csr_rw.4206644607 Jun 09 12:35:54 PM PDT 24 Jun 09 12:35:55 PM PDT 24 45645424 ps
T1171 /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.3554023251 Jun 09 12:35:54 PM PDT 24 Jun 09 12:35:55 PM PDT 24 17891919 ps
T1172 /workspace/coverage/cover_reg_top/12.uart_tl_errors.3683801679 Jun 09 12:35:59 PM PDT 24 Jun 09 12:36:02 PM PDT 24 191610239 ps
T97 /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.3831490634 Jun 09 12:36:15 PM PDT 24 Jun 09 12:36:17 PM PDT 24 129336222 ps
T1173 /workspace/coverage/cover_reg_top/23.uart_intr_test.3575923625 Jun 09 12:35:50 PM PDT 24 Jun 09 12:35:51 PM PDT 24 11645529 ps
T1174 /workspace/coverage/cover_reg_top/49.uart_intr_test.460286604 Jun 09 12:35:56 PM PDT 24 Jun 09 12:35:58 PM PDT 24 14404082 ps
T1175 /workspace/coverage/cover_reg_top/4.uart_csr_rw.1403870770 Jun 09 12:35:47 PM PDT 24 Jun 09 12:35:48 PM PDT 24 12030890 ps
T1176 /workspace/coverage/cover_reg_top/41.uart_intr_test.2378482417 Jun 09 12:35:58 PM PDT 24 Jun 09 12:36:00 PM PDT 24 18508901 ps
T1177 /workspace/coverage/cover_reg_top/7.uart_intr_test.836434707 Jun 09 12:35:51 PM PDT 24 Jun 09 12:35:52 PM PDT 24 13835749 ps
T1178 /workspace/coverage/cover_reg_top/12.uart_intr_test.2535303137 Jun 09 12:35:45 PM PDT 24 Jun 09 12:35:46 PM PDT 24 25501677 ps
T1179 /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.1859130590 Jun 09 12:35:51 PM PDT 24 Jun 09 12:35:52 PM PDT 24 13882216 ps
T1180 /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.1576369449 Jun 09 12:35:49 PM PDT 24 Jun 09 12:35:50 PM PDT 24 19717562 ps
T1181 /workspace/coverage/cover_reg_top/1.uart_intr_test.648996834 Jun 09 12:35:58 PM PDT 24 Jun 09 12:36:01 PM PDT 24 49254848 ps
T1182 /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.2816305091 Jun 09 12:35:50 PM PDT 24 Jun 09 12:35:53 PM PDT 24 387741231 ps
T1183 /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.4222013637 Jun 09 12:35:52 PM PDT 24 Jun 09 12:35:53 PM PDT 24 41371890 ps
T1184 /workspace/coverage/cover_reg_top/35.uart_intr_test.1865945137 Jun 09 12:35:58 PM PDT 24 Jun 09 12:36:00 PM PDT 24 42451972 ps
T1185 /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.3952365944 Jun 09 12:35:51 PM PDT 24 Jun 09 12:35:53 PM PDT 24 147728958 ps
T1186 /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.1073615675 Jun 09 12:35:57 PM PDT 24 Jun 09 12:35:59 PM PDT 24 20415184 ps
T1187 /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.1380022410 Jun 09 12:36:10 PM PDT 24 Jun 09 12:36:11 PM PDT 24 70174616 ps
T1188 /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.834393744 Jun 09 12:35:47 PM PDT 24 Jun 09 12:35:48 PM PDT 24 14592744 ps
T1189 /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.1624871123 Jun 09 12:35:51 PM PDT 24 Jun 09 12:35:52 PM PDT 24 86298097 ps
T1190 /workspace/coverage/cover_reg_top/44.uart_intr_test.1541475618 Jun 09 12:35:58 PM PDT 24 Jun 09 12:36:00 PM PDT 24 23113931 ps
T1191 /workspace/coverage/cover_reg_top/9.uart_tl_errors.2104280016 Jun 09 12:35:47 PM PDT 24 Jun 09 12:35:49 PM PDT 24 36495050 ps
T1192 /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.2167419570 Jun 09 12:35:57 PM PDT 24 Jun 09 12:36:09 PM PDT 24 120869196 ps
T1193 /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.4256999812 Jun 09 12:35:49 PM PDT 24 Jun 09 12:35:51 PM PDT 24 84309396 ps
T1194 /workspace/coverage/cover_reg_top/8.uart_tl_errors.211917005 Jun 09 12:35:50 PM PDT 24 Jun 09 12:35:53 PM PDT 24 59479189 ps
T1195 /workspace/coverage/cover_reg_top/11.uart_intr_test.152107417 Jun 09 12:35:51 PM PDT 24 Jun 09 12:35:52 PM PDT 24 15386615 ps
T1196 /workspace/coverage/cover_reg_top/13.uart_intr_test.3534119314 Jun 09 12:35:51 PM PDT 24 Jun 09 12:35:52 PM PDT 24 14882266 ps
T1197 /workspace/coverage/cover_reg_top/22.uart_intr_test.1131545643 Jun 09 12:35:57 PM PDT 24 Jun 09 12:35:59 PM PDT 24 47000893 ps
T78 /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.859297405 Jun 09 12:35:49 PM PDT 24 Jun 09 12:35:51 PM PDT 24 26230824 ps
T1198 /workspace/coverage/cover_reg_top/6.uart_tl_errors.1820146954 Jun 09 12:35:49 PM PDT 24 Jun 09 12:35:51 PM PDT 24 49600263 ps
T1199 /workspace/coverage/cover_reg_top/17.uart_csr_rw.1154094603 Jun 09 12:35:59 PM PDT 24 Jun 09 12:36:01 PM PDT 24 14856187 ps
T1200 /workspace/coverage/cover_reg_top/19.uart_intr_test.3407887501 Jun 09 12:35:49 PM PDT 24 Jun 09 12:35:50 PM PDT 24 13951307 ps
T95 /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.166067717 Jun 09 12:35:46 PM PDT 24 Jun 09 12:35:48 PM PDT 24 154937365 ps
T1201 /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.2801842135 Jun 09 12:35:59 PM PDT 24 Jun 09 12:36:01 PM PDT 24 61594912 ps
T1202 /workspace/coverage/cover_reg_top/39.uart_intr_test.2028173453 Jun 09 12:36:25 PM PDT 24 Jun 09 12:36:26 PM PDT 24 14405508 ps
T67 /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.3039785676 Jun 09 12:35:48 PM PDT 24 Jun 09 12:35:49 PM PDT 24 26294561 ps
T1203 /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.327361876 Jun 09 12:35:47 PM PDT 24 Jun 09 12:35:49 PM PDT 24 45577315 ps
T1204 /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.4162793738 Jun 09 12:36:00 PM PDT 24 Jun 09 12:36:02 PM PDT 24 140980329 ps
T1205 /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.2554679257 Jun 09 12:35:52 PM PDT 24 Jun 09 12:35:53 PM PDT 24 37668196 ps
T1206 /workspace/coverage/cover_reg_top/9.uart_intr_test.100843402 Jun 09 12:35:56 PM PDT 24 Jun 09 12:35:58 PM PDT 24 45339495 ps
T1207 /workspace/coverage/cover_reg_top/0.uart_csr_rw.3195053096 Jun 09 12:35:46 PM PDT 24 Jun 09 12:35:47 PM PDT 24 38576542 ps
T1208 /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.2558510982 Jun 09 12:35:50 PM PDT 24 Jun 09 12:35:51 PM PDT 24 35161201 ps
T1209 /workspace/coverage/cover_reg_top/2.uart_intr_test.1254177398 Jun 09 12:35:49 PM PDT 24 Jun 09 12:35:51 PM PDT 24 29292625 ps
T1210 /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.2408999239 Jun 09 12:35:59 PM PDT 24 Jun 09 12:36:01 PM PDT 24 87269435 ps
T1211 /workspace/coverage/cover_reg_top/5.uart_intr_test.2274561515 Jun 09 12:35:51 PM PDT 24 Jun 09 12:35:52 PM PDT 24 34430848 ps
T1212 /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.1593970131 Jun 09 12:35:52 PM PDT 24 Jun 09 12:35:55 PM PDT 24 1037852277 ps
T1213 /workspace/coverage/cover_reg_top/34.uart_intr_test.3496912135 Jun 09 12:35:56 PM PDT 24 Jun 09 12:35:58 PM PDT 24 41805391 ps
T1214 /workspace/coverage/cover_reg_top/17.uart_intr_test.2363115899 Jun 09 12:35:57 PM PDT 24 Jun 09 12:36:00 PM PDT 24 25440551 ps
T1215 /workspace/coverage/cover_reg_top/3.uart_tl_errors.823241593 Jun 09 12:36:00 PM PDT 24 Jun 09 12:36:02 PM PDT 24 102257009 ps
T1216 /workspace/coverage/cover_reg_top/24.uart_intr_test.2718292734 Jun 09 12:35:59 PM PDT 24 Jun 09 12:36:01 PM PDT 24 18804338 ps
T1217 /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.2017074778 Jun 09 12:35:58 PM PDT 24 Jun 09 12:36:00 PM PDT 24 50938749 ps
T1218 /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.860564193 Jun 09 12:35:54 PM PDT 24 Jun 09 12:35:55 PM PDT 24 20452314 ps
T1219 /workspace/coverage/cover_reg_top/28.uart_intr_test.1364989093 Jun 09 12:36:04 PM PDT 24 Jun 09 12:36:05 PM PDT 24 93278286 ps
T1220 /workspace/coverage/cover_reg_top/3.uart_intr_test.2693136595 Jun 09 12:35:58 PM PDT 24 Jun 09 12:36:00 PM PDT 24 22483969 ps
T1221 /workspace/coverage/cover_reg_top/31.uart_intr_test.3800653199 Jun 09 12:35:58 PM PDT 24 Jun 09 12:36:00 PM PDT 24 11017858 ps
T1222 /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.1990930625 Jun 09 12:35:45 PM PDT 24 Jun 09 12:35:51 PM PDT 24 21432309 ps

Test location /workspace/coverage/default/43.uart_stress_all_with_rand_reset.2655796234
Short name T8
Test name
Test status
Simulation time 126363899671 ps
CPU time 477.1 seconds
Started Jun 09 02:18:31 PM PDT 24
Finished Jun 09 02:26:29 PM PDT 24
Peak memory 216032 kb
Host smart-8ab23bea-3839-4549-9e29-31c325ce17a5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655796234 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 43.uart_stress_all_with_rand_reset.2655796234
Directory /workspace/43.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/74.uart_stress_all_with_rand_reset.799764755
Short name T16
Test name
Test status
Simulation time 396761992843 ps
CPU time 915.48 seconds
Started Jun 09 02:19:32 PM PDT 24
Finished Jun 09 02:34:48 PM PDT 24
Peak memory 226896 kb
Host smart-19529dff-c1af-4472-8771-9563030a2f11
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799764755 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 74.uart_stress_all_with_rand_reset.799764755
Directory /workspace/74.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.uart_long_xfer_wo_dly.4040335868
Short name T45
Test name
Test status
Simulation time 142935268910 ps
CPU time 573.19 seconds
Started Jun 09 02:12:52 PM PDT 24
Finished Jun 09 02:22:25 PM PDT 24
Peak memory 200324 kb
Host smart-a67a780b-0e8a-4c85-a476-fbdaea6bf0c5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4040335868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.4040335868
Directory /workspace/0.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/30.uart_stress_all.1004793098
Short name T7
Test name
Test status
Simulation time 364565811349 ps
CPU time 579.03 seconds
Started Jun 09 02:17:02 PM PDT 24
Finished Jun 09 02:26:42 PM PDT 24
Peak memory 200352 kb
Host smart-6d20f9cf-0ae7-4212-8a3f-14197f10bbed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004793098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.1004793098
Directory /workspace/30.uart_stress_all/latest

Test location /workspace/coverage/default/40.uart_stress_all_with_rand_reset.3060573543
Short name T46
Test name
Test status
Simulation time 107091757884 ps
CPU time 489.93 seconds
Started Jun 09 02:18:15 PM PDT 24
Finished Jun 09 02:26:26 PM PDT 24
Peak memory 216880 kb
Host smart-1e311864-ca2a-4341-bc69-0d48f46ceb9f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060573543 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 40.uart_stress_all_with_rand_reset.3060573543
Directory /workspace/40.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.uart_stress_all_with_rand_reset.4075823350
Short name T13
Test name
Test status
Simulation time 222247661024 ps
CPU time 173.56 seconds
Started Jun 09 02:16:35 PM PDT 24
Finished Jun 09 02:19:29 PM PDT 24
Peak memory 216852 kb
Host smart-382fecbc-6f0b-4113-9c97-4c48e517182c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075823350 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 25.uart_stress_all_with_rand_reset.4075823350
Directory /workspace/25.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.uart_long_xfer_wo_dly.2337706092
Short name T260
Test name
Test status
Simulation time 110016710787 ps
CPU time 372.04 seconds
Started Jun 09 02:16:51 PM PDT 24
Finished Jun 09 02:23:04 PM PDT 24
Peak memory 200400 kb
Host smart-1ef4c500-70b5-4cce-b7bc-e073981da299
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2337706092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.2337706092
Directory /workspace/28.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/1.uart_sec_cm.1808559399
Short name T4
Test name
Test status
Simulation time 302830159 ps
CPU time 0.79 seconds
Started Jun 09 02:12:59 PM PDT 24
Finished Jun 09 02:13:00 PM PDT 24
Peak memory 218860 kb
Host smart-7eafcba0-f8c3-4960-a587-4627fa5a1f57
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808559399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.1808559399
Directory /workspace/1.uart_sec_cm/latest

Test location /workspace/coverage/default/1.uart_stress_all.3670648310
Short name T129
Test name
Test status
Simulation time 298423280313 ps
CPU time 309.76 seconds
Started Jun 09 02:13:06 PM PDT 24
Finished Jun 09 02:18:16 PM PDT 24
Peak memory 200376 kb
Host smart-9b84cf92-73f7-417b-983b-295e2ce70ba4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670648310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.3670648310
Directory /workspace/1.uart_stress_all/latest

Test location /workspace/coverage/default/18.uart_rx_parity_err.623015453
Short name T131
Test name
Test status
Simulation time 119319847283 ps
CPU time 130.59 seconds
Started Jun 09 02:15:39 PM PDT 24
Finished Jun 09 02:17:50 PM PDT 24
Peak memory 200320 kb
Host smart-5fd08109-03aa-4f16-a973-1d812769ed5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623015453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.623015453
Directory /workspace/18.uart_rx_parity_err/latest

Test location /workspace/coverage/default/39.uart_fifo_full.2184709830
Short name T106
Test name
Test status
Simulation time 159656902430 ps
CPU time 449.5 seconds
Started Jun 09 02:18:05 PM PDT 24
Finished Jun 09 02:25:35 PM PDT 24
Peak memory 200396 kb
Host smart-76f2960c-1463-483b-a25b-35c524303165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184709830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.2184709830
Directory /workspace/39.uart_fifo_full/latest

Test location /workspace/coverage/default/10.uart_stress_all.3457067301
Short name T176
Test name
Test status
Simulation time 490691707288 ps
CPU time 1149.41 seconds
Started Jun 09 02:14:30 PM PDT 24
Finished Jun 09 02:33:40 PM PDT 24
Peak memory 200320 kb
Host smart-59eeb5eb-99b5-4fbc-bc23-13521f80f4c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457067301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.3457067301
Directory /workspace/10.uart_stress_all/latest

Test location /workspace/coverage/default/197.uart_fifo_reset.2722858091
Short name T293
Test name
Test status
Simulation time 101765732742 ps
CPU time 73.35 seconds
Started Jun 09 02:20:48 PM PDT 24
Finished Jun 09 02:22:02 PM PDT 24
Peak memory 200364 kb
Host smart-d0ff18db-cb70-4ac8-884f-35965edbbdad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722858091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.2722858091
Directory /workspace/197.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_stress_all_with_rand_reset.2789074143
Short name T156
Test name
Test status
Simulation time 349222390330 ps
CPU time 1193.29 seconds
Started Jun 09 02:15:01 PM PDT 24
Finished Jun 09 02:34:55 PM PDT 24
Peak memory 225176 kb
Host smart-ddeeda41-f3e7-4872-bcff-e7a8734d380b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789074143 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 13.uart_stress_all_with_rand_reset.2789074143
Directory /workspace/13.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.uart_stress_all_with_rand_reset.2861532170
Short name T100
Test name
Test status
Simulation time 283773733767 ps
CPU time 1015.96 seconds
Started Jun 09 02:17:55 PM PDT 24
Finished Jun 09 02:34:51 PM PDT 24
Peak memory 225184 kb
Host smart-3b463d2c-90f8-457f-9fb6-4371eac42af2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861532170 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 37.uart_stress_all_with_rand_reset.2861532170
Directory /workspace/37.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.uart_stress_all_with_rand_reset.1710385717
Short name T34
Test name
Test status
Simulation time 122421440888 ps
CPU time 434.12 seconds
Started Jun 09 02:16:43 PM PDT 24
Finished Jun 09 02:23:57 PM PDT 24
Peak memory 216884 kb
Host smart-0e07810f-e08a-421b-b831-a5c4b62edfcf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710385717 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 27.uart_stress_all_with_rand_reset.1710385717
Directory /workspace/27.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.1917402894
Short name T90
Test name
Test status
Simulation time 90068674 ps
CPU time 1.36 seconds
Started Jun 09 12:35:56 PM PDT 24
Finished Jun 09 12:35:58 PM PDT 24
Peak memory 200072 kb
Host smart-399b8d95-6c7d-4685-a5ea-e7b5633edc99
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917402894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.1917402894
Directory /workspace/11.uart_tl_intg_err/latest

Test location /workspace/coverage/default/198.uart_fifo_reset.1135389632
Short name T216
Test name
Test status
Simulation time 63005378388 ps
CPU time 37.6 seconds
Started Jun 09 02:20:45 PM PDT 24
Finished Jun 09 02:21:23 PM PDT 24
Peak memory 200304 kb
Host smart-0f24dcf3-6e20-4a08-88ec-8c3190407e94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135389632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.1135389632
Directory /workspace/198.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_alert_test.2342511885
Short name T51
Test name
Test status
Simulation time 15570708 ps
CPU time 0.56 seconds
Started Jun 09 02:12:51 PM PDT 24
Finished Jun 09 02:12:51 PM PDT 24
Peak memory 195240 kb
Host smart-6f5fbae5-5e05-44ed-bf3c-deaaf5f90f5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342511885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.2342511885
Directory /workspace/0.uart_alert_test/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_rw.4049923358
Short name T62
Test name
Test status
Simulation time 48753158 ps
CPU time 0.63 seconds
Started Jun 09 12:35:57 PM PDT 24
Finished Jun 09 12:35:59 PM PDT 24
Peak memory 196100 kb
Host smart-1ae6450c-c546-4184-aee7-73b415708da2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049923358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.4049923358
Directory /workspace/13.uart_csr_rw/latest

Test location /workspace/coverage/default/20.uart_stress_all.1312876856
Short name T141
Test name
Test status
Simulation time 252489673466 ps
CPU time 195.09 seconds
Started Jun 09 02:16:00 PM PDT 24
Finished Jun 09 02:19:15 PM PDT 24
Peak memory 200336 kb
Host smart-a83e58fd-81f5-44ed-b438-57b5bdd3aa7a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312876856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.1312876856
Directory /workspace/20.uart_stress_all/latest

Test location /workspace/coverage/default/50.uart_stress_all_with_rand_reset.1525748339
Short name T199
Test name
Test status
Simulation time 598562154674 ps
CPU time 1282.85 seconds
Started Jun 09 02:19:16 PM PDT 24
Finished Jun 09 02:40:39 PM PDT 24
Peak memory 225040 kb
Host smart-ee0ac3e7-73c2-435c-9cff-30d8e66fdf52
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525748339 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 50.uart_stress_all_with_rand_reset.1525748339
Directory /workspace/50.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/78.uart_stress_all_with_rand_reset.2437705538
Short name T56
Test name
Test status
Simulation time 365267001996 ps
CPU time 973.55 seconds
Started Jun 09 02:19:37 PM PDT 24
Finished Jun 09 02:35:51 PM PDT 24
Peak memory 225116 kb
Host smart-f34fca16-4a78-45ee-9ceb-a43157606c9a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437705538 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 78.uart_stress_all_with_rand_reset.2437705538
Directory /workspace/78.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/237.uart_fifo_reset.1036684524
Short name T133
Test name
Test status
Simulation time 70563362114 ps
CPU time 55.09 seconds
Started Jun 09 02:21:00 PM PDT 24
Finished Jun 09 02:21:56 PM PDT 24
Peak memory 200368 kb
Host smart-5d0a60b0-ded9-4786-95d4-ebd5750c5943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036684524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.1036684524
Directory /workspace/237.uart_fifo_reset/latest

Test location /workspace/coverage/default/38.uart_stress_all.3165727729
Short name T117
Test name
Test status
Simulation time 176200793368 ps
CPU time 178.64 seconds
Started Jun 09 02:18:00 PM PDT 24
Finished Jun 09 02:20:59 PM PDT 24
Peak memory 200384 kb
Host smart-291ff0b2-5057-4db1-9dd5-d3e8a5cdc2f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165727729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.3165727729
Directory /workspace/38.uart_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.3156005252
Short name T82
Test name
Test status
Simulation time 49899144 ps
CPU time 0.66 seconds
Started Jun 09 12:35:57 PM PDT 24
Finished Jun 09 12:35:59 PM PDT 24
Peak memory 195464 kb
Host smart-47b915f0-516f-40bd-997e-33541c52ab2e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156005252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr
_outstanding.3156005252
Directory /workspace/1.uart_same_csr_outstanding/latest

Test location /workspace/coverage/default/12.uart_fifo_overflow.3891504905
Short name T146
Test name
Test status
Simulation time 55016836265 ps
CPU time 46.22 seconds
Started Jun 09 02:14:45 PM PDT 24
Finished Jun 09 02:15:32 PM PDT 24
Peak memory 200380 kb
Host smart-e3166204-edb5-4cc3-9bca-e024458118a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891504905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.3891504905
Directory /workspace/12.uart_fifo_overflow/latest

Test location /workspace/coverage/default/42.uart_stress_all_with_rand_reset.2701990647
Short name T209
Test name
Test status
Simulation time 99231463620 ps
CPU time 1050.39 seconds
Started Jun 09 02:18:26 PM PDT 24
Finished Jun 09 02:35:57 PM PDT 24
Peak memory 216900 kb
Host smart-28280e28-d5bf-4335-97dd-974655043549
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701990647 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 42.uart_stress_all_with_rand_reset.2701990647
Directory /workspace/42.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.166067717
Short name T95
Test name
Test status
Simulation time 154937365 ps
CPU time 1.3 seconds
Started Jun 09 12:35:46 PM PDT 24
Finished Jun 09 12:35:48 PM PDT 24
Peak memory 200016 kb
Host smart-30165660-f4e5-4ef1-b6c5-7648c5fd214d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166067717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.166067717
Directory /workspace/1.uart_tl_intg_err/latest

Test location /workspace/coverage/default/5.uart_fifo_overflow.4201716028
Short name T130
Test name
Test status
Simulation time 123637474497 ps
CPU time 63.03 seconds
Started Jun 09 02:13:40 PM PDT 24
Finished Jun 09 02:14:43 PM PDT 24
Peak memory 200296 kb
Host smart-8e6e204e-001d-4458-9f1c-975c7176178f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201716028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.4201716028
Directory /workspace/5.uart_fifo_overflow/latest

Test location /workspace/coverage/default/44.uart_stress_all.3026173699
Short name T111
Test name
Test status
Simulation time 216695873175 ps
CPU time 100.14 seconds
Started Jun 09 02:18:46 PM PDT 24
Finished Jun 09 02:20:27 PM PDT 24
Peak memory 200384 kb
Host smart-86218c90-57cf-4bcc-8de7-2d62c7c1df7d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026173699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.3026173699
Directory /workspace/44.uart_stress_all/latest

Test location /workspace/coverage/default/0.uart_stress_all.1877069883
Short name T460
Test name
Test status
Simulation time 989002669863 ps
CPU time 135.28 seconds
Started Jun 09 02:12:52 PM PDT 24
Finished Jun 09 02:15:07 PM PDT 24
Peak memory 200300 kb
Host smart-4245ab46-2e39-4d5d-8cc5-6f03d1e20c84
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877069883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.1877069883
Directory /workspace/0.uart_stress_all/latest

Test location /workspace/coverage/default/164.uart_fifo_reset.1628643994
Short name T190
Test name
Test status
Simulation time 200915967069 ps
CPU time 117.88 seconds
Started Jun 09 02:20:29 PM PDT 24
Finished Jun 09 02:22:27 PM PDT 24
Peak memory 200328 kb
Host smart-fd558004-e1ea-48a0-a9f3-46a612e69def
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628643994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.1628643994
Directory /workspace/164.uart_fifo_reset/latest

Test location /workspace/coverage/default/1.uart_perf.24022018
Short name T298
Test name
Test status
Simulation time 18115128832 ps
CPU time 588.06 seconds
Started Jun 09 02:13:04 PM PDT 24
Finished Jun 09 02:22:52 PM PDT 24
Peak memory 200408 kb
Host smart-fa716bde-208e-4388-aa24-86b742fbd29f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=24022018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.24022018
Directory /workspace/1.uart_perf/latest

Test location /workspace/coverage/default/130.uart_fifo_reset.3922776382
Short name T114
Test name
Test status
Simulation time 341527600809 ps
CPU time 110.45 seconds
Started Jun 09 02:20:11 PM PDT 24
Finished Jun 09 02:22:02 PM PDT 24
Peak memory 200292 kb
Host smart-e20a7450-78f6-4ebb-8979-fa0d24bfdf39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922776382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.3922776382
Directory /workspace/130.uart_fifo_reset/latest

Test location /workspace/coverage/default/42.uart_stress_all.1786375189
Short name T143
Test name
Test status
Simulation time 28051919197 ps
CPU time 67.66 seconds
Started Jun 09 02:18:27 PM PDT 24
Finished Jun 09 02:19:35 PM PDT 24
Peak memory 200320 kb
Host smart-0a86ceb1-d0e6-4001-a748-104dbff6843a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786375189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.1786375189
Directory /workspace/42.uart_stress_all/latest

Test location /workspace/coverage/default/178.uart_fifo_reset.1571345578
Short name T174
Test name
Test status
Simulation time 48183736611 ps
CPU time 41.99 seconds
Started Jun 09 02:20:37 PM PDT 24
Finished Jun 09 02:21:19 PM PDT 24
Peak memory 200332 kb
Host smart-ad7a25e6-1fa6-415f-b7b0-42138e97ee23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571345578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.1571345578
Directory /workspace/178.uart_fifo_reset/latest

Test location /workspace/coverage/default/283.uart_fifo_reset.4080186141
Short name T314
Test name
Test status
Simulation time 267846786081 ps
CPU time 48.58 seconds
Started Jun 09 02:21:22 PM PDT 24
Finished Jun 09 02:22:11 PM PDT 24
Peak memory 200316 kb
Host smart-aebbd2bc-2944-4715-8da1-a8cb0473f262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080186141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.4080186141
Directory /workspace/283.uart_fifo_reset/latest

Test location /workspace/coverage/default/293.uart_fifo_reset.3228790756
Short name T308
Test name
Test status
Simulation time 187593509760 ps
CPU time 24.66 seconds
Started Jun 09 02:21:28 PM PDT 24
Finished Jun 09 02:21:53 PM PDT 24
Peak memory 200364 kb
Host smart-7bc6789b-bc9b-4bba-b16c-fa0ac3eeaa23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228790756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.3228790756
Directory /workspace/293.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_fifo_reset.444943709
Short name T244
Test name
Test status
Simulation time 56599526670 ps
CPU time 22.43 seconds
Started Jun 09 02:12:42 PM PDT 24
Finished Jun 09 02:13:05 PM PDT 24
Peak memory 200308 kb
Host smart-6795db6d-7323-4cca-ad7c-e491ba4c2cfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444943709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.444943709
Directory /workspace/0.uart_fifo_reset/latest

Test location /workspace/coverage/default/108.uart_fifo_reset.1811126872
Short name T253
Test name
Test status
Simulation time 91067088609 ps
CPU time 82.02 seconds
Started Jun 09 02:19:54 PM PDT 24
Finished Jun 09 02:21:17 PM PDT 24
Peak memory 200592 kb
Host smart-9968081d-7d46-4da8-aaf2-4e87e8db79bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811126872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.1811126872
Directory /workspace/108.uart_fifo_reset/latest

Test location /workspace/coverage/default/143.uart_fifo_reset.3959266035
Short name T167
Test name
Test status
Simulation time 15375503634 ps
CPU time 27.31 seconds
Started Jun 09 02:20:15 PM PDT 24
Finished Jun 09 02:20:42 PM PDT 24
Peak memory 200376 kb
Host smart-b62ae9b7-cd46-4166-ab78-2442214cbedc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959266035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.3959266035
Directory /workspace/143.uart_fifo_reset/latest

Test location /workspace/coverage/default/10.uart_fifo_full.308305183
Short name T76
Test name
Test status
Simulation time 60588484354 ps
CPU time 28.49 seconds
Started Jun 09 02:14:24 PM PDT 24
Finished Jun 09 02:14:52 PM PDT 24
Peak memory 200356 kb
Host smart-3be33d31-011f-4573-92dd-1fd94e7c0d82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308305183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.308305183
Directory /workspace/10.uart_fifo_full/latest

Test location /workspace/coverage/default/13.uart_intr.2404112752
Short name T17
Test name
Test status
Simulation time 291718276131 ps
CPU time 114.43 seconds
Started Jun 09 02:14:56 PM PDT 24
Finished Jun 09 02:16:51 PM PDT 24
Peak memory 197608 kb
Host smart-97c1bdcc-82a9-4a95-98bd-356cfe6a01a3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404112752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.2404112752
Directory /workspace/13.uart_intr/latest

Test location /workspace/coverage/default/259.uart_fifo_reset.2647456889
Short name T188
Test name
Test status
Simulation time 39461200501 ps
CPU time 34.3 seconds
Started Jun 09 02:21:08 PM PDT 24
Finished Jun 09 02:21:43 PM PDT 24
Peak memory 200140 kb
Host smart-57289cbd-4fed-4d75-ac87-e01eb341c638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647456889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.2647456889
Directory /workspace/259.uart_fifo_reset/latest

Test location /workspace/coverage/default/48.uart_fifo_reset.644295887
Short name T202
Test name
Test status
Simulation time 47856523786 ps
CPU time 36.61 seconds
Started Jun 09 02:18:58 PM PDT 24
Finished Jun 09 02:19:34 PM PDT 24
Peak memory 200384 kb
Host smart-2d30a6d4-0920-4fcc-8d1d-686dd421d0f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644295887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.644295887
Directory /workspace/48.uart_fifo_reset/latest

Test location /workspace/coverage/default/54.uart_stress_all_with_rand_reset.8720252
Short name T322
Test name
Test status
Simulation time 106861343984 ps
CPU time 175.73 seconds
Started Jun 09 02:19:23 PM PDT 24
Finished Jun 09 02:22:19 PM PDT 24
Peak memory 216884 kb
Host smart-b544b56a-da12-4b00-9edf-5960e3f8e726
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8720252 -assert nopostproc
+UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 54.uart_stress_all_with_rand_reset.8720252
Directory /workspace/54.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/103.uart_fifo_reset.2491653097
Short name T198
Test name
Test status
Simulation time 17281678944 ps
CPU time 28.59 seconds
Started Jun 09 02:19:55 PM PDT 24
Finished Jun 09 02:20:24 PM PDT 24
Peak memory 200344 kb
Host smart-217f5c5d-359c-40b3-ac05-c3657cc0d4bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491653097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.2491653097
Directory /workspace/103.uart_fifo_reset/latest

Test location /workspace/coverage/default/109.uart_fifo_reset.124107252
Short name T201
Test name
Test status
Simulation time 22119378779 ps
CPU time 32.68 seconds
Started Jun 09 02:19:56 PM PDT 24
Finished Jun 09 02:20:29 PM PDT 24
Peak memory 200372 kb
Host smart-b5b3eed2-3d37-45fb-9fdc-93a6a02e5920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124107252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.124107252
Directory /workspace/109.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_rx_parity_err.400254446
Short name T136
Test name
Test status
Simulation time 127308895115 ps
CPU time 122.59 seconds
Started Jun 09 02:14:39 PM PDT 24
Finished Jun 09 02:16:42 PM PDT 24
Peak memory 200380 kb
Host smart-33dd3d76-ec40-4d42-ad22-fcc563cdbd16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400254446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.400254446
Directory /workspace/11.uart_rx_parity_err/latest

Test location /workspace/coverage/default/14.uart_stress_all_with_rand_reset.3048687860
Short name T326
Test name
Test status
Simulation time 52915517810 ps
CPU time 167.21 seconds
Started Jun 09 02:15:09 PM PDT 24
Finished Jun 09 02:17:57 PM PDT 24
Peak memory 216656 kb
Host smart-8cbb8504-d0c4-4198-9845-0b9552708986
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048687860 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 14.uart_stress_all_with_rand_reset.3048687860
Directory /workspace/14.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.uart_fifo_reset.314032887
Short name T222
Test name
Test status
Simulation time 47766197831 ps
CPU time 42.44 seconds
Started Jun 09 02:20:36 PM PDT 24
Finished Jun 09 02:21:18 PM PDT 24
Peak memory 200348 kb
Host smart-03844ba2-39e2-4034-9d9b-41172104f7eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314032887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.314032887
Directory /workspace/170.uart_fifo_reset/latest

Test location /workspace/coverage/default/40.uart_fifo_full.801799511
Short name T164
Test name
Test status
Simulation time 37181450937 ps
CPU time 28.9 seconds
Started Jun 09 02:18:05 PM PDT 24
Finished Jun 09 02:18:34 PM PDT 24
Peak memory 200308 kb
Host smart-c07ff175-1d34-4f4f-b214-deb54952fa35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801799511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.801799511
Directory /workspace/40.uart_fifo_full/latest

Test location /workspace/coverage/default/43.uart_fifo_reset.3566269982
Short name T338
Test name
Test status
Simulation time 15493470961 ps
CPU time 17.48 seconds
Started Jun 09 02:18:27 PM PDT 24
Finished Jun 09 02:18:44 PM PDT 24
Peak memory 200308 kb
Host smart-bf3d8e28-cfc6-4167-bbaa-b23e8e10ac62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566269982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.3566269982
Directory /workspace/43.uart_fifo_reset/latest

Test location /workspace/coverage/default/60.uart_fifo_reset.3270060504
Short name T242
Test name
Test status
Simulation time 70176046372 ps
CPU time 13.78 seconds
Started Jun 09 02:19:21 PM PDT 24
Finished Jun 09 02:19:35 PM PDT 24
Peak memory 200360 kb
Host smart-41a9e591-1350-47b3-ab46-168901439bc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270060504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.3270060504
Directory /workspace/60.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.2700899608
Short name T96
Test name
Test status
Simulation time 176605079 ps
CPU time 1.26 seconds
Started Jun 09 12:35:59 PM PDT 24
Finished Jun 09 12:36:01 PM PDT 24
Peak memory 199732 kb
Host smart-8e8460ff-30c7-44b2-a4ec-ed3fdddee31b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700899608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.2700899608
Directory /workspace/16.uart_tl_intg_err/latest

Test location /workspace/coverage/default/1.uart_fifo_reset.3558447807
Short name T227
Test name
Test status
Simulation time 100086855457 ps
CPU time 158.72 seconds
Started Jun 09 02:12:55 PM PDT 24
Finished Jun 09 02:15:34 PM PDT 24
Peak memory 200340 kb
Host smart-31b5fa63-53db-4852-8d4e-6a17404a8ab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558447807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.3558447807
Directory /workspace/1.uart_fifo_reset/latest

Test location /workspace/coverage/default/10.uart_fifo_reset.2985645514
Short name T223
Test name
Test status
Simulation time 158104431410 ps
CPU time 29.91 seconds
Started Jun 09 02:14:26 PM PDT 24
Finished Jun 09 02:14:56 PM PDT 24
Peak memory 200316 kb
Host smart-bf478db8-7ded-45b2-914a-3207269a3ee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985645514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.2985645514
Directory /workspace/10.uart_fifo_reset/latest

Test location /workspace/coverage/default/119.uart_fifo_reset.2721629334
Short name T128
Test name
Test status
Simulation time 56814824248 ps
CPU time 99.69 seconds
Started Jun 09 02:20:08 PM PDT 24
Finished Jun 09 02:21:48 PM PDT 24
Peak memory 200416 kb
Host smart-d7ea4a52-acf5-4578-a3d4-500a87898809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721629334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.2721629334
Directory /workspace/119.uart_fifo_reset/latest

Test location /workspace/coverage/default/128.uart_fifo_reset.878495170
Short name T233
Test name
Test status
Simulation time 15098456723 ps
CPU time 16.78 seconds
Started Jun 09 02:20:10 PM PDT 24
Finished Jun 09 02:20:27 PM PDT 24
Peak memory 200368 kb
Host smart-6b9f5b1b-08dd-4a2c-9b36-ad9e2cd67654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878495170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.878495170
Directory /workspace/128.uart_fifo_reset/latest

Test location /workspace/coverage/default/129.uart_fifo_reset.2628993637
Short name T154
Test name
Test status
Simulation time 73793615003 ps
CPU time 108.1 seconds
Started Jun 09 02:20:11 PM PDT 24
Finished Jun 09 02:21:59 PM PDT 24
Peak memory 200000 kb
Host smart-75af5ffa-b919-4803-92f3-ea3d7a4b12c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628993637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.2628993637
Directory /workspace/129.uart_fifo_reset/latest

Test location /workspace/coverage/default/131.uart_fifo_reset.455919686
Short name T665
Test name
Test status
Simulation time 21220048226 ps
CPU time 33.32 seconds
Started Jun 09 02:20:10 PM PDT 24
Finished Jun 09 02:20:44 PM PDT 24
Peak memory 200344 kb
Host smart-fb567c7d-c939-40d1-9a19-a1c11e9aff04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455919686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.455919686
Directory /workspace/131.uart_fifo_reset/latest

Test location /workspace/coverage/default/134.uart_fifo_reset.3084666442
Short name T213
Test name
Test status
Simulation time 107277570450 ps
CPU time 170.07 seconds
Started Jun 09 02:20:12 PM PDT 24
Finished Jun 09 02:23:03 PM PDT 24
Peak memory 200308 kb
Host smart-d047bb1c-2a0d-4575-9ec4-c925e7cbc58f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084666442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.3084666442
Directory /workspace/134.uart_fifo_reset/latest

Test location /workspace/coverage/default/135.uart_fifo_reset.809611347
Short name T232
Test name
Test status
Simulation time 103992235923 ps
CPU time 326.36 seconds
Started Jun 09 02:20:14 PM PDT 24
Finished Jun 09 02:25:41 PM PDT 24
Peak memory 200368 kb
Host smart-53513cd5-29d1-4305-bce7-a19052fcec68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809611347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.809611347
Directory /workspace/135.uart_fifo_reset/latest

Test location /workspace/coverage/default/139.uart_fifo_reset.396273776
Short name T340
Test name
Test status
Simulation time 83993873192 ps
CPU time 33.33 seconds
Started Jun 09 02:20:16 PM PDT 24
Finished Jun 09 02:20:50 PM PDT 24
Peak memory 200332 kb
Host smart-edcdef4c-3e9b-4da2-91d4-fb592f95d4a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396273776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.396273776
Directory /workspace/139.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_stress_all_with_rand_reset.1018475276
Short name T36
Test name
Test status
Simulation time 19611109095 ps
CPU time 326.06 seconds
Started Jun 09 02:15:21 PM PDT 24
Finished Jun 09 02:20:47 PM PDT 24
Peak memory 208768 kb
Host smart-6ef6b832-6175-49f8-9a53-f632baba9016
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018475276 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 15.uart_stress_all_with_rand_reset.1018475276
Directory /workspace/15.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/172.uart_fifo_reset.2074292185
Short name T239
Test name
Test status
Simulation time 10804502897 ps
CPU time 20.02 seconds
Started Jun 09 02:20:35 PM PDT 24
Finished Jun 09 02:20:55 PM PDT 24
Peak memory 200068 kb
Host smart-4d7dc486-be03-43c3-9e52-fa338c0973ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074292185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.2074292185
Directory /workspace/172.uart_fifo_reset/latest

Test location /workspace/coverage/default/180.uart_fifo_reset.932936103
Short name T249
Test name
Test status
Simulation time 125095929774 ps
CPU time 58.1 seconds
Started Jun 09 02:20:38 PM PDT 24
Finished Jun 09 02:21:37 PM PDT 24
Peak memory 200420 kb
Host smart-5d0cc098-494f-4a23-88aa-683117a692bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932936103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.932936103
Directory /workspace/180.uart_fifo_reset/latest

Test location /workspace/coverage/default/196.uart_fifo_reset.810576638
Short name T236
Test name
Test status
Simulation time 25367177283 ps
CPU time 42.97 seconds
Started Jun 09 02:20:47 PM PDT 24
Finished Jun 09 02:21:30 PM PDT 24
Peak memory 200360 kb
Host smart-6e70eecd-daeb-4cf9-b043-48ecee41be7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810576638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.810576638
Directory /workspace/196.uart_fifo_reset/latest

Test location /workspace/coverage/default/206.uart_fifo_reset.1430599313
Short name T220
Test name
Test status
Simulation time 185663771243 ps
CPU time 21.14 seconds
Started Jun 09 02:20:51 PM PDT 24
Finished Jun 09 02:21:13 PM PDT 24
Peak memory 200364 kb
Host smart-5af9c955-4bb3-4179-9bbf-7c19a8bdeafc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430599313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.1430599313
Directory /workspace/206.uart_fifo_reset/latest

Test location /workspace/coverage/default/215.uart_fifo_reset.3833282069
Short name T247
Test name
Test status
Simulation time 139920070331 ps
CPU time 127.33 seconds
Started Jun 09 02:20:51 PM PDT 24
Finished Jun 09 02:22:59 PM PDT 24
Peak memory 200308 kb
Host smart-36ee6a25-149f-4208-8751-8fbe85a7d3db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833282069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.3833282069
Directory /workspace/215.uart_fifo_reset/latest

Test location /workspace/coverage/default/239.uart_fifo_reset.3566000126
Short name T237
Test name
Test status
Simulation time 29336126425 ps
CPU time 24.23 seconds
Started Jun 09 02:21:01 PM PDT 24
Finished Jun 09 02:21:25 PM PDT 24
Peak memory 200368 kb
Host smart-3ddc9513-6b21-4d89-aa4c-7df185ab85fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566000126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.3566000126
Directory /workspace/239.uart_fifo_reset/latest

Test location /workspace/coverage/default/298.uart_fifo_reset.1229112203
Short name T243
Test name
Test status
Simulation time 25497777078 ps
CPU time 41.22 seconds
Started Jun 09 02:21:29 PM PDT 24
Finished Jun 09 02:22:10 PM PDT 24
Peak memory 200380 kb
Host smart-9fd1213e-b270-4ef3-8b7b-6719e981cc3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229112203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.1229112203
Directory /workspace/298.uart_fifo_reset/latest

Test location /workspace/coverage/default/38.uart_fifo_reset.600757001
Short name T229
Test name
Test status
Simulation time 72734531703 ps
CPU time 26.83 seconds
Started Jun 09 02:17:57 PM PDT 24
Finished Jun 09 02:18:24 PM PDT 24
Peak memory 199968 kb
Host smart-2e64ca06-a05d-4294-ba6b-980bfd75bdc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600757001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.600757001
Directory /workspace/38.uart_fifo_reset/latest

Test location /workspace/coverage/default/70.uart_fifo_reset.1360566286
Short name T226
Test name
Test status
Simulation time 16059041319 ps
CPU time 32.38 seconds
Started Jun 09 02:19:39 PM PDT 24
Finished Jun 09 02:20:12 PM PDT 24
Peak memory 200288 kb
Host smart-41cbf0bd-932a-4fe7-b090-58300c14763e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360566286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.1360566286
Directory /workspace/70.uart_fifo_reset/latest

Test location /workspace/coverage/default/76.uart_fifo_reset.2822616868
Short name T240
Test name
Test status
Simulation time 14484109459 ps
CPU time 32.75 seconds
Started Jun 09 02:19:31 PM PDT 24
Finished Jun 09 02:20:04 PM PDT 24
Peak memory 200392 kb
Host smart-a1504e09-2162-44b8-a957-6cb379ec4444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822616868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.2822616868
Directory /workspace/76.uart_fifo_reset/latest

Test location /workspace/coverage/default/81.uart_fifo_reset.604542337
Short name T230
Test name
Test status
Simulation time 37961532314 ps
CPU time 34.54 seconds
Started Jun 09 02:19:37 PM PDT 24
Finished Jun 09 02:20:12 PM PDT 24
Peak memory 200400 kb
Host smart-354b8896-8841-41c0-a242-012e7c51be9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604542337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.604542337
Directory /workspace/81.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.859297405
Short name T78
Test name
Test status
Simulation time 26230824 ps
CPU time 0.79 seconds
Started Jun 09 12:35:49 PM PDT 24
Finished Jun 09 12:35:51 PM PDT 24
Peak memory 197112 kb
Host smart-a10002ac-8791-4a73-a91f-bee50a3b3566
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859297405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.859297405
Directory /workspace/0.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.2669772321
Short name T1139
Test name
Test status
Simulation time 262559534 ps
CPU time 2.45 seconds
Started Jun 09 12:35:50 PM PDT 24
Finished Jun 09 12:35:53 PM PDT 24
Peak memory 198296 kb
Host smart-9657ac3d-1f64-4fbd-9040-f3bfa98e4b2b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669772321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.2669772321
Directory /workspace/0.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.4151659253
Short name T60
Test name
Test status
Simulation time 14474590 ps
CPU time 0.58 seconds
Started Jun 09 12:35:49 PM PDT 24
Finished Jun 09 12:35:50 PM PDT 24
Peak memory 196068 kb
Host smart-e365d191-05da-4663-a809-05bd492710f6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151659253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.4151659253
Directory /workspace/0.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.3965015971
Short name T1093
Test name
Test status
Simulation time 28698174 ps
CPU time 0.77 seconds
Started Jun 09 12:35:58 PM PDT 24
Finished Jun 09 12:36:00 PM PDT 24
Peak memory 200568 kb
Host smart-4801209d-5b91-4347-bb51-7994907379d2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965015971 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.3965015971
Directory /workspace/0.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_rw.3195053096
Short name T1207
Test name
Test status
Simulation time 38576542 ps
CPU time 0.58 seconds
Started Jun 09 12:35:46 PM PDT 24
Finished Jun 09 12:35:47 PM PDT 24
Peak memory 196068 kb
Host smart-c7d910e9-fb7b-4982-bdc3-20084246306c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195053096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.3195053096
Directory /workspace/0.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.uart_intr_test.1248440219
Short name T1106
Test name
Test status
Simulation time 15569374 ps
CPU time 0.56 seconds
Started Jun 09 12:35:47 PM PDT 24
Finished Jun 09 12:35:49 PM PDT 24
Peak memory 195112 kb
Host smart-34a0d556-d7e3-46da-8b42-1bec4913df3e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248440219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.1248440219
Directory /workspace/0.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.2558510982
Short name T1208
Test name
Test status
Simulation time 35161201 ps
CPU time 0.63 seconds
Started Jun 09 12:35:50 PM PDT 24
Finished Jun 09 12:35:51 PM PDT 24
Peak memory 196220 kb
Host smart-bb93d3e4-fbb8-4dcb-8704-da00e7a8b42c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558510982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr
_outstanding.2558510982
Directory /workspace/0.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_errors.4240073309
Short name T1141
Test name
Test status
Simulation time 26660599 ps
CPU time 1.31 seconds
Started Jun 09 12:35:53 PM PDT 24
Finished Jun 09 12:35:55 PM PDT 24
Peak memory 200784 kb
Host smart-5b51f0b6-aa2d-42cd-b3e3-11ed007543af
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240073309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.4240073309
Directory /workspace/0.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.1724098258
Short name T1163
Test name
Test status
Simulation time 145190370 ps
CPU time 0.93 seconds
Started Jun 09 12:36:02 PM PDT 24
Finished Jun 09 12:36:04 PM PDT 24
Peak memory 199552 kb
Host smart-c24498fa-e9bb-4075-907b-c3cfc4a94d0a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724098258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.1724098258
Directory /workspace/0.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.2554679257
Short name T1205
Test name
Test status
Simulation time 37668196 ps
CPU time 0.68 seconds
Started Jun 09 12:35:52 PM PDT 24
Finished Jun 09 12:35:53 PM PDT 24
Peak memory 195640 kb
Host smart-2f35daf5-9618-4dea-8a36-dac474a6ced8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554679257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.2554679257
Directory /workspace/1.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.1593970131
Short name T1212
Test name
Test status
Simulation time 1037852277 ps
CPU time 2.45 seconds
Started Jun 09 12:35:52 PM PDT 24
Finished Jun 09 12:35:55 PM PDT 24
Peak memory 198356 kb
Host smart-247421aa-e9bc-4f86-9109-534bb6b22cf9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593970131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.1593970131
Directory /workspace/1.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.834393744
Short name T1188
Test name
Test status
Simulation time 14592744 ps
CPU time 0.55 seconds
Started Jun 09 12:35:47 PM PDT 24
Finished Jun 09 12:35:48 PM PDT 24
Peak memory 196100 kb
Host smart-f5ed5dc2-11f7-41b0-80ac-050457f114b8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834393744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.834393744
Directory /workspace/1.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.678448928
Short name T1131
Test name
Test status
Simulation time 35881967 ps
CPU time 0.96 seconds
Started Jun 09 12:35:53 PM PDT 24
Finished Jun 09 12:35:54 PM PDT 24
Peak memory 200588 kb
Host smart-0d8cc3ed-14b3-4e67-ac5b-756c80fb669a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678448928 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.678448928
Directory /workspace/1.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_rw.1561850208
Short name T77
Test name
Test status
Simulation time 25390673 ps
CPU time 0.63 seconds
Started Jun 09 12:35:51 PM PDT 24
Finished Jun 09 12:35:53 PM PDT 24
Peak memory 196092 kb
Host smart-93500302-27f3-421d-9f03-1460112b3037
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561850208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.1561850208
Directory /workspace/1.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.uart_intr_test.648996834
Short name T1181
Test name
Test status
Simulation time 49254848 ps
CPU time 0.56 seconds
Started Jun 09 12:35:58 PM PDT 24
Finished Jun 09 12:36:01 PM PDT 24
Peak memory 195092 kb
Host smart-7e5a1b80-dcbc-44cb-bf60-438b158ae6e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648996834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.648996834
Directory /workspace/1.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_errors.672871016
Short name T1149
Test name
Test status
Simulation time 467565655 ps
CPU time 1.91 seconds
Started Jun 09 12:35:48 PM PDT 24
Finished Jun 09 12:35:50 PM PDT 24
Peak memory 200736 kb
Host smart-6178b289-4aed-4cca-ab23-722384d43ce6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672871016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.672871016
Directory /workspace/1.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.1624871123
Short name T1189
Test name
Test status
Simulation time 86298097 ps
CPU time 0.76 seconds
Started Jun 09 12:35:51 PM PDT 24
Finished Jun 09 12:35:52 PM PDT 24
Peak memory 199292 kb
Host smart-d42537cb-a14c-472f-b946-90ce3dd9f927
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624871123 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.1624871123
Directory /workspace/10.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_rw.4206644607
Short name T1170
Test name
Test status
Simulation time 45645424 ps
CPU time 0.61 seconds
Started Jun 09 12:35:54 PM PDT 24
Finished Jun 09 12:35:55 PM PDT 24
Peak memory 196300 kb
Host smart-c1a08cc8-f04d-4791-a38f-6b11d294eb5d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206644607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.4206644607
Directory /workspace/10.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.uart_intr_test.2967260448
Short name T1165
Test name
Test status
Simulation time 19536223 ps
CPU time 0.57 seconds
Started Jun 09 12:35:58 PM PDT 24
Finished Jun 09 12:36:00 PM PDT 24
Peak memory 195128 kb
Host smart-1e8a7733-f1d2-43d0-861d-8acac129e3fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967260448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.2967260448
Directory /workspace/10.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.3560194259
Short name T1169
Test name
Test status
Simulation time 20582072 ps
CPU time 0.62 seconds
Started Jun 09 12:35:50 PM PDT 24
Finished Jun 09 12:35:51 PM PDT 24
Peak memory 196312 kb
Host smart-cb55b529-4a59-4e20-bda5-fcf5f004f5b4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560194259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_cs
r_outstanding.3560194259
Directory /workspace/10.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_errors.1795569046
Short name T1144
Test name
Test status
Simulation time 110625924 ps
CPU time 1.78 seconds
Started Jun 09 12:35:55 PM PDT 24
Finished Jun 09 12:35:57 PM PDT 24
Peak memory 200776 kb
Host smart-2556524f-09e6-4569-9cbc-0acc67daada0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795569046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.1795569046
Directory /workspace/10.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.3952365944
Short name T1185
Test name
Test status
Simulation time 147728958 ps
CPU time 1 seconds
Started Jun 09 12:35:51 PM PDT 24
Finished Jun 09 12:35:53 PM PDT 24
Peak memory 199792 kb
Host smart-cdcf370b-7b67-4ea2-9d5a-63c263683128
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952365944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.3952365944
Directory /workspace/10.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.863342274
Short name T1142
Test name
Test status
Simulation time 53893733 ps
CPU time 0.8 seconds
Started Jun 09 12:35:48 PM PDT 24
Finished Jun 09 12:35:49 PM PDT 24
Peak memory 200584 kb
Host smart-79885a2e-11ac-401a-aa65-7bedac3496e2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863342274 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.863342274
Directory /workspace/11.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_rw.1017037841
Short name T80
Test name
Test status
Simulation time 13410647 ps
CPU time 0.62 seconds
Started Jun 09 12:35:51 PM PDT 24
Finished Jun 09 12:35:52 PM PDT 24
Peak memory 196104 kb
Host smart-2b8f6eed-588d-48df-bcf0-18532ca59091
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017037841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.1017037841
Directory /workspace/11.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.uart_intr_test.152107417
Short name T1195
Test name
Test status
Simulation time 15386615 ps
CPU time 0.56 seconds
Started Jun 09 12:35:51 PM PDT 24
Finished Jun 09 12:35:52 PM PDT 24
Peak memory 195148 kb
Host smart-0fab8b1d-f80f-41cf-881a-25a9986d9b7a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152107417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.152107417
Directory /workspace/11.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.894897505
Short name T1137
Test name
Test status
Simulation time 24019567 ps
CPU time 0.65 seconds
Started Jun 09 12:35:55 PM PDT 24
Finished Jun 09 12:35:56 PM PDT 24
Peak memory 196388 kb
Host smart-cb1aa88f-18bc-4eea-ae7e-37380d6dd0ad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894897505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_csr
_outstanding.894897505
Directory /workspace/11.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_errors.3423309555
Short name T1130
Test name
Test status
Simulation time 203027292 ps
CPU time 1.96 seconds
Started Jun 09 12:35:49 PM PDT 24
Finished Jun 09 12:35:51 PM PDT 24
Peak memory 200768 kb
Host smart-56b89cb8-6611-4fd7-a351-3cef8023fd20
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423309555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.3423309555
Directory /workspace/11.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.701052065
Short name T1092
Test name
Test status
Simulation time 439119283 ps
CPU time 0.8 seconds
Started Jun 09 12:35:49 PM PDT 24
Finished Jun 09 12:35:50 PM PDT 24
Peak memory 200588 kb
Host smart-accb4d59-8fa7-40d0-b6cb-987765d78926
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701052065 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.701052065
Directory /workspace/12.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_rw.2910019022
Short name T66
Test name
Test status
Simulation time 14396300 ps
CPU time 0.58 seconds
Started Jun 09 12:35:47 PM PDT 24
Finished Jun 09 12:35:48 PM PDT 24
Peak memory 196200 kb
Host smart-2fb2b57e-a960-4e84-bb71-4de224d9a214
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910019022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.2910019022
Directory /workspace/12.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.uart_intr_test.2535303137
Short name T1178
Test name
Test status
Simulation time 25501677 ps
CPU time 0.52 seconds
Started Jun 09 12:35:45 PM PDT 24
Finished Jun 09 12:35:46 PM PDT 24
Peak memory 194988 kb
Host smart-d0a89d7f-4dd2-4d7c-8a07-7e824a31e649
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535303137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.2535303137
Directory /workspace/12.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.2801842135
Short name T1201
Test name
Test status
Simulation time 61594912 ps
CPU time 0.64 seconds
Started Jun 09 12:35:59 PM PDT 24
Finished Jun 09 12:36:01 PM PDT 24
Peak memory 196192 kb
Host smart-fc49bfbc-ace4-4c2b-a02f-cc8ae868a831
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801842135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_cs
r_outstanding.2801842135
Directory /workspace/12.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_errors.3683801679
Short name T1172
Test name
Test status
Simulation time 191610239 ps
CPU time 2.07 seconds
Started Jun 09 12:35:59 PM PDT 24
Finished Jun 09 12:36:02 PM PDT 24
Peak memory 200780 kb
Host smart-10aec8eb-8cb5-47c9-ad5e-150213c99dcc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683801679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.3683801679
Directory /workspace/12.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.3946827592
Short name T124
Test name
Test status
Simulation time 51357478 ps
CPU time 0.94 seconds
Started Jun 09 12:35:51 PM PDT 24
Finished Jun 09 12:35:53 PM PDT 24
Peak memory 199228 kb
Host smart-71b88bc6-a77f-4b23-9674-23dae81dac28
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946827592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.3946827592
Directory /workspace/12.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.2644394362
Short name T1119
Test name
Test status
Simulation time 164067149 ps
CPU time 0.74 seconds
Started Jun 09 12:35:51 PM PDT 24
Finished Jun 09 12:35:52 PM PDT 24
Peak memory 200280 kb
Host smart-e3719577-e0f4-4bec-89ff-52f84979f70c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644394362 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.2644394362
Directory /workspace/13.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_intr_test.3534119314
Short name T1196
Test name
Test status
Simulation time 14882266 ps
CPU time 0.58 seconds
Started Jun 09 12:35:51 PM PDT 24
Finished Jun 09 12:35:52 PM PDT 24
Peak memory 195136 kb
Host smart-3eaacce0-ec22-437b-90e8-206f13e4fcbd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534119314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.3534119314
Directory /workspace/13.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.3080474615
Short name T1166
Test name
Test status
Simulation time 78231089 ps
CPU time 0.65 seconds
Started Jun 09 12:35:50 PM PDT 24
Finished Jun 09 12:35:52 PM PDT 24
Peak memory 196412 kb
Host smart-588c96d9-533c-43b0-812c-1701c5a296e5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080474615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_cs
r_outstanding.3080474615
Directory /workspace/13.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_errors.3633302514
Short name T1088
Test name
Test status
Simulation time 235104071 ps
CPU time 1.43 seconds
Started Jun 09 12:35:57 PM PDT 24
Finished Jun 09 12:36:00 PM PDT 24
Peak memory 200780 kb
Host smart-e176702c-83e0-4a24-8cba-beac0351a780
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633302514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.3633302514
Directory /workspace/13.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.2669468267
Short name T1161
Test name
Test status
Simulation time 102596720 ps
CPU time 0.96 seconds
Started Jun 09 12:36:26 PM PDT 24
Finished Jun 09 12:36:27 PM PDT 24
Peak memory 199724 kb
Host smart-767b6ac8-0a1c-4257-9d6c-2aefc3e43c00
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669468267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.2669468267
Directory /workspace/13.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.2117850465
Short name T1147
Test name
Test status
Simulation time 20144299 ps
CPU time 0.84 seconds
Started Jun 09 12:35:56 PM PDT 24
Finished Jun 09 12:35:58 PM PDT 24
Peak memory 200556 kb
Host smart-86cd9b83-4ec4-4b43-9d4f-71c6722e8d04
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117850465 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.2117850465
Directory /workspace/14.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_rw.1418292689
Short name T1151
Test name
Test status
Simulation time 15808477 ps
CPU time 0.56 seconds
Started Jun 09 12:35:56 PM PDT 24
Finished Jun 09 12:35:57 PM PDT 24
Peak memory 196044 kb
Host smart-3c79d293-c57b-4e51-a4ee-49386211f023
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418292689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.1418292689
Directory /workspace/14.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.uart_intr_test.220899367
Short name T1152
Test name
Test status
Simulation time 21065318 ps
CPU time 0.54 seconds
Started Jun 09 12:35:53 PM PDT 24
Finished Jun 09 12:35:54 PM PDT 24
Peak memory 195148 kb
Host smart-026b9e4e-1388-4ff5-b15b-e2f8c0069375
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220899367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.220899367
Directory /workspace/14.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.1380022410
Short name T1187
Test name
Test status
Simulation time 70174616 ps
CPU time 0.66 seconds
Started Jun 09 12:36:10 PM PDT 24
Finished Jun 09 12:36:11 PM PDT 24
Peak memory 195252 kb
Host smart-f6ef2035-ac68-49bd-9eb3-33a44fd5f32f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380022410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_cs
r_outstanding.1380022410
Directory /workspace/14.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_errors.126254468
Short name T1136
Test name
Test status
Simulation time 241996314 ps
CPU time 1.17 seconds
Started Jun 09 12:35:48 PM PDT 24
Finished Jun 09 12:35:50 PM PDT 24
Peak memory 200772 kb
Host smart-296a194a-7777-4f72-ada6-c94549a38ee9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126254468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.126254468
Directory /workspace/14.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.4222013637
Short name T1183
Test name
Test status
Simulation time 41371890 ps
CPU time 0.89 seconds
Started Jun 09 12:35:52 PM PDT 24
Finished Jun 09 12:35:53 PM PDT 24
Peak memory 199436 kb
Host smart-16da8405-6f27-4d0f-818b-f9fd42747d81
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222013637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.4222013637
Directory /workspace/14.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.1073615675
Short name T1186
Test name
Test status
Simulation time 20415184 ps
CPU time 1 seconds
Started Jun 09 12:35:57 PM PDT 24
Finished Jun 09 12:35:59 PM PDT 24
Peak memory 200564 kb
Host smart-509a20e8-5ad9-4717-93f9-29c9288f7f18
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073615675 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.1073615675
Directory /workspace/15.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_rw.1575880781
Short name T64
Test name
Test status
Simulation time 16386669 ps
CPU time 0.57 seconds
Started Jun 09 12:36:05 PM PDT 24
Finished Jun 09 12:36:06 PM PDT 24
Peak memory 196100 kb
Host smart-914d5dd6-22d3-49ff-a6ec-991053c3c393
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575880781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.1575880781
Directory /workspace/15.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.uart_intr_test.38626278
Short name T1148
Test name
Test status
Simulation time 56047938 ps
CPU time 0.62 seconds
Started Jun 09 12:36:26 PM PDT 24
Finished Jun 09 12:36:27 PM PDT 24
Peak memory 195148 kb
Host smart-d927bf44-9738-41c7-ac4a-0b8abcb68e7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38626278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.38626278
Directory /workspace/15.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.424096038
Short name T84
Test name
Test status
Simulation time 110020154 ps
CPU time 0.76 seconds
Started Jun 09 12:35:59 PM PDT 24
Finished Jun 09 12:36:01 PM PDT 24
Peak memory 197400 kb
Host smart-1d6938f6-45c4-4a8b-9671-ea4c3e26f48d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424096038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_csr
_outstanding.424096038
Directory /workspace/15.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_errors.3335974122
Short name T1129
Test name
Test status
Simulation time 73556609 ps
CPU time 1.86 seconds
Started Jun 09 12:36:17 PM PDT 24
Finished Jun 09 12:36:20 PM PDT 24
Peak memory 200680 kb
Host smart-a559dfad-d0df-460b-a4b9-865707c900e9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335974122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.3335974122
Directory /workspace/15.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.626881104
Short name T1105
Test name
Test status
Simulation time 72032964 ps
CPU time 1 seconds
Started Jun 09 12:36:29 PM PDT 24
Finished Jun 09 12:36:31 PM PDT 24
Peak memory 199720 kb
Host smart-e2fcf53a-5851-4226-88a0-31379d145fd9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626881104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.626881104
Directory /workspace/15.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.3152462587
Short name T1125
Test name
Test status
Simulation time 84020481 ps
CPU time 1.13 seconds
Started Jun 09 12:35:48 PM PDT 24
Finished Jun 09 12:35:50 PM PDT 24
Peak memory 200776 kb
Host smart-6234309b-94b7-477b-94e8-2bcede8fb8ff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152462587 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.3152462587
Directory /workspace/16.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_rw.403381876
Short name T1146
Test name
Test status
Simulation time 21142065 ps
CPU time 0.56 seconds
Started Jun 09 12:35:47 PM PDT 24
Finished Jun 09 12:35:48 PM PDT 24
Peak memory 196084 kb
Host smart-bf516990-8de9-49cb-9b7d-2ef18abcc5fe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403381876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.403381876
Directory /workspace/16.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.uart_intr_test.2416123021
Short name T1167
Test name
Test status
Simulation time 48520387 ps
CPU time 0.55 seconds
Started Jun 09 12:35:50 PM PDT 24
Finished Jun 09 12:35:52 PM PDT 24
Peak memory 195040 kb
Host smart-19686193-92d2-447c-b2be-ee599b515813
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416123021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.2416123021
Directory /workspace/16.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.1249008548
Short name T86
Test name
Test status
Simulation time 90497900 ps
CPU time 0.7 seconds
Started Jun 09 12:36:00 PM PDT 24
Finished Jun 09 12:36:02 PM PDT 24
Peak memory 196596 kb
Host smart-6eb20cb2-5a13-45f9-9f98-ff325795532e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249008548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_cs
r_outstanding.1249008548
Directory /workspace/16.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_errors.999080198
Short name T1127
Test name
Test status
Simulation time 222337271 ps
CPU time 1.34 seconds
Started Jun 09 12:36:00 PM PDT 24
Finished Jun 09 12:36:02 PM PDT 24
Peak memory 200788 kb
Host smart-9524e31a-918d-452b-8a2d-b93ff22ca825
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999080198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.999080198
Directory /workspace/16.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.2220883088
Short name T1133
Test name
Test status
Simulation time 102681081 ps
CPU time 0.89 seconds
Started Jun 09 12:35:57 PM PDT 24
Finished Jun 09 12:36:00 PM PDT 24
Peak memory 200524 kb
Host smart-6d98ebb3-659e-47eb-b1f8-b85c02871862
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220883088 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.2220883088
Directory /workspace/17.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_rw.1154094603
Short name T1199
Test name
Test status
Simulation time 14856187 ps
CPU time 0.63 seconds
Started Jun 09 12:35:59 PM PDT 24
Finished Jun 09 12:36:01 PM PDT 24
Peak memory 196028 kb
Host smart-d7ccced4-1816-4089-b156-f2daa099962f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154094603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.1154094603
Directory /workspace/17.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.uart_intr_test.2363115899
Short name T1214
Test name
Test status
Simulation time 25440551 ps
CPU time 0.57 seconds
Started Jun 09 12:35:57 PM PDT 24
Finished Jun 09 12:36:00 PM PDT 24
Peak memory 195136 kb
Host smart-c36ba8ea-bd8c-473a-b47c-c4ccd400ef3f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363115899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.2363115899
Directory /workspace/17.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.3687898588
Short name T1168
Test name
Test status
Simulation time 101431109 ps
CPU time 0.72 seconds
Started Jun 09 12:35:51 PM PDT 24
Finished Jun 09 12:35:52 PM PDT 24
Peak memory 198248 kb
Host smart-2d428859-a217-412e-9417-8049c9742ef5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687898588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_cs
r_outstanding.3687898588
Directory /workspace/17.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_errors.1509056798
Short name T1138
Test name
Test status
Simulation time 115023806 ps
CPU time 1.55 seconds
Started Jun 09 12:35:49 PM PDT 24
Finished Jun 09 12:35:52 PM PDT 24
Peak memory 200780 kb
Host smart-7fda56a1-defa-4ff0-b9c4-f18a8758a7f4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509056798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.1509056798
Directory /workspace/17.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.2408999239
Short name T1210
Test name
Test status
Simulation time 87269435 ps
CPU time 1.25 seconds
Started Jun 09 12:35:59 PM PDT 24
Finished Jun 09 12:36:01 PM PDT 24
Peak memory 199788 kb
Host smart-7e3c761e-81f7-42fe-a095-dba3ab31bda3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408999239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.2408999239
Directory /workspace/17.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.2769485623
Short name T1158
Test name
Test status
Simulation time 18964649 ps
CPU time 0.87 seconds
Started Jun 09 12:35:44 PM PDT 24
Finished Jun 09 12:35:45 PM PDT 24
Peak memory 200544 kb
Host smart-305a3be3-347c-4c27-95a1-5d210c508ef6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769485623 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.2769485623
Directory /workspace/18.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_rw.329531859
Short name T1143
Test name
Test status
Simulation time 53399915 ps
CPU time 0.55 seconds
Started Jun 09 12:35:49 PM PDT 24
Finished Jun 09 12:35:50 PM PDT 24
Peak memory 196092 kb
Host smart-c735a33d-98ec-4ad1-97ad-c2423acd41e7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329531859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.329531859
Directory /workspace/18.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.uart_intr_test.3138540960
Short name T1116
Test name
Test status
Simulation time 22165884 ps
CPU time 0.62 seconds
Started Jun 09 12:35:59 PM PDT 24
Finished Jun 09 12:36:01 PM PDT 24
Peak memory 195044 kb
Host smart-61b612b3-1979-4558-b6a4-5d66d7c1c13e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138540960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.3138540960
Directory /workspace/18.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.1535090683
Short name T1156
Test name
Test status
Simulation time 31819458 ps
CPU time 0.77 seconds
Started Jun 09 12:35:57 PM PDT 24
Finished Jun 09 12:35:59 PM PDT 24
Peak memory 197812 kb
Host smart-1deb7ce9-e3cd-44fe-a15d-1ad390afb8e7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535090683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_cs
r_outstanding.1535090683
Directory /workspace/18.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_errors.1730932081
Short name T1132
Test name
Test status
Simulation time 283962862 ps
CPU time 1.94 seconds
Started Jun 09 12:35:53 PM PDT 24
Finished Jun 09 12:35:56 PM PDT 24
Peak memory 200788 kb
Host smart-5b9bf2c9-4e8d-4cb8-bb98-491bbb0a6816
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730932081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.1730932081
Directory /workspace/18.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.4256999812
Short name T1193
Test name
Test status
Simulation time 84309396 ps
CPU time 1.36 seconds
Started Jun 09 12:35:49 PM PDT 24
Finished Jun 09 12:35:51 PM PDT 24
Peak memory 200032 kb
Host smart-9e792ed6-8943-41c6-9804-95bd4c756a57
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256999812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.4256999812
Directory /workspace/18.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.2167419570
Short name T1192
Test name
Test status
Simulation time 120869196 ps
CPU time 0.72 seconds
Started Jun 09 12:35:57 PM PDT 24
Finished Jun 09 12:36:09 PM PDT 24
Peak memory 199652 kb
Host smart-9c596be2-b838-4605-9d18-565a6a750b99
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167419570 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.2167419570
Directory /workspace/19.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_rw.1481366761
Short name T1091
Test name
Test status
Simulation time 11648236 ps
CPU time 0.55 seconds
Started Jun 09 12:35:50 PM PDT 24
Finished Jun 09 12:35:52 PM PDT 24
Peak memory 196112 kb
Host smart-88ec314b-8bf8-4efe-a247-e7316f62ab4d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481366761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.1481366761
Directory /workspace/19.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.uart_intr_test.3407887501
Short name T1200
Test name
Test status
Simulation time 13951307 ps
CPU time 0.57 seconds
Started Jun 09 12:35:49 PM PDT 24
Finished Jun 09 12:35:50 PM PDT 24
Peak memory 195144 kb
Host smart-bcbffbab-78de-4516-9064-1bd1f8da1827
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407887501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.3407887501
Directory /workspace/19.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.2355136450
Short name T1145
Test name
Test status
Simulation time 34336622 ps
CPU time 0.64 seconds
Started Jun 09 12:35:48 PM PDT 24
Finished Jun 09 12:35:49 PM PDT 24
Peak memory 197268 kb
Host smart-2e5e778a-0020-46b4-9511-765ea1fe7860
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355136450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_cs
r_outstanding.2355136450
Directory /workspace/19.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_errors.146375280
Short name T1089
Test name
Test status
Simulation time 113249345 ps
CPU time 2.28 seconds
Started Jun 09 12:35:59 PM PDT 24
Finished Jun 09 12:36:02 PM PDT 24
Peak memory 200772 kb
Host smart-3edb8d91-b70e-4cec-9cd6-61dad2ee4a33
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146375280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.146375280
Directory /workspace/19.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.2880344075
Short name T91
Test name
Test status
Simulation time 365167162 ps
CPU time 1.26 seconds
Started Jun 09 12:35:51 PM PDT 24
Finished Jun 09 12:35:53 PM PDT 24
Peak memory 199812 kb
Host smart-1ea4b073-bec5-46d5-8d61-8906a38eb0f5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880344075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.2880344075
Directory /workspace/19.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.1576369449
Short name T1180
Test name
Test status
Simulation time 19717562 ps
CPU time 0.63 seconds
Started Jun 09 12:35:49 PM PDT 24
Finished Jun 09 12:35:50 PM PDT 24
Peak memory 195384 kb
Host smart-343af0a6-635c-421e-96d8-65c6e4403fc0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576369449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.1576369449
Directory /workspace/2.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.2816305091
Short name T1182
Test name
Test status
Simulation time 387741231 ps
CPU time 2.28 seconds
Started Jun 09 12:35:50 PM PDT 24
Finished Jun 09 12:35:53 PM PDT 24
Peak memory 198676 kb
Host smart-d24a8021-5675-4a61-afe1-fcd11ce0145f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816305091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.2816305091
Directory /workspace/2.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.1845709489
Short name T63
Test name
Test status
Simulation time 47102657 ps
CPU time 0.59 seconds
Started Jun 09 12:35:50 PM PDT 24
Finished Jun 09 12:35:51 PM PDT 24
Peak memory 196084 kb
Host smart-0f73fefa-d3cf-45b7-86bf-7e0fe554f445
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845709489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.1845709489
Directory /workspace/2.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.1083693668
Short name T1114
Test name
Test status
Simulation time 28748702 ps
CPU time 0.82 seconds
Started Jun 09 12:35:57 PM PDT 24
Finished Jun 09 12:35:59 PM PDT 24
Peak memory 200448 kb
Host smart-20b15c8d-990d-4bc4-b753-006e1a4b6f34
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083693668 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.1083693668
Directory /workspace/2.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_rw.1099918258
Short name T1134
Test name
Test status
Simulation time 41505498 ps
CPU time 0.6 seconds
Started Jun 09 12:35:48 PM PDT 24
Finished Jun 09 12:35:49 PM PDT 24
Peak memory 196064 kb
Host smart-dfa18949-6ece-4b5b-a46d-828a446ef182
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099918258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.1099918258
Directory /workspace/2.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.uart_intr_test.1254177398
Short name T1209
Test name
Test status
Simulation time 29292625 ps
CPU time 0.54 seconds
Started Jun 09 12:35:49 PM PDT 24
Finished Jun 09 12:35:51 PM PDT 24
Peak memory 195040 kb
Host smart-b5f9cc62-ecaf-4d5d-a3dc-677e5b38cf47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254177398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.1254177398
Directory /workspace/2.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.2136437213
Short name T1155
Test name
Test status
Simulation time 64264475 ps
CPU time 0.69 seconds
Started Jun 09 12:36:00 PM PDT 24
Finished Jun 09 12:36:02 PM PDT 24
Peak memory 196696 kb
Host smart-236ad33a-46c3-43b7-9d96-fd3443b62239
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136437213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr
_outstanding.2136437213
Directory /workspace/2.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_errors.2406002554
Short name T1101
Test name
Test status
Simulation time 48222540 ps
CPU time 1.26 seconds
Started Jun 09 12:35:49 PM PDT 24
Finished Jun 09 12:35:50 PM PDT 24
Peak memory 200772 kb
Host smart-0159a17a-fd60-4586-ac25-e9719dc02eeb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406002554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.2406002554
Directory /workspace/2.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.1696828586
Short name T93
Test name
Test status
Simulation time 330972929 ps
CPU time 1.24 seconds
Started Jun 09 12:35:54 PM PDT 24
Finished Jun 09 12:35:55 PM PDT 24
Peak memory 199988 kb
Host smart-12708e86-d9de-4a2e-b077-986e37e94fc5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696828586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.1696828586
Directory /workspace/2.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.uart_intr_test.780272863
Short name T1109
Test name
Test status
Simulation time 13873973 ps
CPU time 0.55 seconds
Started Jun 09 12:35:56 PM PDT 24
Finished Jun 09 12:35:57 PM PDT 24
Peak memory 195172 kb
Host smart-b1326a28-28a9-459e-87c5-bbe9692b0cf2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780272863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.780272863
Directory /workspace/20.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.uart_intr_test.4254432174
Short name T1123
Test name
Test status
Simulation time 108946363 ps
CPU time 0.56 seconds
Started Jun 09 12:35:58 PM PDT 24
Finished Jun 09 12:36:00 PM PDT 24
Peak memory 195140 kb
Host smart-e4e13cdc-b119-443d-8625-db64782a277d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254432174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.4254432174
Directory /workspace/21.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.uart_intr_test.1131545643
Short name T1197
Test name
Test status
Simulation time 47000893 ps
CPU time 0.56 seconds
Started Jun 09 12:35:57 PM PDT 24
Finished Jun 09 12:35:59 PM PDT 24
Peak memory 195064 kb
Host smart-fb08dac9-216d-4358-9852-3d020c3dc178
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131545643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.1131545643
Directory /workspace/22.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.uart_intr_test.3575923625
Short name T1173
Test name
Test status
Simulation time 11645529 ps
CPU time 0.54 seconds
Started Jun 09 12:35:50 PM PDT 24
Finished Jun 09 12:35:51 PM PDT 24
Peak memory 195084 kb
Host smart-4a900e90-3d29-47b4-8cd3-82080d9b9075
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575923625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.3575923625
Directory /workspace/23.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.uart_intr_test.2718292734
Short name T1216
Test name
Test status
Simulation time 18804338 ps
CPU time 0.58 seconds
Started Jun 09 12:35:59 PM PDT 24
Finished Jun 09 12:36:01 PM PDT 24
Peak memory 195140 kb
Host smart-ed8303c7-7908-4cff-ab97-51f71da29d95
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718292734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.2718292734
Directory /workspace/24.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.uart_intr_test.2112947033
Short name T1110
Test name
Test status
Simulation time 17319246 ps
CPU time 0.57 seconds
Started Jun 09 12:36:07 PM PDT 24
Finished Jun 09 12:36:08 PM PDT 24
Peak memory 195108 kb
Host smart-b1d181ed-1f26-4205-9614-bb319db86ed8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112947033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.2112947033
Directory /workspace/25.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.uart_intr_test.1432071337
Short name T1117
Test name
Test status
Simulation time 11310823 ps
CPU time 0.54 seconds
Started Jun 09 12:35:57 PM PDT 24
Finished Jun 09 12:35:59 PM PDT 24
Peak memory 195148 kb
Host smart-59810779-e75e-4e6a-b6a1-ddef32b4fd13
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432071337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.1432071337
Directory /workspace/26.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.uart_intr_test.4137048264
Short name T1135
Test name
Test status
Simulation time 38067350 ps
CPU time 0.56 seconds
Started Jun 09 12:35:58 PM PDT 24
Finished Jun 09 12:36:00 PM PDT 24
Peak memory 195076 kb
Host smart-3963d9de-a18e-4ff8-b760-424109d328d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137048264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.4137048264
Directory /workspace/27.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.uart_intr_test.1364989093
Short name T1219
Test name
Test status
Simulation time 93278286 ps
CPU time 0.57 seconds
Started Jun 09 12:36:04 PM PDT 24
Finished Jun 09 12:36:05 PM PDT 24
Peak memory 195092 kb
Host smart-06c7133e-2d79-4ac6-81e0-7a2734223fda
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364989093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.1364989093
Directory /workspace/28.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.uart_intr_test.3127405164
Short name T1120
Test name
Test status
Simulation time 25844694 ps
CPU time 0.54 seconds
Started Jun 09 12:35:51 PM PDT 24
Finished Jun 09 12:35:53 PM PDT 24
Peak memory 195064 kb
Host smart-b5b1e34f-2415-49e8-80af-7cb85c1e17fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127405164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.3127405164
Directory /workspace/29.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.3039785676
Short name T67
Test name
Test status
Simulation time 26294561 ps
CPU time 0.75 seconds
Started Jun 09 12:35:48 PM PDT 24
Finished Jun 09 12:35:49 PM PDT 24
Peak memory 196936 kb
Host smart-d6f36fdf-8ab1-4894-8750-fd7c39e758ad
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039785676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.3039785676
Directory /workspace/3.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.4162793738
Short name T1204
Test name
Test status
Simulation time 140980329 ps
CPU time 1.65 seconds
Started Jun 09 12:36:00 PM PDT 24
Finished Jun 09 12:36:02 PM PDT 24
Peak memory 198464 kb
Host smart-e8b09059-48c0-43ce-abeb-1296bd8a8591
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162793738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.4162793738
Directory /workspace/3.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.3554023251
Short name T1171
Test name
Test status
Simulation time 17891919 ps
CPU time 0.64 seconds
Started Jun 09 12:35:54 PM PDT 24
Finished Jun 09 12:35:55 PM PDT 24
Peak memory 196084 kb
Host smart-68c23f78-9b64-4db1-b4bd-8475a9247baa
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554023251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.3554023251
Directory /workspace/3.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.1777589470
Short name T1159
Test name
Test status
Simulation time 52490125 ps
CPU time 0.69 seconds
Started Jun 09 12:35:51 PM PDT 24
Finished Jun 09 12:35:53 PM PDT 24
Peak memory 198272 kb
Host smart-b3d78eb4-a1a6-4e71-991c-4097f667d032
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777589470 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.1777589470
Directory /workspace/3.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_rw.3825398643
Short name T1157
Test name
Test status
Simulation time 78969508 ps
CPU time 0.59 seconds
Started Jun 09 12:35:52 PM PDT 24
Finished Jun 09 12:35:53 PM PDT 24
Peak memory 196312 kb
Host smart-fd0b77b4-2f58-4c90-9630-60f09b73070b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825398643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.3825398643
Directory /workspace/3.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.uart_intr_test.2693136595
Short name T1220
Test name
Test status
Simulation time 22483969 ps
CPU time 0.63 seconds
Started Jun 09 12:35:58 PM PDT 24
Finished Jun 09 12:36:00 PM PDT 24
Peak memory 195316 kb
Host smart-c0fb5aa7-176b-4822-977c-782d692dc958
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693136595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.2693136595
Directory /workspace/3.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.923122082
Short name T87
Test name
Test status
Simulation time 23947253 ps
CPU time 0.76 seconds
Started Jun 09 12:35:57 PM PDT 24
Finished Jun 09 12:35:59 PM PDT 24
Peak memory 198008 kb
Host smart-8cb3f03f-a3b0-4c68-9411-b5d72df53c55
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923122082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr_
outstanding.923122082
Directory /workspace/3.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_errors.823241593
Short name T1215
Test name
Test status
Simulation time 102257009 ps
CPU time 1.47 seconds
Started Jun 09 12:36:00 PM PDT 24
Finished Jun 09 12:36:02 PM PDT 24
Peak memory 200784 kb
Host smart-0e179f3f-1288-4461-a490-0c1f3697021c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823241593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.823241593
Directory /workspace/3.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.2123034541
Short name T126
Test name
Test status
Simulation time 296018790 ps
CPU time 1.26 seconds
Started Jun 09 12:35:51 PM PDT 24
Finished Jun 09 12:35:53 PM PDT 24
Peak memory 200032 kb
Host smart-e24c4941-b288-4d66-96cf-ae5d715e0079
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123034541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.2123034541
Directory /workspace/3.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.uart_intr_test.609248098
Short name T1124
Test name
Test status
Simulation time 106578730 ps
CPU time 0.59 seconds
Started Jun 09 12:35:59 PM PDT 24
Finished Jun 09 12:36:01 PM PDT 24
Peak memory 195148 kb
Host smart-5ae789a9-5ea2-4626-a3cd-939efa37786e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609248098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.609248098
Directory /workspace/30.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.uart_intr_test.3800653199
Short name T1221
Test name
Test status
Simulation time 11017858 ps
CPU time 0.57 seconds
Started Jun 09 12:35:58 PM PDT 24
Finished Jun 09 12:36:00 PM PDT 24
Peak memory 195108 kb
Host smart-75be78c4-0467-4d1d-84c8-f4ff5ebfa5de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800653199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.3800653199
Directory /workspace/31.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.uart_intr_test.4146994950
Short name T1121
Test name
Test status
Simulation time 44126230 ps
CPU time 0.53 seconds
Started Jun 09 12:35:54 PM PDT 24
Finished Jun 09 12:35:55 PM PDT 24
Peak memory 195064 kb
Host smart-b749fb49-4160-4645-9a3b-15e227908f9b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146994950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.4146994950
Directory /workspace/32.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.uart_intr_test.134269113
Short name T1140
Test name
Test status
Simulation time 23666953 ps
CPU time 0.59 seconds
Started Jun 09 12:35:53 PM PDT 24
Finished Jun 09 12:35:54 PM PDT 24
Peak memory 195076 kb
Host smart-4145bec5-2ca2-4b6a-874f-79359c77904b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134269113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.134269113
Directory /workspace/33.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.uart_intr_test.3496912135
Short name T1213
Test name
Test status
Simulation time 41805391 ps
CPU time 0.55 seconds
Started Jun 09 12:35:56 PM PDT 24
Finished Jun 09 12:35:58 PM PDT 24
Peak memory 195060 kb
Host smart-57178ec1-f376-445c-8a4f-acf094b52558
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496912135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.3496912135
Directory /workspace/34.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.uart_intr_test.1865945137
Short name T1184
Test name
Test status
Simulation time 42451972 ps
CPU time 0.57 seconds
Started Jun 09 12:35:58 PM PDT 24
Finished Jun 09 12:36:00 PM PDT 24
Peak memory 195136 kb
Host smart-1182ebc9-4c3f-4d63-a46c-f685cf974faf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865945137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.1865945137
Directory /workspace/35.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.uart_intr_test.2670941790
Short name T1115
Test name
Test status
Simulation time 78471249 ps
CPU time 0.54 seconds
Started Jun 09 12:35:50 PM PDT 24
Finished Jun 09 12:35:51 PM PDT 24
Peak memory 195064 kb
Host smart-157b1615-b600-47bc-80fd-7b8fcbf3c543
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670941790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.2670941790
Directory /workspace/36.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.uart_intr_test.1360078036
Short name T1095
Test name
Test status
Simulation time 12847092 ps
CPU time 0.59 seconds
Started Jun 09 12:35:56 PM PDT 24
Finished Jun 09 12:35:57 PM PDT 24
Peak memory 195136 kb
Host smart-5a0eaaf2-bee9-4506-aa0d-6deaf48886de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360078036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.1360078036
Directory /workspace/37.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.uart_intr_test.682580142
Short name T1104
Test name
Test status
Simulation time 20245789 ps
CPU time 0.59 seconds
Started Jun 09 12:35:49 PM PDT 24
Finished Jun 09 12:35:55 PM PDT 24
Peak memory 195084 kb
Host smart-1700513a-9218-4fef-8a46-3eeae6ac4f73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682580142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.682580142
Directory /workspace/38.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.uart_intr_test.2028173453
Short name T1202
Test name
Test status
Simulation time 14405508 ps
CPU time 0.6 seconds
Started Jun 09 12:36:25 PM PDT 24
Finished Jun 09 12:36:26 PM PDT 24
Peak memory 195064 kb
Host smart-255a9b3e-5430-46e5-a71f-10a52cdcb16e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028173453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.2028173453
Directory /workspace/39.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.1990930625
Short name T1222
Test name
Test status
Simulation time 21432309 ps
CPU time 0.65 seconds
Started Jun 09 12:35:45 PM PDT 24
Finished Jun 09 12:35:51 PM PDT 24
Peak memory 196084 kb
Host smart-e9656bb4-0c65-4860-a9b6-c3aee16017d1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990930625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.1990930625
Directory /workspace/4.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.359024802
Short name T1153
Test name
Test status
Simulation time 269186357 ps
CPU time 1.6 seconds
Started Jun 09 12:35:56 PM PDT 24
Finished Jun 09 12:35:58 PM PDT 24
Peak memory 198576 kb
Host smart-15515b6d-1e87-43a1-97df-2fe4d38c37dd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359024802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.359024802
Directory /workspace/4.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.3018359101
Short name T61
Test name
Test status
Simulation time 13849864 ps
CPU time 0.58 seconds
Started Jun 09 12:35:48 PM PDT 24
Finished Jun 09 12:35:49 PM PDT 24
Peak memory 196036 kb
Host smart-f22d29eb-d970-40bf-9f9f-ea45511cecdc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018359101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.3018359101
Directory /workspace/4.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.1058678289
Short name T1118
Test name
Test status
Simulation time 48978356 ps
CPU time 0.71 seconds
Started Jun 09 12:35:49 PM PDT 24
Finished Jun 09 12:35:51 PM PDT 24
Peak memory 199420 kb
Host smart-c84f375e-c3f1-4d34-aeb3-d741b392127f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058678289 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.1058678289
Directory /workspace/4.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_rw.1403870770
Short name T1175
Test name
Test status
Simulation time 12030890 ps
CPU time 0.62 seconds
Started Jun 09 12:35:47 PM PDT 24
Finished Jun 09 12:35:48 PM PDT 24
Peak memory 196324 kb
Host smart-4505f958-1ef3-4860-96d7-dd8dc29fe363
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403870770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.1403870770
Directory /workspace/4.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.uart_intr_test.345993763
Short name T1103
Test name
Test status
Simulation time 42314519 ps
CPU time 0.57 seconds
Started Jun 09 12:35:53 PM PDT 24
Finished Jun 09 12:35:54 PM PDT 24
Peak memory 195080 kb
Host smart-8aa671fc-0073-4bc1-bcc2-e88d3a698e53
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345993763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.345993763
Directory /workspace/4.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.3070231376
Short name T1154
Test name
Test status
Simulation time 18021215 ps
CPU time 0.64 seconds
Started Jun 09 12:35:51 PM PDT 24
Finished Jun 09 12:35:52 PM PDT 24
Peak memory 196076 kb
Host smart-afa92908-105f-4fb3-a80f-69a00233165d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070231376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr
_outstanding.3070231376
Directory /workspace/4.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_errors.2518776809
Short name T1097
Test name
Test status
Simulation time 48721906 ps
CPU time 1.05 seconds
Started Jun 09 12:36:03 PM PDT 24
Finished Jun 09 12:36:04 PM PDT 24
Peak memory 200560 kb
Host smart-36ab58f5-fcfe-4d56-aea2-05dd36a758df
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518776809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.2518776809
Directory /workspace/4.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.1683213420
Short name T1090
Test name
Test status
Simulation time 74693402 ps
CPU time 0.9 seconds
Started Jun 09 12:35:53 PM PDT 24
Finished Jun 09 12:35:54 PM PDT 24
Peak memory 199620 kb
Host smart-7ddffa1e-7e55-4390-b527-a93a602561db
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683213420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.1683213420
Directory /workspace/4.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.uart_intr_test.165701661
Short name T1100
Test name
Test status
Simulation time 11536201 ps
CPU time 0.55 seconds
Started Jun 09 12:35:56 PM PDT 24
Finished Jun 09 12:35:57 PM PDT 24
Peak memory 195100 kb
Host smart-7f84c8b4-2ac9-4b1e-bfe4-e8eaa601fee8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165701661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.165701661
Directory /workspace/40.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.uart_intr_test.2378482417
Short name T1176
Test name
Test status
Simulation time 18508901 ps
CPU time 0.57 seconds
Started Jun 09 12:35:58 PM PDT 24
Finished Jun 09 12:36:00 PM PDT 24
Peak memory 195128 kb
Host smart-f2d9387c-e984-4ff3-850a-33f4cf46ef34
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378482417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.2378482417
Directory /workspace/41.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.uart_intr_test.3408725431
Short name T1099
Test name
Test status
Simulation time 74480558 ps
CPU time 0.55 seconds
Started Jun 09 12:35:55 PM PDT 24
Finished Jun 09 12:35:56 PM PDT 24
Peak memory 195132 kb
Host smart-f7940c21-ba53-4620-900f-405a636cacb4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408725431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.3408725431
Directory /workspace/42.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.uart_intr_test.1713407703
Short name T1150
Test name
Test status
Simulation time 47327442 ps
CPU time 0.56 seconds
Started Jun 09 12:35:59 PM PDT 24
Finished Jun 09 12:36:01 PM PDT 24
Peak memory 195088 kb
Host smart-96eadfdd-fea9-4ad7-ad38-3d96b2333854
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713407703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.1713407703
Directory /workspace/43.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.uart_intr_test.1541475618
Short name T1190
Test name
Test status
Simulation time 23113931 ps
CPU time 0.57 seconds
Started Jun 09 12:35:58 PM PDT 24
Finished Jun 09 12:36:00 PM PDT 24
Peak memory 195076 kb
Host smart-23b3d7ce-bbf7-456d-9f82-619b54d824a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541475618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.1541475618
Directory /workspace/44.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.uart_intr_test.3147823487
Short name T1096
Test name
Test status
Simulation time 13550413 ps
CPU time 0.54 seconds
Started Jun 09 12:36:03 PM PDT 24
Finished Jun 09 12:36:03 PM PDT 24
Peak memory 195108 kb
Host smart-f76767d4-f757-435a-8ba0-68da2f8f93ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147823487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.3147823487
Directory /workspace/45.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.uart_intr_test.2879319979
Short name T1126
Test name
Test status
Simulation time 44763893 ps
CPU time 0.55 seconds
Started Jun 09 12:35:50 PM PDT 24
Finished Jun 09 12:35:51 PM PDT 24
Peak memory 195160 kb
Host smart-7998a0f9-380d-4f7b-83c3-844fda21a3d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879319979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.2879319979
Directory /workspace/46.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.uart_intr_test.3781206958
Short name T1162
Test name
Test status
Simulation time 65820225 ps
CPU time 0.55 seconds
Started Jun 09 12:35:49 PM PDT 24
Finished Jun 09 12:35:50 PM PDT 24
Peak memory 195064 kb
Host smart-1874ca4d-c87b-4e75-9f20-bf8adb3ae411
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781206958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.3781206958
Directory /workspace/47.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.uart_intr_test.282256910
Short name T1102
Test name
Test status
Simulation time 13728632 ps
CPU time 0.6 seconds
Started Jun 09 12:36:09 PM PDT 24
Finished Jun 09 12:36:10 PM PDT 24
Peak memory 195156 kb
Host smart-917f6d69-28a0-458b-a4b1-6905660ef908
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282256910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.282256910
Directory /workspace/48.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.uart_intr_test.460286604
Short name T1174
Test name
Test status
Simulation time 14404082 ps
CPU time 0.55 seconds
Started Jun 09 12:35:56 PM PDT 24
Finished Jun 09 12:35:58 PM PDT 24
Peak memory 195084 kb
Host smart-00bd042d-4ea3-4877-a95a-b932b541fa22
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460286604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.460286604
Directory /workspace/49.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.860564193
Short name T1218
Test name
Test status
Simulation time 20452314 ps
CPU time 0.7 seconds
Started Jun 09 12:35:54 PM PDT 24
Finished Jun 09 12:35:55 PM PDT 24
Peak memory 198428 kb
Host smart-f43049fa-4d95-48ca-be65-d6ea6b565cc5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860564193 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.860564193
Directory /workspace/5.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_rw.1639698636
Short name T1108
Test name
Test status
Simulation time 80993086 ps
CPU time 0.56 seconds
Started Jun 09 12:35:57 PM PDT 24
Finished Jun 09 12:35:59 PM PDT 24
Peak memory 196076 kb
Host smart-0e26b97e-8286-474d-bf31-12783f552e01
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639698636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.1639698636
Directory /workspace/5.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.uart_intr_test.2274561515
Short name T1211
Test name
Test status
Simulation time 34430848 ps
CPU time 0.56 seconds
Started Jun 09 12:35:51 PM PDT 24
Finished Jun 09 12:35:52 PM PDT 24
Peak memory 195076 kb
Host smart-30daa80a-ecd6-42da-9835-ff242032b01b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274561515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.2274561515
Directory /workspace/5.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.2603392276
Short name T79
Test name
Test status
Simulation time 90015494 ps
CPU time 0.72 seconds
Started Jun 09 12:35:48 PM PDT 24
Finished Jun 09 12:35:49 PM PDT 24
Peak memory 198256 kb
Host smart-1379b7cd-6c94-4b98-a49a-0ea609d9f35e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603392276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr
_outstanding.2603392276
Directory /workspace/5.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_errors.1502877900
Short name T1094
Test name
Test status
Simulation time 68233937 ps
CPU time 1.03 seconds
Started Jun 09 12:35:56 PM PDT 24
Finished Jun 09 12:35:57 PM PDT 24
Peak memory 200560 kb
Host smart-316112ec-109d-43bd-a342-e65da0ba2bdb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502877900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.1502877900
Directory /workspace/5.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.3831490634
Short name T97
Test name
Test status
Simulation time 129336222 ps
CPU time 1.33 seconds
Started Jun 09 12:36:15 PM PDT 24
Finished Jun 09 12:36:17 PM PDT 24
Peak memory 200128 kb
Host smart-582305bf-2ef4-4f5c-84c8-accb3178ff7d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831490634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.3831490634
Directory /workspace/5.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.3943928061
Short name T1098
Test name
Test status
Simulation time 51105686 ps
CPU time 0.76 seconds
Started Jun 09 12:35:49 PM PDT 24
Finished Jun 09 12:35:51 PM PDT 24
Peak memory 200532 kb
Host smart-bd9dbe62-2be9-41ac-bdce-bcd143565846
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943928061 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.3943928061
Directory /workspace/6.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_rw.1258152486
Short name T1164
Test name
Test status
Simulation time 34456467 ps
CPU time 0.58 seconds
Started Jun 09 12:35:59 PM PDT 24
Finished Jun 09 12:36:01 PM PDT 24
Peak memory 196028 kb
Host smart-0977ae74-0875-4e65-8de8-1a6f142df4f4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258152486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.1258152486
Directory /workspace/6.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.uart_intr_test.272230793
Short name T1113
Test name
Test status
Simulation time 15607869 ps
CPU time 0.6 seconds
Started Jun 09 12:35:55 PM PDT 24
Finished Jun 09 12:35:56 PM PDT 24
Peak memory 195148 kb
Host smart-83c51c27-9893-4277-96e2-c056afa827db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272230793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.272230793
Directory /workspace/6.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.2017074778
Short name T1217
Test name
Test status
Simulation time 50938749 ps
CPU time 0.65 seconds
Started Jun 09 12:35:58 PM PDT 24
Finished Jun 09 12:36:00 PM PDT 24
Peak memory 196392 kb
Host smart-28ca81bf-5095-40fd-9c2c-95018b31a2b2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017074778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr
_outstanding.2017074778
Directory /workspace/6.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_errors.1820146954
Short name T1198
Test name
Test status
Simulation time 49600263 ps
CPU time 1.27 seconds
Started Jun 09 12:35:49 PM PDT 24
Finished Jun 09 12:35:51 PM PDT 24
Peak memory 200764 kb
Host smart-d5f4f46c-d059-4d6a-9ab0-300d965fe1d0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820146954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.1820146954
Directory /workspace/6.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.2105780507
Short name T92
Test name
Test status
Simulation time 53867646 ps
CPU time 0.95 seconds
Started Jun 09 12:35:44 PM PDT 24
Finished Jun 09 12:35:45 PM PDT 24
Peak memory 199552 kb
Host smart-980c2d8d-406a-4a68-97d6-30723fc94b7f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105780507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.2105780507
Directory /workspace/6.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.327361876
Short name T1203
Test name
Test status
Simulation time 45577315 ps
CPU time 0.74 seconds
Started Jun 09 12:35:47 PM PDT 24
Finished Jun 09 12:35:49 PM PDT 24
Peak memory 199604 kb
Host smart-67c8e257-b131-42a6-81b5-32c4904b1005
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327361876 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.327361876
Directory /workspace/7.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_rw.900852202
Short name T85
Test name
Test status
Simulation time 43251411 ps
CPU time 0.57 seconds
Started Jun 09 12:35:59 PM PDT 24
Finished Jun 09 12:36:01 PM PDT 24
Peak memory 196080 kb
Host smart-5edf5d79-473e-4690-8b69-8aa86465e76a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900852202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.900852202
Directory /workspace/7.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.uart_intr_test.836434707
Short name T1177
Test name
Test status
Simulation time 13835749 ps
CPU time 0.56 seconds
Started Jun 09 12:35:51 PM PDT 24
Finished Jun 09 12:35:52 PM PDT 24
Peak memory 195092 kb
Host smart-76f82c8b-506e-45bb-9f69-4d7b59f97e91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836434707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.836434707
Directory /workspace/7.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.629565948
Short name T1160
Test name
Test status
Simulation time 114309148 ps
CPU time 0.65 seconds
Started Jun 09 12:35:56 PM PDT 24
Finished Jun 09 12:35:58 PM PDT 24
Peak memory 197180 kb
Host smart-cbfe8f76-1d8f-4115-81b2-4469c4767935
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629565948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr_
outstanding.629565948
Directory /workspace/7.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_errors.2257222790
Short name T1107
Test name
Test status
Simulation time 25927269 ps
CPU time 1.19 seconds
Started Jun 09 12:35:44 PM PDT 24
Finished Jun 09 12:35:46 PM PDT 24
Peak memory 200728 kb
Host smart-047dbc09-b310-4035-bbd9-c34e8dad24a2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257222790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.2257222790
Directory /workspace/7.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.1158138390
Short name T94
Test name
Test status
Simulation time 82767802 ps
CPU time 1.29 seconds
Started Jun 09 12:35:59 PM PDT 24
Finished Jun 09 12:36:02 PM PDT 24
Peak memory 200040 kb
Host smart-64309757-288c-4619-a2ff-8910eb7fece1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158138390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.1158138390
Directory /workspace/7.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.1859130590
Short name T1179
Test name
Test status
Simulation time 13882216 ps
CPU time 0.63 seconds
Started Jun 09 12:35:51 PM PDT 24
Finished Jun 09 12:35:52 PM PDT 24
Peak memory 197948 kb
Host smart-c1468afe-ea5f-40a2-9a03-5669c803ccf0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859130590 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.1859130590
Directory /workspace/8.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_rw.1534745466
Short name T1128
Test name
Test status
Simulation time 14921974 ps
CPU time 0.6 seconds
Started Jun 09 12:35:59 PM PDT 24
Finished Jun 09 12:36:01 PM PDT 24
Peak memory 196180 kb
Host smart-e16d01f1-2296-4226-847c-811301e9e120
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534745466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.1534745466
Directory /workspace/8.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.uart_intr_test.1027879969
Short name T1122
Test name
Test status
Simulation time 24192252 ps
CPU time 0.63 seconds
Started Jun 09 12:36:01 PM PDT 24
Finished Jun 09 12:36:02 PM PDT 24
Peak memory 195064 kb
Host smart-4509a06c-9140-4900-872c-9394e36b4077
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027879969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.1027879969
Directory /workspace/8.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.2852412150
Short name T81
Test name
Test status
Simulation time 16677609 ps
CPU time 0.7 seconds
Started Jun 09 12:35:48 PM PDT 24
Finished Jun 09 12:35:49 PM PDT 24
Peak memory 197596 kb
Host smart-9cdc9444-44e6-47b7-8ad5-72b8f684f3aa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852412150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr
_outstanding.2852412150
Directory /workspace/8.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_errors.211917005
Short name T1194
Test name
Test status
Simulation time 59479189 ps
CPU time 1.33 seconds
Started Jun 09 12:35:50 PM PDT 24
Finished Jun 09 12:35:53 PM PDT 24
Peak memory 200772 kb
Host smart-0e8bef87-95f9-4003-b19f-c94d7207dee9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211917005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.211917005
Directory /workspace/8.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.2705872982
Short name T1112
Test name
Test status
Simulation time 178818812 ps
CPU time 0.93 seconds
Started Jun 09 12:35:44 PM PDT 24
Finished Jun 09 12:35:46 PM PDT 24
Peak memory 199836 kb
Host smart-7c745508-205b-4ae0-bed1-f07c000247a1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705872982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.2705872982
Directory /workspace/8.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.1952527348
Short name T1111
Test name
Test status
Simulation time 37292340 ps
CPU time 0.94 seconds
Started Jun 09 12:35:57 PM PDT 24
Finished Jun 09 12:35:59 PM PDT 24
Peak memory 200568 kb
Host smart-f1cb6dbf-ac14-4181-8f53-ab359cb4b980
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952527348 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.1952527348
Directory /workspace/9.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_rw.3704058515
Short name T65
Test name
Test status
Simulation time 49093597 ps
CPU time 0.68 seconds
Started Jun 09 12:35:50 PM PDT 24
Finished Jun 09 12:35:51 PM PDT 24
Peak memory 196140 kb
Host smart-84ddea9f-d053-45a8-bc35-ff647ed46421
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704058515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.3704058515
Directory /workspace/9.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.uart_intr_test.100843402
Short name T1206
Test name
Test status
Simulation time 45339495 ps
CPU time 0.59 seconds
Started Jun 09 12:35:56 PM PDT 24
Finished Jun 09 12:35:58 PM PDT 24
Peak memory 195144 kb
Host smart-fbc86416-4be1-44eb-811b-36e2e8fcec9b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100843402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.100843402
Directory /workspace/9.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.1388214763
Short name T83
Test name
Test status
Simulation time 58328243 ps
CPU time 0.65 seconds
Started Jun 09 12:35:47 PM PDT 24
Finished Jun 09 12:35:48 PM PDT 24
Peak memory 197292 kb
Host smart-f16a6425-fbec-4432-9b8e-fb388e53b658
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388214763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr
_outstanding.1388214763
Directory /workspace/9.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_errors.2104280016
Short name T1191
Test name
Test status
Simulation time 36495050 ps
CPU time 1.6 seconds
Started Jun 09 12:35:47 PM PDT 24
Finished Jun 09 12:35:49 PM PDT 24
Peak memory 200780 kb
Host smart-cf8fb8d1-9c15-4407-900f-0e7b21b4b18d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104280016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.2104280016
Directory /workspace/9.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.2475565656
Short name T125
Test name
Test status
Simulation time 185866454 ps
CPU time 0.89 seconds
Started Jun 09 12:35:56 PM PDT 24
Finished Jun 09 12:35:58 PM PDT 24
Peak memory 199376 kb
Host smart-67882ae6-6511-46a0-8456-1adcc7de1e5c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475565656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.2475565656
Directory /workspace/9.uart_tl_intg_err/latest

Test location /workspace/coverage/default/0.uart_fifo_full.2257742681
Short name T72
Test name
Test status
Simulation time 33717757811 ps
CPU time 32.23 seconds
Started Jun 09 02:12:42 PM PDT 24
Finished Jun 09 02:13:14 PM PDT 24
Peak memory 200388 kb
Host smart-941f3fd5-02c8-4605-8d8a-15c241b5b570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257742681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.2257742681
Directory /workspace/0.uart_fifo_full/latest

Test location /workspace/coverage/default/0.uart_fifo_overflow.4087435279
Short name T291
Test name
Test status
Simulation time 74520070404 ps
CPU time 115.45 seconds
Started Jun 09 02:12:41 PM PDT 24
Finished Jun 09 02:14:37 PM PDT 24
Peak memory 200344 kb
Host smart-99f6aa05-350c-4af8-b6a0-2ba78c847b7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087435279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.4087435279
Directory /workspace/0.uart_fifo_overflow/latest

Test location /workspace/coverage/default/0.uart_intr.3595584658
Short name T656
Test name
Test status
Simulation time 1640367185 ps
CPU time 0.79 seconds
Started Jun 09 02:12:40 PM PDT 24
Finished Jun 09 02:12:41 PM PDT 24
Peak memory 195984 kb
Host smart-b25a83c7-b196-4084-8172-4f04822898e8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595584658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.3595584658
Directory /workspace/0.uart_intr/latest

Test location /workspace/coverage/default/0.uart_loopback.2060517958
Short name T904
Test name
Test status
Simulation time 8799480932 ps
CPU time 5.3 seconds
Started Jun 09 02:12:46 PM PDT 24
Finished Jun 09 02:12:52 PM PDT 24
Peak memory 198992 kb
Host smart-9595cbc7-1e3e-47f1-8281-b3a2b03218bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060517958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_loopback.2060517958
Directory /workspace/0.uart_loopback/latest

Test location /workspace/coverage/default/0.uart_perf.3384460068
Short name T848
Test name
Test status
Simulation time 14785594394 ps
CPU time 818.82 seconds
Started Jun 09 02:12:46 PM PDT 24
Finished Jun 09 02:26:25 PM PDT 24
Peak memory 200384 kb
Host smart-907072e3-3673-4500-a329-bc90a3c076ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3384460068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.3384460068
Directory /workspace/0.uart_perf/latest

Test location /workspace/coverage/default/0.uart_rx_oversample.1703610047
Short name T919
Test name
Test status
Simulation time 7331809815 ps
CPU time 62.3 seconds
Started Jun 09 02:12:41 PM PDT 24
Finished Jun 09 02:13:43 PM PDT 24
Peak memory 199520 kb
Host smart-8d9a52ab-be64-42cc-ab99-9f8b205cd7a7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1703610047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.1703610047
Directory /workspace/0.uart_rx_oversample/latest

Test location /workspace/coverage/default/0.uart_rx_parity_err.1299082902
Short name T723
Test name
Test status
Simulation time 52547369156 ps
CPU time 45.65 seconds
Started Jun 09 02:12:47 PM PDT 24
Finished Jun 09 02:13:33 PM PDT 24
Peak memory 199372 kb
Host smart-e373de05-c936-4a1d-b10e-2dd32490e8e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299082902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.1299082902
Directory /workspace/0.uart_rx_parity_err/latest

Test location /workspace/coverage/default/0.uart_rx_start_bit_filter.2513484998
Short name T917
Test name
Test status
Simulation time 3601311866 ps
CPU time 3.82 seconds
Started Jun 09 02:12:45 PM PDT 24
Finished Jun 09 02:12:49 PM PDT 24
Peak memory 196404 kb
Host smart-04f2f68e-8db0-4835-8ee5-a39a9f06ae7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513484998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.2513484998
Directory /workspace/0.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/0.uart_sec_cm.209715825
Short name T28
Test name
Test status
Simulation time 228006523 ps
CPU time 0.76 seconds
Started Jun 09 02:12:51 PM PDT 24
Finished Jun 09 02:12:52 PM PDT 24
Peak memory 218728 kb
Host smart-c5239ffd-9cfc-426c-99fa-ab001184576c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209715825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.209715825
Directory /workspace/0.uart_sec_cm/latest

Test location /workspace/coverage/default/0.uart_smoke.1521380324
Short name T804
Test name
Test status
Simulation time 5388952261 ps
CPU time 8.31 seconds
Started Jun 09 02:12:36 PM PDT 24
Finished Jun 09 02:12:44 PM PDT 24
Peak memory 199596 kb
Host smart-f94bfa3c-3394-4623-8d2b-111efe9f629f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521380324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_smoke.1521380324
Directory /workspace/0.uart_smoke/latest

Test location /workspace/coverage/default/0.uart_stress_all_with_rand_reset.1978347758
Short name T740
Test name
Test status
Simulation time 55901544253 ps
CPU time 168.68 seconds
Started Jun 09 02:12:52 PM PDT 24
Finished Jun 09 02:15:41 PM PDT 24
Peak memory 208768 kb
Host smart-6c743b8a-2318-441d-9490-7bdf8d0de9c9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978347758 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.uart_stress_all_with_rand_reset.1978347758
Directory /workspace/0.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.uart_tx_ovrd.1263790213
Short name T387
Test name
Test status
Simulation time 794516139 ps
CPU time 2.66 seconds
Started Jun 09 02:12:47 PM PDT 24
Finished Jun 09 02:12:50 PM PDT 24
Peak memory 199028 kb
Host smart-a64b20cf-3061-41e7-9eb2-fafe7749f0b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263790213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.1263790213
Directory /workspace/0.uart_tx_ovrd/latest

Test location /workspace/coverage/default/0.uart_tx_rx.3248958380
Short name T465
Test name
Test status
Simulation time 49794917821 ps
CPU time 17.71 seconds
Started Jun 09 02:12:35 PM PDT 24
Finished Jun 09 02:12:53 PM PDT 24
Peak memory 200288 kb
Host smart-435ca504-d17c-4efe-a7d8-061b1bb56517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248958380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.3248958380
Directory /workspace/0.uart_tx_rx/latest

Test location /workspace/coverage/default/1.uart_alert_test.1034280072
Short name T693
Test name
Test status
Simulation time 37581274 ps
CPU time 0.58 seconds
Started Jun 09 02:13:07 PM PDT 24
Finished Jun 09 02:13:07 PM PDT 24
Peak memory 195212 kb
Host smart-eaccd106-5fd7-43aa-9812-6bcc21dacbd1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034280072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.1034280072
Directory /workspace/1.uart_alert_test/latest

Test location /workspace/coverage/default/1.uart_fifo_full.924371513
Short name T405
Test name
Test status
Simulation time 16527285703 ps
CPU time 25.98 seconds
Started Jun 09 02:12:55 PM PDT 24
Finished Jun 09 02:13:21 PM PDT 24
Peak memory 200192 kb
Host smart-d6ad6409-64a9-46c9-b09f-ce8b76c45b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924371513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.924371513
Directory /workspace/1.uart_fifo_full/latest

Test location /workspace/coverage/default/1.uart_fifo_overflow.2122147520
Short name T462
Test name
Test status
Simulation time 19575709186 ps
CPU time 39.07 seconds
Started Jun 09 02:12:55 PM PDT 24
Finished Jun 09 02:13:34 PM PDT 24
Peak memory 200576 kb
Host smart-fb199cb6-25df-4140-968a-8ad28cee36e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122147520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.2122147520
Directory /workspace/1.uart_fifo_overflow/latest

Test location /workspace/coverage/default/1.uart_intr.1325675729
Short name T1059
Test name
Test status
Simulation time 35574236543 ps
CPU time 60.47 seconds
Started Jun 09 02:12:58 PM PDT 24
Finished Jun 09 02:13:59 PM PDT 24
Peak memory 200384 kb
Host smart-2f1642a8-bbc7-4137-9718-16341cc35038
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325675729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.1325675729
Directory /workspace/1.uart_intr/latest

Test location /workspace/coverage/default/1.uart_long_xfer_wo_dly.3021319622
Short name T429
Test name
Test status
Simulation time 154448760163 ps
CPU time 191.81 seconds
Started Jun 09 02:13:02 PM PDT 24
Finished Jun 09 02:16:14 PM PDT 24
Peak memory 200248 kb
Host smart-2c51abeb-36ff-4930-8572-1e718d7a2152
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3021319622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.3021319622
Directory /workspace/1.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/1.uart_loopback.980375209
Short name T767
Test name
Test status
Simulation time 2126097447 ps
CPU time 5.3 seconds
Started Jun 09 02:13:09 PM PDT 24
Finished Jun 09 02:13:14 PM PDT 24
Peak memory 198832 kb
Host smart-62ea6267-37e0-440e-809c-0b88a6440960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980375209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_loopback.980375209
Directory /workspace/1.uart_loopback/latest

Test location /workspace/coverage/default/1.uart_rx_oversample.1955292623
Short name T530
Test name
Test status
Simulation time 1479424076 ps
CPU time 2.84 seconds
Started Jun 09 02:12:54 PM PDT 24
Finished Jun 09 02:12:57 PM PDT 24
Peak memory 198160 kb
Host smart-a95c63a7-cb67-4375-a327-e10ce05239f8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1955292623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.1955292623
Directory /workspace/1.uart_rx_oversample/latest

Test location /workspace/coverage/default/1.uart_rx_parity_err.1963973193
Short name T571
Test name
Test status
Simulation time 6760605593 ps
CPU time 4.07 seconds
Started Jun 09 02:12:59 PM PDT 24
Finished Jun 09 02:13:04 PM PDT 24
Peak memory 199628 kb
Host smart-0bc3e105-7eaf-4011-82c6-2e54805c4a6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963973193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.1963973193
Directory /workspace/1.uart_rx_parity_err/latest

Test location /workspace/coverage/default/1.uart_rx_start_bit_filter.1664132213
Short name T463
Test name
Test status
Simulation time 5753613238 ps
CPU time 3.01 seconds
Started Jun 09 02:12:59 PM PDT 24
Finished Jun 09 02:13:03 PM PDT 24
Peak memory 196668 kb
Host smart-5c442b8b-021e-41eb-9dd0-080f707cafc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664132213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.1664132213
Directory /workspace/1.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/1.uart_smoke.3826216835
Short name T814
Test name
Test status
Simulation time 477971636 ps
CPU time 1.65 seconds
Started Jun 09 02:12:50 PM PDT 24
Finished Jun 09 02:12:52 PM PDT 24
Peak memory 199412 kb
Host smart-ca1411fe-3f4b-44d2-be69-57d8387cc27a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826216835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_smoke.3826216835
Directory /workspace/1.uart_smoke/latest

Test location /workspace/coverage/default/1.uart_stress_all_with_rand_reset.465902972
Short name T121
Test name
Test status
Simulation time 66697938781 ps
CPU time 348.11 seconds
Started Jun 09 02:12:58 PM PDT 24
Finished Jun 09 02:18:46 PM PDT 24
Peak memory 216800 kb
Host smart-7118f767-1f7a-470a-94e3-13e744f2e989
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465902972 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 1.uart_stress_all_with_rand_reset.465902972
Directory /workspace/1.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.uart_tx_ovrd.4026299729
Short name T285
Test name
Test status
Simulation time 897319706 ps
CPU time 2.09 seconds
Started Jun 09 02:13:00 PM PDT 24
Finished Jun 09 02:13:03 PM PDT 24
Peak memory 198992 kb
Host smart-ce8bcad0-8bfc-4ff7-9339-826723250d02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026299729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.4026299729
Directory /workspace/1.uart_tx_ovrd/latest

Test location /workspace/coverage/default/1.uart_tx_rx.3407676111
Short name T432
Test name
Test status
Simulation time 26547819506 ps
CPU time 12.91 seconds
Started Jun 09 02:12:50 PM PDT 24
Finished Jun 09 02:13:03 PM PDT 24
Peak memory 200368 kb
Host smart-4cefe29c-75eb-48f6-8123-b05ab18162a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407676111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.3407676111
Directory /workspace/1.uart_tx_rx/latest

Test location /workspace/coverage/default/10.uart_alert_test.804605433
Short name T635
Test name
Test status
Simulation time 78811901 ps
CPU time 0.55 seconds
Started Jun 09 02:14:34 PM PDT 24
Finished Jun 09 02:14:35 PM PDT 24
Peak memory 195188 kb
Host smart-1f9ff921-a940-40bf-b411-b1b893a7db4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804605433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.804605433
Directory /workspace/10.uart_alert_test/latest

Test location /workspace/coverage/default/10.uart_fifo_overflow.4122819436
Short name T150
Test name
Test status
Simulation time 116767215444 ps
CPU time 98.82 seconds
Started Jun 09 02:14:25 PM PDT 24
Finished Jun 09 02:16:04 PM PDT 24
Peak memory 200400 kb
Host smart-eff4d515-bec3-436d-b916-ebd621d44317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122819436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.4122819436
Directory /workspace/10.uart_fifo_overflow/latest

Test location /workspace/coverage/default/10.uart_intr.641214452
Short name T115
Test name
Test status
Simulation time 34381860899 ps
CPU time 45.57 seconds
Started Jun 09 02:14:27 PM PDT 24
Finished Jun 09 02:15:13 PM PDT 24
Peak memory 199900 kb
Host smart-4bef0ae3-4aac-43c2-888a-ecc8edf29d9e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641214452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.641214452
Directory /workspace/10.uart_intr/latest

Test location /workspace/coverage/default/10.uart_long_xfer_wo_dly.1180448098
Short name T1029
Test name
Test status
Simulation time 73645747035 ps
CPU time 167.14 seconds
Started Jun 09 02:14:32 PM PDT 24
Finished Jun 09 02:17:19 PM PDT 24
Peak memory 200324 kb
Host smart-87ccfa1a-98e6-4111-a97c-436bf6657c7a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1180448098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.1180448098
Directory /workspace/10.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/10.uart_loopback.1843960158
Short name T629
Test name
Test status
Simulation time 10057792944 ps
CPU time 18.8 seconds
Started Jun 09 02:14:35 PM PDT 24
Finished Jun 09 02:14:54 PM PDT 24
Peak memory 200240 kb
Host smart-fc597cdd-c1e0-40e6-a06a-6a16966d6285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843960158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_loopback.1843960158
Directory /workspace/10.uart_loopback/latest

Test location /workspace/coverage/default/10.uart_noise_filter.143513629
Short name T913
Test name
Test status
Simulation time 240502142 ps
CPU time 0.93 seconds
Started Jun 09 02:14:35 PM PDT 24
Finished Jun 09 02:14:36 PM PDT 24
Peak memory 198432 kb
Host smart-dca84a55-82dc-4605-b2ac-b1d2c978db90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143513629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_noise_filter.143513629
Directory /workspace/10.uart_noise_filter/latest

Test location /workspace/coverage/default/10.uart_perf.2905421750
Short name T668
Test name
Test status
Simulation time 3942268820 ps
CPU time 177.98 seconds
Started Jun 09 02:14:32 PM PDT 24
Finished Jun 09 02:17:30 PM PDT 24
Peak memory 200300 kb
Host smart-91f30d54-9932-4c54-8c09-3f64ecaaca13
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2905421750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.2905421750
Directory /workspace/10.uart_perf/latest

Test location /workspace/coverage/default/10.uart_rx_oversample.3658679917
Short name T978
Test name
Test status
Simulation time 1815428816 ps
CPU time 2.67 seconds
Started Jun 09 02:14:25 PM PDT 24
Finished Jun 09 02:14:28 PM PDT 24
Peak memory 198352 kb
Host smart-3286dcf4-53bb-49f1-a967-8f332d8e3589
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3658679917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.3658679917
Directory /workspace/10.uart_rx_oversample/latest

Test location /workspace/coverage/default/10.uart_rx_parity_err.2517261920
Short name T305
Test name
Test status
Simulation time 53779177103 ps
CPU time 22.4 seconds
Started Jun 09 02:14:34 PM PDT 24
Finished Jun 09 02:14:57 PM PDT 24
Peak memory 200344 kb
Host smart-b0e70d87-675d-4cc3-a2ea-98f5990caf59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517261920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.2517261920
Directory /workspace/10.uart_rx_parity_err/latest

Test location /workspace/coverage/default/10.uart_rx_start_bit_filter.2636506499
Short name T438
Test name
Test status
Simulation time 6258257590 ps
CPU time 8.67 seconds
Started Jun 09 02:14:31 PM PDT 24
Finished Jun 09 02:14:40 PM PDT 24
Peak memory 196684 kb
Host smart-7c8bb437-740b-488f-b967-770ef3429c13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636506499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.2636506499
Directory /workspace/10.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/10.uart_smoke.1568298393
Short name T803
Test name
Test status
Simulation time 976482512 ps
CPU time 2.03 seconds
Started Jun 09 02:14:21 PM PDT 24
Finished Jun 09 02:14:24 PM PDT 24
Peak memory 200000 kb
Host smart-064750db-1d2e-4274-a5eb-85114c5b44e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568298393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_smoke.1568298393
Directory /workspace/10.uart_smoke/latest

Test location /workspace/coverage/default/10.uart_stress_all_with_rand_reset.1713859281
Short name T1043
Test name
Test status
Simulation time 12373709486 ps
CPU time 154.22 seconds
Started Jun 09 02:14:30 PM PDT 24
Finished Jun 09 02:17:04 PM PDT 24
Peak memory 216208 kb
Host smart-cc97a7ce-f55c-4fb0-ac8e-9468edff49d8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713859281 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 10.uart_stress_all_with_rand_reset.1713859281
Directory /workspace/10.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.uart_tx_ovrd.467233662
Short name T537
Test name
Test status
Simulation time 7173368150 ps
CPU time 15.4 seconds
Started Jun 09 02:14:31 PM PDT 24
Finished Jun 09 02:14:46 PM PDT 24
Peak memory 200176 kb
Host smart-2035044a-4bd6-47c7-8f10-edb80c13db40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467233662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.467233662
Directory /workspace/10.uart_tx_ovrd/latest

Test location /workspace/coverage/default/10.uart_tx_rx.13496444
Short name T877
Test name
Test status
Simulation time 43516628369 ps
CPU time 72.33 seconds
Started Jun 09 02:14:25 PM PDT 24
Finished Jun 09 02:15:37 PM PDT 24
Peak memory 200364 kb
Host smart-8e688946-3242-4c94-8e2b-f6bb2df39eaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13496444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.13496444
Directory /workspace/10.uart_tx_rx/latest

Test location /workspace/coverage/default/100.uart_fifo_reset.3664305415
Short name T539
Test name
Test status
Simulation time 113023200891 ps
CPU time 109.42 seconds
Started Jun 09 02:19:56 PM PDT 24
Finished Jun 09 02:21:45 PM PDT 24
Peak memory 200336 kb
Host smart-a28eab33-3ed5-46da-b10f-ffdbc9b5af1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664305415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.3664305415
Directory /workspace/100.uart_fifo_reset/latest

Test location /workspace/coverage/default/101.uart_fifo_reset.3390238542
Short name T569
Test name
Test status
Simulation time 183981156388 ps
CPU time 26.62 seconds
Started Jun 09 02:19:57 PM PDT 24
Finished Jun 09 02:20:24 PM PDT 24
Peak memory 200360 kb
Host smart-ea13c5d3-1472-4c26-a320-3b6b75279650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390238542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.3390238542
Directory /workspace/101.uart_fifo_reset/latest

Test location /workspace/coverage/default/102.uart_fifo_reset.344516667
Short name T642
Test name
Test status
Simulation time 84240190047 ps
CPU time 33.49 seconds
Started Jun 09 02:19:54 PM PDT 24
Finished Jun 09 02:20:28 PM PDT 24
Peak memory 200316 kb
Host smart-cf641b1a-89b6-41c0-b808-ae0a2f1b1fe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344516667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.344516667
Directory /workspace/102.uart_fifo_reset/latest

Test location /workspace/coverage/default/104.uart_fifo_reset.3460424243
Short name T210
Test name
Test status
Simulation time 16293686068 ps
CPU time 52.37 seconds
Started Jun 09 02:19:57 PM PDT 24
Finished Jun 09 02:20:49 PM PDT 24
Peak memory 200364 kb
Host smart-7ed2c7a7-6b96-44fb-90f1-97b7d900e4b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460424243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.3460424243
Directory /workspace/104.uart_fifo_reset/latest

Test location /workspace/coverage/default/105.uart_fifo_reset.3837996581
Short name T847
Test name
Test status
Simulation time 167588619218 ps
CPU time 68.5 seconds
Started Jun 09 02:19:57 PM PDT 24
Finished Jun 09 02:21:06 PM PDT 24
Peak memory 200352 kb
Host smart-4eee5082-0e49-4175-8dd8-c1d23f4785e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837996581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.3837996581
Directory /workspace/105.uart_fifo_reset/latest

Test location /workspace/coverage/default/106.uart_fifo_reset.2561570493
Short name T868
Test name
Test status
Simulation time 194014040575 ps
CPU time 167.7 seconds
Started Jun 09 02:19:58 PM PDT 24
Finished Jun 09 02:22:46 PM PDT 24
Peak memory 200236 kb
Host smart-59523e32-1dcc-4c31-a7c1-34df571b68e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561570493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.2561570493
Directory /workspace/106.uart_fifo_reset/latest

Test location /workspace/coverage/default/107.uart_fifo_reset.964121389
Short name T760
Test name
Test status
Simulation time 119152461926 ps
CPU time 55.33 seconds
Started Jun 09 02:19:55 PM PDT 24
Finished Jun 09 02:20:51 PM PDT 24
Peak memory 200336 kb
Host smart-d4ad17b0-13bd-4176-8ab8-f2c317b0e421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964121389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.964121389
Directory /workspace/107.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_alert_test.2266761006
Short name T742
Test name
Test status
Simulation time 21817757 ps
CPU time 0.54 seconds
Started Jun 09 02:14:47 PM PDT 24
Finished Jun 09 02:14:47 PM PDT 24
Peak memory 195756 kb
Host smart-85a5f0e6-c3e1-4136-95ee-be1efb1cb9ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266761006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.2266761006
Directory /workspace/11.uart_alert_test/latest

Test location /workspace/coverage/default/11.uart_fifo_full.1956933275
Short name T1001
Test name
Test status
Simulation time 92892807383 ps
CPU time 87.29 seconds
Started Jun 09 02:14:35 PM PDT 24
Finished Jun 09 02:16:03 PM PDT 24
Peak memory 200436 kb
Host smart-3b4bc6d8-904c-435d-a1fa-706472eed404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956933275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.1956933275
Directory /workspace/11.uart_fifo_full/latest

Test location /workspace/coverage/default/11.uart_fifo_overflow.3508553544
Short name T662
Test name
Test status
Simulation time 155234079053 ps
CPU time 58.26 seconds
Started Jun 09 02:14:35 PM PDT 24
Finished Jun 09 02:15:33 PM PDT 24
Peak memory 199432 kb
Host smart-4caa7459-319b-44a6-bacf-19f52343c3af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508553544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.3508553544
Directory /workspace/11.uart_fifo_overflow/latest

Test location /workspace/coverage/default/11.uart_fifo_reset.2680318698
Short name T598
Test name
Test status
Simulation time 165373965214 ps
CPU time 64.88 seconds
Started Jun 09 02:14:37 PM PDT 24
Finished Jun 09 02:15:42 PM PDT 24
Peak memory 200344 kb
Host smart-dd3fed4a-7882-42f5-87fa-4bff4c069c8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680318698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.2680318698
Directory /workspace/11.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_intr.2437207077
Short name T1021
Test name
Test status
Simulation time 54614445224 ps
CPU time 88.53 seconds
Started Jun 09 02:14:35 PM PDT 24
Finished Jun 09 02:16:04 PM PDT 24
Peak memory 200152 kb
Host smart-86203823-aa5f-42ad-a0d7-78a6deac9888
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437207077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.2437207077
Directory /workspace/11.uart_intr/latest

Test location /workspace/coverage/default/11.uart_long_xfer_wo_dly.2542884698
Short name T920
Test name
Test status
Simulation time 115391343708 ps
CPU time 119.46 seconds
Started Jun 09 02:14:46 PM PDT 24
Finished Jun 09 02:16:46 PM PDT 24
Peak memory 200320 kb
Host smart-ea711cdf-ffcc-4164-a9da-53c2fb535ad1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2542884698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.2542884698
Directory /workspace/11.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/11.uart_loopback.2298481386
Short name T505
Test name
Test status
Simulation time 9802305043 ps
CPU time 3.38 seconds
Started Jun 09 02:14:40 PM PDT 24
Finished Jun 09 02:14:43 PM PDT 24
Peak memory 200336 kb
Host smart-36a9cfc4-6568-4152-bf54-74aab7ba7faf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298481386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_loopback.2298481386
Directory /workspace/11.uart_loopback/latest

Test location /workspace/coverage/default/11.uart_perf.1069508869
Short name T517
Test name
Test status
Simulation time 8887018837 ps
CPU time 450.14 seconds
Started Jun 09 02:14:40 PM PDT 24
Finished Jun 09 02:22:10 PM PDT 24
Peak memory 200316 kb
Host smart-eccc090f-5f3d-43c6-89fe-1b12c3f262aa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1069508869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.1069508869
Directory /workspace/11.uart_perf/latest

Test location /workspace/coverage/default/11.uart_rx_oversample.2614540786
Short name T574
Test name
Test status
Simulation time 5242135488 ps
CPU time 38.42 seconds
Started Jun 09 02:14:37 PM PDT 24
Finished Jun 09 02:15:16 PM PDT 24
Peak memory 198576 kb
Host smart-86db11fb-3849-4674-ab20-2d116bd2f0f8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2614540786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.2614540786
Directory /workspace/11.uart_rx_oversample/latest

Test location /workspace/coverage/default/11.uart_rx_start_bit_filter.459182480
Short name T983
Test name
Test status
Simulation time 4182716611 ps
CPU time 1.98 seconds
Started Jun 09 02:14:41 PM PDT 24
Finished Jun 09 02:14:43 PM PDT 24
Peak memory 196820 kb
Host smart-85770e98-c5ed-4119-a282-093c09a50dfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459182480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.459182480
Directory /workspace/11.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/11.uart_smoke.448855242
Short name T452
Test name
Test status
Simulation time 954229476 ps
CPU time 1.8 seconds
Started Jun 09 02:14:36 PM PDT 24
Finished Jun 09 02:14:38 PM PDT 24
Peak memory 200084 kb
Host smart-01ab4b7b-eaf7-4b6c-b115-781671334c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448855242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_smoke.448855242
Directory /workspace/11.uart_smoke/latest

Test location /workspace/coverage/default/11.uart_stress_all.171755890
Short name T430
Test name
Test status
Simulation time 63977106717 ps
CPU time 75.75 seconds
Started Jun 09 02:14:50 PM PDT 24
Finished Jun 09 02:16:06 PM PDT 24
Peak memory 200352 kb
Host smart-9dab3533-a93d-43bc-8268-f4917b81c96c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171755890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.171755890
Directory /workspace/11.uart_stress_all/latest

Test location /workspace/coverage/default/11.uart_stress_all_with_rand_reset.3078257989
Short name T730
Test name
Test status
Simulation time 96255534791 ps
CPU time 1292.11 seconds
Started Jun 09 02:14:44 PM PDT 24
Finished Jun 09 02:36:17 PM PDT 24
Peak memory 225120 kb
Host smart-9bced207-648b-4ee5-99e4-c06ce33ae211
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078257989 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 11.uart_stress_all_with_rand_reset.3078257989
Directory /workspace/11.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.uart_tx_ovrd.861565467
Short name T296
Test name
Test status
Simulation time 858699935 ps
CPU time 1.44 seconds
Started Jun 09 02:14:40 PM PDT 24
Finished Jun 09 02:14:41 PM PDT 24
Peak memory 198612 kb
Host smart-6f18e29d-2708-4dd5-99be-37525d12ccb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861565467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.861565467
Directory /workspace/11.uart_tx_ovrd/latest

Test location /workspace/coverage/default/11.uart_tx_rx.3567312594
Short name T624
Test name
Test status
Simulation time 169926314119 ps
CPU time 36.36 seconds
Started Jun 09 02:14:37 PM PDT 24
Finished Jun 09 02:15:13 PM PDT 24
Peak memory 200348 kb
Host smart-9280054c-a977-4207-9713-36b38158a938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567312594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.3567312594
Directory /workspace/11.uart_tx_rx/latest

Test location /workspace/coverage/default/110.uart_fifo_reset.2395111689
Short name T875
Test name
Test status
Simulation time 197318581772 ps
CPU time 49.69 seconds
Started Jun 09 02:20:00 PM PDT 24
Finished Jun 09 02:20:50 PM PDT 24
Peak memory 200232 kb
Host smart-094bd158-fb77-4efa-8770-e8e89eec8a59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395111689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.2395111689
Directory /workspace/110.uart_fifo_reset/latest

Test location /workspace/coverage/default/111.uart_fifo_reset.4032958846
Short name T886
Test name
Test status
Simulation time 71975593012 ps
CPU time 22.52 seconds
Started Jun 09 02:20:01 PM PDT 24
Finished Jun 09 02:20:23 PM PDT 24
Peak memory 200308 kb
Host smart-e55e5601-0bf0-4af9-868c-99db766fa3b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032958846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.4032958846
Directory /workspace/111.uart_fifo_reset/latest

Test location /workspace/coverage/default/112.uart_fifo_reset.4272385
Short name T403
Test name
Test status
Simulation time 36001015376 ps
CPU time 13.82 seconds
Started Jun 09 02:20:02 PM PDT 24
Finished Jun 09 02:20:16 PM PDT 24
Peak memory 199128 kb
Host smart-25da9a7b-5bb1-4c01-a38f-344e61e3e9a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.4272385
Directory /workspace/112.uart_fifo_reset/latest

Test location /workspace/coverage/default/113.uart_fifo_reset.3621620693
Short name T184
Test name
Test status
Simulation time 128903094911 ps
CPU time 210.14 seconds
Started Jun 09 02:20:00 PM PDT 24
Finished Jun 09 02:23:31 PM PDT 24
Peak memory 200636 kb
Host smart-cddfd1d7-1cac-4a20-85e4-a97b87dde43f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621620693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.3621620693
Directory /workspace/113.uart_fifo_reset/latest

Test location /workspace/coverage/default/114.uart_fifo_reset.2778038803
Short name T835
Test name
Test status
Simulation time 126427581555 ps
CPU time 226.17 seconds
Started Jun 09 02:20:00 PM PDT 24
Finished Jun 09 02:23:46 PM PDT 24
Peak memory 200372 kb
Host smart-e2be1aea-68ae-4579-aa56-68b35c3ed5cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778038803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.2778038803
Directory /workspace/114.uart_fifo_reset/latest

Test location /workspace/coverage/default/115.uart_fifo_reset.1374565950
Short name T728
Test name
Test status
Simulation time 62186182681 ps
CPU time 101.19 seconds
Started Jun 09 02:20:02 PM PDT 24
Finished Jun 09 02:21:43 PM PDT 24
Peak memory 200320 kb
Host smart-4df795bf-7a43-4566-8fd7-6e7cbfda7671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374565950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.1374565950
Directory /workspace/115.uart_fifo_reset/latest

Test location /workspace/coverage/default/116.uart_fifo_reset.200797568
Short name T75
Test name
Test status
Simulation time 30140240266 ps
CPU time 16.55 seconds
Started Jun 09 02:20:01 PM PDT 24
Finished Jun 09 02:20:18 PM PDT 24
Peak memory 200336 kb
Host smart-51e3eb3e-df38-48f8-bc91-7f09a036b1c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200797568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.200797568
Directory /workspace/116.uart_fifo_reset/latest

Test location /workspace/coverage/default/117.uart_fifo_reset.1958647117
Short name T194
Test name
Test status
Simulation time 101084486820 ps
CPU time 49.95 seconds
Started Jun 09 02:19:59 PM PDT 24
Finished Jun 09 02:20:49 PM PDT 24
Peak memory 200588 kb
Host smart-b828e9fa-470e-4ac1-9228-340fa52fd89c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958647117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.1958647117
Directory /workspace/117.uart_fifo_reset/latest

Test location /workspace/coverage/default/118.uart_fifo_reset.2842634794
Short name T1000
Test name
Test status
Simulation time 47811692332 ps
CPU time 8.2 seconds
Started Jun 09 02:20:02 PM PDT 24
Finished Jun 09 02:20:11 PM PDT 24
Peak memory 200368 kb
Host smart-d7b41779-01e7-4d94-8e8b-a04ff6ae25e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842634794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.2842634794
Directory /workspace/118.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_alert_test.4189036347
Short name T384
Test name
Test status
Simulation time 14777119 ps
CPU time 0.56 seconds
Started Jun 09 02:14:56 PM PDT 24
Finished Jun 09 02:14:57 PM PDT 24
Peak memory 195948 kb
Host smart-953cd0db-6ae6-4238-a223-eeabcc3c3d46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189036347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.4189036347
Directory /workspace/12.uart_alert_test/latest

Test location /workspace/coverage/default/12.uart_fifo_full.3438525304
Short name T619
Test name
Test status
Simulation time 81805526476 ps
CPU time 29.67 seconds
Started Jun 09 02:14:46 PM PDT 24
Finished Jun 09 02:15:16 PM PDT 24
Peak memory 200388 kb
Host smart-167836c9-b924-49b3-8495-b30f5a08d682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438525304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.3438525304
Directory /workspace/12.uart_fifo_full/latest

Test location /workspace/coverage/default/12.uart_fifo_reset.1050317092
Short name T521
Test name
Test status
Simulation time 7658128179 ps
CPU time 10.74 seconds
Started Jun 09 02:14:49 PM PDT 24
Finished Jun 09 02:15:00 PM PDT 24
Peak memory 200420 kb
Host smart-53bec273-9ae6-47c2-9c9e-7f9adc066907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050317092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.1050317092
Directory /workspace/12.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_intr.3532162606
Short name T525
Test name
Test status
Simulation time 51812355221 ps
CPU time 56.17 seconds
Started Jun 09 02:14:52 PM PDT 24
Finished Jun 09 02:15:48 PM PDT 24
Peak memory 200292 kb
Host smart-073a467f-8e6a-4e1c-bbc5-d4a322d21227
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532162606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.3532162606
Directory /workspace/12.uart_intr/latest

Test location /workspace/coverage/default/12.uart_loopback.969982342
Short name T342
Test name
Test status
Simulation time 4508298164 ps
CPU time 2.69 seconds
Started Jun 09 02:14:51 PM PDT 24
Finished Jun 09 02:14:54 PM PDT 24
Peak memory 199420 kb
Host smart-95cdd241-0064-44c4-a0ba-13909e33d5b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969982342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_loopback.969982342
Directory /workspace/12.uart_loopback/latest

Test location /workspace/coverage/default/12.uart_noise_filter.2364463994
Short name T927
Test name
Test status
Simulation time 2772842133 ps
CPU time 5.23 seconds
Started Jun 09 02:14:52 PM PDT 24
Finished Jun 09 02:14:57 PM PDT 24
Peak memory 197784 kb
Host smart-ca3b6b36-c9c3-4ee6-aa90-382eb81a5960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364463994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_noise_filter.2364463994
Directory /workspace/12.uart_noise_filter/latest

Test location /workspace/coverage/default/12.uart_perf.3113748136
Short name T292
Test name
Test status
Simulation time 10623112650 ps
CPU time 137.6 seconds
Started Jun 09 02:14:50 PM PDT 24
Finished Jun 09 02:17:08 PM PDT 24
Peak memory 200388 kb
Host smart-19e6e33d-d2f2-4ebd-a980-ef4697deedc6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3113748136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.3113748136
Directory /workspace/12.uart_perf/latest

Test location /workspace/coverage/default/12.uart_rx_oversample.1513284707
Short name T846
Test name
Test status
Simulation time 4522027300 ps
CPU time 38.75 seconds
Started Jun 09 02:14:51 PM PDT 24
Finished Jun 09 02:15:30 PM PDT 24
Peak memory 199420 kb
Host smart-9fb4a8a4-4ede-439b-8823-a657b9dbbcc5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1513284707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.1513284707
Directory /workspace/12.uart_rx_oversample/latest

Test location /workspace/coverage/default/12.uart_rx_parity_err.4278706682
Short name T427
Test name
Test status
Simulation time 56489580863 ps
CPU time 51.55 seconds
Started Jun 09 02:14:51 PM PDT 24
Finished Jun 09 02:15:43 PM PDT 24
Peak memory 200384 kb
Host smart-324f49fd-b163-488a-9a03-0d34df687bd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278706682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.4278706682
Directory /workspace/12.uart_rx_parity_err/latest

Test location /workspace/coverage/default/12.uart_rx_start_bit_filter.1773593521
Short name T644
Test name
Test status
Simulation time 3162707903 ps
CPU time 3.13 seconds
Started Jun 09 02:14:49 PM PDT 24
Finished Jun 09 02:14:53 PM PDT 24
Peak memory 196600 kb
Host smart-ded3608c-f2b7-4782-8c72-f96ea29efbfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773593521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.1773593521
Directory /workspace/12.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/12.uart_smoke.3604811940
Short name T614
Test name
Test status
Simulation time 119415683 ps
CPU time 1.02 seconds
Started Jun 09 02:14:45 PM PDT 24
Finished Jun 09 02:14:46 PM PDT 24
Peak memory 198644 kb
Host smart-bf291a8a-a324-4926-82df-84ebdfe86f78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604811940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_smoke.3604811940
Directory /workspace/12.uart_smoke/latest

Test location /workspace/coverage/default/12.uart_stress_all.3394971516
Short name T567
Test name
Test status
Simulation time 100410987130 ps
CPU time 737.39 seconds
Started Jun 09 02:14:55 PM PDT 24
Finished Jun 09 02:27:13 PM PDT 24
Peak memory 200368 kb
Host smart-3e4314d9-935c-4228-9960-43761975f94f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394971516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.3394971516
Directory /workspace/12.uart_stress_all/latest

Test location /workspace/coverage/default/12.uart_stress_all_with_rand_reset.1293812770
Short name T865
Test name
Test status
Simulation time 331249730378 ps
CPU time 395.93 seconds
Started Jun 09 02:14:55 PM PDT 24
Finished Jun 09 02:21:31 PM PDT 24
Peak memory 216920 kb
Host smart-384140cf-1aeb-44c6-be3c-dd3ab99701f9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293812770 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 12.uart_stress_all_with_rand_reset.1293812770
Directory /workspace/12.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.uart_tx_ovrd.504336051
Short name T811
Test name
Test status
Simulation time 1244806038 ps
CPU time 4.5 seconds
Started Jun 09 02:14:50 PM PDT 24
Finished Jun 09 02:14:55 PM PDT 24
Peak memory 200220 kb
Host smart-0149afee-ebaa-49e1-8628-e10ea71e6b63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504336051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.504336051
Directory /workspace/12.uart_tx_ovrd/latest

Test location /workspace/coverage/default/12.uart_tx_rx.1521599336
Short name T616
Test name
Test status
Simulation time 86611393238 ps
CPU time 58.19 seconds
Started Jun 09 02:14:46 PM PDT 24
Finished Jun 09 02:15:44 PM PDT 24
Peak memory 200424 kb
Host smart-dfc053a5-74f1-4b4d-ada9-8de881866511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521599336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.1521599336
Directory /workspace/12.uart_tx_rx/latest

Test location /workspace/coverage/default/120.uart_fifo_reset.1533316123
Short name T283
Test name
Test status
Simulation time 103212648861 ps
CPU time 37.34 seconds
Started Jun 09 02:20:06 PM PDT 24
Finished Jun 09 02:20:43 PM PDT 24
Peak memory 200308 kb
Host smart-8151900d-a270-4b01-afc1-4c802955ec4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533316123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.1533316123
Directory /workspace/120.uart_fifo_reset/latest

Test location /workspace/coverage/default/121.uart_fifo_reset.2512995149
Short name T545
Test name
Test status
Simulation time 65045115664 ps
CPU time 140.84 seconds
Started Jun 09 02:20:04 PM PDT 24
Finished Jun 09 02:22:25 PM PDT 24
Peak memory 200300 kb
Host smart-a46cee6b-9f57-4c72-ad22-235bc539b10f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512995149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.2512995149
Directory /workspace/121.uart_fifo_reset/latest

Test location /workspace/coverage/default/122.uart_fifo_reset.2364815636
Short name T696
Test name
Test status
Simulation time 17144720265 ps
CPU time 13.83 seconds
Started Jun 09 02:20:07 PM PDT 24
Finished Jun 09 02:20:21 PM PDT 24
Peak memory 200300 kb
Host smart-7175ed1d-cb38-40fc-953f-81f4ac816a09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364815636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.2364815636
Directory /workspace/122.uart_fifo_reset/latest

Test location /workspace/coverage/default/123.uart_fifo_reset.774387446
Short name T422
Test name
Test status
Simulation time 43039428169 ps
CPU time 20.52 seconds
Started Jun 09 02:20:05 PM PDT 24
Finished Jun 09 02:20:26 PM PDT 24
Peak memory 200420 kb
Host smart-72c71f15-2f01-448b-94c1-c6c3f5ec4413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774387446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.774387446
Directory /workspace/123.uart_fifo_reset/latest

Test location /workspace/coverage/default/124.uart_fifo_reset.2091808734
Short name T203
Test name
Test status
Simulation time 92024009352 ps
CPU time 74.52 seconds
Started Jun 09 02:20:06 PM PDT 24
Finished Jun 09 02:21:21 PM PDT 24
Peak memory 200332 kb
Host smart-444ecdeb-bb19-49a0-a67b-3619edea6f25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091808734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.2091808734
Directory /workspace/124.uart_fifo_reset/latest

Test location /workspace/coverage/default/125.uart_fifo_reset.1789716203
Short name T335
Test name
Test status
Simulation time 35140250957 ps
CPU time 61 seconds
Started Jun 09 02:20:05 PM PDT 24
Finished Jun 09 02:21:06 PM PDT 24
Peak memory 200316 kb
Host smart-3708d2f6-d7fd-4455-9ab3-410d1e29ff0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789716203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.1789716203
Directory /workspace/125.uart_fifo_reset/latest

Test location /workspace/coverage/default/126.uart_fifo_reset.2116603024
Short name T415
Test name
Test status
Simulation time 20321053775 ps
CPU time 10.46 seconds
Started Jun 09 02:20:11 PM PDT 24
Finished Jun 09 02:20:22 PM PDT 24
Peak memory 200332 kb
Host smart-0091ce11-3b24-43ef-9144-5d92049cdbaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116603024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.2116603024
Directory /workspace/126.uart_fifo_reset/latest

Test location /workspace/coverage/default/127.uart_fifo_reset.2947332388
Short name T1076
Test name
Test status
Simulation time 98464332643 ps
CPU time 806.65 seconds
Started Jun 09 02:20:09 PM PDT 24
Finished Jun 09 02:33:36 PM PDT 24
Peak memory 200412 kb
Host smart-d19905cf-0531-48af-872b-a0cd4f21db34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947332388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.2947332388
Directory /workspace/127.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_alert_test.347516796
Short name T380
Test name
Test status
Simulation time 40127969 ps
CPU time 0.55 seconds
Started Jun 09 02:15:01 PM PDT 24
Finished Jun 09 02:15:01 PM PDT 24
Peak memory 196040 kb
Host smart-de1c6de1-34d1-448b-88da-1852780688ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347516796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.347516796
Directory /workspace/13.uart_alert_test/latest

Test location /workspace/coverage/default/13.uart_fifo_full.2133174166
Short name T989
Test name
Test status
Simulation time 28387053342 ps
CPU time 20.66 seconds
Started Jun 09 02:14:55 PM PDT 24
Finished Jun 09 02:15:16 PM PDT 24
Peak memory 200404 kb
Host smart-7f212cbd-f3f3-45ff-aa7e-240081c9a5a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133174166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.2133174166
Directory /workspace/13.uart_fifo_full/latest

Test location /workspace/coverage/default/13.uart_fifo_overflow.3802226405
Short name T169
Test name
Test status
Simulation time 124669727925 ps
CPU time 116.16 seconds
Started Jun 09 02:14:55 PM PDT 24
Finished Jun 09 02:16:52 PM PDT 24
Peak memory 200400 kb
Host smart-011509a9-3fec-4877-96f9-f189ed409788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802226405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.3802226405
Directory /workspace/13.uart_fifo_overflow/latest

Test location /workspace/coverage/default/13.uart_fifo_reset.1467802999
Short name T869
Test name
Test status
Simulation time 69759777868 ps
CPU time 49.86 seconds
Started Jun 09 02:14:57 PM PDT 24
Finished Jun 09 02:15:47 PM PDT 24
Peak memory 199972 kb
Host smart-ed1be061-89ab-410b-8d81-8a639471bccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467802999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.1467802999
Directory /workspace/13.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_long_xfer_wo_dly.3756114781
Short name T1061
Test name
Test status
Simulation time 60741008144 ps
CPU time 473.11 seconds
Started Jun 09 02:15:01 PM PDT 24
Finished Jun 09 02:22:54 PM PDT 24
Peak memory 200436 kb
Host smart-bb1b9248-a77d-49b9-ad60-2acb1e71af40
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3756114781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.3756114781
Directory /workspace/13.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/13.uart_loopback.555102860
Short name T908
Test name
Test status
Simulation time 4151550698 ps
CPU time 4.17 seconds
Started Jun 09 02:14:56 PM PDT 24
Finished Jun 09 02:15:01 PM PDT 24
Peak memory 200032 kb
Host smart-1528f825-0eac-4836-b710-2a026bc36a80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555102860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_loopback.555102860
Directory /workspace/13.uart_loopback/latest

Test location /workspace/coverage/default/13.uart_noise_filter.2971231339
Short name T472
Test name
Test status
Simulation time 8887287224 ps
CPU time 13.64 seconds
Started Jun 09 02:14:55 PM PDT 24
Finished Jun 09 02:15:09 PM PDT 24
Peak memory 199072 kb
Host smart-4b79c6d7-a536-428d-988b-4db39b6956e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971231339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_noise_filter.2971231339
Directory /workspace/13.uart_noise_filter/latest

Test location /workspace/coverage/default/13.uart_perf.1862821375
Short name T575
Test name
Test status
Simulation time 17950996264 ps
CPU time 778.45 seconds
Started Jun 09 02:15:01 PM PDT 24
Finished Jun 09 02:28:00 PM PDT 24
Peak memory 200392 kb
Host smart-8406a4c9-de81-4208-a223-cab368620f4c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1862821375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.1862821375
Directory /workspace/13.uart_perf/latest

Test location /workspace/coverage/default/13.uart_rx_oversample.1715377416
Short name T453
Test name
Test status
Simulation time 5585312263 ps
CPU time 13.73 seconds
Started Jun 09 02:15:06 PM PDT 24
Finished Jun 09 02:15:20 PM PDT 24
Peak memory 199492 kb
Host smart-c94a05b2-8ed9-464c-9ec3-c2a58fe1ede1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1715377416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.1715377416
Directory /workspace/13.uart_rx_oversample/latest

Test location /workspace/coverage/default/13.uart_rx_parity_err.1110046377
Short name T797
Test name
Test status
Simulation time 36276118544 ps
CPU time 16.55 seconds
Started Jun 09 02:14:57 PM PDT 24
Finished Jun 09 02:15:14 PM PDT 24
Peak memory 199224 kb
Host smart-64423ac0-434f-4c71-ae83-0d8da73322af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110046377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.1110046377
Directory /workspace/13.uart_rx_parity_err/latest

Test location /workspace/coverage/default/13.uart_rx_start_bit_filter.2626831703
Short name T396
Test name
Test status
Simulation time 1513066615 ps
CPU time 3.23 seconds
Started Jun 09 02:14:57 PM PDT 24
Finished Jun 09 02:15:00 PM PDT 24
Peak memory 195736 kb
Host smart-ce25d2c1-60dc-49d8-8378-53e7dff1e1c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626831703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.2626831703
Directory /workspace/13.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/13.uart_smoke.839046207
Short name T945
Test name
Test status
Simulation time 707521347 ps
CPU time 1.98 seconds
Started Jun 09 02:14:56 PM PDT 24
Finished Jun 09 02:14:58 PM PDT 24
Peak memory 199192 kb
Host smart-fff4af28-f611-4bd8-9573-1d0b957fcc6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839046207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_smoke.839046207
Directory /workspace/13.uart_smoke/latest

Test location /workspace/coverage/default/13.uart_stress_all.1306580561
Short name T812
Test name
Test status
Simulation time 358558018105 ps
CPU time 1189.54 seconds
Started Jun 09 02:15:00 PM PDT 24
Finished Jun 09 02:34:50 PM PDT 24
Peak memory 200376 kb
Host smart-3752b7b1-6be8-4b4c-aff9-39a00b07fa96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306580561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.1306580561
Directory /workspace/13.uart_stress_all/latest

Test location /workspace/coverage/default/13.uart_tx_ovrd.2231159539
Short name T375
Test name
Test status
Simulation time 926174981 ps
CPU time 2.28 seconds
Started Jun 09 02:14:55 PM PDT 24
Finished Jun 09 02:14:58 PM PDT 24
Peak memory 198672 kb
Host smart-5d8969bd-356a-4c1f-a3f3-e215ac86d3d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231159539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.2231159539
Directory /workspace/13.uart_tx_ovrd/latest

Test location /workspace/coverage/default/13.uart_tx_rx.1424555030
Short name T315
Test name
Test status
Simulation time 110474394193 ps
CPU time 136.59 seconds
Started Jun 09 02:14:55 PM PDT 24
Finished Jun 09 02:17:12 PM PDT 24
Peak memory 200384 kb
Host smart-0a49303c-8558-4697-8f8a-893654a891e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424555030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.1424555030
Directory /workspace/13.uart_tx_rx/latest

Test location /workspace/coverage/default/132.uart_fifo_reset.2733227537
Short name T752
Test name
Test status
Simulation time 139353071186 ps
CPU time 32.76 seconds
Started Jun 09 02:20:09 PM PDT 24
Finished Jun 09 02:20:42 PM PDT 24
Peak memory 200332 kb
Host smart-46eaaa93-2662-44c9-8de0-02328cd8271b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733227537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.2733227537
Directory /workspace/132.uart_fifo_reset/latest

Test location /workspace/coverage/default/133.uart_fifo_reset.3091869080
Short name T189
Test name
Test status
Simulation time 38168036362 ps
CPU time 19.35 seconds
Started Jun 09 02:20:11 PM PDT 24
Finished Jun 09 02:20:30 PM PDT 24
Peak memory 200368 kb
Host smart-909b6fad-75c1-4a2c-8856-27d365921a6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091869080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.3091869080
Directory /workspace/133.uart_fifo_reset/latest

Test location /workspace/coverage/default/136.uart_fifo_reset.694314579
Short name T675
Test name
Test status
Simulation time 154768109663 ps
CPU time 161.2 seconds
Started Jun 09 02:20:17 PM PDT 24
Finished Jun 09 02:22:58 PM PDT 24
Peak memory 200348 kb
Host smart-219b1cb5-fc4d-47d7-9591-bcf9fb011391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694314579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.694314579
Directory /workspace/136.uart_fifo_reset/latest

Test location /workspace/coverage/default/137.uart_fifo_reset.1262737299
Short name T897
Test name
Test status
Simulation time 132221413202 ps
CPU time 211.71 seconds
Started Jun 09 02:20:15 PM PDT 24
Finished Jun 09 02:23:47 PM PDT 24
Peak memory 200340 kb
Host smart-b9ce5d66-484e-4028-a240-e92c1f72f059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262737299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.1262737299
Directory /workspace/137.uart_fifo_reset/latest

Test location /workspace/coverage/default/138.uart_fifo_reset.3720568546
Short name T942
Test name
Test status
Simulation time 81957839382 ps
CPU time 197.64 seconds
Started Jun 09 02:20:17 PM PDT 24
Finished Jun 09 02:23:35 PM PDT 24
Peak memory 200320 kb
Host smart-05c640c2-d50c-4cc8-8bdf-3fa3848558e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720568546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.3720568546
Directory /workspace/138.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_alert_test.3965839387
Short name T706
Test name
Test status
Simulation time 12759820 ps
CPU time 0.57 seconds
Started Jun 09 02:15:12 PM PDT 24
Finished Jun 09 02:15:12 PM PDT 24
Peak memory 195768 kb
Host smart-8d608c8a-7279-45e9-9775-d76ca6639213
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965839387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.3965839387
Directory /workspace/14.uart_alert_test/latest

Test location /workspace/coverage/default/14.uart_fifo_full.153008398
Short name T821
Test name
Test status
Simulation time 87948478243 ps
CPU time 83.91 seconds
Started Jun 09 02:15:00 PM PDT 24
Finished Jun 09 02:16:24 PM PDT 24
Peak memory 200276 kb
Host smart-e218b1d4-77ab-42ce-92ea-5d71ea5d7d2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153008398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.153008398
Directory /workspace/14.uart_fifo_full/latest

Test location /workspace/coverage/default/14.uart_fifo_overflow.623694232
Short name T1047
Test name
Test status
Simulation time 137692736763 ps
CPU time 167.16 seconds
Started Jun 09 02:14:59 PM PDT 24
Finished Jun 09 02:17:47 PM PDT 24
Peak memory 200576 kb
Host smart-727d10e0-4eb6-419d-9ece-9a839245c94d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623694232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.623694232
Directory /workspace/14.uart_fifo_overflow/latest

Test location /workspace/coverage/default/14.uart_fifo_reset.1764149822
Short name T690
Test name
Test status
Simulation time 23958864487 ps
CPU time 12.71 seconds
Started Jun 09 02:15:01 PM PDT 24
Finished Jun 09 02:15:14 PM PDT 24
Peak memory 200288 kb
Host smart-45c5d0e5-4e4f-44c8-8b36-5bb1c9899bfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764149822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.1764149822
Directory /workspace/14.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_intr.2074675349
Short name T1026
Test name
Test status
Simulation time 60134139048 ps
CPU time 26.97 seconds
Started Jun 09 02:15:01 PM PDT 24
Finished Jun 09 02:15:28 PM PDT 24
Peak memory 200384 kb
Host smart-8c7ae6d9-da88-4ff0-aa79-f6b1317dfa98
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074675349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.2074675349
Directory /workspace/14.uart_intr/latest

Test location /workspace/coverage/default/14.uart_long_xfer_wo_dly.4122413621
Short name T991
Test name
Test status
Simulation time 185767101723 ps
CPU time 195.19 seconds
Started Jun 09 02:15:09 PM PDT 24
Finished Jun 09 02:18:25 PM PDT 24
Peak memory 200316 kb
Host smart-81b1ba42-5b33-4eed-af53-1b5179012b0d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4122413621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.4122413621
Directory /workspace/14.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/14.uart_loopback.1687521535
Short name T1074
Test name
Test status
Simulation time 5270706811 ps
CPU time 7.73 seconds
Started Jun 09 02:15:05 PM PDT 24
Finished Jun 09 02:15:13 PM PDT 24
Peak memory 199892 kb
Host smart-0f7d2f61-a08f-4917-bb3c-132565b8acb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687521535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_loopback.1687521535
Directory /workspace/14.uart_loopback/latest

Test location /workspace/coverage/default/14.uart_perf.1579729530
Short name T746
Test name
Test status
Simulation time 15839668461 ps
CPU time 367.38 seconds
Started Jun 09 02:15:04 PM PDT 24
Finished Jun 09 02:21:12 PM PDT 24
Peak memory 200364 kb
Host smart-791aa754-eb3f-45cd-a009-cbf8178edb8f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1579729530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.1579729530
Directory /workspace/14.uart_perf/latest

Test location /workspace/coverage/default/14.uart_rx_oversample.3507948705
Short name T481
Test name
Test status
Simulation time 5922843613 ps
CPU time 3.96 seconds
Started Jun 09 02:14:59 PM PDT 24
Finished Jun 09 02:15:03 PM PDT 24
Peak memory 198648 kb
Host smart-fda6ce6b-e687-4a13-bfe0-1469b2c9dfc1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3507948705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.3507948705
Directory /workspace/14.uart_rx_oversample/latest

Test location /workspace/coverage/default/14.uart_rx_parity_err.1204173945
Short name T1048
Test name
Test status
Simulation time 36467245724 ps
CPU time 36.73 seconds
Started Jun 09 02:15:05 PM PDT 24
Finished Jun 09 02:15:42 PM PDT 24
Peak memory 200344 kb
Host smart-ebf1d8e3-704f-4ddf-afec-811506e465c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204173945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.1204173945
Directory /workspace/14.uart_rx_parity_err/latest

Test location /workspace/coverage/default/14.uart_rx_start_bit_filter.4176641567
Short name T398
Test name
Test status
Simulation time 29921597215 ps
CPU time 47.21 seconds
Started Jun 09 02:15:03 PM PDT 24
Finished Jun 09 02:15:51 PM PDT 24
Peak memory 196184 kb
Host smart-194310a8-1be5-4a3d-aeff-0894039eb0d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176641567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.4176641567
Directory /workspace/14.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/14.uart_smoke.2880123504
Short name T674
Test name
Test status
Simulation time 5557261233 ps
CPU time 22.83 seconds
Started Jun 09 02:15:01 PM PDT 24
Finished Jun 09 02:15:24 PM PDT 24
Peak memory 200224 kb
Host smart-ba58177a-7547-4ef3-b724-8b72f0f1207b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880123504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_smoke.2880123504
Directory /workspace/14.uart_smoke/latest

Test location /workspace/coverage/default/14.uart_stress_all.2896963143
Short name T473
Test name
Test status
Simulation time 523178796053 ps
CPU time 603.14 seconds
Started Jun 09 02:15:10 PM PDT 24
Finished Jun 09 02:25:14 PM PDT 24
Peak memory 200624 kb
Host smart-299e32b0-11de-4906-b25d-c1f1e92fa142
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896963143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.2896963143
Directory /workspace/14.uart_stress_all/latest

Test location /workspace/coverage/default/14.uart_tx_ovrd.2929068687
Short name T957
Test name
Test status
Simulation time 8806275155 ps
CPU time 10.8 seconds
Started Jun 09 02:15:05 PM PDT 24
Finished Jun 09 02:15:16 PM PDT 24
Peak memory 200400 kb
Host smart-d25815e1-3327-4256-9213-7a01e37cf8ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929068687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.2929068687
Directory /workspace/14.uart_tx_ovrd/latest

Test location /workspace/coverage/default/14.uart_tx_rx.3824526398
Short name T287
Test name
Test status
Simulation time 20167973457 ps
CPU time 11.14 seconds
Started Jun 09 02:15:00 PM PDT 24
Finished Jun 09 02:15:11 PM PDT 24
Peak memory 200396 kb
Host smart-7b493dbd-2b33-4960-af96-2ef02e3d27b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824526398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.3824526398
Directory /workspace/14.uart_tx_rx/latest

Test location /workspace/coverage/default/140.uart_fifo_reset.3144251311
Short name T524
Test name
Test status
Simulation time 107842998109 ps
CPU time 47.15 seconds
Started Jun 09 02:20:16 PM PDT 24
Finished Jun 09 02:21:03 PM PDT 24
Peak memory 200332 kb
Host smart-5fcdf3a7-729b-4824-9980-e0fa38ec0112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144251311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.3144251311
Directory /workspace/140.uart_fifo_reset/latest

Test location /workspace/coverage/default/141.uart_fifo_reset.2578089000
Short name T874
Test name
Test status
Simulation time 39489342913 ps
CPU time 72.01 seconds
Started Jun 09 02:20:15 PM PDT 24
Finished Jun 09 02:21:27 PM PDT 24
Peak memory 200276 kb
Host smart-ba20f225-4884-4d10-98dd-eed96541aefa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578089000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.2578089000
Directory /workspace/141.uart_fifo_reset/latest

Test location /workspace/coverage/default/142.uart_fifo_reset.161833866
Short name T317
Test name
Test status
Simulation time 64081095112 ps
CPU time 101.03 seconds
Started Jun 09 02:20:15 PM PDT 24
Finished Jun 09 02:21:57 PM PDT 24
Peak memory 200356 kb
Host smart-b2ee27bc-6c55-4a49-ba59-1790057592c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161833866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.161833866
Directory /workspace/142.uart_fifo_reset/latest

Test location /workspace/coverage/default/144.uart_fifo_reset.2725928297
Short name T584
Test name
Test status
Simulation time 43056201799 ps
CPU time 39.76 seconds
Started Jun 09 02:20:22 PM PDT 24
Finished Jun 09 02:21:02 PM PDT 24
Peak memory 200308 kb
Host smart-3992b60c-8d01-4f7e-8d56-06fb8051dc1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725928297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.2725928297
Directory /workspace/144.uart_fifo_reset/latest

Test location /workspace/coverage/default/145.uart_fifo_reset.1312972615
Short name T838
Test name
Test status
Simulation time 364375210693 ps
CPU time 168.86 seconds
Started Jun 09 02:20:20 PM PDT 24
Finished Jun 09 02:23:09 PM PDT 24
Peak memory 200308 kb
Host smart-eb201196-e0ce-483e-9292-827807849f4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312972615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.1312972615
Directory /workspace/145.uart_fifo_reset/latest

Test location /workspace/coverage/default/146.uart_fifo_reset.576929192
Short name T975
Test name
Test status
Simulation time 225913120695 ps
CPU time 64.5 seconds
Started Jun 09 02:20:22 PM PDT 24
Finished Jun 09 02:21:26 PM PDT 24
Peak memory 200348 kb
Host smart-298c9aaa-c6c7-4fac-bd2a-6e8fa70a3d5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576929192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.576929192
Directory /workspace/146.uart_fifo_reset/latest

Test location /workspace/coverage/default/147.uart_fifo_reset.38347433
Short name T299
Test name
Test status
Simulation time 45278649569 ps
CPU time 57.25 seconds
Started Jun 09 02:20:18 PM PDT 24
Finished Jun 09 02:21:16 PM PDT 24
Peak memory 200444 kb
Host smart-ebb46220-f12e-43e7-a6a7-643a0074065f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38347433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.38347433
Directory /workspace/147.uart_fifo_reset/latest

Test location /workspace/coverage/default/148.uart_fifo_reset.1965565284
Short name T271
Test name
Test status
Simulation time 97358168726 ps
CPU time 221.76 seconds
Started Jun 09 02:20:20 PM PDT 24
Finished Jun 09 02:24:02 PM PDT 24
Peak memory 200344 kb
Host smart-58d5c0c9-05ae-45bd-b45a-e1d5c9cc8017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965565284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.1965565284
Directory /workspace/148.uart_fifo_reset/latest

Test location /workspace/coverage/default/149.uart_fifo_reset.1669710084
Short name T1081
Test name
Test status
Simulation time 293620410663 ps
CPU time 30.26 seconds
Started Jun 09 02:20:19 PM PDT 24
Finished Jun 09 02:20:50 PM PDT 24
Peak memory 200368 kb
Host smart-546a6e94-6cf6-4481-8b91-d1cec22dda02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669710084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.1669710084
Directory /workspace/149.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_alert_test.4237780166
Short name T1038
Test name
Test status
Simulation time 40149257 ps
CPU time 0.61 seconds
Started Jun 09 02:15:19 PM PDT 24
Finished Jun 09 02:15:20 PM PDT 24
Peak memory 196052 kb
Host smart-d3056c8e-4d5e-48b1-b539-02fd0df6baf9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237780166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.4237780166
Directory /workspace/15.uart_alert_test/latest

Test location /workspace/coverage/default/15.uart_fifo_full.1577107369
Short name T779
Test name
Test status
Simulation time 21420055636 ps
CPU time 39.25 seconds
Started Jun 09 02:15:14 PM PDT 24
Finished Jun 09 02:15:54 PM PDT 24
Peak memory 200416 kb
Host smart-cea25aa9-c46d-40c9-a439-b03021b7428a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577107369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.1577107369
Directory /workspace/15.uart_fifo_full/latest

Test location /workspace/coverage/default/15.uart_fifo_overflow.1311576487
Short name T998
Test name
Test status
Simulation time 44521164995 ps
CPU time 26 seconds
Started Jun 09 02:15:15 PM PDT 24
Finished Jun 09 02:15:42 PM PDT 24
Peak memory 200320 kb
Host smart-25508ec4-f27f-4e5a-ac13-a2a6eeb86537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311576487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.1311576487
Directory /workspace/15.uart_fifo_overflow/latest

Test location /workspace/coverage/default/15.uart_fifo_reset.1797613463
Short name T108
Test name
Test status
Simulation time 96529069266 ps
CPU time 51.5 seconds
Started Jun 09 02:15:14 PM PDT 24
Finished Jun 09 02:16:06 PM PDT 24
Peak memory 200344 kb
Host smart-c717a696-b63b-423d-9719-244a7e34d3eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797613463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.1797613463
Directory /workspace/15.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_intr.4150632735
Short name T771
Test name
Test status
Simulation time 8277978572 ps
CPU time 3.67 seconds
Started Jun 09 02:15:14 PM PDT 24
Finished Jun 09 02:15:18 PM PDT 24
Peak memory 196884 kb
Host smart-a529e17b-86fd-4de8-ba9c-cd149e7f7060
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150632735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.4150632735
Directory /workspace/15.uart_intr/latest

Test location /workspace/coverage/default/15.uart_long_xfer_wo_dly.4046247580
Short name T503
Test name
Test status
Simulation time 171456441046 ps
CPU time 1619.91 seconds
Started Jun 09 02:15:19 PM PDT 24
Finished Jun 09 02:42:19 PM PDT 24
Peak memory 200380 kb
Host smart-039c598b-722a-4373-85d4-d094df3a388d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4046247580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.4046247580
Directory /workspace/15.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/15.uart_loopback.3061037418
Short name T905
Test name
Test status
Simulation time 488634727 ps
CPU time 0.9 seconds
Started Jun 09 02:15:20 PM PDT 24
Finished Jun 09 02:15:21 PM PDT 24
Peak memory 197176 kb
Host smart-01fd8a86-262e-42a3-9051-9f048b43884f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061037418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_loopback.3061037418
Directory /workspace/15.uart_loopback/latest

Test location /workspace/coverage/default/15.uart_perf.1824920756
Short name T826
Test name
Test status
Simulation time 6117047283 ps
CPU time 152.3 seconds
Started Jun 09 02:15:23 PM PDT 24
Finished Jun 09 02:17:55 PM PDT 24
Peak memory 200340 kb
Host smart-139c88d5-204b-49d5-a7d4-7d025aef5e0c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1824920756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.1824920756
Directory /workspace/15.uart_perf/latest

Test location /workspace/coverage/default/15.uart_rx_oversample.3797067608
Short name T531
Test name
Test status
Simulation time 1303454783 ps
CPU time 1.08 seconds
Started Jun 09 02:15:15 PM PDT 24
Finished Jun 09 02:15:17 PM PDT 24
Peak memory 195896 kb
Host smart-2cd36016-0a62-46e2-9570-a95674c9478c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3797067608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.3797067608
Directory /workspace/15.uart_rx_oversample/latest

Test location /workspace/coverage/default/15.uart_rx_parity_err.3813658778
Short name T378
Test name
Test status
Simulation time 23358892575 ps
CPU time 10.78 seconds
Started Jun 09 02:15:20 PM PDT 24
Finished Jun 09 02:15:31 PM PDT 24
Peak memory 200544 kb
Host smart-e53f5c2f-d20e-445f-8555-06fa5f7d86f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813658778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.3813658778
Directory /workspace/15.uart_rx_parity_err/latest

Test location /workspace/coverage/default/15.uart_rx_start_bit_filter.3366460941
Short name T925
Test name
Test status
Simulation time 31228144573 ps
CPU time 24.09 seconds
Started Jun 09 02:15:16 PM PDT 24
Finished Jun 09 02:15:40 PM PDT 24
Peak memory 196212 kb
Host smart-38ab1ff9-4cf9-416b-8f6a-1f5bc51ba5a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366460941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.3366460941
Directory /workspace/15.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/15.uart_smoke.1945910815
Short name T844
Test name
Test status
Simulation time 474495721 ps
CPU time 2.38 seconds
Started Jun 09 02:15:09 PM PDT 24
Finished Jun 09 02:15:12 PM PDT 24
Peak memory 200168 kb
Host smart-1db94aaa-847e-4317-9b3d-16d11d4fbf8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945910815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_smoke.1945910815
Directory /workspace/15.uart_smoke/latest

Test location /workspace/coverage/default/15.uart_stress_all.3812815845
Short name T1023
Test name
Test status
Simulation time 386632040504 ps
CPU time 545.51 seconds
Started Jun 09 02:15:19 PM PDT 24
Finished Jun 09 02:24:24 PM PDT 24
Peak memory 200360 kb
Host smart-d6a667bb-6882-4344-9d21-c7988e6e37bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812815845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.3812815845
Directory /workspace/15.uart_stress_all/latest

Test location /workspace/coverage/default/15.uart_tx_ovrd.2885857967
Short name T319
Test name
Test status
Simulation time 1081893216 ps
CPU time 2.5 seconds
Started Jun 09 02:15:20 PM PDT 24
Finished Jun 09 02:15:23 PM PDT 24
Peak memory 199200 kb
Host smart-9d77081d-c543-447f-96fd-b00279625495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885857967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.2885857967
Directory /workspace/15.uart_tx_ovrd/latest

Test location /workspace/coverage/default/15.uart_tx_rx.1162500141
Short name T594
Test name
Test status
Simulation time 81927125895 ps
CPU time 18.33 seconds
Started Jun 09 02:15:09 PM PDT 24
Finished Jun 09 02:15:28 PM PDT 24
Peak memory 200392 kb
Host smart-0046da41-5094-444e-bb71-df076ab8dff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162500141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.1162500141
Directory /workspace/15.uart_tx_rx/latest

Test location /workspace/coverage/default/150.uart_fifo_reset.3333807571
Short name T732
Test name
Test status
Simulation time 53635306618 ps
CPU time 16.61 seconds
Started Jun 09 02:20:25 PM PDT 24
Finished Jun 09 02:20:42 PM PDT 24
Peak memory 200036 kb
Host smart-a2aee606-3f11-4bd5-98ed-ab9ddd281806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333807571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.3333807571
Directory /workspace/150.uart_fifo_reset/latest

Test location /workspace/coverage/default/151.uart_fifo_reset.2842046562
Short name T702
Test name
Test status
Simulation time 162347329157 ps
CPU time 88.3 seconds
Started Jun 09 02:20:26 PM PDT 24
Finished Jun 09 02:21:55 PM PDT 24
Peak memory 200388 kb
Host smart-71864375-17a9-4f75-9a6f-2f5d20b6f35b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842046562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.2842046562
Directory /workspace/151.uart_fifo_reset/latest

Test location /workspace/coverage/default/152.uart_fifo_reset.2569897262
Short name T543
Test name
Test status
Simulation time 197095253369 ps
CPU time 103.93 seconds
Started Jun 09 02:20:25 PM PDT 24
Finished Jun 09 02:22:09 PM PDT 24
Peak memory 200308 kb
Host smart-9f3267fb-3e31-43e0-aa53-bd90b8dd1645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569897262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.2569897262
Directory /workspace/152.uart_fifo_reset/latest

Test location /workspace/coverage/default/153.uart_fifo_reset.3350698403
Short name T192
Test name
Test status
Simulation time 102128673119 ps
CPU time 181.91 seconds
Started Jun 09 02:20:24 PM PDT 24
Finished Jun 09 02:23:26 PM PDT 24
Peak memory 200280 kb
Host smart-7aa814f9-802f-4234-a5b7-ac16f020cf3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350698403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.3350698403
Directory /workspace/153.uart_fifo_reset/latest

Test location /workspace/coverage/default/154.uart_fifo_reset.36177604
Short name T605
Test name
Test status
Simulation time 171054654279 ps
CPU time 394.89 seconds
Started Jun 09 02:20:25 PM PDT 24
Finished Jun 09 02:27:00 PM PDT 24
Peak memory 200360 kb
Host smart-f28041f2-69fb-49a8-9e82-8adc60194b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36177604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.36177604
Directory /workspace/154.uart_fifo_reset/latest

Test location /workspace/coverage/default/155.uart_fifo_reset.2691209821
Short name T1086
Test name
Test status
Simulation time 144802245472 ps
CPU time 53.2 seconds
Started Jun 09 02:20:25 PM PDT 24
Finished Jun 09 02:21:18 PM PDT 24
Peak memory 200368 kb
Host smart-07cbcb5c-8012-4d80-aae7-ca9c1c21d78b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691209821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.2691209821
Directory /workspace/155.uart_fifo_reset/latest

Test location /workspace/coverage/default/156.uart_fifo_reset.3375502004
Short name T657
Test name
Test status
Simulation time 131050764380 ps
CPU time 55.14 seconds
Started Jun 09 02:20:23 PM PDT 24
Finished Jun 09 02:21:19 PM PDT 24
Peak memory 200580 kb
Host smart-81d2843d-2fac-4722-b1ac-764d040b3584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375502004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.3375502004
Directory /workspace/156.uart_fifo_reset/latest

Test location /workspace/coverage/default/157.uart_fifo_reset.1769345693
Short name T431
Test name
Test status
Simulation time 104012387833 ps
CPU time 165.24 seconds
Started Jun 09 02:20:25 PM PDT 24
Finished Jun 09 02:23:10 PM PDT 24
Peak memory 200280 kb
Host smart-9aa74de7-2910-49dc-b1a5-765b1c19fdbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769345693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.1769345693
Directory /workspace/157.uart_fifo_reset/latest

Test location /workspace/coverage/default/158.uart_fifo_reset.3837771214
Short name T361
Test name
Test status
Simulation time 75514200898 ps
CPU time 9.83 seconds
Started Jun 09 02:20:26 PM PDT 24
Finished Jun 09 02:20:36 PM PDT 24
Peak memory 198736 kb
Host smart-e183dabb-6551-495a-83d3-c4d3af603b08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837771214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.3837771214
Directory /workspace/158.uart_fifo_reset/latest

Test location /workspace/coverage/default/159.uart_fifo_reset.2481074167
Short name T48
Test name
Test status
Simulation time 29483354162 ps
CPU time 52.97 seconds
Started Jun 09 02:20:29 PM PDT 24
Finished Jun 09 02:21:22 PM PDT 24
Peak memory 200316 kb
Host smart-2541a9b0-b33d-4a10-a453-134b69c51064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481074167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.2481074167
Directory /workspace/159.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_alert_test.149161346
Short name T540
Test name
Test status
Simulation time 12245083 ps
CPU time 0.58 seconds
Started Jun 09 02:15:31 PM PDT 24
Finished Jun 09 02:15:31 PM PDT 24
Peak memory 196240 kb
Host smart-855484a9-5a50-43d2-97ef-52753be76cec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149161346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.149161346
Directory /workspace/16.uart_alert_test/latest

Test location /workspace/coverage/default/16.uart_fifo_full.3558890421
Short name T638
Test name
Test status
Simulation time 35999369458 ps
CPU time 13.47 seconds
Started Jun 09 02:15:23 PM PDT 24
Finished Jun 09 02:15:37 PM PDT 24
Peak memory 200248 kb
Host smart-0d4d56bc-c5f9-4398-a7af-7360db6d8921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558890421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.3558890421
Directory /workspace/16.uart_fifo_full/latest

Test location /workspace/coverage/default/16.uart_fifo_overflow.2623242912
Short name T504
Test name
Test status
Simulation time 33072594415 ps
CPU time 20.86 seconds
Started Jun 09 02:15:20 PM PDT 24
Finished Jun 09 02:15:41 PM PDT 24
Peak memory 200260 kb
Host smart-6e9e4a83-ded0-4e15-97bb-fa1423856b1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623242912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.2623242912
Directory /workspace/16.uart_fifo_overflow/latest

Test location /workspace/coverage/default/16.uart_fifo_reset.1613951466
Short name T42
Test name
Test status
Simulation time 165619509284 ps
CPU time 284.63 seconds
Started Jun 09 02:15:19 PM PDT 24
Finished Jun 09 02:20:04 PM PDT 24
Peak memory 200348 kb
Host smart-19919fea-1440-4f15-8a33-54bbe5195ad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613951466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.1613951466
Directory /workspace/16.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_intr.2521231697
Short name T418
Test name
Test status
Simulation time 26748351626 ps
CPU time 5.58 seconds
Started Jun 09 02:15:19 PM PDT 24
Finished Jun 09 02:15:25 PM PDT 24
Peak memory 198808 kb
Host smart-33925d53-6ee7-4271-b0f8-f8847a6cdab4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521231697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.2521231697
Directory /workspace/16.uart_intr/latest

Test location /workspace/coverage/default/16.uart_long_xfer_wo_dly.3388710808
Short name T818
Test name
Test status
Simulation time 67441916217 ps
CPU time 344.67 seconds
Started Jun 09 02:15:32 PM PDT 24
Finished Jun 09 02:21:17 PM PDT 24
Peak memory 200320 kb
Host smart-7ed00d83-25ce-4f04-a8de-6ecab9bb072d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3388710808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.3388710808
Directory /workspace/16.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/16.uart_loopback.368147256
Short name T1031
Test name
Test status
Simulation time 9072282694 ps
CPU time 10.45 seconds
Started Jun 09 02:15:33 PM PDT 24
Finished Jun 09 02:15:43 PM PDT 24
Peak memory 199808 kb
Host smart-011a5fcc-b4d8-465f-958e-0a61a5cd9bea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368147256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_loopback.368147256
Directory /workspace/16.uart_loopback/latest

Test location /workspace/coverage/default/16.uart_perf.2660071708
Short name T980
Test name
Test status
Simulation time 3247162221 ps
CPU time 141.16 seconds
Started Jun 09 02:15:29 PM PDT 24
Finished Jun 09 02:17:50 PM PDT 24
Peak memory 200348 kb
Host smart-57eb920b-11b2-42bc-8095-4e8e8d16c81d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2660071708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.2660071708
Directory /workspace/16.uart_perf/latest

Test location /workspace/coverage/default/16.uart_rx_oversample.3832290899
Short name T880
Test name
Test status
Simulation time 3890360846 ps
CPU time 32.79 seconds
Started Jun 09 02:15:20 PM PDT 24
Finished Jun 09 02:15:53 PM PDT 24
Peak memory 199368 kb
Host smart-fee7e0d2-81d0-4e4e-9606-1e73647fd86a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3832290899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.3832290899
Directory /workspace/16.uart_rx_oversample/latest

Test location /workspace/coverage/default/16.uart_rx_parity_err.1595818272
Short name T132
Test name
Test status
Simulation time 91291377513 ps
CPU time 42.55 seconds
Started Jun 09 02:15:24 PM PDT 24
Finished Jun 09 02:16:07 PM PDT 24
Peak memory 200552 kb
Host smart-62cc6c71-9454-466e-ac92-7ada74cc0af7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595818272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.1595818272
Directory /workspace/16.uart_rx_parity_err/latest

Test location /workspace/coverage/default/16.uart_rx_start_bit_filter.4266872114
Short name T478
Test name
Test status
Simulation time 4170812661 ps
CPU time 1.91 seconds
Started Jun 09 02:15:24 PM PDT 24
Finished Jun 09 02:15:26 PM PDT 24
Peak memory 196432 kb
Host smart-a50d87c2-0062-4185-a944-6012a205485c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266872114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.4266872114
Directory /workspace/16.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/16.uart_smoke.1671865840
Short name T70
Test name
Test status
Simulation time 260716097 ps
CPU time 0.91 seconds
Started Jun 09 02:15:23 PM PDT 24
Finished Jun 09 02:15:24 PM PDT 24
Peak memory 198856 kb
Host smart-4a52e880-e5e0-4911-a35e-d8cd3f6e2fbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671865840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_smoke.1671865840
Directory /workspace/16.uart_smoke/latest

Test location /workspace/coverage/default/16.uart_stress_all.3522626685
Short name T663
Test name
Test status
Simulation time 24325547547 ps
CPU time 68.06 seconds
Started Jun 09 02:15:33 PM PDT 24
Finished Jun 09 02:16:41 PM PDT 24
Peak memory 200408 kb
Host smart-75604e38-9b74-40af-a91a-71bd299c1380
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522626685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.3522626685
Directory /workspace/16.uart_stress_all/latest

Test location /workspace/coverage/default/16.uart_stress_all_with_rand_reset.2571410117
Short name T895
Test name
Test status
Simulation time 253525488036 ps
CPU time 360.55 seconds
Started Jun 09 02:15:30 PM PDT 24
Finished Jun 09 02:21:31 PM PDT 24
Peak memory 210480 kb
Host smart-32926004-7010-407d-8e72-91fe71a46f7c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571410117 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 16.uart_stress_all_with_rand_reset.2571410117
Directory /workspace/16.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.uart_tx_ovrd.2981150419
Short name T321
Test name
Test status
Simulation time 11642014961 ps
CPU time 4.32 seconds
Started Jun 09 02:15:29 PM PDT 24
Finished Jun 09 02:15:34 PM PDT 24
Peak memory 200080 kb
Host smart-697c7d5e-31ab-41fd-ad38-e72e6a6edae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981150419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.2981150419
Directory /workspace/16.uart_tx_ovrd/latest

Test location /workspace/coverage/default/16.uart_tx_rx.1693029635
Short name T622
Test name
Test status
Simulation time 38558734581 ps
CPU time 36.24 seconds
Started Jun 09 02:15:23 PM PDT 24
Finished Jun 09 02:16:00 PM PDT 24
Peak memory 200376 kb
Host smart-b3a6c3b7-d7f2-459c-b681-acd4243e864e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693029635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.1693029635
Directory /workspace/16.uart_tx_rx/latest

Test location /workspace/coverage/default/160.uart_fifo_reset.579108194
Short name T755
Test name
Test status
Simulation time 37975162378 ps
CPU time 58.3 seconds
Started Jun 09 02:20:30 PM PDT 24
Finished Jun 09 02:21:29 PM PDT 24
Peak memory 200368 kb
Host smart-4fa1e9fe-28ab-4299-b764-9ea4fdcb9571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579108194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.579108194
Directory /workspace/160.uart_fifo_reset/latest

Test location /workspace/coverage/default/161.uart_fifo_reset.392204674
Short name T193
Test name
Test status
Simulation time 6794759924 ps
CPU time 10.86 seconds
Started Jun 09 02:20:28 PM PDT 24
Finished Jun 09 02:20:40 PM PDT 24
Peak memory 200352 kb
Host smart-5cd83249-afa4-4aa1-88c0-64134f956cd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392204674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.392204674
Directory /workspace/161.uart_fifo_reset/latest

Test location /workspace/coverage/default/162.uart_fifo_reset.1981924742
Short name T903
Test name
Test status
Simulation time 43984088867 ps
CPU time 13.37 seconds
Started Jun 09 02:20:28 PM PDT 24
Finished Jun 09 02:20:41 PM PDT 24
Peak memory 198548 kb
Host smart-d6b65c2f-055b-41a9-b48c-94d456645308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981924742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.1981924742
Directory /workspace/162.uart_fifo_reset/latest

Test location /workspace/coverage/default/163.uart_fifo_reset.900664495
Short name T447
Test name
Test status
Simulation time 32384598163 ps
CPU time 8.8 seconds
Started Jun 09 02:20:28 PM PDT 24
Finished Jun 09 02:20:37 PM PDT 24
Peak memory 200328 kb
Host smart-7cef14ef-92e9-4fd7-9749-9f83fe7ae139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900664495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.900664495
Directory /workspace/163.uart_fifo_reset/latest

Test location /workspace/coverage/default/165.uart_fifo_reset.1636761051
Short name T231
Test name
Test status
Simulation time 10410875014 ps
CPU time 18.52 seconds
Started Jun 09 02:20:28 PM PDT 24
Finished Jun 09 02:20:47 PM PDT 24
Peak memory 200328 kb
Host smart-5840a122-a05e-4529-ad77-ceb2f8651e73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636761051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.1636761051
Directory /workspace/165.uart_fifo_reset/latest

Test location /workspace/coverage/default/166.uart_fifo_reset.845535224
Short name T235
Test name
Test status
Simulation time 86306889547 ps
CPU time 209.03 seconds
Started Jun 09 02:20:33 PM PDT 24
Finished Jun 09 02:24:02 PM PDT 24
Peak memory 200396 kb
Host smart-a9b30cf3-ffae-4966-add3-d9f859c5aec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845535224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.845535224
Directory /workspace/166.uart_fifo_reset/latest

Test location /workspace/coverage/default/167.uart_fifo_reset.1909345821
Short name T891
Test name
Test status
Simulation time 26710178831 ps
CPU time 41.59 seconds
Started Jun 09 02:20:34 PM PDT 24
Finished Jun 09 02:21:15 PM PDT 24
Peak memory 200332 kb
Host smart-377e4ed5-e0a0-4893-a627-9418b8bf785b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909345821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.1909345821
Directory /workspace/167.uart_fifo_reset/latest

Test location /workspace/coverage/default/168.uart_fifo_reset.1398310811
Short name T561
Test name
Test status
Simulation time 50970531266 ps
CPU time 12.5 seconds
Started Jun 09 02:20:33 PM PDT 24
Finished Jun 09 02:20:46 PM PDT 24
Peak memory 200400 kb
Host smart-4f8b4802-bce5-448f-9fc1-f393754e4a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398310811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.1398310811
Directory /workspace/168.uart_fifo_reset/latest

Test location /workspace/coverage/default/169.uart_fifo_reset.2110847311
Short name T294
Test name
Test status
Simulation time 39253560224 ps
CPU time 57.15 seconds
Started Jun 09 02:20:35 PM PDT 24
Finished Jun 09 02:21:33 PM PDT 24
Peak memory 200308 kb
Host smart-52297fb2-c22f-4cce-82a6-cdd661bcaa6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110847311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.2110847311
Directory /workspace/169.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_alert_test.2606987277
Short name T780
Test name
Test status
Simulation time 12823284 ps
CPU time 0.55 seconds
Started Jun 09 02:15:37 PM PDT 24
Finished Jun 09 02:15:37 PM PDT 24
Peak memory 194712 kb
Host smart-54f5f59e-bacd-469e-b65c-baec7b0d4e58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606987277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.2606987277
Directory /workspace/17.uart_alert_test/latest

Test location /workspace/coverage/default/17.uart_fifo_full.396277645
Short name T801
Test name
Test status
Simulation time 22512255718 ps
CPU time 42.99 seconds
Started Jun 09 02:15:33 PM PDT 24
Finished Jun 09 02:16:16 PM PDT 24
Peak memory 200280 kb
Host smart-fa91433e-cdc2-4f3a-af16-96397851fde8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396277645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.396277645
Directory /workspace/17.uart_fifo_full/latest

Test location /workspace/coverage/default/17.uart_fifo_overflow.3107372838
Short name T426
Test name
Test status
Simulation time 62151564484 ps
CPU time 24.09 seconds
Started Jun 09 02:15:29 PM PDT 24
Finished Jun 09 02:15:53 PM PDT 24
Peak memory 200144 kb
Host smart-a2a469e4-8816-48ea-af94-c27a3813e5c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107372838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.3107372838
Directory /workspace/17.uart_fifo_overflow/latest

Test location /workspace/coverage/default/17.uart_fifo_reset.463062657
Short name T265
Test name
Test status
Simulation time 178485725350 ps
CPU time 406.52 seconds
Started Jun 09 02:15:29 PM PDT 24
Finished Jun 09 02:22:16 PM PDT 24
Peak memory 200336 kb
Host smart-a46cd9d5-cae4-42b2-9364-81a157dd8347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463062657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.463062657
Directory /workspace/17.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_intr.4160521004
Short name T815
Test name
Test status
Simulation time 36864228759 ps
CPU time 56.24 seconds
Started Jun 09 02:15:29 PM PDT 24
Finished Jun 09 02:16:25 PM PDT 24
Peak memory 200328 kb
Host smart-4977bb0a-be69-4e48-9f57-67f78b21b38b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160521004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.4160521004
Directory /workspace/17.uart_intr/latest

Test location /workspace/coverage/default/17.uart_long_xfer_wo_dly.2604089539
Short name T743
Test name
Test status
Simulation time 82503564980 ps
CPU time 84.55 seconds
Started Jun 09 02:15:33 PM PDT 24
Finished Jun 09 02:16:57 PM PDT 24
Peak memory 200320 kb
Host smart-ac3b56f8-bdd4-4d8b-a84d-5470aed444e5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2604089539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.2604089539
Directory /workspace/17.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/17.uart_loopback.2981644112
Short name T330
Test name
Test status
Simulation time 5386064344 ps
CPU time 7.56 seconds
Started Jun 09 02:15:36 PM PDT 24
Finished Jun 09 02:15:44 PM PDT 24
Peak memory 200284 kb
Host smart-8a9f286f-7b25-4aab-9a37-05e267cabeac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981644112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_loopback.2981644112
Directory /workspace/17.uart_loopback/latest

Test location /workspace/coverage/default/17.uart_perf.1913602556
Short name T566
Test name
Test status
Simulation time 14150925156 ps
CPU time 161.99 seconds
Started Jun 09 02:15:33 PM PDT 24
Finished Jun 09 02:18:16 PM PDT 24
Peak memory 200364 kb
Host smart-d8b173bc-a937-420b-8aa6-8cef4e1f57f1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1913602556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.1913602556
Directory /workspace/17.uart_perf/latest

Test location /workspace/coverage/default/17.uart_rx_oversample.745237384
Short name T14
Test name
Test status
Simulation time 3572510977 ps
CPU time 2.56 seconds
Started Jun 09 02:15:28 PM PDT 24
Finished Jun 09 02:15:31 PM PDT 24
Peak memory 198168 kb
Host smart-f9d44f65-dc47-400e-bb55-e7cd8bb9d8e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=745237384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.745237384
Directory /workspace/17.uart_rx_oversample/latest

Test location /workspace/coverage/default/17.uart_rx_parity_err.3137449166
Short name T934
Test name
Test status
Simulation time 97846967459 ps
CPU time 78.68 seconds
Started Jun 09 02:15:34 PM PDT 24
Finished Jun 09 02:16:53 PM PDT 24
Peak memory 200320 kb
Host smart-2107f279-9c86-4c77-94a0-f14922117553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137449166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.3137449166
Directory /workspace/17.uart_rx_parity_err/latest

Test location /workspace/coverage/default/17.uart_rx_start_bit_filter.316345525
Short name T454
Test name
Test status
Simulation time 1476094799 ps
CPU time 1.26 seconds
Started Jun 09 02:15:33 PM PDT 24
Finished Jun 09 02:15:35 PM PDT 24
Peak memory 195772 kb
Host smart-2f0f7184-b4a5-4a8f-9071-4964032b4901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316345525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.316345525
Directory /workspace/17.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/17.uart_smoke.1940569670
Short name T303
Test name
Test status
Simulation time 453232366 ps
CPU time 1.21 seconds
Started Jun 09 02:15:32 PM PDT 24
Finished Jun 09 02:15:33 PM PDT 24
Peak memory 200244 kb
Host smart-2649e58b-33e9-4c56-9280-6a65b0208d7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940569670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_smoke.1940569670
Directory /workspace/17.uart_smoke/latest

Test location /workspace/coverage/default/17.uart_stress_all.1516757217
Short name T1087
Test name
Test status
Simulation time 220603287938 ps
CPU time 389.79 seconds
Started Jun 09 02:15:34 PM PDT 24
Finished Jun 09 02:22:04 PM PDT 24
Peak memory 200588 kb
Host smart-87b07e8f-17e8-4a8e-91d0-3b4ec501d9f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516757217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.1516757217
Directory /workspace/17.uart_stress_all/latest

Test location /workspace/coverage/default/17.uart_stress_all_with_rand_reset.1317271432
Short name T849
Test name
Test status
Simulation time 24112964711 ps
CPU time 134.52 seconds
Started Jun 09 02:15:33 PM PDT 24
Finished Jun 09 02:17:48 PM PDT 24
Peak memory 216132 kb
Host smart-7bcf98a6-8553-4c10-9696-292bde3c1689
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317271432 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 17.uart_stress_all_with_rand_reset.1317271432
Directory /workspace/17.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.uart_tx_ovrd.391945931
Short name T750
Test name
Test status
Simulation time 1661293387 ps
CPU time 2.05 seconds
Started Jun 09 02:15:36 PM PDT 24
Finished Jun 09 02:15:38 PM PDT 24
Peak memory 199132 kb
Host smart-a8ac4b6b-1985-4a71-85e6-9fcbef8bab2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391945931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.391945931
Directory /workspace/17.uart_tx_ovrd/latest

Test location /workspace/coverage/default/17.uart_tx_rx.4190046934
Short name T648
Test name
Test status
Simulation time 77874843214 ps
CPU time 33.12 seconds
Started Jun 09 02:15:29 PM PDT 24
Finished Jun 09 02:16:02 PM PDT 24
Peak memory 200400 kb
Host smart-2abc50bf-6b46-4583-bce9-1f2b1c5d29d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190046934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.4190046934
Directory /workspace/17.uart_tx_rx/latest

Test location /workspace/coverage/default/171.uart_fifo_reset.1500310425
Short name T963
Test name
Test status
Simulation time 113324245314 ps
CPU time 384.29 seconds
Started Jun 09 02:20:34 PM PDT 24
Finished Jun 09 02:26:58 PM PDT 24
Peak memory 200380 kb
Host smart-d078de8b-b88d-4d1b-8b3f-99f0765c184c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500310425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.1500310425
Directory /workspace/171.uart_fifo_reset/latest

Test location /workspace/coverage/default/173.uart_fifo_reset.2913937810
Short name T191
Test name
Test status
Simulation time 51953317484 ps
CPU time 80.68 seconds
Started Jun 09 02:20:34 PM PDT 24
Finished Jun 09 02:21:55 PM PDT 24
Peak memory 200376 kb
Host smart-aa01b61d-f2aa-4400-bae3-4a5b64bc69d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913937810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.2913937810
Directory /workspace/173.uart_fifo_reset/latest

Test location /workspace/coverage/default/174.uart_fifo_reset.1493015457
Short name T173
Test name
Test status
Simulation time 30580135166 ps
CPU time 47.26 seconds
Started Jun 09 02:20:35 PM PDT 24
Finished Jun 09 02:21:23 PM PDT 24
Peak memory 200364 kb
Host smart-7ea464ed-5100-4a8d-bd66-d4bbc19706d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493015457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.1493015457
Directory /workspace/174.uart_fifo_reset/latest

Test location /workspace/coverage/default/175.uart_fifo_reset.1499060405
Short name T214
Test name
Test status
Simulation time 47784444896 ps
CPU time 18.77 seconds
Started Jun 09 02:20:33 PM PDT 24
Finished Jun 09 02:20:52 PM PDT 24
Peak memory 200324 kb
Host smart-fd818adc-58e7-4fd6-b3b6-8128863a80da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499060405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.1499060405
Directory /workspace/175.uart_fifo_reset/latest

Test location /workspace/coverage/default/176.uart_fifo_reset.3007448338
Short name T144
Test name
Test status
Simulation time 28800396590 ps
CPU time 22.7 seconds
Started Jun 09 02:20:35 PM PDT 24
Finished Jun 09 02:20:58 PM PDT 24
Peak memory 200368 kb
Host smart-b9fec58d-3d92-465e-bce7-74fc703e3829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007448338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.3007448338
Directory /workspace/176.uart_fifo_reset/latest

Test location /workspace/coverage/default/177.uart_fifo_reset.787891302
Short name T782
Test name
Test status
Simulation time 48851228738 ps
CPU time 23.06 seconds
Started Jun 09 02:20:35 PM PDT 24
Finished Jun 09 02:20:58 PM PDT 24
Peak memory 200360 kb
Host smart-f7ea43f7-ddff-4eae-82f2-2c6725530269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787891302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.787891302
Directory /workspace/177.uart_fifo_reset/latest

Test location /workspace/coverage/default/179.uart_fifo_reset.2425988798
Short name T47
Test name
Test status
Simulation time 103781978883 ps
CPU time 42.07 seconds
Started Jun 09 02:20:38 PM PDT 24
Finished Jun 09 02:21:20 PM PDT 24
Peak memory 200136 kb
Host smart-92259fd0-5857-4e68-84c8-deb68e29adf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425988798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.2425988798
Directory /workspace/179.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_alert_test.3939744277
Short name T583
Test name
Test status
Simulation time 35253843 ps
CPU time 0.56 seconds
Started Jun 09 02:15:46 PM PDT 24
Finished Jun 09 02:15:47 PM PDT 24
Peak memory 196024 kb
Host smart-9f7e0f00-468d-48e7-8074-f94e68f62fb3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939744277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.3939744277
Directory /workspace/18.uart_alert_test/latest

Test location /workspace/coverage/default/18.uart_fifo_full.197419074
Short name T267
Test name
Test status
Simulation time 15116388434 ps
CPU time 26.16 seconds
Started Jun 09 02:15:37 PM PDT 24
Finished Jun 09 02:16:04 PM PDT 24
Peak memory 200404 kb
Host smart-bb6a1539-ce22-40a6-8d6c-85aa07c19054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197419074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.197419074
Directory /workspace/18.uart_fifo_full/latest

Test location /workspace/coverage/default/18.uart_fifo_overflow.3602716781
Short name T1068
Test name
Test status
Simulation time 73828226966 ps
CPU time 60.92 seconds
Started Jun 09 02:15:37 PM PDT 24
Finished Jun 09 02:16:38 PM PDT 24
Peak memory 200296 kb
Host smart-da548ce7-a618-425c-adbd-e1939b81710b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602716781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.3602716781
Directory /workspace/18.uart_fifo_overflow/latest

Test location /workspace/coverage/default/18.uart_fifo_reset.2219551936
Short name T1
Test name
Test status
Simulation time 17799695135 ps
CPU time 53.23 seconds
Started Jun 09 02:15:34 PM PDT 24
Finished Jun 09 02:16:27 PM PDT 24
Peak memory 200332 kb
Host smart-8bf5d81f-4908-40b0-8f3f-3c03abb389d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219551936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.2219551936
Directory /workspace/18.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_intr.1632702753
Short name T256
Test name
Test status
Simulation time 17857485111 ps
CPU time 43.43 seconds
Started Jun 09 02:15:40 PM PDT 24
Finished Jun 09 02:16:24 PM PDT 24
Peak memory 200372 kb
Host smart-bcf5d12c-bacb-4c24-81c2-6e221237da40
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632702753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.1632702753
Directory /workspace/18.uart_intr/latest

Test location /workspace/coverage/default/18.uart_long_xfer_wo_dly.3525733650
Short name T938
Test name
Test status
Simulation time 48188962411 ps
CPU time 395.89 seconds
Started Jun 09 02:15:45 PM PDT 24
Finished Jun 09 02:22:21 PM PDT 24
Peak memory 200412 kb
Host smart-debc68af-d7ba-4682-99ad-1d576b14422e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3525733650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.3525733650
Directory /workspace/18.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/18.uart_loopback.2350370835
Short name T388
Test name
Test status
Simulation time 155570562 ps
CPU time 0.97 seconds
Started Jun 09 02:15:43 PM PDT 24
Finished Jun 09 02:15:44 PM PDT 24
Peak memory 197360 kb
Host smart-a4432dfa-df9a-4cf2-97e9-a04d7671e11f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350370835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_loopback.2350370835
Directory /workspace/18.uart_loopback/latest

Test location /workspace/coverage/default/18.uart_perf.2035384336
Short name T358
Test name
Test status
Simulation time 15844110041 ps
CPU time 602.45 seconds
Started Jun 09 02:15:48 PM PDT 24
Finished Jun 09 02:25:50 PM PDT 24
Peak memory 200396 kb
Host smart-ea1e4bcc-9512-4fad-a547-e50fea122b8f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2035384336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.2035384336
Directory /workspace/18.uart_perf/latest

Test location /workspace/coverage/default/18.uart_rx_oversample.2695132675
Short name T450
Test name
Test status
Simulation time 3872208575 ps
CPU time 28.72 seconds
Started Jun 09 02:15:33 PM PDT 24
Finished Jun 09 02:16:02 PM PDT 24
Peak memory 198364 kb
Host smart-7f67e1ad-8e2d-4f10-ac1d-be6db5089572
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2695132675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.2695132675
Directory /workspace/18.uart_rx_oversample/latest

Test location /workspace/coverage/default/18.uart_rx_start_bit_filter.450926407
Short name T857
Test name
Test status
Simulation time 36329572527 ps
CPU time 52.65 seconds
Started Jun 09 02:15:38 PM PDT 24
Finished Jun 09 02:16:31 PM PDT 24
Peak memory 196160 kb
Host smart-3a59fa41-1da5-40e3-b691-1d2ca4b6e811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450926407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.450926407
Directory /workspace/18.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/18.uart_smoke.264409930
Short name T787
Test name
Test status
Simulation time 645250522 ps
CPU time 2.55 seconds
Started Jun 09 02:15:37 PM PDT 24
Finished Jun 09 02:15:40 PM PDT 24
Peak memory 199144 kb
Host smart-131f7d7b-d479-42f7-81a7-7ecaea587cfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264409930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_smoke.264409930
Directory /workspace/18.uart_smoke/latest

Test location /workspace/coverage/default/18.uart_stress_all.2758615627
Short name T140
Test name
Test status
Simulation time 219471280842 ps
CPU time 178.49 seconds
Started Jun 09 02:15:42 PM PDT 24
Finished Jun 09 02:18:41 PM PDT 24
Peak memory 200352 kb
Host smart-e5f0ac59-1c40-487e-bf0c-ce7ca193156e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758615627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.2758615627
Directory /workspace/18.uart_stress_all/latest

Test location /workspace/coverage/default/18.uart_stress_all_with_rand_reset.3085357300
Short name T122
Test name
Test status
Simulation time 62881705502 ps
CPU time 492.45 seconds
Started Jun 09 02:15:44 PM PDT 24
Finished Jun 09 02:23:56 PM PDT 24
Peak memory 217156 kb
Host smart-3f6464d2-f7ae-465b-bb1b-328012401e9c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085357300 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 18.uart_stress_all_with_rand_reset.3085357300
Directory /workspace/18.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.uart_tx_ovrd.1305896134
Short name T832
Test name
Test status
Simulation time 1472735189 ps
CPU time 2.07 seconds
Started Jun 09 02:15:40 PM PDT 24
Finished Jun 09 02:15:42 PM PDT 24
Peak memory 200160 kb
Host smart-1288c7a5-345e-42fb-8bde-ae5cf554a2ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305896134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.1305896134
Directory /workspace/18.uart_tx_ovrd/latest

Test location /workspace/coverage/default/18.uart_tx_rx.1151117562
Short name T127
Test name
Test status
Simulation time 6952470177 ps
CPU time 16.23 seconds
Started Jun 09 02:15:35 PM PDT 24
Finished Jun 09 02:15:51 PM PDT 24
Peak memory 200356 kb
Host smart-ee09458d-93b9-4eef-9587-6c43179dc027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151117562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.1151117562
Directory /workspace/18.uart_tx_rx/latest

Test location /workspace/coverage/default/181.uart_fifo_reset.176848799
Short name T282
Test name
Test status
Simulation time 138933453558 ps
CPU time 60.32 seconds
Started Jun 09 02:20:38 PM PDT 24
Finished Jun 09 02:21:39 PM PDT 24
Peak memory 200384 kb
Host smart-d4c2f33f-1d6e-4d69-b68b-fa2d41755d2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176848799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.176848799
Directory /workspace/181.uart_fifo_reset/latest

Test location /workspace/coverage/default/182.uart_fifo_reset.3093820319
Short name T850
Test name
Test status
Simulation time 377935361412 ps
CPU time 103.9 seconds
Started Jun 09 02:20:38 PM PDT 24
Finished Jun 09 02:22:22 PM PDT 24
Peak memory 200184 kb
Host smart-4be62861-33d8-454f-ac72-cb698fbde2bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093820319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.3093820319
Directory /workspace/182.uart_fifo_reset/latest

Test location /workspace/coverage/default/183.uart_fifo_reset.2760735525
Short name T573
Test name
Test status
Simulation time 101623215275 ps
CPU time 66.8 seconds
Started Jun 09 02:20:38 PM PDT 24
Finished Jun 09 02:21:45 PM PDT 24
Peak memory 200372 kb
Host smart-760dfb43-4b94-47d4-bffd-fac8e8c9c088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760735525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.2760735525
Directory /workspace/183.uart_fifo_reset/latest

Test location /workspace/coverage/default/184.uart_fifo_reset.628380082
Short name T502
Test name
Test status
Simulation time 17527416265 ps
CPU time 33.52 seconds
Started Jun 09 02:20:39 PM PDT 24
Finished Jun 09 02:21:13 PM PDT 24
Peak memory 200364 kb
Host smart-a4c2ec52-30f3-467b-8e2c-3b6a357f7584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628380082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.628380082
Directory /workspace/184.uart_fifo_reset/latest

Test location /workspace/coverage/default/185.uart_fifo_reset.3434571952
Short name T651
Test name
Test status
Simulation time 133244276183 ps
CPU time 120.66 seconds
Started Jun 09 02:20:38 PM PDT 24
Finished Jun 09 02:22:39 PM PDT 24
Peak memory 200336 kb
Host smart-0941d3bf-f778-485f-b80f-feeb831608a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434571952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.3434571952
Directory /workspace/185.uart_fifo_reset/latest

Test location /workspace/coverage/default/186.uart_fifo_reset.540637461
Short name T71
Test name
Test status
Simulation time 23277393052 ps
CPU time 36.86 seconds
Started Jun 09 02:20:37 PM PDT 24
Finished Jun 09 02:21:14 PM PDT 24
Peak memory 200356 kb
Host smart-ce4a7473-4cf0-4948-954b-e0d5d9d660dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540637461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.540637461
Directory /workspace/186.uart_fifo_reset/latest

Test location /workspace/coverage/default/187.uart_fifo_reset.3273688903
Short name T623
Test name
Test status
Simulation time 56295202337 ps
CPU time 31.62 seconds
Started Jun 09 02:20:38 PM PDT 24
Finished Jun 09 02:21:10 PM PDT 24
Peak memory 200368 kb
Host smart-b80c8423-009a-4eb1-8188-7b4f57025d69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273688903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.3273688903
Directory /workspace/187.uart_fifo_reset/latest

Test location /workspace/coverage/default/188.uart_fifo_reset.4112452257
Short name T254
Test name
Test status
Simulation time 175426489077 ps
CPU time 68.98 seconds
Started Jun 09 02:20:37 PM PDT 24
Finished Jun 09 02:21:46 PM PDT 24
Peak memory 200380 kb
Host smart-59449d4d-3b7b-4175-9003-efa83522dd37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112452257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.4112452257
Directory /workspace/188.uart_fifo_reset/latest

Test location /workspace/coverage/default/189.uart_fifo_reset.3571653398
Short name T38
Test name
Test status
Simulation time 24712311582 ps
CPU time 27.13 seconds
Started Jun 09 02:20:35 PM PDT 24
Finished Jun 09 02:21:03 PM PDT 24
Peak memory 199356 kb
Host smart-83b19ca7-f114-4d76-bc70-f39a8014dd9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571653398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.3571653398
Directory /workspace/189.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_alert_test.5408419
Short name T344
Test name
Test status
Simulation time 34025491 ps
CPU time 0.54 seconds
Started Jun 09 02:15:54 PM PDT 24
Finished Jun 09 02:15:55 PM PDT 24
Peak memory 195692 kb
Host smart-d1892bd0-e347-44e0-bfcd-b1b97fa19ad2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5408419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.5408419
Directory /workspace/19.uart_alert_test/latest

Test location /workspace/coverage/default/19.uart_fifo_full.110450606
Short name T870
Test name
Test status
Simulation time 137042825559 ps
CPU time 462.72 seconds
Started Jun 09 02:15:47 PM PDT 24
Finished Jun 09 02:23:30 PM PDT 24
Peak memory 200420 kb
Host smart-c7c9076c-38a2-4218-8eed-628aa049d269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110450606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.110450606
Directory /workspace/19.uart_fifo_full/latest

Test location /workspace/coverage/default/19.uart_fifo_overflow.1132344316
Short name T421
Test name
Test status
Simulation time 194586917363 ps
CPU time 30.19 seconds
Started Jun 09 02:15:48 PM PDT 24
Finished Jun 09 02:16:18 PM PDT 24
Peak memory 199864 kb
Host smart-a925d9b7-ed51-4837-8452-a5e3e8657574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132344316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.1132344316
Directory /workspace/19.uart_fifo_overflow/latest

Test location /workspace/coverage/default/19.uart_fifo_reset.3518620708
Short name T273
Test name
Test status
Simulation time 105108359127 ps
CPU time 46.13 seconds
Started Jun 09 02:15:50 PM PDT 24
Finished Jun 09 02:16:36 PM PDT 24
Peak memory 200328 kb
Host smart-3bcb63b7-f268-4eac-ab36-5b589a4d9313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518620708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.3518620708
Directory /workspace/19.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_intr.1862466695
Short name T564
Test name
Test status
Simulation time 309923343532 ps
CPU time 418.85 seconds
Started Jun 09 02:15:50 PM PDT 24
Finished Jun 09 02:22:49 PM PDT 24
Peak memory 198916 kb
Host smart-08f9b991-2f76-4698-9e17-5e502eb7dd31
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862466695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.1862466695
Directory /workspace/19.uart_intr/latest

Test location /workspace/coverage/default/19.uart_long_xfer_wo_dly.1175460486
Short name T609
Test name
Test status
Simulation time 139426174302 ps
CPU time 412.45 seconds
Started Jun 09 02:15:48 PM PDT 24
Finished Jun 09 02:22:41 PM PDT 24
Peak memory 200404 kb
Host smart-0acb506a-dae5-44ac-a094-9ca428d2e385
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1175460486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.1175460486
Directory /workspace/19.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/19.uart_loopback.2876637540
Short name T21
Test name
Test status
Simulation time 23074386 ps
CPU time 0.59 seconds
Started Jun 09 02:15:55 PM PDT 24
Finished Jun 09 02:15:56 PM PDT 24
Peak memory 196068 kb
Host smart-a7ecd859-cfe5-424b-8533-ad6a3df5e106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876637540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_loopback.2876637540
Directory /workspace/19.uart_loopback/latest

Test location /workspace/coverage/default/19.uart_perf.806238218
Short name T579
Test name
Test status
Simulation time 10782699490 ps
CPU time 578.22 seconds
Started Jun 09 02:15:50 PM PDT 24
Finished Jun 09 02:25:28 PM PDT 24
Peak memory 200356 kb
Host smart-f718670c-2ae1-4ef2-ad81-031bf477c405
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=806238218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.806238218
Directory /workspace/19.uart_perf/latest

Test location /workspace/coverage/default/19.uart_rx_oversample.2278249351
Short name T444
Test name
Test status
Simulation time 5740795117 ps
CPU time 61.8 seconds
Started Jun 09 02:15:55 PM PDT 24
Finished Jun 09 02:16:57 PM PDT 24
Peak memory 199668 kb
Host smart-8686e355-5ddf-4ecf-8b83-ea1218a4ac3c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2278249351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.2278249351
Directory /workspace/19.uart_rx_oversample/latest

Test location /workspace/coverage/default/19.uart_rx_parity_err.173056269
Short name T641
Test name
Test status
Simulation time 232146794040 ps
CPU time 99.77 seconds
Started Jun 09 02:15:49 PM PDT 24
Finished Jun 09 02:17:29 PM PDT 24
Peak memory 200372 kb
Host smart-7b5bb75f-3ea6-4458-a512-cbc79f0ef0ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173056269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.173056269
Directory /workspace/19.uart_rx_parity_err/latest

Test location /workspace/coverage/default/19.uart_rx_start_bit_filter.731698371
Short name T971
Test name
Test status
Simulation time 1568578178 ps
CPU time 1.76 seconds
Started Jun 09 02:15:49 PM PDT 24
Finished Jun 09 02:15:50 PM PDT 24
Peak memory 195964 kb
Host smart-468cf3a5-6a5d-4e1e-ae80-d9162530cb84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731698371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.731698371
Directory /workspace/19.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/19.uart_smoke.1434919044
Short name T10
Test name
Test status
Simulation time 271978840 ps
CPU time 1.41 seconds
Started Jun 09 02:15:43 PM PDT 24
Finished Jun 09 02:15:45 PM PDT 24
Peak memory 198908 kb
Host smart-a7aeb6fa-8755-4a0b-986a-def27f304c07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434919044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_smoke.1434919044
Directory /workspace/19.uart_smoke/latest

Test location /workspace/coverage/default/19.uart_stress_all.3243907434
Short name T1019
Test name
Test status
Simulation time 296422032435 ps
CPU time 409.35 seconds
Started Jun 09 02:15:55 PM PDT 24
Finished Jun 09 02:22:45 PM PDT 24
Peak memory 200400 kb
Host smart-50de3763-095b-410b-aaae-4e15cc5f3808
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243907434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.3243907434
Directory /workspace/19.uart_stress_all/latest

Test location /workspace/coverage/default/19.uart_stress_all_with_rand_reset.4225466936
Short name T32
Test name
Test status
Simulation time 145019883782 ps
CPU time 568.53 seconds
Started Jun 09 02:15:56 PM PDT 24
Finished Jun 09 02:25:25 PM PDT 24
Peak memory 216884 kb
Host smart-229c8ff0-f65a-407c-b882-36c37f544a48
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225466936 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 19.uart_stress_all_with_rand_reset.4225466936
Directory /workspace/19.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.uart_tx_ovrd.4064480130
Short name T676
Test name
Test status
Simulation time 8291604851 ps
CPU time 12.02 seconds
Started Jun 09 02:15:48 PM PDT 24
Finished Jun 09 02:16:00 PM PDT 24
Peak memory 200620 kb
Host smart-980cb175-119b-457e-98cb-be6eea8d1bb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064480130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.4064480130
Directory /workspace/19.uart_tx_ovrd/latest

Test location /workspace/coverage/default/19.uart_tx_rx.2510081660
Short name T276
Test name
Test status
Simulation time 10003174451 ps
CPU time 15.77 seconds
Started Jun 09 02:15:44 PM PDT 24
Finished Jun 09 02:16:00 PM PDT 24
Peak memory 200384 kb
Host smart-b2993870-99d2-4285-9537-afb988487b09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510081660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.2510081660
Directory /workspace/19.uart_tx_rx/latest

Test location /workspace/coverage/default/190.uart_fifo_reset.3365934879
Short name T152
Test name
Test status
Simulation time 20057209125 ps
CPU time 33.47 seconds
Started Jun 09 02:20:42 PM PDT 24
Finished Jun 09 02:21:15 PM PDT 24
Peak memory 200332 kb
Host smart-f864dce8-3e97-4f2a-b993-b0fe4457a84d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365934879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.3365934879
Directory /workspace/190.uart_fifo_reset/latest

Test location /workspace/coverage/default/191.uart_fifo_reset.2553406746
Short name T947
Test name
Test status
Simulation time 44450824746 ps
CPU time 20.43 seconds
Started Jun 09 02:20:44 PM PDT 24
Finished Jun 09 02:21:05 PM PDT 24
Peak memory 200368 kb
Host smart-c729ddc5-b210-46c9-8ec1-48ddb8ab46f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553406746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.2553406746
Directory /workspace/191.uart_fifo_reset/latest

Test location /workspace/coverage/default/192.uart_fifo_reset.1390736032
Short name T556
Test name
Test status
Simulation time 22844071334 ps
CPU time 12.67 seconds
Started Jun 09 02:20:41 PM PDT 24
Finished Jun 09 02:20:54 PM PDT 24
Peak memory 200328 kb
Host smart-ecb3f6ac-647a-4f0d-87bd-f0bfe7ec8ccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390736032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.1390736032
Directory /workspace/192.uart_fifo_reset/latest

Test location /workspace/coverage/default/193.uart_fifo_reset.3098992962
Short name T806
Test name
Test status
Simulation time 138417242843 ps
CPU time 55.98 seconds
Started Jun 09 02:20:43 PM PDT 24
Finished Jun 09 02:21:39 PM PDT 24
Peak memory 200336 kb
Host smart-d605f806-6939-41cc-86de-190d2c5aaf3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098992962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.3098992962
Directory /workspace/193.uart_fifo_reset/latest

Test location /workspace/coverage/default/194.uart_fifo_reset.3447540396
Short name T187
Test name
Test status
Simulation time 43950766883 ps
CPU time 25.43 seconds
Started Jun 09 02:20:43 PM PDT 24
Finished Jun 09 02:21:09 PM PDT 24
Peak memory 200592 kb
Host smart-ed824b92-970a-472d-b2b7-a1ba91eb4649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447540396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.3447540396
Directory /workspace/194.uart_fifo_reset/latest

Test location /workspace/coverage/default/195.uart_fifo_reset.1925184054
Short name T570
Test name
Test status
Simulation time 178183539394 ps
CPU time 65.34 seconds
Started Jun 09 02:20:42 PM PDT 24
Finished Jun 09 02:21:48 PM PDT 24
Peak memory 200308 kb
Host smart-6f75cca4-85b2-48ec-af9f-6389f99fce56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925184054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.1925184054
Directory /workspace/195.uart_fifo_reset/latest

Test location /workspace/coverage/default/199.uart_fifo_reset.3327116389
Short name T686
Test name
Test status
Simulation time 372698469612 ps
CPU time 315.63 seconds
Started Jun 09 02:20:46 PM PDT 24
Finished Jun 09 02:26:01 PM PDT 24
Peak memory 200360 kb
Host smart-9da6349f-3e77-4be3-b555-78f22386dd58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327116389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.3327116389
Directory /workspace/199.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_alert_test.1327269659
Short name T442
Test name
Test status
Simulation time 41129978 ps
CPU time 0.56 seconds
Started Jun 09 02:13:16 PM PDT 24
Finished Jun 09 02:13:17 PM PDT 24
Peak memory 194720 kb
Host smart-0c42b1d2-51ca-453b-8e86-ab5fef996b28
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327269659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.1327269659
Directory /workspace/2.uart_alert_test/latest

Test location /workspace/coverage/default/2.uart_fifo_full.685404293
Short name T500
Test name
Test status
Simulation time 54747356048 ps
CPU time 22.63 seconds
Started Jun 09 02:13:08 PM PDT 24
Finished Jun 09 02:13:30 PM PDT 24
Peak memory 200364 kb
Host smart-5bce7539-7b4e-492f-967d-0d21933fecfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685404293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.685404293
Directory /workspace/2.uart_fifo_full/latest

Test location /workspace/coverage/default/2.uart_fifo_overflow.3994982203
Short name T262
Test name
Test status
Simulation time 123905149581 ps
CPU time 190.29 seconds
Started Jun 09 02:13:06 PM PDT 24
Finished Jun 09 02:16:17 PM PDT 24
Peak memory 200332 kb
Host smart-75119ca4-7790-4d0b-994b-fd1761fa54c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994982203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.3994982203
Directory /workspace/2.uart_fifo_overflow/latest

Test location /workspace/coverage/default/2.uart_fifo_reset.3318362479
Short name T677
Test name
Test status
Simulation time 128468517504 ps
CPU time 104.48 seconds
Started Jun 09 02:13:10 PM PDT 24
Finished Jun 09 02:14:54 PM PDT 24
Peak memory 200388 kb
Host smart-bfc712e9-26f2-4cb6-b716-2f4f38f96eee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318362479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.3318362479
Directory /workspace/2.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_intr.2276392653
Short name T900
Test name
Test status
Simulation time 16434330193 ps
CPU time 18.85 seconds
Started Jun 09 02:13:06 PM PDT 24
Finished Jun 09 02:13:25 PM PDT 24
Peak memory 200172 kb
Host smart-ffc96bc5-1859-460c-9d1a-2e159c44d816
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276392653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.2276392653
Directory /workspace/2.uart_intr/latest

Test location /workspace/coverage/default/2.uart_long_xfer_wo_dly.1362192872
Short name T264
Test name
Test status
Simulation time 105150486654 ps
CPU time 285.48 seconds
Started Jun 09 02:13:09 PM PDT 24
Finished Jun 09 02:17:54 PM PDT 24
Peak memory 200364 kb
Host smart-732dec02-b39b-4b39-a6f9-a23707fbe258
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1362192872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.1362192872
Directory /workspace/2.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/2.uart_loopback.1166331097
Short name T757
Test name
Test status
Simulation time 6884407836 ps
CPU time 10.11 seconds
Started Jun 09 02:13:13 PM PDT 24
Finished Jun 09 02:13:23 PM PDT 24
Peak memory 199916 kb
Host smart-784c9f54-0012-45c6-83c3-66b00d3246a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166331097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_loopback.1166331097
Directory /workspace/2.uart_loopback/latest

Test location /workspace/coverage/default/2.uart_perf.257012776
Short name T717
Test name
Test status
Simulation time 16269609004 ps
CPU time 463.09 seconds
Started Jun 09 02:13:11 PM PDT 24
Finished Jun 09 02:20:54 PM PDT 24
Peak memory 200384 kb
Host smart-f124e04f-81c6-4813-b0f0-afc0713de95f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=257012776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.257012776
Directory /workspace/2.uart_perf/latest

Test location /workspace/coverage/default/2.uart_rx_oversample.3070830191
Short name T992
Test name
Test status
Simulation time 2580747189 ps
CPU time 3.9 seconds
Started Jun 09 02:13:10 PM PDT 24
Finished Jun 09 02:13:14 PM PDT 24
Peak memory 198828 kb
Host smart-8f623641-5236-4862-be2e-cb42f8a35385
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3070830191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.3070830191
Directory /workspace/2.uart_rx_oversample/latest

Test location /workspace/coverage/default/2.uart_rx_parity_err.1376682730
Short name T142
Test name
Test status
Simulation time 44974407795 ps
CPU time 16.58 seconds
Started Jun 09 02:13:09 PM PDT 24
Finished Jun 09 02:13:26 PM PDT 24
Peak memory 200328 kb
Host smart-90a8032f-ed1a-47f0-b461-fbdedaa74acd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376682730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.1376682730
Directory /workspace/2.uart_rx_parity_err/latest

Test location /workspace/coverage/default/2.uart_rx_start_bit_filter.3646821047
Short name T833
Test name
Test status
Simulation time 3393945727 ps
CPU time 3.28 seconds
Started Jun 09 02:13:09 PM PDT 24
Finished Jun 09 02:13:13 PM PDT 24
Peak memory 196428 kb
Host smart-0c230b12-b1dc-4702-bda6-349d07b2383b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646821047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.3646821047
Directory /workspace/2.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/2.uart_sec_cm.3031782008
Short name T29
Test name
Test status
Simulation time 220164917 ps
CPU time 0.83 seconds
Started Jun 09 02:13:18 PM PDT 24
Finished Jun 09 02:13:19 PM PDT 24
Peak memory 218880 kb
Host smart-1ae32780-ce70-4a22-acd8-7e998101470c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031782008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.3031782008
Directory /workspace/2.uart_sec_cm/latest

Test location /workspace/coverage/default/2.uart_smoke.2851040537
Short name T288
Test name
Test status
Simulation time 5561121631 ps
CPU time 10.7 seconds
Started Jun 09 02:13:07 PM PDT 24
Finished Jun 09 02:13:18 PM PDT 24
Peak memory 200220 kb
Host smart-6f856df3-1891-4f77-9839-7d437200a499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851040537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_smoke.2851040537
Directory /workspace/2.uart_smoke/latest

Test location /workspace/coverage/default/2.uart_tx_ovrd.3591940300
Short name T625
Test name
Test status
Simulation time 7167041913 ps
CPU time 19.77 seconds
Started Jun 09 02:13:11 PM PDT 24
Finished Jun 09 02:13:31 PM PDT 24
Peak memory 199932 kb
Host smart-3fe571e4-fa5b-47fd-b072-0c1a828940f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591940300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.3591940300
Directory /workspace/2.uart_tx_ovrd/latest

Test location /workspace/coverage/default/2.uart_tx_rx.3870499673
Short name T591
Test name
Test status
Simulation time 44453251989 ps
CPU time 32.02 seconds
Started Jun 09 02:13:09 PM PDT 24
Finished Jun 09 02:13:41 PM PDT 24
Peak memory 200372 kb
Host smart-921f0041-450b-4d91-81dc-ba99538fa5d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870499673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.3870499673
Directory /workspace/2.uart_tx_rx/latest

Test location /workspace/coverage/default/20.uart_alert_test.1574234114
Short name T881
Test name
Test status
Simulation time 44473959 ps
CPU time 0.57 seconds
Started Jun 09 02:15:58 PM PDT 24
Finished Jun 09 02:15:58 PM PDT 24
Peak memory 195708 kb
Host smart-140ec461-7d21-4eda-a1c3-05947084d41e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574234114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.1574234114
Directory /workspace/20.uart_alert_test/latest

Test location /workspace/coverage/default/20.uart_fifo_full.844596793
Short name T909
Test name
Test status
Simulation time 159122911622 ps
CPU time 28.12 seconds
Started Jun 09 02:15:55 PM PDT 24
Finished Jun 09 02:16:23 PM PDT 24
Peak memory 200396 kb
Host smart-08005647-be5f-43b2-b2da-1df4f67cff1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844596793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.844596793
Directory /workspace/20.uart_fifo_full/latest

Test location /workspace/coverage/default/20.uart_fifo_overflow.610675178
Short name T496
Test name
Test status
Simulation time 238087891800 ps
CPU time 29.96 seconds
Started Jun 09 02:15:55 PM PDT 24
Finished Jun 09 02:16:25 PM PDT 24
Peak memory 200344 kb
Host smart-bd7a1926-80f8-4c31-91d3-8bc4d07cef58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610675178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.610675178
Directory /workspace/20.uart_fifo_overflow/latest

Test location /workspace/coverage/default/20.uart_fifo_reset.4217458447
Short name T840
Test name
Test status
Simulation time 25570455246 ps
CPU time 12.63 seconds
Started Jun 09 02:15:56 PM PDT 24
Finished Jun 09 02:16:09 PM PDT 24
Peak memory 200448 kb
Host smart-037c9899-cb88-4cb1-889e-82a7852ae38c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217458447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.4217458447
Directory /workspace/20.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_intr.959655671
Short name T1064
Test name
Test status
Simulation time 40898294684 ps
CPU time 40.17 seconds
Started Jun 09 02:15:54 PM PDT 24
Finished Jun 09 02:16:34 PM PDT 24
Peak memory 200240 kb
Host smart-921d1f53-27b2-4a0b-b7f4-fa1d5d166a36
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959655671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.959655671
Directory /workspace/20.uart_intr/latest

Test location /workspace/coverage/default/20.uart_long_xfer_wo_dly.835823076
Short name T921
Test name
Test status
Simulation time 100182205476 ps
CPU time 448.62 seconds
Started Jun 09 02:15:57 PM PDT 24
Finished Jun 09 02:23:26 PM PDT 24
Peak memory 200320 kb
Host smart-b5bac1df-ddd3-47cf-8748-0965f4c1399f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=835823076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.835823076
Directory /workspace/20.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/20.uart_loopback.2315742847
Short name T621
Test name
Test status
Simulation time 2867928509 ps
CPU time 3.32 seconds
Started Jun 09 02:15:55 PM PDT 24
Finished Jun 09 02:15:59 PM PDT 24
Peak memory 197920 kb
Host smart-b14b439c-67ab-40b2-b611-1a1fd1257e4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315742847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_loopback.2315742847
Directory /workspace/20.uart_loopback/latest

Test location /workspace/coverage/default/20.uart_perf.1529716468
Short name T955
Test name
Test status
Simulation time 13925549211 ps
CPU time 696.51 seconds
Started Jun 09 02:15:57 PM PDT 24
Finished Jun 09 02:27:34 PM PDT 24
Peak memory 200392 kb
Host smart-bc742d0b-5f37-43ec-ba21-f96e8e1d3470
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1529716468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.1529716468
Directory /workspace/20.uart_perf/latest

Test location /workspace/coverage/default/20.uart_rx_oversample.3183067560
Short name T727
Test name
Test status
Simulation time 2200177592 ps
CPU time 1.22 seconds
Started Jun 09 02:15:55 PM PDT 24
Finished Jun 09 02:15:57 PM PDT 24
Peak memory 198700 kb
Host smart-2440918b-34dd-4b95-94c4-f7fd6c58bb92
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3183067560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.3183067560
Directory /workspace/20.uart_rx_oversample/latest

Test location /workspace/coverage/default/20.uart_rx_parity_err.3595494427
Short name T861
Test name
Test status
Simulation time 72047030051 ps
CPU time 98.89 seconds
Started Jun 09 02:15:52 PM PDT 24
Finished Jun 09 02:17:31 PM PDT 24
Peak memory 200412 kb
Host smart-81dc4727-e3ab-4c80-b051-1646eb1f06cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595494427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.3595494427
Directory /workspace/20.uart_rx_parity_err/latest

Test location /workspace/coverage/default/20.uart_rx_start_bit_filter.2615919191
Short name T6
Test name
Test status
Simulation time 33543825934 ps
CPU time 57.69 seconds
Started Jun 09 02:15:54 PM PDT 24
Finished Jun 09 02:16:52 PM PDT 24
Peak memory 196436 kb
Host smart-141fdd83-880f-4d10-a03f-c3d2ea8a22a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615919191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.2615919191
Directory /workspace/20.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/20.uart_smoke.3445932188
Short name T1051
Test name
Test status
Simulation time 912538027 ps
CPU time 1.96 seconds
Started Jun 09 02:15:55 PM PDT 24
Finished Jun 09 02:15:57 PM PDT 24
Peak memory 200244 kb
Host smart-b4dcd3fc-8a36-4881-b4db-1ef8d930e528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445932188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_smoke.3445932188
Directory /workspace/20.uart_smoke/latest

Test location /workspace/coverage/default/20.uart_stress_all_with_rand_reset.1888936245
Short name T104
Test name
Test status
Simulation time 91678136491 ps
CPU time 403.03 seconds
Started Jun 09 02:15:55 PM PDT 24
Finished Jun 09 02:22:38 PM PDT 24
Peak memory 216824 kb
Host smart-70908596-6446-4297-b7c3-4a4733f81d66
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888936245 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 20.uart_stress_all_with_rand_reset.1888936245
Directory /workspace/20.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.uart_tx_ovrd.525527491
Short name T511
Test name
Test status
Simulation time 7263885768 ps
CPU time 10.41 seconds
Started Jun 09 02:15:51 PM PDT 24
Finished Jun 09 02:16:02 PM PDT 24
Peak memory 199828 kb
Host smart-6d4aa55d-ec00-4a63-872c-3f3dd0c42b71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525527491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.525527491
Directory /workspace/20.uart_tx_ovrd/latest

Test location /workspace/coverage/default/20.uart_tx_rx.2215137889
Short name T653
Test name
Test status
Simulation time 9074278464 ps
CPU time 13.51 seconds
Started Jun 09 02:15:56 PM PDT 24
Finished Jun 09 02:16:10 PM PDT 24
Peak memory 199116 kb
Host smart-8c07ae3e-6877-41f3-a24d-58756c5f559e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215137889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.2215137889
Directory /workspace/20.uart_tx_rx/latest

Test location /workspace/coverage/default/200.uart_fifo_reset.4134447542
Short name T483
Test name
Test status
Simulation time 69235269294 ps
CPU time 30.71 seconds
Started Jun 09 02:20:45 PM PDT 24
Finished Jun 09 02:21:16 PM PDT 24
Peak memory 200336 kb
Host smart-e1a0b98a-8f32-42fb-b1d2-ca70cfe5e9ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134447542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.4134447542
Directory /workspace/200.uart_fifo_reset/latest

Test location /workspace/coverage/default/201.uart_fifo_reset.3506334988
Short name T542
Test name
Test status
Simulation time 63796973147 ps
CPU time 137.95 seconds
Started Jun 09 02:20:47 PM PDT 24
Finished Jun 09 02:23:05 PM PDT 24
Peak memory 200372 kb
Host smart-382a1bb1-3948-4092-b2d4-6bc214354f33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506334988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.3506334988
Directory /workspace/201.uart_fifo_reset/latest

Test location /workspace/coverage/default/202.uart_fifo_reset.4071493810
Short name T753
Test name
Test status
Simulation time 60689229806 ps
CPU time 97.16 seconds
Started Jun 09 02:20:46 PM PDT 24
Finished Jun 09 02:22:23 PM PDT 24
Peak memory 200264 kb
Host smart-0147b6a3-4a42-47a7-8120-d291a8287dfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071493810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.4071493810
Directory /workspace/202.uart_fifo_reset/latest

Test location /workspace/coverage/default/203.uart_fifo_reset.773982079
Short name T770
Test name
Test status
Simulation time 152243028202 ps
CPU time 38.26 seconds
Started Jun 09 02:20:44 PM PDT 24
Finished Jun 09 02:21:23 PM PDT 24
Peak memory 200580 kb
Host smart-e46b5cfe-8c6d-4ea0-8159-dcee01fd47c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773982079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.773982079
Directory /workspace/203.uart_fifo_reset/latest

Test location /workspace/coverage/default/204.uart_fifo_reset.4079834045
Short name T982
Test name
Test status
Simulation time 25602070444 ps
CPU time 16.61 seconds
Started Jun 09 02:20:47 PM PDT 24
Finished Jun 09 02:21:04 PM PDT 24
Peak memory 200296 kb
Host smart-83c4d929-4075-44cf-8044-4c95bf9abe5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079834045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.4079834045
Directory /workspace/204.uart_fifo_reset/latest

Test location /workspace/coverage/default/205.uart_fifo_reset.328016612
Short name T1003
Test name
Test status
Simulation time 18847087760 ps
CPU time 33.49 seconds
Started Jun 09 02:20:54 PM PDT 24
Finished Jun 09 02:21:28 PM PDT 24
Peak memory 200316 kb
Host smart-781b2b15-4849-4b15-90d7-b2458514bcfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328016612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.328016612
Directory /workspace/205.uart_fifo_reset/latest

Test location /workspace/coverage/default/207.uart_fifo_reset.114860467
Short name T339
Test name
Test status
Simulation time 8688197843 ps
CPU time 26.66 seconds
Started Jun 09 02:20:53 PM PDT 24
Finished Jun 09 02:21:19 PM PDT 24
Peak memory 200392 kb
Host smart-536df292-4314-4dd8-9ed1-6a53c509b992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114860467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.114860467
Directory /workspace/207.uart_fifo_reset/latest

Test location /workspace/coverage/default/208.uart_fifo_reset.2087106482
Short name T735
Test name
Test status
Simulation time 261947394551 ps
CPU time 60.42 seconds
Started Jun 09 02:20:51 PM PDT 24
Finished Jun 09 02:21:52 PM PDT 24
Peak memory 200296 kb
Host smart-302ee0b6-22d0-492e-bcd1-2a201b4b06f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087106482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.2087106482
Directory /workspace/208.uart_fifo_reset/latest

Test location /workspace/coverage/default/209.uart_fifo_reset.2848207972
Short name T884
Test name
Test status
Simulation time 40045211435 ps
CPU time 65.34 seconds
Started Jun 09 02:20:52 PM PDT 24
Finished Jun 09 02:21:58 PM PDT 24
Peak memory 200320 kb
Host smart-d8544b71-c76f-43fc-9e9e-ae3ad1f83a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848207972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.2848207972
Directory /workspace/209.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_alert_test.3565717965
Short name T520
Test name
Test status
Simulation time 94194844 ps
CPU time 0.58 seconds
Started Jun 09 02:16:04 PM PDT 24
Finished Jun 09 02:16:05 PM PDT 24
Peak memory 195740 kb
Host smart-8844c542-027b-4ba5-8989-b4eab3219435
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565717965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.3565717965
Directory /workspace/21.uart_alert_test/latest

Test location /workspace/coverage/default/21.uart_fifo_full.1088287401
Short name T872
Test name
Test status
Simulation time 102741700956 ps
CPU time 29.93 seconds
Started Jun 09 02:16:00 PM PDT 24
Finished Jun 09 02:16:30 PM PDT 24
Peak memory 200364 kb
Host smart-46aa9b92-cafb-4959-874d-28bb52036a40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088287401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.1088287401
Directory /workspace/21.uart_fifo_full/latest

Test location /workspace/coverage/default/21.uart_fifo_overflow.218729038
Short name T163
Test name
Test status
Simulation time 39825224915 ps
CPU time 16.12 seconds
Started Jun 09 02:15:58 PM PDT 24
Finished Jun 09 02:16:14 PM PDT 24
Peak memory 200320 kb
Host smart-396f248c-f301-4ca8-8f1d-532ba0bbfe42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218729038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.218729038
Directory /workspace/21.uart_fifo_overflow/latest

Test location /workspace/coverage/default/21.uart_fifo_reset.4275018742
Short name T171
Test name
Test status
Simulation time 27393623593 ps
CPU time 43.58 seconds
Started Jun 09 02:15:58 PM PDT 24
Finished Jun 09 02:16:42 PM PDT 24
Peak memory 200352 kb
Host smart-aa39da6c-5509-4c85-8965-1a52401f5e76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275018742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.4275018742
Directory /workspace/21.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_intr.3487906310
Short name T813
Test name
Test status
Simulation time 5555093550 ps
CPU time 9.16 seconds
Started Jun 09 02:15:59 PM PDT 24
Finished Jun 09 02:16:08 PM PDT 24
Peak memory 197244 kb
Host smart-e97fd0df-31a0-4aaa-85e8-d360edfa1465
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487906310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.3487906310
Directory /workspace/21.uart_intr/latest

Test location /workspace/coverage/default/21.uart_long_xfer_wo_dly.464327864
Short name T939
Test name
Test status
Simulation time 69477263929 ps
CPU time 300.21 seconds
Started Jun 09 02:16:02 PM PDT 24
Finished Jun 09 02:21:03 PM PDT 24
Peak memory 200344 kb
Host smart-2532047a-c8be-4ec3-a5b5-0ab53046bce6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=464327864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.464327864
Directory /workspace/21.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/21.uart_loopback.1214401623
Short name T974
Test name
Test status
Simulation time 1139350454 ps
CPU time 2.05 seconds
Started Jun 09 02:16:02 PM PDT 24
Finished Jun 09 02:16:05 PM PDT 24
Peak memory 198864 kb
Host smart-d83d25a2-473a-4930-ab90-a54793e0aaf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214401623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_loopback.1214401623
Directory /workspace/21.uart_loopback/latest

Test location /workspace/coverage/default/21.uart_perf.643253951
Short name T362
Test name
Test status
Simulation time 1668240412 ps
CPU time 96.58 seconds
Started Jun 09 02:16:03 PM PDT 24
Finished Jun 09 02:17:40 PM PDT 24
Peak memory 200260 kb
Host smart-7c9fd798-770a-4a7c-9274-c6d98e4263cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=643253951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.643253951
Directory /workspace/21.uart_perf/latest

Test location /workspace/coverage/default/21.uart_rx_oversample.3186630836
Short name T756
Test name
Test status
Simulation time 3368297734 ps
CPU time 5.74 seconds
Started Jun 09 02:15:58 PM PDT 24
Finished Jun 09 02:16:04 PM PDT 24
Peak memory 198452 kb
Host smart-232d4554-7b43-449e-898f-0b48f9627861
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3186630836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.3186630836
Directory /workspace/21.uart_rx_oversample/latest

Test location /workspace/coverage/default/21.uart_rx_parity_err.1177549480
Short name T18
Test name
Test status
Simulation time 123157907106 ps
CPU time 102.47 seconds
Started Jun 09 02:16:02 PM PDT 24
Finished Jun 09 02:17:45 PM PDT 24
Peak memory 200320 kb
Host smart-2f263064-a83e-4b4e-989c-25364201217b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177549480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.1177549480
Directory /workspace/21.uart_rx_parity_err/latest

Test location /workspace/coverage/default/21.uart_rx_start_bit_filter.1920395170
Short name T816
Test name
Test status
Simulation time 858306584 ps
CPU time 2.08 seconds
Started Jun 09 02:16:05 PM PDT 24
Finished Jun 09 02:16:07 PM PDT 24
Peak memory 195800 kb
Host smart-e73cd64c-5c6e-4815-8c69-bbdec3df77b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920395170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.1920395170
Directory /workspace/21.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/21.uart_smoke.969567482
Short name T1039
Test name
Test status
Simulation time 493209227 ps
CPU time 2.09 seconds
Started Jun 09 02:15:59 PM PDT 24
Finished Jun 09 02:16:01 PM PDT 24
Peak memory 199068 kb
Host smart-aba4cfe8-67a0-4d1f-bef3-941deb73d3d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969567482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_smoke.969567482
Directory /workspace/21.uart_smoke/latest

Test location /workspace/coverage/default/21.uart_stress_all.1833605292
Short name T580
Test name
Test status
Simulation time 820272139640 ps
CPU time 679.43 seconds
Started Jun 09 02:16:03 PM PDT 24
Finished Jun 09 02:27:23 PM PDT 24
Peak memory 200384 kb
Host smart-94267328-6922-4b25-a94c-651f59bf8acf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833605292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.1833605292
Directory /workspace/21.uart_stress_all/latest

Test location /workspace/coverage/default/21.uart_stress_all_with_rand_reset.768842149
Short name T119
Test name
Test status
Simulation time 57450696230 ps
CPU time 702.81 seconds
Started Jun 09 02:16:03 PM PDT 24
Finished Jun 09 02:27:46 PM PDT 24
Peak memory 216940 kb
Host smart-830a5d5b-7744-4f2e-9723-c8f13631f4c9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768842149 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 21.uart_stress_all_with_rand_reset.768842149
Directory /workspace/21.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.uart_tx_ovrd.2214627499
Short name T577
Test name
Test status
Simulation time 1753336935 ps
CPU time 2.11 seconds
Started Jun 09 02:16:02 PM PDT 24
Finished Jun 09 02:16:05 PM PDT 24
Peak memory 199168 kb
Host smart-eb2fe462-745b-4771-90f1-42b01652395d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214627499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.2214627499
Directory /workspace/21.uart_tx_ovrd/latest

Test location /workspace/coverage/default/21.uart_tx_rx.4194622067
Short name T972
Test name
Test status
Simulation time 49703258414 ps
CPU time 42.46 seconds
Started Jun 09 02:16:00 PM PDT 24
Finished Jun 09 02:16:42 PM PDT 24
Peak memory 200408 kb
Host smart-042755ff-b177-4e00-a849-530ba8c28d1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194622067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.4194622067
Directory /workspace/21.uart_tx_rx/latest

Test location /workspace/coverage/default/210.uart_fifo_reset.29310781
Short name T400
Test name
Test status
Simulation time 119243423826 ps
CPU time 203.3 seconds
Started Jun 09 02:20:54 PM PDT 24
Finished Jun 09 02:24:17 PM PDT 24
Peak memory 200328 kb
Host smart-5b8df1df-0fae-4234-b64b-85699ffa3865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29310781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.29310781
Directory /workspace/210.uart_fifo_reset/latest

Test location /workspace/coverage/default/211.uart_fifo_reset.2837940113
Short name T207
Test name
Test status
Simulation time 34414792466 ps
CPU time 29.82 seconds
Started Jun 09 02:20:52 PM PDT 24
Finished Jun 09 02:21:22 PM PDT 24
Peak memory 200076 kb
Host smart-4b0389e4-f2b7-4697-89e4-76a3f659f7b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837940113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.2837940113
Directory /workspace/211.uart_fifo_reset/latest

Test location /workspace/coverage/default/212.uart_fifo_reset.427285438
Short name T50
Test name
Test status
Simulation time 59498859829 ps
CPU time 11.33 seconds
Started Jun 09 02:20:51 PM PDT 24
Finished Jun 09 02:21:03 PM PDT 24
Peak memory 200400 kb
Host smart-f7e031da-26f0-45a6-9303-ad8ee50ebb77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427285438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.427285438
Directory /workspace/212.uart_fifo_reset/latest

Test location /workspace/coverage/default/213.uart_fifo_reset.4018819341
Short name T166
Test name
Test status
Simulation time 22848907741 ps
CPU time 19.46 seconds
Started Jun 09 02:20:51 PM PDT 24
Finished Jun 09 02:21:11 PM PDT 24
Peak memory 200368 kb
Host smart-868c3f85-fd9f-4d4a-9e28-7f6a821f1e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018819341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.4018819341
Directory /workspace/213.uart_fifo_reset/latest

Test location /workspace/coverage/default/214.uart_fifo_reset.2098192742
Short name T588
Test name
Test status
Simulation time 55223922131 ps
CPU time 111.02 seconds
Started Jun 09 02:20:54 PM PDT 24
Finished Jun 09 02:22:45 PM PDT 24
Peak memory 200360 kb
Host smart-e395d0aa-d71d-4598-afdb-29dd9eb11cc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098192742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.2098192742
Directory /workspace/214.uart_fifo_reset/latest

Test location /workspace/coverage/default/216.uart_fifo_reset.3149806492
Short name T182
Test name
Test status
Simulation time 109717289529 ps
CPU time 61.56 seconds
Started Jun 09 02:20:53 PM PDT 24
Finished Jun 09 02:21:54 PM PDT 24
Peak memory 200328 kb
Host smart-e8a2723f-2135-4f00-b60c-75ec58d4364d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149806492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.3149806492
Directory /workspace/216.uart_fifo_reset/latest

Test location /workspace/coverage/default/217.uart_fifo_reset.2858706908
Short name T548
Test name
Test status
Simulation time 30319505976 ps
CPU time 11.28 seconds
Started Jun 09 02:20:56 PM PDT 24
Finished Jun 09 02:21:08 PM PDT 24
Peak memory 200396 kb
Host smart-9607c7e3-55a2-4420-960d-5852216fb742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858706908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.2858706908
Directory /workspace/217.uart_fifo_reset/latest

Test location /workspace/coverage/default/218.uart_fifo_reset.1685553966
Short name T1010
Test name
Test status
Simulation time 118108680105 ps
CPU time 310.96 seconds
Started Jun 09 02:20:56 PM PDT 24
Finished Jun 09 02:26:08 PM PDT 24
Peak memory 200280 kb
Host smart-be4d11a0-526f-4ee9-9134-4a2520c97b8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685553966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.1685553966
Directory /workspace/218.uart_fifo_reset/latest

Test location /workspace/coverage/default/219.uart_fifo_reset.4131010618
Short name T731
Test name
Test status
Simulation time 17959803913 ps
CPU time 26.85 seconds
Started Jun 09 02:20:56 PM PDT 24
Finished Jun 09 02:21:23 PM PDT 24
Peak memory 200308 kb
Host smart-b60874b8-07f3-495d-9b7f-a565aa34ed9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131010618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.4131010618
Directory /workspace/219.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_alert_test.2036650748
Short name T461
Test name
Test status
Simulation time 11815699 ps
CPU time 0.52 seconds
Started Jun 09 02:16:13 PM PDT 24
Finished Jun 09 02:16:14 PM PDT 24
Peak memory 195208 kb
Host smart-d37a82ea-e7ab-452e-b5b6-89f7875179ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036650748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.2036650748
Directory /workspace/22.uart_alert_test/latest

Test location /workspace/coverage/default/22.uart_fifo_full.2712934106
Short name T758
Test name
Test status
Simulation time 113241722943 ps
CPU time 212.29 seconds
Started Jun 09 02:16:03 PM PDT 24
Finished Jun 09 02:19:36 PM PDT 24
Peak memory 200364 kb
Host smart-725bc754-7b74-44f3-9243-028d6664d3a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712934106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.2712934106
Directory /workspace/22.uart_fifo_full/latest

Test location /workspace/coverage/default/22.uart_fifo_overflow.1037670715
Short name T408
Test name
Test status
Simulation time 49704724898 ps
CPU time 16.28 seconds
Started Jun 09 02:16:07 PM PDT 24
Finished Jun 09 02:16:23 PM PDT 24
Peak memory 200380 kb
Host smart-51ff69da-dc7d-4efe-baf8-796b2e6ee3e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037670715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.1037670715
Directory /workspace/22.uart_fifo_overflow/latest

Test location /workspace/coverage/default/22.uart_fifo_reset.3074898299
Short name T1063
Test name
Test status
Simulation time 79015180891 ps
CPU time 29.59 seconds
Started Jun 09 02:16:06 PM PDT 24
Finished Jun 09 02:16:36 PM PDT 24
Peak memory 200332 kb
Host smart-503a2506-b10f-483c-a5d5-7df2b6b3fcf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074898299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.3074898299
Directory /workspace/22.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_intr.590680637
Short name T258
Test name
Test status
Simulation time 175031940579 ps
CPU time 142.68 seconds
Started Jun 09 02:16:07 PM PDT 24
Finished Jun 09 02:18:30 PM PDT 24
Peak memory 199980 kb
Host smart-97de448c-0361-4886-8aaa-dab5d6523595
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590680637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.590680637
Directory /workspace/22.uart_intr/latest

Test location /workspace/coverage/default/22.uart_long_xfer_wo_dly.3845969198
Short name T1024
Test name
Test status
Simulation time 118391932302 ps
CPU time 149.06 seconds
Started Jun 09 02:16:09 PM PDT 24
Finished Jun 09 02:18:38 PM PDT 24
Peak memory 200588 kb
Host smart-d6544448-f91e-46fb-9ad0-6b55ec8e6666
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3845969198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.3845969198
Directory /workspace/22.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/22.uart_loopback.3712169219
Short name T688
Test name
Test status
Simulation time 8271981543 ps
CPU time 6.94 seconds
Started Jun 09 02:16:08 PM PDT 24
Finished Jun 09 02:16:15 PM PDT 24
Peak memory 200028 kb
Host smart-4f155294-ebad-49f5-b7c2-28ef5d273af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712169219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_loopback.3712169219
Directory /workspace/22.uart_loopback/latest

Test location /workspace/coverage/default/22.uart_perf.3647999934
Short name T867
Test name
Test status
Simulation time 18093421759 ps
CPU time 517.88 seconds
Started Jun 09 02:16:06 PM PDT 24
Finished Jun 09 02:24:45 PM PDT 24
Peak memory 200292 kb
Host smart-f2bc1f2b-ca47-4b19-8c00-bc4c6385e5dc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3647999934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.3647999934
Directory /workspace/22.uart_perf/latest

Test location /workspace/coverage/default/22.uart_rx_oversample.3828725523
Short name T350
Test name
Test status
Simulation time 7505967558 ps
CPU time 65.69 seconds
Started Jun 09 02:16:06 PM PDT 24
Finished Jun 09 02:17:13 PM PDT 24
Peak memory 199644 kb
Host smart-67820000-cd3a-4b0d-80d1-a5752b94f099
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3828725523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.3828725523
Directory /workspace/22.uart_rx_oversample/latest

Test location /workspace/coverage/default/22.uart_rx_parity_err.3514639607
Short name T312
Test name
Test status
Simulation time 73415263216 ps
CPU time 123.32 seconds
Started Jun 09 02:16:08 PM PDT 24
Finished Jun 09 02:18:12 PM PDT 24
Peak memory 200344 kb
Host smart-2b19d964-d06a-4163-8da4-2af86a2a3d64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514639607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.3514639607
Directory /workspace/22.uart_rx_parity_err/latest

Test location /workspace/coverage/default/22.uart_rx_start_bit_filter.1778710412
Short name T559
Test name
Test status
Simulation time 4095098755 ps
CPU time 3.91 seconds
Started Jun 09 02:16:08 PM PDT 24
Finished Jun 09 02:16:12 PM PDT 24
Peak memory 196408 kb
Host smart-24305546-bf59-4292-a604-ab93d6092590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778710412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.1778710412
Directory /workspace/22.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/22.uart_smoke.3179438990
Short name T827
Test name
Test status
Simulation time 316589849 ps
CPU time 1.12 seconds
Started Jun 09 02:16:03 PM PDT 24
Finished Jun 09 02:16:04 PM PDT 24
Peak memory 198956 kb
Host smart-4cacb716-f56c-4592-b2d3-e14397923db8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179438990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_smoke.3179438990
Directory /workspace/22.uart_smoke/latest

Test location /workspace/coverage/default/22.uart_stress_all.3920909768
Short name T712
Test name
Test status
Simulation time 189464641181 ps
CPU time 127.19 seconds
Started Jun 09 02:16:07 PM PDT 24
Finished Jun 09 02:18:15 PM PDT 24
Peak memory 200412 kb
Host smart-55691893-5040-4385-8c61-0790e54d565c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920909768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.3920909768
Directory /workspace/22.uart_stress_all/latest

Test location /workspace/coverage/default/22.uart_tx_ovrd.1856363571
Short name T796
Test name
Test status
Simulation time 1409813447 ps
CPU time 2.68 seconds
Started Jun 09 02:16:09 PM PDT 24
Finished Jun 09 02:16:12 PM PDT 24
Peak memory 198932 kb
Host smart-74a92e87-3f0b-498c-b158-02fc15bb8fb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856363571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.1856363571
Directory /workspace/22.uart_tx_ovrd/latest

Test location /workspace/coverage/default/22.uart_tx_rx.1332115472
Short name T536
Test name
Test status
Simulation time 49200139440 ps
CPU time 35.56 seconds
Started Jun 09 02:16:02 PM PDT 24
Finished Jun 09 02:16:38 PM PDT 24
Peak memory 200384 kb
Host smart-8f595cdc-4cdf-46ef-bc3c-de174146a6e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332115472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.1332115472
Directory /workspace/22.uart_tx_rx/latest

Test location /workspace/coverage/default/220.uart_fifo_reset.476985126
Short name T837
Test name
Test status
Simulation time 145404890438 ps
CPU time 213.43 seconds
Started Jun 09 02:20:55 PM PDT 24
Finished Jun 09 02:24:28 PM PDT 24
Peak memory 200392 kb
Host smart-16b63247-b1bb-46a4-b3e4-607efb8488b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476985126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.476985126
Directory /workspace/220.uart_fifo_reset/latest

Test location /workspace/coverage/default/221.uart_fifo_reset.1707667366
Short name T332
Test name
Test status
Simulation time 18127250022 ps
CPU time 19.34 seconds
Started Jun 09 02:20:55 PM PDT 24
Finished Jun 09 02:21:15 PM PDT 24
Peak memory 200376 kb
Host smart-1aa7ee08-2dc6-42ad-a47c-09856c6372c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707667366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.1707667366
Directory /workspace/221.uart_fifo_reset/latest

Test location /workspace/coverage/default/222.uart_fifo_reset.4099645673
Short name T529
Test name
Test status
Simulation time 10399962200 ps
CPU time 13.59 seconds
Started Jun 09 02:20:56 PM PDT 24
Finished Jun 09 02:21:10 PM PDT 24
Peak memory 200392 kb
Host smart-f88b6dee-dba2-44c5-8d8c-8b2d706ac80e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099645673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.4099645673
Directory /workspace/222.uart_fifo_reset/latest

Test location /workspace/coverage/default/223.uart_fifo_reset.4197686064
Short name T961
Test name
Test status
Simulation time 9923673242 ps
CPU time 20.06 seconds
Started Jun 09 02:20:59 PM PDT 24
Finished Jun 09 02:21:19 PM PDT 24
Peak memory 200392 kb
Host smart-4dc1b164-2315-4ee6-8044-7746ff8c627f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197686064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.4197686064
Directory /workspace/223.uart_fifo_reset/latest

Test location /workspace/coverage/default/224.uart_fifo_reset.811988722
Short name T172
Test name
Test status
Simulation time 55613360352 ps
CPU time 26.28 seconds
Started Jun 09 02:20:56 PM PDT 24
Finished Jun 09 02:21:22 PM PDT 24
Peak memory 200340 kb
Host smart-45e3d7ac-d381-49e4-a8e5-5d530ce38214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811988722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.811988722
Directory /workspace/224.uart_fifo_reset/latest

Test location /workspace/coverage/default/225.uart_fifo_reset.3934733855
Short name T544
Test name
Test status
Simulation time 16125410846 ps
CPU time 34.81 seconds
Started Jun 09 02:20:55 PM PDT 24
Finished Jun 09 02:21:30 PM PDT 24
Peak memory 200352 kb
Host smart-8443845c-376f-4df8-b3ae-3fb3eecc2cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934733855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.3934733855
Directory /workspace/225.uart_fifo_reset/latest

Test location /workspace/coverage/default/226.uart_fifo_reset.2957215742
Short name T367
Test name
Test status
Simulation time 11265121786 ps
CPU time 18.2 seconds
Started Jun 09 02:20:54 PM PDT 24
Finished Jun 09 02:21:12 PM PDT 24
Peak memory 200132 kb
Host smart-852b75d3-8f4b-4fa5-a49a-13168867c54a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957215742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.2957215742
Directory /workspace/226.uart_fifo_reset/latest

Test location /workspace/coverage/default/227.uart_fifo_reset.3888385300
Short name T916
Test name
Test status
Simulation time 140078270193 ps
CPU time 51.82 seconds
Started Jun 09 02:20:59 PM PDT 24
Finished Jun 09 02:21:51 PM PDT 24
Peak memory 200356 kb
Host smart-39269297-84e6-4970-83c2-4012013ff55d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888385300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.3888385300
Directory /workspace/227.uart_fifo_reset/latest

Test location /workspace/coverage/default/228.uart_fifo_reset.3712976064
Short name T739
Test name
Test status
Simulation time 22840461768 ps
CPU time 36.88 seconds
Started Jun 09 02:20:57 PM PDT 24
Finished Jun 09 02:21:34 PM PDT 24
Peak memory 200344 kb
Host smart-04ee4576-b28f-42f6-89ac-0dc47aa820cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712976064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.3712976064
Directory /workspace/228.uart_fifo_reset/latest

Test location /workspace/coverage/default/229.uart_fifo_reset.126428669
Short name T158
Test name
Test status
Simulation time 98886867518 ps
CPU time 44.83 seconds
Started Jun 09 02:21:02 PM PDT 24
Finished Jun 09 02:21:47 PM PDT 24
Peak memory 200176 kb
Host smart-9d1a16eb-9d96-45d7-847e-a7d572213626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126428669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.126428669
Directory /workspace/229.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_alert_test.998671210
Short name T26
Test name
Test status
Simulation time 71039331 ps
CPU time 0.57 seconds
Started Jun 09 02:16:18 PM PDT 24
Finished Jun 09 02:16:18 PM PDT 24
Peak memory 195984 kb
Host smart-468d4bad-7114-4123-9cd1-01e0909b3150
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998671210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.998671210
Directory /workspace/23.uart_alert_test/latest

Test location /workspace/coverage/default/23.uart_fifo_full.2187601233
Short name T563
Test name
Test status
Simulation time 43083945663 ps
CPU time 68.11 seconds
Started Jun 09 02:16:12 PM PDT 24
Finished Jun 09 02:17:20 PM PDT 24
Peak memory 200420 kb
Host smart-bb5a7b4c-8e95-4d1c-b007-b97b99dc6389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187601233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.2187601233
Directory /workspace/23.uart_fifo_full/latest

Test location /workspace/coverage/default/23.uart_fifo_overflow.4268237156
Short name T268
Test name
Test status
Simulation time 67731200923 ps
CPU time 77.86 seconds
Started Jun 09 02:16:13 PM PDT 24
Finished Jun 09 02:17:32 PM PDT 24
Peak memory 199916 kb
Host smart-76bfbca5-3865-443a-b562-bfa9f61da761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268237156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.4268237156
Directory /workspace/23.uart_fifo_overflow/latest

Test location /workspace/coverage/default/23.uart_fifo_reset.2758348768
Short name T206
Test name
Test status
Simulation time 29511536490 ps
CPU time 12.09 seconds
Started Jun 09 02:16:12 PM PDT 24
Finished Jun 09 02:16:25 PM PDT 24
Peak memory 200312 kb
Host smart-0ca93523-dff3-4a5d-9043-3bf5c27f43cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758348768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.2758348768
Directory /workspace/23.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_intr.3354820879
Short name T576
Test name
Test status
Simulation time 9135307442 ps
CPU time 8.75 seconds
Started Jun 09 02:16:13 PM PDT 24
Finished Jun 09 02:16:22 PM PDT 24
Peak memory 197020 kb
Host smart-817fa7d9-98b9-4eea-bafa-9408d78e9866
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354820879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.3354820879
Directory /workspace/23.uart_intr/latest

Test location /workspace/coverage/default/23.uart_long_xfer_wo_dly.621869982
Short name T1033
Test name
Test status
Simulation time 165829024333 ps
CPU time 1118.18 seconds
Started Jun 09 02:16:20 PM PDT 24
Finished Jun 09 02:34:58 PM PDT 24
Peak memory 200384 kb
Host smart-68f555d9-2d27-461b-b721-c6dc662282cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=621869982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.621869982
Directory /workspace/23.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/23.uart_loopback.4062593831
Short name T19
Test name
Test status
Simulation time 4094989590 ps
CPU time 9.48 seconds
Started Jun 09 02:16:14 PM PDT 24
Finished Jun 09 02:16:23 PM PDT 24
Peak memory 199476 kb
Host smart-fe5f7640-02d6-4a02-9113-c4f39a0806dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062593831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_loopback.4062593831
Directory /workspace/23.uart_loopback/latest

Test location /workspace/coverage/default/23.uart_perf.3444479191
Short name T683
Test name
Test status
Simulation time 8819716286 ps
CPU time 120.38 seconds
Started Jun 09 02:16:18 PM PDT 24
Finished Jun 09 02:18:18 PM PDT 24
Peak memory 200332 kb
Host smart-e3aeacd6-210a-4072-a2f7-df292029692c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3444479191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.3444479191
Directory /workspace/23.uart_perf/latest

Test location /workspace/coverage/default/23.uart_rx_oversample.1494223234
Short name T768
Test name
Test status
Simulation time 3737570969 ps
CPU time 13.09 seconds
Started Jun 09 02:16:14 PM PDT 24
Finished Jun 09 02:16:27 PM PDT 24
Peak memory 199484 kb
Host smart-267afcb8-ec5f-4a07-9bc0-774b04901b42
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1494223234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.1494223234
Directory /workspace/23.uart_rx_oversample/latest

Test location /workspace/coverage/default/23.uart_rx_parity_err.3171736487
Short name T410
Test name
Test status
Simulation time 105505180426 ps
CPU time 20.69 seconds
Started Jun 09 02:16:21 PM PDT 24
Finished Jun 09 02:16:42 PM PDT 24
Peak memory 200288 kb
Host smart-d25db995-bc43-4c05-b330-bca8e4356d13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171736487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.3171736487
Directory /workspace/23.uart_rx_parity_err/latest

Test location /workspace/coverage/default/23.uart_rx_start_bit_filter.848528010
Short name T316
Test name
Test status
Simulation time 3120033455 ps
CPU time 1.56 seconds
Started Jun 09 02:16:14 PM PDT 24
Finished Jun 09 02:16:16 PM PDT 24
Peak memory 196320 kb
Host smart-8d2b7ccb-9817-459f-b7a6-60c37f76238f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848528010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.848528010
Directory /workspace/23.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/23.uart_smoke.3458940253
Short name T526
Test name
Test status
Simulation time 303225223 ps
CPU time 1.14 seconds
Started Jun 09 02:16:13 PM PDT 24
Finished Jun 09 02:16:14 PM PDT 24
Peak memory 198936 kb
Host smart-ba090409-bcb6-4603-a0c2-fc24ca772951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458940253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_smoke.3458940253
Directory /workspace/23.uart_smoke/latest

Test location /workspace/coverage/default/23.uart_stress_all.1352020903
Short name T716
Test name
Test status
Simulation time 279092488094 ps
CPU time 57.09 seconds
Started Jun 09 02:16:22 PM PDT 24
Finished Jun 09 02:17:20 PM PDT 24
Peak memory 200344 kb
Host smart-22fdbe3a-e3c9-4652-b195-ed97c6b3b728
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352020903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.1352020903
Directory /workspace/23.uart_stress_all/latest

Test location /workspace/coverage/default/23.uart_stress_all_with_rand_reset.2785620583
Short name T148
Test name
Test status
Simulation time 46858390620 ps
CPU time 565.23 seconds
Started Jun 09 02:16:23 PM PDT 24
Finished Jun 09 02:25:49 PM PDT 24
Peak memory 213316 kb
Host smart-2e286f37-9af7-4f3f-adfa-ae813f0e2fda
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785620583 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 23.uart_stress_all_with_rand_reset.2785620583
Directory /workspace/23.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.uart_tx_ovrd.599378536
Short name T401
Test name
Test status
Simulation time 3139587727 ps
CPU time 2.3 seconds
Started Jun 09 02:16:12 PM PDT 24
Finished Jun 09 02:16:14 PM PDT 24
Peak memory 198988 kb
Host smart-d3895dee-b4fd-4384-9d29-f222fb122ff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599378536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.599378536
Directory /workspace/23.uart_tx_ovrd/latest

Test location /workspace/coverage/default/23.uart_tx_rx.1283871875
Short name T819
Test name
Test status
Simulation time 39169948239 ps
CPU time 61.73 seconds
Started Jun 09 02:16:16 PM PDT 24
Finished Jun 09 02:17:18 PM PDT 24
Peak memory 200320 kb
Host smart-fddbf194-f4b6-427c-8b3d-3e49c67da278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283871875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.1283871875
Directory /workspace/23.uart_tx_rx/latest

Test location /workspace/coverage/default/230.uart_fifo_reset.1012846871
Short name T754
Test name
Test status
Simulation time 251687803661 ps
CPU time 161.61 seconds
Started Jun 09 02:21:01 PM PDT 24
Finished Jun 09 02:23:43 PM PDT 24
Peak memory 200300 kb
Host smart-cb6e5d9a-12bd-41f7-89b7-02ec2532244c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012846871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.1012846871
Directory /workspace/230.uart_fifo_reset/latest

Test location /workspace/coverage/default/231.uart_fifo_reset.742381065
Short name T607
Test name
Test status
Simulation time 249241580687 ps
CPU time 22.37 seconds
Started Jun 09 02:20:58 PM PDT 24
Finished Jun 09 02:21:20 PM PDT 24
Peak memory 200224 kb
Host smart-777234e7-ddfc-4488-8c9c-99a4517febdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742381065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.742381065
Directory /workspace/231.uart_fifo_reset/latest

Test location /workspace/coverage/default/232.uart_fifo_reset.2911628919
Short name T534
Test name
Test status
Simulation time 47420322131 ps
CPU time 93.61 seconds
Started Jun 09 02:21:02 PM PDT 24
Finished Jun 09 02:22:36 PM PDT 24
Peak memory 200372 kb
Host smart-ab4db664-794d-4a34-a732-a35c5335a462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911628919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.2911628919
Directory /workspace/232.uart_fifo_reset/latest

Test location /workspace/coverage/default/233.uart_fifo_reset.2473966292
Short name T197
Test name
Test status
Simulation time 29237903399 ps
CPU time 44.68 seconds
Started Jun 09 02:21:01 PM PDT 24
Finished Jun 09 02:21:46 PM PDT 24
Peak memory 200304 kb
Host smart-8d7dd41e-9600-467a-8def-27c643160d8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473966292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.2473966292
Directory /workspace/233.uart_fifo_reset/latest

Test location /workspace/coverage/default/234.uart_fifo_reset.3954250408
Short name T1071
Test name
Test status
Simulation time 54922386625 ps
CPU time 27.65 seconds
Started Jun 09 02:21:01 PM PDT 24
Finished Jun 09 02:21:28 PM PDT 24
Peak memory 200340 kb
Host smart-391ae268-450c-43a0-bef5-955eeff43bdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954250408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.3954250408
Directory /workspace/234.uart_fifo_reset/latest

Test location /workspace/coverage/default/235.uart_fifo_reset.3068961054
Short name T219
Test name
Test status
Simulation time 176843036811 ps
CPU time 276.56 seconds
Started Jun 09 02:21:01 PM PDT 24
Finished Jun 09 02:25:38 PM PDT 24
Peak memory 200300 kb
Host smart-90afbfe5-3a08-48fa-90cd-118e885b4057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068961054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.3068961054
Directory /workspace/235.uart_fifo_reset/latest

Test location /workspace/coverage/default/236.uart_fifo_reset.888047729
Short name T251
Test name
Test status
Simulation time 26605255577 ps
CPU time 58.47 seconds
Started Jun 09 02:21:01 PM PDT 24
Finished Jun 09 02:22:00 PM PDT 24
Peak memory 200268 kb
Host smart-50f66c6e-9019-4c19-ba3c-9aad9a481dff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888047729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.888047729
Directory /workspace/236.uart_fifo_reset/latest

Test location /workspace/coverage/default/238.uart_fifo_reset.4270011667
Short name T862
Test name
Test status
Simulation time 20412061375 ps
CPU time 29.9 seconds
Started Jun 09 02:21:00 PM PDT 24
Finished Jun 09 02:21:30 PM PDT 24
Peak memory 200376 kb
Host smart-133d0a0f-32e7-4624-b485-d985d0a0dd90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270011667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.4270011667
Directory /workspace/238.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_alert_test.2456619376
Short name T691
Test name
Test status
Simulation time 67264636 ps
CPU time 0.54 seconds
Started Jun 09 02:16:25 PM PDT 24
Finished Jun 09 02:16:26 PM PDT 24
Peak memory 196024 kb
Host smart-80cff22c-9634-4f89-b4bc-35b9c37f6a4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456619376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.2456619376
Directory /workspace/24.uart_alert_test/latest

Test location /workspace/coverage/default/24.uart_fifo_full.446017253
Short name T284
Test name
Test status
Simulation time 19242106377 ps
CPU time 15.5 seconds
Started Jun 09 02:16:19 PM PDT 24
Finished Jun 09 02:16:35 PM PDT 24
Peak memory 199652 kb
Host smart-2e91e013-cff0-40f5-b879-218478aa2ebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446017253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.446017253
Directory /workspace/24.uart_fifo_full/latest

Test location /workspace/coverage/default/24.uart_fifo_overflow.1798151437
Short name T159
Test name
Test status
Simulation time 16936232241 ps
CPU time 7.74 seconds
Started Jun 09 02:16:18 PM PDT 24
Finished Jun 09 02:16:26 PM PDT 24
Peak memory 199752 kb
Host smart-9f2b6b45-e270-4cd2-a802-d97932db33e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798151437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.1798151437
Directory /workspace/24.uart_fifo_overflow/latest

Test location /workspace/coverage/default/24.uart_fifo_reset.461910604
Short name T433
Test name
Test status
Simulation time 100983145003 ps
CPU time 9.75 seconds
Started Jun 09 02:16:18 PM PDT 24
Finished Jun 09 02:16:28 PM PDT 24
Peak memory 200364 kb
Host smart-3336e93d-29d0-46a9-9fdb-98846fe9f542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461910604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.461910604
Directory /workspace/24.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_intr.1917732800
Short name T404
Test name
Test status
Simulation time 57468747695 ps
CPU time 25.03 seconds
Started Jun 09 02:16:19 PM PDT 24
Finished Jun 09 02:16:44 PM PDT 24
Peak memory 200356 kb
Host smart-9168923a-7674-4428-903d-48c8b6c8a4cd
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917732800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.1917732800
Directory /workspace/24.uart_intr/latest

Test location /workspace/coverage/default/24.uart_long_xfer_wo_dly.1544885229
Short name T775
Test name
Test status
Simulation time 112839841301 ps
CPU time 430.22 seconds
Started Jun 09 02:16:26 PM PDT 24
Finished Jun 09 02:23:37 PM PDT 24
Peak memory 200388 kb
Host smart-aac79e54-735e-41bd-8f1e-7b5c1d39132d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1544885229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.1544885229
Directory /workspace/24.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/24.uart_loopback.1693107929
Short name T1008
Test name
Test status
Simulation time 9520101144 ps
CPU time 7.13 seconds
Started Jun 09 02:16:22 PM PDT 24
Finished Jun 09 02:16:30 PM PDT 24
Peak memory 200316 kb
Host smart-aad0e8e3-3463-468b-a178-e77af8ff1653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693107929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_loopback.1693107929
Directory /workspace/24.uart_loopback/latest

Test location /workspace/coverage/default/24.uart_perf.2501098636
Short name T681
Test name
Test status
Simulation time 18814122124 ps
CPU time 307.88 seconds
Started Jun 09 02:16:23 PM PDT 24
Finished Jun 09 02:21:32 PM PDT 24
Peak memory 200384 kb
Host smart-852398b4-4f03-4f3b-b3d7-351a13017294
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2501098636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.2501098636
Directory /workspace/24.uart_perf/latest

Test location /workspace/coverage/default/24.uart_rx_oversample.1867946034
Short name T15
Test name
Test status
Simulation time 2420644966 ps
CPU time 7.2 seconds
Started Jun 09 02:16:18 PM PDT 24
Finished Jun 09 02:16:26 PM PDT 24
Peak memory 199304 kb
Host smart-088ec050-47e4-4a0b-90e0-d50ca719c4d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1867946034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.1867946034
Directory /workspace/24.uart_rx_oversample/latest

Test location /workspace/coverage/default/24.uart_rx_parity_err.1253462546
Short name T645
Test name
Test status
Simulation time 61043003184 ps
CPU time 8.58 seconds
Started Jun 09 02:16:19 PM PDT 24
Finished Jun 09 02:16:28 PM PDT 24
Peak memory 200372 kb
Host smart-392cfa7e-dfe6-4905-9588-644e5de3ab52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253462546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.1253462546
Directory /workspace/24.uart_rx_parity_err/latest

Test location /workspace/coverage/default/24.uart_rx_start_bit_filter.2681146426
Short name T386
Test name
Test status
Simulation time 6724115255 ps
CPU time 6.46 seconds
Started Jun 09 02:16:20 PM PDT 24
Finished Jun 09 02:16:26 PM PDT 24
Peak memory 196676 kb
Host smart-46cf9db7-d493-4a66-9f0f-94c3ace5b225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681146426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.2681146426
Directory /workspace/24.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/24.uart_smoke.1573144153
Short name T999
Test name
Test status
Simulation time 336458217 ps
CPU time 1.12 seconds
Started Jun 09 02:16:23 PM PDT 24
Finished Jun 09 02:16:24 PM PDT 24
Peak memory 198636 kb
Host smart-15989b44-0f03-4adf-94f3-20922e8cab12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573144153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_smoke.1573144153
Directory /workspace/24.uart_smoke/latest

Test location /workspace/coverage/default/24.uart_stress_all.2043052848
Short name T390
Test name
Test status
Simulation time 106623163947 ps
CPU time 255.69 seconds
Started Jun 09 02:16:27 PM PDT 24
Finished Jun 09 02:20:43 PM PDT 24
Peak memory 200324 kb
Host smart-25edeb7a-dc73-415b-9751-93fb5ca86d1f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043052848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.2043052848
Directory /workspace/24.uart_stress_all/latest

Test location /workspace/coverage/default/24.uart_stress_all_with_rand_reset.3275421871
Short name T1045
Test name
Test status
Simulation time 83678536043 ps
CPU time 1025.66 seconds
Started Jun 09 02:16:22 PM PDT 24
Finished Jun 09 02:33:28 PM PDT 24
Peak memory 225048 kb
Host smart-33e2324a-86f0-4435-9cde-86d5fc312ba4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275421871 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 24.uart_stress_all_with_rand_reset.3275421871
Directory /workspace/24.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.uart_tx_ovrd.1525659091
Short name T487
Test name
Test status
Simulation time 309999708 ps
CPU time 1.3 seconds
Started Jun 09 02:16:21 PM PDT 24
Finished Jun 09 02:16:22 PM PDT 24
Peak memory 197164 kb
Host smart-6e55b9d1-28a0-469e-bbb0-1e2487b40afb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525659091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.1525659091
Directory /workspace/24.uart_tx_ovrd/latest

Test location /workspace/coverage/default/24.uart_tx_rx.3194977147
Short name T995
Test name
Test status
Simulation time 19409193167 ps
CPU time 32.74 seconds
Started Jun 09 02:16:23 PM PDT 24
Finished Jun 09 02:16:56 PM PDT 24
Peak memory 200392 kb
Host smart-cf5617a4-cb4a-46f1-b98f-4fdc8cc35307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194977147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.3194977147
Directory /workspace/24.uart_tx_rx/latest

Test location /workspace/coverage/default/240.uart_fifo_reset.420087714
Short name T714
Test name
Test status
Simulation time 4474444125 ps
CPU time 7.81 seconds
Started Jun 09 02:21:00 PM PDT 24
Finished Jun 09 02:21:08 PM PDT 24
Peak memory 200196 kb
Host smart-7d9cf490-d3c3-44a0-bcf9-8c09545e3ebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420087714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.420087714
Directory /workspace/240.uart_fifo_reset/latest

Test location /workspace/coverage/default/241.uart_fifo_reset.3988435850
Short name T149
Test name
Test status
Simulation time 169113327206 ps
CPU time 96.3 seconds
Started Jun 09 02:21:01 PM PDT 24
Finished Jun 09 02:22:38 PM PDT 24
Peak memory 200300 kb
Host smart-6f434e43-08e5-489d-8cde-1e3ef8d1e728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988435850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.3988435850
Directory /workspace/241.uart_fifo_reset/latest

Test location /workspace/coverage/default/242.uart_fifo_reset.2615190832
Short name T707
Test name
Test status
Simulation time 283623425268 ps
CPU time 77.69 seconds
Started Jun 09 02:20:59 PM PDT 24
Finished Jun 09 02:22:17 PM PDT 24
Peak memory 200236 kb
Host smart-96fab3d0-307b-4852-b8eb-21568cfe0261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615190832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.2615190832
Directory /workspace/242.uart_fifo_reset/latest

Test location /workspace/coverage/default/243.uart_fifo_reset.1278677472
Short name T527
Test name
Test status
Simulation time 269755834562 ps
CPU time 30.32 seconds
Started Jun 09 02:21:00 PM PDT 24
Finished Jun 09 02:21:31 PM PDT 24
Peak memory 200284 kb
Host smart-bade3af9-c653-4c24-a073-e2c06efed8e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278677472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.1278677472
Directory /workspace/243.uart_fifo_reset/latest

Test location /workspace/coverage/default/244.uart_fifo_reset.476771176
Short name T879
Test name
Test status
Simulation time 169029392992 ps
CPU time 351.6 seconds
Started Jun 09 02:21:05 PM PDT 24
Finished Jun 09 02:26:57 PM PDT 24
Peak memory 200408 kb
Host smart-674f7fc1-9d58-474b-b48b-9eb2d5f74e86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476771176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.476771176
Directory /workspace/244.uart_fifo_reset/latest

Test location /workspace/coverage/default/245.uart_fifo_reset.647288459
Short name T637
Test name
Test status
Simulation time 34215224102 ps
CPU time 20.34 seconds
Started Jun 09 02:21:03 PM PDT 24
Finished Jun 09 02:21:24 PM PDT 24
Peak memory 200432 kb
Host smart-facef13c-ac5f-4c5e-84ec-0afdb1704088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647288459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.647288459
Directory /workspace/245.uart_fifo_reset/latest

Test location /workspace/coverage/default/246.uart_fifo_reset.362729922
Short name T337
Test name
Test status
Simulation time 117559813964 ps
CPU time 180.05 seconds
Started Jun 09 02:21:04 PM PDT 24
Finished Jun 09 02:24:04 PM PDT 24
Peak memory 200420 kb
Host smart-a55875bb-3d23-4eca-bb3a-d3aaedb5c523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362729922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.362729922
Directory /workspace/246.uart_fifo_reset/latest

Test location /workspace/coverage/default/247.uart_fifo_reset.4181460402
Short name T43
Test name
Test status
Simulation time 149406253714 ps
CPU time 33.32 seconds
Started Jun 09 02:21:07 PM PDT 24
Finished Jun 09 02:21:40 PM PDT 24
Peak memory 200304 kb
Host smart-e8507601-0f55-4dcd-b508-35b90508591c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181460402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.4181460402
Directory /workspace/247.uart_fifo_reset/latest

Test location /workspace/coverage/default/248.uart_fifo_reset.1148360770
Short name T479
Test name
Test status
Simulation time 71269959867 ps
CPU time 27.68 seconds
Started Jun 09 02:21:06 PM PDT 24
Finished Jun 09 02:21:34 PM PDT 24
Peak memory 200328 kb
Host smart-07affae0-fd54-42ca-86a6-7223b01a4a41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148360770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.1148360770
Directory /workspace/248.uart_fifo_reset/latest

Test location /workspace/coverage/default/249.uart_fifo_reset.3801032151
Short name T830
Test name
Test status
Simulation time 50762451100 ps
CPU time 138.93 seconds
Started Jun 09 02:21:04 PM PDT 24
Finished Jun 09 02:23:23 PM PDT 24
Peak memory 200400 kb
Host smart-bdf8b9d3-dd34-479b-a444-6d022d99ef61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801032151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.3801032151
Directory /workspace/249.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_alert_test.1675135276
Short name T27
Test name
Test status
Simulation time 75814724 ps
CPU time 0.56 seconds
Started Jun 09 02:16:32 PM PDT 24
Finished Jun 09 02:16:33 PM PDT 24
Peak memory 195732 kb
Host smart-9d43b7ab-d784-4f73-bdb4-0909f242f638
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675135276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.1675135276
Directory /workspace/25.uart_alert_test/latest

Test location /workspace/coverage/default/25.uart_fifo_full.2969070819
Short name T286
Test name
Test status
Simulation time 116147228080 ps
CPU time 188.03 seconds
Started Jun 09 02:16:26 PM PDT 24
Finished Jun 09 02:19:34 PM PDT 24
Peak memory 200324 kb
Host smart-63141ad5-61b3-46f9-87e5-0d1b81a69bed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969070819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.2969070819
Directory /workspace/25.uart_fifo_full/latest

Test location /workspace/coverage/default/25.uart_fifo_overflow.2483610062
Short name T949
Test name
Test status
Simulation time 98495089267 ps
CPU time 153.01 seconds
Started Jun 09 02:16:30 PM PDT 24
Finished Jun 09 02:19:03 PM PDT 24
Peak memory 200332 kb
Host smart-17243c4b-d0b6-4a88-9f4e-09a97891c58b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483610062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.2483610062
Directory /workspace/25.uart_fifo_overflow/latest

Test location /workspace/coverage/default/25.uart_fifo_reset.1068130663
Short name T212
Test name
Test status
Simulation time 92477973698 ps
CPU time 30.7 seconds
Started Jun 09 02:16:27 PM PDT 24
Finished Jun 09 02:16:58 PM PDT 24
Peak memory 200252 kb
Host smart-84872304-4ce7-4690-81c4-b92a4a9a70bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068130663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.1068130663
Directory /workspace/25.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_intr.308830332
Short name T687
Test name
Test status
Simulation time 19192108167 ps
CPU time 11.21 seconds
Started Jun 09 02:16:26 PM PDT 24
Finished Jun 09 02:16:38 PM PDT 24
Peak memory 199648 kb
Host smart-3fb31dcf-a72c-4e89-a596-5c663f11474a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308830332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.308830332
Directory /workspace/25.uart_intr/latest

Test location /workspace/coverage/default/25.uart_long_xfer_wo_dly.1717488815
Short name T1050
Test name
Test status
Simulation time 117505760118 ps
CPU time 286.62 seconds
Started Jun 09 02:16:31 PM PDT 24
Finished Jun 09 02:21:18 PM PDT 24
Peak memory 200384 kb
Host smart-16c51f24-9a75-4da1-84ed-bdab51859297
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1717488815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.1717488815
Directory /workspace/25.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/25.uart_loopback.1225429971
Short name T373
Test name
Test status
Simulation time 7449331313 ps
CPU time 8.4 seconds
Started Jun 09 02:16:33 PM PDT 24
Finished Jun 09 02:16:41 PM PDT 24
Peak memory 200368 kb
Host smart-7af1f255-b072-49b5-ad1a-9c019d78e6ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225429971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_loopback.1225429971
Directory /workspace/25.uart_loopback/latest

Test location /workspace/coverage/default/25.uart_perf.2904054106
Short name T654
Test name
Test status
Simulation time 4859224055 ps
CPU time 104.54 seconds
Started Jun 09 02:16:32 PM PDT 24
Finished Jun 09 02:18:17 PM PDT 24
Peak memory 200384 kb
Host smart-fc573ac9-6ecf-4cdb-b60d-ca266afd00b6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2904054106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.2904054106
Directory /workspace/25.uart_perf/latest

Test location /workspace/coverage/default/25.uart_rx_oversample.2738385348
Short name T397
Test name
Test status
Simulation time 5684147711 ps
CPU time 12.63 seconds
Started Jun 09 02:16:27 PM PDT 24
Finished Jun 09 02:16:40 PM PDT 24
Peak memory 198592 kb
Host smart-139854e1-c4ba-438e-be5b-e4af7e1d05bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2738385348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.2738385348
Directory /workspace/25.uart_rx_oversample/latest

Test location /workspace/coverage/default/25.uart_rx_parity_err.2466530501
Short name T1040
Test name
Test status
Simulation time 8994430986 ps
CPU time 4.96 seconds
Started Jun 09 02:16:31 PM PDT 24
Finished Jun 09 02:16:36 PM PDT 24
Peak memory 199552 kb
Host smart-a0b2dd85-3281-45a2-878d-9b41a62d629c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466530501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.2466530501
Directory /workspace/25.uart_rx_parity_err/latest

Test location /workspace/coverage/default/25.uart_rx_start_bit_filter.3615356007
Short name T734
Test name
Test status
Simulation time 36136981454 ps
CPU time 5.74 seconds
Started Jun 09 02:16:31 PM PDT 24
Finished Jun 09 02:16:37 PM PDT 24
Peak memory 197184 kb
Host smart-b136c30c-f4b0-43de-bc4a-9d9786872dc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615356007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.3615356007
Directory /workspace/25.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/25.uart_smoke.1619538447
Short name T682
Test name
Test status
Simulation time 5362028960 ps
CPU time 22.1 seconds
Started Jun 09 02:16:28 PM PDT 24
Finished Jun 09 02:16:50 PM PDT 24
Peak memory 200364 kb
Host smart-af32fb8d-ac4d-4e6a-88b2-cfd5b52e192c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619538447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_smoke.1619538447
Directory /workspace/25.uart_smoke/latest

Test location /workspace/coverage/default/25.uart_stress_all.2264673944
Short name T854
Test name
Test status
Simulation time 64475395979 ps
CPU time 112.43 seconds
Started Jun 09 02:16:33 PM PDT 24
Finished Jun 09 02:18:26 PM PDT 24
Peak memory 200372 kb
Host smart-2335b998-e122-464e-81fe-ccf349f484d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264673944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.2264673944
Directory /workspace/25.uart_stress_all/latest

Test location /workspace/coverage/default/25.uart_tx_ovrd.2734213176
Short name T943
Test name
Test status
Simulation time 1976857337 ps
CPU time 2.65 seconds
Started Jun 09 02:16:33 PM PDT 24
Finished Jun 09 02:16:36 PM PDT 24
Peak memory 199056 kb
Host smart-708c62fd-0615-44dd-9cbe-7cb3d905b196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734213176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.2734213176
Directory /workspace/25.uart_tx_ovrd/latest

Test location /workspace/coverage/default/25.uart_tx_rx.1311515394
Short name T457
Test name
Test status
Simulation time 102970458029 ps
CPU time 79.32 seconds
Started Jun 09 02:16:28 PM PDT 24
Finished Jun 09 02:17:48 PM PDT 24
Peak memory 200364 kb
Host smart-54568707-629e-4dae-90e6-62caec367bf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311515394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.1311515394
Directory /workspace/25.uart_tx_rx/latest

Test location /workspace/coverage/default/250.uart_fifo_reset.3571693294
Short name T898
Test name
Test status
Simulation time 229112105569 ps
CPU time 195.49 seconds
Started Jun 09 02:21:03 PM PDT 24
Finished Jun 09 02:24:19 PM PDT 24
Peak memory 200396 kb
Host smart-99c171b9-e84c-4051-b587-af4e9bf35867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571693294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.3571693294
Directory /workspace/250.uart_fifo_reset/latest

Test location /workspace/coverage/default/251.uart_fifo_reset.3935308335
Short name T266
Test name
Test status
Simulation time 50523629798 ps
CPU time 43.7 seconds
Started Jun 09 02:21:03 PM PDT 24
Finished Jun 09 02:21:47 PM PDT 24
Peak memory 200308 kb
Host smart-f9e12179-f517-455b-9cb2-c93894651bcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935308335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.3935308335
Directory /workspace/251.uart_fifo_reset/latest

Test location /workspace/coverage/default/252.uart_fifo_reset.2200504787
Short name T1066
Test name
Test status
Simulation time 120571284470 ps
CPU time 122.51 seconds
Started Jun 09 02:21:06 PM PDT 24
Finished Jun 09 02:23:09 PM PDT 24
Peak memory 200308 kb
Host smart-1ec094ab-0eef-45c8-983e-90278b158a96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200504787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.2200504787
Directory /workspace/252.uart_fifo_reset/latest

Test location /workspace/coverage/default/253.uart_fifo_reset.2512891095
Short name T134
Test name
Test status
Simulation time 88765194891 ps
CPU time 51.51 seconds
Started Jun 09 02:21:06 PM PDT 24
Finished Jun 09 02:21:58 PM PDT 24
Peak memory 200312 kb
Host smart-b50514b8-3f82-425b-8470-49888daf9dca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512891095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.2512891095
Directory /workspace/253.uart_fifo_reset/latest

Test location /workspace/coverage/default/254.uart_fifo_reset.3880351261
Short name T135
Test name
Test status
Simulation time 26918927356 ps
CPU time 42.15 seconds
Started Jun 09 02:21:06 PM PDT 24
Finished Jun 09 02:21:48 PM PDT 24
Peak memory 200364 kb
Host smart-32668a74-7d49-4264-8e15-f85ed9e00019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880351261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.3880351261
Directory /workspace/254.uart_fifo_reset/latest

Test location /workspace/coverage/default/255.uart_fifo_reset.1578372898
Short name T211
Test name
Test status
Simulation time 127830862338 ps
CPU time 15.1 seconds
Started Jun 09 02:21:05 PM PDT 24
Finished Jun 09 02:21:20 PM PDT 24
Peak memory 200308 kb
Host smart-4fa64c19-ae62-4881-a734-6885bd24b736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578372898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.1578372898
Directory /workspace/255.uart_fifo_reset/latest

Test location /workspace/coverage/default/256.uart_fifo_reset.2898122127
Short name T245
Test name
Test status
Simulation time 69476238974 ps
CPU time 32.28 seconds
Started Jun 09 02:21:05 PM PDT 24
Finished Jun 09 02:21:37 PM PDT 24
Peak memory 200368 kb
Host smart-a52ae9af-2327-4b75-85d2-65d87310c787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898122127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.2898122127
Directory /workspace/256.uart_fifo_reset/latest

Test location /workspace/coverage/default/257.uart_fifo_reset.1524703174
Short name T246
Test name
Test status
Simulation time 35527862430 ps
CPU time 18.79 seconds
Started Jun 09 02:21:08 PM PDT 24
Finished Jun 09 02:21:27 PM PDT 24
Peak memory 200560 kb
Host smart-84b3d04c-1b2d-45e0-b271-0cd0090541f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524703174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.1524703174
Directory /workspace/257.uart_fifo_reset/latest

Test location /workspace/coverage/default/258.uart_fifo_reset.113065810
Short name T951
Test name
Test status
Simulation time 13681224472 ps
CPU time 14.61 seconds
Started Jun 09 02:21:11 PM PDT 24
Finished Jun 09 02:21:26 PM PDT 24
Peak memory 200348 kb
Host smart-25ccd29c-41be-4ac4-b5b3-597462258d9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113065810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.113065810
Directory /workspace/258.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_alert_test.1076153958
Short name T715
Test name
Test status
Simulation time 50076997 ps
CPU time 0.57 seconds
Started Jun 09 02:16:37 PM PDT 24
Finished Jun 09 02:16:38 PM PDT 24
Peak memory 195972 kb
Host smart-b8e0ddc2-a086-4365-ad92-2c19a09935d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076153958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.1076153958
Directory /workspace/26.uart_alert_test/latest

Test location /workspace/coverage/default/26.uart_fifo_full.2568338760
Short name T1075
Test name
Test status
Simulation time 70893389258 ps
CPU time 115.55 seconds
Started Jun 09 02:16:35 PM PDT 24
Finished Jun 09 02:18:31 PM PDT 24
Peak memory 200400 kb
Host smart-5005e34c-1c2e-49d8-a81d-90006a32bdc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568338760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.2568338760
Directory /workspace/26.uart_fifo_full/latest

Test location /workspace/coverage/default/26.uart_fifo_overflow.1032897001
Short name T747
Test name
Test status
Simulation time 53201663696 ps
CPU time 21.38 seconds
Started Jun 09 02:16:34 PM PDT 24
Finished Jun 09 02:16:56 PM PDT 24
Peak memory 200356 kb
Host smart-865c587d-5e4b-4696-bbed-4fe6d0bf65fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032897001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.1032897001
Directory /workspace/26.uart_fifo_overflow/latest

Test location /workspace/coverage/default/26.uart_fifo_reset.3848997393
Short name T185
Test name
Test status
Simulation time 181937336552 ps
CPU time 67.51 seconds
Started Jun 09 02:16:32 PM PDT 24
Finished Jun 09 02:17:39 PM PDT 24
Peak memory 200544 kb
Host smart-52ad32b3-7246-429f-968d-60e623b34dcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848997393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.3848997393
Directory /workspace/26.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_intr.4034358294
Short name T455
Test name
Test status
Simulation time 42341161649 ps
CPU time 71.19 seconds
Started Jun 09 02:16:33 PM PDT 24
Finished Jun 09 02:17:44 PM PDT 24
Peak memory 200312 kb
Host smart-ce4e5a4e-1365-4817-b2dc-f7aa70583f63
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034358294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.4034358294
Directory /workspace/26.uart_intr/latest

Test location /workspace/coverage/default/26.uart_long_xfer_wo_dly.3095290115
Short name T1049
Test name
Test status
Simulation time 182953178616 ps
CPU time 246.59 seconds
Started Jun 09 02:16:37 PM PDT 24
Finished Jun 09 02:20:43 PM PDT 24
Peak memory 200316 kb
Host smart-db1e933f-1cbf-4932-bcf7-094c6829914d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3095290115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.3095290115
Directory /workspace/26.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/26.uart_loopback.4017241438
Short name T988
Test name
Test status
Simulation time 9372338433 ps
CPU time 2.12 seconds
Started Jun 09 02:16:38 PM PDT 24
Finished Jun 09 02:16:40 PM PDT 24
Peak memory 198904 kb
Host smart-5e1c6d63-b493-4c05-a332-351fbc14edd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017241438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_loopback.4017241438
Directory /workspace/26.uart_loopback/latest

Test location /workspace/coverage/default/26.uart_perf.759250338
Short name T853
Test name
Test status
Simulation time 7044702860 ps
CPU time 397.42 seconds
Started Jun 09 02:16:37 PM PDT 24
Finished Jun 09 02:23:15 PM PDT 24
Peak memory 200348 kb
Host smart-fd6580c9-1032-4cd5-98ad-7804c43569ed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=759250338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.759250338
Directory /workspace/26.uart_perf/latest

Test location /workspace/coverage/default/26.uart_rx_oversample.955235857
Short name T700
Test name
Test status
Simulation time 2225059941 ps
CPU time 12.46 seconds
Started Jun 09 02:16:35 PM PDT 24
Finished Jun 09 02:16:48 PM PDT 24
Peak memory 198248 kb
Host smart-e413cf2f-571e-4112-85f5-1dd6eac05e6b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=955235857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.955235857
Directory /workspace/26.uart_rx_oversample/latest

Test location /workspace/coverage/default/26.uart_rx_parity_err.2911367208
Short name T1005
Test name
Test status
Simulation time 86617861591 ps
CPU time 296.44 seconds
Started Jun 09 02:16:37 PM PDT 24
Finished Jun 09 02:21:34 PM PDT 24
Peak memory 200348 kb
Host smart-6e4565c2-0f44-4b8e-8d2e-10422eafa39d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911367208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.2911367208
Directory /workspace/26.uart_rx_parity_err/latest

Test location /workspace/coverage/default/26.uart_rx_start_bit_filter.704160033
Short name T309
Test name
Test status
Simulation time 30299538792 ps
CPU time 25.7 seconds
Started Jun 09 02:16:38 PM PDT 24
Finished Jun 09 02:17:04 PM PDT 24
Peak memory 196152 kb
Host smart-140c85cb-81c7-4c34-a658-bf401de0ccd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704160033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.704160033
Directory /workspace/26.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/26.uart_smoke.1077872732
Short name T946
Test name
Test status
Simulation time 537203833 ps
CPU time 1.47 seconds
Started Jun 09 02:16:33 PM PDT 24
Finished Jun 09 02:16:34 PM PDT 24
Peak memory 198896 kb
Host smart-cab4c2ff-a6be-4757-a418-cd6329807c2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077872732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_smoke.1077872732
Directory /workspace/26.uart_smoke/latest

Test location /workspace/coverage/default/26.uart_tx_ovrd.2748051329
Short name T370
Test name
Test status
Simulation time 7750993112 ps
CPU time 16.64 seconds
Started Jun 09 02:16:38 PM PDT 24
Finished Jun 09 02:16:55 PM PDT 24
Peak memory 199932 kb
Host smart-32f403b1-9d22-4581-8b57-c077c907c342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748051329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.2748051329
Directory /workspace/26.uart_tx_ovrd/latest

Test location /workspace/coverage/default/26.uart_tx_rx.360798936
Short name T810
Test name
Test status
Simulation time 33425358939 ps
CPU time 75.02 seconds
Started Jun 09 02:16:32 PM PDT 24
Finished Jun 09 02:17:48 PM PDT 24
Peak memory 200368 kb
Host smart-b966d13b-169b-415c-8821-2377bb447ee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360798936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.360798936
Directory /workspace/26.uart_tx_rx/latest

Test location /workspace/coverage/default/260.uart_fifo_reset.1947136852
Short name T238
Test name
Test status
Simulation time 28143633296 ps
CPU time 115.21 seconds
Started Jun 09 02:21:16 PM PDT 24
Finished Jun 09 02:23:11 PM PDT 24
Peak memory 200388 kb
Host smart-067f2db1-984e-4743-b409-fbacac025558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947136852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.1947136852
Directory /workspace/260.uart_fifo_reset/latest

Test location /workspace/coverage/default/261.uart_fifo_reset.520642611
Short name T248
Test name
Test status
Simulation time 122357006723 ps
CPU time 40.04 seconds
Started Jun 09 02:21:15 PM PDT 24
Finished Jun 09 02:21:55 PM PDT 24
Peak memory 200364 kb
Host smart-85f6e536-22ad-4be6-b440-d6672390688f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520642611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.520642611
Directory /workspace/261.uart_fifo_reset/latest

Test location /workspace/coverage/default/262.uart_fifo_reset.4252327776
Short name T924
Test name
Test status
Simulation time 8573726641 ps
CPU time 16.19 seconds
Started Jun 09 02:21:14 PM PDT 24
Finished Jun 09 02:21:31 PM PDT 24
Peak memory 200312 kb
Host smart-8fbb6ab1-04c9-4a1a-af1f-f4f24edc0722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252327776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.4252327776
Directory /workspace/262.uart_fifo_reset/latest

Test location /workspace/coverage/default/263.uart_fifo_reset.1419190844
Short name T1062
Test name
Test status
Simulation time 24073697881 ps
CPU time 49.22 seconds
Started Jun 09 02:21:15 PM PDT 24
Finished Jun 09 02:22:04 PM PDT 24
Peak memory 200304 kb
Host smart-46c82bf4-ce24-4ccc-baa7-459ee8ed1e1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419190844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.1419190844
Directory /workspace/263.uart_fifo_reset/latest

Test location /workspace/coverage/default/264.uart_fifo_reset.1063623976
Short name T366
Test name
Test status
Simulation time 15109316480 ps
CPU time 20.58 seconds
Started Jun 09 02:21:14 PM PDT 24
Finished Jun 09 02:21:35 PM PDT 24
Peak memory 199856 kb
Host smart-b9de54ef-2e53-4a11-8ffb-4e5ae2ddb759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063623976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.1063623976
Directory /workspace/264.uart_fifo_reset/latest

Test location /workspace/coverage/default/265.uart_fifo_reset.3196465235
Short name T195
Test name
Test status
Simulation time 126753337915 ps
CPU time 53.1 seconds
Started Jun 09 02:21:17 PM PDT 24
Finished Jun 09 02:22:10 PM PDT 24
Peak memory 200396 kb
Host smart-5c72745a-14e3-4742-a421-d5ed649d5c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196465235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.3196465235
Directory /workspace/265.uart_fifo_reset/latest

Test location /workspace/coverage/default/266.uart_fifo_reset.3835949932
Short name T183
Test name
Test status
Simulation time 123104599009 ps
CPU time 173.31 seconds
Started Jun 09 02:21:16 PM PDT 24
Finished Jun 09 02:24:09 PM PDT 24
Peak memory 200296 kb
Host smart-8190315b-3c42-47de-be84-f855bcb39608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835949932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.3835949932
Directory /workspace/266.uart_fifo_reset/latest

Test location /workspace/coverage/default/267.uart_fifo_reset.2504302988
Short name T914
Test name
Test status
Simulation time 15859939738 ps
CPU time 6.99 seconds
Started Jun 09 02:21:18 PM PDT 24
Finished Jun 09 02:21:25 PM PDT 24
Peak memory 200304 kb
Host smart-daa907ac-ebd0-400f-88ed-d8980311d12b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504302988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.2504302988
Directory /workspace/267.uart_fifo_reset/latest

Test location /workspace/coverage/default/268.uart_fifo_reset.516363506
Short name T186
Test name
Test status
Simulation time 209303275295 ps
CPU time 79.12 seconds
Started Jun 09 02:21:14 PM PDT 24
Finished Jun 09 02:22:33 PM PDT 24
Peak memory 200424 kb
Host smart-14cf25b0-671d-403a-9ba4-104f788a89a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516363506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.516363506
Directory /workspace/268.uart_fifo_reset/latest

Test location /workspace/coverage/default/269.uart_fifo_reset.3789552108
Short name T250
Test name
Test status
Simulation time 7961765377 ps
CPU time 14.32 seconds
Started Jun 09 02:21:16 PM PDT 24
Finished Jun 09 02:21:30 PM PDT 24
Peak memory 200252 kb
Host smart-a6ab9c47-5df2-448b-b595-34be6436934a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789552108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.3789552108
Directory /workspace/269.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_alert_test.654757834
Short name T789
Test name
Test status
Simulation time 26941769 ps
CPU time 0.56 seconds
Started Jun 09 02:16:43 PM PDT 24
Finished Jun 09 02:16:44 PM PDT 24
Peak memory 195788 kb
Host smart-31c2275d-1b92-49c4-8c2a-b479f21bc037
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654757834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.654757834
Directory /workspace/27.uart_alert_test/latest

Test location /workspace/coverage/default/27.uart_fifo_full.2934766304
Short name T147
Test name
Test status
Simulation time 51887456076 ps
CPU time 54.05 seconds
Started Jun 09 02:16:36 PM PDT 24
Finished Jun 09 02:17:30 PM PDT 24
Peak memory 200576 kb
Host smart-a093e45f-fa5d-48f3-b9cc-2d2b9f95d2db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934766304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.2934766304
Directory /workspace/27.uart_fifo_full/latest

Test location /workspace/coverage/default/27.uart_fifo_overflow.4244570434
Short name T744
Test name
Test status
Simulation time 35139962850 ps
CPU time 17.62 seconds
Started Jun 09 02:16:38 PM PDT 24
Finished Jun 09 02:16:56 PM PDT 24
Peak memory 200304 kb
Host smart-3bbba167-4706-412c-955e-ea5c28e9f81f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244570434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.4244570434
Directory /workspace/27.uart_fifo_overflow/latest

Test location /workspace/coverage/default/27.uart_fifo_reset.39534306
Short name T200
Test name
Test status
Simulation time 138696390247 ps
CPU time 221.86 seconds
Started Jun 09 02:16:38 PM PDT 24
Finished Jun 09 02:20:20 PM PDT 24
Peak memory 200404 kb
Host smart-b9a23950-46e6-48b6-8ab8-e7102b89905b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39534306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.39534306
Directory /workspace/27.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_intr.660754653
Short name T323
Test name
Test status
Simulation time 151356091215 ps
CPU time 95.1 seconds
Started Jun 09 02:16:44 PM PDT 24
Finished Jun 09 02:18:19 PM PDT 24
Peak memory 200400 kb
Host smart-2522b8cb-8ed6-4ea9-ade1-dc3acb4fc7f4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660754653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.660754653
Directory /workspace/27.uart_intr/latest

Test location /workspace/coverage/default/27.uart_long_xfer_wo_dly.2693443530
Short name T434
Test name
Test status
Simulation time 123158801042 ps
CPU time 1056.82 seconds
Started Jun 09 02:16:43 PM PDT 24
Finished Jun 09 02:34:20 PM PDT 24
Peak memory 200384 kb
Host smart-0950efd1-6078-46c2-a69f-7da8b19e5d53
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2693443530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.2693443530
Directory /workspace/27.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/27.uart_loopback.405856847
Short name T1056
Test name
Test status
Simulation time 6665702731 ps
CPU time 2.42 seconds
Started Jun 09 02:16:41 PM PDT 24
Finished Jun 09 02:16:44 PM PDT 24
Peak memory 197264 kb
Host smart-f6694989-d80d-4b50-bc06-d92aff139911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405856847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_loopback.405856847
Directory /workspace/27.uart_loopback/latest

Test location /workspace/coverage/default/27.uart_perf.3096150016
Short name T883
Test name
Test status
Simulation time 13806346942 ps
CPU time 417.05 seconds
Started Jun 09 02:16:42 PM PDT 24
Finished Jun 09 02:23:39 PM PDT 24
Peak memory 200384 kb
Host smart-6e68c027-1e3c-4b84-8531-3da7a04f52a4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3096150016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.3096150016
Directory /workspace/27.uart_perf/latest

Test location /workspace/coverage/default/27.uart_rx_oversample.3001074165
Short name T685
Test name
Test status
Simulation time 2972169395 ps
CPU time 5.88 seconds
Started Jun 09 02:16:43 PM PDT 24
Finished Jun 09 02:16:49 PM PDT 24
Peak memory 200296 kb
Host smart-9f6fbe04-9e23-41d5-b00b-2a039954ff6d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3001074165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.3001074165
Directory /workspace/27.uart_rx_oversample/latest

Test location /workspace/coverage/default/27.uart_rx_parity_err.782641238
Short name T935
Test name
Test status
Simulation time 107947906105 ps
CPU time 189.75 seconds
Started Jun 09 02:16:44 PM PDT 24
Finished Jun 09 02:19:54 PM PDT 24
Peak memory 200320 kb
Host smart-d6e858ae-5937-42de-b6d7-d5453ec6a6c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782641238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.782641238
Directory /workspace/27.uart_rx_parity_err/latest

Test location /workspace/coverage/default/27.uart_rx_start_bit_filter.417360329
Short name T24
Test name
Test status
Simulation time 4984514625 ps
CPU time 2.51 seconds
Started Jun 09 02:16:40 PM PDT 24
Finished Jun 09 02:16:43 PM PDT 24
Peak memory 196688 kb
Host smart-efd3482c-ac5f-482c-9dec-fbe29e3c7e99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417360329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.417360329
Directory /workspace/27.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/27.uart_smoke.4267157407
Short name T523
Test name
Test status
Simulation time 5681146793 ps
CPU time 8.38 seconds
Started Jun 09 02:16:38 PM PDT 24
Finished Jun 09 02:16:47 PM PDT 24
Peak memory 200040 kb
Host smart-0995a9a7-41df-4324-9891-0e670494fbec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267157407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_smoke.4267157407
Directory /workspace/27.uart_smoke/latest

Test location /workspace/coverage/default/27.uart_tx_ovrd.3124033667
Short name T1077
Test name
Test status
Simulation time 6639220537 ps
CPU time 20.32 seconds
Started Jun 09 02:16:43 PM PDT 24
Finished Jun 09 02:17:04 PM PDT 24
Peak memory 200428 kb
Host smart-1cfd0e26-e326-4185-9409-07f9bddeb911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124033667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.3124033667
Directory /workspace/27.uart_tx_ovrd/latest

Test location /workspace/coverage/default/27.uart_tx_rx.417573033
Short name T272
Test name
Test status
Simulation time 43335143335 ps
CPU time 53.89 seconds
Started Jun 09 02:16:36 PM PDT 24
Finished Jun 09 02:17:30 PM PDT 24
Peak memory 200356 kb
Host smart-94eec1cb-fe8b-442b-b9d9-54b69e219fd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417573033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.417573033
Directory /workspace/27.uart_tx_rx/latest

Test location /workspace/coverage/default/270.uart_fifo_reset.846654864
Short name T829
Test name
Test status
Simulation time 50098087930 ps
CPU time 17.02 seconds
Started Jun 09 02:21:14 PM PDT 24
Finished Jun 09 02:21:31 PM PDT 24
Peak memory 200432 kb
Host smart-a83cb9a8-f70c-4c3c-94d8-7b48dd38442c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846654864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.846654864
Directory /workspace/270.uart_fifo_reset/latest

Test location /workspace/coverage/default/271.uart_fifo_reset.944641590
Short name T582
Test name
Test status
Simulation time 81906623292 ps
CPU time 34.33 seconds
Started Jun 09 02:21:15 PM PDT 24
Finished Jun 09 02:21:50 PM PDT 24
Peak memory 200420 kb
Host smart-487a757e-41d2-4a89-b6e4-eee05160aabf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944641590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.944641590
Directory /workspace/271.uart_fifo_reset/latest

Test location /workspace/coverage/default/272.uart_fifo_reset.3954231182
Short name T632
Test name
Test status
Simulation time 285200368580 ps
CPU time 57.36 seconds
Started Jun 09 02:21:15 PM PDT 24
Finished Jun 09 02:22:12 PM PDT 24
Peak memory 200324 kb
Host smart-f9ee3ab6-226b-4054-8195-76c06859259c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954231182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.3954231182
Directory /workspace/272.uart_fifo_reset/latest

Test location /workspace/coverage/default/273.uart_fifo_reset.1719026406
Short name T290
Test name
Test status
Simulation time 192648720991 ps
CPU time 180.8 seconds
Started Jun 09 02:21:18 PM PDT 24
Finished Jun 09 02:24:19 PM PDT 24
Peak memory 200312 kb
Host smart-d7c135a7-3472-4421-9e8d-e0d9c5c5d397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719026406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.1719026406
Directory /workspace/273.uart_fifo_reset/latest

Test location /workspace/coverage/default/274.uart_fifo_reset.3825062539
Short name T738
Test name
Test status
Simulation time 247560423086 ps
CPU time 87.93 seconds
Started Jun 09 02:21:19 PM PDT 24
Finished Jun 09 02:22:47 PM PDT 24
Peak memory 200300 kb
Host smart-3a0b6795-bcc7-45de-84f2-db17364305f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825062539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.3825062539
Directory /workspace/274.uart_fifo_reset/latest

Test location /workspace/coverage/default/275.uart_fifo_reset.721385255
Short name T168
Test name
Test status
Simulation time 70624195870 ps
CPU time 22.6 seconds
Started Jun 09 02:21:19 PM PDT 24
Finished Jun 09 02:21:42 PM PDT 24
Peak memory 200336 kb
Host smart-9f8ddd14-8150-4801-b498-8c2bbad4e475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721385255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.721385255
Directory /workspace/275.uart_fifo_reset/latest

Test location /workspace/coverage/default/276.uart_fifo_reset.1228134192
Short name T12
Test name
Test status
Simulation time 34859670983 ps
CPU time 16.61 seconds
Started Jun 09 02:21:20 PM PDT 24
Finished Jun 09 02:21:37 PM PDT 24
Peak memory 200088 kb
Host smart-627a498a-a041-4672-92f3-67796058167b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228134192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.1228134192
Directory /workspace/276.uart_fifo_reset/latest

Test location /workspace/coverage/default/277.uart_fifo_reset.42950627
Short name T985
Test name
Test status
Simulation time 31370003043 ps
CPU time 31.06 seconds
Started Jun 09 02:21:19 PM PDT 24
Finished Jun 09 02:21:51 PM PDT 24
Peak memory 200364 kb
Host smart-4eaaa347-4ff0-4d6e-8864-9ac1b8bec147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42950627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.42950627
Directory /workspace/277.uart_fifo_reset/latest

Test location /workspace/coverage/default/278.uart_fifo_reset.2525068536
Short name T698
Test name
Test status
Simulation time 17929920737 ps
CPU time 22.78 seconds
Started Jun 09 02:21:22 PM PDT 24
Finished Jun 09 02:21:45 PM PDT 24
Peak memory 200312 kb
Host smart-1be00d79-9434-4e49-8c6e-630c8817ee4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525068536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.2525068536
Directory /workspace/278.uart_fifo_reset/latest

Test location /workspace/coverage/default/279.uart_fifo_reset.3026829520
Short name T476
Test name
Test status
Simulation time 12015877721 ps
CPU time 20.26 seconds
Started Jun 09 02:21:19 PM PDT 24
Finished Jun 09 02:21:39 PM PDT 24
Peak memory 200320 kb
Host smart-c27668e8-50a4-423f-9f82-a259146816bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026829520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.3026829520
Directory /workspace/279.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_alert_test.3994733584
Short name T964
Test name
Test status
Simulation time 18562238 ps
CPU time 0.58 seconds
Started Jun 09 02:16:53 PM PDT 24
Finished Jun 09 02:16:54 PM PDT 24
Peak memory 195952 kb
Host smart-21cbbefc-3a8f-4716-ae91-d3798aa4ecc2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994733584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.3994733584
Directory /workspace/28.uart_alert_test/latest

Test location /workspace/coverage/default/28.uart_fifo_full.2410204248
Short name T107
Test name
Test status
Simulation time 51204198257 ps
CPU time 37.31 seconds
Started Jun 09 02:16:47 PM PDT 24
Finished Jun 09 02:17:24 PM PDT 24
Peak memory 200396 kb
Host smart-ee95e4b5-d879-4344-baa4-3e143639914c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410204248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.2410204248
Directory /workspace/28.uart_fifo_full/latest

Test location /workspace/coverage/default/28.uart_fifo_overflow.533786509
Short name T551
Test name
Test status
Simulation time 57577924019 ps
CPU time 29.28 seconds
Started Jun 09 02:16:46 PM PDT 24
Finished Jun 09 02:17:15 PM PDT 24
Peak memory 200636 kb
Host smart-366a400c-8f29-482d-aec7-9a79710efe64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533786509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.533786509
Directory /workspace/28.uart_fifo_overflow/latest

Test location /workspace/coverage/default/28.uart_fifo_reset.2174971071
Short name T595
Test name
Test status
Simulation time 44142227403 ps
CPU time 31.89 seconds
Started Jun 09 02:16:47 PM PDT 24
Finished Jun 09 02:17:19 PM PDT 24
Peak memory 200296 kb
Host smart-2031b149-aec7-426c-9527-751acc83d6fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174971071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.2174971071
Directory /workspace/28.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_intr.1153876160
Short name T711
Test name
Test status
Simulation time 67152067457 ps
CPU time 116.52 seconds
Started Jun 09 02:16:47 PM PDT 24
Finished Jun 09 02:18:43 PM PDT 24
Peak memory 200416 kb
Host smart-d78eee2a-b600-425a-b706-758779832677
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153876160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.1153876160
Directory /workspace/28.uart_intr/latest

Test location /workspace/coverage/default/28.uart_loopback.1756616000
Short name T805
Test name
Test status
Simulation time 8716620785 ps
CPU time 12.31 seconds
Started Jun 09 02:16:46 PM PDT 24
Finished Jun 09 02:16:59 PM PDT 24
Peak memory 199352 kb
Host smart-07e30b85-1902-4de7-a839-5688a4791c21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756616000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_loopback.1756616000
Directory /workspace/28.uart_loopback/latest

Test location /workspace/coverage/default/28.uart_perf.3371699731
Short name T784
Test name
Test status
Simulation time 7750023419 ps
CPU time 417.83 seconds
Started Jun 09 02:16:48 PM PDT 24
Finished Jun 09 02:23:46 PM PDT 24
Peak memory 200392 kb
Host smart-4bb78d6a-2617-467f-b648-04c5d9e161ac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3371699731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.3371699731
Directory /workspace/28.uart_perf/latest

Test location /workspace/coverage/default/28.uart_rx_oversample.3572635322
Short name T550
Test name
Test status
Simulation time 4214763001 ps
CPU time 8.74 seconds
Started Jun 09 02:16:47 PM PDT 24
Finished Jun 09 02:16:56 PM PDT 24
Peak memory 198520 kb
Host smart-c1767b1e-b498-43a9-8f5b-c225ea252409
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3572635322 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.3572635322
Directory /workspace/28.uart_rx_oversample/latest

Test location /workspace/coverage/default/28.uart_rx_parity_err.2946722984
Short name T751
Test name
Test status
Simulation time 27762060830 ps
CPU time 35.88 seconds
Started Jun 09 02:16:52 PM PDT 24
Finished Jun 09 02:17:28 PM PDT 24
Peak memory 200300 kb
Host smart-aae593f4-e04a-4da2-b4aa-f19e684e372d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946722984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.2946722984
Directory /workspace/28.uart_rx_parity_err/latest

Test location /workspace/coverage/default/28.uart_rx_start_bit_filter.3423925746
Short name T604
Test name
Test status
Simulation time 42903093842 ps
CPU time 16.17 seconds
Started Jun 09 02:16:48 PM PDT 24
Finished Jun 09 02:17:04 PM PDT 24
Peak memory 196660 kb
Host smart-8b5a7bf6-007e-4a3a-b3ec-94367f03c7af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423925746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.3423925746
Directory /workspace/28.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/28.uart_smoke.3187104129
Short name T69
Test name
Test status
Simulation time 701585493 ps
CPU time 1.52 seconds
Started Jun 09 02:16:41 PM PDT 24
Finished Jun 09 02:16:43 PM PDT 24
Peak memory 199996 kb
Host smart-8265aa6a-849b-475c-be58-ba3a2ab0f888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187104129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_smoke.3187104129
Directory /workspace/28.uart_smoke/latest

Test location /workspace/coverage/default/28.uart_stress_all.2001116327
Short name T1002
Test name
Test status
Simulation time 254081786592 ps
CPU time 109.31 seconds
Started Jun 09 02:16:52 PM PDT 24
Finished Jun 09 02:18:42 PM PDT 24
Peak memory 200408 kb
Host smart-01372b66-7855-4e6f-94e0-bb98fa6efd61
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001116327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.2001116327
Directory /workspace/28.uart_stress_all/latest

Test location /workspace/coverage/default/28.uart_tx_ovrd.2350304033
Short name T1012
Test name
Test status
Simulation time 6629375029 ps
CPU time 25.69 seconds
Started Jun 09 02:16:48 PM PDT 24
Finished Jun 09 02:17:13 PM PDT 24
Peak memory 200244 kb
Host smart-53ba5b22-68b2-4444-b2bb-eee895df7e1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350304033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.2350304033
Directory /workspace/28.uart_tx_ovrd/latest

Test location /workspace/coverage/default/28.uart_tx_rx.2255828983
Short name T824
Test name
Test status
Simulation time 222638661440 ps
CPU time 79.02 seconds
Started Jun 09 02:16:43 PM PDT 24
Finished Jun 09 02:18:02 PM PDT 24
Peak memory 200400 kb
Host smart-a0cba1c1-1f40-402c-b47c-a0fc029e8333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255828983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.2255828983
Directory /workspace/28.uart_tx_rx/latest

Test location /workspace/coverage/default/280.uart_fifo_reset.2783012949
Short name T928
Test name
Test status
Simulation time 158183964401 ps
CPU time 30.72 seconds
Started Jun 09 02:21:20 PM PDT 24
Finished Jun 09 02:21:51 PM PDT 24
Peak memory 200368 kb
Host smart-0acae382-0621-4260-a528-281afce997f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783012949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.2783012949
Directory /workspace/280.uart_fifo_reset/latest

Test location /workspace/coverage/default/281.uart_fifo_reset.165718629
Short name T145
Test name
Test status
Simulation time 46233950990 ps
CPU time 78.67 seconds
Started Jun 09 02:21:19 PM PDT 24
Finished Jun 09 02:22:37 PM PDT 24
Peak memory 200360 kb
Host smart-30c8e49e-c3b2-48bd-901d-96e0509f6621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165718629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.165718629
Directory /workspace/281.uart_fifo_reset/latest

Test location /workspace/coverage/default/282.uart_fifo_reset.940101443
Short name T930
Test name
Test status
Simulation time 48493473693 ps
CPU time 8.12 seconds
Started Jun 09 02:21:20 PM PDT 24
Finished Jun 09 02:21:29 PM PDT 24
Peak memory 200392 kb
Host smart-f7a06bca-ff6f-49a7-b518-0f26c6220de4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940101443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.940101443
Directory /workspace/282.uart_fifo_reset/latest

Test location /workspace/coverage/default/284.uart_fifo_reset.1184202090
Short name T933
Test name
Test status
Simulation time 84282173922 ps
CPU time 61.84 seconds
Started Jun 09 02:21:20 PM PDT 24
Finished Jun 09 02:22:22 PM PDT 24
Peak memory 200324 kb
Host smart-547ad95f-ffd1-49e8-9aee-dee2d63718cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184202090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.1184202090
Directory /workspace/284.uart_fifo_reset/latest

Test location /workspace/coverage/default/285.uart_fifo_reset.2755639759
Short name T196
Test name
Test status
Simulation time 26806515523 ps
CPU time 54.58 seconds
Started Jun 09 02:21:21 PM PDT 24
Finished Jun 09 02:22:16 PM PDT 24
Peak memory 200372 kb
Host smart-2a1e9c84-80f7-45f1-8e9b-19a08de6fbda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755639759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.2755639759
Directory /workspace/285.uart_fifo_reset/latest

Test location /workspace/coverage/default/286.uart_fifo_reset.3482935827
Short name T1036
Test name
Test status
Simulation time 14803096590 ps
CPU time 27.93 seconds
Started Jun 09 02:21:21 PM PDT 24
Finished Jun 09 02:21:49 PM PDT 24
Peak memory 200308 kb
Host smart-58c03b1f-102c-4c96-8564-123783f35ad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482935827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.3482935827
Directory /workspace/286.uart_fifo_reset/latest

Test location /workspace/coverage/default/287.uart_fifo_reset.2095075448
Short name T948
Test name
Test status
Simulation time 10897115876 ps
CPU time 6.22 seconds
Started Jun 09 02:21:28 PM PDT 24
Finished Jun 09 02:21:35 PM PDT 24
Peak memory 200304 kb
Host smart-d14f5d77-7a9f-4d6e-bb42-77b3254f0ab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095075448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.2095075448
Directory /workspace/287.uart_fifo_reset/latest

Test location /workspace/coverage/default/288.uart_fifo_reset.2148667173
Short name T885
Test name
Test status
Simulation time 121714966472 ps
CPU time 43.41 seconds
Started Jun 09 02:21:24 PM PDT 24
Finished Jun 09 02:22:08 PM PDT 24
Peak memory 200108 kb
Host smart-20e44fe8-37a3-4d10-8a63-fb647ae5d2bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148667173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.2148667173
Directory /workspace/288.uart_fifo_reset/latest

Test location /workspace/coverage/default/289.uart_fifo_reset.2351230022
Short name T825
Test name
Test status
Simulation time 40726164380 ps
CPU time 17.64 seconds
Started Jun 09 02:21:23 PM PDT 24
Finished Jun 09 02:21:41 PM PDT 24
Peak memory 200396 kb
Host smart-0576fdf3-6b74-4ce4-a326-57dbd1eeeee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351230022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.2351230022
Directory /workspace/289.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_alert_test.3595337658
Short name T458
Test name
Test status
Simulation time 10433518 ps
CPU time 0.56 seconds
Started Jun 09 02:17:00 PM PDT 24
Finished Jun 09 02:17:01 PM PDT 24
Peak memory 194648 kb
Host smart-24887b8c-1d5b-48f7-a897-c531f46a78cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595337658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.3595337658
Directory /workspace/29.uart_alert_test/latest

Test location /workspace/coverage/default/29.uart_fifo_full.4125923796
Short name T1070
Test name
Test status
Simulation time 77065573672 ps
CPU time 36.41 seconds
Started Jun 09 02:16:52 PM PDT 24
Finished Jun 09 02:17:28 PM PDT 24
Peak memory 200416 kb
Host smart-153ea9b9-1299-42bd-88d6-86c18c5ed572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125923796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.4125923796
Directory /workspace/29.uart_fifo_full/latest

Test location /workspace/coverage/default/29.uart_fifo_overflow.2607274585
Short name T289
Test name
Test status
Simulation time 77255217002 ps
CPU time 177.8 seconds
Started Jun 09 02:16:53 PM PDT 24
Finished Jun 09 02:19:51 PM PDT 24
Peak memory 200396 kb
Host smart-661201ce-140b-4f77-88a7-cc0f64cc4bc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607274585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.2607274585
Directory /workspace/29.uart_fifo_overflow/latest

Test location /workspace/coverage/default/29.uart_fifo_reset.832272151
Short name T553
Test name
Test status
Simulation time 108271326550 ps
CPU time 92.7 seconds
Started Jun 09 02:16:52 PM PDT 24
Finished Jun 09 02:18:25 PM PDT 24
Peak memory 200396 kb
Host smart-765618a6-85fe-4f09-a7ae-cc67d398634b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832272151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.832272151
Directory /workspace/29.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_intr.722137592
Short name T409
Test name
Test status
Simulation time 38147348769 ps
CPU time 38.33 seconds
Started Jun 09 02:16:53 PM PDT 24
Finished Jun 09 02:17:31 PM PDT 24
Peak memory 200384 kb
Host smart-b17a3fef-25e4-40aa-91c5-f2d0fae0a966
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722137592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.722137592
Directory /workspace/29.uart_intr/latest

Test location /workspace/coverage/default/29.uart_long_xfer_wo_dly.1242202217
Short name T1065
Test name
Test status
Simulation time 48566936202 ps
CPU time 347.79 seconds
Started Jun 09 02:16:57 PM PDT 24
Finished Jun 09 02:22:45 PM PDT 24
Peak memory 200380 kb
Host smart-907e5adb-62a7-4d9d-b91b-1a4049038f46
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1242202217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.1242202217
Directory /workspace/29.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/29.uart_loopback.3703938294
Short name T348
Test name
Test status
Simulation time 2047555815 ps
CPU time 1.92 seconds
Started Jun 09 02:17:02 PM PDT 24
Finished Jun 09 02:17:04 PM PDT 24
Peak memory 197844 kb
Host smart-563d5633-b321-4868-8178-6fad179bb45d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703938294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_loopback.3703938294
Directory /workspace/29.uart_loopback/latest

Test location /workspace/coverage/default/29.uart_noise_filter.4099524365
Short name T692
Test name
Test status
Simulation time 32946650263 ps
CPU time 56.12 seconds
Started Jun 09 02:16:57 PM PDT 24
Finished Jun 09 02:17:53 PM PDT 24
Peak memory 200184 kb
Host smart-7aae8051-bbbe-47af-985b-9f2db06fbb7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099524365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_noise_filter.4099524365
Directory /workspace/29.uart_noise_filter/latest

Test location /workspace/coverage/default/29.uart_perf.2710035279
Short name T355
Test name
Test status
Simulation time 9510208621 ps
CPU time 144.89 seconds
Started Jun 09 02:16:56 PM PDT 24
Finished Jun 09 02:19:21 PM PDT 24
Peak memory 200580 kb
Host smart-a3f3e6f2-76a5-468a-adbf-24911554fd55
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2710035279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.2710035279
Directory /workspace/29.uart_perf/latest

Test location /workspace/coverage/default/29.uart_rx_oversample.2995626024
Short name T437
Test name
Test status
Simulation time 5742186569 ps
CPU time 10.64 seconds
Started Jun 09 02:16:51 PM PDT 24
Finished Jun 09 02:17:02 PM PDT 24
Peak memory 198556 kb
Host smart-0a8d50e2-98c0-4e1b-9756-63942642cf48
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2995626024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.2995626024
Directory /workspace/29.uart_rx_oversample/latest

Test location /workspace/coverage/default/29.uart_rx_parity_err.2588399095
Short name T836
Test name
Test status
Simulation time 69601648508 ps
CPU time 36.07 seconds
Started Jun 09 02:17:00 PM PDT 24
Finished Jun 09 02:17:37 PM PDT 24
Peak memory 200300 kb
Host smart-f6ccf3d4-db55-455c-baaf-7d4bdff527fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588399095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.2588399095
Directory /workspace/29.uart_rx_parity_err/latest

Test location /workspace/coverage/default/29.uart_rx_start_bit_filter.3282767914
Short name T280
Test name
Test status
Simulation time 44620701347 ps
CPU time 36.06 seconds
Started Jun 09 02:17:02 PM PDT 24
Finished Jun 09 02:17:39 PM PDT 24
Peak memory 196180 kb
Host smart-f251e47f-0893-4f0d-a34f-b24f74f34ad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282767914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.3282767914
Directory /workspace/29.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/29.uart_smoke.4177426017
Short name T845
Test name
Test status
Simulation time 313728536 ps
CPU time 1.72 seconds
Started Jun 09 02:16:54 PM PDT 24
Finished Jun 09 02:16:56 PM PDT 24
Peak memory 199012 kb
Host smart-62910be9-8e4d-44d7-b8b8-aad55beab258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177426017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_smoke.4177426017
Directory /workspace/29.uart_smoke/latest

Test location /workspace/coverage/default/29.uart_stress_all.1262511189
Short name T123
Test name
Test status
Simulation time 133191545705 ps
CPU time 1417.32 seconds
Started Jun 09 02:16:56 PM PDT 24
Finished Jun 09 02:40:34 PM PDT 24
Peak memory 200396 kb
Host smart-9eb19543-3809-4c38-b3f8-b6bae6c15fa7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262511189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.1262511189
Directory /workspace/29.uart_stress_all/latest

Test location /workspace/coverage/default/29.uart_stress_all_with_rand_reset.804119361
Short name T103
Test name
Test status
Simulation time 15115600365 ps
CPU time 167.23 seconds
Started Jun 09 02:16:56 PM PDT 24
Finished Jun 09 02:19:44 PM PDT 24
Peak memory 208812 kb
Host smart-249e75d2-710f-40ee-a395-c6d4240428f6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804119361 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 29.uart_stress_all_with_rand_reset.804119361
Directory /workspace/29.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.uart_tx_ovrd.933111002
Short name T659
Test name
Test status
Simulation time 13105347824 ps
CPU time 43.14 seconds
Started Jun 09 02:16:56 PM PDT 24
Finished Jun 09 02:17:40 PM PDT 24
Peak memory 200376 kb
Host smart-a142926b-dfe0-4d74-a4af-2a33049d6552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933111002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.933111002
Directory /workspace/29.uart_tx_ovrd/latest

Test location /workspace/coverage/default/29.uart_tx_rx.2978762636
Short name T318
Test name
Test status
Simulation time 62818132152 ps
CPU time 100.51 seconds
Started Jun 09 02:16:52 PM PDT 24
Finished Jun 09 02:18:33 PM PDT 24
Peak memory 200388 kb
Host smart-0d8eba0d-1a50-4967-bb9b-14f56807f444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978762636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.2978762636
Directory /workspace/29.uart_tx_rx/latest

Test location /workspace/coverage/default/290.uart_fifo_reset.3981986130
Short name T976
Test name
Test status
Simulation time 61172782812 ps
CPU time 61.26 seconds
Started Jun 09 02:21:24 PM PDT 24
Finished Jun 09 02:22:25 PM PDT 24
Peak memory 200348 kb
Host smart-62487b3d-f89b-44fa-86e8-c2c952aa7be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981986130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.3981986130
Directory /workspace/290.uart_fifo_reset/latest

Test location /workspace/coverage/default/291.uart_fifo_reset.3885304182
Short name T759
Test name
Test status
Simulation time 76950377210 ps
CPU time 30.45 seconds
Started Jun 09 02:21:24 PM PDT 24
Finished Jun 09 02:21:54 PM PDT 24
Peak memory 200336 kb
Host smart-a6d3e18a-8db2-4bf0-bdb4-008aae30b9ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885304182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.3885304182
Directory /workspace/291.uart_fifo_reset/latest

Test location /workspace/coverage/default/292.uart_fifo_reset.3480809735
Short name T1035
Test name
Test status
Simulation time 30470824044 ps
CPU time 12.35 seconds
Started Jun 09 02:21:27 PM PDT 24
Finished Jun 09 02:21:40 PM PDT 24
Peak memory 200384 kb
Host smart-7c87ec17-addf-4ab5-ba76-169898e5e3ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480809735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.3480809735
Directory /workspace/292.uart_fifo_reset/latest

Test location /workspace/coverage/default/294.uart_fifo_reset.1051458874
Short name T257
Test name
Test status
Simulation time 89167802898 ps
CPU time 151.68 seconds
Started Jun 09 02:21:23 PM PDT 24
Finished Jun 09 02:23:54 PM PDT 24
Peak memory 200284 kb
Host smart-46b14799-a651-4714-8e4d-5d4ec9cc623d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051458874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.1051458874
Directory /workspace/294.uart_fifo_reset/latest

Test location /workspace/coverage/default/295.uart_fifo_reset.345766883
Short name T615
Test name
Test status
Simulation time 62980015101 ps
CPU time 99.88 seconds
Started Jun 09 02:21:24 PM PDT 24
Finished Jun 09 02:23:05 PM PDT 24
Peak memory 200404 kb
Host smart-866dbec1-3daa-40d8-a6b0-08cf353509fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345766883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.345766883
Directory /workspace/295.uart_fifo_reset/latest

Test location /workspace/coverage/default/296.uart_fifo_reset.3091851718
Short name T745
Test name
Test status
Simulation time 166419606509 ps
CPU time 312.53 seconds
Started Jun 09 02:21:29 PM PDT 24
Finished Jun 09 02:26:41 PM PDT 24
Peak memory 200404 kb
Host smart-c8c91574-2ef6-4123-9402-e8247810df63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091851718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.3091851718
Directory /workspace/296.uart_fifo_reset/latest

Test location /workspace/coverage/default/297.uart_fifo_reset.452973779
Short name T800
Test name
Test status
Simulation time 90630472193 ps
CPU time 13.25 seconds
Started Jun 09 02:21:28 PM PDT 24
Finished Jun 09 02:21:42 PM PDT 24
Peak memory 200328 kb
Host smart-6010adf3-f348-4bb3-84e8-adfc652096d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452973779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.452973779
Directory /workspace/297.uart_fifo_reset/latest

Test location /workspace/coverage/default/299.uart_fifo_reset.4288993872
Short name T436
Test name
Test status
Simulation time 23361643386 ps
CPU time 41.63 seconds
Started Jun 09 02:21:29 PM PDT 24
Finished Jun 09 02:22:11 PM PDT 24
Peak memory 200372 kb
Host smart-22410cde-9fd3-437a-8396-d20b49c1ccec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288993872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.4288993872
Directory /workspace/299.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_alert_test.2288397306
Short name T979
Test name
Test status
Simulation time 38778256 ps
CPU time 0.54 seconds
Started Jun 09 02:13:25 PM PDT 24
Finished Jun 09 02:13:26 PM PDT 24
Peak memory 194656 kb
Host smart-d582f8d1-fe1b-4f29-89cd-79669c86ca22
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288397306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.2288397306
Directory /workspace/3.uart_alert_test/latest

Test location /workspace/coverage/default/3.uart_fifo_full.1371778041
Short name T336
Test name
Test status
Simulation time 34894157930 ps
CPU time 26.87 seconds
Started Jun 09 02:13:18 PM PDT 24
Finished Jun 09 02:13:45 PM PDT 24
Peak memory 200324 kb
Host smart-1ca8bbb1-411c-409b-a768-a2b2ae97536a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371778041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.1371778041
Directory /workspace/3.uart_fifo_full/latest

Test location /workspace/coverage/default/3.uart_fifo_overflow.2850824734
Short name T599
Test name
Test status
Simulation time 108306804589 ps
CPU time 60.12 seconds
Started Jun 09 02:13:15 PM PDT 24
Finished Jun 09 02:14:15 PM PDT 24
Peak memory 200380 kb
Host smart-5781ed3d-2bef-45a3-a9e1-36420555fe9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850824734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.2850824734
Directory /workspace/3.uart_fifo_overflow/latest

Test location /workspace/coverage/default/3.uart_fifo_reset.1387383472
Short name T221
Test name
Test status
Simulation time 93228622727 ps
CPU time 156.66 seconds
Started Jun 09 02:13:17 PM PDT 24
Finished Jun 09 02:15:53 PM PDT 24
Peak memory 200376 kb
Host smart-325662c6-7ee7-4d5d-bb97-8e750ae0561f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387383472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.1387383472
Directory /workspace/3.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_intr.4259583163
Short name T834
Test name
Test status
Simulation time 253660864129 ps
CPU time 181.62 seconds
Started Jun 09 02:13:12 PM PDT 24
Finished Jun 09 02:16:14 PM PDT 24
Peak memory 198960 kb
Host smart-205a1fd6-bf28-4d7e-96a8-f0e02f613b42
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259583163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.4259583163
Directory /workspace/3.uart_intr/latest

Test location /workspace/coverage/default/3.uart_long_xfer_wo_dly.79897628
Short name T708
Test name
Test status
Simulation time 70686602625 ps
CPU time 543.73 seconds
Started Jun 09 02:13:22 PM PDT 24
Finished Jun 09 02:22:26 PM PDT 24
Peak memory 200392 kb
Host smart-5c666127-93cb-4a97-8e4a-4e7bd1f3d587
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=79897628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.79897628
Directory /workspace/3.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/3.uart_loopback.712602573
Short name T365
Test name
Test status
Simulation time 8636233396 ps
CPU time 9.07 seconds
Started Jun 09 02:13:19 PM PDT 24
Finished Jun 09 02:13:28 PM PDT 24
Peak memory 200660 kb
Host smart-4c9a02f5-d4ac-4255-9a4d-99cdc76a9ad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712602573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_loopback.712602573
Directory /workspace/3.uart_loopback/latest

Test location /workspace/coverage/default/3.uart_perf.2068520162
Short name T631
Test name
Test status
Simulation time 18341001205 ps
CPU time 890.1 seconds
Started Jun 09 02:13:19 PM PDT 24
Finished Jun 09 02:28:09 PM PDT 24
Peak memory 200372 kb
Host smart-728b39f0-6e5f-45a2-975a-f1f147e94570
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2068520162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.2068520162
Directory /workspace/3.uart_perf/latest

Test location /workspace/coverage/default/3.uart_rx_oversample.3578327920
Short name T507
Test name
Test status
Simulation time 1628621344 ps
CPU time 1.7 seconds
Started Jun 09 02:13:14 PM PDT 24
Finished Jun 09 02:13:16 PM PDT 24
Peak memory 198436 kb
Host smart-754e42dc-90b6-484a-b1a0-1fc6254143ca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3578327920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.3578327920
Directory /workspace/3.uart_rx_oversample/latest

Test location /workspace/coverage/default/3.uart_rx_parity_err.2176959783
Short name T179
Test name
Test status
Simulation time 56119868768 ps
CPU time 26.33 seconds
Started Jun 09 02:13:20 PM PDT 24
Finished Jun 09 02:13:46 PM PDT 24
Peak memory 200408 kb
Host smart-188365b8-9b61-4556-83b4-e574bfb0df6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176959783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.2176959783
Directory /workspace/3.uart_rx_parity_err/latest

Test location /workspace/coverage/default/3.uart_rx_start_bit_filter.2169135685
Short name T393
Test name
Test status
Simulation time 4416934945 ps
CPU time 7.42 seconds
Started Jun 09 02:13:18 PM PDT 24
Finished Jun 09 02:13:26 PM PDT 24
Peak memory 196684 kb
Host smart-2d065ada-c9ea-4675-b9ac-68a6c7df3958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169135685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.2169135685
Directory /workspace/3.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/3.uart_sec_cm.1925933280
Short name T98
Test name
Test status
Simulation time 61628663 ps
CPU time 0.76 seconds
Started Jun 09 02:13:26 PM PDT 24
Finished Jun 09 02:13:27 PM PDT 24
Peak memory 218752 kb
Host smart-d6f574a0-49c9-47de-9917-76f493d3fe06
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925933280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.1925933280
Directory /workspace/3.uart_sec_cm/latest

Test location /workspace/coverage/default/3.uart_smoke.3915006445
Short name T391
Test name
Test status
Simulation time 517132685 ps
CPU time 1.16 seconds
Started Jun 09 02:13:16 PM PDT 24
Finished Jun 09 02:13:17 PM PDT 24
Peak memory 199276 kb
Host smart-5acf4e93-82c9-4862-8b3f-8a25d9358d89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915006445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_smoke.3915006445
Directory /workspace/3.uart_smoke/latest

Test location /workspace/coverage/default/3.uart_stress_all.2570368225
Short name T1044
Test name
Test status
Simulation time 30153165344 ps
CPU time 69.61 seconds
Started Jun 09 02:13:26 PM PDT 24
Finished Jun 09 02:14:36 PM PDT 24
Peak memory 200464 kb
Host smart-724f9840-ebe1-4a9a-b99a-1fac8e458317
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570368225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.2570368225
Directory /workspace/3.uart_stress_all/latest

Test location /workspace/coverage/default/3.uart_tx_ovrd.1320916534
Short name T722
Test name
Test status
Simulation time 416410656 ps
CPU time 1.13 seconds
Started Jun 09 02:13:21 PM PDT 24
Finished Jun 09 02:13:22 PM PDT 24
Peak memory 197512 kb
Host smart-a78c18bc-8632-4329-af85-f248568bb213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320916534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.1320916534
Directory /workspace/3.uart_tx_ovrd/latest

Test location /workspace/coverage/default/3.uart_tx_rx.691723797
Short name T720
Test name
Test status
Simulation time 50977509064 ps
CPU time 88.36 seconds
Started Jun 09 02:13:17 PM PDT 24
Finished Jun 09 02:14:46 PM PDT 24
Peak memory 200396 kb
Host smart-83249224-16da-49ea-a5ef-0fbfb9d97722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691723797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.691723797
Directory /workspace/3.uart_tx_rx/latest

Test location /workspace/coverage/default/30.uart_alert_test.4291944600
Short name T407
Test name
Test status
Simulation time 35901742 ps
CPU time 0.56 seconds
Started Jun 09 02:17:08 PM PDT 24
Finished Jun 09 02:17:09 PM PDT 24
Peak memory 195180 kb
Host smart-2824c44b-628e-40c3-9d70-c05ea20afc06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291944600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.4291944600
Directory /workspace/30.uart_alert_test/latest

Test location /workspace/coverage/default/30.uart_fifo_full.246426361
Short name T1011
Test name
Test status
Simulation time 97464689366 ps
CPU time 88.63 seconds
Started Jun 09 02:17:04 PM PDT 24
Finished Jun 09 02:18:33 PM PDT 24
Peak memory 200360 kb
Host smart-702e50fe-0d3e-4421-a4b8-9c0550abcc82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246426361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.246426361
Directory /workspace/30.uart_fifo_full/latest

Test location /workspace/coverage/default/30.uart_fifo_overflow.1751516523
Short name T175
Test name
Test status
Simulation time 116467204760 ps
CPU time 36.83 seconds
Started Jun 09 02:17:03 PM PDT 24
Finished Jun 09 02:17:40 PM PDT 24
Peak memory 200240 kb
Host smart-d143b4f2-a864-4ba1-9f21-f691e5ef0fa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751516523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.1751516523
Directory /workspace/30.uart_fifo_overflow/latest

Test location /workspace/coverage/default/30.uart_fifo_reset.275619668
Short name T680
Test name
Test status
Simulation time 66526002649 ps
CPU time 24.46 seconds
Started Jun 09 02:17:02 PM PDT 24
Finished Jun 09 02:17:26 PM PDT 24
Peak memory 200368 kb
Host smart-112d37ae-060c-4510-abf9-636283e4fcd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275619668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.275619668
Directory /workspace/30.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_intr.3738218503
Short name T73
Test name
Test status
Simulation time 139753222924 ps
CPU time 38.34 seconds
Started Jun 09 02:17:01 PM PDT 24
Finished Jun 09 02:17:39 PM PDT 24
Peak memory 197148 kb
Host smart-ff06292b-77d0-44f2-b6ce-8efd5b8918fb
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738218503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.3738218503
Directory /workspace/30.uart_intr/latest

Test location /workspace/coverage/default/30.uart_long_xfer_wo_dly.3397165118
Short name T484
Test name
Test status
Simulation time 83861335270 ps
CPU time 805.64 seconds
Started Jun 09 02:17:02 PM PDT 24
Finished Jun 09 02:30:28 PM PDT 24
Peak memory 200412 kb
Host smart-ca0a5867-4d2d-46ba-a3d6-9a0b364c309d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3397165118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.3397165118
Directory /workspace/30.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/30.uart_loopback.3349032474
Short name T630
Test name
Test status
Simulation time 3846626948 ps
CPU time 9.4 seconds
Started Jun 09 02:17:03 PM PDT 24
Finished Jun 09 02:17:12 PM PDT 24
Peak memory 198664 kb
Host smart-1dd3490c-c184-4871-8fdf-bd0a2e30c136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349032474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_loopback.3349032474
Directory /workspace/30.uart_loopback/latest

Test location /workspace/coverage/default/30.uart_perf.1148142958
Short name T733
Test name
Test status
Simulation time 15800555126 ps
CPU time 217.81 seconds
Started Jun 09 02:17:01 PM PDT 24
Finished Jun 09 02:20:39 PM PDT 24
Peak memory 200268 kb
Host smart-415656f5-8ea5-41f5-999b-1723397ae85f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1148142958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.1148142958
Directory /workspace/30.uart_perf/latest

Test location /workspace/coverage/default/30.uart_rx_oversample.25567762
Short name T1032
Test name
Test status
Simulation time 1802747173 ps
CPU time 9.6 seconds
Started Jun 09 02:17:02 PM PDT 24
Finished Jun 09 02:17:12 PM PDT 24
Peak memory 198392 kb
Host smart-3b5e38bb-192a-46de-a8bb-2090da1d4222
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=25567762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.25567762
Directory /workspace/30.uart_rx_oversample/latest

Test location /workspace/coverage/default/30.uart_rx_parity_err.3774359465
Short name T704
Test name
Test status
Simulation time 156912081790 ps
CPU time 37.59 seconds
Started Jun 09 02:16:59 PM PDT 24
Finished Jun 09 02:17:37 PM PDT 24
Peak memory 200384 kb
Host smart-3b8ce26b-3355-434a-ad21-d1ebdb80f22b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774359465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.3774359465
Directory /workspace/30.uart_rx_parity_err/latest

Test location /workspace/coverage/default/30.uart_rx_start_bit_filter.4209197195
Short name T497
Test name
Test status
Simulation time 2566609805 ps
CPU time 2.84 seconds
Started Jun 09 02:17:02 PM PDT 24
Finished Jun 09 02:17:05 PM PDT 24
Peak memory 196080 kb
Host smart-4844c148-33e5-44bc-9ba6-757290b1552f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209197195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.4209197195
Directory /workspace/30.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/30.uart_smoke.3335308338
Short name T555
Test name
Test status
Simulation time 127380883 ps
CPU time 0.83 seconds
Started Jun 09 02:17:04 PM PDT 24
Finished Jun 09 02:17:05 PM PDT 24
Peak memory 197596 kb
Host smart-19173dad-0fdd-45b3-8c30-9b21e1a96cd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335308338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_smoke.3335308338
Directory /workspace/30.uart_smoke/latest

Test location /workspace/coverage/default/30.uart_stress_all_with_rand_reset.1841238609
Short name T33
Test name
Test status
Simulation time 12967738069 ps
CPU time 179.04 seconds
Started Jun 09 02:17:02 PM PDT 24
Finished Jun 09 02:20:02 PM PDT 24
Peak memory 216892 kb
Host smart-a77514d2-37ca-483a-93c3-792a2afd2088
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841238609 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 30.uart_stress_all_with_rand_reset.1841238609
Directory /workspace/30.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.uart_tx_ovrd.693805357
Short name T1079
Test name
Test status
Simulation time 325398457 ps
CPU time 1.96 seconds
Started Jun 09 02:17:01 PM PDT 24
Finished Jun 09 02:17:03 PM PDT 24
Peak memory 199356 kb
Host smart-47efca4e-1de4-47f8-bbaa-aff8108b770f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693805357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.693805357
Directory /workspace/30.uart_tx_ovrd/latest

Test location /workspace/coverage/default/30.uart_tx_rx.3384257979
Short name T761
Test name
Test status
Simulation time 81298646656 ps
CPU time 45.56 seconds
Started Jun 09 02:17:01 PM PDT 24
Finished Jun 09 02:17:47 PM PDT 24
Peak memory 200376 kb
Host smart-d491f2ef-6ad3-4ae3-82e8-592f9388bc10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384257979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.3384257979
Directory /workspace/30.uart_tx_rx/latest

Test location /workspace/coverage/default/31.uart_alert_test.2665180535
Short name T776
Test name
Test status
Simulation time 11601566 ps
CPU time 0.53 seconds
Started Jun 09 02:17:12 PM PDT 24
Finished Jun 09 02:17:13 PM PDT 24
Peak memory 194688 kb
Host smart-e617f8ad-eb35-49a5-8b05-88b8833b378b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665180535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.2665180535
Directory /workspace/31.uart_alert_test/latest

Test location /workspace/coverage/default/31.uart_fifo_full.3339983459
Short name T786
Test name
Test status
Simulation time 189442647759 ps
CPU time 392.92 seconds
Started Jun 09 02:17:07 PM PDT 24
Finished Jun 09 02:23:40 PM PDT 24
Peak memory 200388 kb
Host smart-f8c935fb-0a9f-430b-b6f1-ff582d9ce075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339983459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.3339983459
Directory /workspace/31.uart_fifo_full/latest

Test location /workspace/coverage/default/31.uart_fifo_overflow.3852101054
Short name T817
Test name
Test status
Simulation time 152320819719 ps
CPU time 49.61 seconds
Started Jun 09 02:17:08 PM PDT 24
Finished Jun 09 02:17:58 PM PDT 24
Peak memory 200384 kb
Host smart-3d65a298-9c0e-48dd-8e5b-944c93272454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852101054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.3852101054
Directory /workspace/31.uart_fifo_overflow/latest

Test location /workspace/coverage/default/31.uart_fifo_reset.2594669099
Short name T589
Test name
Test status
Simulation time 74327660709 ps
CPU time 23.01 seconds
Started Jun 09 02:17:06 PM PDT 24
Finished Jun 09 02:17:29 PM PDT 24
Peak memory 200392 kb
Host smart-63b23d72-5530-425f-9226-0a4d51ee2d92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594669099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.2594669099
Directory /workspace/31.uart_fifo_reset/latest

Test location /workspace/coverage/default/31.uart_intr.513088289
Short name T89
Test name
Test status
Simulation time 15820331833 ps
CPU time 7.11 seconds
Started Jun 09 02:17:08 PM PDT 24
Finished Jun 09 02:17:15 PM PDT 24
Peak memory 199664 kb
Host smart-558449db-e0d0-4375-a44c-b1821386017f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513088289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.513088289
Directory /workspace/31.uart_intr/latest

Test location /workspace/coverage/default/31.uart_long_xfer_wo_dly.129117723
Short name T969
Test name
Test status
Simulation time 44170990890 ps
CPU time 289.67 seconds
Started Jun 09 02:17:14 PM PDT 24
Finished Jun 09 02:22:04 PM PDT 24
Peak memory 200292 kb
Host smart-d5993822-4927-4ee8-a5f3-48571496d323
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=129117723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.129117723
Directory /workspace/31.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/31.uart_loopback.1350751814
Short name T721
Test name
Test status
Simulation time 29373931 ps
CPU time 0.63 seconds
Started Jun 09 02:17:13 PM PDT 24
Finished Jun 09 02:17:14 PM PDT 24
Peak memory 196220 kb
Host smart-6de17d21-97e1-4a6e-8d1e-baceee625d8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350751814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_loopback.1350751814
Directory /workspace/31.uart_loopback/latest

Test location /workspace/coverage/default/31.uart_perf.3739472445
Short name T894
Test name
Test status
Simulation time 6043891935 ps
CPU time 113.68 seconds
Started Jun 09 02:17:10 PM PDT 24
Finished Jun 09 02:19:04 PM PDT 24
Peak memory 200308 kb
Host smart-ead88e8b-1e4e-4801-bfc9-c0132f7fbc19
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3739472445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.3739472445
Directory /workspace/31.uart_perf/latest

Test location /workspace/coverage/default/31.uart_rx_oversample.3697517850
Short name T351
Test name
Test status
Simulation time 4198206864 ps
CPU time 18.26 seconds
Started Jun 09 02:17:07 PM PDT 24
Finished Jun 09 02:17:26 PM PDT 24
Peak memory 198432 kb
Host smart-f5c7d4a0-0888-440e-9f76-d75eaade6747
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3697517850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.3697517850
Directory /workspace/31.uart_rx_oversample/latest

Test location /workspace/coverage/default/31.uart_rx_parity_err.2758941593
Short name T137
Test name
Test status
Simulation time 155288206645 ps
CPU time 114.32 seconds
Started Jun 09 02:17:15 PM PDT 24
Finished Jun 09 02:19:10 PM PDT 24
Peak memory 200380 kb
Host smart-e20c7fd1-f089-4f10-a393-ca47a1ba68a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758941593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.2758941593
Directory /workspace/31.uart_rx_parity_err/latest

Test location /workspace/coverage/default/31.uart_rx_start_bit_filter.1921192432
Short name T603
Test name
Test status
Simulation time 30553098420 ps
CPU time 46.32 seconds
Started Jun 09 02:17:14 PM PDT 24
Finished Jun 09 02:18:01 PM PDT 24
Peak memory 196388 kb
Host smart-fa97c720-d19a-4fb2-8b31-e10f70040bc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921192432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.1921192432
Directory /workspace/31.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/31.uart_smoke.1405991388
Short name T439
Test name
Test status
Simulation time 5681548085 ps
CPU time 20.4 seconds
Started Jun 09 02:17:06 PM PDT 24
Finished Jun 09 02:17:27 PM PDT 24
Peak memory 200260 kb
Host smart-8baf35f4-7412-458a-8f60-c893c2987515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405991388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_smoke.1405991388
Directory /workspace/31.uart_smoke/latest

Test location /workspace/coverage/default/31.uart_stress_all.1978347932
Short name T423
Test name
Test status
Simulation time 45103637909 ps
CPU time 208.18 seconds
Started Jun 09 02:17:13 PM PDT 24
Finished Jun 09 02:20:42 PM PDT 24
Peak memory 200388 kb
Host smart-123638f0-20c3-4c6b-83cf-5b2212cb0991
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978347932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.1978347932
Directory /workspace/31.uart_stress_all/latest

Test location /workspace/coverage/default/31.uart_tx_ovrd.3524660516
Short name T554
Test name
Test status
Simulation time 8504325847 ps
CPU time 8.29 seconds
Started Jun 09 02:17:12 PM PDT 24
Finished Jun 09 02:17:20 PM PDT 24
Peak memory 200316 kb
Host smart-8e12a251-7257-479f-822f-0cd7e65dfe80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524660516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.3524660516
Directory /workspace/31.uart_tx_ovrd/latest

Test location /workspace/coverage/default/31.uart_tx_rx.4149182174
Short name T331
Test name
Test status
Simulation time 13041130807 ps
CPU time 10.98 seconds
Started Jun 09 02:17:06 PM PDT 24
Finished Jun 09 02:17:17 PM PDT 24
Peak memory 198872 kb
Host smart-59a1aa85-faf3-46f0-8774-bac385efa15c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149182174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.4149182174
Directory /workspace/31.uart_tx_rx/latest

Test location /workspace/coverage/default/32.uart_alert_test.1107870871
Short name T392
Test name
Test status
Simulation time 19780721 ps
CPU time 0.56 seconds
Started Jun 09 02:17:20 PM PDT 24
Finished Jun 09 02:17:21 PM PDT 24
Peak memory 196024 kb
Host smart-83f55c4a-1885-40f0-bb84-46580d1aa962
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107870871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.1107870871
Directory /workspace/32.uart_alert_test/latest

Test location /workspace/coverage/default/32.uart_fifo_full.2180424010
Short name T334
Test name
Test status
Simulation time 38688067563 ps
CPU time 116.21 seconds
Started Jun 09 02:17:13 PM PDT 24
Finished Jun 09 02:19:10 PM PDT 24
Peak memory 200320 kb
Host smart-246d8b59-c39c-4256-b07c-b5dee3f33df1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180424010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.2180424010
Directory /workspace/32.uart_fifo_full/latest

Test location /workspace/coverage/default/32.uart_fifo_overflow.1784241443
Short name T600
Test name
Test status
Simulation time 31299735045 ps
CPU time 49.64 seconds
Started Jun 09 02:17:12 PM PDT 24
Finished Jun 09 02:18:01 PM PDT 24
Peak memory 200228 kb
Host smart-964ed851-a27b-44f8-aa39-a931df70599e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784241443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.1784241443
Directory /workspace/32.uart_fifo_overflow/latest

Test location /workspace/coverage/default/32.uart_fifo_reset.1195239593
Short name T1034
Test name
Test status
Simulation time 19865985949 ps
CPU time 38.5 seconds
Started Jun 09 02:17:12 PM PDT 24
Finished Jun 09 02:17:51 PM PDT 24
Peak memory 200392 kb
Host smart-6815d2c1-0712-41d9-b8e1-7c79ba94a21b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195239593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.1195239593
Directory /workspace/32.uart_fifo_reset/latest

Test location /workspace/coverage/default/32.uart_intr.3898850652
Short name T940
Test name
Test status
Simulation time 33745635558 ps
CPU time 15.02 seconds
Started Jun 09 02:17:15 PM PDT 24
Finished Jun 09 02:17:31 PM PDT 24
Peak memory 200380 kb
Host smart-d8274461-18a1-4020-b301-da17987298bc
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898850652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.3898850652
Directory /workspace/32.uart_intr/latest

Test location /workspace/coverage/default/32.uart_long_xfer_wo_dly.845010878
Short name T5
Test name
Test status
Simulation time 116444632902 ps
CPU time 1018.68 seconds
Started Jun 09 02:17:17 PM PDT 24
Finished Jun 09 02:34:16 PM PDT 24
Peak memory 200420 kb
Host smart-76bf5acf-7fc6-4898-94f3-2e4daabeb901
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=845010878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.845010878
Directory /workspace/32.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/32.uart_loopback.3725566870
Short name T1028
Test name
Test status
Simulation time 3425074925 ps
CPU time 5.73 seconds
Started Jun 09 02:17:16 PM PDT 24
Finished Jun 09 02:17:22 PM PDT 24
Peak memory 199144 kb
Host smart-6e415c46-64f6-4119-854d-d2ab59a5c67d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725566870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_loopback.3725566870
Directory /workspace/32.uart_loopback/latest

Test location /workspace/coverage/default/32.uart_perf.340509595
Short name T547
Test name
Test status
Simulation time 2716657725 ps
CPU time 53.14 seconds
Started Jun 09 02:17:17 PM PDT 24
Finished Jun 09 02:18:10 PM PDT 24
Peak memory 200244 kb
Host smart-53567962-a011-4283-a496-1ba521f826a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=340509595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.340509595
Directory /workspace/32.uart_perf/latest

Test location /workspace/coverage/default/32.uart_rx_oversample.3875268546
Short name T475
Test name
Test status
Simulation time 2316741991 ps
CPU time 11.93 seconds
Started Jun 09 02:17:13 PM PDT 24
Finished Jun 09 02:17:25 PM PDT 24
Peak memory 198408 kb
Host smart-f3d2a6c0-b2a7-4cd4-9d02-6b1ea37b0e13
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3875268546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.3875268546
Directory /workspace/32.uart_rx_oversample/latest

Test location /workspace/coverage/default/32.uart_rx_parity_err.611130078
Short name T162
Test name
Test status
Simulation time 30509755266 ps
CPU time 18.58 seconds
Started Jun 09 02:17:19 PM PDT 24
Finished Jun 09 02:17:38 PM PDT 24
Peak memory 200336 kb
Host smart-3f6e6761-74e0-496c-a425-359d95b7e72c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611130078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.611130078
Directory /workspace/32.uart_rx_parity_err/latest

Test location /workspace/coverage/default/32.uart_rx_start_bit_filter.3249878826
Short name T311
Test name
Test status
Simulation time 35338112558 ps
CPU time 26.41 seconds
Started Jun 09 02:17:18 PM PDT 24
Finished Jun 09 02:17:44 PM PDT 24
Peak memory 196468 kb
Host smart-bacd4db5-b280-4fb8-b194-110b597230db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249878826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.3249878826
Directory /workspace/32.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/32.uart_smoke.1433587018
Short name T40
Test name
Test status
Simulation time 719762187 ps
CPU time 1.71 seconds
Started Jun 09 02:17:12 PM PDT 24
Finished Jun 09 02:17:14 PM PDT 24
Peak memory 200164 kb
Host smart-a6ddcea2-1c63-4ccc-8243-f8ea75e74e62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433587018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_smoke.1433587018
Directory /workspace/32.uart_smoke/latest

Test location /workspace/coverage/default/32.uart_stress_all_with_rand_reset.3725927275
Short name T118
Test name
Test status
Simulation time 85260777451 ps
CPU time 267.06 seconds
Started Jun 09 02:17:19 PM PDT 24
Finished Jun 09 02:21:46 PM PDT 24
Peak memory 209652 kb
Host smart-3072b5e9-2cda-4550-b72c-f6cf6ccf4b37
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725927275 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 32.uart_stress_all_with_rand_reset.3725927275
Directory /workspace/32.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.uart_tx_ovrd.1363243956
Short name T772
Test name
Test status
Simulation time 1269248834 ps
CPU time 1.52 seconds
Started Jun 09 02:17:19 PM PDT 24
Finished Jun 09 02:17:21 PM PDT 24
Peak memory 198720 kb
Host smart-20363b9d-25ae-4813-b58e-9425c4776f31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363243956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.1363243956
Directory /workspace/32.uart_tx_ovrd/latest

Test location /workspace/coverage/default/32.uart_tx_rx.3510097856
Short name T493
Test name
Test status
Simulation time 25495864358 ps
CPU time 11.44 seconds
Started Jun 09 02:17:13 PM PDT 24
Finished Jun 09 02:17:24 PM PDT 24
Peak memory 200412 kb
Host smart-e1dc4d3d-9854-438f-b615-0517d4ebe906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510097856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.3510097856
Directory /workspace/32.uart_tx_rx/latest

Test location /workspace/coverage/default/33.uart_alert_test.3733443351
Short name T968
Test name
Test status
Simulation time 12022110 ps
CPU time 0.56 seconds
Started Jun 09 02:17:26 PM PDT 24
Finished Jun 09 02:17:27 PM PDT 24
Peak memory 194904 kb
Host smart-887499b0-b442-4fa1-b150-b26715b779a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733443351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.3733443351
Directory /workspace/33.uart_alert_test/latest

Test location /workspace/coverage/default/33.uart_fifo_full.1643679739
Short name T802
Test name
Test status
Simulation time 250518078240 ps
CPU time 319.67 seconds
Started Jun 09 02:17:20 PM PDT 24
Finished Jun 09 02:22:40 PM PDT 24
Peak memory 200284 kb
Host smart-df6eff1e-09a1-436c-9aca-730e7963f42d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643679739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.1643679739
Directory /workspace/33.uart_fifo_full/latest

Test location /workspace/coverage/default/33.uart_fifo_overflow.1865584320
Short name T110
Test name
Test status
Simulation time 107702694923 ps
CPU time 149.98 seconds
Started Jun 09 02:17:17 PM PDT 24
Finished Jun 09 02:19:47 PM PDT 24
Peak memory 200368 kb
Host smart-87fa5189-4754-4484-8cde-2a47b8d8ac62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865584320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.1865584320
Directory /workspace/33.uart_fifo_overflow/latest

Test location /workspace/coverage/default/33.uart_fifo_reset.2624498212
Short name T791
Test name
Test status
Simulation time 37246136967 ps
CPU time 83.77 seconds
Started Jun 09 02:17:19 PM PDT 24
Finished Jun 09 02:18:43 PM PDT 24
Peak memory 200268 kb
Host smart-94a41d51-3729-4532-8092-68fe532bfa4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624498212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.2624498212
Directory /workspace/33.uart_fifo_reset/latest

Test location /workspace/coverage/default/33.uart_intr.2295481358
Short name T866
Test name
Test status
Simulation time 24371604742 ps
CPU time 41.32 seconds
Started Jun 09 02:17:19 PM PDT 24
Finished Jun 09 02:18:00 PM PDT 24
Peak memory 199864 kb
Host smart-3c767849-7833-4ea1-9993-e612d8005f59
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295481358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.2295481358
Directory /workspace/33.uart_intr/latest

Test location /workspace/coverage/default/33.uart_long_xfer_wo_dly.2489360079
Short name T425
Test name
Test status
Simulation time 96795473044 ps
CPU time 691.05 seconds
Started Jun 09 02:17:25 PM PDT 24
Finished Jun 09 02:28:57 PM PDT 24
Peak memory 200340 kb
Host smart-ee53bd79-93e4-46fd-b6e3-67c08df0d184
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2489360079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.2489360079
Directory /workspace/33.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/33.uart_loopback.2138302066
Short name T440
Test name
Test status
Simulation time 3421341784 ps
CPU time 5.88 seconds
Started Jun 09 02:17:22 PM PDT 24
Finished Jun 09 02:17:28 PM PDT 24
Peak memory 196148 kb
Host smart-0f483a00-dc71-4dcd-af38-aab4a2b433fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138302066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_loopback.2138302066
Directory /workspace/33.uart_loopback/latest

Test location /workspace/coverage/default/33.uart_perf.2922031521
Short name T689
Test name
Test status
Simulation time 13269750632 ps
CPU time 155.61 seconds
Started Jun 09 02:17:21 PM PDT 24
Finished Jun 09 02:19:57 PM PDT 24
Peak memory 200320 kb
Host smart-51dbd13a-ca89-495c-b62c-2d4cff36e307
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2922031521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.2922031521
Directory /workspace/33.uart_perf/latest

Test location /workspace/coverage/default/33.uart_rx_oversample.1182270933
Short name T23
Test name
Test status
Simulation time 3361410948 ps
CPU time 19.94 seconds
Started Jun 09 02:17:19 PM PDT 24
Finished Jun 09 02:17:39 PM PDT 24
Peak memory 199232 kb
Host smart-7bb19a02-1b59-4bc4-b90a-ed0d13d14c48
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1182270933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.1182270933
Directory /workspace/33.uart_rx_oversample/latest

Test location /workspace/coverage/default/33.uart_rx_parity_err.2114518804
Short name T667
Test name
Test status
Simulation time 67166383406 ps
CPU time 108.57 seconds
Started Jun 09 02:17:24 PM PDT 24
Finished Jun 09 02:19:12 PM PDT 24
Peak memory 200332 kb
Host smart-9a3467e7-c636-4e86-985e-ebeb95d6b570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114518804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.2114518804
Directory /workspace/33.uart_rx_parity_err/latest

Test location /workspace/coverage/default/33.uart_rx_start_bit_filter.1684696048
Short name T456
Test name
Test status
Simulation time 6749986641 ps
CPU time 11.35 seconds
Started Jun 09 02:17:23 PM PDT 24
Finished Jun 09 02:17:35 PM PDT 24
Peak memory 196648 kb
Host smart-9f8b2c4b-f856-4f3f-82d8-6a152c510e67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684696048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.1684696048
Directory /workspace/33.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/33.uart_smoke.3974848938
Short name T843
Test name
Test status
Simulation time 553389480 ps
CPU time 2.1 seconds
Started Jun 09 02:17:19 PM PDT 24
Finished Jun 09 02:17:21 PM PDT 24
Peak memory 199804 kb
Host smart-edae62e0-a6bc-46db-81b5-26cf03558d25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974848938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_smoke.3974848938
Directory /workspace/33.uart_smoke/latest

Test location /workspace/coverage/default/33.uart_stress_all_with_rand_reset.3462334584
Short name T1009
Test name
Test status
Simulation time 80000417906 ps
CPU time 558.33 seconds
Started Jun 09 02:17:28 PM PDT 24
Finished Jun 09 02:26:47 PM PDT 24
Peak memory 215012 kb
Host smart-a60b24ff-8cfb-4583-a71a-b2b18d159576
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462334584 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 33.uart_stress_all_with_rand_reset.3462334584
Directory /workspace/33.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.uart_tx_ovrd.1177156941
Short name T906
Test name
Test status
Simulation time 2364320935 ps
CPU time 3.3 seconds
Started Jun 09 02:17:23 PM PDT 24
Finished Jun 09 02:17:26 PM PDT 24
Peak memory 198792 kb
Host smart-90ea94fd-e29b-4964-855d-40b6f904c874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177156941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.1177156941
Directory /workspace/33.uart_tx_ovrd/latest

Test location /workspace/coverage/default/33.uart_tx_rx.2799023854
Short name T929
Test name
Test status
Simulation time 5227800098 ps
CPU time 7.91 seconds
Started Jun 09 02:17:20 PM PDT 24
Finished Jun 09 02:17:28 PM PDT 24
Peak memory 197104 kb
Host smart-0e50039d-a04a-4938-9527-73d783252488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799023854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.2799023854
Directory /workspace/33.uart_tx_rx/latest

Test location /workspace/coverage/default/34.uart_alert_test.3278746841
Short name T364
Test name
Test status
Simulation time 29939879 ps
CPU time 0.58 seconds
Started Jun 09 02:17:40 PM PDT 24
Finished Jun 09 02:17:40 PM PDT 24
Peak memory 195456 kb
Host smart-071e8f31-4915-43ee-b8e7-02699d22a896
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278746841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.3278746841
Directory /workspace/34.uart_alert_test/latest

Test location /workspace/coverage/default/34.uart_fifo_full.798313770
Short name T606
Test name
Test status
Simulation time 332579023928 ps
CPU time 222.47 seconds
Started Jun 09 02:17:29 PM PDT 24
Finished Jun 09 02:21:11 PM PDT 24
Peak memory 200312 kb
Host smart-025af00f-a47a-4ec3-a604-cae98cbf5971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798313770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.798313770
Directory /workspace/34.uart_fifo_full/latest

Test location /workspace/coverage/default/34.uart_fifo_overflow.3399532063
Short name T435
Test name
Test status
Simulation time 14852002849 ps
CPU time 24.94 seconds
Started Jun 09 02:17:27 PM PDT 24
Finished Jun 09 02:17:52 PM PDT 24
Peak memory 200308 kb
Host smart-b7b2114c-b578-4b02-923f-7e52e9acf9bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399532063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.3399532063
Directory /workspace/34.uart_fifo_overflow/latest

Test location /workspace/coverage/default/34.uart_fifo_reset.3832028404
Short name T241
Test name
Test status
Simulation time 128551341148 ps
CPU time 114.83 seconds
Started Jun 09 02:17:26 PM PDT 24
Finished Jun 09 02:19:21 PM PDT 24
Peak memory 200428 kb
Host smart-3fb09038-4b38-44ca-942d-55bea174694c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832028404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.3832028404
Directory /workspace/34.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_intr.2234512036
Short name T1078
Test name
Test status
Simulation time 29909161529 ps
CPU time 25.03 seconds
Started Jun 09 02:17:30 PM PDT 24
Finished Jun 09 02:17:56 PM PDT 24
Peak memory 198892 kb
Host smart-137a32c3-f3ea-4c85-829b-530db5e08476
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234512036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.2234512036
Directory /workspace/34.uart_intr/latest

Test location /workspace/coverage/default/34.uart_long_xfer_wo_dly.2713614563
Short name T269
Test name
Test status
Simulation time 144490846133 ps
CPU time 348.16 seconds
Started Jun 09 02:17:31 PM PDT 24
Finished Jun 09 02:23:19 PM PDT 24
Peak memory 200300 kb
Host smart-cf0f3163-cf9f-43e8-b0d2-a815c0d95d05
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2713614563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.2713614563
Directory /workspace/34.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/34.uart_loopback.2626876016
Short name T359
Test name
Test status
Simulation time 3612836159 ps
CPU time 7.44 seconds
Started Jun 09 02:17:34 PM PDT 24
Finished Jun 09 02:17:42 PM PDT 24
Peak memory 198832 kb
Host smart-ddb6e370-8904-4c9e-973c-35f2bfa740ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626876016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_loopback.2626876016
Directory /workspace/34.uart_loopback/latest

Test location /workspace/coverage/default/34.uart_perf.2016630132
Short name T705
Test name
Test status
Simulation time 16853653364 ps
CPU time 206.16 seconds
Started Jun 09 02:17:34 PM PDT 24
Finished Jun 09 02:21:00 PM PDT 24
Peak memory 200360 kb
Host smart-b477822c-2873-4c2d-8c6b-f2e469518312
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2016630132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.2016630132
Directory /workspace/34.uart_perf/latest

Test location /workspace/coverage/default/34.uart_rx_oversample.1581430804
Short name T701
Test name
Test status
Simulation time 1501339522 ps
CPU time 2.09 seconds
Started Jun 09 02:17:27 PM PDT 24
Finished Jun 09 02:17:29 PM PDT 24
Peak memory 198488 kb
Host smart-91fa69fc-eaa1-4c5d-830e-673e7ee48548
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1581430804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.1581430804
Directory /workspace/34.uart_rx_oversample/latest

Test location /workspace/coverage/default/34.uart_rx_parity_err.4031594417
Short name T178
Test name
Test status
Simulation time 36333237541 ps
CPU time 33.75 seconds
Started Jun 09 02:17:34 PM PDT 24
Finished Jun 09 02:18:08 PM PDT 24
Peak memory 200356 kb
Host smart-227e6d43-3900-4448-beeb-65b24f60a2ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031594417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.4031594417
Directory /workspace/34.uart_rx_parity_err/latest

Test location /workspace/coverage/default/34.uart_rx_start_bit_filter.3312208975
Short name T636
Test name
Test status
Simulation time 5075912553 ps
CPU time 7.09 seconds
Started Jun 09 02:17:40 PM PDT 24
Finished Jun 09 02:17:47 PM PDT 24
Peak memory 195916 kb
Host smart-11038c9e-349a-4205-894d-ab2aa08f2436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312208975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.3312208975
Directory /workspace/34.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/34.uart_smoke.1668226828
Short name T49
Test name
Test status
Simulation time 517518810 ps
CPU time 1.15 seconds
Started Jun 09 02:17:27 PM PDT 24
Finished Jun 09 02:17:28 PM PDT 24
Peak memory 198624 kb
Host smart-277d294b-bfd9-4246-817c-341ca539cd79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668226828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_smoke.1668226828
Directory /workspace/34.uart_smoke/latest

Test location /workspace/coverage/default/34.uart_stress_all.4233327658
Short name T769
Test name
Test status
Simulation time 80110737521 ps
CPU time 471.8 seconds
Started Jun 09 02:17:42 PM PDT 24
Finished Jun 09 02:25:34 PM PDT 24
Peak memory 200384 kb
Host smart-952e3ff7-a796-442e-9c56-8f91adec7bab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233327658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.4233327658
Directory /workspace/34.uart_stress_all/latest

Test location /workspace/coverage/default/34.uart_stress_all_with_rand_reset.1912269800
Short name T101
Test name
Test status
Simulation time 44864564145 ps
CPU time 94.57 seconds
Started Jun 09 02:17:33 PM PDT 24
Finished Jun 09 02:19:07 PM PDT 24
Peak memory 216532 kb
Host smart-fb99f922-4ea6-46ea-a990-d443311b9f1d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912269800 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 34.uart_stress_all_with_rand_reset.1912269800
Directory /workspace/34.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.uart_tx_ovrd.1090863436
Short name T1037
Test name
Test status
Simulation time 6856620283 ps
CPU time 17.65 seconds
Started Jun 09 02:17:35 PM PDT 24
Finished Jun 09 02:17:52 PM PDT 24
Peak memory 199864 kb
Host smart-f5bf52c6-5bd0-462f-bc87-a080e8a606e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090863436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.1090863436
Directory /workspace/34.uart_tx_ovrd/latest

Test location /workspace/coverage/default/34.uart_tx_rx.1982238597
Short name T412
Test name
Test status
Simulation time 25903514557 ps
CPU time 15.2 seconds
Started Jun 09 02:17:30 PM PDT 24
Finished Jun 09 02:17:45 PM PDT 24
Peak memory 200412 kb
Host smart-b5da7cfa-4153-4331-95da-439d70bcaba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982238597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.1982238597
Directory /workspace/34.uart_tx_rx/latest

Test location /workspace/coverage/default/35.uart_alert_test.3705553881
Short name T346
Test name
Test status
Simulation time 15263964 ps
CPU time 0.57 seconds
Started Jun 09 02:17:42 PM PDT 24
Finished Jun 09 02:17:43 PM PDT 24
Peak memory 195708 kb
Host smart-8f528c59-0f51-4f4d-881f-1aa4022753f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705553881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.3705553881
Directory /workspace/35.uart_alert_test/latest

Test location /workspace/coverage/default/35.uart_fifo_full.2528417442
Short name T1014
Test name
Test status
Simulation time 78445442760 ps
CPU time 21.82 seconds
Started Jun 09 02:17:33 PM PDT 24
Finished Jun 09 02:17:55 PM PDT 24
Peak memory 200332 kb
Host smart-8928f8e1-3764-45f9-a099-b7b139a9d125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528417442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.2528417442
Directory /workspace/35.uart_fifo_full/latest

Test location /workspace/coverage/default/35.uart_fifo_overflow.1620675476
Short name T841
Test name
Test status
Simulation time 23523310526 ps
CPU time 6.92 seconds
Started Jun 09 02:17:36 PM PDT 24
Finished Jun 09 02:17:43 PM PDT 24
Peak memory 200172 kb
Host smart-d7638510-049a-4f57-ad2a-d5617bf7a286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620675476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.1620675476
Directory /workspace/35.uart_fifo_overflow/latest

Test location /workspace/coverage/default/35.uart_fifo_reset.1301227430
Short name T177
Test name
Test status
Simulation time 34687791241 ps
CPU time 14.73 seconds
Started Jun 09 02:17:37 PM PDT 24
Finished Jun 09 02:17:52 PM PDT 24
Peak memory 199980 kb
Host smart-50ebf754-5a04-4aec-b955-4ff47787c7aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301227430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.1301227430
Directory /workspace/35.uart_fifo_reset/latest

Test location /workspace/coverage/default/35.uart_intr.304548303
Short name T684
Test name
Test status
Simulation time 51451295139 ps
CPU time 86.27 seconds
Started Jun 09 02:17:37 PM PDT 24
Finished Jun 09 02:19:04 PM PDT 24
Peak memory 199984 kb
Host smart-35cae684-96e7-4fc3-9d2c-60c4f132f5bd
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304548303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.304548303
Directory /workspace/35.uart_intr/latest

Test location /workspace/coverage/default/35.uart_long_xfer_wo_dly.4017224673
Short name T549
Test name
Test status
Simulation time 85732807788 ps
CPU time 218.28 seconds
Started Jun 09 02:17:43 PM PDT 24
Finished Jun 09 02:21:21 PM PDT 24
Peak memory 200372 kb
Host smart-77e74af1-a7ee-4e12-a185-f1882c3558bb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4017224673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.4017224673
Directory /workspace/35.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/35.uart_loopback.2710676259
Short name T795
Test name
Test status
Simulation time 98336003 ps
CPU time 0.78 seconds
Started Jun 09 02:17:37 PM PDT 24
Finished Jun 09 02:17:38 PM PDT 24
Peak memory 196304 kb
Host smart-d910edc2-11ff-49bf-9fd7-ea3541bdc6fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710676259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_loopback.2710676259
Directory /workspace/35.uart_loopback/latest

Test location /workspace/coverage/default/35.uart_perf.1896239175
Short name T612
Test name
Test status
Simulation time 6732485255 ps
CPU time 93.97 seconds
Started Jun 09 02:17:41 PM PDT 24
Finished Jun 09 02:19:15 PM PDT 24
Peak memory 200380 kb
Host smart-b0e18d1e-843b-49d1-97b4-1bfa660dcf01
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1896239175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.1896239175
Directory /workspace/35.uart_perf/latest

Test location /workspace/coverage/default/35.uart_rx_oversample.1993775126
Short name T552
Test name
Test status
Simulation time 7002541407 ps
CPU time 31.04 seconds
Started Jun 09 02:17:37 PM PDT 24
Finished Jun 09 02:18:08 PM PDT 24
Peak memory 198536 kb
Host smart-8ffe693e-c305-4c87-8ce5-856e075f422a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1993775126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.1993775126
Directory /workspace/35.uart_rx_oversample/latest

Test location /workspace/coverage/default/35.uart_rx_parity_err.1797707617
Short name T170
Test name
Test status
Simulation time 36930919219 ps
CPU time 15.19 seconds
Started Jun 09 02:17:34 PM PDT 24
Finished Jun 09 02:17:50 PM PDT 24
Peak memory 200592 kb
Host smart-f2335977-0040-42bc-b82f-725cda6ff5f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797707617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.1797707617
Directory /workspace/35.uart_rx_parity_err/latest

Test location /workspace/coverage/default/35.uart_rx_start_bit_filter.1863929516
Short name T994
Test name
Test status
Simulation time 2514783747 ps
CPU time 4.93 seconds
Started Jun 09 02:17:37 PM PDT 24
Finished Jun 09 02:17:42 PM PDT 24
Peak memory 196300 kb
Host smart-20da8f2c-617e-4e60-b49d-98a5919ed144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863929516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.1863929516
Directory /workspace/35.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/35.uart_smoke.3651242083
Short name T533
Test name
Test status
Simulation time 456142313 ps
CPU time 0.95 seconds
Started Jun 09 02:17:31 PM PDT 24
Finished Jun 09 02:17:32 PM PDT 24
Peak memory 198900 kb
Host smart-2878166c-9fb4-4959-b672-20427fcd6939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651242083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_smoke.3651242083
Directory /workspace/35.uart_smoke/latest

Test location /workspace/coverage/default/35.uart_stress_all.1518440855
Short name T1015
Test name
Test status
Simulation time 57519299073 ps
CPU time 45.06 seconds
Started Jun 09 02:17:41 PM PDT 24
Finished Jun 09 02:18:26 PM PDT 24
Peak memory 200336 kb
Host smart-6c21f2f3-d7f5-40ee-926f-3b03ebe04bcd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518440855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.1518440855
Directory /workspace/35.uart_stress_all/latest

Test location /workspace/coverage/default/35.uart_stress_all_with_rand_reset.3763402815
Short name T967
Test name
Test status
Simulation time 25793253260 ps
CPU time 304.88 seconds
Started Jun 09 02:17:41 PM PDT 24
Finished Jun 09 02:22:46 PM PDT 24
Peak memory 216908 kb
Host smart-b2d641ae-7866-4744-b79c-3601213c3fae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763402815 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 35.uart_stress_all_with_rand_reset.3763402815
Directory /workspace/35.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.uart_tx_ovrd.2129006587
Short name T261
Test name
Test status
Simulation time 773824977 ps
CPU time 1.46 seconds
Started Jun 09 02:17:37 PM PDT 24
Finished Jun 09 02:17:39 PM PDT 24
Peak memory 198168 kb
Host smart-dd75e0af-a3bc-41f8-b14f-e33ce81e8c56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129006587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.2129006587
Directory /workspace/35.uart_tx_ovrd/latest

Test location /workspace/coverage/default/35.uart_tx_rx.600633422
Short name T482
Test name
Test status
Simulation time 46157820286 ps
CPU time 49.33 seconds
Started Jun 09 02:17:32 PM PDT 24
Finished Jun 09 02:18:22 PM PDT 24
Peak memory 200348 kb
Host smart-1edd4f53-a7d9-429f-93de-ba383894a8a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600633422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.600633422
Directory /workspace/35.uart_tx_rx/latest

Test location /workspace/coverage/default/36.uart_alert_test.3800795327
Short name T839
Test name
Test status
Simulation time 12195630 ps
CPU time 0.55 seconds
Started Jun 09 02:17:49 PM PDT 24
Finished Jun 09 02:17:50 PM PDT 24
Peak memory 194756 kb
Host smart-3dc4583f-00db-43fb-a713-c013a4cb237e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800795327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.3800795327
Directory /workspace/36.uart_alert_test/latest

Test location /workspace/coverage/default/36.uart_fifo_full.2656402482
Short name T420
Test name
Test status
Simulation time 186017794765 ps
CPU time 343.94 seconds
Started Jun 09 02:17:41 PM PDT 24
Finished Jun 09 02:23:25 PM PDT 24
Peak memory 200324 kb
Host smart-491c49cc-bf6a-4e7f-9f2c-275741ae9810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656402482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.2656402482
Directory /workspace/36.uart_fifo_full/latest

Test location /workspace/coverage/default/36.uart_fifo_overflow.3770916770
Short name T402
Test name
Test status
Simulation time 65051070969 ps
CPU time 135.69 seconds
Started Jun 09 02:17:41 PM PDT 24
Finished Jun 09 02:19:57 PM PDT 24
Peak memory 200380 kb
Host smart-9db34d06-14b9-4b21-a8b3-261f79e80bea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770916770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.3770916770
Directory /workspace/36.uart_fifo_overflow/latest

Test location /workspace/coverage/default/36.uart_fifo_reset.4206428747
Short name T1041
Test name
Test status
Simulation time 55925916698 ps
CPU time 25.73 seconds
Started Jun 09 02:17:46 PM PDT 24
Finished Jun 09 02:18:12 PM PDT 24
Peak memory 200392 kb
Host smart-c7a57eaf-133c-44b6-a16f-1adc36890959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206428747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.4206428747
Directory /workspace/36.uart_fifo_reset/latest

Test location /workspace/coverage/default/36.uart_intr.1706537765
Short name T859
Test name
Test status
Simulation time 39225392917 ps
CPU time 15.58 seconds
Started Jun 09 02:17:47 PM PDT 24
Finished Jun 09 02:18:02 PM PDT 24
Peak memory 200396 kb
Host smart-5dadcb8c-24a5-4aec-b540-4f890aaef50d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706537765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.1706537765
Directory /workspace/36.uart_intr/latest

Test location /workspace/coverage/default/36.uart_long_xfer_wo_dly.994920542
Short name T278
Test name
Test status
Simulation time 126562491397 ps
CPU time 799.37 seconds
Started Jun 09 02:17:46 PM PDT 24
Finished Jun 09 02:31:06 PM PDT 24
Peak memory 200388 kb
Host smart-369e817d-67c9-437a-a9f9-b6181054eac4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=994920542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.994920542
Directory /workspace/36.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/36.uart_loopback.3572842409
Short name T808
Test name
Test status
Simulation time 2509562982 ps
CPU time 2.74 seconds
Started Jun 09 02:17:45 PM PDT 24
Finished Jun 09 02:17:48 PM PDT 24
Peak memory 198036 kb
Host smart-c66a9b2f-dc06-4440-ad1f-60d701e91a0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572842409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_loopback.3572842409
Directory /workspace/36.uart_loopback/latest

Test location /workspace/coverage/default/36.uart_perf.943175026
Short name T528
Test name
Test status
Simulation time 7501905776 ps
CPU time 463.72 seconds
Started Jun 09 02:17:46 PM PDT 24
Finished Jun 09 02:25:30 PM PDT 24
Peak memory 200304 kb
Host smart-6db3f9a6-144c-4c6e-b6a1-60f108176384
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=943175026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.943175026
Directory /workspace/36.uart_perf/latest

Test location /workspace/coverage/default/36.uart_rx_oversample.2565303695
Short name T513
Test name
Test status
Simulation time 2208510425 ps
CPU time 10.16 seconds
Started Jun 09 02:17:46 PM PDT 24
Finished Jun 09 02:17:57 PM PDT 24
Peak memory 199456 kb
Host smart-72800eb4-178a-49d9-af8d-2a544bf7beea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2565303695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.2565303695
Directory /workspace/36.uart_rx_oversample/latest

Test location /workspace/coverage/default/36.uart_rx_parity_err.3583377346
Short name T788
Test name
Test status
Simulation time 33628346372 ps
CPU time 48.86 seconds
Started Jun 09 02:17:46 PM PDT 24
Finished Jun 09 02:18:35 PM PDT 24
Peak memory 200344 kb
Host smart-a1625605-e114-4906-b7e0-60fc21ff3380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583377346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.3583377346
Directory /workspace/36.uart_rx_parity_err/latest

Test location /workspace/coverage/default/36.uart_rx_start_bit_filter.636012937
Short name T306
Test name
Test status
Simulation time 37057262457 ps
CPU time 31.77 seconds
Started Jun 09 02:17:46 PM PDT 24
Finished Jun 09 02:18:18 PM PDT 24
Peak memory 196384 kb
Host smart-d65669e6-f7a1-473d-9c55-be3a486b14a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636012937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.636012937
Directory /workspace/36.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/36.uart_smoke.3925255003
Short name T790
Test name
Test status
Simulation time 705614584 ps
CPU time 1.82 seconds
Started Jun 09 02:17:41 PM PDT 24
Finished Jun 09 02:17:43 PM PDT 24
Peak memory 199020 kb
Host smart-d473abd5-e8b3-415b-8f11-bdc4d877da4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925255003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_smoke.3925255003
Directory /workspace/36.uart_smoke/latest

Test location /workspace/coverage/default/36.uart_tx_ovrd.830381490
Short name T417
Test name
Test status
Simulation time 1482055401 ps
CPU time 1.45 seconds
Started Jun 09 02:17:47 PM PDT 24
Finished Jun 09 02:17:49 PM PDT 24
Peak memory 199472 kb
Host smart-fb194060-e5ec-4247-b1b0-8d4950822b44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830381490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.830381490
Directory /workspace/36.uart_tx_ovrd/latest

Test location /workspace/coverage/default/36.uart_tx_rx.3560399120
Short name T382
Test name
Test status
Simulation time 40124735727 ps
CPU time 27.42 seconds
Started Jun 09 02:17:41 PM PDT 24
Finished Jun 09 02:18:08 PM PDT 24
Peak memory 200380 kb
Host smart-23839801-c5b8-4e4c-90eb-2a9829687ae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560399120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.3560399120
Directory /workspace/36.uart_tx_rx/latest

Test location /workspace/coverage/default/37.uart_alert_test.1253511980
Short name T25
Test name
Test status
Simulation time 15774823 ps
CPU time 0.55 seconds
Started Jun 09 02:18:02 PM PDT 24
Finished Jun 09 02:18:03 PM PDT 24
Peak memory 195748 kb
Host smart-4413a275-a1fc-4172-b1bc-f6673ff138f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253511980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.1253511980
Directory /workspace/37.uart_alert_test/latest

Test location /workspace/coverage/default/37.uart_fifo_full.4036331034
Short name T139
Test name
Test status
Simulation time 123949171927 ps
CPU time 41.93 seconds
Started Jun 09 02:17:57 PM PDT 24
Finished Jun 09 02:18:40 PM PDT 24
Peak memory 200368 kb
Host smart-22db5a4e-0271-4308-8fdd-dd2ed722d97b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036331034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.4036331034
Directory /workspace/37.uart_fifo_full/latest

Test location /workspace/coverage/default/37.uart_fifo_overflow.1342033069
Short name T703
Test name
Test status
Simulation time 90601515443 ps
CPU time 192.48 seconds
Started Jun 09 02:17:59 PM PDT 24
Finished Jun 09 02:21:11 PM PDT 24
Peak memory 200356 kb
Host smart-8bc6406c-468d-46e8-ad21-a72b481099be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342033069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.1342033069
Directory /workspace/37.uart_fifo_overflow/latest

Test location /workspace/coverage/default/37.uart_fifo_reset.215149379
Short name T749
Test name
Test status
Simulation time 48073524887 ps
CPU time 113.11 seconds
Started Jun 09 02:17:57 PM PDT 24
Finished Jun 09 02:19:51 PM PDT 24
Peak memory 200388 kb
Host smart-0155955a-9fdb-49a6-a6e4-09daf846bee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215149379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.215149379
Directory /workspace/37.uart_fifo_reset/latest

Test location /workspace/coverage/default/37.uart_intr.2777232526
Short name T39
Test name
Test status
Simulation time 5274225789 ps
CPU time 3.27 seconds
Started Jun 09 02:17:50 PM PDT 24
Finished Jun 09 02:17:53 PM PDT 24
Peak memory 200300 kb
Host smart-28f48908-6683-4ae7-a6fc-3d6cc390a447
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777232526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.2777232526
Directory /workspace/37.uart_intr/latest

Test location /workspace/coverage/default/37.uart_long_xfer_wo_dly.3464292930
Short name T828
Test name
Test status
Simulation time 134648750827 ps
CPU time 130.39 seconds
Started Jun 09 02:17:56 PM PDT 24
Finished Jun 09 02:20:07 PM PDT 24
Peak memory 200356 kb
Host smart-239d9335-c200-4990-8b6e-2244dcc9c4db
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3464292930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.3464292930
Directory /workspace/37.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/37.uart_loopback.3319387100
Short name T590
Test name
Test status
Simulation time 9535855751 ps
CPU time 3.31 seconds
Started Jun 09 02:17:55 PM PDT 24
Finished Jun 09 02:17:59 PM PDT 24
Peak memory 200028 kb
Host smart-115b05aa-71e7-4955-b33b-12f345957ffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319387100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_loopback.3319387100
Directory /workspace/37.uart_loopback/latest

Test location /workspace/coverage/default/37.uart_perf.2196518904
Short name T585
Test name
Test status
Simulation time 12642532352 ps
CPU time 206.28 seconds
Started Jun 09 02:17:55 PM PDT 24
Finished Jun 09 02:21:22 PM PDT 24
Peak memory 200324 kb
Host smart-bb61d49f-a505-49e4-aa61-2ada601d2fd1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2196518904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.2196518904
Directory /workspace/37.uart_perf/latest

Test location /workspace/coverage/default/37.uart_rx_oversample.3857339009
Short name T901
Test name
Test status
Simulation time 6305556128 ps
CPU time 15.96 seconds
Started Jun 09 02:17:49 PM PDT 24
Finished Jun 09 02:18:05 PM PDT 24
Peak memory 198732 kb
Host smart-16a6fb8f-9c02-4b77-b3a2-0fe58f42c740
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3857339009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.3857339009
Directory /workspace/37.uart_rx_oversample/latest

Test location /workspace/coverage/default/37.uart_rx_parity_err.1259610984
Short name T986
Test name
Test status
Simulation time 91655289083 ps
CPU time 84.72 seconds
Started Jun 09 02:17:50 PM PDT 24
Finished Jun 09 02:19:15 PM PDT 24
Peak memory 200432 kb
Host smart-943dd24d-f250-45a6-83e6-bc066f5c3453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259610984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.1259610984
Directory /workspace/37.uart_rx_parity_err/latest

Test location /workspace/coverage/default/37.uart_rx_start_bit_filter.29564477
Short name T343
Test name
Test status
Simulation time 713195044 ps
CPU time 0.85 seconds
Started Jun 09 02:17:51 PM PDT 24
Finished Jun 09 02:17:52 PM PDT 24
Peak memory 195768 kb
Host smart-17908bd9-cd09-4ab5-86cc-4ae77c8659c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29564477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.29564477
Directory /workspace/37.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/37.uart_smoke.1807135129
Short name T729
Test name
Test status
Simulation time 581301515 ps
CPU time 1.75 seconds
Started Jun 09 02:17:57 PM PDT 24
Finished Jun 09 02:17:59 PM PDT 24
Peak memory 199996 kb
Host smart-f0fcafaa-7346-422b-b826-58c20fa2f262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807135129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_smoke.1807135129
Directory /workspace/37.uart_smoke/latest

Test location /workspace/coverage/default/37.uart_stress_all.3558521146
Short name T161
Test name
Test status
Simulation time 118036886165 ps
CPU time 329.7 seconds
Started Jun 09 02:18:01 PM PDT 24
Finished Jun 09 02:23:31 PM PDT 24
Peak memory 200340 kb
Host smart-8c6baa26-a305-4718-83d2-ac270efbf2bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558521146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.3558521146
Directory /workspace/37.uart_stress_all/latest

Test location /workspace/coverage/default/37.uart_tx_ovrd.3007011552
Short name T655
Test name
Test status
Simulation time 1001441645 ps
CPU time 3.02 seconds
Started Jun 09 02:17:55 PM PDT 24
Finished Jun 09 02:17:58 PM PDT 24
Peak memory 200080 kb
Host smart-8512ea1d-d7e7-4941-978f-6c289724bda6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007011552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.3007011552
Directory /workspace/37.uart_tx_ovrd/latest

Test location /workspace/coverage/default/37.uart_tx_rx.3401120943
Short name T1020
Test name
Test status
Simulation time 65228826195 ps
CPU time 75.63 seconds
Started Jun 09 02:17:50 PM PDT 24
Finished Jun 09 02:19:06 PM PDT 24
Peak memory 200328 kb
Host smart-33fb4f41-d6f5-4c56-b77f-d65452eacd89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401120943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.3401120943
Directory /workspace/37.uart_tx_rx/latest

Test location /workspace/coverage/default/38.uart_alert_test.3840971322
Short name T617
Test name
Test status
Simulation time 20432962 ps
CPU time 0.56 seconds
Started Jun 09 02:18:01 PM PDT 24
Finished Jun 09 02:18:02 PM PDT 24
Peak memory 196024 kb
Host smart-87085231-ae6f-4f65-8b67-69e98bcfa94b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840971322 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.3840971322
Directory /workspace/38.uart_alert_test/latest

Test location /workspace/coverage/default/38.uart_fifo_full.282683306
Short name T160
Test name
Test status
Simulation time 66462503346 ps
CPU time 27.28 seconds
Started Jun 09 02:17:55 PM PDT 24
Finished Jun 09 02:18:23 PM PDT 24
Peak memory 200364 kb
Host smart-9c3c5bc6-fd07-4059-bb24-52b2b8dbf363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282683306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.282683306
Directory /workspace/38.uart_fifo_full/latest

Test location /workspace/coverage/default/38.uart_fifo_overflow.308215619
Short name T448
Test name
Test status
Simulation time 122881797017 ps
CPU time 211.48 seconds
Started Jun 09 02:17:56 PM PDT 24
Finished Jun 09 02:21:28 PM PDT 24
Peak memory 200376 kb
Host smart-30baa4f0-706b-47cb-8328-d7e4f1e35cb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308215619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.308215619
Directory /workspace/38.uart_fifo_overflow/latest

Test location /workspace/coverage/default/38.uart_intr.1909642863
Short name T737
Test name
Test status
Simulation time 48545739212 ps
CPU time 29.18 seconds
Started Jun 09 02:18:00 PM PDT 24
Finished Jun 09 02:18:29 PM PDT 24
Peak memory 200332 kb
Host smart-a6fd3f41-c1e6-4ce6-a673-ba5e02932b90
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909642863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.1909642863
Directory /workspace/38.uart_intr/latest

Test location /workspace/coverage/default/38.uart_long_xfer_wo_dly.694414926
Short name T506
Test name
Test status
Simulation time 229627163484 ps
CPU time 599.41 seconds
Started Jun 09 02:18:00 PM PDT 24
Finished Jun 09 02:27:59 PM PDT 24
Peak memory 200356 kb
Host smart-e21a125e-1574-4a12-8ada-a66e543b692a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=694414926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.694414926
Directory /workspace/38.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/38.uart_loopback.107096338
Short name T1069
Test name
Test status
Simulation time 11049278809 ps
CPU time 21.36 seconds
Started Jun 09 02:18:03 PM PDT 24
Finished Jun 09 02:18:24 PM PDT 24
Peak memory 199388 kb
Host smart-37cddfe1-5f6a-4cf1-8219-94c9e1ee8103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107096338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_loopback.107096338
Directory /workspace/38.uart_loopback/latest

Test location /workspace/coverage/default/38.uart_perf.1524605102
Short name T446
Test name
Test status
Simulation time 19985282644 ps
CPU time 930.47 seconds
Started Jun 09 02:18:01 PM PDT 24
Finished Jun 09 02:33:32 PM PDT 24
Peak memory 200300 kb
Host smart-78998642-c14c-4893-8692-14e9bfc657cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1524605102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.1524605102
Directory /workspace/38.uart_perf/latest

Test location /workspace/coverage/default/38.uart_rx_oversample.934298971
Short name T666
Test name
Test status
Simulation time 6886755296 ps
CPU time 15.11 seconds
Started Jun 09 02:18:01 PM PDT 24
Finished Jun 09 02:18:16 PM PDT 24
Peak memory 199768 kb
Host smart-3319a208-91e4-489b-804e-92128019bd65
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=934298971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.934298971
Directory /workspace/38.uart_rx_oversample/latest

Test location /workspace/coverage/default/38.uart_rx_parity_err.2379901171
Short name T181
Test name
Test status
Simulation time 58416452981 ps
CPU time 19.58 seconds
Started Jun 09 02:18:02 PM PDT 24
Finished Jun 09 02:18:22 PM PDT 24
Peak memory 200376 kb
Host smart-17dfafe6-f1ec-4865-8c42-088d0af006c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379901171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.2379901171
Directory /workspace/38.uart_rx_parity_err/latest

Test location /workspace/coverage/default/38.uart_rx_start_bit_filter.3508735475
Short name T915
Test name
Test status
Simulation time 3926472833 ps
CPU time 1.73 seconds
Started Jun 09 02:18:00 PM PDT 24
Finished Jun 09 02:18:02 PM PDT 24
Peak memory 196400 kb
Host smart-68f7b368-bd76-436f-8545-f1c66f4fa844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508735475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.3508735475
Directory /workspace/38.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/38.uart_smoke.1539063932
Short name T441
Test name
Test status
Simulation time 5469952930 ps
CPU time 20.11 seconds
Started Jun 09 02:17:55 PM PDT 24
Finished Jun 09 02:18:16 PM PDT 24
Peak memory 200108 kb
Host smart-c58169b7-93f8-4254-a138-0751bbaa665b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539063932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_smoke.1539063932
Directory /workspace/38.uart_smoke/latest

Test location /workspace/coverage/default/38.uart_stress_all_with_rand_reset.3045507837
Short name T68
Test name
Test status
Simulation time 380732033721 ps
CPU time 1141.66 seconds
Started Jun 09 02:18:01 PM PDT 24
Finished Jun 09 02:37:03 PM PDT 24
Peak memory 225220 kb
Host smart-bafd925c-0cde-44e8-8b2c-99e931e5d1cd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045507837 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 38.uart_stress_all_with_rand_reset.3045507837
Directory /workspace/38.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.uart_tx_ovrd.3157951649
Short name T2
Test name
Test status
Simulation time 8155849077 ps
CPU time 15.25 seconds
Started Jun 09 02:18:02 PM PDT 24
Finished Jun 09 02:18:17 PM PDT 24
Peak memory 200408 kb
Host smart-96df8c0c-2e32-4594-a741-e037da08f0f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157951649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.3157951649
Directory /workspace/38.uart_tx_ovrd/latest

Test location /workspace/coverage/default/38.uart_tx_rx.1518929142
Short name T889
Test name
Test status
Simulation time 102883986149 ps
CPU time 186.44 seconds
Started Jun 09 02:17:55 PM PDT 24
Finished Jun 09 02:21:02 PM PDT 24
Peak memory 200396 kb
Host smart-a04385a8-8bf9-4e50-8df0-e8be0858b103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518929142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.1518929142
Directory /workspace/38.uart_tx_rx/latest

Test location /workspace/coverage/default/39.uart_alert_test.282094119
Short name T572
Test name
Test status
Simulation time 33554734 ps
CPU time 0.58 seconds
Started Jun 09 02:18:10 PM PDT 24
Finished Jun 09 02:18:11 PM PDT 24
Peak memory 195756 kb
Host smart-b4d0579b-65d1-445b-b192-1c063a5ab222
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282094119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.282094119
Directory /workspace/39.uart_alert_test/latest

Test location /workspace/coverage/default/39.uart_fifo_overflow.3006201513
Short name T777
Test name
Test status
Simulation time 97453828785 ps
CPU time 79.72 seconds
Started Jun 09 02:18:06 PM PDT 24
Finished Jun 09 02:19:26 PM PDT 24
Peak memory 200320 kb
Host smart-75f43495-b69d-4f78-baee-868b06ec5910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006201513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.3006201513
Directory /workspace/39.uart_fifo_overflow/latest

Test location /workspace/coverage/default/39.uart_fifo_reset.2286257901
Short name T773
Test name
Test status
Simulation time 15503836430 ps
CPU time 25.82 seconds
Started Jun 09 02:18:05 PM PDT 24
Finished Jun 09 02:18:32 PM PDT 24
Peak memory 200144 kb
Host smart-812fd80b-55cd-4d07-b1ad-65f7406b4352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286257901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.2286257901
Directory /workspace/39.uart_fifo_reset/latest

Test location /workspace/coverage/default/39.uart_intr.1716358492
Short name T778
Test name
Test status
Simulation time 7001404329 ps
CPU time 8.5 seconds
Started Jun 09 02:18:08 PM PDT 24
Finished Jun 09 02:18:17 PM PDT 24
Peak memory 200000 kb
Host smart-8ee4712b-94af-464c-a8ac-86e2226971f3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716358492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.1716358492
Directory /workspace/39.uart_intr/latest

Test location /workspace/coverage/default/39.uart_long_xfer_wo_dly.590786979
Short name T354
Test name
Test status
Simulation time 37650129134 ps
CPU time 346.01 seconds
Started Jun 09 02:18:08 PM PDT 24
Finished Jun 09 02:23:54 PM PDT 24
Peak memory 199712 kb
Host smart-7d842049-a61b-4ea0-a831-4654b0d1657a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=590786979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.590786979
Directory /workspace/39.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/39.uart_loopback.1406129474
Short name T726
Test name
Test status
Simulation time 2187678568 ps
CPU time 2.56 seconds
Started Jun 09 02:18:05 PM PDT 24
Finished Jun 09 02:18:08 PM PDT 24
Peak memory 195756 kb
Host smart-abd12c60-0b3f-4caa-8a2c-cac0f8ca6eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406129474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_loopback.1406129474
Directory /workspace/39.uart_loopback/latest

Test location /workspace/coverage/default/39.uart_perf.784956645
Short name T950
Test name
Test status
Simulation time 13360163180 ps
CPU time 183.57 seconds
Started Jun 09 02:18:05 PM PDT 24
Finished Jun 09 02:21:09 PM PDT 24
Peak memory 200324 kb
Host smart-9c9ea762-4fb4-461b-9a9d-9729f6371b6e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=784956645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.784956645
Directory /workspace/39.uart_perf/latest

Test location /workspace/coverage/default/39.uart_rx_oversample.3647665864
Short name T639
Test name
Test status
Simulation time 5047845025 ps
CPU time 8.36 seconds
Started Jun 09 02:18:06 PM PDT 24
Finished Jun 09 02:18:15 PM PDT 24
Peak memory 198524 kb
Host smart-62edea27-f086-4854-8fed-646d5603fa6b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3647665864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.3647665864
Directory /workspace/39.uart_rx_oversample/latest

Test location /workspace/coverage/default/39.uart_rx_parity_err.265324
Short name T281
Test name
Test status
Simulation time 229568171022 ps
CPU time 125.99 seconds
Started Jun 09 02:18:04 PM PDT 24
Finished Jun 09 02:20:11 PM PDT 24
Peak memory 200376 kb
Host smart-b6bdd79d-43c0-4352-a6ea-7faf6c56dd70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.265324
Directory /workspace/39.uart_rx_parity_err/latest

Test location /workspace/coverage/default/39.uart_rx_start_bit_filter.2944189983
Short name T587
Test name
Test status
Simulation time 36753897308 ps
CPU time 14.64 seconds
Started Jun 09 02:18:04 PM PDT 24
Finished Jun 09 02:18:19 PM PDT 24
Peak memory 196648 kb
Host smart-904b2b0f-e0db-4d4c-b869-98a16919d36b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944189983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.2944189983
Directory /workspace/39.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/39.uart_smoke.3417046328
Short name T485
Test name
Test status
Simulation time 530216300 ps
CPU time 1.32 seconds
Started Jun 09 02:18:05 PM PDT 24
Finished Jun 09 02:18:06 PM PDT 24
Peak memory 199052 kb
Host smart-c156fc44-2425-40b4-886f-9883af162792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417046328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_smoke.3417046328
Directory /workspace/39.uart_smoke/latest

Test location /workspace/coverage/default/39.uart_stress_all.1743371616
Short name T394
Test name
Test status
Simulation time 87543044156 ps
CPU time 135.34 seconds
Started Jun 09 02:18:05 PM PDT 24
Finished Jun 09 02:20:21 PM PDT 24
Peak memory 200416 kb
Host smart-dbf2bfef-8299-4d7e-9e74-9ad3ce386c36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743371616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.1743371616
Directory /workspace/39.uart_stress_all/latest

Test location /workspace/coverage/default/39.uart_tx_ovrd.1886026083
Short name T923
Test name
Test status
Simulation time 1669507019 ps
CPU time 2.79 seconds
Started Jun 09 02:18:07 PM PDT 24
Finished Jun 09 02:18:10 PM PDT 24
Peak memory 198788 kb
Host smart-3c13ac23-9392-49fd-8fa6-202d8f8a6011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886026083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.1886026083
Directory /workspace/39.uart_tx_ovrd/latest

Test location /workspace/coverage/default/39.uart_tx_rx.1037058571
Short name T3
Test name
Test status
Simulation time 45411489235 ps
CPU time 23.3 seconds
Started Jun 09 02:18:08 PM PDT 24
Finished Jun 09 02:18:31 PM PDT 24
Peak memory 200388 kb
Host smart-171edc91-a676-4ce0-a0d6-4a6c27a8eb2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037058571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.1037058571
Directory /workspace/39.uart_tx_rx/latest

Test location /workspace/coverage/default/4.uart_alert_test.4233646720
Short name T369
Test name
Test status
Simulation time 39690886 ps
CPU time 0.56 seconds
Started Jun 09 02:13:40 PM PDT 24
Finished Jun 09 02:13:41 PM PDT 24
Peak memory 195756 kb
Host smart-58bd5aac-344c-4f54-a4dc-e2b14eb84761
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233646720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.4233646720
Directory /workspace/4.uart_alert_test/latest

Test location /workspace/coverage/default/4.uart_fifo_full.1489912548
Short name T871
Test name
Test status
Simulation time 136127064601 ps
CPU time 22.95 seconds
Started Jun 09 02:13:26 PM PDT 24
Finished Jun 09 02:13:49 PM PDT 24
Peak memory 200348 kb
Host smart-31c54ce8-ef43-4171-8942-0f66a8aaec8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489912548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.1489912548
Directory /workspace/4.uart_fifo_full/latest

Test location /workspace/coverage/default/4.uart_fifo_overflow.3001460672
Short name T470
Test name
Test status
Simulation time 8852801337 ps
CPU time 14.64 seconds
Started Jun 09 02:13:28 PM PDT 24
Finished Jun 09 02:13:42 PM PDT 24
Peak memory 198800 kb
Host smart-f1594e62-7dbe-494f-8ead-7732a5f9d5eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001460672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.3001460672
Directory /workspace/4.uart_fifo_overflow/latest

Test location /workspace/coverage/default/4.uart_fifo_reset.382316396
Short name T892
Test name
Test status
Simulation time 44523840220 ps
CPU time 9.23 seconds
Started Jun 09 02:13:31 PM PDT 24
Finished Jun 09 02:13:41 PM PDT 24
Peak memory 200328 kb
Host smart-97ba1c36-4ec0-4204-977d-61ffcf4016d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382316396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.382316396
Directory /workspace/4.uart_fifo_reset/latest

Test location /workspace/coverage/default/4.uart_intr.2889902640
Short name T374
Test name
Test status
Simulation time 61140940081 ps
CPU time 47.49 seconds
Started Jun 09 02:13:29 PM PDT 24
Finished Jun 09 02:14:16 PM PDT 24
Peak memory 200412 kb
Host smart-1a89debc-8991-45be-ad2b-806df598a6d0
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889902640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.2889902640
Directory /workspace/4.uart_intr/latest

Test location /workspace/coverage/default/4.uart_long_xfer_wo_dly.3289024535
Short name T41
Test name
Test status
Simulation time 163273223863 ps
CPU time 610.22 seconds
Started Jun 09 02:13:34 PM PDT 24
Finished Jun 09 02:23:45 PM PDT 24
Peak memory 200404 kb
Host smart-351ec9f4-3a4f-4c44-9fea-00021e9c3ff4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3289024535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.3289024535
Directory /workspace/4.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/4.uart_loopback.2106787835
Short name T459
Test name
Test status
Simulation time 3771428308 ps
CPU time 2.81 seconds
Started Jun 09 02:13:35 PM PDT 24
Finished Jun 09 02:13:38 PM PDT 24
Peak memory 196808 kb
Host smart-5f86bacc-65a2-45ac-ba39-0dd4831c9623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106787835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_loopback.2106787835
Directory /workspace/4.uart_loopback/latest

Test location /workspace/coverage/default/4.uart_perf.23828053
Short name T586
Test name
Test status
Simulation time 7539292958 ps
CPU time 112.1 seconds
Started Jun 09 02:13:36 PM PDT 24
Finished Jun 09 02:15:29 PM PDT 24
Peak memory 200384 kb
Host smart-4a9a50ec-44be-4673-acf3-694f890d7a56
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=23828053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.23828053
Directory /workspace/4.uart_perf/latest

Test location /workspace/coverage/default/4.uart_rx_oversample.651206716
Short name T1083
Test name
Test status
Simulation time 1802267853 ps
CPU time 6.5 seconds
Started Jun 09 02:13:30 PM PDT 24
Finished Jun 09 02:13:36 PM PDT 24
Peak memory 198508 kb
Host smart-bba7eded-8dc6-47d2-af78-fe988c8b48b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=651206716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.651206716
Directory /workspace/4.uart_rx_oversample/latest

Test location /workspace/coverage/default/4.uart_rx_parity_err.2247853915
Short name T876
Test name
Test status
Simulation time 144363536436 ps
CPU time 69.52 seconds
Started Jun 09 02:13:29 PM PDT 24
Finished Jun 09 02:14:39 PM PDT 24
Peak memory 200388 kb
Host smart-7a8df28a-b649-4b40-81ac-a0e064a32346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247853915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.2247853915
Directory /workspace/4.uart_rx_parity_err/latest

Test location /workspace/coverage/default/4.uart_rx_start_bit_filter.2367736571
Short name T578
Test name
Test status
Simulation time 1660888941 ps
CPU time 1.35 seconds
Started Jun 09 02:13:30 PM PDT 24
Finished Jun 09 02:13:31 PM PDT 24
Peak memory 195960 kb
Host smart-4882431a-778c-42dd-a0a4-e67045f09e8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367736571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.2367736571
Directory /workspace/4.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/4.uart_sec_cm.2036842668
Short name T99
Test name
Test status
Simulation time 123187362 ps
CPU time 0.75 seconds
Started Jun 09 02:13:36 PM PDT 24
Finished Jun 09 02:13:37 PM PDT 24
Peak memory 218720 kb
Host smart-78d55c70-70f8-47a4-9dd5-7e439c77c09e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036842668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.2036842668
Directory /workspace/4.uart_sec_cm/latest

Test location /workspace/coverage/default/4.uart_smoke.3075775001
Short name T449
Test name
Test status
Simulation time 5681441583 ps
CPU time 19.56 seconds
Started Jun 09 02:13:25 PM PDT 24
Finished Jun 09 02:13:45 PM PDT 24
Peak memory 200096 kb
Host smart-1c61062e-e531-4e0e-8c84-28c803a812e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075775001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_smoke.3075775001
Directory /workspace/4.uart_smoke/latest

Test location /workspace/coverage/default/4.uart_stress_all_with_rand_reset.1283856331
Short name T793
Test name
Test status
Simulation time 121828704973 ps
CPU time 685.77 seconds
Started Jun 09 02:13:35 PM PDT 24
Finished Jun 09 02:25:01 PM PDT 24
Peak memory 216904 kb
Host smart-7893a6ba-df2e-45fd-94c0-7d27eaaa6610
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283856331 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.uart_stress_all_with_rand_reset.1283856331
Directory /workspace/4.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.uart_tx_ovrd.2322526271
Short name T379
Test name
Test status
Simulation time 772860254 ps
CPU time 2.59 seconds
Started Jun 09 02:13:34 PM PDT 24
Finished Jun 09 02:13:37 PM PDT 24
Peak memory 200252 kb
Host smart-01cc7fdc-1155-466b-ba3a-06d14d510875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322526271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.2322526271
Directory /workspace/4.uart_tx_ovrd/latest

Test location /workspace/coverage/default/4.uart_tx_rx.2063499125
Short name T275
Test name
Test status
Simulation time 46892830331 ps
CPU time 103.27 seconds
Started Jun 09 02:13:27 PM PDT 24
Finished Jun 09 02:15:11 PM PDT 24
Peak memory 200364 kb
Host smart-52b161f1-666d-46b8-9824-0d6c47dfec75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063499125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.2063499125
Directory /workspace/4.uart_tx_rx/latest

Test location /workspace/coverage/default/40.uart_alert_test.172943409
Short name T371
Test name
Test status
Simulation time 47478046 ps
CPU time 0.56 seconds
Started Jun 09 02:18:15 PM PDT 24
Finished Jun 09 02:18:16 PM PDT 24
Peak memory 195776 kb
Host smart-a86423f7-a3bf-416a-854f-c292c0de12a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172943409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.172943409
Directory /workspace/40.uart_alert_test/latest

Test location /workspace/coverage/default/40.uart_fifo_overflow.3896504070
Short name T932
Test name
Test status
Simulation time 125691328866 ps
CPU time 141.22 seconds
Started Jun 09 02:18:10 PM PDT 24
Finished Jun 09 02:20:32 PM PDT 24
Peak memory 200512 kb
Host smart-46c2296b-7cb8-465e-992b-549fceb5569b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896504070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.3896504070
Directory /workspace/40.uart_fifo_overflow/latest

Test location /workspace/coverage/default/40.uart_fifo_reset.2672374702
Short name T672
Test name
Test status
Simulation time 12300381545 ps
CPU time 29.6 seconds
Started Jun 09 02:18:11 PM PDT 24
Finished Jun 09 02:18:41 PM PDT 24
Peak memory 200332 kb
Host smart-32c9d5cb-e438-4010-8e53-d54ba345aa8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672374702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.2672374702
Directory /workspace/40.uart_fifo_reset/latest

Test location /workspace/coverage/default/40.uart_intr.2944872292
Short name T860
Test name
Test status
Simulation time 28165120340 ps
CPU time 14.25 seconds
Started Jun 09 02:18:12 PM PDT 24
Finished Jun 09 02:18:26 PM PDT 24
Peak memory 200296 kb
Host smart-846fdc57-39f0-4192-8523-a64e7c39199d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944872292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.2944872292
Directory /workspace/40.uart_intr/latest

Test location /workspace/coverage/default/40.uart_long_xfer_wo_dly.306238651
Short name T55
Test name
Test status
Simulation time 65549785677 ps
CPU time 315.61 seconds
Started Jun 09 02:18:15 PM PDT 24
Finished Jun 09 02:23:31 PM PDT 24
Peak memory 200336 kb
Host smart-3bcd6790-86a0-4643-9ef1-691c4379128c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=306238651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.306238651
Directory /workspace/40.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/40.uart_loopback.874427753
Short name T652
Test name
Test status
Simulation time 6745453749 ps
CPU time 5.79 seconds
Started Jun 09 02:18:18 PM PDT 24
Finished Jun 09 02:18:24 PM PDT 24
Peak memory 198804 kb
Host smart-1b898eff-09da-4fc3-a17d-cd019b2120ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874427753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_loopback.874427753
Directory /workspace/40.uart_loopback/latest

Test location /workspace/coverage/default/40.uart_perf.1678224662
Short name T1055
Test name
Test status
Simulation time 11443801730 ps
CPU time 102.59 seconds
Started Jun 09 02:18:17 PM PDT 24
Finished Jun 09 02:20:00 PM PDT 24
Peak memory 200300 kb
Host smart-8a7fec6d-708f-4554-9ec5-cb107f7667e4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1678224662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.1678224662
Directory /workspace/40.uart_perf/latest

Test location /workspace/coverage/default/40.uart_rx_oversample.1350485332
Short name T345
Test name
Test status
Simulation time 5478613179 ps
CPU time 53.73 seconds
Started Jun 09 02:18:10 PM PDT 24
Finished Jun 09 02:19:04 PM PDT 24
Peak memory 199652 kb
Host smart-c889cbf8-a309-488d-90ab-73658b7e55d8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1350485332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.1350485332
Directory /workspace/40.uart_rx_oversample/latest

Test location /workspace/coverage/default/40.uart_rx_parity_err.2464056166
Short name T157
Test name
Test status
Simulation time 20794339574 ps
CPU time 9.97 seconds
Started Jun 09 02:18:17 PM PDT 24
Finished Jun 09 02:18:28 PM PDT 24
Peak memory 200104 kb
Host smart-ca61747c-b3b1-46ed-a43c-9121da8abd63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464056166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.2464056166
Directory /workspace/40.uart_rx_parity_err/latest

Test location /workspace/coverage/default/40.uart_rx_start_bit_filter.463456318
Short name T820
Test name
Test status
Simulation time 4530985617 ps
CPU time 4.17 seconds
Started Jun 09 02:18:16 PM PDT 24
Finished Jun 09 02:18:20 PM PDT 24
Peak memory 197204 kb
Host smart-5ba7e199-b268-4691-9553-63a0a6d25954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463456318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.463456318
Directory /workspace/40.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/40.uart_smoke.3428786091
Short name T516
Test name
Test status
Simulation time 459050882 ps
CPU time 2.55 seconds
Started Jun 09 02:18:08 PM PDT 24
Finished Jun 09 02:18:11 PM PDT 24
Peak memory 199524 kb
Host smart-4dfa890b-d75c-44a6-8153-1935c13bc18a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428786091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_smoke.3428786091
Directory /workspace/40.uart_smoke/latest

Test location /workspace/coverage/default/40.uart_stress_all.3686855483
Short name T678
Test name
Test status
Simulation time 135837343009 ps
CPU time 119.87 seconds
Started Jun 09 02:18:18 PM PDT 24
Finished Jun 09 02:20:19 PM PDT 24
Peak memory 200444 kb
Host smart-7856ce5a-2128-4d18-b5aa-bc71e6eb2214
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686855483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.3686855483
Directory /workspace/40.uart_stress_all/latest

Test location /workspace/coverage/default/40.uart_tx_ovrd.3144784093
Short name T295
Test name
Test status
Simulation time 1665746636 ps
CPU time 1.17 seconds
Started Jun 09 02:18:17 PM PDT 24
Finished Jun 09 02:18:19 PM PDT 24
Peak memory 199036 kb
Host smart-17c70e5f-ce17-44ba-8efe-2fccb72c0519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144784093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.3144784093
Directory /workspace/40.uart_tx_ovrd/latest

Test location /workspace/coverage/default/40.uart_tx_rx.717341731
Short name T783
Test name
Test status
Simulation time 76729128803 ps
CPU time 161.02 seconds
Started Jun 09 02:18:03 PM PDT 24
Finished Jun 09 02:20:44 PM PDT 24
Peak memory 200376 kb
Host smart-711e8226-27d6-422f-8183-dcd069439573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717341731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.717341731
Directory /workspace/40.uart_tx_rx/latest

Test location /workspace/coverage/default/41.uart_alert_test.737354967
Short name T357
Test name
Test status
Simulation time 20979815 ps
CPU time 0.56 seconds
Started Jun 09 02:18:23 PM PDT 24
Finished Jun 09 02:18:24 PM PDT 24
Peak memory 194664 kb
Host smart-001bb683-76fb-45ed-8ef3-2b3ef5fa36eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737354967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.737354967
Directory /workspace/41.uart_alert_test/latest

Test location /workspace/coverage/default/41.uart_fifo_full.188157902
Short name T970
Test name
Test status
Simulation time 100369316566 ps
CPU time 78.25 seconds
Started Jun 09 02:18:14 PM PDT 24
Finished Jun 09 02:19:33 PM PDT 24
Peak memory 200324 kb
Host smart-c3489a5c-1ab5-4f70-98d9-f901f1855b94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188157902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.188157902
Directory /workspace/41.uart_fifo_full/latest

Test location /workspace/coverage/default/41.uart_fifo_overflow.3434452131
Short name T37
Test name
Test status
Simulation time 71362628590 ps
CPU time 63.61 seconds
Started Jun 09 02:18:16 PM PDT 24
Finished Jun 09 02:19:20 PM PDT 24
Peak memory 200324 kb
Host smart-18063b27-cd55-4f47-9cec-27481553f63b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434452131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.3434452131
Directory /workspace/41.uart_fifo_overflow/latest

Test location /workspace/coverage/default/41.uart_fifo_reset.3612318810
Short name T882
Test name
Test status
Simulation time 11499601492 ps
CPU time 21.33 seconds
Started Jun 09 02:18:15 PM PDT 24
Finished Jun 09 02:18:36 PM PDT 24
Peak memory 200328 kb
Host smart-d2450e83-b34f-4428-923a-e716c534140d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612318810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.3612318810
Directory /workspace/41.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_intr.2796131192
Short name T962
Test name
Test status
Simulation time 69838620233 ps
CPU time 134.55 seconds
Started Jun 09 02:18:15 PM PDT 24
Finished Jun 09 02:20:30 PM PDT 24
Peak memory 200392 kb
Host smart-8f45160a-79cb-4f35-84ce-1f299c0669ab
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796131192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.2796131192
Directory /workspace/41.uart_intr/latest

Test location /workspace/coverage/default/41.uart_long_xfer_wo_dly.1520181198
Short name T498
Test name
Test status
Simulation time 164165500063 ps
CPU time 303.33 seconds
Started Jun 09 02:18:22 PM PDT 24
Finished Jun 09 02:23:26 PM PDT 24
Peak memory 200380 kb
Host smart-9517987c-c22e-498e-95ea-2e443c0d4791
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1520181198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.1520181198
Directory /workspace/41.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/41.uart_loopback.1128032208
Short name T538
Test name
Test status
Simulation time 8616484743 ps
CPU time 21.76 seconds
Started Jun 09 02:18:21 PM PDT 24
Finished Jun 09 02:18:43 PM PDT 24
Peak memory 200552 kb
Host smart-17a5ba03-22bb-48bf-8380-fb5247f78406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128032208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_loopback.1128032208
Directory /workspace/41.uart_loopback/latest

Test location /workspace/coverage/default/41.uart_perf.2214504752
Short name T990
Test name
Test status
Simulation time 15811203167 ps
CPU time 305.97 seconds
Started Jun 09 02:18:19 PM PDT 24
Finished Jun 09 02:23:25 PM PDT 24
Peak memory 200312 kb
Host smart-ecc1d26d-47e8-4994-a021-4ac864512de1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2214504752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.2214504752
Directory /workspace/41.uart_perf/latest

Test location /workspace/coverage/default/41.uart_rx_oversample.4267709467
Short name T352
Test name
Test status
Simulation time 4130986926 ps
CPU time 36.23 seconds
Started Jun 09 02:18:16 PM PDT 24
Finished Jun 09 02:18:53 PM PDT 24
Peak memory 198808 kb
Host smart-07227d66-430d-4448-8783-59b6a7af68cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4267709467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.4267709467
Directory /workspace/41.uart_rx_oversample/latest

Test location /workspace/coverage/default/41.uart_rx_parity_err.4108632336
Short name T626
Test name
Test status
Simulation time 144654492130 ps
CPU time 44.24 seconds
Started Jun 09 02:18:22 PM PDT 24
Finished Jun 09 02:19:07 PM PDT 24
Peak memory 200272 kb
Host smart-8280dcc1-f13a-4e1a-b620-074808b2f3e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108632336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.4108632336
Directory /workspace/41.uart_rx_parity_err/latest

Test location /workspace/coverage/default/41.uart_rx_start_bit_filter.1285380631
Short name T414
Test name
Test status
Simulation time 4830337294 ps
CPU time 8.15 seconds
Started Jun 09 02:18:16 PM PDT 24
Finished Jun 09 02:18:25 PM PDT 24
Peak memory 196456 kb
Host smart-55e96f46-94f0-48dd-8053-0c221a3f888d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285380631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.1285380631
Directory /workspace/41.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/41.uart_smoke.1424401100
Short name T1054
Test name
Test status
Simulation time 488739257 ps
CPU time 1.25 seconds
Started Jun 09 02:18:15 PM PDT 24
Finished Jun 09 02:18:17 PM PDT 24
Peak memory 199348 kb
Host smart-12b113c7-44fa-4b48-af5c-271d3f2a280d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424401100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_smoke.1424401100
Directory /workspace/41.uart_smoke/latest

Test location /workspace/coverage/default/41.uart_stress_all.1976297927
Short name T1058
Test name
Test status
Simulation time 445425904596 ps
CPU time 106.58 seconds
Started Jun 09 02:18:21 PM PDT 24
Finished Jun 09 02:20:08 PM PDT 24
Peak memory 200348 kb
Host smart-daea09e7-f02d-4b7d-9470-db0dfd19c69a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976297927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.1976297927
Directory /workspace/41.uart_stress_all/latest

Test location /workspace/coverage/default/41.uart_stress_all_with_rand_reset.1002979555
Short name T328
Test name
Test status
Simulation time 53287285134 ps
CPU time 219.85 seconds
Started Jun 09 02:18:22 PM PDT 24
Finished Jun 09 02:22:02 PM PDT 24
Peak memory 216972 kb
Host smart-7d4ef363-5a81-4088-b3eb-92ba2fd5142f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002979555 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 41.uart_stress_all_with_rand_reset.1002979555
Directory /workspace/41.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.uart_tx_ovrd.3134996368
Short name T522
Test name
Test status
Simulation time 13141516614 ps
CPU time 21.09 seconds
Started Jun 09 02:18:23 PM PDT 24
Finished Jun 09 02:18:44 PM PDT 24
Peak memory 200360 kb
Host smart-ffc12dfd-e11c-4274-941a-bd44ccb263a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134996368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.3134996368
Directory /workspace/41.uart_tx_ovrd/latest

Test location /workspace/coverage/default/41.uart_tx_rx.3573882832
Short name T792
Test name
Test status
Simulation time 103146841182 ps
CPU time 231.24 seconds
Started Jun 09 02:18:17 PM PDT 24
Finished Jun 09 02:22:09 PM PDT 24
Peak memory 200388 kb
Host smart-909c6fec-b8e4-4f83-b721-b9d6fcd0936b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573882832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.3573882832
Directory /workspace/41.uart_tx_rx/latest

Test location /workspace/coverage/default/42.uart_alert_test.1326538430
Short name T395
Test name
Test status
Simulation time 63900699 ps
CPU time 0.57 seconds
Started Jun 09 02:18:25 PM PDT 24
Finished Jun 09 02:18:26 PM PDT 24
Peak memory 195760 kb
Host smart-3b88bc8f-c3f0-467b-801f-6f5f1171933f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326538430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.1326538430
Directory /workspace/42.uart_alert_test/latest

Test location /workspace/coverage/default/42.uart_fifo_full.2484435897
Short name T1046
Test name
Test status
Simulation time 35403321127 ps
CPU time 64.03 seconds
Started Jun 09 02:18:22 PM PDT 24
Finished Jun 09 02:19:27 PM PDT 24
Peak memory 200368 kb
Host smart-fa651b4e-3e23-4716-ac6d-f281de842616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484435897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.2484435897
Directory /workspace/42.uart_fifo_full/latest

Test location /workspace/coverage/default/42.uart_fifo_overflow.999388359
Short name T996
Test name
Test status
Simulation time 21068713353 ps
CPU time 32.23 seconds
Started Jun 09 02:18:22 PM PDT 24
Finished Jun 09 02:18:54 PM PDT 24
Peak memory 200312 kb
Host smart-ad8f0c0f-764f-4df1-a0fd-c26b16480461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999388359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.999388359
Directory /workspace/42.uart_fifo_overflow/latest

Test location /workspace/coverage/default/42.uart_fifo_reset.3299408707
Short name T218
Test name
Test status
Simulation time 97966886792 ps
CPU time 76.19 seconds
Started Jun 09 02:18:23 PM PDT 24
Finished Jun 09 02:19:39 PM PDT 24
Peak memory 200356 kb
Host smart-ce979e73-3d06-4c8f-ac15-8133c6b9e946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299408707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.3299408707
Directory /workspace/42.uart_fifo_reset/latest

Test location /workspace/coverage/default/42.uart_intr.1713520040
Short name T88
Test name
Test status
Simulation time 51366907486 ps
CPU time 149.45 seconds
Started Jun 09 02:18:26 PM PDT 24
Finished Jun 09 02:20:55 PM PDT 24
Peak memory 200416 kb
Host smart-ce157c3c-771d-47be-937e-7115d87d0261
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713520040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.1713520040
Directory /workspace/42.uart_intr/latest

Test location /workspace/coverage/default/42.uart_long_xfer_wo_dly.4117435263
Short name T1060
Test name
Test status
Simulation time 74534701349 ps
CPU time 148.35 seconds
Started Jun 09 02:18:25 PM PDT 24
Finished Jun 09 02:20:54 PM PDT 24
Peak memory 200340 kb
Host smart-237a1eee-f502-4213-baf6-d666cbd2b77c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4117435263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.4117435263
Directory /workspace/42.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/42.uart_loopback.509873982
Short name T363
Test name
Test status
Simulation time 266275928 ps
CPU time 1.09 seconds
Started Jun 09 02:18:25 PM PDT 24
Finished Jun 09 02:18:26 PM PDT 24
Peak memory 196428 kb
Host smart-8cfd6f85-8f0c-48a9-a333-1fda62c5b84c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509873982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_loopback.509873982
Directory /workspace/42.uart_loopback/latest

Test location /workspace/coverage/default/42.uart_perf.988388546
Short name T628
Test name
Test status
Simulation time 22976045034 ps
CPU time 131.3 seconds
Started Jun 09 02:18:24 PM PDT 24
Finished Jun 09 02:20:35 PM PDT 24
Peak memory 200388 kb
Host smart-6cb327da-b82d-4889-83c0-2a71165ac61f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=988388546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.988388546
Directory /workspace/42.uart_perf/latest

Test location /workspace/coverage/default/42.uart_rx_oversample.3893730923
Short name T509
Test name
Test status
Simulation time 3707862392 ps
CPU time 15.36 seconds
Started Jun 09 02:18:28 PM PDT 24
Finished Jun 09 02:18:43 PM PDT 24
Peak memory 198508 kb
Host smart-6fc629dc-0e77-4625-934c-2fa73f050043
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3893730923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.3893730923
Directory /workspace/42.uart_rx_oversample/latest

Test location /workspace/coverage/default/42.uart_rx_parity_err.1025489336
Short name T151
Test name
Test status
Simulation time 134397172748 ps
CPU time 95.49 seconds
Started Jun 09 02:18:25 PM PDT 24
Finished Jun 09 02:20:01 PM PDT 24
Peak memory 200600 kb
Host smart-dd70831f-60a3-47c6-b2cf-38cc0ba1d1cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025489336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.1025489336
Directory /workspace/42.uart_rx_parity_err/latest

Test location /workspace/coverage/default/42.uart_rx_start_bit_filter.3093975625
Short name T307
Test name
Test status
Simulation time 39199053353 ps
CPU time 16.41 seconds
Started Jun 09 02:18:24 PM PDT 24
Finished Jun 09 02:18:41 PM PDT 24
Peak memory 196692 kb
Host smart-7985ec5f-adef-45de-ad47-7dcfd5593988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093975625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.3093975625
Directory /workspace/42.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/42.uart_smoke.1984070867
Short name T601
Test name
Test status
Simulation time 11109272612 ps
CPU time 36.64 seconds
Started Jun 09 02:18:21 PM PDT 24
Finished Jun 09 02:18:58 PM PDT 24
Peak memory 200064 kb
Host smart-9d940d70-3e65-435a-a31e-117c0fae9000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984070867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_smoke.1984070867
Directory /workspace/42.uart_smoke/latest

Test location /workspace/coverage/default/42.uart_tx_ovrd.3618530163
Short name T785
Test name
Test status
Simulation time 630455986 ps
CPU time 2.07 seconds
Started Jun 09 02:18:26 PM PDT 24
Finished Jun 09 02:18:29 PM PDT 24
Peak memory 200252 kb
Host smart-fb31cb94-8774-493c-b7a7-cdc89520a4ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618530163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.3618530163
Directory /workspace/42.uart_tx_ovrd/latest

Test location /workspace/coverage/default/42.uart_tx_rx.1958545496
Short name T301
Test name
Test status
Simulation time 39799917610 ps
CPU time 53.9 seconds
Started Jun 09 02:18:21 PM PDT 24
Finished Jun 09 02:19:16 PM PDT 24
Peak memory 200608 kb
Host smart-47830544-1992-4a43-962e-e5cc160ad569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958545496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.1958545496
Directory /workspace/42.uart_tx_rx/latest

Test location /workspace/coverage/default/43.uart_alert_test.1627488501
Short name T953
Test name
Test status
Simulation time 22641448 ps
CPU time 0.56 seconds
Started Jun 09 02:18:42 PM PDT 24
Finished Jun 09 02:18:43 PM PDT 24
Peak memory 195780 kb
Host smart-764320b4-abd9-429c-8d4f-f986fbac4f6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627488501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.1627488501
Directory /workspace/43.uart_alert_test/latest

Test location /workspace/coverage/default/43.uart_fifo_full.1055109834
Short name T697
Test name
Test status
Simulation time 27399359598 ps
CPU time 45.01 seconds
Started Jun 09 02:18:25 PM PDT 24
Finished Jun 09 02:19:10 PM PDT 24
Peak memory 200392 kb
Host smart-053c613a-3f2e-45dd-b0bc-c6d0b2c08868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055109834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.1055109834
Directory /workspace/43.uart_fifo_full/latest

Test location /workspace/coverage/default/43.uart_fifo_overflow.1652671326
Short name T1016
Test name
Test status
Simulation time 94038418677 ps
CPU time 16.89 seconds
Started Jun 09 02:18:25 PM PDT 24
Finished Jun 09 02:18:43 PM PDT 24
Peak memory 199864 kb
Host smart-48715be5-f7ca-49ba-81ef-9466a2da10cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652671326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.1652671326
Directory /workspace/43.uart_fifo_overflow/latest

Test location /workspace/coverage/default/43.uart_intr.1465548411
Short name T546
Test name
Test status
Simulation time 31056392157 ps
CPU time 75.15 seconds
Started Jun 09 02:18:32 PM PDT 24
Finished Jun 09 02:19:48 PM PDT 24
Peak memory 200380 kb
Host smart-df540613-ab90-4b74-95eb-4fda26238b6b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465548411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.1465548411
Directory /workspace/43.uart_intr/latest

Test location /workspace/coverage/default/43.uart_long_xfer_wo_dly.2252733870
Short name T270
Test name
Test status
Simulation time 85764346705 ps
CPU time 530.28 seconds
Started Jun 09 02:18:30 PM PDT 24
Finished Jun 09 02:27:20 PM PDT 24
Peak memory 200392 kb
Host smart-85305516-1b3c-4215-8a1f-1f507100da12
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2252733870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.2252733870
Directory /workspace/43.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/43.uart_loopback.1275448696
Short name T20
Test name
Test status
Simulation time 4641953510 ps
CPU time 2.87 seconds
Started Jun 09 02:18:30 PM PDT 24
Finished Jun 09 02:18:33 PM PDT 24
Peak memory 199000 kb
Host smart-104f0fb1-3b77-4d92-bec9-4e6a5e4582a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275448696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_loopback.1275448696
Directory /workspace/43.uart_loopback/latest

Test location /workspace/coverage/default/43.uart_perf.2527773643
Short name T406
Test name
Test status
Simulation time 4399804813 ps
CPU time 257.44 seconds
Started Jun 09 02:18:30 PM PDT 24
Finished Jun 09 02:22:48 PM PDT 24
Peak memory 200404 kb
Host smart-18c765e9-c0a8-4ae9-b4b6-79de0127d427
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2527773643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.2527773643
Directory /workspace/43.uart_perf/latest

Test location /workspace/coverage/default/43.uart_rx_oversample.406480553
Short name T765
Test name
Test status
Simulation time 6213224413 ps
CPU time 53.79 seconds
Started Jun 09 02:18:30 PM PDT 24
Finished Jun 09 02:19:24 PM PDT 24
Peak memory 198544 kb
Host smart-3a875512-553e-4d0f-8857-a30e45d2f934
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=406480553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.406480553
Directory /workspace/43.uart_rx_oversample/latest

Test location /workspace/coverage/default/43.uart_rx_parity_err.1177263919
Short name T255
Test name
Test status
Simulation time 113471980105 ps
CPU time 199.14 seconds
Started Jun 09 02:18:31 PM PDT 24
Finished Jun 09 02:21:50 PM PDT 24
Peak memory 200372 kb
Host smart-da9445c0-03c6-4644-95c1-7190cd1f492d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177263919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.1177263919
Directory /workspace/43.uart_rx_parity_err/latest

Test location /workspace/coverage/default/43.uart_rx_start_bit_filter.2427381985
Short name T699
Test name
Test status
Simulation time 3270275719 ps
CPU time 1.8 seconds
Started Jun 09 02:18:29 PM PDT 24
Finished Jun 09 02:18:31 PM PDT 24
Peak memory 196852 kb
Host smart-8645d94b-14c7-4df7-bbcb-df9de05f1d5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427381985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.2427381985
Directory /workspace/43.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/43.uart_smoke.1824620415
Short name T855
Test name
Test status
Simulation time 691553400 ps
CPU time 4.76 seconds
Started Jun 09 02:18:25 PM PDT 24
Finished Jun 09 02:18:30 PM PDT 24
Peak memory 198676 kb
Host smart-28887606-f8e9-4723-8ad8-cd9065d2aac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824620415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_smoke.1824620415
Directory /workspace/43.uart_smoke/latest

Test location /workspace/coverage/default/43.uart_tx_ovrd.1295457229
Short name T912
Test name
Test status
Simulation time 2032048262 ps
CPU time 2.05 seconds
Started Jun 09 02:18:30 PM PDT 24
Finished Jun 09 02:18:33 PM PDT 24
Peak memory 200168 kb
Host smart-0f4512e9-9a89-4e03-8fd9-e87317c0f3cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295457229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.1295457229
Directory /workspace/43.uart_tx_ovrd/latest

Test location /workspace/coverage/default/43.uart_tx_rx.1901226465
Short name T952
Test name
Test status
Simulation time 91592621909 ps
CPU time 44.65 seconds
Started Jun 09 02:18:27 PM PDT 24
Finished Jun 09 02:19:12 PM PDT 24
Peak memory 200608 kb
Host smart-022e4763-f00d-41f0-9361-c6bf06d0b966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901226465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.1901226465
Directory /workspace/43.uart_tx_rx/latest

Test location /workspace/coverage/default/44.uart_alert_test.1891227857
Short name T360
Test name
Test status
Simulation time 55165714 ps
CPU time 0.57 seconds
Started Jun 09 02:18:40 PM PDT 24
Finished Jun 09 02:18:40 PM PDT 24
Peak memory 195748 kb
Host smart-6ef7fcec-9c8e-4425-86f6-63c0fa1ed2de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891227857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.1891227857
Directory /workspace/44.uart_alert_test/latest

Test location /workspace/coverage/default/44.uart_fifo_full.225019676
Short name T494
Test name
Test status
Simulation time 84846013983 ps
CPU time 16.74 seconds
Started Jun 09 02:18:37 PM PDT 24
Finished Jun 09 02:18:54 PM PDT 24
Peak memory 200312 kb
Host smart-ce5b8679-0018-4b80-9ca5-d989a81cbf43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225019676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.225019676
Directory /workspace/44.uart_fifo_full/latest

Test location /workspace/coverage/default/44.uart_fifo_overflow.2117230485
Short name T608
Test name
Test status
Simulation time 225596121114 ps
CPU time 409.95 seconds
Started Jun 09 02:18:38 PM PDT 24
Finished Jun 09 02:25:28 PM PDT 24
Peak memory 200316 kb
Host smart-d143a8ee-70ec-446b-81df-b270bcc779b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117230485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.2117230485
Directory /workspace/44.uart_fifo_overflow/latest

Test location /workspace/coverage/default/44.uart_fifo_reset.3072749371
Short name T512
Test name
Test status
Simulation time 40165365077 ps
CPU time 63.57 seconds
Started Jun 09 02:18:37 PM PDT 24
Finished Jun 09 02:19:41 PM PDT 24
Peak memory 200344 kb
Host smart-256f13a7-1bf5-47ca-a91b-705bcba3683e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072749371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.3072749371
Directory /workspace/44.uart_fifo_reset/latest

Test location /workspace/coverage/default/44.uart_intr.3964503967
Short name T965
Test name
Test status
Simulation time 19481524409 ps
CPU time 18.45 seconds
Started Jun 09 02:18:35 PM PDT 24
Finished Jun 09 02:18:54 PM PDT 24
Peak memory 200300 kb
Host smart-ea64a9b6-c94f-4cd9-911c-9653f1f76fee
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964503967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.3964503967
Directory /workspace/44.uart_intr/latest

Test location /workspace/coverage/default/44.uart_loopback.3272980373
Short name T372
Test name
Test status
Simulation time 9960609470 ps
CPU time 20.26 seconds
Started Jun 09 02:18:35 PM PDT 24
Finished Jun 09 02:18:55 PM PDT 24
Peak memory 200364 kb
Host smart-67b5737c-5566-4f2f-97fd-f5b3cf18d8cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272980373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_loopback.3272980373
Directory /workspace/44.uart_loopback/latest

Test location /workspace/coverage/default/44.uart_perf.3477639044
Short name T277
Test name
Test status
Simulation time 6037919246 ps
CPU time 96.78 seconds
Started Jun 09 02:18:39 PM PDT 24
Finished Jun 09 02:20:16 PM PDT 24
Peak memory 200384 kb
Host smart-77b05ea3-3015-45ec-ae66-aeafedda3666
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3477639044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.3477639044
Directory /workspace/44.uart_perf/latest

Test location /workspace/coverage/default/44.uart_rx_oversample.1487358857
Short name T535
Test name
Test status
Simulation time 4118773019 ps
CPU time 28.67 seconds
Started Jun 09 02:18:35 PM PDT 24
Finished Jun 09 02:19:04 PM PDT 24
Peak memory 198804 kb
Host smart-6f3790a1-1de8-4f0a-920c-c44e344d3476
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1487358857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.1487358857
Directory /workspace/44.uart_rx_oversample/latest

Test location /workspace/coverage/default/44.uart_rx_parity_err.2885748469
Short name T302
Test name
Test status
Simulation time 24425243366 ps
CPU time 16.57 seconds
Started Jun 09 02:18:35 PM PDT 24
Finished Jun 09 02:18:52 PM PDT 24
Peak memory 200344 kb
Host smart-3c38c033-a5aa-45d9-ada0-c6d6d61e3190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885748469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.2885748469
Directory /workspace/44.uart_rx_parity_err/latest

Test location /workspace/coverage/default/44.uart_rx_start_bit_filter.2367307766
Short name T451
Test name
Test status
Simulation time 4379357613 ps
CPU time 2.49 seconds
Started Jun 09 02:18:35 PM PDT 24
Finished Jun 09 02:18:38 PM PDT 24
Peak memory 196436 kb
Host smart-e06b821e-d9f0-4d4f-8cf9-5df7f68f0d2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367307766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.2367307766
Directory /workspace/44.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/44.uart_smoke.2837602287
Short name T1004
Test name
Test status
Simulation time 288285310 ps
CPU time 1.52 seconds
Started Jun 09 02:18:36 PM PDT 24
Finished Jun 09 02:18:38 PM PDT 24
Peak memory 200172 kb
Host smart-e2cd3158-855f-4869-b1cb-85439856c4b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837602287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_smoke.2837602287
Directory /workspace/44.uart_smoke/latest

Test location /workspace/coverage/default/44.uart_tx_ovrd.749357548
Short name T381
Test name
Test status
Simulation time 2239038383 ps
CPU time 2.21 seconds
Started Jun 09 02:18:37 PM PDT 24
Finished Jun 09 02:18:39 PM PDT 24
Peak memory 199664 kb
Host smart-d0750b4a-781e-4f63-80d6-24a604686ca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749357548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.749357548
Directory /workspace/44.uart_tx_ovrd/latest

Test location /workspace/coverage/default/44.uart_tx_rx.3310825855
Short name T113
Test name
Test status
Simulation time 19406882655 ps
CPU time 7.54 seconds
Started Jun 09 02:18:38 PM PDT 24
Finished Jun 09 02:18:45 PM PDT 24
Peak memory 200420 kb
Host smart-783451bb-4e4b-4267-98b0-40177ba68eff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310825855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.3310825855
Directory /workspace/44.uart_tx_rx/latest

Test location /workspace/coverage/default/45.uart_alert_test.3898303885
Short name T1042
Test name
Test status
Simulation time 60856824 ps
CPU time 0.53 seconds
Started Jun 09 02:18:44 PM PDT 24
Finished Jun 09 02:18:44 PM PDT 24
Peak memory 195748 kb
Host smart-2e482380-88be-4398-9cc5-b23c4661a72d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898303885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.3898303885
Directory /workspace/45.uart_alert_test/latest

Test location /workspace/coverage/default/45.uart_fifo_full.733625060
Short name T907
Test name
Test status
Simulation time 138904630767 ps
CPU time 521.62 seconds
Started Jun 09 02:18:46 PM PDT 24
Finished Jun 09 02:27:28 PM PDT 24
Peak memory 200364 kb
Host smart-a5f4af21-e35f-46ff-bc06-a3dcf4e7a0c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733625060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.733625060
Directory /workspace/45.uart_fifo_full/latest

Test location /workspace/coverage/default/45.uart_fifo_overflow.4073523286
Short name T774
Test name
Test status
Simulation time 21424889454 ps
CPU time 10.38 seconds
Started Jun 09 02:18:39 PM PDT 24
Finished Jun 09 02:18:50 PM PDT 24
Peak memory 200340 kb
Host smart-5cd94844-b26e-4594-b562-10865703ae2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073523286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.4073523286
Directory /workspace/45.uart_fifo_overflow/latest

Test location /workspace/coverage/default/45.uart_fifo_reset.3042271506
Short name T105
Test name
Test status
Simulation time 26422535184 ps
CPU time 29.74 seconds
Started Jun 09 02:18:41 PM PDT 24
Finished Jun 09 02:19:11 PM PDT 24
Peak memory 200036 kb
Host smart-189f405d-42c0-42b7-a701-91f5884b2220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042271506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.3042271506
Directory /workspace/45.uart_fifo_reset/latest

Test location /workspace/coverage/default/45.uart_intr.1832279469
Short name T1013
Test name
Test status
Simulation time 31090517203 ps
CPU time 49.93 seconds
Started Jun 09 02:18:46 PM PDT 24
Finished Jun 09 02:19:37 PM PDT 24
Peak memory 200320 kb
Host smart-f9e13836-5293-490c-ae19-e746b76e559e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832279469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.1832279469
Directory /workspace/45.uart_intr/latest

Test location /workspace/coverage/default/45.uart_long_xfer_wo_dly.1444372364
Short name T419
Test name
Test status
Simulation time 74417907627 ps
CPU time 608.26 seconds
Started Jun 09 02:18:44 PM PDT 24
Finished Jun 09 02:28:53 PM PDT 24
Peak memory 200332 kb
Host smart-243f3144-a32f-4a0a-a222-b52c6ac3d56e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1444372364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.1444372364
Directory /workspace/45.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/45.uart_loopback.3690357884
Short name T864
Test name
Test status
Simulation time 11689759743 ps
CPU time 12.44 seconds
Started Jun 09 02:18:44 PM PDT 24
Finished Jun 09 02:18:57 PM PDT 24
Peak memory 200112 kb
Host smart-80f9b1d2-80ae-4c5f-a156-8de42d58004a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690357884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_loopback.3690357884
Directory /workspace/45.uart_loopback/latest

Test location /workspace/coverage/default/45.uart_perf.2231481086
Short name T997
Test name
Test status
Simulation time 14271915316 ps
CPU time 416.88 seconds
Started Jun 09 02:18:44 PM PDT 24
Finished Jun 09 02:25:41 PM PDT 24
Peak memory 200360 kb
Host smart-64da7017-71af-4925-b8c2-c56f4c396dc0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2231481086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.2231481086
Directory /workspace/45.uart_perf/latest

Test location /workspace/coverage/default/45.uart_rx_oversample.3047551398
Short name T383
Test name
Test status
Simulation time 4100615453 ps
CPU time 3.13 seconds
Started Jun 09 02:18:46 PM PDT 24
Finished Jun 09 02:18:50 PM PDT 24
Peak memory 198168 kb
Host smart-1aee7952-7ae6-4701-befc-ae35c007b69f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3047551398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.3047551398
Directory /workspace/45.uart_rx_oversample/latest

Test location /workspace/coverage/default/45.uart_rx_parity_err.718837464
Short name T664
Test name
Test status
Simulation time 63039096122 ps
CPU time 19.84 seconds
Started Jun 09 02:18:46 PM PDT 24
Finished Jun 09 02:19:06 PM PDT 24
Peak memory 200392 kb
Host smart-026b9579-535c-43d3-bc14-6163f5ff9ef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718837464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.718837464
Directory /workspace/45.uart_rx_parity_err/latest

Test location /workspace/coverage/default/45.uart_rx_start_bit_filter.260150399
Short name T74
Test name
Test status
Simulation time 40746930472 ps
CPU time 11.33 seconds
Started Jun 09 02:18:46 PM PDT 24
Finished Jun 09 02:18:57 PM PDT 24
Peak memory 196120 kb
Host smart-7d3512e1-9ea3-4a7b-aaaa-2657138caa88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260150399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.260150399
Directory /workspace/45.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/45.uart_smoke.2909922401
Short name T565
Test name
Test status
Simulation time 477660265 ps
CPU time 1.44 seconds
Started Jun 09 02:18:40 PM PDT 24
Finished Jun 09 02:18:42 PM PDT 24
Peak memory 199920 kb
Host smart-19e99b17-5d74-4df0-82ec-4dfb2da7f885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909922401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_smoke.2909922401
Directory /workspace/45.uart_smoke/latest

Test location /workspace/coverage/default/45.uart_stress_all.3351411736
Short name T558
Test name
Test status
Simulation time 178197320861 ps
CPU time 294.24 seconds
Started Jun 09 02:18:44 PM PDT 24
Finished Jun 09 02:23:38 PM PDT 24
Peak memory 200380 kb
Host smart-69ff56e7-6018-458b-a276-be11c27e789c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351411736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.3351411736
Directory /workspace/45.uart_stress_all/latest

Test location /workspace/coverage/default/45.uart_tx_ovrd.2033970183
Short name T389
Test name
Test status
Simulation time 3154052980 ps
CPU time 1.72 seconds
Started Jun 09 02:18:44 PM PDT 24
Finished Jun 09 02:18:46 PM PDT 24
Peak memory 198744 kb
Host smart-139fa6e4-8a39-42a0-a732-d283dc0f22f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033970183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.2033970183
Directory /workspace/45.uart_tx_ovrd/latest

Test location /workspace/coverage/default/45.uart_tx_rx.2895211778
Short name T274
Test name
Test status
Simulation time 93766303469 ps
CPU time 84.55 seconds
Started Jun 09 02:18:40 PM PDT 24
Finished Jun 09 02:20:05 PM PDT 24
Peak memory 200368 kb
Host smart-6aed4f5b-c6cb-44fe-b268-0ac9497c4fd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895211778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.2895211778
Directory /workspace/45.uart_tx_rx/latest

Test location /workspace/coverage/default/46.uart_alert_test.2071575376
Short name T52
Test name
Test status
Simulation time 40386473 ps
CPU time 0.6 seconds
Started Jun 09 02:18:52 PM PDT 24
Finished Jun 09 02:18:53 PM PDT 24
Peak memory 195752 kb
Host smart-59be7852-ff37-402e-a9f3-f57bc0bbea15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071575376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.2071575376
Directory /workspace/46.uart_alert_test/latest

Test location /workspace/coverage/default/46.uart_fifo_full.142158263
Short name T428
Test name
Test status
Simulation time 179456350722 ps
CPU time 49 seconds
Started Jun 09 02:18:50 PM PDT 24
Finished Jun 09 02:19:39 PM PDT 24
Peak memory 199364 kb
Host smart-bd6fa22d-d3a4-498a-84c2-856b0cec9758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142158263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.142158263
Directory /workspace/46.uart_fifo_full/latest

Test location /workspace/coverage/default/46.uart_fifo_overflow.1915824637
Short name T831
Test name
Test status
Simulation time 125546709930 ps
CPU time 229.81 seconds
Started Jun 09 02:18:49 PM PDT 24
Finished Jun 09 02:22:39 PM PDT 24
Peak memory 200296 kb
Host smart-fe763bcf-e844-4807-85e7-9c9f2f35fdf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915824637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.1915824637
Directory /workspace/46.uart_fifo_overflow/latest

Test location /workspace/coverage/default/46.uart_fifo_reset.2209086994
Short name T669
Test name
Test status
Simulation time 96781816475 ps
CPU time 33.9 seconds
Started Jun 09 02:18:52 PM PDT 24
Finished Jun 09 02:19:26 PM PDT 24
Peak memory 200412 kb
Host smart-7672bcc3-2c49-41bd-8124-737025c8b9e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209086994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.2209086994
Directory /workspace/46.uart_fifo_reset/latest

Test location /workspace/coverage/default/46.uart_intr.851245751
Short name T1082
Test name
Test status
Simulation time 29906875266 ps
CPU time 55.07 seconds
Started Jun 09 02:18:52 PM PDT 24
Finished Jun 09 02:19:47 PM PDT 24
Peak memory 200320 kb
Host smart-1fdc612b-fb39-42de-af8f-99d0df75bc5c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851245751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.851245751
Directory /workspace/46.uart_intr/latest

Test location /workspace/coverage/default/46.uart_long_xfer_wo_dly.2223068887
Short name T741
Test name
Test status
Simulation time 83992591596 ps
CPU time 403.76 seconds
Started Jun 09 02:18:53 PM PDT 24
Finished Jun 09 02:25:37 PM PDT 24
Peak memory 200356 kb
Host smart-f287066e-dd39-4bec-8551-d6280d7fbf60
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2223068887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.2223068887
Directory /workspace/46.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/46.uart_loopback.888166478
Short name T954
Test name
Test status
Simulation time 2176732988 ps
CPU time 4.22 seconds
Started Jun 09 02:18:49 PM PDT 24
Finished Jun 09 02:18:53 PM PDT 24
Peak memory 197712 kb
Host smart-ca453a50-3502-473e-94b4-f97fc9603f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888166478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_loopback.888166478
Directory /workspace/46.uart_loopback/latest

Test location /workspace/coverage/default/46.uart_perf.3243523658
Short name T560
Test name
Test status
Simulation time 10772281168 ps
CPU time 140.31 seconds
Started Jun 09 02:18:48 PM PDT 24
Finished Jun 09 02:21:09 PM PDT 24
Peak memory 200272 kb
Host smart-b55b54df-060e-4543-9899-abf7b53f71ce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3243523658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.3243523658
Directory /workspace/46.uart_perf/latest

Test location /workspace/coverage/default/46.uart_rx_oversample.2868461703
Short name T634
Test name
Test status
Simulation time 2855952724 ps
CPU time 6.97 seconds
Started Jun 09 02:18:48 PM PDT 24
Finished Jun 09 02:18:56 PM PDT 24
Peak memory 198488 kb
Host smart-0f7b498b-ab30-43e0-8455-e89873d05b9c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2868461703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.2868461703
Directory /workspace/46.uart_rx_oversample/latest

Test location /workspace/coverage/default/46.uart_rx_parity_err.3329395404
Short name T1080
Test name
Test status
Simulation time 42613644059 ps
CPU time 76.73 seconds
Started Jun 09 02:18:48 PM PDT 24
Finished Jun 09 02:20:05 PM PDT 24
Peak memory 200340 kb
Host smart-687bc818-360f-48c8-84af-4131a0019911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329395404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.3329395404
Directory /workspace/46.uart_rx_parity_err/latest

Test location /workspace/coverage/default/46.uart_rx_start_bit_filter.2833106426
Short name T368
Test name
Test status
Simulation time 727838879 ps
CPU time 1.66 seconds
Started Jun 09 02:18:52 PM PDT 24
Finished Jun 09 02:18:54 PM PDT 24
Peak memory 195804 kb
Host smart-cf88ad3d-2b62-4579-8fa8-b6980b202925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833106426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.2833106426
Directory /workspace/46.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/46.uart_smoke.3703720417
Short name T356
Test name
Test status
Simulation time 504296521 ps
CPU time 1.25 seconds
Started Jun 09 02:18:44 PM PDT 24
Finished Jun 09 02:18:45 PM PDT 24
Peak memory 198752 kb
Host smart-73bf3f43-f755-4e63-b7e0-ac11fd04b746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703720417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_smoke.3703720417
Directory /workspace/46.uart_smoke/latest

Test location /workspace/coverage/default/46.uart_stress_all_with_rand_reset.1492453500
Short name T956
Test name
Test status
Simulation time 20207915221 ps
CPU time 183.23 seconds
Started Jun 09 02:18:54 PM PDT 24
Finished Jun 09 02:21:58 PM PDT 24
Peak memory 216572 kb
Host smart-acda5e06-a76d-4135-a0e3-b33b417637da
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492453500 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 46.uart_stress_all_with_rand_reset.1492453500
Directory /workspace/46.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.uart_tx_ovrd.2326945162
Short name T718
Test name
Test status
Simulation time 730977673 ps
CPU time 2.52 seconds
Started Jun 09 02:18:48 PM PDT 24
Finished Jun 09 02:18:51 PM PDT 24
Peak memory 198652 kb
Host smart-50fc1b0f-34c6-4bb4-973c-3ae9376f0c56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326945162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.2326945162
Directory /workspace/46.uart_tx_ovrd/latest

Test location /workspace/coverage/default/46.uart_tx_rx.3789378678
Short name T325
Test name
Test status
Simulation time 27263791001 ps
CPU time 6.11 seconds
Started Jun 09 02:18:47 PM PDT 24
Finished Jun 09 02:18:54 PM PDT 24
Peak memory 200424 kb
Host smart-0c023cff-7efa-4ce5-b33e-bab774ab3704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789378678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.3789378678
Directory /workspace/46.uart_tx_rx/latest

Test location /workspace/coverage/default/47.uart_alert_test.2051187034
Short name T349
Test name
Test status
Simulation time 14958763 ps
CPU time 0.59 seconds
Started Jun 09 02:18:59 PM PDT 24
Finished Jun 09 02:19:00 PM PDT 24
Peak memory 196048 kb
Host smart-0b6fbff5-8dec-4b02-a862-e8afd288578b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051187034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.2051187034
Directory /workspace/47.uart_alert_test/latest

Test location /workspace/coverage/default/47.uart_fifo_full.796023117
Short name T1006
Test name
Test status
Simulation time 37465966928 ps
CPU time 64.68 seconds
Started Jun 09 02:18:54 PM PDT 24
Finished Jun 09 02:19:58 PM PDT 24
Peak memory 200328 kb
Host smart-96b0a162-c0ea-4c7f-8b94-6aea7a0b5af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796023117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.796023117
Directory /workspace/47.uart_fifo_full/latest

Test location /workspace/coverage/default/47.uart_fifo_overflow.194728823
Short name T896
Test name
Test status
Simulation time 168350729278 ps
CPU time 150.34 seconds
Started Jun 09 02:18:54 PM PDT 24
Finished Jun 09 02:21:24 PM PDT 24
Peak memory 200376 kb
Host smart-9b06db53-54d4-4902-b04d-d86850481c1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194728823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.194728823
Directory /workspace/47.uart_fifo_overflow/latest

Test location /workspace/coverage/default/47.uart_fifo_reset.518501274
Short name T204
Test name
Test status
Simulation time 31403369396 ps
CPU time 29.93 seconds
Started Jun 09 02:18:54 PM PDT 24
Finished Jun 09 02:19:24 PM PDT 24
Peak memory 200396 kb
Host smart-3d6900e7-b76d-468a-a4f8-8e24764b43ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518501274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.518501274
Directory /workspace/47.uart_fifo_reset/latest

Test location /workspace/coverage/default/47.uart_intr.4139681740
Short name T22
Test name
Test status
Simulation time 56316072677 ps
CPU time 37.68 seconds
Started Jun 09 02:18:53 PM PDT 24
Finished Jun 09 02:19:30 PM PDT 24
Peak memory 200404 kb
Host smart-3ab4e055-b3c3-4e04-a117-4e94e669c42c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139681740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.4139681740
Directory /workspace/47.uart_intr/latest

Test location /workspace/coverage/default/47.uart_long_xfer_wo_dly.326196160
Short name T823
Test name
Test status
Simulation time 84525435391 ps
CPU time 590.09 seconds
Started Jun 09 02:18:59 PM PDT 24
Finished Jun 09 02:28:50 PM PDT 24
Peak memory 200380 kb
Host smart-bab3e04d-32dc-4e0b-b424-f4249604330b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=326196160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.326196160
Directory /workspace/47.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/47.uart_loopback.2567335931
Short name T519
Test name
Test status
Simulation time 7631698837 ps
CPU time 6.52 seconds
Started Jun 09 02:18:59 PM PDT 24
Finished Jun 09 02:19:06 PM PDT 24
Peak memory 200368 kb
Host smart-ecd1fd72-3ac6-4b42-9c10-0355449839b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567335931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_loopback.2567335931
Directory /workspace/47.uart_loopback/latest

Test location /workspace/coverage/default/47.uart_perf.564954667
Short name T944
Test name
Test status
Simulation time 15184271804 ps
CPU time 890.08 seconds
Started Jun 09 02:19:01 PM PDT 24
Finished Jun 09 02:33:51 PM PDT 24
Peak memory 200364 kb
Host smart-d2de7160-9e69-4808-a91f-dd3f12515ac1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=564954667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.564954667
Directory /workspace/47.uart_perf/latest

Test location /workspace/coverage/default/47.uart_rx_oversample.1322570939
Short name T856
Test name
Test status
Simulation time 4902164657 ps
CPU time 38.51 seconds
Started Jun 09 02:18:55 PM PDT 24
Finished Jun 09 02:19:34 PM PDT 24
Peak memory 199744 kb
Host smart-c40cee93-c7ac-4364-a2ba-b235d4059d77
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1322570939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.1322570939
Directory /workspace/47.uart_rx_oversample/latest

Test location /workspace/coverage/default/47.uart_rx_parity_err.1438785087
Short name T1018
Test name
Test status
Simulation time 109101863312 ps
CPU time 223.94 seconds
Started Jun 09 02:18:59 PM PDT 24
Finished Jun 09 02:22:43 PM PDT 24
Peak memory 200376 kb
Host smart-f82f251d-598f-436f-a9d9-8d06b35026e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438785087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.1438785087
Directory /workspace/47.uart_rx_parity_err/latest

Test location /workspace/coverage/default/47.uart_rx_start_bit_filter.1768850368
Short name T399
Test name
Test status
Simulation time 846158871 ps
CPU time 1.02 seconds
Started Jun 09 02:18:53 PM PDT 24
Finished Jun 09 02:18:54 PM PDT 24
Peak memory 195764 kb
Host smart-ff944c73-2daf-4245-a3a6-99abbd768d14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768850368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.1768850368
Directory /workspace/47.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/47.uart_smoke.3978559485
Short name T977
Test name
Test status
Simulation time 667393491 ps
CPU time 3.02 seconds
Started Jun 09 02:18:53 PM PDT 24
Finished Jun 09 02:18:56 PM PDT 24
Peak memory 200156 kb
Host smart-85fe78de-7276-458b-8e0e-9dd4b337bb35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978559485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_smoke.3978559485
Directory /workspace/47.uart_smoke/latest

Test location /workspace/coverage/default/47.uart_stress_all_with_rand_reset.2839509664
Short name T58
Test name
Test status
Simulation time 60727992693 ps
CPU time 127.78 seconds
Started Jun 09 02:18:58 PM PDT 24
Finished Jun 09 02:21:06 PM PDT 24
Peak memory 208708 kb
Host smart-eb3b8146-3ad9-4429-b691-07c5a7a668ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839509664 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 47.uart_stress_all_with_rand_reset.2839509664
Directory /workspace/47.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.uart_tx_ovrd.910736640
Short name T300
Test name
Test status
Simulation time 3389078325 ps
CPU time 1.99 seconds
Started Jun 09 02:19:00 PM PDT 24
Finished Jun 09 02:19:02 PM PDT 24
Peak memory 198980 kb
Host smart-ebd437f6-b382-4826-a3b2-e60038c3339d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910736640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.910736640
Directory /workspace/47.uart_tx_ovrd/latest

Test location /workspace/coverage/default/47.uart_tx_rx.3903117745
Short name T888
Test name
Test status
Simulation time 36618977799 ps
CPU time 36.55 seconds
Started Jun 09 02:18:52 PM PDT 24
Finished Jun 09 02:19:29 PM PDT 24
Peak memory 200308 kb
Host smart-7f5f4fdc-a5c0-4178-bb74-a7add6cc27b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903117745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.3903117745
Directory /workspace/47.uart_tx_rx/latest

Test location /workspace/coverage/default/48.uart_alert_test.3842284572
Short name T633
Test name
Test status
Simulation time 12205525 ps
CPU time 0.57 seconds
Started Jun 09 02:19:08 PM PDT 24
Finished Jun 09 02:19:09 PM PDT 24
Peak memory 195760 kb
Host smart-7efb517d-7e2a-4c7b-88d4-bb482610179f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842284572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.3842284572
Directory /workspace/48.uart_alert_test/latest

Test location /workspace/coverage/default/48.uart_fifo_full.2186243221
Short name T541
Test name
Test status
Simulation time 97477746953 ps
CPU time 168.53 seconds
Started Jun 09 02:19:00 PM PDT 24
Finished Jun 09 02:21:48 PM PDT 24
Peak memory 200368 kb
Host smart-06142ae7-c406-4d9b-aa55-c7c8161a571b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186243221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.2186243221
Directory /workspace/48.uart_fifo_full/latest

Test location /workspace/coverage/default/48.uart_fifo_overflow.1210879236
Short name T764
Test name
Test status
Simulation time 203555055977 ps
CPU time 172.19 seconds
Started Jun 09 02:18:59 PM PDT 24
Finished Jun 09 02:21:52 PM PDT 24
Peak memory 200292 kb
Host smart-6806a45d-fabf-48df-8b0b-3c84968861c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210879236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.1210879236
Directory /workspace/48.uart_fifo_overflow/latest

Test location /workspace/coverage/default/48.uart_intr.1622178205
Short name T931
Test name
Test status
Simulation time 14348919129 ps
CPU time 20.71 seconds
Started Jun 09 02:19:05 PM PDT 24
Finished Jun 09 02:19:26 PM PDT 24
Peak memory 200352 kb
Host smart-ea1e6e02-28f7-4f34-821d-98c8eb3f39a6
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622178205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.1622178205
Directory /workspace/48.uart_intr/latest

Test location /workspace/coverage/default/48.uart_long_xfer_wo_dly.3303362300
Short name T466
Test name
Test status
Simulation time 73401380095 ps
CPU time 278.83 seconds
Started Jun 09 02:19:05 PM PDT 24
Finished Jun 09 02:23:44 PM PDT 24
Peak memory 200392 kb
Host smart-ca555b13-920e-4218-a95e-d3996effe8f0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3303362300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.3303362300
Directory /workspace/48.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/48.uart_loopback.1640635145
Short name T679
Test name
Test status
Simulation time 6244527467 ps
CPU time 14.88 seconds
Started Jun 09 02:19:05 PM PDT 24
Finished Jun 09 02:19:21 PM PDT 24
Peak memory 200108 kb
Host smart-67c03de7-6ab1-4481-a7b4-4f23d5b566b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640635145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_loopback.1640635145
Directory /workspace/48.uart_loopback/latest

Test location /workspace/coverage/default/48.uart_noise_filter.991670323
Short name T259
Test name
Test status
Simulation time 90205132069 ps
CPU time 84.84 seconds
Started Jun 09 02:19:05 PM PDT 24
Finished Jun 09 02:20:30 PM PDT 24
Peak memory 200436 kb
Host smart-c58be07b-16b7-4add-b321-c7d245d95ea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991670323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_noise_filter.991670323
Directory /workspace/48.uart_noise_filter/latest

Test location /workspace/coverage/default/48.uart_perf.3776956017
Short name T958
Test name
Test status
Simulation time 10169918240 ps
CPU time 106.19 seconds
Started Jun 09 02:19:05 PM PDT 24
Finished Jun 09 02:20:51 PM PDT 24
Peak memory 200352 kb
Host smart-e45eab65-a4a7-4b25-9cef-991392605faf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3776956017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.3776956017
Directory /workspace/48.uart_perf/latest

Test location /workspace/coverage/default/48.uart_rx_oversample.1500520786
Short name T1057
Test name
Test status
Simulation time 3371435411 ps
CPU time 5.67 seconds
Started Jun 09 02:18:59 PM PDT 24
Finished Jun 09 02:19:05 PM PDT 24
Peak memory 198520 kb
Host smart-2f14d4bf-85c6-4a4e-a811-4d2a935a1e2f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1500520786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.1500520786
Directory /workspace/48.uart_rx_oversample/latest

Test location /workspace/coverage/default/48.uart_rx_parity_err.872507516
Short name T937
Test name
Test status
Simulation time 47548690417 ps
CPU time 73.48 seconds
Started Jun 09 02:19:04 PM PDT 24
Finished Jun 09 02:20:18 PM PDT 24
Peak memory 200360 kb
Host smart-3e4d4384-f6c3-42b3-ac93-64312e1dcb7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872507516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.872507516
Directory /workspace/48.uart_rx_parity_err/latest

Test location /workspace/coverage/default/48.uart_rx_start_bit_filter.2697001429
Short name T766
Test name
Test status
Simulation time 52767592547 ps
CPU time 19.45 seconds
Started Jun 09 02:19:05 PM PDT 24
Finished Jun 09 02:19:25 PM PDT 24
Peak memory 196132 kb
Host smart-04ed5d25-c2e2-46e9-9bc4-7cff03dc8db7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697001429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.2697001429
Directory /workspace/48.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/48.uart_smoke.2230307358
Short name T468
Test name
Test status
Simulation time 934530290 ps
CPU time 3.01 seconds
Started Jun 09 02:18:58 PM PDT 24
Finished Jun 09 02:19:02 PM PDT 24
Peak memory 200292 kb
Host smart-d3d63fe6-3257-4372-afdd-66f365706260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230307358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_smoke.2230307358
Directory /workspace/48.uart_smoke/latest

Test location /workspace/coverage/default/48.uart_tx_ovrd.1292668305
Short name T491
Test name
Test status
Simulation time 4274217160 ps
CPU time 1.9 seconds
Started Jun 09 02:19:05 PM PDT 24
Finished Jun 09 02:19:07 PM PDT 24
Peak memory 199076 kb
Host smart-9e2d44c3-3523-466f-bc4f-2b4333349046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292668305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.1292668305
Directory /workspace/48.uart_tx_ovrd/latest

Test location /workspace/coverage/default/48.uart_tx_rx.2501762952
Short name T640
Test name
Test status
Simulation time 46597002686 ps
CPU time 38.18 seconds
Started Jun 09 02:18:58 PM PDT 24
Finished Jun 09 02:19:36 PM PDT 24
Peak memory 200408 kb
Host smart-53847db5-9af7-4dac-a504-6d21b03d2d94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501762952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.2501762952
Directory /workspace/48.uart_tx_rx/latest

Test location /workspace/coverage/default/49.uart_alert_test.1384629696
Short name T499
Test name
Test status
Simulation time 35960805 ps
CPU time 0.57 seconds
Started Jun 09 02:19:14 PM PDT 24
Finished Jun 09 02:19:14 PM PDT 24
Peak memory 196052 kb
Host smart-9420fd7f-6edc-4865-83b6-8bece84eca44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384629696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.1384629696
Directory /workspace/49.uart_alert_test/latest

Test location /workspace/coverage/default/49.uart_fifo_full.1889472969
Short name T649
Test name
Test status
Simulation time 31627292440 ps
CPU time 57.95 seconds
Started Jun 09 02:19:09 PM PDT 24
Finished Jun 09 02:20:07 PM PDT 24
Peak memory 200424 kb
Host smart-f56afd95-477a-4173-aeb3-168899140d16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889472969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.1889472969
Directory /workspace/49.uart_fifo_full/latest

Test location /workspace/coverage/default/49.uart_fifo_overflow.2224395404
Short name T310
Test name
Test status
Simulation time 85038640354 ps
CPU time 45.78 seconds
Started Jun 09 02:19:13 PM PDT 24
Finished Jun 09 02:19:59 PM PDT 24
Peak memory 200372 kb
Host smart-3bd2ea0b-4320-44dd-8294-5d4f2ba4cc81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224395404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.2224395404
Directory /workspace/49.uart_fifo_overflow/latest

Test location /workspace/coverage/default/49.uart_fifo_reset.468063232
Short name T610
Test name
Test status
Simulation time 187150234133 ps
CPU time 156.56 seconds
Started Jun 09 02:19:10 PM PDT 24
Finished Jun 09 02:21:47 PM PDT 24
Peak memory 200316 kb
Host smart-d8d577bb-ebfd-4333-bbe0-f0dac8f05377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468063232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.468063232
Directory /workspace/49.uart_fifo_reset/latest

Test location /workspace/coverage/default/49.uart_intr.2358728114
Short name T116
Test name
Test status
Simulation time 21035152680 ps
CPU time 40.51 seconds
Started Jun 09 02:19:09 PM PDT 24
Finished Jun 09 02:19:50 PM PDT 24
Peak memory 200296 kb
Host smart-66e33516-2227-4e22-9321-338862a3f1db
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358728114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.2358728114
Directory /workspace/49.uart_intr/latest

Test location /workspace/coverage/default/49.uart_long_xfer_wo_dly.1970277563
Short name T490
Test name
Test status
Simulation time 104830075675 ps
CPU time 554.07 seconds
Started Jun 09 02:19:13 PM PDT 24
Finished Jun 09 02:28:28 PM PDT 24
Peak memory 200336 kb
Host smart-a910ac37-e918-40a5-9116-076d45493c80
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1970277563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.1970277563
Directory /workspace/49.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/49.uart_loopback.2104517464
Short name T477
Test name
Test status
Simulation time 4476383830 ps
CPU time 3.88 seconds
Started Jun 09 02:19:09 PM PDT 24
Finished Jun 09 02:19:14 PM PDT 24
Peak memory 200300 kb
Host smart-80c179e7-c2ad-47d5-9544-263f1d8a4483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104517464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_loopback.2104517464
Directory /workspace/49.uart_loopback/latest

Test location /workspace/coverage/default/49.uart_perf.1937987605
Short name T646
Test name
Test status
Simulation time 14515437277 ps
CPU time 164.03 seconds
Started Jun 09 02:19:15 PM PDT 24
Finished Jun 09 02:21:59 PM PDT 24
Peak memory 200332 kb
Host smart-27c7d226-caa8-40ff-85a5-b3bd86cf802b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1937987605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.1937987605
Directory /workspace/49.uart_perf/latest

Test location /workspace/coverage/default/49.uart_rx_oversample.1823655289
Short name T694
Test name
Test status
Simulation time 3150708611 ps
CPU time 5.34 seconds
Started Jun 09 02:19:11 PM PDT 24
Finished Jun 09 02:19:17 PM PDT 24
Peak memory 198768 kb
Host smart-9153f1a6-b170-4615-8da0-3935cacd9e71
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1823655289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.1823655289
Directory /workspace/49.uart_rx_oversample/latest

Test location /workspace/coverage/default/49.uart_rx_parity_err.1193286637
Short name T799
Test name
Test status
Simulation time 157066305003 ps
CPU time 165.18 seconds
Started Jun 09 02:19:09 PM PDT 24
Finished Jun 09 02:21:55 PM PDT 24
Peak memory 200368 kb
Host smart-50832c4d-82d1-4caf-a967-f20e5efc2424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193286637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.1193286637
Directory /workspace/49.uart_rx_parity_err/latest

Test location /workspace/coverage/default/49.uart_rx_start_bit_filter.1715155607
Short name T304
Test name
Test status
Simulation time 47966701972 ps
CPU time 19.52 seconds
Started Jun 09 02:19:10 PM PDT 24
Finished Jun 09 02:19:30 PM PDT 24
Peak memory 196156 kb
Host smart-96e87ab2-f602-4fd8-8573-d44ef52d377d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715155607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.1715155607
Directory /workspace/49.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/49.uart_smoke.3018648400
Short name T725
Test name
Test status
Simulation time 835190813 ps
CPU time 1.15 seconds
Started Jun 09 02:19:07 PM PDT 24
Finished Jun 09 02:19:08 PM PDT 24
Peak memory 199412 kb
Host smart-56f9e9f1-ef43-4274-9b46-3edb57730c26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018648400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_smoke.3018648400
Directory /workspace/49.uart_smoke/latest

Test location /workspace/coverage/default/49.uart_tx_ovrd.2937070015
Short name T858
Test name
Test status
Simulation time 7695291787 ps
CPU time 21.57 seconds
Started Jun 09 02:19:09 PM PDT 24
Finished Jun 09 02:19:31 PM PDT 24
Peak memory 199868 kb
Host smart-b10d105d-74a2-44f1-8d64-e1f5a185eea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937070015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.2937070015
Directory /workspace/49.uart_tx_ovrd/latest

Test location /workspace/coverage/default/49.uart_tx_rx.4208136360
Short name T532
Test name
Test status
Simulation time 46292400569 ps
CPU time 27.05 seconds
Started Jun 09 02:19:12 PM PDT 24
Finished Jun 09 02:19:39 PM PDT 24
Peak memory 200392 kb
Host smart-278cc92c-70f2-431d-a52d-3ca1cb883c14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208136360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.4208136360
Directory /workspace/49.uart_tx_rx/latest

Test location /workspace/coverage/default/5.uart_alert_test.703066834
Short name T347
Test name
Test status
Simulation time 23650969 ps
CPU time 0.57 seconds
Started Jun 09 02:13:47 PM PDT 24
Finished Jun 09 02:13:48 PM PDT 24
Peak memory 195408 kb
Host smart-f8419a33-3cef-4509-b62f-c15f8e6fa1d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703066834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.703066834
Directory /workspace/5.uart_alert_test/latest

Test location /workspace/coverage/default/5.uart_fifo_full.834538256
Short name T320
Test name
Test status
Simulation time 118936972942 ps
CPU time 95.42 seconds
Started Jun 09 02:13:38 PM PDT 24
Finished Jun 09 02:15:14 PM PDT 24
Peak memory 200360 kb
Host smart-5774f8a7-b2c3-4a1f-937a-60346cd753f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834538256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.834538256
Directory /workspace/5.uart_fifo_full/latest

Test location /workspace/coverage/default/5.uart_fifo_reset.3125034709
Short name T228
Test name
Test status
Simulation time 56697735612 ps
CPU time 25.08 seconds
Started Jun 09 02:13:38 PM PDT 24
Finished Jun 09 02:14:04 PM PDT 24
Peak memory 200420 kb
Host smart-7ee746b3-e455-4c20-86f1-678ddc28620b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125034709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.3125034709
Directory /workspace/5.uart_fifo_reset/latest

Test location /workspace/coverage/default/5.uart_intr.3232823625
Short name T411
Test name
Test status
Simulation time 69355091870 ps
CPU time 45.39 seconds
Started Jun 09 02:13:39 PM PDT 24
Finished Jun 09 02:14:25 PM PDT 24
Peak memory 200244 kb
Host smart-02171fd1-eeb1-4b87-84cb-6523805872bc
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232823625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.3232823625
Directory /workspace/5.uart_intr/latest

Test location /workspace/coverage/default/5.uart_long_xfer_wo_dly.893496723
Short name T469
Test name
Test status
Simulation time 84576428279 ps
CPU time 779.09 seconds
Started Jun 09 02:14:34 PM PDT 24
Finished Jun 09 02:27:33 PM PDT 24
Peak memory 200336 kb
Host smart-eb17b5b9-9d00-4a77-925b-af28b38486bb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=893496723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.893496723
Directory /workspace/5.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/5.uart_loopback.2779219505
Short name T413
Test name
Test status
Simulation time 11378711235 ps
CPU time 7.17 seconds
Started Jun 09 02:13:50 PM PDT 24
Finished Jun 09 02:13:58 PM PDT 24
Peak memory 199072 kb
Host smart-ab06576b-8fd1-4939-9573-ae73f36f0866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779219505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_loopback.2779219505
Directory /workspace/5.uart_loopback/latest

Test location /workspace/coverage/default/5.uart_perf.3465855050
Short name T279
Test name
Test status
Simulation time 13668980517 ps
CPU time 383.84 seconds
Started Jun 09 02:13:48 PM PDT 24
Finished Jun 09 02:20:13 PM PDT 24
Peak memory 200332 kb
Host smart-6cdda6f4-986e-409a-b449-de7bf5175ac1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3465855050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.3465855050
Directory /workspace/5.uart_perf/latest

Test location /workspace/coverage/default/5.uart_rx_oversample.550120854
Short name T353
Test name
Test status
Simulation time 3915143512 ps
CPU time 2.3 seconds
Started Jun 09 02:13:39 PM PDT 24
Finished Jun 09 02:13:42 PM PDT 24
Peak memory 198572 kb
Host smart-892424d3-ad1e-42c4-81e0-fcba636a8574
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=550120854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.550120854
Directory /workspace/5.uart_rx_oversample/latest

Test location /workspace/coverage/default/5.uart_rx_parity_err.2067832770
Short name T1025
Test name
Test status
Simulation time 11336413960 ps
CPU time 24.24 seconds
Started Jun 09 02:13:45 PM PDT 24
Finished Jun 09 02:14:09 PM PDT 24
Peak memory 200324 kb
Host smart-ca73bd11-8f9c-4fe9-99e9-db08ce9131be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067832770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.2067832770
Directory /workspace/5.uart_rx_parity_err/latest

Test location /workspace/coverage/default/5.uart_rx_start_bit_filter.2174562285
Short name T514
Test name
Test status
Simulation time 4527253275 ps
CPU time 1.15 seconds
Started Jun 09 02:13:46 PM PDT 24
Finished Jun 09 02:13:47 PM PDT 24
Peak memory 196460 kb
Host smart-df0f9f58-1af4-4622-bc62-67fac1253979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174562285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.2174562285
Directory /workspace/5.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/5.uart_smoke.1840598156
Short name T763
Test name
Test status
Simulation time 249344206 ps
CPU time 1.46 seconds
Started Jun 09 02:13:39 PM PDT 24
Finished Jun 09 02:13:40 PM PDT 24
Peak memory 198796 kb
Host smart-adc742e9-d0a4-468f-b2fc-1b559fcf5c83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840598156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_smoke.1840598156
Directory /workspace/5.uart_smoke/latest

Test location /workspace/coverage/default/5.uart_stress_all.1252023215
Short name T650
Test name
Test status
Simulation time 279326551661 ps
CPU time 551.38 seconds
Started Jun 09 02:13:51 PM PDT 24
Finished Jun 09 02:23:03 PM PDT 24
Peak memory 200368 kb
Host smart-703b8f4a-44c4-4cb8-9cc7-010b8c1cbe52
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252023215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.1252023215
Directory /workspace/5.uart_stress_all/latest

Test location /workspace/coverage/default/5.uart_stress_all_with_rand_reset.725212288
Short name T57
Test name
Test status
Simulation time 150429220838 ps
CPU time 833.95 seconds
Started Jun 09 02:13:50 PM PDT 24
Finished Jun 09 02:27:45 PM PDT 24
Peak memory 216872 kb
Host smart-3c1057a1-e874-4fdf-9148-e45a456809e6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725212288 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 5.uart_stress_all_with_rand_reset.725212288
Directory /workspace/5.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.uart_tx_ovrd.3714536418
Short name T887
Test name
Test status
Simulation time 1797167188 ps
CPU time 2.01 seconds
Started Jun 09 02:13:43 PM PDT 24
Finished Jun 09 02:13:45 PM PDT 24
Peak memory 200252 kb
Host smart-d153091a-0fc0-419d-abfc-a3114650fbc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714536418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.3714536418
Directory /workspace/5.uart_tx_ovrd/latest

Test location /workspace/coverage/default/5.uart_tx_rx.4096278433
Short name T643
Test name
Test status
Simulation time 86829898039 ps
CPU time 82.49 seconds
Started Jun 09 02:13:38 PM PDT 24
Finished Jun 09 02:15:00 PM PDT 24
Peak memory 200292 kb
Host smart-3a25eedf-58a7-49dd-972f-2fc674f7a42b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096278433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.4096278433
Directory /workspace/5.uart_tx_rx/latest

Test location /workspace/coverage/default/50.uart_fifo_reset.3149204195
Short name T518
Test name
Test status
Simulation time 18313010976 ps
CPU time 27.63 seconds
Started Jun 09 02:19:14 PM PDT 24
Finished Jun 09 02:19:42 PM PDT 24
Peak memory 200156 kb
Host smart-ce094452-066f-4a1c-962e-3c61da695338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149204195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.3149204195
Directory /workspace/50.uart_fifo_reset/latest

Test location /workspace/coverage/default/51.uart_fifo_reset.2591809403
Short name T492
Test name
Test status
Simulation time 97114970364 ps
CPU time 40.4 seconds
Started Jun 09 02:19:16 PM PDT 24
Finished Jun 09 02:19:57 PM PDT 24
Peak memory 200360 kb
Host smart-8ffbf212-d73d-46cb-8baf-0c72313fe3be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591809403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.2591809403
Directory /workspace/51.uart_fifo_reset/latest

Test location /workspace/coverage/default/51.uart_stress_all_with_rand_reset.1261329360
Short name T911
Test name
Test status
Simulation time 53685892951 ps
CPU time 582.16 seconds
Started Jun 09 02:19:17 PM PDT 24
Finished Jun 09 02:29:00 PM PDT 24
Peak memory 216988 kb
Host smart-ef329d34-fe2c-47a9-81da-da072c9a2101
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261329360 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 51.uart_stress_all_with_rand_reset.1261329360
Directory /workspace/51.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.uart_fifo_reset.2352306004
Short name T488
Test name
Test status
Simulation time 165509088838 ps
CPU time 72.43 seconds
Started Jun 09 02:19:19 PM PDT 24
Finished Jun 09 02:20:32 PM PDT 24
Peak memory 200228 kb
Host smart-9dac2434-db60-488b-8073-95d409bdbf23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352306004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.2352306004
Directory /workspace/52.uart_fifo_reset/latest

Test location /workspace/coverage/default/53.uart_fifo_reset.1599232477
Short name T224
Test name
Test status
Simulation time 25552504154 ps
CPU time 43.6 seconds
Started Jun 09 02:19:20 PM PDT 24
Finished Jun 09 02:20:04 PM PDT 24
Peak memory 200544 kb
Host smart-4335558a-6419-4409-bb44-430f2764feea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599232477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.1599232477
Directory /workspace/53.uart_fifo_reset/latest

Test location /workspace/coverage/default/53.uart_stress_all_with_rand_reset.630558089
Short name T329
Test name
Test status
Simulation time 171830940281 ps
CPU time 501.46 seconds
Started Jun 09 02:19:21 PM PDT 24
Finished Jun 09 02:27:43 PM PDT 24
Peak memory 216928 kb
Host smart-ac5d3591-18e5-47be-a106-cec3ff862fe6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630558089 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 53.uart_stress_all_with_rand_reset.630558089
Directory /workspace/53.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.uart_fifo_reset.2327333475
Short name T695
Test name
Test status
Simulation time 28576493190 ps
CPU time 28.39 seconds
Started Jun 09 02:19:19 PM PDT 24
Finished Jun 09 02:19:47 PM PDT 24
Peak memory 200240 kb
Host smart-08d8a8ad-4b31-45e7-b8e5-f774129f05a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327333475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.2327333475
Directory /workspace/54.uart_fifo_reset/latest

Test location /workspace/coverage/default/55.uart_fifo_reset.1550360416
Short name T673
Test name
Test status
Simulation time 114987762763 ps
CPU time 97.22 seconds
Started Jun 09 02:19:20 PM PDT 24
Finished Jun 09 02:20:58 PM PDT 24
Peak memory 200356 kb
Host smart-8ee261e5-b0ee-4efe-8e5c-c0f992085a1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550360416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.1550360416
Directory /workspace/55.uart_fifo_reset/latest

Test location /workspace/coverage/default/55.uart_stress_all_with_rand_reset.3777411281
Short name T327
Test name
Test status
Simulation time 21008579211 ps
CPU time 169.87 seconds
Started Jun 09 02:19:19 PM PDT 24
Finished Jun 09 02:22:09 PM PDT 24
Peak memory 216844 kb
Host smart-5e348158-74dc-483e-8272-fde61130931f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777411281 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 55.uart_stress_all_with_rand_reset.3777411281
Directory /workspace/55.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/56.uart_fifo_reset.1632998089
Short name T153
Test name
Test status
Simulation time 50832960188 ps
CPU time 68.7 seconds
Started Jun 09 02:19:19 PM PDT 24
Finished Jun 09 02:20:28 PM PDT 24
Peak memory 200416 kb
Host smart-58eac9b4-a17d-477e-a8c6-42b02a523294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632998089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.1632998089
Directory /workspace/56.uart_fifo_reset/latest

Test location /workspace/coverage/default/56.uart_stress_all_with_rand_reset.954730722
Short name T993
Test name
Test status
Simulation time 56822459991 ps
CPU time 794.17 seconds
Started Jun 09 02:19:25 PM PDT 24
Finished Jun 09 02:32:39 PM PDT 24
Peak memory 216920 kb
Host smart-32580c46-c6e8-4d41-ad33-331f405bbac3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954730722 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 56.uart_stress_all_with_rand_reset.954730722
Directory /workspace/56.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.uart_fifo_reset.488114326
Short name T1007
Test name
Test status
Simulation time 188605781389 ps
CPU time 17.11 seconds
Started Jun 09 02:19:25 PM PDT 24
Finished Jun 09 02:19:42 PM PDT 24
Peak memory 200368 kb
Host smart-639cfdee-0f9a-4fd5-a186-df322744d296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488114326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.488114326
Directory /workspace/57.uart_fifo_reset/latest

Test location /workspace/coverage/default/57.uart_stress_all_with_rand_reset.2194319050
Short name T1067
Test name
Test status
Simulation time 191314200264 ps
CPU time 832.39 seconds
Started Jun 09 02:19:19 PM PDT 24
Finished Jun 09 02:33:12 PM PDT 24
Peak memory 216852 kb
Host smart-5b28cdcb-99e7-4a19-8a8f-1ca5c0ffad54
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194319050 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 57.uart_stress_all_with_rand_reset.2194319050
Directory /workspace/57.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/58.uart_fifo_reset.1635818961
Short name T1017
Test name
Test status
Simulation time 86173056762 ps
CPU time 134.27 seconds
Started Jun 09 02:19:20 PM PDT 24
Finished Jun 09 02:21:34 PM PDT 24
Peak memory 200544 kb
Host smart-45b9fbc7-eadc-4915-8541-3d6f6536396d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635818961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.1635818961
Directory /workspace/58.uart_fifo_reset/latest

Test location /workspace/coverage/default/58.uart_stress_all_with_rand_reset.196944403
Short name T31
Test name
Test status
Simulation time 18059686768 ps
CPU time 79.92 seconds
Started Jun 09 02:19:22 PM PDT 24
Finished Jun 09 02:20:43 PM PDT 24
Peak memory 208680 kb
Host smart-f22bdaa5-e9d1-42e2-88c1-37c39552b113
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196944403 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 58.uart_stress_all_with_rand_reset.196944403
Directory /workspace/58.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/59.uart_fifo_reset.847353719
Short name T736
Test name
Test status
Simulation time 152028835098 ps
CPU time 63.01 seconds
Started Jun 09 02:19:22 PM PDT 24
Finished Jun 09 02:20:25 PM PDT 24
Peak memory 200188 kb
Host smart-aa316423-5f5b-4586-9d71-0f363e3ba997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847353719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.847353719
Directory /workspace/59.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_alert_test.4060848755
Short name T893
Test name
Test status
Simulation time 14110116 ps
CPU time 0.57 seconds
Started Jun 09 02:14:00 PM PDT 24
Finished Jun 09 02:14:00 PM PDT 24
Peak memory 195744 kb
Host smart-24d451d4-e9f5-4c5d-a354-07a996d08e96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060848755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.4060848755
Directory /workspace/6.uart_alert_test/latest

Test location /workspace/coverage/default/6.uart_fifo_full.578884464
Short name T501
Test name
Test status
Simulation time 33628217328 ps
CPU time 25.83 seconds
Started Jun 09 02:13:51 PM PDT 24
Finished Jun 09 02:14:17 PM PDT 24
Peak memory 200408 kb
Host smart-f8ee9730-8058-4f13-89ba-1314d17507f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578884464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.578884464
Directory /workspace/6.uart_fifo_full/latest

Test location /workspace/coverage/default/6.uart_fifo_overflow.3867746508
Short name T165
Test name
Test status
Simulation time 164737090568 ps
CPU time 71.9 seconds
Started Jun 09 02:13:55 PM PDT 24
Finished Jun 09 02:15:07 PM PDT 24
Peak memory 200348 kb
Host smart-bd84b041-9534-497b-a559-01e4197f90f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867746508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.3867746508
Directory /workspace/6.uart_fifo_overflow/latest

Test location /workspace/coverage/default/6.uart_fifo_reset.1430992419
Short name T611
Test name
Test status
Simulation time 19076743892 ps
CPU time 9.67 seconds
Started Jun 09 02:13:54 PM PDT 24
Finished Jun 09 02:14:04 PM PDT 24
Peak memory 200364 kb
Host smart-ec661904-cce1-4474-876a-31ee22f8163b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430992419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.1430992419
Directory /workspace/6.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_intr.1327729453
Short name T377
Test name
Test status
Simulation time 147090560805 ps
CPU time 225.24 seconds
Started Jun 09 02:13:55 PM PDT 24
Finished Jun 09 02:17:41 PM PDT 24
Peak memory 198180 kb
Host smart-a02e8dd8-d05e-418d-8ee3-de0688b8336e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327729453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.1327729453
Directory /workspace/6.uart_intr/latest

Test location /workspace/coverage/default/6.uart_long_xfer_wo_dly.2279534757
Short name T593
Test name
Test status
Simulation time 63378975094 ps
CPU time 387.1 seconds
Started Jun 09 02:13:58 PM PDT 24
Finished Jun 09 02:20:26 PM PDT 24
Peak memory 200380 kb
Host smart-aa7ee973-0454-466b-af20-d82b0ccd4f26
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2279534757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.2279534757
Directory /workspace/6.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/6.uart_loopback.2235452467
Short name T443
Test name
Test status
Simulation time 7153727515 ps
CPU time 7.24 seconds
Started Jun 09 02:13:53 PM PDT 24
Finished Jun 09 02:14:01 PM PDT 24
Peak memory 200224 kb
Host smart-2f8c3d76-bcf7-44ce-807d-4597320f1afa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235452467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_loopback.2235452467
Directory /workspace/6.uart_loopback/latest

Test location /workspace/coverage/default/6.uart_noise_filter.1542255131
Short name T557
Test name
Test status
Simulation time 18324892874 ps
CPU time 33.34 seconds
Started Jun 09 02:13:54 PM PDT 24
Finished Jun 09 02:14:27 PM PDT 24
Peak memory 200340 kb
Host smart-74f8479f-2e85-4c54-8af6-461287b4f1fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542255131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_noise_filter.1542255131
Directory /workspace/6.uart_noise_filter/latest

Test location /workspace/coverage/default/6.uart_perf.446180860
Short name T613
Test name
Test status
Simulation time 17565460381 ps
CPU time 849.19 seconds
Started Jun 09 02:13:58 PM PDT 24
Finished Jun 09 02:28:08 PM PDT 24
Peak memory 200440 kb
Host smart-26744cc6-bf76-4d8f-9c81-a370512cbf14
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=446180860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.446180860
Directory /workspace/6.uart_perf/latest

Test location /workspace/coverage/default/6.uart_rx_oversample.4201109826
Short name T341
Test name
Test status
Simulation time 2687435610 ps
CPU time 2.57 seconds
Started Jun 09 02:13:55 PM PDT 24
Finished Jun 09 02:13:58 PM PDT 24
Peak memory 198824 kb
Host smart-5b4009ed-6fba-46b4-9789-4464f4f7adce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4201109826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.4201109826
Directory /workspace/6.uart_rx_oversample/latest

Test location /workspace/coverage/default/6.uart_rx_parity_err.2393254462
Short name T852
Test name
Test status
Simulation time 19623513448 ps
CPU time 29.39 seconds
Started Jun 09 02:13:55 PM PDT 24
Finished Jun 09 02:14:24 PM PDT 24
Peak memory 200328 kb
Host smart-b4ba82e2-827b-47da-9dd0-793f3644358e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393254462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.2393254462
Directory /workspace/6.uart_rx_parity_err/latest

Test location /workspace/coverage/default/6.uart_rx_start_bit_filter.792875272
Short name T474
Test name
Test status
Simulation time 2499432059 ps
CPU time 1.58 seconds
Started Jun 09 02:13:55 PM PDT 24
Finished Jun 09 02:13:57 PM PDT 24
Peak memory 196088 kb
Host smart-f4a299df-f0c3-4433-b971-aec8f9c279e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792875272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.792875272
Directory /workspace/6.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/6.uart_smoke.3823116875
Short name T1072
Test name
Test status
Simulation time 427704005 ps
CPU time 2.1 seconds
Started Jun 09 02:13:51 PM PDT 24
Finished Jun 09 02:13:53 PM PDT 24
Peak memory 199244 kb
Host smart-c652415f-d855-4425-97c2-5867e582a43d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823116875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_smoke.3823116875
Directory /workspace/6.uart_smoke/latest

Test location /workspace/coverage/default/6.uart_stress_all.19497767
Short name T208
Test name
Test status
Simulation time 48683780862 ps
CPU time 20.78 seconds
Started Jun 09 02:14:01 PM PDT 24
Finished Jun 09 02:14:22 PM PDT 24
Peak memory 200332 kb
Host smart-6d2271dc-555e-4a15-bab8-db1de0f2dbe8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19497767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.19497767
Directory /workspace/6.uart_stress_all/latest

Test location /workspace/coverage/default/6.uart_stress_all_with_rand_reset.1800369099
Short name T926
Test name
Test status
Simulation time 318671822453 ps
CPU time 1539.77 seconds
Started Jun 09 02:13:56 PM PDT 24
Finished Jun 09 02:39:37 PM PDT 24
Peak memory 225048 kb
Host smart-6ca16bd5-83e3-4bc1-b6b9-b11b91e4363b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800369099 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 6.uart_stress_all_with_rand_reset.1800369099
Directory /workspace/6.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_tx_ovrd.743459629
Short name T495
Test name
Test status
Simulation time 1297308630 ps
CPU time 3.88 seconds
Started Jun 09 02:13:53 PM PDT 24
Finished Jun 09 02:13:57 PM PDT 24
Peak memory 198680 kb
Host smart-fbe3ca49-a9cc-4377-b293-b9cae45512b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743459629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.743459629
Directory /workspace/6.uart_tx_ovrd/latest

Test location /workspace/coverage/default/6.uart_tx_rx.2766105912
Short name T910
Test name
Test status
Simulation time 103910412145 ps
CPU time 41.49 seconds
Started Jun 09 02:13:50 PM PDT 24
Finished Jun 09 02:14:32 PM PDT 24
Peak memory 200308 kb
Host smart-d965c313-8445-4d68-a8c2-84ea729f031c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766105912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.2766105912
Directory /workspace/6.uart_tx_rx/latest

Test location /workspace/coverage/default/61.uart_fifo_reset.1665375640
Short name T510
Test name
Test status
Simulation time 92794272235 ps
CPU time 60.77 seconds
Started Jun 09 02:19:17 PM PDT 24
Finished Jun 09 02:20:18 PM PDT 24
Peak memory 200412 kb
Host smart-fadf9d9a-9e11-4d74-9e92-dae9738888ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665375640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.1665375640
Directory /workspace/61.uart_fifo_reset/latest

Test location /workspace/coverage/default/61.uart_stress_all_with_rand_reset.1157321906
Short name T120
Test name
Test status
Simulation time 8586699755 ps
CPU time 173.55 seconds
Started Jun 09 02:19:25 PM PDT 24
Finished Jun 09 02:22:18 PM PDT 24
Peak memory 216812 kb
Host smart-edc06332-5ef2-4857-9c0a-6634d8519823
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157321906 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 61.uart_stress_all_with_rand_reset.1157321906
Directory /workspace/61.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.uart_fifo_reset.165915595
Short name T215
Test name
Test status
Simulation time 34108212548 ps
CPU time 28.45 seconds
Started Jun 09 02:19:22 PM PDT 24
Finished Jun 09 02:19:51 PM PDT 24
Peak memory 200340 kb
Host smart-bb0ab937-b32f-4fc1-bd4b-96db87beb9c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165915595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.165915595
Directory /workspace/62.uart_fifo_reset/latest

Test location /workspace/coverage/default/63.uart_fifo_reset.3210779933
Short name T205
Test name
Test status
Simulation time 412598586063 ps
CPU time 58.68 seconds
Started Jun 09 02:19:22 PM PDT 24
Finished Jun 09 02:20:20 PM PDT 24
Peak memory 199308 kb
Host smart-20d2be2a-9f80-473b-9fe3-c3dabc1ca39b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210779933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.3210779933
Directory /workspace/63.uart_fifo_reset/latest

Test location /workspace/coverage/default/64.uart_fifo_reset.745050315
Short name T1085
Test name
Test status
Simulation time 64050823946 ps
CPU time 95.27 seconds
Started Jun 09 02:19:23 PM PDT 24
Finished Jun 09 02:20:59 PM PDT 24
Peak memory 200292 kb
Host smart-6384f0a3-515a-4815-8ca7-258904c913e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745050315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.745050315
Directory /workspace/64.uart_fifo_reset/latest

Test location /workspace/coverage/default/64.uart_stress_all_with_rand_reset.580819488
Short name T234
Test name
Test status
Simulation time 206432085932 ps
CPU time 351.07 seconds
Started Jun 09 02:19:28 PM PDT 24
Finished Jun 09 02:25:19 PM PDT 24
Peak memory 216928 kb
Host smart-cccb400f-689b-4235-99d2-e0d7f4cf7425
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580819488 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 64.uart_stress_all_with_rand_reset.580819488
Directory /workspace/64.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/65.uart_fifo_reset.3041605933
Short name T592
Test name
Test status
Simulation time 22443653978 ps
CPU time 42.46 seconds
Started Jun 09 02:19:28 PM PDT 24
Finished Jun 09 02:20:11 PM PDT 24
Peak memory 200392 kb
Host smart-3f0f9b7f-e9af-4502-ad0d-32d971f800a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041605933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.3041605933
Directory /workspace/65.uart_fifo_reset/latest

Test location /workspace/coverage/default/66.uart_fifo_reset.3610393563
Short name T9
Test name
Test status
Simulation time 125022604758 ps
CPU time 53.36 seconds
Started Jun 09 02:19:39 PM PDT 24
Finished Jun 09 02:20:33 PM PDT 24
Peak memory 200364 kb
Host smart-3b60da2d-e83d-45f8-bab8-6fba3ba20f12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610393563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.3610393563
Directory /workspace/66.uart_fifo_reset/latest

Test location /workspace/coverage/default/66.uart_stress_all_with_rand_reset.416696485
Short name T899
Test name
Test status
Simulation time 16819697358 ps
CPU time 176.79 seconds
Started Jun 09 02:19:28 PM PDT 24
Finished Jun 09 02:22:25 PM PDT 24
Peak memory 208732 kb
Host smart-0a01ca5c-3054-4c87-83be-2226706e072f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416696485 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 66.uart_stress_all_with_rand_reset.416696485
Directory /workspace/66.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.uart_fifo_reset.460223028
Short name T480
Test name
Test status
Simulation time 20677306995 ps
CPU time 36.54 seconds
Started Jun 09 02:19:29 PM PDT 24
Finished Jun 09 02:20:06 PM PDT 24
Peak memory 200304 kb
Host smart-83cc5d7b-2ea8-45e1-a8fe-eee3bb4b5b07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460223028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.460223028
Directory /workspace/67.uart_fifo_reset/latest

Test location /workspace/coverage/default/68.uart_fifo_reset.2356220856
Short name T324
Test name
Test status
Simulation time 34871856747 ps
CPU time 44.84 seconds
Started Jun 09 02:19:27 PM PDT 24
Finished Jun 09 02:20:12 PM PDT 24
Peak memory 200316 kb
Host smart-120e27cc-dde6-4152-839e-859462bd44f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356220856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.2356220856
Directory /workspace/68.uart_fifo_reset/latest

Test location /workspace/coverage/default/68.uart_stress_all_with_rand_reset.3884287869
Short name T30
Test name
Test status
Simulation time 23496542270 ps
CPU time 217.01 seconds
Started Jun 09 02:19:40 PM PDT 24
Finished Jun 09 02:23:18 PM PDT 24
Peak memory 208744 kb
Host smart-436a0096-6c6f-469d-8c93-d6cb63106513
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884287869 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 68.uart_stress_all_with_rand_reset.3884287869
Directory /workspace/68.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.uart_fifo_reset.3303752910
Short name T54
Test name
Test status
Simulation time 19229958681 ps
CPU time 28.79 seconds
Started Jun 09 02:19:30 PM PDT 24
Finished Jun 09 02:19:59 PM PDT 24
Peak memory 200204 kb
Host smart-72c0a728-fd47-4084-ac7a-a3b8baaf1fe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303752910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.3303752910
Directory /workspace/69.uart_fifo_reset/latest

Test location /workspace/coverage/default/69.uart_stress_all_with_rand_reset.4013110189
Short name T59
Test name
Test status
Simulation time 435799518590 ps
CPU time 587.82 seconds
Started Jun 09 02:19:29 PM PDT 24
Finished Jun 09 02:29:17 PM PDT 24
Peak memory 215352 kb
Host smart-163098a0-ccfc-4fea-a751-4ee786aa6c40
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013110189 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 69.uart_stress_all_with_rand_reset.4013110189
Directory /workspace/69.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_alert_test.1321596199
Short name T709
Test name
Test status
Simulation time 14227899 ps
CPU time 0.57 seconds
Started Jun 09 02:14:09 PM PDT 24
Finished Jun 09 02:14:09 PM PDT 24
Peak memory 195724 kb
Host smart-cd14c005-7c0d-4103-8571-f05e88b43964
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321596199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.1321596199
Directory /workspace/7.uart_alert_test/latest

Test location /workspace/coverage/default/7.uart_fifo_full.3368611576
Short name T822
Test name
Test status
Simulation time 201505628140 ps
CPU time 310.82 seconds
Started Jun 09 02:13:57 PM PDT 24
Finished Jun 09 02:19:08 PM PDT 24
Peak memory 200408 kb
Host smart-8f5f4919-b904-46b8-8bf2-59a3123c29ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368611576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.3368611576
Directory /workspace/7.uart_fifo_full/latest

Test location /workspace/coverage/default/7.uart_fifo_overflow.1481964364
Short name T878
Test name
Test status
Simulation time 36311007046 ps
CPU time 68.97 seconds
Started Jun 09 02:13:57 PM PDT 24
Finished Jun 09 02:15:07 PM PDT 24
Peak memory 200404 kb
Host smart-02fdb339-2656-402a-9a38-4ef223be53d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481964364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.1481964364
Directory /workspace/7.uart_fifo_overflow/latest

Test location /workspace/coverage/default/7.uart_fifo_reset.1776707953
Short name T109
Test name
Test status
Simulation time 23498188499 ps
CPU time 17.27 seconds
Started Jun 09 02:14:03 PM PDT 24
Finished Jun 09 02:14:20 PM PDT 24
Peak memory 200356 kb
Host smart-a047b432-7af0-42d7-9d24-3162a34c4dff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776707953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.1776707953
Directory /workspace/7.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_intr.1002319263
Short name T984
Test name
Test status
Simulation time 38101292772 ps
CPU time 14.45 seconds
Started Jun 09 02:14:04 PM PDT 24
Finished Jun 09 02:14:18 PM PDT 24
Peak memory 199444 kb
Host smart-f76f5e8b-6682-4210-b8fd-3b24c6f029de
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002319263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.1002319263
Directory /workspace/7.uart_intr/latest

Test location /workspace/coverage/default/7.uart_long_xfer_wo_dly.4085498021
Short name T1030
Test name
Test status
Simulation time 95408432926 ps
CPU time 1010.72 seconds
Started Jun 09 02:14:08 PM PDT 24
Finished Jun 09 02:30:59 PM PDT 24
Peak memory 200324 kb
Host smart-7e8d2f31-4a6d-4515-ab3a-54b56e6c2fea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4085498021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.4085498021
Directory /workspace/7.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/7.uart_loopback.2462022731
Short name T464
Test name
Test status
Simulation time 2744445300 ps
CPU time 5.27 seconds
Started Jun 09 02:14:03 PM PDT 24
Finished Jun 09 02:14:09 PM PDT 24
Peak memory 199380 kb
Host smart-16181f6b-368e-4c5d-88d3-0641b6ecf66c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462022731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_loopback.2462022731
Directory /workspace/7.uart_loopback/latest

Test location /workspace/coverage/default/7.uart_perf.1494567263
Short name T53
Test name
Test status
Simulation time 2880230598 ps
CPU time 36.49 seconds
Started Jun 09 02:14:08 PM PDT 24
Finished Jun 09 02:14:45 PM PDT 24
Peak memory 200264 kb
Host smart-3e6346b8-e36f-4b4a-99c1-1b1a7b1af1f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1494567263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.1494567263
Directory /workspace/7.uart_perf/latest

Test location /workspace/coverage/default/7.uart_rx_oversample.785354290
Short name T376
Test name
Test status
Simulation time 5033568887 ps
CPU time 15.3 seconds
Started Jun 09 02:14:03 PM PDT 24
Finished Jun 09 02:14:19 PM PDT 24
Peak memory 199716 kb
Host smart-7a261dab-dc54-4a8c-9b31-4a95eb90ddf4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=785354290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.785354290
Directory /workspace/7.uart_rx_oversample/latest

Test location /workspace/coverage/default/7.uart_rx_parity_err.3163504270
Short name T941
Test name
Test status
Simulation time 23413812030 ps
CPU time 41.35 seconds
Started Jun 09 02:14:01 PM PDT 24
Finished Jun 09 02:14:42 PM PDT 24
Peak memory 200344 kb
Host smart-53441df5-28a6-4101-8052-3134386f9007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163504270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.3163504270
Directory /workspace/7.uart_rx_parity_err/latest

Test location /workspace/coverage/default/7.uart_rx_start_bit_filter.2328091057
Short name T809
Test name
Test status
Simulation time 34257732740 ps
CPU time 15.67 seconds
Started Jun 09 02:14:03 PM PDT 24
Finished Jun 09 02:14:19 PM PDT 24
Peak memory 196476 kb
Host smart-d5b1e165-4c27-4097-bdbf-2ceb11fa731b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328091057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.2328091057
Directory /workspace/7.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/7.uart_smoke.3240813352
Short name T1053
Test name
Test status
Simulation time 624961079 ps
CPU time 3.39 seconds
Started Jun 09 02:13:57 PM PDT 24
Finished Jun 09 02:14:01 PM PDT 24
Peak memory 200144 kb
Host smart-88c7e70f-22ce-49db-b9d4-27d1589affc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240813352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_smoke.3240813352
Directory /workspace/7.uart_smoke/latest

Test location /workspace/coverage/default/7.uart_tx_ovrd.474125779
Short name T385
Test name
Test status
Simulation time 373203671 ps
CPU time 1.39 seconds
Started Jun 09 02:14:05 PM PDT 24
Finished Jun 09 02:14:06 PM PDT 24
Peak memory 197508 kb
Host smart-61d5aea1-ecac-4940-8745-4c65224eb6f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474125779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.474125779
Directory /workspace/7.uart_tx_ovrd/latest

Test location /workspace/coverage/default/7.uart_tx_rx.1313298003
Short name T508
Test name
Test status
Simulation time 29720172230 ps
CPU time 13.56 seconds
Started Jun 09 02:13:57 PM PDT 24
Finished Jun 09 02:14:11 PM PDT 24
Peak memory 200140 kb
Host smart-db0e8fd2-40f8-4663-8c55-fab6fd79119f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313298003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.1313298003
Directory /workspace/7.uart_tx_rx/latest

Test location /workspace/coverage/default/71.uart_fifo_reset.2816783823
Short name T922
Test name
Test status
Simulation time 36061759121 ps
CPU time 59.54 seconds
Started Jun 09 02:19:27 PM PDT 24
Finished Jun 09 02:20:26 PM PDT 24
Peak memory 200392 kb
Host smart-85a1cd2f-05b4-4535-98e1-e9a05e8f8dea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816783823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.2816783823
Directory /workspace/71.uart_fifo_reset/latest

Test location /workspace/coverage/default/71.uart_stress_all_with_rand_reset.830191883
Short name T966
Test name
Test status
Simulation time 181409830701 ps
CPU time 452.14 seconds
Started Jun 09 02:19:30 PM PDT 24
Finished Jun 09 02:27:02 PM PDT 24
Peak memory 216888 kb
Host smart-62c802d6-f834-4526-985c-2933c79b4ccb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830191883 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 71.uart_stress_all_with_rand_reset.830191883
Directory /workspace/71.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/72.uart_fifo_reset.3415272695
Short name T620
Test name
Test status
Simulation time 13239848229 ps
CPU time 23.48 seconds
Started Jun 09 02:19:40 PM PDT 24
Finished Jun 09 02:20:04 PM PDT 24
Peak memory 200300 kb
Host smart-9ac339f2-1f98-4bdc-ae13-508a7dc3cd66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415272695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.3415272695
Directory /workspace/72.uart_fifo_reset/latest

Test location /workspace/coverage/default/73.uart_fifo_reset.2441589829
Short name T936
Test name
Test status
Simulation time 68155958343 ps
CPU time 31.34 seconds
Started Jun 09 02:19:27 PM PDT 24
Finished Jun 09 02:19:58 PM PDT 24
Peak memory 200348 kb
Host smart-2a118082-19cb-4814-b3eb-805f00262c10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441589829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.2441589829
Directory /workspace/73.uart_fifo_reset/latest

Test location /workspace/coverage/default/73.uart_stress_all_with_rand_reset.2668148946
Short name T842
Test name
Test status
Simulation time 635564034695 ps
CPU time 1170.71 seconds
Started Jun 09 02:19:40 PM PDT 24
Finished Jun 09 02:39:11 PM PDT 24
Peak memory 225072 kb
Host smart-a97e3507-1cb8-4585-8fff-2d64e85fbade
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668148946 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 73.uart_stress_all_with_rand_reset.2668148946
Directory /workspace/73.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/74.uart_fifo_reset.2329935440
Short name T180
Test name
Test status
Simulation time 55344367888 ps
CPU time 23.2 seconds
Started Jun 09 02:19:32 PM PDT 24
Finished Jun 09 02:19:56 PM PDT 24
Peak memory 200416 kb
Host smart-5960b35c-8e10-4070-9e0e-0e07292d3c48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329935440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.2329935440
Directory /workspace/74.uart_fifo_reset/latest

Test location /workspace/coverage/default/75.uart_fifo_reset.3723901794
Short name T217
Test name
Test status
Simulation time 56330436167 ps
CPU time 23.94 seconds
Started Jun 09 02:19:33 PM PDT 24
Finished Jun 09 02:19:58 PM PDT 24
Peak memory 200416 kb
Host smart-166dc61f-78c6-4d65-bded-5f39948c849a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723901794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.3723901794
Directory /workspace/75.uart_fifo_reset/latest

Test location /workspace/coverage/default/77.uart_fifo_reset.582359042
Short name T1052
Test name
Test status
Simulation time 96225813600 ps
CPU time 47.65 seconds
Started Jun 09 02:19:39 PM PDT 24
Finished Jun 09 02:20:27 PM PDT 24
Peak memory 200296 kb
Host smart-d3f2e4fa-6fce-4cfe-bd0f-9be0a4eb1b89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582359042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.582359042
Directory /workspace/77.uart_fifo_reset/latest

Test location /workspace/coverage/default/78.uart_fifo_reset.1989635278
Short name T562
Test name
Test status
Simulation time 27165819492 ps
CPU time 49.03 seconds
Started Jun 09 02:19:37 PM PDT 24
Finished Jun 09 02:20:26 PM PDT 24
Peak memory 200328 kb
Host smart-9cd6605a-85cd-4f3e-ba11-3c306e86fe5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989635278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.1989635278
Directory /workspace/78.uart_fifo_reset/latest

Test location /workspace/coverage/default/79.uart_fifo_reset.708707264
Short name T918
Test name
Test status
Simulation time 101507365442 ps
CPU time 108.78 seconds
Started Jun 09 02:19:37 PM PDT 24
Finished Jun 09 02:21:26 PM PDT 24
Peak memory 200360 kb
Host smart-91fe9d88-11c0-42a8-bb21-12aaf922c87a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708707264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.708707264
Directory /workspace/79.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_alert_test.4178283367
Short name T661
Test name
Test status
Simulation time 15003216 ps
CPU time 0.56 seconds
Started Jun 09 02:14:19 PM PDT 24
Finished Jun 09 02:14:20 PM PDT 24
Peak memory 196236 kb
Host smart-cb4a08ac-58cc-4930-bb05-11da5e4130d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178283367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.4178283367
Directory /workspace/8.uart_alert_test/latest

Test location /workspace/coverage/default/8.uart_fifo_full.3490106376
Short name T981
Test name
Test status
Simulation time 67343634295 ps
CPU time 35.92 seconds
Started Jun 09 02:14:06 PM PDT 24
Finished Jun 09 02:14:43 PM PDT 24
Peak memory 200284 kb
Host smart-8c0414d4-44e9-4389-8014-d116c719a91e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490106376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.3490106376
Directory /workspace/8.uart_fifo_full/latest

Test location /workspace/coverage/default/8.uart_fifo_overflow.3826694448
Short name T658
Test name
Test status
Simulation time 40623215109 ps
CPU time 24.49 seconds
Started Jun 09 02:14:07 PM PDT 24
Finished Jun 09 02:14:32 PM PDT 24
Peak memory 200580 kb
Host smart-8f90b824-a35b-4649-bde0-5644702a91c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826694448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.3826694448
Directory /workspace/8.uart_fifo_overflow/latest

Test location /workspace/coverage/default/8.uart_fifo_reset.4108668850
Short name T618
Test name
Test status
Simulation time 216466377840 ps
CPU time 102.94 seconds
Started Jun 09 02:14:09 PM PDT 24
Finished Jun 09 02:15:52 PM PDT 24
Peak memory 200328 kb
Host smart-9d8f9aac-af15-4b99-87df-d97d2c5b4d2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108668850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.4108668850
Directory /workspace/8.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_intr.1169372208
Short name T959
Test name
Test status
Simulation time 46093873807 ps
CPU time 76.02 seconds
Started Jun 09 02:14:08 PM PDT 24
Finished Jun 09 02:15:24 PM PDT 24
Peak memory 200320 kb
Host smart-30c58435-ad53-4f23-af31-0a23fec10eab
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169372208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.1169372208
Directory /workspace/8.uart_intr/latest

Test location /workspace/coverage/default/8.uart_long_xfer_wo_dly.3686512235
Short name T416
Test name
Test status
Simulation time 63092222837 ps
CPU time 486.15 seconds
Started Jun 09 02:14:12 PM PDT 24
Finished Jun 09 02:22:18 PM PDT 24
Peak memory 200316 kb
Host smart-94290d16-2517-410c-89b3-914c0a22793a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3686512235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.3686512235
Directory /workspace/8.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/8.uart_loopback.1838607731
Short name T807
Test name
Test status
Simulation time 3931812583 ps
CPU time 8.54 seconds
Started Jun 09 02:14:12 PM PDT 24
Finished Jun 09 02:14:21 PM PDT 24
Peak memory 200196 kb
Host smart-753eea24-7bc5-4f16-8d96-21acad4530bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838607731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_loopback.1838607731
Directory /workspace/8.uart_loopback/latest

Test location /workspace/coverage/default/8.uart_perf.2313445106
Short name T960
Test name
Test status
Simulation time 13024254378 ps
CPU time 743.98 seconds
Started Jun 09 02:14:13 PM PDT 24
Finished Jun 09 02:26:37 PM PDT 24
Peak memory 200316 kb
Host smart-865c1c65-12ab-4231-9587-946d427c6ea0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2313445106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.2313445106
Directory /workspace/8.uart_perf/latest

Test location /workspace/coverage/default/8.uart_rx_oversample.1952935613
Short name T44
Test name
Test status
Simulation time 6368271213 ps
CPU time 52.11 seconds
Started Jun 09 02:14:09 PM PDT 24
Finished Jun 09 02:15:01 PM PDT 24
Peak memory 199512 kb
Host smart-290102b7-1b99-4769-9977-9eb81aabc2d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1952935613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.1952935613
Directory /workspace/8.uart_rx_oversample/latest

Test location /workspace/coverage/default/8.uart_rx_parity_err.2592197055
Short name T973
Test name
Test status
Simulation time 27923143821 ps
CPU time 12.08 seconds
Started Jun 09 02:14:11 PM PDT 24
Finished Jun 09 02:14:23 PM PDT 24
Peak memory 198476 kb
Host smart-2b24b4b8-ed2f-4bc2-9ff4-e790255f72b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592197055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.2592197055
Directory /workspace/8.uart_rx_parity_err/latest

Test location /workspace/coverage/default/8.uart_rx_start_bit_filter.2449157388
Short name T471
Test name
Test status
Simulation time 4455675046 ps
CPU time 7.13 seconds
Started Jun 09 02:14:07 PM PDT 24
Finished Jun 09 02:14:14 PM PDT 24
Peak memory 196440 kb
Host smart-304c12ea-90e2-41fd-bdfe-54e817df4ec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449157388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.2449157388
Directory /workspace/8.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/8.uart_smoke.1619463587
Short name T445
Test name
Test status
Simulation time 6038657985 ps
CPU time 7.08 seconds
Started Jun 09 02:14:07 PM PDT 24
Finished Jun 09 02:14:15 PM PDT 24
Peak memory 200108 kb
Host smart-cf5ae8e5-bc91-4d39-a086-9c1e670bd9a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619463587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_smoke.1619463587
Directory /workspace/8.uart_smoke/latest

Test location /workspace/coverage/default/8.uart_stress_all.2101391121
Short name T647
Test name
Test status
Simulation time 66978761427 ps
CPU time 49.23 seconds
Started Jun 09 02:14:11 PM PDT 24
Finished Jun 09 02:15:00 PM PDT 24
Peak memory 200424 kb
Host smart-e89d55bd-1353-44a9-bb9f-c1727ce3b83a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101391121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.2101391121
Directory /workspace/8.uart_stress_all/latest

Test location /workspace/coverage/default/8.uart_tx_ovrd.2355623625
Short name T486
Test name
Test status
Simulation time 6905994856 ps
CPU time 41.57 seconds
Started Jun 09 02:14:10 PM PDT 24
Finished Jun 09 02:14:52 PM PDT 24
Peak memory 200160 kb
Host smart-c7e9f863-8e4a-4ae5-8df5-1eff223a6834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355623625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.2355623625
Directory /workspace/8.uart_tx_ovrd/latest

Test location /workspace/coverage/default/8.uart_tx_rx.2636434395
Short name T798
Test name
Test status
Simulation time 96488443478 ps
CPU time 52.28 seconds
Started Jun 09 02:14:06 PM PDT 24
Finished Jun 09 02:14:59 PM PDT 24
Peak memory 200332 kb
Host smart-f9779f57-0aa1-48e3-b568-4f24c940d336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636434395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.2636434395
Directory /workspace/8.uart_tx_rx/latest

Test location /workspace/coverage/default/80.uart_fifo_reset.4071671746
Short name T660
Test name
Test status
Simulation time 16669183865 ps
CPU time 16.89 seconds
Started Jun 09 02:19:38 PM PDT 24
Finished Jun 09 02:19:55 PM PDT 24
Peak memory 200280 kb
Host smart-0f47f4bc-6ad6-4714-ba30-4efefe72ae5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071671746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.4071671746
Directory /workspace/80.uart_fifo_reset/latest

Test location /workspace/coverage/default/80.uart_stress_all_with_rand_reset.3394317987
Short name T35
Test name
Test status
Simulation time 53627366442 ps
CPU time 208.78 seconds
Started Jun 09 02:19:39 PM PDT 24
Finished Jun 09 02:23:08 PM PDT 24
Peak memory 208692 kb
Host smart-34d3fb90-0581-4f50-9992-4b556fb00699
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394317987 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 80.uart_stress_all_with_rand_reset.3394317987
Directory /workspace/80.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.uart_fifo_reset.1649113339
Short name T297
Test name
Test status
Simulation time 27369945246 ps
CPU time 13.93 seconds
Started Jun 09 02:19:39 PM PDT 24
Finished Jun 09 02:19:53 PM PDT 24
Peak memory 200420 kb
Host smart-85e27d5f-374f-4484-8a60-06ee2526213b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649113339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.1649113339
Directory /workspace/82.uart_fifo_reset/latest

Test location /workspace/coverage/default/83.uart_fifo_reset.4082992119
Short name T138
Test name
Test status
Simulation time 138084768241 ps
CPU time 181.24 seconds
Started Jun 09 02:19:38 PM PDT 24
Finished Jun 09 02:22:39 PM PDT 24
Peak memory 200280 kb
Host smart-6a10a6e7-0028-468e-9891-50c1c87c7803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082992119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.4082992119
Directory /workspace/83.uart_fifo_reset/latest

Test location /workspace/coverage/default/83.uart_stress_all_with_rand_reset.626190473
Short name T748
Test name
Test status
Simulation time 67873992471 ps
CPU time 430.74 seconds
Started Jun 09 02:19:39 PM PDT 24
Finished Jun 09 02:26:50 PM PDT 24
Peak memory 216304 kb
Host smart-a8116dfe-1474-4f7d-9185-23a3a12e23f5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626190473 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 83.uart_stress_all_with_rand_reset.626190473
Directory /workspace/83.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/84.uart_fifo_reset.4110001828
Short name T11
Test name
Test status
Simulation time 41809904468 ps
CPU time 37.72 seconds
Started Jun 09 02:19:40 PM PDT 24
Finished Jun 09 02:20:18 PM PDT 24
Peak memory 200324 kb
Host smart-ccb40e66-fdeb-4563-b604-3e142ff33f3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110001828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.4110001828
Directory /workspace/84.uart_fifo_reset/latest

Test location /workspace/coverage/default/85.uart_fifo_reset.1967709272
Short name T597
Test name
Test status
Simulation time 136821110571 ps
CPU time 195.6 seconds
Started Jun 09 02:19:40 PM PDT 24
Finished Jun 09 02:22:56 PM PDT 24
Peak memory 200324 kb
Host smart-835efb4e-e71b-4f63-ae49-151e41ecf19d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967709272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.1967709272
Directory /workspace/85.uart_fifo_reset/latest

Test location /workspace/coverage/default/86.uart_fifo_reset.1797801448
Short name T987
Test name
Test status
Simulation time 24715203793 ps
CPU time 50.32 seconds
Started Jun 09 02:19:41 PM PDT 24
Finished Jun 09 02:20:32 PM PDT 24
Peak memory 200404 kb
Host smart-fbf54f6f-5771-4c2d-94a2-b5ceeb9dc8b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797801448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.1797801448
Directory /workspace/86.uart_fifo_reset/latest

Test location /workspace/coverage/default/86.uart_stress_all_with_rand_reset.408511848
Short name T851
Test name
Test status
Simulation time 47284921269 ps
CPU time 830.48 seconds
Started Jun 09 02:19:41 PM PDT 24
Finished Jun 09 02:33:32 PM PDT 24
Peak memory 216876 kb
Host smart-612fd97a-5904-487d-b142-1dda5528b098
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408511848 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 86.uart_stress_all_with_rand_reset.408511848
Directory /workspace/86.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/87.uart_fifo_reset.2777862797
Short name T627
Test name
Test status
Simulation time 78509901458 ps
CPU time 127.59 seconds
Started Jun 09 02:19:42 PM PDT 24
Finished Jun 09 02:21:50 PM PDT 24
Peak memory 200320 kb
Host smart-e1b89a40-56de-4306-b1cd-0c0cd067e8ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777862797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.2777862797
Directory /workspace/87.uart_fifo_reset/latest

Test location /workspace/coverage/default/88.uart_fifo_reset.1425724521
Short name T489
Test name
Test status
Simulation time 276262878420 ps
CPU time 99.66 seconds
Started Jun 09 02:19:41 PM PDT 24
Finished Jun 09 02:21:21 PM PDT 24
Peak memory 200368 kb
Host smart-ed90e01f-9f59-43f8-8044-5df57a6f50f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425724521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.1425724521
Directory /workspace/88.uart_fifo_reset/latest

Test location /workspace/coverage/default/88.uart_stress_all_with_rand_reset.2302391910
Short name T102
Test name
Test status
Simulation time 124203999856 ps
CPU time 753.93 seconds
Started Jun 09 02:19:41 PM PDT 24
Finished Jun 09 02:32:15 PM PDT 24
Peak memory 216836 kb
Host smart-a3467f13-b3a5-4294-b726-8bab074eb205
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302391910 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 88.uart_stress_all_with_rand_reset.2302391910
Directory /workspace/88.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.uart_fifo_reset.2090842309
Short name T568
Test name
Test status
Simulation time 94894377011 ps
CPU time 135.61 seconds
Started Jun 09 02:19:41 PM PDT 24
Finished Jun 09 02:21:57 PM PDT 24
Peak memory 200556 kb
Host smart-2c64fcdb-4bd0-4f37-a212-a7d29c5acbea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090842309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.2090842309
Directory /workspace/89.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_alert_test.1564506317
Short name T781
Test name
Test status
Simulation time 15241545 ps
CPU time 0.56 seconds
Started Jun 09 02:14:23 PM PDT 24
Finished Jun 09 02:14:24 PM PDT 24
Peak memory 195776 kb
Host smart-290387e1-f788-4e05-a7b3-69ecb978352b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564506317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.1564506317
Directory /workspace/9.uart_alert_test/latest

Test location /workspace/coverage/default/9.uart_fifo_full.832151543
Short name T313
Test name
Test status
Simulation time 68244721510 ps
CPU time 58.22 seconds
Started Jun 09 02:14:18 PM PDT 24
Finished Jun 09 02:15:16 PM PDT 24
Peak memory 200380 kb
Host smart-828b05d7-af29-4889-add9-a3e404e811b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832151543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.832151543
Directory /workspace/9.uart_fifo_full/latest

Test location /workspace/coverage/default/9.uart_fifo_overflow.2487089176
Short name T263
Test name
Test status
Simulation time 24464671438 ps
CPU time 36.44 seconds
Started Jun 09 02:14:16 PM PDT 24
Finished Jun 09 02:14:53 PM PDT 24
Peak memory 200168 kb
Host smart-e0908e9d-a9d9-4aee-a7e2-57ba19867646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487089176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.2487089176
Directory /workspace/9.uart_fifo_overflow/latest

Test location /workspace/coverage/default/9.uart_fifo_reset.4064623480
Short name T333
Test name
Test status
Simulation time 10388739330 ps
CPU time 22.71 seconds
Started Jun 09 02:14:18 PM PDT 24
Finished Jun 09 02:14:41 PM PDT 24
Peak memory 200348 kb
Host smart-f4d49fb6-caf4-4cda-8915-513d4cc3f971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064623480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.4064623480
Directory /workspace/9.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_intr.4138205561
Short name T424
Test name
Test status
Simulation time 50904432492 ps
CPU time 8.52 seconds
Started Jun 09 02:14:20 PM PDT 24
Finished Jun 09 02:14:28 PM PDT 24
Peak memory 200476 kb
Host smart-6f0fe266-e841-4283-b790-e9806e66446f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138205561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.4138205561
Directory /workspace/9.uart_intr/latest

Test location /workspace/coverage/default/9.uart_long_xfer_wo_dly.2110742785
Short name T1084
Test name
Test status
Simulation time 63890725377 ps
CPU time 679.13 seconds
Started Jun 09 02:14:21 PM PDT 24
Finished Jun 09 02:25:40 PM PDT 24
Peak memory 200320 kb
Host smart-24025ab0-f599-499c-84ec-53758e08161e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2110742785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.2110742785
Directory /workspace/9.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/9.uart_loopback.3270930074
Short name T467
Test name
Test status
Simulation time 6679970036 ps
CPU time 6.13 seconds
Started Jun 09 02:14:25 PM PDT 24
Finished Jun 09 02:14:31 PM PDT 24
Peak memory 199608 kb
Host smart-ccda166d-35e5-40d7-a300-f2f2b243ce02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270930074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_loopback.3270930074
Directory /workspace/9.uart_loopback/latest

Test location /workspace/coverage/default/9.uart_noise_filter.3734195145
Short name T602
Test name
Test status
Simulation time 47497454948 ps
CPU time 23.21 seconds
Started Jun 09 02:14:19 PM PDT 24
Finished Jun 09 02:14:42 PM PDT 24
Peak memory 200388 kb
Host smart-27ec2c70-b2ac-4a55-b2bc-2f172325c1c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734195145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.3734195145
Directory /workspace/9.uart_noise_filter/latest

Test location /workspace/coverage/default/9.uart_perf.1921096462
Short name T515
Test name
Test status
Simulation time 7135884041 ps
CPU time 86.58 seconds
Started Jun 09 02:14:23 PM PDT 24
Finished Jun 09 02:15:50 PM PDT 24
Peak memory 200276 kb
Host smart-0b5c6a63-3889-4768-b2bb-22e36e1dbdf7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1921096462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.1921096462
Directory /workspace/9.uart_perf/latest

Test location /workspace/coverage/default/9.uart_rx_oversample.1347471441
Short name T596
Test name
Test status
Simulation time 4931618950 ps
CPU time 47.19 seconds
Started Jun 09 02:14:19 PM PDT 24
Finished Jun 09 02:15:06 PM PDT 24
Peak memory 199508 kb
Host smart-949a129a-ee0e-4fba-aa58-a3cb79dd0b18
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1347471441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.1347471441
Directory /workspace/9.uart_rx_oversample/latest

Test location /workspace/coverage/default/9.uart_rx_parity_err.1532556746
Short name T671
Test name
Test status
Simulation time 86523533071 ps
CPU time 137.68 seconds
Started Jun 09 02:14:24 PM PDT 24
Finished Jun 09 02:16:41 PM PDT 24
Peak memory 200392 kb
Host smart-b5ed87b9-3af4-4286-a9ca-31f22c783ecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532556746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.1532556746
Directory /workspace/9.uart_rx_parity_err/latest

Test location /workspace/coverage/default/9.uart_rx_start_bit_filter.1189349699
Short name T873
Test name
Test status
Simulation time 4165442793 ps
CPU time 2.11 seconds
Started Jun 09 02:14:16 PM PDT 24
Finished Jun 09 02:14:18 PM PDT 24
Peak memory 196360 kb
Host smart-eb78245b-5956-4169-a886-cf0a440bb3c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189349699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.1189349699
Directory /workspace/9.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/9.uart_smoke.104308258
Short name T1022
Test name
Test status
Simulation time 5620106524 ps
CPU time 4.81 seconds
Started Jun 09 02:14:17 PM PDT 24
Finished Jun 09 02:14:23 PM PDT 24
Peak memory 199632 kb
Host smart-2426d3a1-28cd-43da-a706-4791f2e4617a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104308258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_smoke.104308258
Directory /workspace/9.uart_smoke/latest

Test location /workspace/coverage/default/9.uart_stress_all.727823452
Short name T112
Test name
Test status
Simulation time 225932271839 ps
CPU time 258.22 seconds
Started Jun 09 02:14:21 PM PDT 24
Finished Jun 09 02:18:39 PM PDT 24
Peak memory 200312 kb
Host smart-6d66212a-8a8f-4d98-a15b-1f379cd9979e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727823452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.727823452
Directory /workspace/9.uart_stress_all/latest

Test location /workspace/coverage/default/9.uart_tx_ovrd.4259833644
Short name T890
Test name
Test status
Simulation time 4338017468 ps
CPU time 1.56 seconds
Started Jun 09 02:14:21 PM PDT 24
Finished Jun 09 02:14:22 PM PDT 24
Peak memory 200240 kb
Host smart-06d8f932-67e3-4429-ae9b-9cb78b71d9aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259833644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.4259833644
Directory /workspace/9.uart_tx_ovrd/latest

Test location /workspace/coverage/default/9.uart_tx_rx.214054288
Short name T794
Test name
Test status
Simulation time 182757978669 ps
CPU time 76.12 seconds
Started Jun 09 02:14:17 PM PDT 24
Finished Jun 09 02:15:33 PM PDT 24
Peak memory 200368 kb
Host smart-276e75e8-bf94-464d-b41e-a6263d25e1f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214054288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.214054288
Directory /workspace/9.uart_tx_rx/latest

Test location /workspace/coverage/default/90.uart_fifo_reset.2867897452
Short name T762
Test name
Test status
Simulation time 24200432724 ps
CPU time 45.43 seconds
Started Jun 09 02:19:46 PM PDT 24
Finished Jun 09 02:20:32 PM PDT 24
Peak memory 200288 kb
Host smart-ad3bc3ce-17ca-4c58-ac00-9056c26bf85c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867897452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.2867897452
Directory /workspace/90.uart_fifo_reset/latest

Test location /workspace/coverage/default/91.uart_fifo_reset.3470123949
Short name T1027
Test name
Test status
Simulation time 8808300720 ps
CPU time 15.81 seconds
Started Jun 09 02:19:46 PM PDT 24
Finished Jun 09 02:20:02 PM PDT 24
Peak memory 200328 kb
Host smart-dc554b14-de41-43ac-97e4-3a0876d29ca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470123949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.3470123949
Directory /workspace/91.uart_fifo_reset/latest

Test location /workspace/coverage/default/92.uart_fifo_reset.4037886397
Short name T225
Test name
Test status
Simulation time 219792613978 ps
CPU time 58.22 seconds
Started Jun 09 02:19:48 PM PDT 24
Finished Jun 09 02:20:46 PM PDT 24
Peak memory 200288 kb
Host smart-445d53bb-1c23-46fb-b200-e07fe49125d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037886397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.4037886397
Directory /workspace/92.uart_fifo_reset/latest

Test location /workspace/coverage/default/93.uart_fifo_reset.3488242360
Short name T252
Test name
Test status
Simulation time 64648785004 ps
CPU time 30.88 seconds
Started Jun 09 02:19:45 PM PDT 24
Finished Jun 09 02:20:16 PM PDT 24
Peak memory 200376 kb
Host smart-dd462477-a531-4c4b-95f5-b05f75ce0002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488242360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.3488242360
Directory /workspace/93.uart_fifo_reset/latest

Test location /workspace/coverage/default/94.uart_fifo_reset.1447745682
Short name T724
Test name
Test status
Simulation time 68704723373 ps
CPU time 51.94 seconds
Started Jun 09 02:19:47 PM PDT 24
Finished Jun 09 02:20:40 PM PDT 24
Peak memory 200416 kb
Host smart-e398b0a2-205c-4be4-aa5e-155c0d3bed62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447745682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.1447745682
Directory /workspace/94.uart_fifo_reset/latest

Test location /workspace/coverage/default/94.uart_stress_all_with_rand_reset.3207090531
Short name T1073
Test name
Test status
Simulation time 91060321310 ps
CPU time 1860.84 seconds
Started Jun 09 02:19:47 PM PDT 24
Finished Jun 09 02:50:49 PM PDT 24
Peak memory 225100 kb
Host smart-a26c6c0c-1e01-4c14-9967-31da397cba40
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207090531 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 94.uart_stress_all_with_rand_reset.3207090531
Directory /workspace/94.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/95.uart_fifo_reset.3277261580
Short name T155
Test name
Test status
Simulation time 93540043977 ps
CPU time 31.31 seconds
Started Jun 09 02:19:47 PM PDT 24
Finished Jun 09 02:20:19 PM PDT 24
Peak memory 200312 kb
Host smart-9ec8f625-6c99-4fda-b3c4-d7925d903097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277261580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.3277261580
Directory /workspace/95.uart_fifo_reset/latest

Test location /workspace/coverage/default/95.uart_stress_all_with_rand_reset.3633060398
Short name T863
Test name
Test status
Simulation time 16261408610 ps
CPU time 92.22 seconds
Started Jun 09 02:19:46 PM PDT 24
Finished Jun 09 02:21:18 PM PDT 24
Peak memory 215900 kb
Host smart-8e08d81b-4eef-4c2a-adf5-a8024f74beaf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633060398 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 95.uart_stress_all_with_rand_reset.3633060398
Directory /workspace/95.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/96.uart_fifo_reset.3969798184
Short name T670
Test name
Test status
Simulation time 70905488392 ps
CPU time 33.79 seconds
Started Jun 09 02:19:47 PM PDT 24
Finished Jun 09 02:20:21 PM PDT 24
Peak memory 200284 kb
Host smart-102054e3-56cf-4a1c-925b-4ab66d030009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969798184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.3969798184
Directory /workspace/96.uart_fifo_reset/latest

Test location /workspace/coverage/default/97.uart_fifo_reset.365117399
Short name T713
Test name
Test status
Simulation time 34784176662 ps
CPU time 17.43 seconds
Started Jun 09 02:19:53 PM PDT 24
Finished Jun 09 02:20:11 PM PDT 24
Peak memory 200388 kb
Host smart-30ece33f-63ee-4cf8-a118-26510e5d9df4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365117399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.365117399
Directory /workspace/97.uart_fifo_reset/latest

Test location /workspace/coverage/default/97.uart_stress_all_with_rand_reset.4179118473
Short name T710
Test name
Test status
Simulation time 39833757894 ps
CPU time 470.35 seconds
Started Jun 09 02:19:52 PM PDT 24
Finished Jun 09 02:27:43 PM PDT 24
Peak memory 216912 kb
Host smart-3a97cadb-a18f-403f-b6eb-d9366d28b4a1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179118473 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 97.uart_stress_all_with_rand_reset.4179118473
Directory /workspace/97.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/98.uart_fifo_reset.2651618468
Short name T719
Test name
Test status
Simulation time 142075593312 ps
CPU time 178 seconds
Started Jun 09 02:19:50 PM PDT 24
Finished Jun 09 02:22:48 PM PDT 24
Peak memory 200332 kb
Host smart-01f3f672-fdc1-46b8-89df-05bdb5643628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651618468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.2651618468
Directory /workspace/98.uart_fifo_reset/latest

Test location /workspace/coverage/default/99.uart_fifo_reset.1778836259
Short name T902
Test name
Test status
Simulation time 119861966077 ps
CPU time 159.3 seconds
Started Jun 09 02:19:54 PM PDT 24
Finished Jun 09 02:22:34 PM PDT 24
Peak memory 200416 kb
Host smart-2f9aada2-d9ad-4dc8-88ec-5ce1e96c6965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778836259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.1778836259
Directory /workspace/99.uart_fifo_reset/latest

Test location /workspace/coverage/default/99.uart_stress_all_with_rand_reset.3605127906
Short name T581
Test name
Test status
Simulation time 44061046437 ps
CPU time 173.06 seconds
Started Jun 09 02:19:53 PM PDT 24
Finished Jun 09 02:22:46 PM PDT 24
Peak memory 208900 kb
Host smart-b49992d3-ef27-4dc3-b3bb-cf534c00090f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605127906 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 99.uart_stress_all_with_rand_reset.3605127906
Directory /workspace/99.uart_stress_all_with_rand_reset/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%