Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	84027	1			T1	3		T2	7		T3	114
all_values[1]	84027	1			T1	3		T2	7		T3	114
all_values[2]	84027	1			T1	3		T2	7		T3	114
all_values[3]	84027	1			T1	3		T2	7		T3	114
all_values[4]	84027	1			T1	3		T2	7		T3	114
all_values[5]	84027	1			T1	3		T2	7		T3	114
all_values[6]	84027	1			T1	3		T2	7		T3	114
all_values[7]	84027	1			T1	3		T2	7		T3	114
all_values[8]	84027	1			T1	3		T2	7		T3	114

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

384007

1

T1

18

T2

43

T3

362

auto[1]

372236

1

T1

9

T2

20

T3

664

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

691985

1

T1

21

T2

47

T3

999

auto[1]

64258

1

T1

6

T2

16

T3

27

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	24617	1			T4	111		T7	32		T21	9
all_values[0]	auto[0]	auto[1]	15670	1			T2	1		T3	8		T4	380
all_values[0]	auto[1]	auto[0]	27817	1			T1	1		T3	102		T4	456
all_values[0]	auto[1]	auto[1]	15923	1			T1	2		T2	6		T3	4
all_values[1]	auto[0]	auto[0]	43074	1			T1	3		T2	7		T3	11
all_values[1]	auto[0]	auto[1]	1204	1			T12	4		T13	9		T42	3
all_values[1]	auto[1]	auto[0]	38398	1			T3	103		T4	181		T6	10
all_values[1]	auto[1]	auto[1]	1351	1			T6	2		T45	31		T13	13
all_values[2]	auto[0]	auto[0]	42430	1			T1	1		T2	4		T3	7
all_values[2]	auto[0]	auto[1]	2249	1			T1	2		T2	1		T3	3
all_values[2]	auto[1]	auto[0]	37430	1			T2	1		T3	104		T4	696
all_values[2]	auto[1]	auto[1]	1918	1			T2	1		T4	15		T6	3
all_values[3]	auto[0]	auto[0]	38861	1			T1	3		T2	5		T3	101
all_values[3]	auto[0]	auto[1]	199	1			T6	1		T7	5		T10	2
all_values[3]	auto[1]	auto[0]	44745	1			T2	2		T3	13		T4	818
all_values[3]	auto[1]	auto[1]	222	1			T13	4		T19	2		T32	4
all_values[4]	auto[0]	auto[0]	42204	1			T1	3		T2	5		T3	101
all_values[4]	auto[0]	auto[1]	336	1			T13	3		T15	11		T19	8
all_values[4]	auto[1]	auto[0]	41189	1			T2	2		T3	13		T4	639
all_values[4]	auto[1]	auto[1]	298	1			T12	11		T13	11		T19	3
all_values[5]	auto[0]	auto[0]	46745	1			T2	5		T3	109		T4	665
all_values[5]	auto[0]	auto[1]	116	1			T19	3		T132	2		T133	1
all_values[5]	auto[1]	auto[0]	37069	1			T1	3		T2	2		T3	5
all_values[5]	auto[1]	auto[1]	97	1			T13	2		T19	1		T132	3
all_values[6]	auto[0]	auto[0]	38755	1			T1	3		T2	5		T3	5
all_values[6]	auto[0]	auto[1]	118	1			T13	3		T19	4		T90	5
all_values[6]	auto[1]	auto[0]	45049	1			T2	2		T3	109		T4	838
all_values[6]	auto[1]	auto[1]	105	1			T19	2		T90	1		T132	3
all_values[7]	auto[0]	auto[0]	43587	1			T1	3		T2	5		T3	5
all_values[7]	auto[0]	auto[1]	299	1			T13	10		T16	2		T19	3
all_values[7]	auto[1]	auto[0]	39848	1			T2	2		T3	109		T4	328
all_values[7]	auto[1]	auto[1]	293	1			T13	7		T16	2		T15	4
all_values[8]	auto[0]	auto[0]	30852	1			T3	3		T4	230		T6	2
all_values[8]	auto[0]	auto[1]	12691	1			T2	5		T3	9		T4	3
all_values[8]	auto[1]	auto[0]	29315	1			T1	1		T3	99		T4	445
all_values[8]	auto[1]	auto[1]	11169	1			T1	2		T2	2		T3	3