Unified Coverage Report :: Group :: uart_agent_pkg::uart_agent_cov::uart_reset_cg

Group : uart_agent_pkg::uart_agent_cov::uart_reset_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_agent_0.1/uart_agent_cov.sv

---

Summary for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	22	0	22	100.00

Variables for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	0
cp_rst_pos	11	0	11	100.00	100	1	1	0

Crosses for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
uart_reset_cg_cc	22	0	22	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[UartTx]

2232

1

T1

1

T2

1

T3

1

auto[UartRx]

2232

1

T1

1

T2

1

T3

1

---

Summary for Variable cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_rst_pos

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4015	1			T1	2		T2	2		T3	2
values[1]	38	1			T13	3		T19	1		T31	2
values[2]	37	1			T31	2		T32	1		T33	1
values[3]	45	1			T22	2		T31	1		T33	1
values[4]	36	1			T19	1		T30	1		T34	1
values[5]	36	1			T13	1		T22	1		T29	2
values[6]	38	1			T13	2		T22	2		T31	1
values[7]	40	1			T22	1		T19	1		T33	1
values[8]	44	1			T13	2		T22	1		T31	1
values[9]	62	1			T13	3		T22	1		T29	2
values[10]	52	1			T13	1		T30	1		T34	3

---

Summary for Cross uart_reset_cg_cc

Samples crossed: cp_dir cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	22	0	22	100.00

Automatically Generated Cross Bins for uart_reset_cg_cc

Bins

cp_dir	cp_rst_pos	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[UartTx]	values[0]	2062	1			T1	1		T2	1		T3	1
auto[UartTx]	values[1]	18	1			T13	1		T19	1		T31	2
auto[UartTx]	values[2]	10	1			T33	1		T134	1		T223	1
auto[UartTx]	values[3]	21	1			T22	1		T34	1		T114	1
auto[UartTx]	values[4]	14	1			T30	1		T57	1		T118	2
auto[UartTx]	values[5]	16	1			T57	1		T345	1		T58	1
auto[UartTx]	values[6]	12	1			T13	1		T22	1		T32	1
auto[UartTx]	values[7]	14	1			T33	1		T34	1		T35	1
auto[UartTx]	values[8]	20	1			T13	1		T22	1		T31	1
auto[UartTx]	values[9]	20	1			T22	1		T30	1		T117	1
auto[UartTx]	values[10]	18	1			T34	1		T113	1		T134	1
auto[UartRx]	values[0]	1953	1			T1	1		T2	1		T3	1
auto[UartRx]	values[1]	20	1			T13	2		T32	1		T114	1
auto[UartRx]	values[2]	27	1			T31	2		T32	1		T34	1
auto[UartRx]	values[3]	24	1			T22	1		T31	1		T33	1
auto[UartRx]	values[4]	22	1			T19	1		T34	1		T115	1
auto[UartRx]	values[5]	20	1			T13	1		T22	1		T29	2
auto[UartRx]	values[6]	26	1			T13	1		T22	1		T31	1
auto[UartRx]	values[7]	26	1			T22	1		T19	1		T113	1
auto[UartRx]	values[8]	24	1			T13	1		T114	1		T133	1
auto[UartRx]	values[9]	42	1			T13	3		T29	2		T31	1
auto[UartRx]	values[10]	34	1			T13	1		T30	1		T34	2