Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	2016	1			T2	1		T3	1		T5	1
auto[BaudRate115200]	1433	1			T2	1		T4	2		T6	1
auto[BaudRate230400]	1476	1			T1	1		T3	1		T5	1
auto[BaudRate128Kbps]	1557	1			T3	2		T8	1		T9	9
auto[BaudRate256Kbps]	1626	1			T1	2		T4	2		T6	1
auto[BaudRate1Mbps]	1443	1			T1	1		T2	2		T4	4
auto[BaudRate1p5Mbps]	1152	1			T1	1		T2	1		T3	1

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Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	860	1			T36	5		T14	16		T274	2
freqs[25]	1079	1			T5	2		T40	1		T42	10
freqs[48]	364	1			T1	5		T41	8		T187	6
freqs[50]	609	1			T253	7		T141	7		T30	15
freqs[100]	1072	1			T2	5		T45	7		T37	9

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Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	194	1			T36	1		T14	16		T32	1
auto[BaudRate9600]	freqs[25]	221	1			T5	1		T42	5		T18	1
auto[BaudRate9600]	freqs[48]	31	1			T187	1		T29	1		T52	1
auto[BaudRate9600]	freqs[50]	111	1			T253	1		T141	1		T30	3
auto[BaudRate9600]	freqs[100]	136	1			T2	1		T37	1		T15	4
auto[BaudRate115200]	freqs[24]	122	1			T32	4		T68	3		T254	4
auto[BaudRate115200]	freqs[25]	136	1			T165	1		T66	1		T189	2
auto[BaudRate115200]	freqs[48]	42	1			T52	1		T33	3		T301	1
auto[BaudRate115200]	freqs[50]	83	1			T253	2		T30	2		T259	1
auto[BaudRate115200]	freqs[100]	121	1			T2	1		T45	2		T37	1
auto[BaudRate230400]	freqs[24]	90	1			T274	1		T32	3		T181	1
auto[BaudRate230400]	freqs[25]	165	1			T5	1		T40	1		T42	1
auto[BaudRate230400]	freqs[48]	52	1			T1	1		T187	2		T29	1
auto[BaudRate230400]	freqs[50]	83	1			T253	1		T141	1		T30	2
auto[BaudRate230400]	freqs[100]	172	1			T45	1		T37	3		T15	3
auto[BaudRate128Kbps]	freqs[24]	110	1			T36	1		T32	2		T68	1
auto[BaudRate128Kbps]	freqs[25]	132	1			T66	2		T346	3		T131	1
auto[BaudRate128Kbps]	freqs[48]	45	1			T187	2		T29	3		T52	2
auto[BaudRate128Kbps]	freqs[50]	87	1			T253	1		T141	1		T30	3
auto[BaudRate128Kbps]	freqs[100]	166	1			T45	1		T304	1		T15	10
auto[BaudRate256Kbps]	freqs[24]	126	1			T36	1		T274	1		T32	2
auto[BaudRate256Kbps]	freqs[25]	164	1			T42	2		T18	1		T56	1
auto[BaudRate256Kbps]	freqs[48]	67	1			T1	2		T41	5		T187	1
auto[BaudRate256Kbps]	freqs[50]	93	1			T253	1		T141	1		T30	2
auto[BaudRate256Kbps]	freqs[100]	160	1			T37	3		T15	7		T139	2
auto[BaudRate1Mbps]	freqs[24]	136	1			T36	2		T32	2		T68	2
auto[BaudRate1Mbps]	freqs[25]	164	1			T42	1		T56	2		T165	3
auto[BaudRate1Mbps]	freqs[48]	74	1			T1	1		T41	2		T29	4
auto[BaudRate1Mbps]	freqs[50]	62	1			T253	1		T141	1		T30	1
auto[BaudRate1Mbps]	freqs[100]	145	1			T2	2		T45	2		T304	1
auto[BaudRate1p5Mbps]	freqs[25]	97	1			T42	1		T302	2		T346	3
auto[BaudRate1p5Mbps]	freqs[48]	53	1			T1	1		T41	1		T29	5
auto[BaudRate1p5Mbps]	freqs[50]	90	1			T141	2		T30	2		T259	1
auto[BaudRate1p5Mbps]	freqs[100]	172	1			T2	1		T45	1		T37	1

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded