Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::rx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::rx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.43	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	67	0	67	100.00
Crosses	130	9	121	93.08

Variables for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	65	0	65	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
rx_fifo_level_cg_cc	130	9	121	93.08	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	23756747	1			T1	26		T2	24		T3	288
all_levels[1]	181660	1			T2	2		T4	235		T6	7
all_levels[2]	2153	1			T6	2		T7	9		T8	1
all_levels[3]	873	1			T6	3		T7	5		T8	2
all_levels[4]	616	1			T1	2		T7	1		T45	5
all_levels[5]	471	1			T8	1		T45	5		T46	3
all_levels[6]	336	1			T1	1		T6	1		T45	1
all_levels[7]	265	1			T7	2		T45	2		T89	1
all_levels[8]	238	1			T8	1		T10	1		T45	3
all_levels[9]	210	1			T6	1		T8	2		T45	1
all_levels[10]	174	1			T8	1		T21	1		T45	1
all_levels[11]	153	1			T45	3		T88	1		T37	1
all_levels[12]	146	1			T2	2		T10	1		T45	2
all_levels[13]	138	1			T8	1		T10	2		T21	1
all_levels[14]	111	1			T7	1		T45	1		T13	2
all_levels[15]	101	1			T1	1		T45	4		T13	1
all_levels[16]	93	1			T45	2		T37	1		T30	1
all_levels[17]	93	1			T45	2		T43	1		T44	1
all_levels[18]	72	1			T45	1		T43	1		T22	1
all_levels[19]	65	1			T45	1		T16	1		T129	1
all_levels[20]	78	1			T89	1		T37	1		T22	1
all_levels[21]	59	1			T50	2		T52	1		T137	1
all_levels[22]	70	1			T138	1		T139	1		T127	1
all_levels[23]	52	1			T1	1		T10	1		T45	1
all_levels[24]	61	1			T1	1		T89	1		T50	1
all_levels[25]	50	1			T88	1		T139	2		T128	1
all_levels[26]	38	1			T45	2		T13	4		T37	1
all_levels[27]	38	1			T89	4		T36	1		T140	1
all_levels[28]	31	1			T139	1		T56	4		T137	1
all_levels[29]	37	1			T16	1		T22	1		T129	1
all_levels[30]	35	1			T141	3		T129	1		T67	1
all_levels[31]	25	1			T16	1		T142	1		T143	1
all_levels[32]	21	1			T139	1		T120	3		T54	1
all_levels[33]	29	1			T13	1		T66	1		T144	1
all_levels[34]	25	1			T7	1		T88	1		T145	1
all_levels[35]	20	1			T50	1		T35	1		T145	1
all_levels[36]	15	1			T32	1		T54	1		T146	1
all_levels[37]	16	1			T146	1		T147	1		T148	2
all_levels[38]	18	1			T132	1		T149	1		T150	1
all_levels[39]	22	1			T129	1		T151	1		T114	1
all_levels[40]	12	1			T137	2		T132	1		T152	1
all_levels[41]	15	1			T7	1		T153	1		T154	2
all_levels[42]	18	1			T155	1		T156	2		T143	2
all_levels[43]	12	1			T6	2		T29	1		T155	1
all_levels[44]	13	1			T157	1		T116	1		T158	1
all_levels[45]	20	1			T132	1		T159	6		T133	1
all_levels[46]	7	1			T42	1		T155	1		T160	1
all_levels[47]	16	1			T161	1		T152	1		T162	1
all_levels[48]	7	1			T163	1		T158	1		T164	2
all_levels[49]	12	1			T7	1		T141	2		T165	1
all_levels[50]	13	1			T166	1		T167	3		T168	3
all_levels[51]	10	1			T163	1		T161	1		T133	1
all_levels[52]	13	1			T42	1		T68	1		T169	1
all_levels[53]	16	1			T129	1		T53	1		T170	1
all_levels[54]	9	1			T170	1		T158	1		T171	1
all_levels[55]	7	1			T132	1		T172	1		T171	1
all_levels[56]	11	1			T170	1		T156	1		T173	1
all_levels[57]	8	1			T161	1		T174	1		T175	1
all_levels[58]	3	1			T176	1		T177	1		T178	1
all_levels[59]	5	1			T179	1		T161	1		T180	1
all_levels[60]	9	1			T181	1		T182	1		T183	1
all_levels[61]	1	1			T184	1		-	-		-	-
all_levels[62]	5	1			T109	1		T185	1		T186	1
all_levels[63]	13	1			T181	3		T166	1		T169	1
all_levels[64]	80	1			T7	1		T10	1		T89	1

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23941723

1

T1

32

T2

24

T3

288

auto[1]

4067

1

T2

4

T6

8

T7

8

---

Summary for Cross rx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	9	121	93.08	9

Automatically Generated Cross Bins for rx_fifo_level_cg_cc

Uncovered bins

cp_lvl	cp_rst	COUNT	AT LEAST	NUMBER	STATUS
[all_levels[29]]	[auto[1]]	0	1	1
[all_levels[36]]	[auto[1]]	0	1	1
[all_levels[46]]	[auto[1]]	0	1	1
[all_levels[51]]	[auto[1]]	0	1	1
[all_levels[56]]	[auto[1]]	0	1	1
[all_levels[58] , all_levels[59] , all_levels[60] , all_levels[61]]	[auto[1]]	--	--	4

Covered bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	23753162	1			T1	26		T2	21		T3	288
all_levels[0]	auto[1]	3585	1			T2	3		T6	6		T7	8
all_levels[1]	auto[0]	181572	1			T2	2		T4	235		T6	7
all_levels[1]	auto[1]	88	1			T89	1		T141	1		T139	1
all_levels[2]	auto[0]	2119	1			T6	2		T7	9		T8	1
all_levels[2]	auto[1]	34	1			T43	1		T187	1		T128	1
all_levels[3]	auto[0]	838	1			T6	2		T7	5		T8	2
all_levels[3]	auto[1]	35	1			T6	1		T120	1		T137	1
all_levels[4]	auto[0]	596	1			T1	2		T7	1		T45	5
all_levels[4]	auto[1]	20	1			T43	1		T137	1		T188	2
all_levels[5]	auto[0]	452	1			T8	1		T45	5		T46	3
all_levels[5]	auto[1]	19	1			T189	1		T190	1		T191	1
all_levels[6]	auto[0]	326	1			T1	1		T6	1		T45	1
all_levels[6]	auto[1]	10	1			T146	1		T156	1		T192	2
all_levels[7]	auto[0]	252	1			T7	2		T45	2		T89	1
all_levels[7]	auto[1]	13	1			T42	1		T193	1		T194	3
all_levels[8]	auto[0]	217	1			T8	1		T10	1		T45	3
all_levels[8]	auto[1]	21	1			T36	1		T44	5		T195	2
all_levels[9]	auto[0]	194	1			T6	1		T8	2		T45	1
all_levels[9]	auto[1]	16	1			T196	2		T194	2		T197	1
all_levels[10]	auto[0]	161	1			T8	1		T21	1		T45	1
all_levels[10]	auto[1]	13	1			T198	1		T150	1		T199	1
all_levels[11]	auto[0]	134	1			T45	3		T88	1		T37	1
all_levels[11]	auto[1]	19	1			T119	7		T200	2		T173	2
all_levels[12]	auto[0]	130	1			T2	1		T10	1		T45	2
all_levels[12]	auto[1]	16	1			T2	1		T35	1		T201	6
all_levels[13]	auto[0]	130	1			T8	1		T10	1		T21	1
all_levels[13]	auto[1]	8	1			T10	1		T193	2		T172	1
all_levels[14]	auto[0]	104	1			T7	1		T45	1		T13	2
all_levels[14]	auto[1]	7	1			T202	1		T203	1		T204	2
all_levels[15]	auto[0]	90	1			T1	1		T45	4		T13	1
all_levels[15]	auto[1]	11	1			T149	1		T205	1		T206	1
all_levels[16]	auto[0]	87	1			T45	2		T37	1		T30	1
all_levels[16]	auto[1]	6	1			T127	3		T207	1		T208	1
all_levels[17]	auto[0]	85	1			T45	2		T43	1		T44	1
all_levels[17]	auto[1]	8	1			T209	1		T210	1		T211	4
all_levels[18]	auto[0]	69	1			T45	1		T43	1		T22	1
all_levels[18]	auto[1]	3	1			T212	2		T213	1		-	-
all_levels[19]	auto[0]	59	1			T45	1		T16	1		T129	1
all_levels[19]	auto[1]	6	1			T214	1		T215	1		T216	2
all_levels[20]	auto[0]	68	1			T89	1		T37	1		T22	1
all_levels[20]	auto[1]	10	1			T156	2		T195	2		T217	1
all_levels[21]	auto[0]	51	1			T50	2		T52	1		T137	1
all_levels[21]	auto[1]	8	1			T196	1		T218	1		T219	4
all_levels[22]	auto[0]	68	1			T138	1		T139	1		T127	1
all_levels[22]	auto[1]	2	1			T154	1		T220	1		-	-
all_levels[23]	auto[0]	51	1			T1	1		T10	1		T45	1
all_levels[23]	auto[1]	1	1			T221	1		-	-		-	-
all_levels[24]	auto[0]	48	1			T1	1		T89	1		T50	1
all_levels[24]	auto[1]	13	1			T222	1		T218	1		T223	1
all_levels[25]	auto[0]	44	1			T88	1		T139	2		T128	1
all_levels[25]	auto[1]	6	1			T224	1		T110	4		T225	1
all_levels[26]	auto[0]	35	1			T45	2		T13	3		T37	1
all_levels[26]	auto[1]	3	1			T13	1		T226	1		T150	1
all_levels[27]	auto[0]	34	1			T89	1		T36	1		T140	1
all_levels[27]	auto[1]	4	1			T89	3		T227	1		-	-
all_levels[28]	auto[0]	27	1			T139	1		T56	1		T137	1
all_levels[28]	auto[1]	4	1			T56	3		T133	1		-	-
all_levels[29]	auto[0]	37	1			T16	1		T22	1		T129	1
all_levels[30]	auto[0]	26	1			T141	1		T129	1		T67	1
all_levels[30]	auto[1]	9	1			T141	2		T199	2		T228	1
all_levels[31]	auto[0]	19	1			T16	1		T142	1		T143	1
all_levels[31]	auto[1]	6	1			T229	1		T230	1		T231	3
all_levels[32]	auto[0]	15	1			T139	1		T120	1		T54	1
all_levels[32]	auto[1]	6	1			T120	2		T232	3		T233	1
all_levels[33]	auto[0]	24	1			T13	1		T66	1		T144	1
all_levels[33]	auto[1]	5	1			T234	1		T235	2		T236	2
all_levels[34]	auto[0]	22	1			T7	1		T88	1		T145	1
all_levels[34]	auto[1]	3	1			T237	3		-	-		-	-
all_levels[35]	auto[0]	19	1			T50	1		T35	1		T145	1
all_levels[35]	auto[1]	1	1			T212	1		-	-		-	-
all_levels[36]	auto[0]	15	1			T32	1		T54	1		T146	1
all_levels[37]	auto[0]	13	1			T146	1		T147	1		T148	2
all_levels[37]	auto[1]	3	1			T238	3		-	-		-	-
all_levels[38]	auto[0]	17	1			T132	1		T149	1		T150	1
all_levels[38]	auto[1]	1	1			T167	1		-	-		-	-
all_levels[39]	auto[0]	21	1			T129	1		T151	1		T114	1
all_levels[39]	auto[1]	1	1			T239	1		-	-		-	-
all_levels[40]	auto[0]	11	1			T137	1		T132	1		T152	1
all_levels[40]	auto[1]	1	1			T137	1		-	-		-	-
all_levels[41]	auto[0]	14	1			T7	1		T153	1		T154	1
all_levels[41]	auto[1]	1	1			T154	1		-	-		-	-
all_levels[42]	auto[0]	17	1			T155	1		T156	1		T143	2
all_levels[42]	auto[1]	1	1			T156	1		-	-		-	-
all_levels[43]	auto[0]	11	1			T6	1		T29	1		T155	1
all_levels[43]	auto[1]	1	1			T6	1		-	-		-	-
all_levels[44]	auto[0]	12	1			T157	1		T116	1		T158	1
all_levels[44]	auto[1]	1	1			T183	1		-	-		-	-
all_levels[45]	auto[0]	14	1			T132	1		T159	1		T133	1
all_levels[45]	auto[1]	6	1			T159	5		T240	1		-	-
all_levels[46]	auto[0]	7	1			T42	1		T155	1		T160	1
all_levels[47]	auto[0]	14	1			T161	1		T152	1		T162	1
all_levels[47]	auto[1]	2	1			T241	2		-	-		-	-
all_levels[48]	auto[0]	6	1			T163	1		T158	1		T164	1
all_levels[48]	auto[1]	1	1			T164	1		-	-		-	-
all_levels[49]	auto[0]	9	1			T7	1		T141	1		T165	1
all_levels[49]	auto[1]	3	1			T141	1		T242	2		-	-
all_levels[50]	auto[0]	8	1			T166	1		T167	1		T168	1
all_levels[50]	auto[1]	5	1			T167	2		T168	2		T243	1
all_levels[51]	auto[0]	10	1			T163	1		T161	1		T133	1
all_levels[52]	auto[0]	9	1			T42	1		T68	1		T169	1
all_levels[52]	auto[1]	4	1			T244	2		T245	2		-	-
all_levels[53]	auto[0]	14	1			T129	1		T53	1		T170	1
all_levels[53]	auto[1]	2	1			T239	2		-	-		-	-
all_levels[54]	auto[0]	7	1			T170	1		T158	1		T171	1
all_levels[54]	auto[1]	2	1			T246	1		T247	1		-	-
all_levels[55]	auto[0]	6	1			T132	1		T172	1		T171	1
all_levels[55]	auto[1]	1	1			T248	1		-	-		-	-
all_levels[56]	auto[0]	11	1			T170	1		T156	1		T173	1
all_levels[57]	auto[0]	6	1			T161	1		T174	1		T175	1
all_levels[57]	auto[1]	2	1			T249	2		-	-		-	-
all_levels[58]	auto[0]	3	1			T176	1		T177	1		T178	1
all_levels[59]	auto[0]	5	1			T179	1		T161	1		T180	1
all_levels[60]	auto[0]	9	1			T181	1		T182	1		T183	1
all_levels[61]	auto[0]	1	1			T184	1		-	-		-	-
all_levels[62]	auto[0]	4	1			T109	1		T185	1		T186	1
all_levels[62]	auto[1]	1	1			T250	1		-	-		-	-
all_levels[63]	auto[0]	11	1			T181	2		T166	1		T169	1
all_levels[63]	auto[1]	2	1			T181	1		T251	1		-	-
all_levels[64]	auto[0]	73	1			T7	1		T10	1		T89	1
all_levels[64]	auto[1]	7	1			T146	1		T202	1		T252	1