Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	9	0	9	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	84027	1			T1	3		T2	7		T3	114
all_pins[1]	84027	1			T1	3		T2	7		T3	114
all_pins[2]	84027	1			T1	3		T2	7		T3	114
all_pins[3]	84027	1			T1	3		T2	7		T3	114
all_pins[4]	84027	1			T1	3		T2	7		T3	114
all_pins[5]	84027	1			T1	3		T2	7		T3	114
all_pins[6]	84027	1			T1	3		T2	7		T3	114
all_pins[7]	84027	1			T1	3		T2	7		T3	114
all_pins[8]	84027	1			T1	3		T2	7		T3	114

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	724163	1			T1	23		T2	54		T3	1019
values[0x1]	32080	1			T1	4		T2	9		T3	7
transitions[0x0=>0x1]	25459	1			T1	3		T2	7		T3	4
transitions[0x1=>0x0]	25284	1			T1	2		T2	6		T3	4

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	68053	1			T1	1		T2	1		T3	110
all_pins[0]	values[0x1]	15974	1			T1	2		T2	6		T3	4
all_pins[0]	transitions[0x0=>0x1]	15578	1			T1	2		T2	6		T3	4
all_pins[0]	transitions[0x1=>0x0]	955	1			T45	31		T13	11		T36	2
all_pins[1]	values[0x0]	82676	1			T1	3		T2	7		T3	114
all_pins[1]	values[0x1]	1351	1			T6	2		T45	31		T13	13
all_pins[1]	transitions[0x0=>0x1]	1255	1			T6	2		T45	31		T13	13
all_pins[1]	transitions[0x1=>0x0]	1867	1			T2	1		T4	15		T6	3
all_pins[2]	values[0x0]	82064	1			T1	3		T2	6		T3	114
all_pins[2]	values[0x1]	1963	1			T2	1		T4	15		T6	3
all_pins[2]	transitions[0x0=>0x1]	1919	1			T2	1		T4	15		T6	3
all_pins[2]	transitions[0x1=>0x0]	178	1			T13	4		T19	2		T32	4
all_pins[3]	values[0x0]	83805	1			T1	3		T2	7		T3	114
all_pins[3]	values[0x1]	222	1			T13	4		T19	2		T32	4
all_pins[3]	transitions[0x0=>0x1]	189	1			T13	3		T19	2		T32	4
all_pins[3]	transitions[0x1=>0x0]	265	1			T12	11		T13	10		T19	3
all_pins[4]	values[0x0]	83729	1			T1	3		T2	7		T3	114
all_pins[4]	values[0x1]	298	1			T12	11		T13	11		T19	3
all_pins[4]	transitions[0x0=>0x1]	268	1			T12	9		T13	9		T19	3
all_pins[4]	transitions[0x1=>0x0]	102	1			T13	2		T15	2		T19	1
all_pins[5]	values[0x0]	83895	1			T1	3		T2	7		T3	114
all_pins[5]	values[0x1]	132	1			T12	2		T13	4		T15	2
all_pins[5]	transitions[0x0=>0x1]	114	1			T12	2		T13	4		T15	2
all_pins[5]	transitions[0x1=>0x0]	605	1			T6	3		T8	1		T21	1
all_pins[6]	values[0x0]	83404	1			T1	3		T2	7		T3	114
all_pins[6]	values[0x1]	623	1			T6	3		T8	1		T21	1
all_pins[6]	transitions[0x0=>0x1]	591	1			T6	3		T8	1		T21	1
all_pins[6]	transitions[0x1=>0x0]	261	1			T13	7		T16	2		T15	2
all_pins[7]	values[0x0]	83734	1			T1	3		T2	7		T3	114
all_pins[7]	values[0x1]	293	1			T13	7		T16	2		T15	4
all_pins[7]	transitions[0x0=>0x1]	187	1			T13	4		T16	2		T15	4
all_pins[7]	transitions[0x1=>0x0]	11118	1			T1	2		T2	2		T3	3
all_pins[8]	values[0x0]	72803	1			T1	1		T2	5		T3	111
all_pins[8]	values[0x1]	11224	1			T1	2		T2	2		T3	3
all_pins[8]	transitions[0x0=>0x1]	5358	1			T1	1		T4	307		T6	1
all_pins[8]	transitions[0x1=>0x0]	9933	1			T2	3		T3	1		T4	37