Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::tx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::tx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	35	0	35	100.00
Crosses	66	0	66	100.00

Variables for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	33	0	33	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tx_fifo_level_cg_cc	66	0	66	100.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	4882060	1			T1	1		T2	17		T3	1
all_levels[1]	1430470	1			T1	3		T2	2		T4	10324
all_levels[2]	270250	1			T4	4735		T7	3		T8	12
all_levels[3]	312081	1			T1	1		T4	4790		T8	4
all_levels[4]	177209	1			T1	3		T4	4792		T7	1
all_levels[5]	165620	1			T4	4752		T46	13		T13	654
all_levels[6]	172690	1			T4	4791		T7	2		T8	37
all_levels[7]	172243	1			T4	4796		T7	1		T21	2
all_levels[8]	236467	1			T1	4		T4	4771		T7	6
all_levels[9]	156182	1			T4	4792		T8	1		T13	1105
all_levels[10]	206243	1			T4	4781		T88	3		T141	6
all_levels[11]	190474	1			T1	7		T3	1		T4	4789
all_levels[12]	167723	1			T1	1		T4	4799		T7	1
all_levels[13]	281561	1			T1	1		T4	4863		T13	862
all_levels[14]	165267	1			T4	4857		T10	3		T13	1171
all_levels[15]	192881	1			T4	4876		T88	1		T13	609
all_levels[16]	179504	1			T1	5		T4	4869		T13	51
all_levels[17]	158769	1			T1	4		T2	10		T4	4869
all_levels[18]	151895	1			T4	4851		T45	1		T13	43
all_levels[19]	167360	1			T4	4864		T45	1		T13	44
all_levels[20]	208960	1			T3	2		T4	4858		T7	77
all_levels[21]	212027	1			T1	3		T4	4871		T8	13
all_levels[22]	156461	1			T4	4791		T8	8		T88	2
all_levels[23]	178711	1			T4	2390		T8	1		T45	1
all_levels[24]	374015	1			T4	2395		T8	4		T253	5
all_levels[25]	577066	1			T4	2382		T13	51		T38	100
all_levels[26]	135481	1			T4	2395		T8	2		T13	42
all_levels[27]	283005	1			T3	2		T4	2391		T8	9
all_levels[28]	440647	1			T4	2381		T8	3		T13	47
all_levels[29]	261085	1			T4	2278		T8	1		T45	1
all_levels[30]	136754	1			T4	1969		T7	1		T8	2
all_levels[31]	451650	1			T4	1960		T6	2		T8	4
all_levels[32]	10692710	1			T3	283		T4	2391		T6	12

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23941723

1

T1

32

T2

24

T3

288

auto[1]

3798

1

T1

1

T2

5

T3

1

---

Summary for Cross tx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	66	0	66	100.00

Automatically Generated Cross Bins for tx_fifo_level_cg_cc

Bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	4879894	1			T1	1		T2	15		T3	1
all_levels[0]	auto[1]	2166	1			T2	2		T6	6		T7	4
all_levels[1]	auto[0]	1430179	1			T1	3		T2	1		T4	10324
all_levels[1]	auto[1]	291	1			T2	1		T141	1		T43	1
all_levels[2]	auto[0]	270217	1			T4	4735		T7	3		T8	12
all_levels[2]	auto[1]	33	1			T120	1		T53	1		T272	1
all_levels[3]	auto[0]	312014	1			T1	1		T4	4790		T8	4
all_levels[3]	auto[1]	67	1			T36	1		T22	1		T343	3
all_levels[4]	auto[0]	177191	1			T1	3		T4	4792		T7	1
all_levels[4]	auto[1]	18	1			T253	1		T139	1		T190	1
all_levels[5]	auto[0]	165589	1			T4	4752		T46	13		T13	654
all_levels[5]	auto[1]	31	1			T187	2		T55	1		T56	1
all_levels[6]	auto[0]	172657	1			T4	4791		T7	2		T8	37
all_levels[6]	auto[1]	33	1			T139	1		T53	3		T66	1
all_levels[7]	auto[0]	172180	1			T4	4796		T7	1		T21	2
all_levels[7]	auto[1]	63	1			T31	1		T321	4		T200	1
all_levels[8]	auto[0]	236443	1			T1	4		T4	4771		T7	4
all_levels[8]	auto[1]	24	1			T7	2		T43	1		T155	1
all_levels[9]	auto[0]	156156	1			T4	4792		T8	1		T13	1105
all_levels[9]	auto[1]	26	1			T191	1		T305	3		T316	1
all_levels[10]	auto[0]	206219	1			T4	4781		T88	2		T141	4
all_levels[10]	auto[1]	24	1			T88	1		T141	2		T36	1
all_levels[11]	auto[0]	190460	1			T1	6		T3	1		T4	4789
all_levels[11]	auto[1]	14	1			T1	1		T181	2		T155	1
all_levels[12]	auto[0]	167707	1			T1	1		T4	4799		T7	1
all_levels[12]	auto[1]	16	1			T187	1		T35	1		T347	1
all_levels[13]	auto[0]	281545	1			T1	1		T4	4863		T13	862
all_levels[13]	auto[1]	16	1			T154	1		T317	1		T290	1
all_levels[14]	auto[0]	165242	1			T4	4857		T10	2		T13	1171
all_levels[14]	auto[1]	25	1			T10	1		T128	1		T112	1
all_levels[15]	auto[0]	192791	1			T4	4876		T88	1		T13	609
all_levels[15]	auto[1]	90	1			T181	1		T130	4		T273	2
all_levels[16]	auto[0]	179492	1			T1	5		T4	4869		T13	51
all_levels[16]	auto[1]	12	1			T37	1		T43	1		T132	1
all_levels[17]	auto[0]	158748	1			T1	4		T2	8		T4	4869
all_levels[17]	auto[1]	21	1			T2	2		T145	1		T290	1
all_levels[18]	auto[0]	151869	1			T4	4851		T45	1		T13	43
all_levels[18]	auto[1]	26	1			T56	1		T315	1		T299	1
all_levels[19]	auto[0]	167333	1			T4	4864		T45	1		T13	44
all_levels[19]	auto[1]	27	1			T187	1		T50	1		T155	1
all_levels[20]	auto[0]	208941	1			T3	2		T4	4858		T7	76
all_levels[20]	auto[1]	19	1			T7	1		T45	1		T43	1
all_levels[21]	auto[0]	211997	1			T1	3		T4	4871		T8	13
all_levels[21]	auto[1]	30	1			T21	2		T42	1		T256	1
all_levels[22]	auto[0]	156444	1			T4	4791		T8	8		T88	2
all_levels[22]	auto[1]	17	1			T193	2		T196	2		T309	1
all_levels[23]	auto[0]	178697	1			T4	2390		T8	1		T45	1
all_levels[23]	auto[1]	14	1			T56	3		T144	1		T348	1
all_levels[24]	auto[0]	373993	1			T4	2395		T8	4		T253	2
all_levels[24]	auto[1]	22	1			T253	3		T191	1		T349	1
all_levels[25]	auto[0]	577050	1			T4	2382		T13	51		T38	100
all_levels[25]	auto[1]	16	1			T289	5		T305	2		T277	1
all_levels[26]	auto[0]	135467	1			T4	2395		T8	2		T13	42
all_levels[26]	auto[1]	14	1			T268	1		T190	1		T146	1
all_levels[27]	auto[0]	282985	1			T3	2		T4	2391		T8	9
all_levels[27]	auto[1]	20	1			T88	1		T272	1		T172	1
all_levels[28]	auto[0]	440627	1			T4	2381		T8	3		T13	47
all_levels[28]	auto[1]	20	1			T272	1		T198	1		T350	3
all_levels[29]	auto[0]	261062	1			T4	2278		T8	1		T45	1
all_levels[29]	auto[1]	23	1			T146	2		T351	2		T328	1
all_levels[30]	auto[0]	136744	1			T4	1969		T7	1		T8	2
all_levels[30]	auto[1]	10	1			T190	3		T168	1		T352	1
all_levels[31]	auto[0]	451618	1			T4	1960		T6	1		T8	4
all_levels[31]	auto[1]	32	1			T6	1		T43	2		T159	1
all_levels[32]	auto[0]	10692172	1			T3	282		T4	2391		T6	10
all_levels[32]	auto[1]	538	1			T3	1		T6	2		T7	1