Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.30	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	54	6	48	88.89

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	54	6	48	88.89	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	521	1			T13	11		T19	11		T90	7
all_values[1]	521	1			T13	11		T19	11		T90	7
all_values[2]	521	1			T13	11		T19	11		T90	7
all_values[3]	521	1			T13	11		T19	11		T90	7
all_values[4]	521	1			T13	11		T19	11		T90	7
all_values[5]	521	1			T13	11		T19	11		T90	7
all_values[6]	521	1			T13	11		T19	11		T90	7
all_values[7]	521	1			T13	11		T19	11		T90	7
all_values[8]	521	1			T13	11		T19	11		T90	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2587

1

T13

53

T19

58

T90

36

auto[1]

2102

1

T13

46

T19

41

T90

27

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1587

1

T13

34

T19

20

T90

20

auto[1]

3102

1

T13

65

T19

79

T90

43

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2782

1

T13

60

T19

48

T90

37

auto[1]

1907

1

T13

39

T19

51

T90

26

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	54	6	48	88.89	6
Automatically Generated Cross Bins	54	6	48	88.89	6
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	*	[auto[0]]	--	--	2
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2
[all_values[8]]	[auto[0]]	*	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	157	1			T13	3		T19	3		T90	2
all_values[0]	auto[0]	auto[1]	auto[1]	143	1			T13	3		T19	1		T90	2
all_values[0]	auto[1]	auto[0]	auto[1]	123	1			T13	2		T19	3		T90	2
all_values[0]	auto[1]	auto[1]	auto[1]	98	1			T13	3		T19	4		T90	1
all_values[1]	auto[0]	auto[0]	auto[0]	162	1			T13	4		T90	2		T132	4
all_values[1]	auto[0]	auto[1]	auto[0]	159	1			T13	2		T19	4		T90	3
all_values[1]	auto[1]	auto[0]	auto[1]	123	1			T13	4		T19	5		T90	1
all_values[1]	auto[1]	auto[1]	auto[1]	77	1			T13	1		T19	2		T90	1
all_values[2]	auto[0]	auto[0]	auto[0]	111	1			T13	2		T19	3		T90	1
all_values[2]	auto[0]	auto[0]	auto[1]	43	1			T13	1		T19	2		T90	2
all_values[2]	auto[0]	auto[1]	auto[0]	97	1			T13	1		T132	2		T114	1
all_values[2]	auto[0]	auto[1]	auto[1]	57	1			T13	3		T19	1		T90	1
all_values[2]	auto[1]	auto[0]	auto[1]	111	1			T13	3		T19	4		T132	2
all_values[2]	auto[1]	auto[1]	auto[1]	102	1			T13	1		T19	1		T90	3
all_values[3]	auto[0]	auto[0]	auto[0]	139	1			T13	2		T19	1		T90	1
all_values[3]	auto[0]	auto[0]	auto[1]	49	1			T13	1		T19	3		T35	1
all_values[3]	auto[0]	auto[1]	auto[0]	70	1			T13	2		T19	3		T90	2
all_values[3]	auto[0]	auto[1]	auto[1]	55	1			T13	2		T19	1		T133	1
all_values[3]	auto[1]	auto[0]	auto[1]	113	1			T13	3		T19	2		T90	4
all_values[3]	auto[1]	auto[1]	auto[1]	95	1			T13	1		T19	1		T132	1
all_values[4]	auto[0]	auto[0]	auto[0]	118	1			T13	1		T90	2		T35	3
all_values[4]	auto[0]	auto[0]	auto[1]	52	1			T13	1		T19	4		T114	1
all_values[4]	auto[0]	auto[1]	auto[0]	92	1			T13	3		T90	1		T132	1
all_values[4]	auto[0]	auto[1]	auto[1]	43	1			T13	2		T19	2		T90	1
all_values[4]	auto[1]	auto[0]	auto[1]	126	1			T13	3		T19	3		T90	2
all_values[4]	auto[1]	auto[1]	auto[1]	90	1			T13	1		T19	2		T90	1
all_values[5]	auto[0]	auto[0]	auto[0]	112	1			T13	1		T19	3		T90	2
all_values[5]	auto[0]	auto[0]	auto[1]	43	1			T19	2		T132	1		T134	1
all_values[5]	auto[0]	auto[1]	auto[0]	108	1			T13	5		T19	1		T90	3
all_values[5]	auto[0]	auto[1]	auto[1]	48	1			T13	2		T132	1		T35	1
all_values[5]	auto[1]	auto[0]	auto[1]	116	1			T13	2		T19	4		T90	1
all_values[5]	auto[1]	auto[1]	auto[1]	94	1			T13	1		T19	1		T90	1
all_values[6]	auto[0]	auto[0]	auto[0]	130	1			T13	4		T19	1		T132	1
all_values[6]	auto[0]	auto[0]	auto[1]	47	1			T13	1		T19	1		T90	3
all_values[6]	auto[0]	auto[1]	auto[0]	96	1			T13	4		T19	1		T90	1
all_values[6]	auto[0]	auto[1]	auto[1]	45	1			T19	2		T132	1		T134	1
all_values[6]	auto[1]	auto[0]	auto[1]	119	1			T13	2		T19	3		T90	3
all_values[6]	auto[1]	auto[1]	auto[1]	84	1			T19	3		T132	1		T133	2
all_values[7]	auto[0]	auto[0]	auto[0]	123	1			T13	2		T19	1		T90	1
all_values[7]	auto[0]	auto[0]	auto[1]	48	1			T90	1		T132	2		T114	1
all_values[7]	auto[0]	auto[1]	auto[0]	70	1			T13	1		T19	2		T90	1
all_values[7]	auto[0]	auto[1]	auto[1]	57	1			T13	3		T19	2		T90	1
all_values[7]	auto[1]	auto[0]	auto[1]	125	1			T13	4		T19	4		T90	3
all_values[7]	auto[1]	auto[1]	auto[1]	98	1			T13	1		T19	2		T132	1
all_values[8]	auto[0]	auto[0]	auto[1]	166	1			T13	2		T19	2		T90	3
all_values[8]	auto[0]	auto[1]	auto[1]	142	1			T13	2		T19	2		T90	1
all_values[8]	auto[1]	auto[0]	auto[1]	131	1			T13	5		T19	4		T132	1
all_values[8]	auto[1]	auto[1]	auto[1]	82	1			T13	2		T19	3		T90	3

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal