Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.12 99.10 97.65 100.00 98.38 100.00 99.57


Total test records in report: 1227
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T1036 /workspace/coverage/default/75.uart_stress_all_with_rand_reset.1103018539 Jun 10 05:15:10 PM PDT 24 Jun 10 05:24:42 PM PDT 24 97359275514 ps
T1037 /workspace/coverage/default/19.uart_tx_ovrd.2537843516 Jun 10 05:13:40 PM PDT 24 Jun 10 05:13:59 PM PDT 24 6418038451 ps
T1038 /workspace/coverage/default/11.uart_intr.1348073538 Jun 10 05:13:17 PM PDT 24 Jun 10 05:13:47 PM PDT 24 87104198706 ps
T1039 /workspace/coverage/default/140.uart_fifo_reset.1706836784 Jun 10 05:15:30 PM PDT 24 Jun 10 05:17:19 PM PDT 24 234674147728 ps
T1040 /workspace/coverage/default/45.uart_tx_rx.1666273425 Jun 10 05:14:51 PM PDT 24 Jun 10 05:15:26 PM PDT 24 56809850216 ps
T1041 /workspace/coverage/default/268.uart_fifo_reset.1990285575 Jun 10 05:16:07 PM PDT 24 Jun 10 05:16:52 PM PDT 24 60160031790 ps
T248 /workspace/coverage/default/108.uart_fifo_reset.3959293433 Jun 10 05:15:19 PM PDT 24 Jun 10 05:15:51 PM PDT 24 132190508438 ps
T245 /workspace/coverage/default/125.uart_fifo_reset.1677981306 Jun 10 05:15:26 PM PDT 24 Jun 10 05:16:19 PM PDT 24 133990070556 ps
T1042 /workspace/coverage/default/280.uart_fifo_reset.562235677 Jun 10 05:16:12 PM PDT 24 Jun 10 05:17:36 PM PDT 24 55024348539 ps
T1043 /workspace/coverage/default/238.uart_fifo_reset.3595944125 Jun 10 05:15:52 PM PDT 24 Jun 10 05:16:19 PM PDT 24 52647906325 ps
T1044 /workspace/coverage/default/41.uart_tx_ovrd.1612155330 Jun 10 05:14:39 PM PDT 24 Jun 10 05:14:46 PM PDT 24 1278408816 ps
T1045 /workspace/coverage/default/10.uart_loopback.2923503423 Jun 10 05:13:21 PM PDT 24 Jun 10 05:13:23 PM PDT 24 1977974081 ps
T1046 /workspace/coverage/default/273.uart_fifo_reset.2626566800 Jun 10 05:16:12 PM PDT 24 Jun 10 05:17:11 PM PDT 24 412619792993 ps
T1047 /workspace/coverage/default/68.uart_stress_all_with_rand_reset.3983956066 Jun 10 05:15:11 PM PDT 24 Jun 10 05:39:51 PM PDT 24 121503398535 ps
T1048 /workspace/coverage/default/262.uart_fifo_reset.1183324798 Jun 10 05:16:13 PM PDT 24 Jun 10 05:17:21 PM PDT 24 37726592816 ps
T1049 /workspace/coverage/default/195.uart_fifo_reset.1927367040 Jun 10 05:15:39 PM PDT 24 Jun 10 05:18:04 PM PDT 24 116095989190 ps
T1050 /workspace/coverage/default/49.uart_tx_ovrd.482102381 Jun 10 05:14:58 PM PDT 24 Jun 10 05:15:07 PM PDT 24 8216213300 ps
T1051 /workspace/coverage/default/237.uart_fifo_reset.1984150374 Jun 10 05:15:52 PM PDT 24 Jun 10 05:16:42 PM PDT 24 193215756468 ps
T1052 /workspace/coverage/default/16.uart_tx_ovrd.1011547774 Jun 10 05:13:29 PM PDT 24 Jun 10 05:13:32 PM PDT 24 3807481752 ps
T1053 /workspace/coverage/default/26.uart_loopback.682890292 Jun 10 05:13:55 PM PDT 24 Jun 10 05:13:59 PM PDT 24 2547565764 ps
T1054 /workspace/coverage/default/17.uart_perf.2871416287 Jun 10 05:13:32 PM PDT 24 Jun 10 05:22:05 PM PDT 24 13161554649 ps
T1055 /workspace/coverage/default/288.uart_fifo_reset.2141263478 Jun 10 05:16:09 PM PDT 24 Jun 10 05:16:35 PM PDT 24 57513261478 ps
T1056 /workspace/coverage/default/143.uart_fifo_reset.3007839567 Jun 10 05:15:29 PM PDT 24 Jun 10 05:15:56 PM PDT 24 22190490199 ps
T1057 /workspace/coverage/default/118.uart_fifo_reset.319758795 Jun 10 05:15:20 PM PDT 24 Jun 10 05:16:14 PM PDT 24 61134670100 ps
T1058 /workspace/coverage/default/9.uart_rx_oversample.1393009889 Jun 10 05:13:14 PM PDT 24 Jun 10 05:13:21 PM PDT 24 3346170835 ps
T1059 /workspace/coverage/default/19.uart_rx_start_bit_filter.1388938445 Jun 10 05:13:37 PM PDT 24 Jun 10 05:13:40 PM PDT 24 3934128553 ps
T240 /workspace/coverage/default/150.uart_fifo_reset.2992706824 Jun 10 05:15:32 PM PDT 24 Jun 10 05:18:25 PM PDT 24 110468807449 ps
T1060 /workspace/coverage/default/43.uart_perf.1222354394 Jun 10 05:14:46 PM PDT 24 Jun 10 05:16:33 PM PDT 24 22891097547 ps
T1061 /workspace/coverage/default/106.uart_fifo_reset.888752141 Jun 10 05:15:19 PM PDT 24 Jun 10 05:17:09 PM PDT 24 76499051839 ps
T1062 /workspace/coverage/default/26.uart_long_xfer_wo_dly.584501494 Jun 10 05:13:47 PM PDT 24 Jun 10 05:17:39 PM PDT 24 74936157834 ps
T178 /workspace/coverage/default/183.uart_fifo_reset.2442446389 Jun 10 05:15:35 PM PDT 24 Jun 10 05:16:16 PM PDT 24 34227742594 ps
T1063 /workspace/coverage/default/47.uart_stress_all.2948706384 Jun 10 05:14:49 PM PDT 24 Jun 10 05:16:19 PM PDT 24 232243263642 ps
T1064 /workspace/coverage/default/45.uart_stress_all.2426389989 Jun 10 05:14:50 PM PDT 24 Jun 10 05:15:13 PM PDT 24 27257971111 ps
T1065 /workspace/coverage/default/132.uart_fifo_reset.1350942369 Jun 10 05:15:29 PM PDT 24 Jun 10 05:16:26 PM PDT 24 36306751784 ps
T1066 /workspace/coverage/default/293.uart_fifo_reset.1749659254 Jun 10 05:16:14 PM PDT 24 Jun 10 05:16:37 PM PDT 24 55810905145 ps
T1067 /workspace/coverage/default/175.uart_fifo_reset.1269141147 Jun 10 05:15:36 PM PDT 24 Jun 10 05:19:27 PM PDT 24 127283179090 ps
T1068 /workspace/coverage/default/35.uart_fifo_full.4126458498 Jun 10 05:14:13 PM PDT 24 Jun 10 05:16:36 PM PDT 24 179617100911 ps
T1069 /workspace/coverage/default/7.uart_stress_all_with_rand_reset.3526077529 Jun 10 05:13:08 PM PDT 24 Jun 10 05:23:46 PM PDT 24 252271128854 ps
T1070 /workspace/coverage/default/46.uart_tx_ovrd.2934939802 Jun 10 05:14:50 PM PDT 24 Jun 10 05:14:54 PM PDT 24 947805439 ps
T1071 /workspace/coverage/default/45.uart_tx_ovrd.4087011497 Jun 10 05:14:49 PM PDT 24 Jun 10 05:15:20 PM PDT 24 7312014129 ps
T1072 /workspace/coverage/default/220.uart_fifo_reset.4077268394 Jun 10 05:15:45 PM PDT 24 Jun 10 05:18:17 PM PDT 24 88372176802 ps
T1073 /workspace/coverage/default/45.uart_perf.2093049857 Jun 10 05:14:51 PM PDT 24 Jun 10 05:18:10 PM PDT 24 17171145015 ps
T1074 /workspace/coverage/default/45.uart_fifo_overflow.590338286 Jun 10 05:14:50 PM PDT 24 Jun 10 05:18:24 PM PDT 24 83077217445 ps
T1075 /workspace/coverage/default/16.uart_fifo_overflow.2885249568 Jun 10 05:13:30 PM PDT 24 Jun 10 05:14:31 PM PDT 24 56564764711 ps
T1076 /workspace/coverage/default/1.uart_rx_parity_err.2623932574 Jun 10 05:12:40 PM PDT 24 Jun 10 05:13:03 PM PDT 24 113082235174 ps
T1077 /workspace/coverage/default/11.uart_perf.880177659 Jun 10 05:13:18 PM PDT 24 Jun 10 05:16:29 PM PDT 24 12523505319 ps
T1078 /workspace/coverage/default/230.uart_fifo_reset.2240277133 Jun 10 05:15:50 PM PDT 24 Jun 10 05:16:06 PM PDT 24 33453868995 ps
T1079 /workspace/coverage/default/12.uart_stress_all.759750587 Jun 10 05:13:26 PM PDT 24 Jun 10 05:22:53 PM PDT 24 236510983795 ps
T1080 /workspace/coverage/default/32.uart_intr.2029723043 Jun 10 05:14:11 PM PDT 24 Jun 10 05:14:14 PM PDT 24 4515286459 ps
T1081 /workspace/coverage/default/34.uart_tx_ovrd.1392918268 Jun 10 05:14:17 PM PDT 24 Jun 10 05:14:19 PM PDT 24 9918040544 ps
T1082 /workspace/coverage/default/30.uart_long_xfer_wo_dly.2803057534 Jun 10 05:14:00 PM PDT 24 Jun 10 05:22:00 PM PDT 24 64032949570 ps
T1083 /workspace/coverage/default/111.uart_fifo_reset.1464774054 Jun 10 05:15:20 PM PDT 24 Jun 10 05:17:14 PM PDT 24 81305877748 ps
T1084 /workspace/coverage/default/30.uart_smoke.2135449689 Jun 10 05:14:09 PM PDT 24 Jun 10 05:14:13 PM PDT 24 802346443 ps
T1085 /workspace/coverage/default/21.uart_tx_rx.733110497 Jun 10 05:13:59 PM PDT 24 Jun 10 05:14:06 PM PDT 24 8114883870 ps
T1086 /workspace/coverage/default/10.uart_perf.2461826325 Jun 10 05:13:20 PM PDT 24 Jun 10 05:18:19 PM PDT 24 11865974359 ps
T1087 /workspace/coverage/default/152.uart_fifo_reset.1780614034 Jun 10 05:15:29 PM PDT 24 Jun 10 05:16:07 PM PDT 24 23606867448 ps
T1088 /workspace/coverage/default/19.uart_long_xfer_wo_dly.852868345 Jun 10 05:13:37 PM PDT 24 Jun 10 05:16:39 PM PDT 24 147239570499 ps
T1089 /workspace/coverage/default/20.uart_tx_rx.3744542284 Jun 10 05:13:37 PM PDT 24 Jun 10 05:13:50 PM PDT 24 26699233777 ps
T238 /workspace/coverage/default/47.uart_fifo_reset.3788306803 Jun 10 05:14:49 PM PDT 24 Jun 10 05:15:16 PM PDT 24 39475462490 ps
T227 /workspace/coverage/default/188.uart_fifo_reset.1851552006 Jun 10 05:15:39 PM PDT 24 Jun 10 05:16:15 PM PDT 24 76157155070 ps
T1090 /workspace/coverage/default/11.uart_fifo_full.3256479785 Jun 10 05:13:20 PM PDT 24 Jun 10 05:14:52 PM PDT 24 103553217244 ps
T1091 /workspace/coverage/default/4.uart_fifo_overflow.3212498053 Jun 10 05:12:56 PM PDT 24 Jun 10 05:14:08 PM PDT 24 77647693696 ps
T1092 /workspace/coverage/cover_reg_top/10.uart_intr_test.3225448795 Jun 10 05:09:54 PM PDT 24 Jun 10 05:09:54 PM PDT 24 24771187 ps
T1093 /workspace/coverage/cover_reg_top/12.uart_intr_test.739115939 Jun 10 05:09:41 PM PDT 24 Jun 10 05:09:42 PM PDT 24 75743069 ps
T1094 /workspace/coverage/cover_reg_top/44.uart_intr_test.993538885 Jun 10 05:09:52 PM PDT 24 Jun 10 05:09:53 PM PDT 24 55485663 ps
T92 /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.2654136859 Jun 10 05:09:56 PM PDT 24 Jun 10 05:09:57 PM PDT 24 298282873 ps
T1095 /workspace/coverage/cover_reg_top/11.uart_tl_errors.506153030 Jun 10 05:09:53 PM PDT 24 Jun 10 05:09:54 PM PDT 24 103216741 ps
T79 /workspace/coverage/cover_reg_top/3.uart_csr_rw.85638079 Jun 10 05:09:43 PM PDT 24 Jun 10 05:09:44 PM PDT 24 57136099 ps
T1096 /workspace/coverage/cover_reg_top/9.uart_tl_errors.6493477 Jun 10 05:09:43 PM PDT 24 Jun 10 05:09:45 PM PDT 24 82512202 ps
T1097 /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.203534633 Jun 10 05:09:40 PM PDT 24 Jun 10 05:09:42 PM PDT 24 22796388 ps
T80 /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.1300468097 Jun 10 05:09:50 PM PDT 24 Jun 10 05:09:51 PM PDT 24 34542218 ps
T93 /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.1276960759 Jun 10 05:09:33 PM PDT 24 Jun 10 05:09:35 PM PDT 24 883381648 ps
T1098 /workspace/coverage/cover_reg_top/13.uart_intr_test.1025252389 Jun 10 05:09:36 PM PDT 24 Jun 10 05:09:38 PM PDT 24 52321694 ps
T1099 /workspace/coverage/cover_reg_top/6.uart_tl_errors.2965967777 Jun 10 05:09:50 PM PDT 24 Jun 10 05:09:52 PM PDT 24 461158073 ps
T1100 /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.4183843044 Jun 10 05:09:52 PM PDT 24 Jun 10 05:09:55 PM PDT 24 1076323940 ps
T63 /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.2327752206 Jun 10 05:09:41 PM PDT 24 Jun 10 05:09:43 PM PDT 24 14454940 ps
T1101 /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.3613204459 Jun 10 05:09:38 PM PDT 24 Jun 10 05:09:41 PM PDT 24 15493214 ps
T1102 /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.868208878 Jun 10 05:09:43 PM PDT 24 Jun 10 05:09:45 PM PDT 24 35173131 ps
T94 /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.69325425 Jun 10 05:09:27 PM PDT 24 Jun 10 05:09:28 PM PDT 24 201105372 ps
T1103 /workspace/coverage/cover_reg_top/40.uart_intr_test.3645433453 Jun 10 05:09:46 PM PDT 24 Jun 10 05:09:47 PM PDT 24 153481497 ps
T1104 /workspace/coverage/cover_reg_top/4.uart_tl_errors.2098274613 Jun 10 05:09:34 PM PDT 24 Jun 10 05:09:37 PM PDT 24 96110404 ps
T135 /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.2492949418 Jun 10 05:09:47 PM PDT 24 Jun 10 05:09:48 PM PDT 24 49378160 ps
T81 /workspace/coverage/cover_reg_top/10.uart_csr_rw.4050173165 Jun 10 05:09:46 PM PDT 24 Jun 10 05:09:47 PM PDT 24 46633433 ps
T82 /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.3589229470 Jun 10 05:09:43 PM PDT 24 Jun 10 05:09:45 PM PDT 24 112907101 ps
T83 /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.3622252428 Jun 10 05:09:34 PM PDT 24 Jun 10 05:09:36 PM PDT 24 79995882 ps
T1105 /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.1203551849 Jun 10 05:09:30 PM PDT 24 Jun 10 05:09:32 PM PDT 24 68714936 ps
T1106 /workspace/coverage/cover_reg_top/3.uart_intr_test.2266121454 Jun 10 05:09:33 PM PDT 24 Jun 10 05:09:34 PM PDT 24 44594449 ps
T1107 /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.636121413 Jun 10 05:10:03 PM PDT 24 Jun 10 05:10:05 PM PDT 24 286513354 ps
T84 /workspace/coverage/cover_reg_top/17.uart_csr_rw.2001120710 Jun 10 05:09:38 PM PDT 24 Jun 10 05:09:40 PM PDT 24 23765122 ps
T85 /workspace/coverage/cover_reg_top/0.uart_csr_rw.913613035 Jun 10 05:10:02 PM PDT 24 Jun 10 05:10:03 PM PDT 24 19348167 ps
T1108 /workspace/coverage/cover_reg_top/42.uart_intr_test.2023170538 Jun 10 05:09:44 PM PDT 24 Jun 10 05:09:45 PM PDT 24 13645690 ps
T86 /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.820844642 Jun 10 05:09:34 PM PDT 24 Jun 10 05:09:35 PM PDT 24 58969549 ps
T1109 /workspace/coverage/cover_reg_top/35.uart_intr_test.2771317354 Jun 10 05:09:55 PM PDT 24 Jun 10 05:09:56 PM PDT 24 13647405 ps
T72 /workspace/coverage/cover_reg_top/9.uart_csr_rw.4166313923 Jun 10 05:09:38 PM PDT 24 Jun 10 05:09:41 PM PDT 24 264609427 ps
T1110 /workspace/coverage/cover_reg_top/49.uart_intr_test.2058345427 Jun 10 05:09:45 PM PDT 24 Jun 10 05:09:46 PM PDT 24 13732269 ps
T87 /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.3560680721 Jun 10 05:09:39 PM PDT 24 Jun 10 05:09:41 PM PDT 24 63167167 ps
T1111 /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.2083511102 Jun 10 05:09:35 PM PDT 24 Jun 10 05:09:36 PM PDT 24 25948804 ps
T1112 /workspace/coverage/cover_reg_top/15.uart_tl_errors.50805998 Jun 10 05:09:44 PM PDT 24 Jun 10 05:09:46 PM PDT 24 84540944 ps
T1113 /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.3943825863 Jun 10 05:09:33 PM PDT 24 Jun 10 05:09:35 PM PDT 24 25179261 ps
T1114 /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.3881506122 Jun 10 05:09:48 PM PDT 24 Jun 10 05:09:49 PM PDT 24 28106878 ps
T1115 /workspace/coverage/cover_reg_top/1.uart_csr_rw.4216501122 Jun 10 05:09:43 PM PDT 24 Jun 10 05:09:44 PM PDT 24 14611040 ps
T1116 /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.3281490269 Jun 10 05:09:36 PM PDT 24 Jun 10 05:09:38 PM PDT 24 69120295 ps
T1117 /workspace/coverage/cover_reg_top/9.uart_intr_test.1883056282 Jun 10 05:09:42 PM PDT 24 Jun 10 05:09:44 PM PDT 24 18801026 ps
T1118 /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.3341227685 Jun 10 05:09:44 PM PDT 24 Jun 10 05:09:46 PM PDT 24 33608273 ps
T1119 /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.1533210971 Jun 10 05:09:36 PM PDT 24 Jun 10 05:09:39 PM PDT 24 148718812 ps
T1120 /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.1422123402 Jun 10 05:09:44 PM PDT 24 Jun 10 05:09:45 PM PDT 24 52030217 ps
T73 /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.3085499124 Jun 10 05:09:55 PM PDT 24 Jun 10 05:09:56 PM PDT 24 45946232 ps
T1121 /workspace/coverage/cover_reg_top/30.uart_intr_test.902133272 Jun 10 05:09:43 PM PDT 24 Jun 10 05:09:45 PM PDT 24 17430029 ps
T1122 /workspace/coverage/cover_reg_top/3.uart_tl_errors.3885256066 Jun 10 05:09:37 PM PDT 24 Jun 10 05:09:40 PM PDT 24 84700390 ps
T1123 /workspace/coverage/cover_reg_top/18.uart_tl_errors.1314078932 Jun 10 05:09:38 PM PDT 24 Jun 10 05:09:42 PM PDT 24 572958871 ps
T97 /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.1305276603 Jun 10 05:09:35 PM PDT 24 Jun 10 05:09:37 PM PDT 24 38604405 ps
T1124 /workspace/coverage/cover_reg_top/11.uart_intr_test.3337322417 Jun 10 05:09:35 PM PDT 24 Jun 10 05:09:38 PM PDT 24 43041457 ps
T1125 /workspace/coverage/cover_reg_top/47.uart_intr_test.1198976306 Jun 10 05:09:49 PM PDT 24 Jun 10 05:09:49 PM PDT 24 12479321 ps
T1126 /workspace/coverage/cover_reg_top/7.uart_csr_rw.3906649108 Jun 10 05:09:38 PM PDT 24 Jun 10 05:09:41 PM PDT 24 60093151 ps
T1127 /workspace/coverage/cover_reg_top/19.uart_tl_errors.3298256548 Jun 10 05:09:53 PM PDT 24 Jun 10 05:09:57 PM PDT 24 135565817 ps
T1128 /workspace/coverage/cover_reg_top/18.uart_intr_test.4027691886 Jun 10 05:09:40 PM PDT 24 Jun 10 05:09:42 PM PDT 24 43292476 ps
T1129 /workspace/coverage/cover_reg_top/15.uart_intr_test.2760174573 Jun 10 05:09:43 PM PDT 24 Jun 10 05:09:44 PM PDT 24 15051089 ps
T1130 /workspace/coverage/cover_reg_top/2.uart_intr_test.1418128082 Jun 10 05:09:29 PM PDT 24 Jun 10 05:09:30 PM PDT 24 55977133 ps
T1131 /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.2109322593 Jun 10 05:09:52 PM PDT 24 Jun 10 05:09:59 PM PDT 24 54533896 ps
T1132 /workspace/coverage/cover_reg_top/1.uart_tl_errors.3776386322 Jun 10 05:09:30 PM PDT 24 Jun 10 05:09:33 PM PDT 24 196584125 ps
T1133 /workspace/coverage/cover_reg_top/39.uart_intr_test.2774507000 Jun 10 05:09:37 PM PDT 24 Jun 10 05:09:40 PM PDT 24 168042789 ps
T100 /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.778986543 Jun 10 05:09:41 PM PDT 24 Jun 10 05:09:42 PM PDT 24 357646744 ps
T1134 /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.67088414 Jun 10 05:09:40 PM PDT 24 Jun 10 05:09:42 PM PDT 24 49204960 ps
T1135 /workspace/coverage/cover_reg_top/14.uart_intr_test.988257844 Jun 10 05:09:44 PM PDT 24 Jun 10 05:09:45 PM PDT 24 36193584 ps
T1136 /workspace/coverage/cover_reg_top/48.uart_intr_test.1987905049 Jun 10 05:09:44 PM PDT 24 Jun 10 05:09:45 PM PDT 24 71449219 ps
T1137 /workspace/coverage/cover_reg_top/23.uart_intr_test.4047168283 Jun 10 05:09:47 PM PDT 24 Jun 10 05:09:48 PM PDT 24 40596286 ps
T1138 /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.2296668918 Jun 10 05:09:34 PM PDT 24 Jun 10 05:09:36 PM PDT 24 29428174 ps
T1139 /workspace/coverage/cover_reg_top/5.uart_tl_errors.1794464414 Jun 10 05:09:34 PM PDT 24 Jun 10 05:09:37 PM PDT 24 450272294 ps
T1140 /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.3626352944 Jun 10 05:09:46 PM PDT 24 Jun 10 05:09:47 PM PDT 24 54878299 ps
T1141 /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.1223472864 Jun 10 05:09:39 PM PDT 24 Jun 10 05:09:42 PM PDT 24 52019674 ps
T1142 /workspace/coverage/cover_reg_top/2.uart_tl_errors.299109750 Jun 10 05:09:43 PM PDT 24 Jun 10 05:09:46 PM PDT 24 407448057 ps
T1143 /workspace/coverage/cover_reg_top/5.uart_csr_rw.1097305492 Jun 10 05:09:34 PM PDT 24 Jun 10 05:09:36 PM PDT 24 12049429 ps
T77 /workspace/coverage/cover_reg_top/2.uart_csr_rw.914726086 Jun 10 05:09:47 PM PDT 24 Jun 10 05:09:48 PM PDT 24 30418238 ps
T1144 /workspace/coverage/cover_reg_top/7.uart_tl_errors.817812907 Jun 10 05:09:35 PM PDT 24 Jun 10 05:09:38 PM PDT 24 70375844 ps
T1145 /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.2048183916 Jun 10 05:09:30 PM PDT 24 Jun 10 05:09:32 PM PDT 24 158704320 ps
T1146 /workspace/coverage/cover_reg_top/32.uart_intr_test.3609674194 Jun 10 05:09:52 PM PDT 24 Jun 10 05:09:53 PM PDT 24 76517898 ps
T1147 /workspace/coverage/cover_reg_top/7.uart_intr_test.1901449662 Jun 10 05:09:35 PM PDT 24 Jun 10 05:09:37 PM PDT 24 36654748 ps
T78 /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.550794477 Jun 10 05:09:34 PM PDT 24 Jun 10 05:09:35 PM PDT 24 37370157 ps
T1148 /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.2080229104 Jun 10 05:09:33 PM PDT 24 Jun 10 05:09:34 PM PDT 24 17838355 ps
T1149 /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.4103970372 Jun 10 05:09:41 PM PDT 24 Jun 10 05:09:43 PM PDT 24 30020607 ps
T98 /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.1349113025 Jun 10 05:09:45 PM PDT 24 Jun 10 05:09:46 PM PDT 24 287259184 ps
T1150 /workspace/coverage/cover_reg_top/46.uart_intr_test.874403633 Jun 10 05:09:38 PM PDT 24 Jun 10 05:09:41 PM PDT 24 12188920 ps
T1151 /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.3267176171 Jun 10 05:09:37 PM PDT 24 Jun 10 05:09:40 PM PDT 24 100425148 ps
T1152 /workspace/coverage/cover_reg_top/27.uart_intr_test.2374977070 Jun 10 05:09:43 PM PDT 24 Jun 10 05:09:44 PM PDT 24 20658470 ps
T101 /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.1691227922 Jun 10 05:09:34 PM PDT 24 Jun 10 05:09:36 PM PDT 24 92437075 ps
T99 /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.185166073 Jun 10 05:09:44 PM PDT 24 Jun 10 05:09:46 PM PDT 24 314423809 ps
T1153 /workspace/coverage/cover_reg_top/21.uart_intr_test.3387306923 Jun 10 05:09:42 PM PDT 24 Jun 10 05:09:44 PM PDT 24 26585036 ps
T1154 /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.2083148943 Jun 10 05:09:51 PM PDT 24 Jun 10 05:09:52 PM PDT 24 42031982 ps
T74 /workspace/coverage/cover_reg_top/19.uart_csr_rw.1369702499 Jun 10 05:09:42 PM PDT 24 Jun 10 05:09:43 PM PDT 24 64661884 ps
T1155 /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.3903631062 Jun 10 05:09:31 PM PDT 24 Jun 10 05:09:33 PM PDT 24 28796931 ps
T1156 /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.1705048870 Jun 10 05:09:39 PM PDT 24 Jun 10 05:09:41 PM PDT 24 29069927 ps
T1157 /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.3573703484 Jun 10 05:09:43 PM PDT 24 Jun 10 05:09:45 PM PDT 24 45608244 ps
T1158 /workspace/coverage/cover_reg_top/14.uart_tl_errors.4148533826 Jun 10 05:09:50 PM PDT 24 Jun 10 05:09:53 PM PDT 24 83114704 ps
T1159 /workspace/coverage/cover_reg_top/10.uart_tl_errors.2321212009 Jun 10 05:09:37 PM PDT 24 Jun 10 05:09:42 PM PDT 24 141280979 ps
T1160 /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.3258200087 Jun 10 05:09:29 PM PDT 24 Jun 10 05:09:37 PM PDT 24 71060453 ps
T1161 /workspace/coverage/cover_reg_top/16.uart_csr_rw.2560264484 Jun 10 05:09:33 PM PDT 24 Jun 10 05:09:35 PM PDT 24 50112877 ps
T1162 /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.4014727862 Jun 10 05:09:49 PM PDT 24 Jun 10 05:09:50 PM PDT 24 85702607 ps
T1163 /workspace/coverage/cover_reg_top/34.uart_intr_test.3031461395 Jun 10 05:09:52 PM PDT 24 Jun 10 05:09:53 PM PDT 24 13720214 ps
T1164 /workspace/coverage/cover_reg_top/19.uart_intr_test.4219434061 Jun 10 05:09:38 PM PDT 24 Jun 10 05:09:40 PM PDT 24 46539849 ps
T1165 /workspace/coverage/cover_reg_top/38.uart_intr_test.1455264720 Jun 10 05:09:41 PM PDT 24 Jun 10 05:09:43 PM PDT 24 54643536 ps
T1166 /workspace/coverage/cover_reg_top/1.uart_intr_test.532118879 Jun 10 05:09:29 PM PDT 24 Jun 10 05:09:30 PM PDT 24 14372235 ps
T136 /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.3554167485 Jun 10 05:09:43 PM PDT 24 Jun 10 05:09:44 PM PDT 24 40771668 ps
T1167 /workspace/coverage/cover_reg_top/20.uart_intr_test.3974472118 Jun 10 05:09:38 PM PDT 24 Jun 10 05:09:41 PM PDT 24 13632221 ps
T1168 /workspace/coverage/cover_reg_top/17.uart_tl_errors.4156550007 Jun 10 05:09:38 PM PDT 24 Jun 10 05:09:43 PM PDT 24 1284198464 ps
T1169 /workspace/coverage/cover_reg_top/37.uart_intr_test.2025194186 Jun 10 05:09:41 PM PDT 24 Jun 10 05:09:43 PM PDT 24 16038175 ps
T95 /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.3073917614 Jun 10 05:09:41 PM PDT 24 Jun 10 05:09:43 PM PDT 24 346151976 ps
T1170 /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.2621317989 Jun 10 05:10:01 PM PDT 24 Jun 10 05:10:02 PM PDT 24 36566620 ps
T1171 /workspace/coverage/cover_reg_top/36.uart_intr_test.1485706564 Jun 10 05:09:44 PM PDT 24 Jun 10 05:09:45 PM PDT 24 55304615 ps
T1172 /workspace/coverage/cover_reg_top/4.uart_intr_test.1621115014 Jun 10 05:09:42 PM PDT 24 Jun 10 05:09:43 PM PDT 24 31578101 ps
T1173 /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.2842653132 Jun 10 05:09:57 PM PDT 24 Jun 10 05:09:58 PM PDT 24 93354254 ps
T75 /workspace/coverage/cover_reg_top/18.uart_csr_rw.3219023091 Jun 10 05:09:37 PM PDT 24 Jun 10 05:09:40 PM PDT 24 56039614 ps
T1174 /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.152694671 Jun 10 05:09:51 PM PDT 24 Jun 10 05:09:52 PM PDT 24 26582550 ps
T1175 /workspace/coverage/cover_reg_top/11.uart_csr_rw.1140881284 Jun 10 05:09:42 PM PDT 24 Jun 10 05:09:43 PM PDT 24 26370820 ps
T1176 /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.1041251115 Jun 10 05:09:58 PM PDT 24 Jun 10 05:09:59 PM PDT 24 32634594 ps
T1177 /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.446036374 Jun 10 05:09:37 PM PDT 24 Jun 10 05:09:40 PM PDT 24 45466878 ps
T1178 /workspace/coverage/cover_reg_top/0.uart_intr_test.3911461920 Jun 10 05:09:47 PM PDT 24 Jun 10 05:09:48 PM PDT 24 22698348 ps
T1179 /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.122003885 Jun 10 05:09:50 PM PDT 24 Jun 10 05:09:52 PM PDT 24 97492198 ps
T76 /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.3384069349 Jun 10 05:09:30 PM PDT 24 Jun 10 05:09:32 PM PDT 24 147302376 ps
T1180 /workspace/coverage/cover_reg_top/8.uart_csr_rw.3729289993 Jun 10 05:09:34 PM PDT 24 Jun 10 05:09:36 PM PDT 24 50677858 ps
T1181 /workspace/coverage/cover_reg_top/8.uart_tl_errors.1675816972 Jun 10 05:09:43 PM PDT 24 Jun 10 05:09:44 PM PDT 24 65341825 ps
T1182 /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.999791304 Jun 10 05:09:34 PM PDT 24 Jun 10 05:09:41 PM PDT 24 99456376 ps
T1183 /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.548021065 Jun 10 05:09:50 PM PDT 24 Jun 10 05:09:52 PM PDT 24 34065961 ps
T1184 /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.757882059 Jun 10 05:09:46 PM PDT 24 Jun 10 05:09:47 PM PDT 24 44108745 ps
T1185 /workspace/coverage/cover_reg_top/8.uart_intr_test.4166268496 Jun 10 05:09:42 PM PDT 24 Jun 10 05:09:43 PM PDT 24 14981350 ps
T1186 /workspace/coverage/cover_reg_top/5.uart_intr_test.1556282615 Jun 10 05:09:32 PM PDT 24 Jun 10 05:09:34 PM PDT 24 37483263 ps
T1187 /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.3676662545 Jun 10 05:09:38 PM PDT 24 Jun 10 05:09:41 PM PDT 24 22385858 ps
T1188 /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.2781926854 Jun 10 05:09:36 PM PDT 24 Jun 10 05:09:38 PM PDT 24 125018252 ps
T1189 /workspace/coverage/cover_reg_top/15.uart_csr_rw.2843602250 Jun 10 05:09:39 PM PDT 24 Jun 10 05:09:41 PM PDT 24 15951218 ps
T1190 /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.3527527972 Jun 10 05:09:33 PM PDT 24 Jun 10 05:09:36 PM PDT 24 89997213 ps
T1191 /workspace/coverage/cover_reg_top/29.uart_intr_test.2508531212 Jun 10 05:09:47 PM PDT 24 Jun 10 05:09:48 PM PDT 24 41376702 ps
T1192 /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.2164871217 Jun 10 05:09:57 PM PDT 24 Jun 10 05:09:58 PM PDT 24 16691633 ps
T1193 /workspace/coverage/cover_reg_top/17.uart_intr_test.1590603488 Jun 10 05:09:46 PM PDT 24 Jun 10 05:09:47 PM PDT 24 38956886 ps
T1194 /workspace/coverage/cover_reg_top/16.uart_tl_errors.1676619159 Jun 10 05:10:05 PM PDT 24 Jun 10 05:10:07 PM PDT 24 82450204 ps
T1195 /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.1234292985 Jun 10 05:09:38 PM PDT 24 Jun 10 05:09:41 PM PDT 24 36153036 ps
T1196 /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.334900030 Jun 10 05:09:36 PM PDT 24 Jun 10 05:09:38 PM PDT 24 36050141 ps
T1197 /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.315072938 Jun 10 05:09:49 PM PDT 24 Jun 10 05:09:50 PM PDT 24 97692412 ps
T1198 /workspace/coverage/cover_reg_top/12.uart_csr_rw.2766870111 Jun 10 05:09:37 PM PDT 24 Jun 10 05:09:39 PM PDT 24 19967594 ps
T1199 /workspace/coverage/cover_reg_top/14.uart_csr_rw.1565425338 Jun 10 05:09:38 PM PDT 24 Jun 10 05:09:41 PM PDT 24 43877655 ps
T1200 /workspace/coverage/cover_reg_top/33.uart_intr_test.535588781 Jun 10 05:09:38 PM PDT 24 Jun 10 05:09:41 PM PDT 24 18332001 ps
T1201 /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.3652544983 Jun 10 05:09:48 PM PDT 24 Jun 10 05:09:50 PM PDT 24 20441175 ps
T1202 /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.418680641 Jun 10 05:09:42 PM PDT 24 Jun 10 05:09:44 PM PDT 24 93037606 ps
T1203 /workspace/coverage/cover_reg_top/25.uart_intr_test.301563935 Jun 10 05:09:39 PM PDT 24 Jun 10 05:09:41 PM PDT 24 16929142 ps
T1204 /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.819476774 Jun 10 05:09:41 PM PDT 24 Jun 10 05:09:43 PM PDT 24 57408328 ps
T1205 /workspace/coverage/cover_reg_top/26.uart_intr_test.3397588256 Jun 10 05:09:41 PM PDT 24 Jun 10 05:09:43 PM PDT 24 40275757 ps
T1206 /workspace/coverage/cover_reg_top/28.uart_intr_test.2714689807 Jun 10 05:09:45 PM PDT 24 Jun 10 05:09:46 PM PDT 24 28814124 ps
T1207 /workspace/coverage/cover_reg_top/16.uart_intr_test.2054844073 Jun 10 05:09:36 PM PDT 24 Jun 10 05:09:38 PM PDT 24 19506538 ps
T1208 /workspace/coverage/cover_reg_top/22.uart_intr_test.1109925741 Jun 10 05:09:36 PM PDT 24 Jun 10 05:09:39 PM PDT 24 12886363 ps
T1209 /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.3250170495 Jun 10 05:09:46 PM PDT 24 Jun 10 05:09:47 PM PDT 24 70561752 ps
T1210 /workspace/coverage/cover_reg_top/6.uart_csr_rw.4233445380 Jun 10 05:09:34 PM PDT 24 Jun 10 05:09:36 PM PDT 24 15990883 ps
T1211 /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.1179535246 Jun 10 05:09:38 PM PDT 24 Jun 10 05:09:40 PM PDT 24 65503284 ps
T1212 /workspace/coverage/cover_reg_top/43.uart_intr_test.1897639981 Jun 10 05:09:38 PM PDT 24 Jun 10 05:09:41 PM PDT 24 14014047 ps
T1213 /workspace/coverage/cover_reg_top/4.uart_csr_rw.1276425830 Jun 10 05:09:32 PM PDT 24 Jun 10 05:09:33 PM PDT 24 13951555 ps
T1214 /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.175587120 Jun 10 05:09:32 PM PDT 24 Jun 10 05:09:34 PM PDT 24 502430993 ps
T1215 /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.1126695153 Jun 10 05:09:33 PM PDT 24 Jun 10 05:09:36 PM PDT 24 180495687 ps
T1216 /workspace/coverage/cover_reg_top/13.uart_csr_rw.2917312034 Jun 10 05:09:44 PM PDT 24 Jun 10 05:09:45 PM PDT 24 41649942 ps
T1217 /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.1045623184 Jun 10 05:09:49 PM PDT 24 Jun 10 05:09:50 PM PDT 24 435061519 ps
T96 /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.2638579459 Jun 10 05:09:31 PM PDT 24 Jun 10 05:09:32 PM PDT 24 600791217 ps
T1218 /workspace/coverage/cover_reg_top/41.uart_intr_test.1242531008 Jun 10 05:09:45 PM PDT 24 Jun 10 05:09:46 PM PDT 24 53816347 ps
T1219 /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.2290937266 Jun 10 05:09:33 PM PDT 24 Jun 10 05:09:34 PM PDT 24 32803346 ps
T1220 /workspace/coverage/cover_reg_top/6.uart_intr_test.2241027672 Jun 10 05:09:45 PM PDT 24 Jun 10 05:09:46 PM PDT 24 43360284 ps
T1221 /workspace/coverage/cover_reg_top/31.uart_intr_test.2888290413 Jun 10 05:09:52 PM PDT 24 Jun 10 05:09:52 PM PDT 24 23013219 ps
T1222 /workspace/coverage/cover_reg_top/24.uart_intr_test.61496363 Jun 10 05:09:38 PM PDT 24 Jun 10 05:09:40 PM PDT 24 23822023 ps
T1223 /workspace/coverage/cover_reg_top/13.uart_tl_errors.3494337025 Jun 10 05:09:49 PM PDT 24 Jun 10 05:09:51 PM PDT 24 525857169 ps
T1224 /workspace/coverage/cover_reg_top/12.uart_tl_errors.3198735828 Jun 10 05:09:36 PM PDT 24 Jun 10 05:09:40 PM PDT 24 317352456 ps
T1225 /workspace/coverage/cover_reg_top/0.uart_tl_errors.1153077636 Jun 10 05:09:26 PM PDT 24 Jun 10 05:09:29 PM PDT 24 675222689 ps
T1226 /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.1542933775 Jun 10 05:09:35 PM PDT 24 Jun 10 05:09:37 PM PDT 24 113774311 ps
T1227 /workspace/coverage/cover_reg_top/45.uart_intr_test.162148674 Jun 10 05:09:41 PM PDT 24 Jun 10 05:09:42 PM PDT 24 18817903 ps

Test location /workspace/coverage/default/257.uart_fifo_reset.3101490399
Short name T10
Test name
Test status
Simulation time 18908385121 ps
CPU time 33 seconds
Started Jun 10 05:15:59 PM PDT 24
Finished Jun 10 05:16:33 PM PDT 24
Peak memory 200372 kb
Host smart-2399633f-7734-49a0-898f-81b5998c7b3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101490399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.3101490399
Directory /workspace/257.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_stress_all_with_rand_reset.1127637727
Short name T13
Test name
Test status
Simulation time 162437506581 ps
CPU time 1267.54 seconds
Started Jun 10 05:13:16 PM PDT 24
Finished Jun 10 05:34:24 PM PDT 24
Peak memory 225128 kb
Host smart-99e0c88f-d58b-4eb6-a82e-e3ddf75fe974
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127637727 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 9.uart_stress_all_with_rand_reset.1127637727
Directory /workspace/9.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/66.uart_stress_all_with_rand_reset.2971077047
Short name T33
Test name
Test status
Simulation time 122634875355 ps
CPU time 421.69 seconds
Started Jun 10 05:15:04 PM PDT 24
Finished Jun 10 05:22:06 PM PDT 24
Peak memory 217016 kb
Host smart-d242a2fb-6d1d-4bc9-95fb-b502e20b4793
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971077047 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 66.uart_stress_all_with_rand_reset.2971077047
Directory /workspace/66.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.uart_stress_all.2278521047
Short name T155
Test name
Test status
Simulation time 391137502736 ps
CPU time 1787.97 seconds
Started Jun 10 05:13:20 PM PDT 24
Finished Jun 10 05:43:08 PM PDT 24
Peak memory 200312 kb
Host smart-0348e324-fbbd-4d34-b101-32f199d72344
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278521047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.2278521047
Directory /workspace/10.uart_stress_all/latest

Test location /workspace/coverage/default/56.uart_stress_all_with_rand_reset.1942421077
Short name T22
Test name
Test status
Simulation time 73549031869 ps
CPU time 962.58 seconds
Started Jun 10 05:15:07 PM PDT 24
Finished Jun 10 05:31:10 PM PDT 24
Peak memory 216776 kb
Host smart-5087a227-8d26-43cd-9a8f-c71133914f30
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942421077 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 56.uart_stress_all_with_rand_reset.1942421077
Directory /workspace/56.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.uart_stress_all.916039753
Short name T132
Test name
Test status
Simulation time 491448278940 ps
CPU time 277.08 seconds
Started Jun 10 05:14:05 PM PDT 24
Finished Jun 10 05:18:42 PM PDT 24
Peak memory 200200 kb
Host smart-2e30c8cb-11f2-48b8-9de0-fd44bb2247cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916039753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.916039753
Directory /workspace/23.uart_stress_all/latest

Test location /workspace/coverage/default/44.uart_stress_all.2639253088
Short name T15
Test name
Test status
Simulation time 118694055315 ps
CPU time 230.67 seconds
Started Jun 10 05:14:42 PM PDT 24
Finished Jun 10 05:18:33 PM PDT 24
Peak memory 200344 kb
Host smart-fa27ac77-20f7-488f-bdb2-b64c28c22450
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639253088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.2639253088
Directory /workspace/44.uart_stress_all/latest

Test location /workspace/coverage/default/22.uart_perf.651309059
Short name T4
Test name
Test status
Simulation time 22543394336 ps
CPU time 544.93 seconds
Started Jun 10 05:13:46 PM PDT 24
Finished Jun 10 05:22:51 PM PDT 24
Peak memory 200252 kb
Host smart-5798ddb1-d545-4e9e-b5ba-a744c5150f27
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=651309059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.651309059
Directory /workspace/22.uart_perf/latest

Test location /workspace/coverage/default/13.uart_fifo_reset.3841734799
Short name T7
Test name
Test status
Simulation time 96740808498 ps
CPU time 156.06 seconds
Started Jun 10 05:13:26 PM PDT 24
Finished Jun 10 05:16:02 PM PDT 24
Peak memory 200324 kb
Host smart-ae1a4d57-0441-41cf-ba99-98ce1c3912e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841734799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.3841734799
Directory /workspace/13.uart_fifo_reset/latest

Test location /workspace/coverage/default/51.uart_stress_all_with_rand_reset.852974479
Short name T173
Test name
Test status
Simulation time 630742476215 ps
CPU time 1098.38 seconds
Started Jun 10 05:15:02 PM PDT 24
Finished Jun 10 05:33:21 PM PDT 24
Peak memory 225028 kb
Host smart-2064c108-b0fa-4e71-8205-3fe7f0c53dae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852974479 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 51.uart_stress_all_with_rand_reset.852974479
Directory /workspace/51.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/101.uart_fifo_reset.2430647728
Short name T56
Test name
Test status
Simulation time 136590897531 ps
CPU time 61.88 seconds
Started Jun 10 05:15:22 PM PDT 24
Finished Jun 10 05:16:24 PM PDT 24
Peak memory 200300 kb
Host smart-60b13b4c-b072-4191-8b77-b1697ee8dbf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430647728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.2430647728
Directory /workspace/101.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_sec_cm.3744496582
Short name T27
Test name
Test status
Simulation time 199557417 ps
CPU time 0.82 seconds
Started Jun 10 05:12:36 PM PDT 24
Finished Jun 10 05:12:37 PM PDT 24
Peak memory 218580 kb
Host smart-57f022de-8081-44da-84b1-c70fa6ba4d88
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744496582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.3744496582
Directory /workspace/0.uart_sec_cm/latest

Test location /workspace/coverage/default/15.uart_alert_test.4164444810
Short name T24
Test name
Test status
Simulation time 158853257 ps
CPU time 0.57 seconds
Started Jun 10 05:13:30 PM PDT 24
Finished Jun 10 05:13:32 PM PDT 24
Peak memory 195676 kb
Host smart-4397feb6-6f95-449f-89e1-4f1bbe0eb835
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164444810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.4164444810
Directory /workspace/15.uart_alert_test/latest

Test location /workspace/coverage/default/32.uart_fifo_full.3241846964
Short name T45
Test name
Test status
Simulation time 33173541150 ps
CPU time 55.36 seconds
Started Jun 10 05:14:10 PM PDT 24
Finished Jun 10 05:15:06 PM PDT 24
Peak memory 200268 kb
Host smart-dde458e4-501f-4f76-9b0b-b439221aca5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241846964 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.3241846964
Directory /workspace/32.uart_fifo_full/latest

Test location /workspace/coverage/default/213.uart_fifo_reset.2742117658
Short name T139
Test name
Test status
Simulation time 77211205794 ps
CPU time 131.66 seconds
Started Jun 10 05:15:44 PM PDT 24
Finished Jun 10 05:17:56 PM PDT 24
Peak memory 200344 kb
Host smart-8829cc7e-d264-46d9-b1eb-0de83bcfe063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742117658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.2742117658
Directory /workspace/213.uart_fifo_reset/latest

Test location /workspace/coverage/default/99.uart_stress_all_with_rand_reset.2632311415
Short name T113
Test name
Test status
Simulation time 80060222705 ps
CPU time 248 seconds
Started Jun 10 05:15:24 PM PDT 24
Finished Jun 10 05:19:32 PM PDT 24
Peak memory 215960 kb
Host smart-015e58e8-32d9-4f10-8842-0c623918c515
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632311415 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 99.uart_stress_all_with_rand_reset.2632311415
Directory /workspace/99.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.uart_tx_rx.655447112
Short name T266
Test name
Test status
Simulation time 290304861639 ps
CPU time 56.38 seconds
Started Jun 10 05:13:47 PM PDT 24
Finished Jun 10 05:14:44 PM PDT 24
Peak memory 200128 kb
Host smart-f5ff12ec-b5d6-4466-9743-0ffa2db1a111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655447112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.655447112
Directory /workspace/23.uart_tx_rx/latest

Test location /workspace/coverage/default/266.uart_fifo_reset.532957295
Short name T190
Test name
Test status
Simulation time 81451040973 ps
CPU time 216.61 seconds
Started Jun 10 05:16:04 PM PDT 24
Finished Jun 10 05:19:41 PM PDT 24
Peak memory 200252 kb
Host smart-5141bfce-9def-473e-90bd-4826e0127deb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532957295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.532957295
Directory /workspace/266.uart_fifo_reset/latest

Test location /workspace/coverage/default/38.uart_fifo_full.3604259877
Short name T151
Test name
Test status
Simulation time 50586062028 ps
CPU time 42.5 seconds
Started Jun 10 05:14:44 PM PDT 24
Finished Jun 10 05:15:27 PM PDT 24
Peak memory 200296 kb
Host smart-b6305668-6db0-48b9-8e74-19deea35f79d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604259877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.3604259877
Directory /workspace/38.uart_fifo_full/latest

Test location /workspace/coverage/default/20.uart_fifo_overflow.2718487240
Short name T140
Test name
Test status
Simulation time 169735879303 ps
CPU time 317.39 seconds
Started Jun 10 05:13:34 PM PDT 24
Finished Jun 10 05:18:52 PM PDT 24
Peak memory 200156 kb
Host smart-056cb323-06cf-4886-a09b-7e35fae07310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718487240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.2718487240
Directory /workspace/20.uart_fifo_overflow/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.1349113025
Short name T98
Test name
Test status
Simulation time 287259184 ps
CPU time 1.22 seconds
Started Jun 10 05:09:45 PM PDT 24
Finished Jun 10 05:09:46 PM PDT 24
Peak memory 199812 kb
Host smart-5899688f-969c-4e05-b34f-5a5e96986155
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349113025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.1349113025
Directory /workspace/13.uart_tl_intg_err/latest

Test location /workspace/coverage/default/48.uart_stress_all.3636462164
Short name T129
Test name
Test status
Simulation time 278029921225 ps
CPU time 71.28 seconds
Started Jun 10 05:14:54 PM PDT 24
Finished Jun 10 05:16:06 PM PDT 24
Peak memory 200292 kb
Host smart-8940faaa-a7be-4446-899f-b6d1e8065799
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636462164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.3636462164
Directory /workspace/48.uart_stress_all/latest

Test location /workspace/coverage/default/234.uart_fifo_reset.2629819679
Short name T181
Test name
Test status
Simulation time 119476238810 ps
CPU time 43.45 seconds
Started Jun 10 05:15:50 PM PDT 24
Finished Jun 10 05:16:33 PM PDT 24
Peak memory 200300 kb
Host smart-4410fde4-f619-4cef-920f-ce59a852a86f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629819679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.2629819679
Directory /workspace/234.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_stress_all_with_rand_reset.335615900
Short name T133
Test name
Test status
Simulation time 266894918866 ps
CPU time 948.76 seconds
Started Jun 10 05:13:30 PM PDT 24
Finished Jun 10 05:29:20 PM PDT 24
Peak memory 227452 kb
Host smart-4ecd08e0-af82-4f6a-9b49-661d3fb95236
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335615900 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 15.uart_stress_all_with_rand_reset.335615900
Directory /workspace/15.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.uart_stress_all_with_rand_reset.3335170787
Short name T35
Test name
Test status
Simulation time 66641589016 ps
CPU time 925.7 seconds
Started Jun 10 05:15:12 PM PDT 24
Finished Jun 10 05:30:38 PM PDT 24
Peak memory 216884 kb
Host smart-505903f3-cedc-4774-a991-95898bf033f0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335170787 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 86.uart_stress_all_with_rand_reset.3335170787
Directory /workspace/86.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/252.uart_fifo_reset.1471659793
Short name T228
Test name
Test status
Simulation time 168733715207 ps
CPU time 328.3 seconds
Started Jun 10 05:15:59 PM PDT 24
Finished Jun 10 05:21:27 PM PDT 24
Peak memory 200332 kb
Host smart-6dc61e0a-1993-450f-a367-416321be284d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471659793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.1471659793
Directory /workspace/252.uart_fifo_reset/latest

Test location /workspace/coverage/default/168.uart_fifo_reset.1205694892
Short name T289
Test name
Test status
Simulation time 139952184634 ps
CPU time 84.74 seconds
Started Jun 10 05:15:38 PM PDT 24
Finished Jun 10 05:17:03 PM PDT 24
Peak memory 200316 kb
Host smart-3bda2b47-8c7f-4c87-9780-8a2c3e0778ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205694892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.1205694892
Directory /workspace/168.uart_fifo_reset/latest

Test location /workspace/coverage/default/33.uart_stress_all_with_rand_reset.3819915695
Short name T30
Test name
Test status
Simulation time 33264651383 ps
CPU time 175.59 seconds
Started Jun 10 05:14:21 PM PDT 24
Finished Jun 10 05:17:17 PM PDT 24
Peak memory 216172 kb
Host smart-e351d0d1-ad00-46ad-a057-99cc346309b4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819915695 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 33.uart_stress_all_with_rand_reset.3819915695
Directory /workspace/33.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/74.uart_fifo_reset.1001065623
Short name T44
Test name
Test status
Simulation time 198746197948 ps
CPU time 18.05 seconds
Started Jun 10 05:15:07 PM PDT 24
Finished Jun 10 05:15:25 PM PDT 24
Peak memory 200240 kb
Host smart-850800da-6d80-4c92-a9f0-f252417b0f82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001065623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.1001065623
Directory /workspace/74.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_rw.913613035
Short name T85
Test name
Test status
Simulation time 19348167 ps
CPU time 0.69 seconds
Started Jun 10 05:10:02 PM PDT 24
Finished Jun 10 05:10:03 PM PDT 24
Peak memory 196108 kb
Host smart-d053ec5d-720f-481d-8b0a-7f8d0436a362
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913613035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.913613035
Directory /workspace/0.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_rw.3219023091
Short name T75
Test name
Test status
Simulation time 56039614 ps
CPU time 0.61 seconds
Started Jun 10 05:09:37 PM PDT 24
Finished Jun 10 05:09:40 PM PDT 24
Peak memory 195992 kb
Host smart-a857f45c-c15e-4509-b621-e189585621fe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219023091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.3219023091
Directory /workspace/18.uart_csr_rw/latest

Test location /workspace/coverage/default/41.uart_stress_all.857147894
Short name T319
Test name
Test status
Simulation time 328676893110 ps
CPU time 590.53 seconds
Started Jun 10 05:14:32 PM PDT 24
Finished Jun 10 05:24:23 PM PDT 24
Peak memory 200320 kb
Host smart-709afc73-a38b-4ff0-a70a-e69bc2217972
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857147894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.857147894
Directory /workspace/41.uart_stress_all/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.1276960759
Short name T93
Test name
Test status
Simulation time 883381648 ps
CPU time 1.02 seconds
Started Jun 10 05:09:33 PM PDT 24
Finished Jun 10 05:09:35 PM PDT 24
Peak memory 200016 kb
Host smart-54aec418-a609-4336-ad7b-c592ad198c83
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276960759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.1276960759
Directory /workspace/4.uart_tl_intg_err/latest

Test location /workspace/coverage/default/26.uart_fifo_overflow.3625388478
Short name T54
Test name
Test status
Simulation time 45997528787 ps
CPU time 72.63 seconds
Started Jun 10 05:13:59 PM PDT 24
Finished Jun 10 05:15:11 PM PDT 24
Peak memory 200308 kb
Host smart-58d62a24-6e12-46bd-8a00-efd07df103a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625388478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.3625388478
Directory /workspace/26.uart_fifo_overflow/latest

Test location /workspace/coverage/default/29.uart_fifo_overflow.467426011
Short name T158
Test name
Test status
Simulation time 161039608727 ps
CPU time 191.46 seconds
Started Jun 10 05:13:57 PM PDT 24
Finished Jun 10 05:17:09 PM PDT 24
Peak memory 200328 kb
Host smart-500a950b-e152-436d-b461-aedd42b1df8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467426011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.467426011
Directory /workspace/29.uart_fifo_overflow/latest

Test location /workspace/coverage/default/0.uart_stress_all_with_rand_reset.3374747433
Short name T313
Test name
Test status
Simulation time 151377566671 ps
CPU time 382.74 seconds
Started Jun 10 05:12:35 PM PDT 24
Finished Jun 10 05:18:58 PM PDT 24
Peak memory 216928 kb
Host smart-5b5e6db9-3db6-43be-968d-64d48b80b7ac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374747433 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.uart_stress_all_with_rand_reset.3374747433
Directory /workspace/0.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/149.uart_fifo_reset.1732851929
Short name T167
Test name
Test status
Simulation time 239377760755 ps
CPU time 28.13 seconds
Started Jun 10 05:15:30 PM PDT 24
Finished Jun 10 05:15:59 PM PDT 24
Peak memory 200228 kb
Host smart-569b7247-14c2-4016-bd4b-b2ee2344daf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732851929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.1732851929
Directory /workspace/149.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_rx_parity_err.4067003511
Short name T161
Test name
Test status
Simulation time 18097094617 ps
CPU time 27.89 seconds
Started Jun 10 05:13:54 PM PDT 24
Finished Jun 10 05:14:23 PM PDT 24
Peak memory 200392 kb
Host smart-c583a7b5-5568-4cea-a474-c12a97d74c29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067003511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.4067003511
Directory /workspace/26.uart_rx_parity_err/latest

Test location /workspace/coverage/default/270.uart_fifo_reset.3020424604
Short name T146
Test name
Test status
Simulation time 109879837530 ps
CPU time 101.95 seconds
Started Jun 10 05:16:12 PM PDT 24
Finished Jun 10 05:17:54 PM PDT 24
Peak memory 200248 kb
Host smart-fd73275b-2db4-43ab-a9a8-006428eadc63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020424604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.3020424604
Directory /workspace/270.uart_fifo_reset/latest

Test location /workspace/coverage/default/93.uart_fifo_reset.3177781943
Short name T309
Test name
Test status
Simulation time 69879084801 ps
CPU time 443.53 seconds
Started Jun 10 05:15:15 PM PDT 24
Finished Jun 10 05:22:39 PM PDT 24
Peak memory 200380 kb
Host smart-cbfe1d70-3f94-4e15-9f74-3462c435a838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177781943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.3177781943
Directory /workspace/93.uart_fifo_reset/latest

Test location /workspace/coverage/default/145.uart_fifo_reset.1951635923
Short name T42
Test name
Test status
Simulation time 132698010995 ps
CPU time 55.11 seconds
Started Jun 10 05:15:31 PM PDT 24
Finished Jun 10 05:16:26 PM PDT 24
Peak memory 200304 kb
Host smart-3edd12e6-54d7-4dfe-8bc1-14e78927efc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951635923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.1951635923
Directory /workspace/145.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_intr.162506495
Short name T314
Test name
Test status
Simulation time 15001253270 ps
CPU time 28.95 seconds
Started Jun 10 05:12:42 PM PDT 24
Finished Jun 10 05:13:11 PM PDT 24
Peak memory 199780 kb
Host smart-74a47677-2d29-49fe-a0ea-a6ed803e2317
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162506495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.162506495
Directory /workspace/0.uart_intr/latest

Test location /workspace/coverage/default/172.uart_fifo_reset.2024311361
Short name T229
Test name
Test status
Simulation time 21654266190 ps
CPU time 62.36 seconds
Started Jun 10 05:15:38 PM PDT 24
Finished Jun 10 05:16:41 PM PDT 24
Peak memory 200176 kb
Host smart-7360b0c4-f113-4a39-bf53-c78d6bb2e25d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024311361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.2024311361
Directory /workspace/172.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_perf.126946866
Short name T49
Test name
Test status
Simulation time 7786437227 ps
CPU time 451.92 seconds
Started Jun 10 05:12:41 PM PDT 24
Finished Jun 10 05:20:14 PM PDT 24
Peak memory 200536 kb
Host smart-451ee189-e921-4209-b52d-be6b55c15f89
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=126946866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.126946866
Directory /workspace/0.uart_perf/latest

Test location /workspace/coverage/default/17.uart_stress_all_with_rand_reset.3395156731
Short name T19
Test name
Test status
Simulation time 8620487890 ps
CPU time 123.21 seconds
Started Jun 10 05:13:34 PM PDT 24
Finished Jun 10 05:15:38 PM PDT 24
Peak memory 216784 kb
Host smart-548406a5-0150-4b94-954e-ffa1132335b8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395156731 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 17.uart_stress_all_with_rand_reset.3395156731
Directory /workspace/17.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/202.uart_fifo_reset.808899031
Short name T6
Test name
Test status
Simulation time 31370020764 ps
CPU time 49.56 seconds
Started Jun 10 05:15:39 PM PDT 24
Finished Jun 10 05:16:29 PM PDT 24
Peak memory 200348 kb
Host smart-7ba52258-f2d3-4e7f-b547-0b2d4cd2cada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808899031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.808899031
Directory /workspace/202.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_fifo_full.2511560219
Short name T52
Test name
Test status
Simulation time 136824288568 ps
CPU time 163.32 seconds
Started Jun 10 05:12:40 PM PDT 24
Finished Jun 10 05:15:24 PM PDT 24
Peak memory 200164 kb
Host smart-0a9f5f24-a0a1-4cd4-9e59-e592cd0a7723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511560219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.2511560219
Directory /workspace/0.uart_fifo_full/latest

Test location /workspace/coverage/default/157.uart_fifo_reset.1816586159
Short name T250
Test name
Test status
Simulation time 41067611684 ps
CPU time 11.77 seconds
Started Jun 10 05:15:33 PM PDT 24
Finished Jun 10 05:15:45 PM PDT 24
Peak memory 200204 kb
Host smart-a6e25613-a4d7-4f38-8dbc-0b55081e8606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816586159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.1816586159
Directory /workspace/157.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_fifo_reset.2960368732
Short name T198
Test name
Test status
Simulation time 29450945602 ps
CPU time 24.17 seconds
Started Jun 10 05:13:39 PM PDT 24
Finished Jun 10 05:14:04 PM PDT 24
Peak memory 200176 kb
Host smart-bbcf7117-cec6-4577-9813-a1083b932d08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960368732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.2960368732
Directory /workspace/16.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_perf.3233561089
Short name T125
Test name
Test status
Simulation time 14639124918 ps
CPU time 193.68 seconds
Started Jun 10 05:13:36 PM PDT 24
Finished Jun 10 05:16:51 PM PDT 24
Peak memory 200304 kb
Host smart-f5834636-1296-41bf-bfe9-04cbd187e66c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3233561089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.3233561089
Directory /workspace/18.uart_perf/latest

Test location /workspace/coverage/default/72.uart_fifo_reset.3716219505
Short name T212
Test name
Test status
Simulation time 40493667987 ps
CPU time 38.18 seconds
Started Jun 10 05:15:07 PM PDT 24
Finished Jun 10 05:15:46 PM PDT 24
Peak memory 200348 kb
Host smart-13a03a50-216d-4ce2-a40d-1c83c41c923e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716219505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.3716219505
Directory /workspace/72.uart_fifo_reset/latest

Test location /workspace/coverage/default/100.uart_fifo_reset.2761201717
Short name T224
Test name
Test status
Simulation time 110395839869 ps
CPU time 45.3 seconds
Started Jun 10 05:15:29 PM PDT 24
Finished Jun 10 05:16:14 PM PDT 24
Peak memory 200220 kb
Host smart-f2253ab4-8671-4607-8188-935d6d4767ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761201717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.2761201717
Directory /workspace/100.uart_fifo_reset/latest

Test location /workspace/coverage/default/123.uart_fifo_reset.1695563065
Short name T503
Test name
Test status
Simulation time 140261088130 ps
CPU time 156.46 seconds
Started Jun 10 05:15:25 PM PDT 24
Finished Jun 10 05:18:02 PM PDT 24
Peak memory 200240 kb
Host smart-1d4644a4-abda-43e8-b7b9-365d47e136c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695563065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.1695563065
Directory /workspace/123.uart_fifo_reset/latest

Test location /workspace/coverage/default/133.uart_fifo_reset.1423730211
Short name T204
Test name
Test status
Simulation time 81187844774 ps
CPU time 348.57 seconds
Started Jun 10 05:15:27 PM PDT 24
Finished Jun 10 05:21:16 PM PDT 24
Peak memory 200216 kb
Host smart-fea13868-35e2-449b-b82a-1944401ad54b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423730211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.1423730211
Directory /workspace/133.uart_fifo_reset/latest

Test location /workspace/coverage/default/155.uart_fifo_reset.3605244933
Short name T239
Test name
Test status
Simulation time 20780700949 ps
CPU time 19.75 seconds
Started Jun 10 05:15:31 PM PDT 24
Finished Jun 10 05:15:51 PM PDT 24
Peak memory 200360 kb
Host smart-31080535-a330-41ae-b7aa-2e72f16f942d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605244933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.3605244933
Directory /workspace/155.uart_fifo_reset/latest

Test location /workspace/coverage/default/182.uart_fifo_reset.710980578
Short name T156
Test name
Test status
Simulation time 50293902490 ps
CPU time 21.92 seconds
Started Jun 10 05:15:37 PM PDT 24
Finished Jun 10 05:15:59 PM PDT 24
Peak memory 200364 kb
Host smart-17febb44-8a69-4407-b185-dc83215cdd3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710980578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.710980578
Directory /workspace/182.uart_fifo_reset/latest

Test location /workspace/coverage/default/183.uart_fifo_reset.2442446389
Short name T178
Test name
Test status
Simulation time 34227742594 ps
CPU time 40.14 seconds
Started Jun 10 05:15:35 PM PDT 24
Finished Jun 10 05:16:16 PM PDT 24
Peak memory 200244 kb
Host smart-7e0544ea-423f-43b1-b5cb-0f565be9f69c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442446389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.2442446389
Directory /workspace/183.uart_fifo_reset/latest

Test location /workspace/coverage/default/186.uart_fifo_reset.2645067011
Short name T196
Test name
Test status
Simulation time 45948297162 ps
CPU time 27.81 seconds
Started Jun 10 05:15:41 PM PDT 24
Finished Jun 10 05:16:09 PM PDT 24
Peak memory 200248 kb
Host smart-8f5c0b50-7855-4129-8c5c-66192fca33d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645067011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.2645067011
Directory /workspace/186.uart_fifo_reset/latest

Test location /workspace/coverage/default/276.uart_fifo_reset.2262060126
Short name T246
Test name
Test status
Simulation time 161901313235 ps
CPU time 53.83 seconds
Started Jun 10 05:16:11 PM PDT 24
Finished Jun 10 05:17:05 PM PDT 24
Peak memory 200376 kb
Host smart-6e2143b5-d760-44eb-b195-3442f3738c8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262060126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.2262060126
Directory /workspace/276.uart_fifo_reset/latest

Test location /workspace/coverage/default/32.uart_rx_parity_err.3058554672
Short name T184
Test name
Test status
Simulation time 56904844576 ps
CPU time 26.51 seconds
Started Jun 10 05:14:09 PM PDT 24
Finished Jun 10 05:14:36 PM PDT 24
Peak memory 200284 kb
Host smart-45a57b1c-51e8-40eb-b2be-ec9452ce8579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058554672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.3058554672
Directory /workspace/32.uart_rx_parity_err/latest

Test location /workspace/coverage/default/45.uart_fifo_reset.3872276502
Short name T154
Test name
Test status
Simulation time 65897375353 ps
CPU time 33.95 seconds
Started Jun 10 05:14:47 PM PDT 24
Finished Jun 10 05:15:21 PM PDT 24
Peak memory 200384 kb
Host smart-4e3daa15-9037-49d6-b5ab-be78894652d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872276502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.3872276502
Directory /workspace/45.uart_fifo_reset/latest

Test location /workspace/coverage/default/47.uart_intr.2894063369
Short name T91
Test name
Test status
Simulation time 30053974981 ps
CPU time 13.54 seconds
Started Jun 10 05:14:48 PM PDT 24
Finished Jun 10 05:15:02 PM PDT 24
Peak memory 198636 kb
Host smart-1a96b6a3-908d-450f-9b51-3a8996659d8c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894063369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.2894063369
Directory /workspace/47.uart_intr/latest

Test location /workspace/coverage/default/70.uart_fifo_reset.3269162196
Short name T835
Test name
Test status
Simulation time 27684769635 ps
CPU time 8.05 seconds
Started Jun 10 05:15:07 PM PDT 24
Finished Jun 10 05:15:16 PM PDT 24
Peak memory 200120 kb
Host smart-9cfae749-bb35-40c0-b53c-4b0c6b6ee1dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269162196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.3269162196
Directory /workspace/70.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.3258200087
Short name T1160
Test name
Test status
Simulation time 71060453 ps
CPU time 1.34 seconds
Started Jun 10 05:09:29 PM PDT 24
Finished Jun 10 05:09:37 PM PDT 24
Peak memory 199984 kb
Host smart-dd7426c4-a5b3-4a04-b3f6-2920716aea9c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258200087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.3258200087
Directory /workspace/0.uart_tl_intg_err/latest

Test location /workspace/coverage/default/1.uart_fifo_full.1737028807
Short name T37
Test name
Test status
Simulation time 118733850919 ps
CPU time 188.1 seconds
Started Jun 10 05:12:33 PM PDT 24
Finished Jun 10 05:15:41 PM PDT 24
Peak memory 200292 kb
Host smart-4a25319e-453b-40cc-a15c-959db9cfe3fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737028807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.1737028807
Directory /workspace/1.uart_fifo_full/latest

Test location /workspace/coverage/default/1.uart_stress_all_with_rand_reset.1866844177
Short name T791
Test name
Test status
Simulation time 17783536595 ps
CPU time 279.74 seconds
Started Jun 10 05:12:43 PM PDT 24
Finished Jun 10 05:17:23 PM PDT 24
Peak memory 208736 kb
Host smart-37327d74-0e66-4e0c-8ad3-f592bdca2b02
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866844177 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.uart_stress_all_with_rand_reset.1866844177
Directory /workspace/1.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/108.uart_fifo_reset.3959293433
Short name T248
Test name
Test status
Simulation time 132190508438 ps
CPU time 31.71 seconds
Started Jun 10 05:15:19 PM PDT 24
Finished Jun 10 05:15:51 PM PDT 24
Peak memory 200268 kb
Host smart-4003c2be-ef37-4c85-886b-a78af4ea93aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959293433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.3959293433
Directory /workspace/108.uart_fifo_reset/latest

Test location /workspace/coverage/default/113.uart_fifo_reset.3258340541
Short name T214
Test name
Test status
Simulation time 32756110451 ps
CPU time 33.01 seconds
Started Jun 10 05:15:22 PM PDT 24
Finished Jun 10 05:15:56 PM PDT 24
Peak memory 200268 kb
Host smart-168070f0-e7ab-48a9-9950-b7d824d437cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258340541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.3258340541
Directory /workspace/113.uart_fifo_reset/latest

Test location /workspace/coverage/default/117.uart_fifo_reset.4282367332
Short name T159
Test name
Test status
Simulation time 53471372802 ps
CPU time 35.31 seconds
Started Jun 10 05:15:18 PM PDT 24
Finished Jun 10 05:15:54 PM PDT 24
Peak memory 200512 kb
Host smart-a2fe5598-f61d-4251-8ae5-ee11447eb8dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282367332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.4282367332
Directory /workspace/117.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_tx_rx.1792562977
Short name T312
Test name
Test status
Simulation time 154263414451 ps
CPU time 28.46 seconds
Started Jun 10 05:13:25 PM PDT 24
Finished Jun 10 05:13:54 PM PDT 24
Peak memory 200380 kb
Host smart-56a35456-eab3-4f14-a038-c17acf5746d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792562977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.1792562977
Directory /workspace/12.uart_tx_rx/latest

Test location /workspace/coverage/default/120.uart_fifo_reset.4204698961
Short name T149
Test name
Test status
Simulation time 142945181647 ps
CPU time 70.79 seconds
Started Jun 10 05:15:23 PM PDT 24
Finished Jun 10 05:16:35 PM PDT 24
Peak memory 200292 kb
Host smart-40e1f6d2-e35d-4213-8175-d01925883b84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204698961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.4204698961
Directory /workspace/120.uart_fifo_reset/latest

Test location /workspace/coverage/default/125.uart_fifo_reset.1677981306
Short name T245
Test name
Test status
Simulation time 133990070556 ps
CPU time 52.84 seconds
Started Jun 10 05:15:26 PM PDT 24
Finished Jun 10 05:16:19 PM PDT 24
Peak memory 199996 kb
Host smart-637d1cb3-5b40-4f9f-a2bc-204ac39bbe17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677981306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.1677981306
Directory /workspace/125.uart_fifo_reset/latest

Test location /workspace/coverage/default/128.uart_fifo_reset.533617722
Short name T242
Test name
Test status
Simulation time 41047422032 ps
CPU time 24.12 seconds
Started Jun 10 05:15:28 PM PDT 24
Finished Jun 10 05:15:52 PM PDT 24
Peak memory 200340 kb
Host smart-88f28c8c-1cd8-4b87-b050-2cd9cf98122b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533617722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.533617722
Directory /workspace/128.uart_fifo_reset/latest

Test location /workspace/coverage/default/153.uart_fifo_reset.4215853307
Short name T137
Test name
Test status
Simulation time 40624534098 ps
CPU time 66.75 seconds
Started Jun 10 05:15:28 PM PDT 24
Finished Jun 10 05:16:35 PM PDT 24
Peak memory 200304 kb
Host smart-4fd9c9af-1709-42d5-822a-763aedb9d6bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215853307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.4215853307
Directory /workspace/153.uart_fifo_reset/latest

Test location /workspace/coverage/default/173.uart_fifo_reset.3810985240
Short name T221
Test name
Test status
Simulation time 102678275974 ps
CPU time 13.44 seconds
Started Jun 10 05:15:37 PM PDT 24
Finished Jun 10 05:15:50 PM PDT 24
Peak memory 200352 kb
Host smart-b9fbf783-106a-43e7-a99a-135fbb7b3cb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810985240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.3810985240
Directory /workspace/173.uart_fifo_reset/latest

Test location /workspace/coverage/default/185.uart_fifo_reset.3201993641
Short name T225
Test name
Test status
Simulation time 54833072705 ps
CPU time 143.06 seconds
Started Jun 10 05:15:41 PM PDT 24
Finished Jun 10 05:18:04 PM PDT 24
Peak memory 200360 kb
Host smart-f2fcce55-2e2d-4d89-8263-58cd3385b9fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201993641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.3201993641
Directory /workspace/185.uart_fifo_reset/latest

Test location /workspace/coverage/default/188.uart_fifo_reset.1851552006
Short name T227
Test name
Test status
Simulation time 76157155070 ps
CPU time 35.31 seconds
Started Jun 10 05:15:39 PM PDT 24
Finished Jun 10 05:16:15 PM PDT 24
Peak memory 200360 kb
Host smart-45a1b1f5-bdb1-41aa-99e1-d652070e3865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851552006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.1851552006
Directory /workspace/188.uart_fifo_reset/latest

Test location /workspace/coverage/default/189.uart_fifo_reset.3278976170
Short name T234
Test name
Test status
Simulation time 108714526691 ps
CPU time 167.22 seconds
Started Jun 10 05:15:41 PM PDT 24
Finished Jun 10 05:18:29 PM PDT 24
Peak memory 200360 kb
Host smart-1a647d13-de2d-4002-ae39-e3ad33a1b9d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278976170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.3278976170
Directory /workspace/189.uart_fifo_reset/latest

Test location /workspace/coverage/default/190.uart_fifo_reset.1364834480
Short name T233
Test name
Test status
Simulation time 10238251909 ps
CPU time 23.48 seconds
Started Jun 10 05:15:42 PM PDT 24
Finished Jun 10 05:16:05 PM PDT 24
Peak memory 200256 kb
Host smart-4098ee0f-64e5-4280-8c82-9a123a8c71ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364834480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.1364834480
Directory /workspace/190.uart_fifo_reset/latest

Test location /workspace/coverage/default/197.uart_fifo_reset.2566136783
Short name T164
Test name
Test status
Simulation time 30731227955 ps
CPU time 8.54 seconds
Started Jun 10 05:15:41 PM PDT 24
Finished Jun 10 05:15:50 PM PDT 24
Peak memory 200084 kb
Host smart-acd76154-67b2-40e7-a71e-1de173003f01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566136783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.2566136783
Directory /workspace/197.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_fifo_reset.2132134448
Short name T249
Test name
Test status
Simulation time 97964841333 ps
CPU time 155.81 seconds
Started Jun 10 05:14:11 PM PDT 24
Finished Jun 10 05:16:47 PM PDT 24
Peak memory 200344 kb
Host smart-7560e6a7-3cc3-476c-8bee-50e05165b0f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132134448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.2132134448
Directory /workspace/30.uart_fifo_reset/latest

Test location /workspace/coverage/default/47.uart_fifo_reset.3788306803
Short name T238
Test name
Test status
Simulation time 39475462490 ps
CPU time 26.18 seconds
Started Jun 10 05:14:49 PM PDT 24
Finished Jun 10 05:15:16 PM PDT 24
Peak memory 200324 kb
Host smart-786d48d4-a0c7-4429-8dbb-92c89d6a8782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788306803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.3788306803
Directory /workspace/47.uart_fifo_reset/latest

Test location /workspace/coverage/default/48.uart_fifo_reset.2329285608
Short name T183
Test name
Test status
Simulation time 24646936246 ps
CPU time 8.95 seconds
Started Jun 10 05:14:53 PM PDT 24
Finished Jun 10 05:15:02 PM PDT 24
Peak memory 200052 kb
Host smart-74f67942-adef-467e-8b2f-3aa07c10d0d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329285608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.2329285608
Directory /workspace/48.uart_fifo_reset/latest

Test location /workspace/coverage/default/51.uart_fifo_reset.3124638272
Short name T237
Test name
Test status
Simulation time 30257000150 ps
CPU time 22.26 seconds
Started Jun 10 05:14:59 PM PDT 24
Finished Jun 10 05:15:21 PM PDT 24
Peak memory 200240 kb
Host smart-debe9b3d-1b61-4112-a1c3-77563bf662ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124638272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.3124638272
Directory /workspace/51.uart_fifo_reset/latest

Test location /workspace/coverage/default/76.uart_fifo_reset.770373365
Short name T241
Test name
Test status
Simulation time 203657633500 ps
CPU time 35.36 seconds
Started Jun 10 05:15:11 PM PDT 24
Finished Jun 10 05:15:47 PM PDT 24
Peak memory 200328 kb
Host smart-39f0f203-aefa-4b2c-a0f2-a449e9c03d2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770373365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.770373365
Directory /workspace/76.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.203534633
Short name T1097
Test name
Test status
Simulation time 22796388 ps
CPU time 0.65 seconds
Started Jun 10 05:09:40 PM PDT 24
Finished Jun 10 05:09:42 PM PDT 24
Peak memory 195368 kb
Host smart-7b9bf2d6-ab4b-4302-8f41-67fc366c8a6b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203534633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.203534633
Directory /workspace/0.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.3527527972
Short name T1190
Test name
Test status
Simulation time 89997213 ps
CPU time 2.32 seconds
Started Jun 10 05:09:33 PM PDT 24
Finished Jun 10 05:09:36 PM PDT 24
Peak memory 198392 kb
Host smart-a9f77f6a-7fae-4e6b-a8f8-5126b13cf0ac
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527527972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.3527527972
Directory /workspace/0.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.2083148943
Short name T1154
Test name
Test status
Simulation time 42031982 ps
CPU time 0.63 seconds
Started Jun 10 05:09:51 PM PDT 24
Finished Jun 10 05:09:52 PM PDT 24
Peak memory 195920 kb
Host smart-0d87746b-5c99-4b74-a6fc-76330942ae46
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083148943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.2083148943
Directory /workspace/0.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.2290937266
Short name T1219
Test name
Test status
Simulation time 32803346 ps
CPU time 0.77 seconds
Started Jun 10 05:09:33 PM PDT 24
Finished Jun 10 05:09:34 PM PDT 24
Peak memory 200496 kb
Host smart-ea4ea296-9f93-40fc-a7da-e687c94be02e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290937266 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.2290937266
Directory /workspace/0.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_intr_test.3911461920
Short name T1178
Test name
Test status
Simulation time 22698348 ps
CPU time 0.64 seconds
Started Jun 10 05:09:47 PM PDT 24
Finished Jun 10 05:09:48 PM PDT 24
Peak memory 195032 kb
Host smart-28503ed1-d85c-48f6-b9ea-7237ddf9bc5f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911461920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.3911461920
Directory /workspace/0.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.819476774
Short name T1204
Test name
Test status
Simulation time 57408328 ps
CPU time 0.67 seconds
Started Jun 10 05:09:41 PM PDT 24
Finished Jun 10 05:09:43 PM PDT 24
Peak memory 196056 kb
Host smart-fd20660f-e43a-4c2e-86b6-013015332541
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819476774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr_
outstanding.819476774
Directory /workspace/0.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_errors.1153077636
Short name T1225
Test name
Test status
Simulation time 675222689 ps
CPU time 1.89 seconds
Started Jun 10 05:09:26 PM PDT 24
Finished Jun 10 05:09:29 PM PDT 24
Peak memory 200692 kb
Host smart-0a94d0d5-51f3-4c4f-a78d-1ce88421e23a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153077636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.1153077636
Directory /workspace/0.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.3085499124
Short name T73
Test name
Test status
Simulation time 45946232 ps
CPU time 0.78 seconds
Started Jun 10 05:09:55 PM PDT 24
Finished Jun 10 05:09:56 PM PDT 24
Peak memory 197128 kb
Host smart-6350b3b4-1c73-46fe-a7c0-256d725bbfe2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085499124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.3085499124
Directory /workspace/1.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.1126695153
Short name T1215
Test name
Test status
Simulation time 180495687 ps
CPU time 2.44 seconds
Started Jun 10 05:09:33 PM PDT 24
Finished Jun 10 05:09:36 PM PDT 24
Peak memory 198252 kb
Host smart-9e8f44ed-d783-4025-8587-719e71317f09
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126695153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.1126695153
Directory /workspace/1.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.2327752206
Short name T63
Test name
Test status
Simulation time 14454940 ps
CPU time 0.58 seconds
Started Jun 10 05:09:41 PM PDT 24
Finished Jun 10 05:09:43 PM PDT 24
Peak memory 195964 kb
Host smart-415897c4-a80d-48b7-ade0-8ebc9e45c421
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327752206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.2327752206
Directory /workspace/1.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.2048183916
Short name T1145
Test name
Test status
Simulation time 158704320 ps
CPU time 0.89 seconds
Started Jun 10 05:09:30 PM PDT 24
Finished Jun 10 05:09:32 PM PDT 24
Peak memory 200688 kb
Host smart-c61baa50-9bb9-41e3-b033-16d77788f62d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048183916 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.2048183916
Directory /workspace/1.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_rw.4216501122
Short name T1115
Test name
Test status
Simulation time 14611040 ps
CPU time 0.65 seconds
Started Jun 10 05:09:43 PM PDT 24
Finished Jun 10 05:09:44 PM PDT 24
Peak memory 196308 kb
Host smart-5e601c97-c188-444a-8b5d-ef03f5fba7de
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216501122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.4216501122
Directory /workspace/1.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.uart_intr_test.532118879
Short name T1166
Test name
Test status
Simulation time 14372235 ps
CPU time 0.57 seconds
Started Jun 10 05:09:29 PM PDT 24
Finished Jun 10 05:09:30 PM PDT 24
Peak memory 194864 kb
Host smart-c6fbe10d-d615-4b32-b86f-3994b0f7f039
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532118879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.532118879
Directory /workspace/1.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.2080229104
Short name T1148
Test name
Test status
Simulation time 17838355 ps
CPU time 0.73 seconds
Started Jun 10 05:09:33 PM PDT 24
Finished Jun 10 05:09:34 PM PDT 24
Peak memory 197620 kb
Host smart-a9241c49-e4dd-44d0-a908-90e65c879c7d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080229104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr
_outstanding.2080229104
Directory /workspace/1.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_errors.3776386322
Short name T1132
Test name
Test status
Simulation time 196584125 ps
CPU time 1.97 seconds
Started Jun 10 05:09:30 PM PDT 24
Finished Jun 10 05:09:33 PM PDT 24
Peak memory 200568 kb
Host smart-dd70f1fc-12e7-4227-ab34-e51c6c1a08cf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776386322 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.3776386322
Directory /workspace/1.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.1203551849
Short name T1105
Test name
Test status
Simulation time 68714936 ps
CPU time 1.06 seconds
Started Jun 10 05:09:30 PM PDT 24
Finished Jun 10 05:09:32 PM PDT 24
Peak memory 199676 kb
Host smart-1de665ca-effc-46d3-b86b-b3f388b8d159
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203551849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.1203551849
Directory /workspace/1.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.4014727862
Short name T1162
Test name
Test status
Simulation time 85702607 ps
CPU time 0.88 seconds
Started Jun 10 05:09:49 PM PDT 24
Finished Jun 10 05:09:50 PM PDT 24
Peak memory 200400 kb
Host smart-5efa0df8-deba-4583-bbd0-be983e750cfd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014727862 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.4014727862
Directory /workspace/10.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_rw.4050173165
Short name T81
Test name
Test status
Simulation time 46633433 ps
CPU time 0.58 seconds
Started Jun 10 05:09:46 PM PDT 24
Finished Jun 10 05:09:47 PM PDT 24
Peak memory 195912 kb
Host smart-98e75fe6-e688-4888-89c2-8d9ccdbf0da1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050173165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.4050173165
Directory /workspace/10.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.uart_intr_test.3225448795
Short name T1092
Test name
Test status
Simulation time 24771187 ps
CPU time 0.58 seconds
Started Jun 10 05:09:54 PM PDT 24
Finished Jun 10 05:09:54 PM PDT 24
Peak memory 194972 kb
Host smart-3f7693f9-7a2e-4ff6-ba80-c7ad4e51bcc1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225448795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.3225448795
Directory /workspace/10.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.3560680721
Short name T87
Test name
Test status
Simulation time 63167167 ps
CPU time 0.78 seconds
Started Jun 10 05:09:39 PM PDT 24
Finished Jun 10 05:09:41 PM PDT 24
Peak memory 197676 kb
Host smart-30b096e5-508d-4f82-8f2a-20743971e63c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560680721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_cs
r_outstanding.3560680721
Directory /workspace/10.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_errors.2321212009
Short name T1159
Test name
Test status
Simulation time 141280979 ps
CPU time 2.5 seconds
Started Jun 10 05:09:37 PM PDT 24
Finished Jun 10 05:09:42 PM PDT 24
Peak memory 200564 kb
Host smart-81fbf0e6-7585-4f38-9e3d-26df67d8bcfb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321212009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.2321212009
Directory /workspace/10.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.122003885
Short name T1179
Test name
Test status
Simulation time 97492198 ps
CPU time 0.93 seconds
Started Jun 10 05:09:50 PM PDT 24
Finished Jun 10 05:09:52 PM PDT 24
Peak memory 199196 kb
Host smart-b91bdd72-66b9-44d9-805b-1d1e6c3a9000
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122003885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.122003885
Directory /workspace/10.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.2083511102
Short name T1111
Test name
Test status
Simulation time 25948804 ps
CPU time 0.81 seconds
Started Jun 10 05:09:35 PM PDT 24
Finished Jun 10 05:09:36 PM PDT 24
Peak memory 199048 kb
Host smart-2960e3ab-cd2f-4dbe-8870-c34ef2028bbc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083511102 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.2083511102
Directory /workspace/11.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_rw.1140881284
Short name T1175
Test name
Test status
Simulation time 26370820 ps
CPU time 0.64 seconds
Started Jun 10 05:09:42 PM PDT 24
Finished Jun 10 05:09:43 PM PDT 24
Peak memory 196152 kb
Host smart-1abf3ef7-7d18-4085-9b8c-7150ffe475e8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140881284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.1140881284
Directory /workspace/11.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.uart_intr_test.3337322417
Short name T1124
Test name
Test status
Simulation time 43041457 ps
CPU time 0.6 seconds
Started Jun 10 05:09:35 PM PDT 24
Finished Jun 10 05:09:38 PM PDT 24
Peak memory 194968 kb
Host smart-98deec61-870a-4b48-937b-dcf7a24210a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337322417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.3337322417
Directory /workspace/11.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.1234292985
Short name T1195
Test name
Test status
Simulation time 36153036 ps
CPU time 0.71 seconds
Started Jun 10 05:09:38 PM PDT 24
Finished Jun 10 05:09:41 PM PDT 24
Peak memory 197620 kb
Host smart-23850312-cb2d-44ab-8f25-11b74cb1069a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234292985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_cs
r_outstanding.1234292985
Directory /workspace/11.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_errors.506153030
Short name T1095
Test name
Test status
Simulation time 103216741 ps
CPU time 1.49 seconds
Started Jun 10 05:09:53 PM PDT 24
Finished Jun 10 05:09:54 PM PDT 24
Peak memory 200612 kb
Host smart-468716cd-e0f5-46b0-adc6-b8eed03d4536
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506153030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.506153030
Directory /workspace/11.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.2109322593
Short name T1131
Test name
Test status
Simulation time 54533896 ps
CPU time 1 seconds
Started Jun 10 05:09:52 PM PDT 24
Finished Jun 10 05:09:59 PM PDT 24
Peak memory 199452 kb
Host smart-ec59af11-2ce2-46e8-916f-541298215abf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109322593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.2109322593
Directory /workspace/11.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.3573703484
Short name T1157
Test name
Test status
Simulation time 45608244 ps
CPU time 0.73 seconds
Started Jun 10 05:09:43 PM PDT 24
Finished Jun 10 05:09:45 PM PDT 24
Peak memory 198344 kb
Host smart-5636ca94-87da-4e5f-b966-afe2db583590
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573703484 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.3573703484
Directory /workspace/12.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_rw.2766870111
Short name T1198
Test name
Test status
Simulation time 19967594 ps
CPU time 0.6 seconds
Started Jun 10 05:09:37 PM PDT 24
Finished Jun 10 05:09:39 PM PDT 24
Peak memory 196012 kb
Host smart-310e7455-43a8-4196-a76c-75e87448bbf4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766870111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.2766870111
Directory /workspace/12.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.uart_intr_test.739115939
Short name T1093
Test name
Test status
Simulation time 75743069 ps
CPU time 0.56 seconds
Started Jun 10 05:09:41 PM PDT 24
Finished Jun 10 05:09:42 PM PDT 24
Peak memory 194976 kb
Host smart-e8df5e42-832a-492d-abbb-83c56e3231e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739115939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.739115939
Directory /workspace/12.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.3267176171
Short name T1151
Test name
Test status
Simulation time 100425148 ps
CPU time 0.75 seconds
Started Jun 10 05:09:37 PM PDT 24
Finished Jun 10 05:09:40 PM PDT 24
Peak memory 196728 kb
Host smart-2a1649fd-ec65-44fc-908c-85b8315b35d6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267176171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_cs
r_outstanding.3267176171
Directory /workspace/12.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_errors.3198735828
Short name T1224
Test name
Test status
Simulation time 317352456 ps
CPU time 1.69 seconds
Started Jun 10 05:09:36 PM PDT 24
Finished Jun 10 05:09:40 PM PDT 24
Peak memory 200580 kb
Host smart-4ca73897-d415-4de8-ab13-a1107fdb1c9c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198735828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.3198735828
Directory /workspace/12.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.2638579459
Short name T96
Test name
Test status
Simulation time 600791217 ps
CPU time 1.21 seconds
Started Jun 10 05:09:31 PM PDT 24
Finished Jun 10 05:09:32 PM PDT 24
Peak memory 199848 kb
Host smart-89b8e532-5b74-4c67-914a-a4ec9f67e20b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638579459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.2638579459
Directory /workspace/12.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.3281490269
Short name T1116
Test name
Test status
Simulation time 69120295 ps
CPU time 0.73 seconds
Started Jun 10 05:09:36 PM PDT 24
Finished Jun 10 05:09:38 PM PDT 24
Peak memory 198840 kb
Host smart-0bd64e7a-c7ce-4c11-a1e6-87f2f4fe221e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281490269 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.3281490269
Directory /workspace/13.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_rw.2917312034
Short name T1216
Test name
Test status
Simulation time 41649942 ps
CPU time 0.58 seconds
Started Jun 10 05:09:44 PM PDT 24
Finished Jun 10 05:09:45 PM PDT 24
Peak memory 195912 kb
Host smart-cbff17c5-25b8-4cbb-8418-fdc0addcd33c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917312034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.2917312034
Directory /workspace/13.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.uart_intr_test.1025252389
Short name T1098
Test name
Test status
Simulation time 52321694 ps
CPU time 0.58 seconds
Started Jun 10 05:09:36 PM PDT 24
Finished Jun 10 05:09:38 PM PDT 24
Peak memory 194936 kb
Host smart-b5ee20ab-7ccc-4701-9b2e-c32fc9fe49e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025252389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.1025252389
Directory /workspace/13.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.1045623184
Short name T1217
Test name
Test status
Simulation time 435061519 ps
CPU time 0.78 seconds
Started Jun 10 05:09:49 PM PDT 24
Finished Jun 10 05:09:50 PM PDT 24
Peak memory 197148 kb
Host smart-3dff2460-28c1-4fe6-aefc-ee720e75b5d9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045623184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_cs
r_outstanding.1045623184
Directory /workspace/13.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_errors.3494337025
Short name T1223
Test name
Test status
Simulation time 525857169 ps
CPU time 2.23 seconds
Started Jun 10 05:09:49 PM PDT 24
Finished Jun 10 05:09:51 PM PDT 24
Peak memory 200668 kb
Host smart-6c001ffd-d403-40a8-97ae-4a4fc3d163dd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494337025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.3494337025
Directory /workspace/13.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.868208878
Short name T1102
Test name
Test status
Simulation time 35173131 ps
CPU time 0.71 seconds
Started Jun 10 05:09:43 PM PDT 24
Finished Jun 10 05:09:45 PM PDT 24
Peak memory 199176 kb
Host smart-656767c1-a1a9-4b94-90b0-055992b0853c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868208878 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.868208878
Directory /workspace/14.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_rw.1565425338
Short name T1199
Test name
Test status
Simulation time 43877655 ps
CPU time 0.59 seconds
Started Jun 10 05:09:38 PM PDT 24
Finished Jun 10 05:09:41 PM PDT 24
Peak memory 195988 kb
Host smart-4aa94a70-1315-4d8c-95be-a68c8e649330
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565425338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.1565425338
Directory /workspace/14.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.uart_intr_test.988257844
Short name T1135
Test name
Test status
Simulation time 36193584 ps
CPU time 0.55 seconds
Started Jun 10 05:09:44 PM PDT 24
Finished Jun 10 05:09:45 PM PDT 24
Peak memory 195000 kb
Host smart-8cf3b623-54b9-4cf7-b290-b7115c9d37e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988257844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.988257844
Directory /workspace/14.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.3943825863
Short name T1113
Test name
Test status
Simulation time 25179261 ps
CPU time 0.66 seconds
Started Jun 10 05:09:33 PM PDT 24
Finished Jun 10 05:09:35 PM PDT 24
Peak memory 196488 kb
Host smart-5ead6113-d5cf-48b7-b9e3-336ea8d563e0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943825863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_cs
r_outstanding.3943825863
Directory /workspace/14.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_errors.4148533826
Short name T1158
Test name
Test status
Simulation time 83114704 ps
CPU time 2.08 seconds
Started Jun 10 05:09:50 PM PDT 24
Finished Jun 10 05:09:53 PM PDT 24
Peak memory 200604 kb
Host smart-f1d6565e-0692-4e92-88ea-6a88b1292c8b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148533826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.4148533826
Directory /workspace/14.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.2654136859
Short name T92
Test name
Test status
Simulation time 298282873 ps
CPU time 1.01 seconds
Started Jun 10 05:09:56 PM PDT 24
Finished Jun 10 05:09:57 PM PDT 24
Peak memory 199752 kb
Host smart-64318920-d5cf-4261-9d59-b48842c720c4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654136859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.2654136859
Directory /workspace/14.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.3881506122
Short name T1114
Test name
Test status
Simulation time 28106878 ps
CPU time 0.8 seconds
Started Jun 10 05:09:48 PM PDT 24
Finished Jun 10 05:09:49 PM PDT 24
Peak memory 200468 kb
Host smart-fdc2be89-228d-46e7-bd92-5953a3e9cc92
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881506122 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.3881506122
Directory /workspace/15.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_rw.2843602250
Short name T1189
Test name
Test status
Simulation time 15951218 ps
CPU time 0.59 seconds
Started Jun 10 05:09:39 PM PDT 24
Finished Jun 10 05:09:41 PM PDT 24
Peak memory 196020 kb
Host smart-420adaec-6405-4a0d-8417-fb8726bbfbb2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843602250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.2843602250
Directory /workspace/15.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.uart_intr_test.2760174573
Short name T1129
Test name
Test status
Simulation time 15051089 ps
CPU time 0.64 seconds
Started Jun 10 05:09:43 PM PDT 24
Finished Jun 10 05:09:44 PM PDT 24
Peak memory 195016 kb
Host smart-e1e5d9a1-8e68-4808-9eaf-5af8e6744c54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760174573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.2760174573
Directory /workspace/15.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.334900030
Short name T1196
Test name
Test status
Simulation time 36050141 ps
CPU time 0.63 seconds
Started Jun 10 05:09:36 PM PDT 24
Finished Jun 10 05:09:38 PM PDT 24
Peak memory 195168 kb
Host smart-3693184b-ac36-4002-bd2e-6513f45bc0b9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334900030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_csr
_outstanding.334900030
Directory /workspace/15.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_errors.50805998
Short name T1112
Test name
Test status
Simulation time 84540944 ps
CPU time 2.2 seconds
Started Jun 10 05:09:44 PM PDT 24
Finished Jun 10 05:09:46 PM PDT 24
Peak memory 200696 kb
Host smart-9884d759-9d35-4281-9ff5-41e2a6a9da62
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50805998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.50805998
Directory /workspace/15.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.3554167485
Short name T136
Test name
Test status
Simulation time 40771668 ps
CPU time 0.95 seconds
Started Jun 10 05:09:43 PM PDT 24
Finished Jun 10 05:09:44 PM PDT 24
Peak memory 199636 kb
Host smart-7418d397-fe88-44ec-bef0-5bcaab1bc26f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554167485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.3554167485
Directory /workspace/15.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.3652544983
Short name T1201
Test name
Test status
Simulation time 20441175 ps
CPU time 1.01 seconds
Started Jun 10 05:09:48 PM PDT 24
Finished Jun 10 05:09:50 PM PDT 24
Peak memory 200464 kb
Host smart-66f0e258-edb0-4d08-9ca8-7bd1f9609962
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652544983 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.3652544983
Directory /workspace/16.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_rw.2560264484
Short name T1161
Test name
Test status
Simulation time 50112877 ps
CPU time 0.65 seconds
Started Jun 10 05:09:33 PM PDT 24
Finished Jun 10 05:09:35 PM PDT 24
Peak memory 196096 kb
Host smart-89913d79-e7b7-461c-ad16-da85fb949f82
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560264484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.2560264484
Directory /workspace/16.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.uart_intr_test.2054844073
Short name T1207
Test name
Test status
Simulation time 19506538 ps
CPU time 0.58 seconds
Started Jun 10 05:09:36 PM PDT 24
Finished Jun 10 05:09:38 PM PDT 24
Peak memory 195048 kb
Host smart-2415ac6f-13b8-4bad-9feb-3b2aa83aa66e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054844073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.2054844073
Directory /workspace/16.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.757882059
Short name T1184
Test name
Test status
Simulation time 44108745 ps
CPU time 0.67 seconds
Started Jun 10 05:09:46 PM PDT 24
Finished Jun 10 05:09:47 PM PDT 24
Peak memory 196392 kb
Host smart-3af297f7-9389-4d53-ae46-02c36f52d49c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757882059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_csr
_outstanding.757882059
Directory /workspace/16.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_errors.1676619159
Short name T1194
Test name
Test status
Simulation time 82450204 ps
CPU time 2.24 seconds
Started Jun 10 05:10:05 PM PDT 24
Finished Jun 10 05:10:07 PM PDT 24
Peak memory 200600 kb
Host smart-2594e70e-c57c-4a23-81e2-f80866fb032a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676619159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.1676619159
Directory /workspace/16.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.3073917614
Short name T95
Test name
Test status
Simulation time 346151976 ps
CPU time 0.98 seconds
Started Jun 10 05:09:41 PM PDT 24
Finished Jun 10 05:09:43 PM PDT 24
Peak memory 199720 kb
Host smart-070fd973-31d1-46d5-952f-6a5929fbc39f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073917614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.3073917614
Directory /workspace/16.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.1179535246
Short name T1211
Test name
Test status
Simulation time 65503284 ps
CPU time 0.74 seconds
Started Jun 10 05:09:38 PM PDT 24
Finished Jun 10 05:09:40 PM PDT 24
Peak memory 198936 kb
Host smart-0af1a039-0a6e-4cfa-88d6-fa856b78e8c8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179535246 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.1179535246
Directory /workspace/17.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_rw.2001120710
Short name T84
Test name
Test status
Simulation time 23765122 ps
CPU time 0.58 seconds
Started Jun 10 05:09:38 PM PDT 24
Finished Jun 10 05:09:40 PM PDT 24
Peak memory 195920 kb
Host smart-93ae6386-2e1d-4c84-876b-39133185c85d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001120710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.2001120710
Directory /workspace/17.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.uart_intr_test.1590603488
Short name T1193
Test name
Test status
Simulation time 38956886 ps
CPU time 0.55 seconds
Started Jun 10 05:09:46 PM PDT 24
Finished Jun 10 05:09:47 PM PDT 24
Peak memory 194888 kb
Host smart-f16114d7-fd54-45ed-9e36-a008af800e61
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590603488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.1590603488
Directory /workspace/17.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.446036374
Short name T1177
Test name
Test status
Simulation time 45466878 ps
CPU time 0.67 seconds
Started Jun 10 05:09:37 PM PDT 24
Finished Jun 10 05:09:40 PM PDT 24
Peak memory 196112 kb
Host smart-abf45053-f79b-4dfa-92bd-a9895904b9eb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446036374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_csr
_outstanding.446036374
Directory /workspace/17.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_errors.4156550007
Short name T1168
Test name
Test status
Simulation time 1284198464 ps
CPU time 2.26 seconds
Started Jun 10 05:09:38 PM PDT 24
Finished Jun 10 05:09:43 PM PDT 24
Peak memory 200596 kb
Host smart-2f94f4f2-c878-4435-ba72-876313568769
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156550007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.4156550007
Directory /workspace/17.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.2842653132
Short name T1173
Test name
Test status
Simulation time 93354254 ps
CPU time 0.95 seconds
Started Jun 10 05:09:57 PM PDT 24
Finished Jun 10 05:09:58 PM PDT 24
Peak memory 199652 kb
Host smart-bf2fa309-b866-4bf9-a118-7db9298a366d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842653132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.2842653132
Directory /workspace/17.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.2296668918
Short name T1138
Test name
Test status
Simulation time 29428174 ps
CPU time 0.76 seconds
Started Jun 10 05:09:34 PM PDT 24
Finished Jun 10 05:09:36 PM PDT 24
Peak memory 199996 kb
Host smart-54afe0f1-6807-4b12-9098-1cc5add2e202
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296668918 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.2296668918
Directory /workspace/18.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.uart_intr_test.4027691886
Short name T1128
Test name
Test status
Simulation time 43292476 ps
CPU time 0.59 seconds
Started Jun 10 05:09:40 PM PDT 24
Finished Jun 10 05:09:42 PM PDT 24
Peak memory 195052 kb
Host smart-fed84ca9-5e45-4663-9dc8-6ad4fc06ddfc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027691886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.4027691886
Directory /workspace/18.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.152694671
Short name T1174
Test name
Test status
Simulation time 26582550 ps
CPU time 0.72 seconds
Started Jun 10 05:09:51 PM PDT 24
Finished Jun 10 05:09:52 PM PDT 24
Peak memory 197436 kb
Host smart-6798254f-8865-43b3-bef1-e0c134156406
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152694671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_csr
_outstanding.152694671
Directory /workspace/18.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_errors.1314078932
Short name T1123
Test name
Test status
Simulation time 572958871 ps
CPU time 2.52 seconds
Started Jun 10 05:09:38 PM PDT 24
Finished Jun 10 05:09:42 PM PDT 24
Peak memory 200628 kb
Host smart-50b3d3ac-f62a-41aa-8586-dad586752f14
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314078932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.1314078932
Directory /workspace/18.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.778986543
Short name T100
Test name
Test status
Simulation time 357646744 ps
CPU time 0.96 seconds
Started Jun 10 05:09:41 PM PDT 24
Finished Jun 10 05:09:42 PM PDT 24
Peak memory 199600 kb
Host smart-48ae4efe-72a4-48a6-a2f3-c3ad2c2bc88b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778986543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.778986543
Directory /workspace/18.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.2621317989
Short name T1170
Test name
Test status
Simulation time 36566620 ps
CPU time 0.72 seconds
Started Jun 10 05:10:01 PM PDT 24
Finished Jun 10 05:10:02 PM PDT 24
Peak memory 198152 kb
Host smart-82324781-45fb-4fb1-871e-b47f53893189
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621317989 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.2621317989
Directory /workspace/19.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_rw.1369702499
Short name T74
Test name
Test status
Simulation time 64661884 ps
CPU time 0.61 seconds
Started Jun 10 05:09:42 PM PDT 24
Finished Jun 10 05:09:43 PM PDT 24
Peak memory 195996 kb
Host smart-f6025cdf-e542-4cc4-9662-3e2ae45bbbb1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369702499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.1369702499
Directory /workspace/19.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.uart_intr_test.4219434061
Short name T1164
Test name
Test status
Simulation time 46539849 ps
CPU time 0.58 seconds
Started Jun 10 05:09:38 PM PDT 24
Finished Jun 10 05:09:40 PM PDT 24
Peak memory 195052 kb
Host smart-c79a516d-067d-4e3f-a1aa-2ecc25c5e562
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219434061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.4219434061
Directory /workspace/19.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.1300468097
Short name T80
Test name
Test status
Simulation time 34542218 ps
CPU time 0.67 seconds
Started Jun 10 05:09:50 PM PDT 24
Finished Jun 10 05:09:51 PM PDT 24
Peak memory 197244 kb
Host smart-8dfc3021-ead6-4e24-b175-fa6de9c945aa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300468097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_cs
r_outstanding.1300468097
Directory /workspace/19.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_errors.3298256548
Short name T1127
Test name
Test status
Simulation time 135565817 ps
CPU time 2.73 seconds
Started Jun 10 05:09:53 PM PDT 24
Finished Jun 10 05:09:57 PM PDT 24
Peak memory 200540 kb
Host smart-5dcc1c96-ee35-4783-937f-1b5c7565d18e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298256548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.3298256548
Directory /workspace/19.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.2492949418
Short name T135
Test name
Test status
Simulation time 49378160 ps
CPU time 0.93 seconds
Started Jun 10 05:09:47 PM PDT 24
Finished Jun 10 05:09:48 PM PDT 24
Peak memory 199344 kb
Host smart-91d519df-d31a-4d4a-a362-bfd5975642bb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492949418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.2492949418
Directory /workspace/19.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.548021065
Short name T1183
Test name
Test status
Simulation time 34065961 ps
CPU time 0.86 seconds
Started Jun 10 05:09:50 PM PDT 24
Finished Jun 10 05:09:52 PM PDT 24
Peak memory 196868 kb
Host smart-757db492-3793-43b2-ab6f-bcb41b7f6b22
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548021065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.548021065
Directory /workspace/2.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.3384069349
Short name T76
Test name
Test status
Simulation time 147302376 ps
CPU time 1.51 seconds
Started Jun 10 05:09:30 PM PDT 24
Finished Jun 10 05:09:32 PM PDT 24
Peak memory 198256 kb
Host smart-b5e84c8f-3767-428d-a1b6-275143d84b7d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384069349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.3384069349
Directory /workspace/2.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.3626352944
Short name T1140
Test name
Test status
Simulation time 54878299 ps
CPU time 0.61 seconds
Started Jun 10 05:09:46 PM PDT 24
Finished Jun 10 05:09:47 PM PDT 24
Peak memory 195968 kb
Host smart-096ec422-9052-4bdf-9fef-49dc979e9096
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626352944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.3626352944
Directory /workspace/2.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.3341227685
Short name T1118
Test name
Test status
Simulation time 33608273 ps
CPU time 0.81 seconds
Started Jun 10 05:09:44 PM PDT 24
Finished Jun 10 05:09:46 PM PDT 24
Peak memory 200476 kb
Host smart-af4812a6-0942-4c84-a24b-7eb4f297fb24
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341227685 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.3341227685
Directory /workspace/2.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_rw.914726086
Short name T77
Test name
Test status
Simulation time 30418238 ps
CPU time 0.61 seconds
Started Jun 10 05:09:47 PM PDT 24
Finished Jun 10 05:09:48 PM PDT 24
Peak memory 196020 kb
Host smart-aee19ae0-4d95-4c96-ba07-bcf41b7fd020
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914726086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.914726086
Directory /workspace/2.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.uart_intr_test.1418128082
Short name T1130
Test name
Test status
Simulation time 55977133 ps
CPU time 0.59 seconds
Started Jun 10 05:09:29 PM PDT 24
Finished Jun 10 05:09:30 PM PDT 24
Peak memory 194960 kb
Host smart-21320cc5-34cd-420e-abbe-20aa064a5433
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418128082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.1418128082
Directory /workspace/2.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.820844642
Short name T86
Test name
Test status
Simulation time 58969549 ps
CPU time 0.79 seconds
Started Jun 10 05:09:34 PM PDT 24
Finished Jun 10 05:09:35 PM PDT 24
Peak memory 196992 kb
Host smart-27891d85-7fca-4e1b-851c-7ce41ecd7f85
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820844642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr_
outstanding.820844642
Directory /workspace/2.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_errors.299109750
Short name T1142
Test name
Test status
Simulation time 407448057 ps
CPU time 2.45 seconds
Started Jun 10 05:09:43 PM PDT 24
Finished Jun 10 05:09:46 PM PDT 24
Peak memory 200664 kb
Host smart-31059db5-6734-404b-bf29-4eafb1089fc1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299109750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.299109750
Directory /workspace/2.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.69325425
Short name T94
Test name
Test status
Simulation time 201105372 ps
CPU time 1.01 seconds
Started Jun 10 05:09:27 PM PDT 24
Finished Jun 10 05:09:28 PM PDT 24
Peak memory 199532 kb
Host smart-e5e26376-b7a2-4495-9ecc-f3c48efb8a8c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69325425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.69325425
Directory /workspace/2.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.uart_intr_test.3974472118
Short name T1167
Test name
Test status
Simulation time 13632221 ps
CPU time 0.61 seconds
Started Jun 10 05:09:38 PM PDT 24
Finished Jun 10 05:09:41 PM PDT 24
Peak memory 194988 kb
Host smart-b89916b7-9b2b-4a8c-b455-628f6eb8f849
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974472118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.3974472118
Directory /workspace/20.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.uart_intr_test.3387306923
Short name T1153
Test name
Test status
Simulation time 26585036 ps
CPU time 0.59 seconds
Started Jun 10 05:09:42 PM PDT 24
Finished Jun 10 05:09:44 PM PDT 24
Peak memory 194984 kb
Host smart-fb1e3f00-9a78-462f-8382-ceffbe0b7db9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387306923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.3387306923
Directory /workspace/21.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.uart_intr_test.1109925741
Short name T1208
Test name
Test status
Simulation time 12886363 ps
CPU time 0.59 seconds
Started Jun 10 05:09:36 PM PDT 24
Finished Jun 10 05:09:39 PM PDT 24
Peak memory 195008 kb
Host smart-5aa073ee-cb28-4741-ac81-4ec4b5c08ccf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109925741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.1109925741
Directory /workspace/22.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.uart_intr_test.4047168283
Short name T1137
Test name
Test status
Simulation time 40596286 ps
CPU time 0.57 seconds
Started Jun 10 05:09:47 PM PDT 24
Finished Jun 10 05:09:48 PM PDT 24
Peak memory 194996 kb
Host smart-4d6d728a-cac7-4119-b450-845c1461b0c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047168283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.4047168283
Directory /workspace/23.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.uart_intr_test.61496363
Short name T1222
Test name
Test status
Simulation time 23822023 ps
CPU time 0.61 seconds
Started Jun 10 05:09:38 PM PDT 24
Finished Jun 10 05:09:40 PM PDT 24
Peak memory 195076 kb
Host smart-26e22b7c-99ef-4827-9b95-cbaf686b5c69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61496363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.61496363
Directory /workspace/24.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.uart_intr_test.301563935
Short name T1203
Test name
Test status
Simulation time 16929142 ps
CPU time 0.63 seconds
Started Jun 10 05:09:39 PM PDT 24
Finished Jun 10 05:09:41 PM PDT 24
Peak memory 195064 kb
Host smart-e7304f08-b945-4811-80b8-f06e3af4428e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301563935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.301563935
Directory /workspace/25.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.uart_intr_test.3397588256
Short name T1205
Test name
Test status
Simulation time 40275757 ps
CPU time 0.57 seconds
Started Jun 10 05:09:41 PM PDT 24
Finished Jun 10 05:09:43 PM PDT 24
Peak memory 194940 kb
Host smart-74846d64-d1c0-477b-a71d-4932a9522b19
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397588256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.3397588256
Directory /workspace/26.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.uart_intr_test.2374977070
Short name T1152
Test name
Test status
Simulation time 20658470 ps
CPU time 0.6 seconds
Started Jun 10 05:09:43 PM PDT 24
Finished Jun 10 05:09:44 PM PDT 24
Peak memory 194964 kb
Host smart-af1d875d-eeaf-41fe-a788-39bcd5b583de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374977070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.2374977070
Directory /workspace/27.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.uart_intr_test.2714689807
Short name T1206
Test name
Test status
Simulation time 28814124 ps
CPU time 0.65 seconds
Started Jun 10 05:09:45 PM PDT 24
Finished Jun 10 05:09:46 PM PDT 24
Peak memory 194952 kb
Host smart-af57e18f-205b-4f36-98ce-0f50f775bb3e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714689807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.2714689807
Directory /workspace/28.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.uart_intr_test.2508531212
Short name T1191
Test name
Test status
Simulation time 41376702 ps
CPU time 0.59 seconds
Started Jun 10 05:09:47 PM PDT 24
Finished Jun 10 05:09:48 PM PDT 24
Peak memory 195020 kb
Host smart-0a6f2d48-b53c-4884-9fd7-016a2ff7b699
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508531212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.2508531212
Directory /workspace/29.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.315072938
Short name T1197
Test name
Test status
Simulation time 97692412 ps
CPU time 0.82 seconds
Started Jun 10 05:09:49 PM PDT 24
Finished Jun 10 05:09:50 PM PDT 24
Peak memory 197396 kb
Host smart-b575cfaa-12ad-4151-9a8b-e42ed4950c39
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315072938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.315072938
Directory /workspace/3.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.4183843044
Short name T1100
Test name
Test status
Simulation time 1076323940 ps
CPU time 2.67 seconds
Started Jun 10 05:09:52 PM PDT 24
Finished Jun 10 05:09:55 PM PDT 24
Peak memory 197764 kb
Host smart-013fe942-1188-4dc1-9841-86c76847bd24
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183843044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.4183843044
Directory /workspace/3.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.2164871217
Short name T1192
Test name
Test status
Simulation time 16691633 ps
CPU time 0.6 seconds
Started Jun 10 05:09:57 PM PDT 24
Finished Jun 10 05:09:58 PM PDT 24
Peak memory 195924 kb
Host smart-e1853386-ff3d-4535-8b34-0812d9e9fecd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164871217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.2164871217
Directory /workspace/3.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.3903631062
Short name T1155
Test name
Test status
Simulation time 28796931 ps
CPU time 1.18 seconds
Started Jun 10 05:09:31 PM PDT 24
Finished Jun 10 05:09:33 PM PDT 24
Peak memory 200688 kb
Host smart-ac31aedf-af80-4a92-bad3-bdbf5f6b56df
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903631062 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.3903631062
Directory /workspace/3.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_rw.85638079
Short name T79
Test name
Test status
Simulation time 57136099 ps
CPU time 0.63 seconds
Started Jun 10 05:09:43 PM PDT 24
Finished Jun 10 05:09:44 PM PDT 24
Peak memory 196036 kb
Host smart-dfe34964-7b4c-491a-9880-2b0daae512f9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85638079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.85638079
Directory /workspace/3.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.uart_intr_test.2266121454
Short name T1106
Test name
Test status
Simulation time 44594449 ps
CPU time 0.58 seconds
Started Jun 10 05:09:33 PM PDT 24
Finished Jun 10 05:09:34 PM PDT 24
Peak memory 195072 kb
Host smart-5c669e91-cd65-4595-b2f3-7619a55967ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266121454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.2266121454
Directory /workspace/3.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.1705048870
Short name T1156
Test name
Test status
Simulation time 29069927 ps
CPU time 0.8 seconds
Started Jun 10 05:09:39 PM PDT 24
Finished Jun 10 05:09:41 PM PDT 24
Peak memory 197536 kb
Host smart-116a4fbd-7374-41b3-bf16-11ba4b35f1d1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705048870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr
_outstanding.1705048870
Directory /workspace/3.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_errors.3885256066
Short name T1122
Test name
Test status
Simulation time 84700390 ps
CPU time 1.18 seconds
Started Jun 10 05:09:37 PM PDT 24
Finished Jun 10 05:09:40 PM PDT 24
Peak memory 200684 kb
Host smart-6327b027-79b5-4cc3-88b6-ce5650a0015b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885256066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.3885256066
Directory /workspace/3.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.418680641
Short name T1202
Test name
Test status
Simulation time 93037606 ps
CPU time 1.31 seconds
Started Jun 10 05:09:42 PM PDT 24
Finished Jun 10 05:09:44 PM PDT 24
Peak memory 199860 kb
Host smart-3a924fe0-4b9d-4672-8e39-7e7eb772f118
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418680641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.418680641
Directory /workspace/3.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.uart_intr_test.902133272
Short name T1121
Test name
Test status
Simulation time 17430029 ps
CPU time 0.59 seconds
Started Jun 10 05:09:43 PM PDT 24
Finished Jun 10 05:09:45 PM PDT 24
Peak memory 195032 kb
Host smart-e4df8ae6-cb9d-4b0b-9ccd-a76a91bfb4de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902133272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.902133272
Directory /workspace/30.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.uart_intr_test.2888290413
Short name T1221
Test name
Test status
Simulation time 23013219 ps
CPU time 0.56 seconds
Started Jun 10 05:09:52 PM PDT 24
Finished Jun 10 05:09:52 PM PDT 24
Peak memory 195024 kb
Host smart-6bb17597-17ef-4914-82aa-0fddd045b8d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888290413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.2888290413
Directory /workspace/31.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.uart_intr_test.3609674194
Short name T1146
Test name
Test status
Simulation time 76517898 ps
CPU time 0.53 seconds
Started Jun 10 05:09:52 PM PDT 24
Finished Jun 10 05:09:53 PM PDT 24
Peak memory 194952 kb
Host smart-46e44c80-dd93-4ee0-9157-5f269f30107e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609674194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.3609674194
Directory /workspace/32.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.uart_intr_test.535588781
Short name T1200
Test name
Test status
Simulation time 18332001 ps
CPU time 0.62 seconds
Started Jun 10 05:09:38 PM PDT 24
Finished Jun 10 05:09:41 PM PDT 24
Peak memory 194840 kb
Host smart-45e42400-1fad-4a38-9ad9-f39075a13051
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535588781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.535588781
Directory /workspace/33.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.uart_intr_test.3031461395
Short name T1163
Test name
Test status
Simulation time 13720214 ps
CPU time 0.57 seconds
Started Jun 10 05:09:52 PM PDT 24
Finished Jun 10 05:09:53 PM PDT 24
Peak memory 194944 kb
Host smart-612b8b9e-a118-40a7-a9a2-e8dac6ffffe9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031461395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.3031461395
Directory /workspace/34.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.uart_intr_test.2771317354
Short name T1109
Test name
Test status
Simulation time 13647405 ps
CPU time 0.56 seconds
Started Jun 10 05:09:55 PM PDT 24
Finished Jun 10 05:09:56 PM PDT 24
Peak memory 194960 kb
Host smart-f700ce90-5676-43b0-92e7-df56ea905096
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771317354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.2771317354
Directory /workspace/35.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.uart_intr_test.1485706564
Short name T1171
Test name
Test status
Simulation time 55304615 ps
CPU time 0.6 seconds
Started Jun 10 05:09:44 PM PDT 24
Finished Jun 10 05:09:45 PM PDT 24
Peak memory 194936 kb
Host smart-7c5867fe-1364-43b7-a1e1-f52ba489f4a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485706564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.1485706564
Directory /workspace/36.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.uart_intr_test.2025194186
Short name T1169
Test name
Test status
Simulation time 16038175 ps
CPU time 0.57 seconds
Started Jun 10 05:09:41 PM PDT 24
Finished Jun 10 05:09:43 PM PDT 24
Peak memory 194940 kb
Host smart-a0318717-a79f-439d-89f3-fd02ca07fb8c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025194186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.2025194186
Directory /workspace/37.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.uart_intr_test.1455264720
Short name T1165
Test name
Test status
Simulation time 54643536 ps
CPU time 0.6 seconds
Started Jun 10 05:09:41 PM PDT 24
Finished Jun 10 05:09:43 PM PDT 24
Peak memory 195020 kb
Host smart-fe4c9a93-399b-419d-8028-af58709e27fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455264720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.1455264720
Directory /workspace/38.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.uart_intr_test.2774507000
Short name T1133
Test name
Test status
Simulation time 168042789 ps
CPU time 0.59 seconds
Started Jun 10 05:09:37 PM PDT 24
Finished Jun 10 05:09:40 PM PDT 24
Peak memory 194920 kb
Host smart-355794d1-25c8-4940-a738-b0e56c921e40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774507000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.2774507000
Directory /workspace/39.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.550794477
Short name T78
Test name
Test status
Simulation time 37370157 ps
CPU time 0.64 seconds
Started Jun 10 05:09:34 PM PDT 24
Finished Jun 10 05:09:35 PM PDT 24
Peak memory 195540 kb
Host smart-8be6b1ee-43d1-4bcf-8ba4-4ae5f65b8191
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550794477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.550794477
Directory /workspace/4.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.636121413
Short name T1107
Test name
Test status
Simulation time 286513354 ps
CPU time 1.37 seconds
Started Jun 10 05:10:03 PM PDT 24
Finished Jun 10 05:10:05 PM PDT 24
Peak memory 198492 kb
Host smart-55d7f865-cca5-4631-bc6d-181f8816f4c0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636121413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.636121413
Directory /workspace/4.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.3613204459
Short name T1101
Test name
Test status
Simulation time 15493214 ps
CPU time 0.62 seconds
Started Jun 10 05:09:38 PM PDT 24
Finished Jun 10 05:09:41 PM PDT 24
Peak memory 195964 kb
Host smart-f5bbcc55-0f3e-4b22-9216-740d61b3a55c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613204459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.3613204459
Directory /workspace/4.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.1422123402
Short name T1120
Test name
Test status
Simulation time 52030217 ps
CPU time 0.65 seconds
Started Jun 10 05:09:44 PM PDT 24
Finished Jun 10 05:09:45 PM PDT 24
Peak memory 198152 kb
Host smart-a18d7c1a-cca7-4579-8de5-a21e4aa3f069
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422123402 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.1422123402
Directory /workspace/4.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_rw.1276425830
Short name T1213
Test name
Test status
Simulation time 13951555 ps
CPU time 0.6 seconds
Started Jun 10 05:09:32 PM PDT 24
Finished Jun 10 05:09:33 PM PDT 24
Peak memory 196012 kb
Host smart-ba14b983-6220-43ec-8d91-3dcbb2ed06b2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276425830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.1276425830
Directory /workspace/4.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.uart_intr_test.1621115014
Short name T1172
Test name
Test status
Simulation time 31578101 ps
CPU time 0.55 seconds
Started Jun 10 05:09:42 PM PDT 24
Finished Jun 10 05:09:43 PM PDT 24
Peak memory 194936 kb
Host smart-0b33747a-f210-4169-ba93-3c0d597deac4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621115014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.1621115014
Directory /workspace/4.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.3622252428
Short name T83
Test name
Test status
Simulation time 79995882 ps
CPU time 0.68 seconds
Started Jun 10 05:09:34 PM PDT 24
Finished Jun 10 05:09:36 PM PDT 24
Peak memory 197388 kb
Host smart-93c0b767-0d4b-4d86-bbb3-0be0e02b60b7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622252428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr
_outstanding.3622252428
Directory /workspace/4.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_errors.2098274613
Short name T1104
Test name
Test status
Simulation time 96110404 ps
CPU time 1.28 seconds
Started Jun 10 05:09:34 PM PDT 24
Finished Jun 10 05:09:37 PM PDT 24
Peak memory 200196 kb
Host smart-f51d9d43-e87e-41d0-a5cb-a9c28a416008
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098274613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.2098274613
Directory /workspace/4.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.uart_intr_test.3645433453
Short name T1103
Test name
Test status
Simulation time 153481497 ps
CPU time 0.59 seconds
Started Jun 10 05:09:46 PM PDT 24
Finished Jun 10 05:09:47 PM PDT 24
Peak memory 195016 kb
Host smart-33b54caf-8230-4632-8b7e-87e77f357ea6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645433453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.3645433453
Directory /workspace/40.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.uart_intr_test.1242531008
Short name T1218
Test name
Test status
Simulation time 53816347 ps
CPU time 0.63 seconds
Started Jun 10 05:09:45 PM PDT 24
Finished Jun 10 05:09:46 PM PDT 24
Peak memory 195024 kb
Host smart-27521211-0087-428b-839f-ef18b91a5d9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242531008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.1242531008
Directory /workspace/41.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.uart_intr_test.2023170538
Short name T1108
Test name
Test status
Simulation time 13645690 ps
CPU time 0.58 seconds
Started Jun 10 05:09:44 PM PDT 24
Finished Jun 10 05:09:45 PM PDT 24
Peak memory 195044 kb
Host smart-26152112-7d9a-4983-8293-545c8fa98dbf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023170538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.2023170538
Directory /workspace/42.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.uart_intr_test.1897639981
Short name T1212
Test name
Test status
Simulation time 14014047 ps
CPU time 0.6 seconds
Started Jun 10 05:09:38 PM PDT 24
Finished Jun 10 05:09:41 PM PDT 24
Peak memory 194980 kb
Host smart-ede4c52f-1558-482c-b88f-31875cacabd8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897639981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.1897639981
Directory /workspace/43.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.uart_intr_test.993538885
Short name T1094
Test name
Test status
Simulation time 55485663 ps
CPU time 0.6 seconds
Started Jun 10 05:09:52 PM PDT 24
Finished Jun 10 05:09:53 PM PDT 24
Peak memory 195040 kb
Host smart-21092197-eb6a-43fc-b649-25b8de7a5628
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993538885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.993538885
Directory /workspace/44.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.uart_intr_test.162148674
Short name T1227
Test name
Test status
Simulation time 18817903 ps
CPU time 0.56 seconds
Started Jun 10 05:09:41 PM PDT 24
Finished Jun 10 05:09:42 PM PDT 24
Peak memory 195004 kb
Host smart-d9a75155-d6b2-4010-94c9-da4bbc09777e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162148674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.162148674
Directory /workspace/45.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.uart_intr_test.874403633
Short name T1150
Test name
Test status
Simulation time 12188920 ps
CPU time 0.6 seconds
Started Jun 10 05:09:38 PM PDT 24
Finished Jun 10 05:09:41 PM PDT 24
Peak memory 194936 kb
Host smart-52f5adf3-1bb4-49c0-b7f2-a58a278c65e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874403633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.874403633
Directory /workspace/46.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.uart_intr_test.1198976306
Short name T1125
Test name
Test status
Simulation time 12479321 ps
CPU time 0.56 seconds
Started Jun 10 05:09:49 PM PDT 24
Finished Jun 10 05:09:49 PM PDT 24
Peak memory 194888 kb
Host smart-218e4a72-7932-4827-a11a-a2c427c77fbc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198976306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.1198976306
Directory /workspace/47.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.uart_intr_test.1987905049
Short name T1136
Test name
Test status
Simulation time 71449219 ps
CPU time 0.58 seconds
Started Jun 10 05:09:44 PM PDT 24
Finished Jun 10 05:09:45 PM PDT 24
Peak memory 195016 kb
Host smart-2a0cc35b-f8a7-445e-86aa-d48248957d52
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987905049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.1987905049
Directory /workspace/48.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.uart_intr_test.2058345427
Short name T1110
Test name
Test status
Simulation time 13732269 ps
CPU time 0.57 seconds
Started Jun 10 05:09:45 PM PDT 24
Finished Jun 10 05:09:46 PM PDT 24
Peak memory 195020 kb
Host smart-f7557a72-0b18-4c24-a337-90bde50ad896
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058345427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.2058345427
Directory /workspace/49.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.4103970372
Short name T1149
Test name
Test status
Simulation time 30020607 ps
CPU time 1.34 seconds
Started Jun 10 05:09:41 PM PDT 24
Finished Jun 10 05:09:43 PM PDT 24
Peak memory 200652 kb
Host smart-c2ad5e9d-d275-47f7-b238-6131dd6c60b7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103970372 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.4103970372
Directory /workspace/5.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_rw.1097305492
Short name T1143
Test name
Test status
Simulation time 12049429 ps
CPU time 0.59 seconds
Started Jun 10 05:09:34 PM PDT 24
Finished Jun 10 05:09:36 PM PDT 24
Peak memory 196012 kb
Host smart-3ed21bbb-46c1-43c1-a958-bb5a930674c0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097305492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.1097305492
Directory /workspace/5.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.uart_intr_test.1556282615
Short name T1186
Test name
Test status
Simulation time 37483263 ps
CPU time 0.64 seconds
Started Jun 10 05:09:32 PM PDT 24
Finished Jun 10 05:09:34 PM PDT 24
Peak memory 195024 kb
Host smart-4d94fb82-502d-460b-8546-cc5221384b4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556282615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.1556282615
Directory /workspace/5.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.1041251115
Short name T1176
Test name
Test status
Simulation time 32634594 ps
CPU time 0.75 seconds
Started Jun 10 05:09:58 PM PDT 24
Finished Jun 10 05:09:59 PM PDT 24
Peak memory 196676 kb
Host smart-ef8ee4a6-c587-4a22-b6c9-cbc70c148b04
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041251115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr
_outstanding.1041251115
Directory /workspace/5.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_errors.1794464414
Short name T1139
Test name
Test status
Simulation time 450272294 ps
CPU time 2.09 seconds
Started Jun 10 05:09:34 PM PDT 24
Finished Jun 10 05:09:37 PM PDT 24
Peak memory 200676 kb
Host smart-a323574e-3f79-4bc0-90c0-cebdb85ac64f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794464414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.1794464414
Directory /workspace/5.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.1691227922
Short name T101
Test name
Test status
Simulation time 92437075 ps
CPU time 0.93 seconds
Started Jun 10 05:09:34 PM PDT 24
Finished Jun 10 05:09:36 PM PDT 24
Peak memory 198828 kb
Host smart-30ba66f6-5366-4e73-8486-7b2b486c715c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691227922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.1691227922
Directory /workspace/5.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.67088414
Short name T1134
Test name
Test status
Simulation time 49204960 ps
CPU time 0.77 seconds
Started Jun 10 05:09:40 PM PDT 24
Finished Jun 10 05:09:42 PM PDT 24
Peak memory 199388 kb
Host smart-f271f100-e1d8-452f-8ba0-a45d5813085a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67088414 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.67088414
Directory /workspace/6.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_rw.4233445380
Short name T1210
Test name
Test status
Simulation time 15990883 ps
CPU time 0.61 seconds
Started Jun 10 05:09:34 PM PDT 24
Finished Jun 10 05:09:36 PM PDT 24
Peak memory 195972 kb
Host smart-de665573-66e6-492d-aa07-f1f19ef84c34
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233445380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.4233445380
Directory /workspace/6.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.uart_intr_test.2241027672
Short name T1220
Test name
Test status
Simulation time 43360284 ps
CPU time 0.58 seconds
Started Jun 10 05:09:45 PM PDT 24
Finished Jun 10 05:09:46 PM PDT 24
Peak memory 195024 kb
Host smart-674f2c7e-76a5-460a-8cea-e9bf22039b5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241027672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.2241027672
Directory /workspace/6.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.999791304
Short name T1182
Test name
Test status
Simulation time 99456376 ps
CPU time 0.77 seconds
Started Jun 10 05:09:34 PM PDT 24
Finished Jun 10 05:09:41 PM PDT 24
Peak memory 197892 kb
Host smart-32a6d3ac-e5a4-4981-9437-32678999b258
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999791304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr_
outstanding.999791304
Directory /workspace/6.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_errors.2965967777
Short name T1099
Test name
Test status
Simulation time 461158073 ps
CPU time 1.32 seconds
Started Jun 10 05:09:50 PM PDT 24
Finished Jun 10 05:09:52 PM PDT 24
Peak memory 200688 kb
Host smart-3fed74f4-c266-43dd-aaaa-8c28e69d75a2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965967777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.2965967777
Directory /workspace/6.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.175587120
Short name T1214
Test name
Test status
Simulation time 502430993 ps
CPU time 1.38 seconds
Started Jun 10 05:09:32 PM PDT 24
Finished Jun 10 05:09:34 PM PDT 24
Peak memory 199976 kb
Host smart-24cc0ba0-9068-4783-8be0-d5d366d07f18
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175587120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.175587120
Directory /workspace/6.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.3676662545
Short name T1187
Test name
Test status
Simulation time 22385858 ps
CPU time 1.11 seconds
Started Jun 10 05:09:38 PM PDT 24
Finished Jun 10 05:09:41 PM PDT 24
Peak memory 200500 kb
Host smart-f318a44e-d4de-4a90-9f99-35a02da1d2d7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676662545 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.3676662545
Directory /workspace/7.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_rw.3906649108
Short name T1126
Test name
Test status
Simulation time 60093151 ps
CPU time 0.63 seconds
Started Jun 10 05:09:38 PM PDT 24
Finished Jun 10 05:09:41 PM PDT 24
Peak memory 195948 kb
Host smart-9fce20d8-8397-418c-bfdb-d4f152deba20
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906649108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.3906649108
Directory /workspace/7.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.uart_intr_test.1901449662
Short name T1147
Test name
Test status
Simulation time 36654748 ps
CPU time 0.59 seconds
Started Jun 10 05:09:35 PM PDT 24
Finished Jun 10 05:09:37 PM PDT 24
Peak memory 195036 kb
Host smart-64d402e7-716e-4541-9f01-789360880634
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901449662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.1901449662
Directory /workspace/7.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.1533210971
Short name T1119
Test name
Test status
Simulation time 148718812 ps
CPU time 0.7 seconds
Started Jun 10 05:09:36 PM PDT 24
Finished Jun 10 05:09:39 PM PDT 24
Peak memory 196120 kb
Host smart-8c16e0d3-ac6f-45c3-97ab-39171e2ec498
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533210971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr
_outstanding.1533210971
Directory /workspace/7.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_errors.817812907
Short name T1144
Test name
Test status
Simulation time 70375844 ps
CPU time 1.83 seconds
Started Jun 10 05:09:35 PM PDT 24
Finished Jun 10 05:09:38 PM PDT 24
Peak memory 200680 kb
Host smart-4f889627-2113-4824-9eab-5855a50423b2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817812907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.817812907
Directory /workspace/7.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.1305276603
Short name T97
Test name
Test status
Simulation time 38604405 ps
CPU time 0.97 seconds
Started Jun 10 05:09:35 PM PDT 24
Finished Jun 10 05:09:37 PM PDT 24
Peak memory 199632 kb
Host smart-9fbef3fc-9640-4936-a99a-a376a07c4421
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305276603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.1305276603
Directory /workspace/7.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.1542933775
Short name T1226
Test name
Test status
Simulation time 113774311 ps
CPU time 0.86 seconds
Started Jun 10 05:09:35 PM PDT 24
Finished Jun 10 05:09:37 PM PDT 24
Peak memory 200436 kb
Host smart-897d49c0-3794-4e8d-8b68-f2f421fdc2db
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542933775 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.1542933775
Directory /workspace/8.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_rw.3729289993
Short name T1180
Test name
Test status
Simulation time 50677858 ps
CPU time 0.59 seconds
Started Jun 10 05:09:34 PM PDT 24
Finished Jun 10 05:09:36 PM PDT 24
Peak memory 196044 kb
Host smart-779ef3ee-99bb-41e4-99a4-3b385b3a69b1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729289993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.3729289993
Directory /workspace/8.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.uart_intr_test.4166268496
Short name T1185
Test name
Test status
Simulation time 14981350 ps
CPU time 0.63 seconds
Started Jun 10 05:09:42 PM PDT 24
Finished Jun 10 05:09:43 PM PDT 24
Peak memory 194984 kb
Host smart-9e6a9cf2-f493-4910-9c6d-ca8d1bf79d89
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166268496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.4166268496
Directory /workspace/8.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.3589229470
Short name T82
Test name
Test status
Simulation time 112907101 ps
CPU time 0.8 seconds
Started Jun 10 05:09:43 PM PDT 24
Finished Jun 10 05:09:45 PM PDT 24
Peak memory 197580 kb
Host smart-59b5b964-d6c3-461f-966b-401a1c08d328
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589229470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr
_outstanding.3589229470
Directory /workspace/8.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_errors.1675816972
Short name T1181
Test name
Test status
Simulation time 65341825 ps
CPU time 1.4 seconds
Started Jun 10 05:09:43 PM PDT 24
Finished Jun 10 05:09:44 PM PDT 24
Peak memory 200652 kb
Host smart-e8151957-3fc1-4a10-8a50-056d8cfdf127
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675816972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.1675816972
Directory /workspace/8.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.1223472864
Short name T1141
Test name
Test status
Simulation time 52019674 ps
CPU time 1.02 seconds
Started Jun 10 05:09:39 PM PDT 24
Finished Jun 10 05:09:42 PM PDT 24
Peak memory 199664 kb
Host smart-9ae8a1af-c189-4dea-b7da-4f5dfaa65596
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223472864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.1223472864
Directory /workspace/8.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.3250170495
Short name T1209
Test name
Test status
Simulation time 70561752 ps
CPU time 0.7 seconds
Started Jun 10 05:09:46 PM PDT 24
Finished Jun 10 05:09:47 PM PDT 24
Peak memory 199472 kb
Host smart-aa65b14c-b6f5-40f2-9181-5f6333714b0f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250170495 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.3250170495
Directory /workspace/9.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_rw.4166313923
Short name T72
Test name
Test status
Simulation time 264609427 ps
CPU time 0.65 seconds
Started Jun 10 05:09:38 PM PDT 24
Finished Jun 10 05:09:41 PM PDT 24
Peak memory 196052 kb
Host smart-d186075d-31a2-4036-8501-8074a6c50696
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166313923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.4166313923
Directory /workspace/9.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.uart_intr_test.1883056282
Short name T1117
Test name
Test status
Simulation time 18801026 ps
CPU time 0.58 seconds
Started Jun 10 05:09:42 PM PDT 24
Finished Jun 10 05:09:44 PM PDT 24
Peak memory 194956 kb
Host smart-2dca540c-8952-4f71-9a47-443077318b9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883056282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.1883056282
Directory /workspace/9.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.2781926854
Short name T1188
Test name
Test status
Simulation time 125018252 ps
CPU time 0.76 seconds
Started Jun 10 05:09:36 PM PDT 24
Finished Jun 10 05:09:38 PM PDT 24
Peak memory 197744 kb
Host smart-bd72161c-6ee9-48ed-a205-75c3d579146d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781926854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr
_outstanding.2781926854
Directory /workspace/9.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_errors.6493477
Short name T1096
Test name
Test status
Simulation time 82512202 ps
CPU time 1.34 seconds
Started Jun 10 05:09:43 PM PDT 24
Finished Jun 10 05:09:45 PM PDT 24
Peak memory 200620 kb
Host smart-ec2c5574-5935-41f8-9f41-44643015ea0d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6493477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.6493477
Directory /workspace/9.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.185166073
Short name T99
Test name
Test status
Simulation time 314423809 ps
CPU time 1.33 seconds
Started Jun 10 05:09:44 PM PDT 24
Finished Jun 10 05:09:46 PM PDT 24
Peak memory 200000 kb
Host smart-23a7546b-e001-4388-8389-17087c160a26
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185166073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.185166073
Directory /workspace/9.uart_tl_intg_err/latest

Test location /workspace/coverage/default/0.uart_alert_test.553381199
Short name T492
Test name
Test status
Simulation time 190267292 ps
CPU time 0.63 seconds
Started Jun 10 05:12:35 PM PDT 24
Finished Jun 10 05:12:36 PM PDT 24
Peak memory 195716 kb
Host smart-ab3ae2d1-5359-4bbc-873f-f65f73c89008
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553381199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.553381199
Directory /workspace/0.uart_alert_test/latest

Test location /workspace/coverage/default/0.uart_fifo_overflow.2830299500
Short name T891
Test name
Test status
Simulation time 22852430792 ps
CPU time 37.88 seconds
Started Jun 10 05:12:40 PM PDT 24
Finished Jun 10 05:13:19 PM PDT 24
Peak memory 200232 kb
Host smart-6a87e52f-3410-4000-97ee-5379dee2c556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830299500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.2830299500
Directory /workspace/0.uart_fifo_overflow/latest

Test location /workspace/coverage/default/0.uart_fifo_reset.4005784473
Short name T801
Test name
Test status
Simulation time 72703147048 ps
CPU time 180.98 seconds
Started Jun 10 05:12:36 PM PDT 24
Finished Jun 10 05:15:37 PM PDT 24
Peak memory 200380 kb
Host smart-30089830-db2a-4556-9b5a-457d62885175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005784473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.4005784473
Directory /workspace/0.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_long_xfer_wo_dly.603131924
Short name T502
Test name
Test status
Simulation time 42814330527 ps
CPU time 291.17 seconds
Started Jun 10 05:12:41 PM PDT 24
Finished Jun 10 05:17:32 PM PDT 24
Peak memory 200312 kb
Host smart-d41cf5b3-b0a0-410d-80d7-3103dc68232a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=603131924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.603131924
Directory /workspace/0.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/0.uart_loopback.39322421
Short name T678
Test name
Test status
Simulation time 1387136894 ps
CPU time 2.68 seconds
Started Jun 10 05:12:32 PM PDT 24
Finished Jun 10 05:12:35 PM PDT 24
Peak memory 198716 kb
Host smart-c5e32c0d-9a99-4173-bebe-1be3e5d68a24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39322421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_loopback.39322421
Directory /workspace/0.uart_loopback/latest

Test location /workspace/coverage/default/0.uart_rx_oversample.4199512082
Short name T978
Test name
Test status
Simulation time 2022120196 ps
CPU time 2.89 seconds
Started Jun 10 05:12:40 PM PDT 24
Finished Jun 10 05:12:43 PM PDT 24
Peak memory 198280 kb
Host smart-b2fe01ed-f935-47a3-aea1-24a49a37f3c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4199512082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.4199512082
Directory /workspace/0.uart_rx_oversample/latest

Test location /workspace/coverage/default/0.uart_rx_parity_err.559364808
Short name T544
Test name
Test status
Simulation time 219101442984 ps
CPU time 337.04 seconds
Started Jun 10 05:12:39 PM PDT 24
Finished Jun 10 05:18:17 PM PDT 24
Peak memory 200312 kb
Host smart-f2bc97ba-e566-45dd-9ffa-4c597e1256ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559364808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.559364808
Directory /workspace/0.uart_rx_parity_err/latest

Test location /workspace/coverage/default/0.uart_rx_start_bit_filter.416418266
Short name T568
Test name
Test status
Simulation time 51033992397 ps
CPU time 77.19 seconds
Started Jun 10 05:12:36 PM PDT 24
Finished Jun 10 05:13:54 PM PDT 24
Peak memory 196460 kb
Host smart-587242b3-b7fb-4105-be62-6dda7f418a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416418266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.416418266
Directory /workspace/0.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/0.uart_smoke.4282213052
Short name T281
Test name
Test status
Simulation time 882846288 ps
CPU time 4.55 seconds
Started Jun 10 05:12:30 PM PDT 24
Finished Jun 10 05:12:35 PM PDT 24
Peak memory 198608 kb
Host smart-011ee88a-4f49-48ca-b16c-9745f62340b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282213052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_smoke.4282213052
Directory /workspace/0.uart_smoke/latest

Test location /workspace/coverage/default/0.uart_tx_ovrd.980389925
Short name T911
Test name
Test status
Simulation time 1191160752 ps
CPU time 3.11 seconds
Started Jun 10 05:12:36 PM PDT 24
Finished Jun 10 05:12:39 PM PDT 24
Peak memory 199860 kb
Host smart-903c646b-189c-4bcd-a84f-1611e3e43394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980389925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.980389925
Directory /workspace/0.uart_tx_ovrd/latest

Test location /workspace/coverage/default/0.uart_tx_rx.342125131
Short name T293
Test name
Test status
Simulation time 10099377390 ps
CPU time 17.18 seconds
Started Jun 10 05:12:35 PM PDT 24
Finished Jun 10 05:12:52 PM PDT 24
Peak memory 198816 kb
Host smart-c7b586fc-5389-455d-81c4-90fcf6664ba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342125131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.342125131
Directory /workspace/0.uart_tx_rx/latest

Test location /workspace/coverage/default/1.uart_alert_test.1363628352
Short name T776
Test name
Test status
Simulation time 13675243 ps
CPU time 0.56 seconds
Started Jun 10 05:12:43 PM PDT 24
Finished Jun 10 05:12:44 PM PDT 24
Peak memory 194728 kb
Host smart-485acd2c-c7e9-4f34-8054-0d6188d7c25b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363628352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.1363628352
Directory /workspace/1.uart_alert_test/latest

Test location /workspace/coverage/default/1.uart_fifo_overflow.1721533754
Short name T679
Test name
Test status
Simulation time 187222410734 ps
CPU time 74.14 seconds
Started Jun 10 05:12:37 PM PDT 24
Finished Jun 10 05:13:51 PM PDT 24
Peak memory 200356 kb
Host smart-8059694c-c67a-467e-82b9-5397bc6e003d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721533754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.1721533754
Directory /workspace/1.uart_fifo_overflow/latest

Test location /workspace/coverage/default/1.uart_fifo_reset.2931578617
Short name T326
Test name
Test status
Simulation time 253620665140 ps
CPU time 204.94 seconds
Started Jun 10 05:12:41 PM PDT 24
Finished Jun 10 05:16:06 PM PDT 24
Peak memory 200304 kb
Host smart-f9c222ae-550b-4529-bbfd-019d5d775514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931578617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.2931578617
Directory /workspace/1.uart_fifo_reset/latest

Test location /workspace/coverage/default/1.uart_intr.3216361189
Short name T415
Test name
Test status
Simulation time 28575466934 ps
CPU time 40.99 seconds
Started Jun 10 05:12:44 PM PDT 24
Finished Jun 10 05:13:26 PM PDT 24
Peak memory 198988 kb
Host smart-e548f214-543b-4ee4-a491-2eb87f98cb70
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216361189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.3216361189
Directory /workspace/1.uart_intr/latest

Test location /workspace/coverage/default/1.uart_long_xfer_wo_dly.3788392656
Short name T912
Test name
Test status
Simulation time 55769840867 ps
CPU time 214.15 seconds
Started Jun 10 05:12:45 PM PDT 24
Finished Jun 10 05:16:19 PM PDT 24
Peak memory 200292 kb
Host smart-af1f6180-c875-4be1-bf1d-f8b3ddf5d4b4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3788392656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.3788392656
Directory /workspace/1.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/1.uart_loopback.2919997554
Short name T346
Test name
Test status
Simulation time 4028590332 ps
CPU time 2.83 seconds
Started Jun 10 05:12:50 PM PDT 24
Finished Jun 10 05:12:53 PM PDT 24
Peak memory 199268 kb
Host smart-a700231f-963c-45ad-b1b7-ccfece82c2e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919997554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_loopback.2919997554
Directory /workspace/1.uart_loopback/latest

Test location /workspace/coverage/default/1.uart_perf.1149728092
Short name T255
Test name
Test status
Simulation time 19496227685 ps
CPU time 348.73 seconds
Started Jun 10 05:12:45 PM PDT 24
Finished Jun 10 05:18:34 PM PDT 24
Peak memory 200252 kb
Host smart-85a5c3c6-6300-4e2f-95d4-a6bed492e333
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1149728092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.1149728092
Directory /workspace/1.uart_perf/latest

Test location /workspace/coverage/default/1.uart_rx_oversample.2806328650
Short name T354
Test name
Test status
Simulation time 6310227472 ps
CPU time 8.02 seconds
Started Jun 10 05:12:38 PM PDT 24
Finished Jun 10 05:12:46 PM PDT 24
Peak memory 198740 kb
Host smart-7d2c9b83-7daf-4d48-90b4-9b9b4b6bc7e6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2806328650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.2806328650
Directory /workspace/1.uart_rx_oversample/latest

Test location /workspace/coverage/default/1.uart_rx_parity_err.2623932574
Short name T1076
Test name
Test status
Simulation time 113082235174 ps
CPU time 22.7 seconds
Started Jun 10 05:12:40 PM PDT 24
Finished Jun 10 05:13:03 PM PDT 24
Peak memory 200228 kb
Host smart-fe801076-2dcf-49d7-848c-f63cfd958bcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623932574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.2623932574
Directory /workspace/1.uart_rx_parity_err/latest

Test location /workspace/coverage/default/1.uart_rx_start_bit_filter.2338323239
Short name T684
Test name
Test status
Simulation time 3821960810 ps
CPU time 7.46 seconds
Started Jun 10 05:12:42 PM PDT 24
Finished Jun 10 05:12:50 PM PDT 24
Peak memory 197016 kb
Host smart-235af0a3-6f29-42e1-adf1-cfb4f4c96bf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338323239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.2338323239
Directory /workspace/1.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/1.uart_sec_cm.355184472
Short name T28
Test name
Test status
Simulation time 250961321 ps
CPU time 0.9 seconds
Started Jun 10 05:12:43 PM PDT 24
Finished Jun 10 05:12:44 PM PDT 24
Peak memory 218832 kb
Host smart-34ec5554-ba78-4c30-81c7-52c967f51c0c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355184472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.355184472
Directory /workspace/1.uart_sec_cm/latest

Test location /workspace/coverage/default/1.uart_smoke.876598594
Short name T810
Test name
Test status
Simulation time 448754992 ps
CPU time 2.03 seconds
Started Jun 10 05:12:37 PM PDT 24
Finished Jun 10 05:12:40 PM PDT 24
Peak memory 199956 kb
Host smart-8e0a8db8-60dc-4182-bfb6-f9ce763faf72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876598594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_smoke.876598594
Directory /workspace/1.uart_smoke/latest

Test location /workspace/coverage/default/1.uart_stress_all.2638544567
Short name T643
Test name
Test status
Simulation time 236639795734 ps
CPU time 1200.24 seconds
Started Jun 10 05:12:41 PM PDT 24
Finished Jun 10 05:32:42 PM PDT 24
Peak memory 200284 kb
Host smart-2e5e5731-8daa-47a7-af06-3d0cbbddc8f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638544567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.2638544567
Directory /workspace/1.uart_stress_all/latest

Test location /workspace/coverage/default/1.uart_tx_ovrd.1117200270
Short name T394
Test name
Test status
Simulation time 6835321510 ps
CPU time 9.94 seconds
Started Jun 10 05:12:41 PM PDT 24
Finished Jun 10 05:12:51 PM PDT 24
Peak memory 200320 kb
Host smart-2bcb9a48-f462-4363-94b6-25750124eba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117200270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.1117200270
Directory /workspace/1.uart_tx_ovrd/latest

Test location /workspace/coverage/default/1.uart_tx_rx.1653505917
Short name T582
Test name
Test status
Simulation time 45823775860 ps
CPU time 20.97 seconds
Started Jun 10 05:12:37 PM PDT 24
Finished Jun 10 05:12:58 PM PDT 24
Peak memory 200408 kb
Host smart-0caf6286-c115-414b-afca-4ceb79685f31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653505917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.1653505917
Directory /workspace/1.uart_tx_rx/latest

Test location /workspace/coverage/default/10.uart_alert_test.2799698862
Short name T636
Test name
Test status
Simulation time 15738680 ps
CPU time 0.57 seconds
Started Jun 10 05:13:17 PM PDT 24
Finished Jun 10 05:13:17 PM PDT 24
Peak memory 195728 kb
Host smart-687ecc8f-32b7-435f-8d08-aac38941e50d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799698862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.2799698862
Directory /workspace/10.uart_alert_test/latest

Test location /workspace/coverage/default/10.uart_fifo_full.4094608605
Short name T411
Test name
Test status
Simulation time 96828662016 ps
CPU time 154.65 seconds
Started Jun 10 05:13:20 PM PDT 24
Finished Jun 10 05:15:55 PM PDT 24
Peak memory 200244 kb
Host smart-c87cd7c2-23b5-45e5-87d3-54beb656ecfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094608605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.4094608605
Directory /workspace/10.uart_fifo_full/latest

Test location /workspace/coverage/default/10.uart_fifo_overflow.2388596456
Short name T282
Test name
Test status
Simulation time 128477694858 ps
CPU time 51.23 seconds
Started Jun 10 05:13:18 PM PDT 24
Finished Jun 10 05:14:09 PM PDT 24
Peak memory 200124 kb
Host smart-6ad9267f-8edf-46ec-8e3b-8d338b22625e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388596456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.2388596456
Directory /workspace/10.uart_fifo_overflow/latest

Test location /workspace/coverage/default/10.uart_fifo_reset.1731800788
Short name T653
Test name
Test status
Simulation time 143500410061 ps
CPU time 60.21 seconds
Started Jun 10 05:13:16 PM PDT 24
Finished Jun 10 05:14:17 PM PDT 24
Peak memory 200244 kb
Host smart-b9fb861a-cb8d-4458-9d33-aa6d836367e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731800788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.1731800788
Directory /workspace/10.uart_fifo_reset/latest

Test location /workspace/coverage/default/10.uart_intr.1110460200
Short name T711
Test name
Test status
Simulation time 235733199014 ps
CPU time 440.98 seconds
Started Jun 10 05:13:26 PM PDT 24
Finished Jun 10 05:20:47 PM PDT 24
Peak memory 199892 kb
Host smart-6ece98fe-2adb-4ba2-a56e-450d2d35901c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110460200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.1110460200
Directory /workspace/10.uart_intr/latest

Test location /workspace/coverage/default/10.uart_long_xfer_wo_dly.1529368714
Short name T271
Test name
Test status
Simulation time 56509616666 ps
CPU time 328.62 seconds
Started Jun 10 05:13:19 PM PDT 24
Finished Jun 10 05:18:48 PM PDT 24
Peak memory 200368 kb
Host smart-0fc8ebdc-0725-418b-b824-b973fbe374aa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1529368714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.1529368714
Directory /workspace/10.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/10.uart_loopback.2923503423
Short name T1045
Test name
Test status
Simulation time 1977974081 ps
CPU time 1.68 seconds
Started Jun 10 05:13:21 PM PDT 24
Finished Jun 10 05:13:23 PM PDT 24
Peak memory 196328 kb
Host smart-1aec242c-844a-484b-af79-69da8b279e32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923503423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_loopback.2923503423
Directory /workspace/10.uart_loopback/latest

Test location /workspace/coverage/default/10.uart_perf.2461826325
Short name T1086
Test name
Test status
Simulation time 11865974359 ps
CPU time 299.04 seconds
Started Jun 10 05:13:20 PM PDT 24
Finished Jun 10 05:18:19 PM PDT 24
Peak memory 200220 kb
Host smart-a99c5ebf-7556-4670-898f-ffe144b6222b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2461826325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.2461826325
Directory /workspace/10.uart_perf/latest

Test location /workspace/coverage/default/10.uart_rx_oversample.3157594977
Short name T126
Test name
Test status
Simulation time 2762150857 ps
CPU time 11.6 seconds
Started Jun 10 05:13:19 PM PDT 24
Finished Jun 10 05:13:31 PM PDT 24
Peak memory 200228 kb
Host smart-d4c88011-e8f7-4483-b63b-564e5c196d06
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3157594977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.3157594977
Directory /workspace/10.uart_rx_oversample/latest

Test location /workspace/coverage/default/10.uart_rx_parity_err.1767689292
Short name T404
Test name
Test status
Simulation time 12637833879 ps
CPU time 18.65 seconds
Started Jun 10 05:13:17 PM PDT 24
Finished Jun 10 05:13:36 PM PDT 24
Peak memory 198852 kb
Host smart-5254e81a-6c84-4509-ac0f-3c527d931d66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767689292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.1767689292
Directory /workspace/10.uart_rx_parity_err/latest

Test location /workspace/coverage/default/10.uart_rx_start_bit_filter.336628661
Short name T482
Test name
Test status
Simulation time 2827497130 ps
CPU time 5.31 seconds
Started Jun 10 05:13:19 PM PDT 24
Finished Jun 10 05:13:24 PM PDT 24
Peak memory 196824 kb
Host smart-06745b22-2745-42ef-9bc7-4728a0cb8ed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336628661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.336628661
Directory /workspace/10.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/10.uart_smoke.110987402
Short name T915
Test name
Test status
Simulation time 290061672 ps
CPU time 1.76 seconds
Started Jun 10 05:13:18 PM PDT 24
Finished Jun 10 05:13:20 PM PDT 24
Peak memory 198536 kb
Host smart-fe7f19e5-62dd-4790-be5a-fc6b26ea5bfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110987402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_smoke.110987402
Directory /workspace/10.uart_smoke/latest

Test location /workspace/coverage/default/10.uart_stress_all_with_rand_reset.579281338
Short name T867
Test name
Test status
Simulation time 66666799360 ps
CPU time 730.96 seconds
Started Jun 10 05:13:21 PM PDT 24
Finished Jun 10 05:25:32 PM PDT 24
Peak memory 227440 kb
Host smart-c3d122c7-cd31-4eec-a01f-11e3dee2e8d8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579281338 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 10.uart_stress_all_with_rand_reset.579281338
Directory /workspace/10.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.uart_tx_ovrd.1052823562
Short name T657
Test name
Test status
Simulation time 298656522 ps
CPU time 1.48 seconds
Started Jun 10 05:13:21 PM PDT 24
Finished Jun 10 05:13:23 PM PDT 24
Peak memory 199528 kb
Host smart-7d870c3e-1745-4193-b7ae-375dfa518bd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052823562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.1052823562
Directory /workspace/10.uart_tx_ovrd/latest

Test location /workspace/coverage/default/10.uart_tx_rx.3966188171
Short name T820
Test name
Test status
Simulation time 128489956909 ps
CPU time 24.44 seconds
Started Jun 10 05:13:18 PM PDT 24
Finished Jun 10 05:13:43 PM PDT 24
Peak memory 200352 kb
Host smart-d30bb43d-07e5-4e56-a96d-b58cbb5ee082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966188171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.3966188171
Directory /workspace/10.uart_tx_rx/latest

Test location /workspace/coverage/default/102.uart_fifo_reset.4034737098
Short name T699
Test name
Test status
Simulation time 85274252746 ps
CPU time 123.04 seconds
Started Jun 10 05:15:22 PM PDT 24
Finished Jun 10 05:17:26 PM PDT 24
Peak memory 200348 kb
Host smart-e6c15072-e67b-48ef-abf1-c9adf56792be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034737098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.4034737098
Directory /workspace/102.uart_fifo_reset/latest

Test location /workspace/coverage/default/103.uart_fifo_reset.4161802663
Short name T992
Test name
Test status
Simulation time 77367240624 ps
CPU time 29.76 seconds
Started Jun 10 05:15:23 PM PDT 24
Finished Jun 10 05:15:53 PM PDT 24
Peak memory 200280 kb
Host smart-c3a8dbf6-5b76-4592-92ca-7bcfa2d340c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161802663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.4161802663
Directory /workspace/103.uart_fifo_reset/latest

Test location /workspace/coverage/default/104.uart_fifo_reset.261405727
Short name T738
Test name
Test status
Simulation time 287198017057 ps
CPU time 30.06 seconds
Started Jun 10 05:15:29 PM PDT 24
Finished Jun 10 05:15:59 PM PDT 24
Peak memory 200160 kb
Host smart-9b90cc52-f7b8-434c-b55e-568d0fa520b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261405727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.261405727
Directory /workspace/104.uart_fifo_reset/latest

Test location /workspace/coverage/default/105.uart_fifo_reset.1698252188
Short name T220
Test name
Test status
Simulation time 120291326030 ps
CPU time 180.88 seconds
Started Jun 10 05:15:23 PM PDT 24
Finished Jun 10 05:18:24 PM PDT 24
Peak memory 200308 kb
Host smart-b22001e2-36ab-4435-a691-7e60e91a33b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698252188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.1698252188
Directory /workspace/105.uart_fifo_reset/latest

Test location /workspace/coverage/default/106.uart_fifo_reset.888752141
Short name T1061
Test name
Test status
Simulation time 76499051839 ps
CPU time 109.74 seconds
Started Jun 10 05:15:19 PM PDT 24
Finished Jun 10 05:17:09 PM PDT 24
Peak memory 200184 kb
Host smart-5233ade1-a2b6-4571-8307-aa150fb96501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888752141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.888752141
Directory /workspace/106.uart_fifo_reset/latest

Test location /workspace/coverage/default/107.uart_fifo_reset.3004886887
Short name T716
Test name
Test status
Simulation time 55432154989 ps
CPU time 24.24 seconds
Started Jun 10 05:15:20 PM PDT 24
Finished Jun 10 05:15:45 PM PDT 24
Peak memory 200420 kb
Host smart-4174ae21-2098-446c-a283-8eb8a07d18d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004886887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.3004886887
Directory /workspace/107.uart_fifo_reset/latest

Test location /workspace/coverage/default/109.uart_fifo_reset.3888701188
Short name T473
Test name
Test status
Simulation time 18675149687 ps
CPU time 8.52 seconds
Started Jun 10 05:15:22 PM PDT 24
Finished Jun 10 05:15:31 PM PDT 24
Peak memory 200240 kb
Host smart-3ba8d9d4-5995-4907-85a6-2752f5ab24e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888701188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.3888701188
Directory /workspace/109.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_alert_test.2655370776
Short name T883
Test name
Test status
Simulation time 75440691 ps
CPU time 0.59 seconds
Started Jun 10 05:13:25 PM PDT 24
Finished Jun 10 05:13:26 PM PDT 24
Peak memory 195696 kb
Host smart-70cec004-1f6f-4c24-b1a8-876751b0ef4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655370776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.2655370776
Directory /workspace/11.uart_alert_test/latest

Test location /workspace/coverage/default/11.uart_fifo_full.3256479785
Short name T1090
Test name
Test status
Simulation time 103553217244 ps
CPU time 92.05 seconds
Started Jun 10 05:13:20 PM PDT 24
Finished Jun 10 05:14:52 PM PDT 24
Peak memory 200308 kb
Host smart-bcd477a9-ad50-4d00-90d0-c860f2728e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256479785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.3256479785
Directory /workspace/11.uart_fifo_full/latest

Test location /workspace/coverage/default/11.uart_fifo_overflow.696493273
Short name T487
Test name
Test status
Simulation time 221694182144 ps
CPU time 161.55 seconds
Started Jun 10 05:13:19 PM PDT 24
Finished Jun 10 05:16:01 PM PDT 24
Peak memory 200372 kb
Host smart-e93f51cb-7b0d-4576-865d-821880e023d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696493273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.696493273
Directory /workspace/11.uart_fifo_overflow/latest

Test location /workspace/coverage/default/11.uart_fifo_reset.3760789964
Short name T193
Test name
Test status
Simulation time 22858849303 ps
CPU time 33.74 seconds
Started Jun 10 05:13:17 PM PDT 24
Finished Jun 10 05:13:51 PM PDT 24
Peak memory 199988 kb
Host smart-750e2510-77f1-420f-8429-6ef18ac50275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760789964 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.3760789964
Directory /workspace/11.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_intr.1348073538
Short name T1038
Test name
Test status
Simulation time 87104198706 ps
CPU time 30 seconds
Started Jun 10 05:13:17 PM PDT 24
Finished Jun 10 05:13:47 PM PDT 24
Peak memory 200348 kb
Host smart-fee46256-6895-435c-8525-d8f829649e41
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348073538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.1348073538
Directory /workspace/11.uart_intr/latest

Test location /workspace/coverage/default/11.uart_long_xfer_wo_dly.3774414431
Short name T611
Test name
Test status
Simulation time 98586763956 ps
CPU time 654.37 seconds
Started Jun 10 05:13:23 PM PDT 24
Finished Jun 10 05:24:18 PM PDT 24
Peak memory 200324 kb
Host smart-a94dcc48-8c6d-40c2-97ec-7914173fc57a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3774414431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.3774414431
Directory /workspace/11.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/11.uart_loopback.1117251956
Short name T51
Test name
Test status
Simulation time 1192273465 ps
CPU time 2.54 seconds
Started Jun 10 05:13:19 PM PDT 24
Finished Jun 10 05:13:22 PM PDT 24
Peak memory 195956 kb
Host smart-ec5c2fbc-5d7b-445a-a609-17dfcf3d3799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117251956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_loopback.1117251956
Directory /workspace/11.uart_loopback/latest

Test location /workspace/coverage/default/11.uart_perf.880177659
Short name T1077
Test name
Test status
Simulation time 12523505319 ps
CPU time 191.03 seconds
Started Jun 10 05:13:18 PM PDT 24
Finished Jun 10 05:16:29 PM PDT 24
Peak memory 200252 kb
Host smart-9eba981b-cc6e-493b-a5ca-f930f5c28a45
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=880177659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.880177659
Directory /workspace/11.uart_perf/latest

Test location /workspace/coverage/default/11.uart_rx_oversample.3758748525
Short name T1021
Test name
Test status
Simulation time 3860022703 ps
CPU time 28.17 seconds
Started Jun 10 05:13:17 PM PDT 24
Finished Jun 10 05:13:46 PM PDT 24
Peak memory 198488 kb
Host smart-05d34ca5-696a-4933-98eb-93ffa3cc107e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3758748525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.3758748525
Directory /workspace/11.uart_rx_oversample/latest

Test location /workspace/coverage/default/11.uart_rx_parity_err.1519002347
Short name T567
Test name
Test status
Simulation time 28525695945 ps
CPU time 49.97 seconds
Started Jun 10 05:13:19 PM PDT 24
Finished Jun 10 05:14:09 PM PDT 24
Peak memory 200208 kb
Host smart-a1c74ffa-448a-46ce-a526-19bcbc25eed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519002347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.1519002347
Directory /workspace/11.uart_rx_parity_err/latest

Test location /workspace/coverage/default/11.uart_rx_start_bit_filter.4007676803
Short name T5
Test name
Test status
Simulation time 49767408491 ps
CPU time 22.99 seconds
Started Jun 10 05:13:23 PM PDT 24
Finished Jun 10 05:13:47 PM PDT 24
Peak memory 196128 kb
Host smart-8276f797-15a8-4042-8f32-983ab5bf54a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007676803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.4007676803
Directory /workspace/11.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/11.uart_smoke.3123978600
Short name T306
Test name
Test status
Simulation time 840219880 ps
CPU time 3.99 seconds
Started Jun 10 05:13:20 PM PDT 24
Finished Jun 10 05:13:25 PM PDT 24
Peak memory 200248 kb
Host smart-071d90a5-dd6d-4f0d-a971-9bf98e5be603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123978600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_smoke.3123978600
Directory /workspace/11.uart_smoke/latest

Test location /workspace/coverage/default/11.uart_stress_all.3301826292
Short name T305
Test name
Test status
Simulation time 259288950390 ps
CPU time 475.4 seconds
Started Jun 10 05:13:22 PM PDT 24
Finished Jun 10 05:21:18 PM PDT 24
Peak memory 200224 kb
Host smart-142c5b57-39e6-400f-888b-c1edbba73311
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301826292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.3301826292
Directory /workspace/11.uart_stress_all/latest

Test location /workspace/coverage/default/11.uart_tx_ovrd.2270877903
Short name T372
Test name
Test status
Simulation time 349906615 ps
CPU time 1.63 seconds
Started Jun 10 05:13:19 PM PDT 24
Finished Jun 10 05:13:20 PM PDT 24
Peak memory 198852 kb
Host smart-4e39271e-58d6-4785-a5f6-4399f95f71f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270877903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.2270877903
Directory /workspace/11.uart_tx_ovrd/latest

Test location /workspace/coverage/default/11.uart_tx_rx.159729164
Short name T644
Test name
Test status
Simulation time 136215070492 ps
CPU time 259.17 seconds
Started Jun 10 05:13:18 PM PDT 24
Finished Jun 10 05:17:37 PM PDT 24
Peak memory 200316 kb
Host smart-1d932abd-f151-47e3-a3fe-cba627856029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159729164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.159729164
Directory /workspace/11.uart_tx_rx/latest

Test location /workspace/coverage/default/110.uart_fifo_reset.1242109048
Short name T172
Test name
Test status
Simulation time 24694413148 ps
CPU time 43.54 seconds
Started Jun 10 05:15:21 PM PDT 24
Finished Jun 10 05:16:05 PM PDT 24
Peak memory 200220 kb
Host smart-5591f2fa-2527-444c-b30f-2873740c36e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242109048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.1242109048
Directory /workspace/110.uart_fifo_reset/latest

Test location /workspace/coverage/default/111.uart_fifo_reset.1464774054
Short name T1083
Test name
Test status
Simulation time 81305877748 ps
CPU time 114.17 seconds
Started Jun 10 05:15:20 PM PDT 24
Finished Jun 10 05:17:14 PM PDT 24
Peak memory 200280 kb
Host smart-53e04a35-d4dd-4d06-9041-107da869adbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464774054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.1464774054
Directory /workspace/111.uart_fifo_reset/latest

Test location /workspace/coverage/default/112.uart_fifo_reset.3339790856
Short name T726
Test name
Test status
Simulation time 22679343410 ps
CPU time 30.16 seconds
Started Jun 10 05:15:23 PM PDT 24
Finished Jun 10 05:15:53 PM PDT 24
Peak memory 200260 kb
Host smart-da96d15f-6011-453d-a1a8-e47cbcfd2328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339790856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.3339790856
Directory /workspace/112.uart_fifo_reset/latest

Test location /workspace/coverage/default/114.uart_fifo_reset.3402999831
Short name T203
Test name
Test status
Simulation time 31750115087 ps
CPU time 26.19 seconds
Started Jun 10 05:15:20 PM PDT 24
Finished Jun 10 05:15:47 PM PDT 24
Peak memory 200160 kb
Host smart-6c461c6c-2c86-4b30-a8fd-1c00d6029f9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402999831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.3402999831
Directory /workspace/114.uart_fifo_reset/latest

Test location /workspace/coverage/default/115.uart_fifo_reset.2389121559
Short name T191
Test name
Test status
Simulation time 88261526292 ps
CPU time 79.58 seconds
Started Jun 10 05:15:18 PM PDT 24
Finished Jun 10 05:16:38 PM PDT 24
Peak memory 200236 kb
Host smart-7f2f3d56-6bdc-4b7a-be7e-c8c5d23ec155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389121559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.2389121559
Directory /workspace/115.uart_fifo_reset/latest

Test location /workspace/coverage/default/116.uart_fifo_reset.4013110777
Short name T606
Test name
Test status
Simulation time 12391547937 ps
CPU time 24.25 seconds
Started Jun 10 05:15:23 PM PDT 24
Finished Jun 10 05:15:48 PM PDT 24
Peak memory 200268 kb
Host smart-dc5cd754-4b87-4895-b774-5b4dde38eeb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013110777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.4013110777
Directory /workspace/116.uart_fifo_reset/latest

Test location /workspace/coverage/default/118.uart_fifo_reset.319758795
Short name T1057
Test name
Test status
Simulation time 61134670100 ps
CPU time 52.93 seconds
Started Jun 10 05:15:20 PM PDT 24
Finished Jun 10 05:16:14 PM PDT 24
Peak memory 200240 kb
Host smart-f9306dd9-5db2-40e2-bbcc-aab8119d2168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319758795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.319758795
Directory /workspace/118.uart_fifo_reset/latest

Test location /workspace/coverage/default/119.uart_fifo_reset.3091603993
Short name T508
Test name
Test status
Simulation time 31885247292 ps
CPU time 50.42 seconds
Started Jun 10 05:15:20 PM PDT 24
Finished Jun 10 05:16:11 PM PDT 24
Peak memory 200296 kb
Host smart-b49eab78-9bca-4961-9fbc-37055f8364a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091603993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.3091603993
Directory /workspace/119.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_alert_test.2458285578
Short name T432
Test name
Test status
Simulation time 14194929 ps
CPU time 0.56 seconds
Started Jun 10 05:13:25 PM PDT 24
Finished Jun 10 05:13:26 PM PDT 24
Peak memory 195676 kb
Host smart-3b4e32c8-a2aa-4c68-90b9-508c03af5ebd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458285578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.2458285578
Directory /workspace/12.uart_alert_test/latest

Test location /workspace/coverage/default/12.uart_fifo_full.1105992480
Short name T1018
Test name
Test status
Simulation time 143334703128 ps
CPU time 303.3 seconds
Started Jun 10 05:13:24 PM PDT 24
Finished Jun 10 05:18:28 PM PDT 24
Peak memory 200176 kb
Host smart-233841cf-e794-42c7-a93d-20167507731b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105992480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.1105992480
Directory /workspace/12.uart_fifo_full/latest

Test location /workspace/coverage/default/12.uart_fifo_overflow.3096652532
Short name T174
Test name
Test status
Simulation time 305596469203 ps
CPU time 50.69 seconds
Started Jun 10 05:13:28 PM PDT 24
Finished Jun 10 05:14:19 PM PDT 24
Peak memory 200324 kb
Host smart-1d0f3f47-4a7b-4b42-9a27-1f7de6d80925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096652532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.3096652532
Directory /workspace/12.uart_fifo_overflow/latest

Test location /workspace/coverage/default/12.uart_fifo_reset.2141339023
Short name T21
Test name
Test status
Simulation time 26667316650 ps
CPU time 45.05 seconds
Started Jun 10 05:13:23 PM PDT 24
Finished Jun 10 05:14:09 PM PDT 24
Peak memory 200348 kb
Host smart-53a56282-f2c6-44b9-b448-3341f7424114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141339023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.2141339023
Directory /workspace/12.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_intr.577087109
Short name T812
Test name
Test status
Simulation time 39247584213 ps
CPU time 60.99 seconds
Started Jun 10 05:13:29 PM PDT 24
Finished Jun 10 05:14:30 PM PDT 24
Peak memory 199336 kb
Host smart-26cdcdbc-4db0-4aea-84e4-06cc7d123b9f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577087109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.577087109
Directory /workspace/12.uart_intr/latest

Test location /workspace/coverage/default/12.uart_long_xfer_wo_dly.2530726989
Short name T758
Test name
Test status
Simulation time 85415718046 ps
CPU time 398.17 seconds
Started Jun 10 05:13:27 PM PDT 24
Finished Jun 10 05:20:05 PM PDT 24
Peak memory 200324 kb
Host smart-059d6460-ade5-4d12-ac63-2887e8857ebd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2530726989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.2530726989
Directory /workspace/12.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/12.uart_loopback.2405724054
Short name T380
Test name
Test status
Simulation time 11337667376 ps
CPU time 12.28 seconds
Started Jun 10 05:13:28 PM PDT 24
Finished Jun 10 05:13:41 PM PDT 24
Peak memory 200196 kb
Host smart-11ae8582-e156-47a3-9d83-8628221d7ddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405724054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_loopback.2405724054
Directory /workspace/12.uart_loopback/latest

Test location /workspace/coverage/default/12.uart_perf.3707900075
Short name T421
Test name
Test status
Simulation time 11163424482 ps
CPU time 32.77 seconds
Started Jun 10 05:13:23 PM PDT 24
Finished Jun 10 05:13:56 PM PDT 24
Peak memory 200276 kb
Host smart-6242d602-09f3-477a-98a5-4d06ba1c9f57
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3707900075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.3707900075
Directory /workspace/12.uart_perf/latest

Test location /workspace/coverage/default/12.uart_rx_oversample.185173110
Short name T823
Test name
Test status
Simulation time 6057377236 ps
CPU time 8.6 seconds
Started Jun 10 05:13:21 PM PDT 24
Finished Jun 10 05:13:30 PM PDT 24
Peak memory 199548 kb
Host smart-fb217537-c351-4730-aa21-0783f867739d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=185173110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.185173110
Directory /workspace/12.uart_rx_oversample/latest

Test location /workspace/coverage/default/12.uart_rx_parity_err.3239557696
Short name T584
Test name
Test status
Simulation time 76503386181 ps
CPU time 172.64 seconds
Started Jun 10 05:13:24 PM PDT 24
Finished Jun 10 05:16:17 PM PDT 24
Peak memory 200348 kb
Host smart-21886542-8ed8-40b8-a02c-fef327dddb01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239557696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.3239557696
Directory /workspace/12.uart_rx_parity_err/latest

Test location /workspace/coverage/default/12.uart_rx_start_bit_filter.4071229999
Short name T513
Test name
Test status
Simulation time 36017533203 ps
CPU time 60.34 seconds
Started Jun 10 05:13:20 PM PDT 24
Finished Jun 10 05:14:21 PM PDT 24
Peak memory 196204 kb
Host smart-3a005afc-4112-4b4c-bd0e-04edbcb2d174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071229999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.4071229999
Directory /workspace/12.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/12.uart_smoke.2223431283
Short name T882
Test name
Test status
Simulation time 5902495982 ps
CPU time 21.77 seconds
Started Jun 10 05:13:20 PM PDT 24
Finished Jun 10 05:13:42 PM PDT 24
Peak memory 200316 kb
Host smart-979553db-ab23-44ea-ab6e-a08047b6e6a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223431283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_smoke.2223431283
Directory /workspace/12.uart_smoke/latest

Test location /workspace/coverage/default/12.uart_stress_all.759750587
Short name T1079
Test name
Test status
Simulation time 236510983795 ps
CPU time 566.54 seconds
Started Jun 10 05:13:26 PM PDT 24
Finished Jun 10 05:22:53 PM PDT 24
Peak memory 200316 kb
Host smart-7d7042e8-5a9f-4a7b-9fc7-9ce6d8b95d9e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759750587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.759750587
Directory /workspace/12.uart_stress_all/latest

Test location /workspace/coverage/default/12.uart_stress_all_with_rand_reset.89074111
Short name T58
Test name
Test status
Simulation time 78397011494 ps
CPU time 736.35 seconds
Started Jun 10 05:13:25 PM PDT 24
Finished Jun 10 05:25:42 PM PDT 24
Peak memory 216864 kb
Host smart-730d006c-7b51-4e6d-9e0f-f802d3d37287
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89074111 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 12.uart_stress_all_with_rand_reset.89074111
Directory /workspace/12.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.uart_tx_ovrd.993368274
Short name T108
Test name
Test status
Simulation time 6627751753 ps
CPU time 22.99 seconds
Started Jun 10 05:13:24 PM PDT 24
Finished Jun 10 05:13:48 PM PDT 24
Peak memory 200216 kb
Host smart-cf98a309-535a-46cb-be08-9b618bf97ada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993368274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.993368274
Directory /workspace/12.uart_tx_ovrd/latest

Test location /workspace/coverage/default/121.uart_fifo_reset.4028583546
Short name T119
Test name
Test status
Simulation time 49234947248 ps
CPU time 18.89 seconds
Started Jun 10 05:15:20 PM PDT 24
Finished Jun 10 05:15:39 PM PDT 24
Peak memory 200312 kb
Host smart-3c90dc48-9c45-493e-9274-b450a8303e39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028583546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.4028583546
Directory /workspace/121.uart_fifo_reset/latest

Test location /workspace/coverage/default/122.uart_fifo_reset.1428531572
Short name T157
Test name
Test status
Simulation time 32744003635 ps
CPU time 66.71 seconds
Started Jun 10 05:15:24 PM PDT 24
Finished Jun 10 05:16:31 PM PDT 24
Peak memory 200296 kb
Host smart-4da56a71-cb1b-4dec-8066-763f4b452416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428531572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.1428531572
Directory /workspace/122.uart_fifo_reset/latest

Test location /workspace/coverage/default/124.uart_fifo_reset.3934830201
Short name T1014
Test name
Test status
Simulation time 37696904524 ps
CPU time 19.67 seconds
Started Jun 10 05:15:28 PM PDT 24
Finished Jun 10 05:15:48 PM PDT 24
Peak memory 200320 kb
Host smart-29d0e087-6029-475a-a333-f4d456b3dec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934830201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.3934830201
Directory /workspace/124.uart_fifo_reset/latest

Test location /workspace/coverage/default/126.uart_fifo_reset.329552083
Short name T458
Test name
Test status
Simulation time 57067278063 ps
CPU time 94.91 seconds
Started Jun 10 05:15:30 PM PDT 24
Finished Jun 10 05:17:05 PM PDT 24
Peak memory 200160 kb
Host smart-38dbf860-571b-4722-ae26-15e35e562906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329552083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.329552083
Directory /workspace/126.uart_fifo_reset/latest

Test location /workspace/coverage/default/127.uart_fifo_reset.680447896
Short name T784
Test name
Test status
Simulation time 103728945571 ps
CPU time 39.73 seconds
Started Jun 10 05:15:26 PM PDT 24
Finished Jun 10 05:16:06 PM PDT 24
Peak memory 200088 kb
Host smart-c1e6dca7-0d63-4030-9e10-a18d21ae084b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680447896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.680447896
Directory /workspace/127.uart_fifo_reset/latest

Test location /workspace/coverage/default/129.uart_fifo_reset.2470140899
Short name T453
Test name
Test status
Simulation time 149936539128 ps
CPU time 498.29 seconds
Started Jun 10 05:15:25 PM PDT 24
Finished Jun 10 05:23:44 PM PDT 24
Peak memory 200356 kb
Host smart-ca1bdaba-f6db-4559-ac16-d3d20cc267fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470140899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.2470140899
Directory /workspace/129.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_alert_test.1984694266
Short name T428
Test name
Test status
Simulation time 28967973 ps
CPU time 0.59 seconds
Started Jun 10 05:13:26 PM PDT 24
Finished Jun 10 05:13:27 PM PDT 24
Peak memory 195728 kb
Host smart-b6adbc57-5fb9-4908-a131-6b1cf5e9129d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984694266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.1984694266
Directory /workspace/13.uart_alert_test/latest

Test location /workspace/coverage/default/13.uart_fifo_full.1408623426
Short name T609
Test name
Test status
Simulation time 62117375808 ps
CPU time 32.18 seconds
Started Jun 10 05:13:25 PM PDT 24
Finished Jun 10 05:13:58 PM PDT 24
Peak memory 200324 kb
Host smart-93f51abc-b5c0-4ba3-b2d5-7b4c81a0f309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408623426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.1408623426
Directory /workspace/13.uart_fifo_full/latest

Test location /workspace/coverage/default/13.uart_fifo_overflow.1462417714
Short name T720
Test name
Test status
Simulation time 17896420115 ps
CPU time 7.57 seconds
Started Jun 10 05:13:27 PM PDT 24
Finished Jun 10 05:13:35 PM PDT 24
Peak memory 200324 kb
Host smart-c17ba280-b3fb-4fdd-bba3-1ff434b7909a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462417714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.1462417714
Directory /workspace/13.uart_fifo_overflow/latest

Test location /workspace/coverage/default/13.uart_intr.566737687
Short name T545
Test name
Test status
Simulation time 105624651105 ps
CPU time 21.05 seconds
Started Jun 10 05:13:29 PM PDT 24
Finished Jun 10 05:13:50 PM PDT 24
Peak memory 200144 kb
Host smart-3c372749-dd5c-442a-a2e4-1df38fc554b5
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566737687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.566737687
Directory /workspace/13.uart_intr/latest

Test location /workspace/coverage/default/13.uart_long_xfer_wo_dly.2749775480
Short name T382
Test name
Test status
Simulation time 47871339801 ps
CPU time 41.46 seconds
Started Jun 10 05:13:25 PM PDT 24
Finished Jun 10 05:14:07 PM PDT 24
Peak memory 200372 kb
Host smart-7c7ed97f-1aee-4322-a666-2769dc9c736f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2749775480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.2749775480
Directory /workspace/13.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/13.uart_loopback.4072385154
Short name T959
Test name
Test status
Simulation time 4883023817 ps
CPU time 5.55 seconds
Started Jun 10 05:13:21 PM PDT 24
Finished Jun 10 05:13:27 PM PDT 24
Peak memory 198664 kb
Host smart-fe6d4de7-2668-4f8c-9978-744407829ea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072385154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_loopback.4072385154
Directory /workspace/13.uart_loopback/latest

Test location /workspace/coverage/default/13.uart_perf.2931861222
Short name T261
Test name
Test status
Simulation time 14534501836 ps
CPU time 471.73 seconds
Started Jun 10 05:13:24 PM PDT 24
Finished Jun 10 05:21:16 PM PDT 24
Peak memory 200364 kb
Host smart-ca7a4b86-07ca-4d2a-937d-6c7ece7f8df0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2931861222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.2931861222
Directory /workspace/13.uart_perf/latest

Test location /workspace/coverage/default/13.uart_rx_oversample.709720301
Short name T821
Test name
Test status
Simulation time 3602126759 ps
CPU time 23.77 seconds
Started Jun 10 05:13:22 PM PDT 24
Finished Jun 10 05:13:46 PM PDT 24
Peak memory 199296 kb
Host smart-a603403c-d895-4be8-8a8e-36ed9df9b3e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=709720301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.709720301
Directory /workspace/13.uart_rx_oversample/latest

Test location /workspace/coverage/default/13.uart_rx_parity_err.2808392078
Short name T956
Test name
Test status
Simulation time 17837960209 ps
CPU time 29.55 seconds
Started Jun 10 05:13:23 PM PDT 24
Finished Jun 10 05:13:53 PM PDT 24
Peak memory 200188 kb
Host smart-a860de50-b49f-4b91-92ff-2dc2c618a4af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808392078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.2808392078
Directory /workspace/13.uart_rx_parity_err/latest

Test location /workspace/coverage/default/13.uart_rx_start_bit_filter.1662790713
Short name T651
Test name
Test status
Simulation time 3683040462 ps
CPU time 6.1 seconds
Started Jun 10 05:13:24 PM PDT 24
Finished Jun 10 05:13:31 PM PDT 24
Peak memory 196932 kb
Host smart-3df37c58-9fb0-45d1-ad67-a0965235822f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662790713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.1662790713
Directory /workspace/13.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/13.uart_smoke.55028314
Short name T538
Test name
Test status
Simulation time 770045225 ps
CPU time 1.18 seconds
Started Jun 10 05:13:25 PM PDT 24
Finished Jun 10 05:13:27 PM PDT 24
Peak memory 198540 kb
Host smart-92ace470-e8c1-43cd-b6da-0117f2213c5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55028314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_smoke.55028314
Directory /workspace/13.uart_smoke/latest

Test location /workspace/coverage/default/13.uart_stress_all.4287003597
Short name T937
Test name
Test status
Simulation time 8239294685 ps
CPU time 4.56 seconds
Started Jun 10 05:13:25 PM PDT 24
Finished Jun 10 05:13:30 PM PDT 24
Peak memory 200360 kb
Host smart-f9c0449e-40ad-44bf-97de-7b1685acb863
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287003597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.4287003597
Directory /workspace/13.uart_stress_all/latest

Test location /workspace/coverage/default/13.uart_tx_ovrd.3341688819
Short name T330
Test name
Test status
Simulation time 6808873675 ps
CPU time 32.85 seconds
Started Jun 10 05:13:25 PM PDT 24
Finished Jun 10 05:13:58 PM PDT 24
Peak memory 200264 kb
Host smart-be5cc6da-e4e1-4275-b7ac-af64d2f64c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341688819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.3341688819
Directory /workspace/13.uart_tx_ovrd/latest

Test location /workspace/coverage/default/13.uart_tx_rx.2661532999
Short name T966
Test name
Test status
Simulation time 98668564850 ps
CPU time 36.67 seconds
Started Jun 10 05:13:26 PM PDT 24
Finished Jun 10 05:14:03 PM PDT 24
Peak memory 200288 kb
Host smart-fc660893-3e6f-4ccf-a9f1-f309f7587b6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661532999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.2661532999
Directory /workspace/13.uart_tx_rx/latest

Test location /workspace/coverage/default/130.uart_fifo_reset.2597863859
Short name T808
Test name
Test status
Simulation time 138029666917 ps
CPU time 75.37 seconds
Started Jun 10 05:15:29 PM PDT 24
Finished Jun 10 05:16:44 PM PDT 24
Peak memory 200320 kb
Host smart-51df1313-857d-43ae-bef7-1c8af6d920fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597863859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.2597863859
Directory /workspace/130.uart_fifo_reset/latest

Test location /workspace/coverage/default/131.uart_fifo_reset.4214469398
Short name T796
Test name
Test status
Simulation time 57985487352 ps
CPU time 26.41 seconds
Started Jun 10 05:15:27 PM PDT 24
Finished Jun 10 05:15:53 PM PDT 24
Peak memory 200352 kb
Host smart-7424787b-fc2f-419d-ad8a-0e36fa761d95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214469398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.4214469398
Directory /workspace/131.uart_fifo_reset/latest

Test location /workspace/coverage/default/132.uart_fifo_reset.1350942369
Short name T1065
Test name
Test status
Simulation time 36306751784 ps
CPU time 56.64 seconds
Started Jun 10 05:15:29 PM PDT 24
Finished Jun 10 05:16:26 PM PDT 24
Peak memory 199888 kb
Host smart-46d65235-a5af-4e2e-8f1a-ed822d4e8ee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350942369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.1350942369
Directory /workspace/132.uart_fifo_reset/latest

Test location /workspace/coverage/default/134.uart_fifo_reset.1466728547
Short name T851
Test name
Test status
Simulation time 25502106337 ps
CPU time 43.57 seconds
Started Jun 10 05:15:30 PM PDT 24
Finished Jun 10 05:16:14 PM PDT 24
Peak memory 200212 kb
Host smart-4996f0fe-ba63-4c84-a8f7-4dbdcf26620c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466728547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.1466728547
Directory /workspace/134.uart_fifo_reset/latest

Test location /workspace/coverage/default/135.uart_fifo_reset.1932016557
Short name T328
Test name
Test status
Simulation time 117456405214 ps
CPU time 102.78 seconds
Started Jun 10 05:15:29 PM PDT 24
Finished Jun 10 05:17:12 PM PDT 24
Peak memory 200312 kb
Host smart-41df6d3e-560d-4c5b-b52b-e57df1992cf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932016557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.1932016557
Directory /workspace/135.uart_fifo_reset/latest

Test location /workspace/coverage/default/136.uart_fifo_reset.2982607426
Short name T596
Test name
Test status
Simulation time 132833436676 ps
CPU time 110.76 seconds
Started Jun 10 05:15:29 PM PDT 24
Finished Jun 10 05:17:20 PM PDT 24
Peak memory 200408 kb
Host smart-2944cf71-9d17-495d-a934-213d33116870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982607426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.2982607426
Directory /workspace/136.uart_fifo_reset/latest

Test location /workspace/coverage/default/137.uart_fifo_reset.837034803
Short name T893
Test name
Test status
Simulation time 101024681079 ps
CPU time 69.91 seconds
Started Jun 10 05:15:31 PM PDT 24
Finished Jun 10 05:16:41 PM PDT 24
Peak memory 200328 kb
Host smart-02189ed8-5925-4913-b957-cf1997faae3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837034803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.837034803
Directory /workspace/137.uart_fifo_reset/latest

Test location /workspace/coverage/default/138.uart_fifo_reset.1392715074
Short name T363
Test name
Test status
Simulation time 38322731573 ps
CPU time 35.42 seconds
Started Jun 10 05:15:31 PM PDT 24
Finished Jun 10 05:16:07 PM PDT 24
Peak memory 200280 kb
Host smart-5b6ab555-6d68-421f-876a-b61c8c77160e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392715074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.1392715074
Directory /workspace/138.uart_fifo_reset/latest

Test location /workspace/coverage/default/139.uart_fifo_reset.1521083252
Short name T889
Test name
Test status
Simulation time 21144010263 ps
CPU time 32.56 seconds
Started Jun 10 05:15:29 PM PDT 24
Finished Jun 10 05:16:02 PM PDT 24
Peak memory 199780 kb
Host smart-72e31592-af97-4f75-819a-463d66305f98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521083252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.1521083252
Directory /workspace/139.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_alert_test.1453429566
Short name T593
Test name
Test status
Simulation time 29311395 ps
CPU time 0.56 seconds
Started Jun 10 05:13:30 PM PDT 24
Finished Jun 10 05:13:32 PM PDT 24
Peak memory 194620 kb
Host smart-1b602ea0-e732-450a-9a93-2b371d94ca82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453429566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.1453429566
Directory /workspace/14.uart_alert_test/latest

Test location /workspace/coverage/default/14.uart_fifo_full.1123463624
Short name T294
Test name
Test status
Simulation time 33640046635 ps
CPU time 15.14 seconds
Started Jun 10 05:13:24 PM PDT 24
Finished Jun 10 05:13:39 PM PDT 24
Peak memory 200396 kb
Host smart-468b151f-d0e3-46c2-bff6-8a6e78c997c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123463624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.1123463624
Directory /workspace/14.uart_fifo_full/latest

Test location /workspace/coverage/default/14.uart_fifo_overflow.2198148742
Short name T550
Test name
Test status
Simulation time 19028581488 ps
CPU time 25.89 seconds
Started Jun 10 05:13:22 PM PDT 24
Finished Jun 10 05:13:48 PM PDT 24
Peak memory 200180 kb
Host smart-fdb9c049-9698-4520-ba5a-ff4865698876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198148742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.2198148742
Directory /workspace/14.uart_fifo_overflow/latest

Test location /workspace/coverage/default/14.uart_fifo_reset.4149409952
Short name T376
Test name
Test status
Simulation time 181485691626 ps
CPU time 30.63 seconds
Started Jun 10 05:13:30 PM PDT 24
Finished Jun 10 05:14:01 PM PDT 24
Peak memory 200260 kb
Host smart-44a082a8-c1ae-43f3-86ba-6c224f7d950e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149409952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.4149409952
Directory /workspace/14.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_intr.460609038
Short name T469
Test name
Test status
Simulation time 20550483067 ps
CPU time 19.62 seconds
Started Jun 10 05:13:30 PM PDT 24
Finished Jun 10 05:13:50 PM PDT 24
Peak memory 197916 kb
Host smart-7d2912b1-ccdc-422e-b95f-3e8d44e171b4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460609038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.460609038
Directory /workspace/14.uart_intr/latest

Test location /workspace/coverage/default/14.uart_long_xfer_wo_dly.1337236671
Short name T986
Test name
Test status
Simulation time 70699027312 ps
CPU time 407.2 seconds
Started Jun 10 05:13:32 PM PDT 24
Finished Jun 10 05:20:20 PM PDT 24
Peak memory 200260 kb
Host smart-568fd777-41c7-4b70-a75a-7ddb49270524
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1337236671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.1337236671
Directory /workspace/14.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/14.uart_loopback.2138811327
Short name T872
Test name
Test status
Simulation time 2260992035 ps
CPU time 1.53 seconds
Started Jun 10 05:13:30 PM PDT 24
Finished Jun 10 05:13:32 PM PDT 24
Peak memory 198228 kb
Host smart-9a6ca6fd-a702-4193-a719-7cd6eddc3892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138811327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_loopback.2138811327
Directory /workspace/14.uart_loopback/latest

Test location /workspace/coverage/default/14.uart_perf.885596442
Short name T944
Test name
Test status
Simulation time 24645852880 ps
CPU time 93.59 seconds
Started Jun 10 05:13:28 PM PDT 24
Finished Jun 10 05:15:02 PM PDT 24
Peak memory 200352 kb
Host smart-0b30a341-689b-450c-8afa-6e521760866a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=885596442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.885596442
Directory /workspace/14.uart_perf/latest

Test location /workspace/coverage/default/14.uart_rx_oversample.4141198311
Short name T124
Test name
Test status
Simulation time 2859579333 ps
CPU time 22.53 seconds
Started Jun 10 05:13:28 PM PDT 24
Finished Jun 10 05:13:51 PM PDT 24
Peak memory 198488 kb
Host smart-4f87943d-a7ef-4c74-92f3-065d2919a26f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4141198311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.4141198311
Directory /workspace/14.uart_rx_oversample/latest

Test location /workspace/coverage/default/14.uart_rx_parity_err.3433984483
Short name T972
Test name
Test status
Simulation time 92842293610 ps
CPU time 71.79 seconds
Started Jun 10 05:13:31 PM PDT 24
Finished Jun 10 05:14:43 PM PDT 24
Peak memory 200364 kb
Host smart-28c2c104-a51e-420d-99e2-fca2b6aff7fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433984483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.3433984483
Directory /workspace/14.uart_rx_parity_err/latest

Test location /workspace/coverage/default/14.uart_rx_start_bit_filter.2101093036
Short name T537
Test name
Test status
Simulation time 38113518108 ps
CPU time 34.47 seconds
Started Jun 10 05:13:28 PM PDT 24
Finished Jun 10 05:14:03 PM PDT 24
Peak memory 196156 kb
Host smart-52c0819a-9dfa-418b-859c-1c65c247d068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101093036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.2101093036
Directory /workspace/14.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/14.uart_smoke.3015243932
Short name T704
Test name
Test status
Simulation time 667491476 ps
CPU time 4.33 seconds
Started Jun 10 05:13:23 PM PDT 24
Finished Jun 10 05:13:27 PM PDT 24
Peak memory 200116 kb
Host smart-27c8e761-a285-4acd-aa40-985c089d8386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015243932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_smoke.3015243932
Directory /workspace/14.uart_smoke/latest

Test location /workspace/coverage/default/14.uart_tx_ovrd.2910245239
Short name T511
Test name
Test status
Simulation time 3388444564 ps
CPU time 2.18 seconds
Started Jun 10 05:13:30 PM PDT 24
Finished Jun 10 05:13:33 PM PDT 24
Peak memory 199664 kb
Host smart-0bb8e971-4d3b-42a6-8edc-8aa10522a6d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910245239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.2910245239
Directory /workspace/14.uart_tx_ovrd/latest

Test location /workspace/coverage/default/14.uart_tx_rx.4185133599
Short name T985
Test name
Test status
Simulation time 32737514666 ps
CPU time 17.23 seconds
Started Jun 10 05:13:23 PM PDT 24
Finished Jun 10 05:13:41 PM PDT 24
Peak memory 200328 kb
Host smart-44a14450-fef0-430e-a95b-48b8300e7c59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185133599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.4185133599
Directory /workspace/14.uart_tx_rx/latest

Test location /workspace/coverage/default/140.uart_fifo_reset.1706836784
Short name T1039
Test name
Test status
Simulation time 234674147728 ps
CPU time 109.44 seconds
Started Jun 10 05:15:30 PM PDT 24
Finished Jun 10 05:17:19 PM PDT 24
Peak memory 200260 kb
Host smart-b5a6a77f-2301-49df-976c-fc9369b8bdea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706836784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.1706836784
Directory /workspace/140.uart_fifo_reset/latest

Test location /workspace/coverage/default/141.uart_fifo_reset.3052989473
Short name T688
Test name
Test status
Simulation time 72405939383 ps
CPU time 175.07 seconds
Started Jun 10 05:15:32 PM PDT 24
Finished Jun 10 05:18:27 PM PDT 24
Peak memory 200392 kb
Host smart-7106e507-3e3b-42fa-9f89-e5aa9013ef45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052989473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.3052989473
Directory /workspace/141.uart_fifo_reset/latest

Test location /workspace/coverage/default/142.uart_fifo_reset.2397738747
Short name T960
Test name
Test status
Simulation time 10382895541 ps
CPU time 16.62 seconds
Started Jun 10 05:15:32 PM PDT 24
Finished Jun 10 05:15:49 PM PDT 24
Peak memory 198688 kb
Host smart-e17f36c8-270b-4d19-b016-2e65da454057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397738747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.2397738747
Directory /workspace/142.uart_fifo_reset/latest

Test location /workspace/coverage/default/143.uart_fifo_reset.3007839567
Short name T1056
Test name
Test status
Simulation time 22190490199 ps
CPU time 26.42 seconds
Started Jun 10 05:15:29 PM PDT 24
Finished Jun 10 05:15:56 PM PDT 24
Peak memory 200304 kb
Host smart-feee6d68-765c-46c1-b3cb-fe9b0e4382de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007839567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.3007839567
Directory /workspace/143.uart_fifo_reset/latest

Test location /workspace/coverage/default/144.uart_fifo_reset.2956631658
Short name T507
Test name
Test status
Simulation time 14424053305 ps
CPU time 21.82 seconds
Started Jun 10 05:15:31 PM PDT 24
Finished Jun 10 05:15:53 PM PDT 24
Peak memory 200256 kb
Host smart-d2e04a30-9363-4fac-933c-12ac4fee4db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956631658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.2956631658
Directory /workspace/144.uart_fifo_reset/latest

Test location /workspace/coverage/default/146.uart_fifo_reset.1281132836
Short name T903
Test name
Test status
Simulation time 172119848905 ps
CPU time 76.62 seconds
Started Jun 10 05:15:32 PM PDT 24
Finished Jun 10 05:16:49 PM PDT 24
Peak memory 200348 kb
Host smart-09114a80-af29-4dae-aac3-ded92d49566c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281132836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.1281132836
Directory /workspace/146.uart_fifo_reset/latest

Test location /workspace/coverage/default/147.uart_fifo_reset.3676683698
Short name T299
Test name
Test status
Simulation time 42770973388 ps
CPU time 79.15 seconds
Started Jun 10 05:15:32 PM PDT 24
Finished Jun 10 05:16:52 PM PDT 24
Peak memory 200300 kb
Host smart-7b1bcd94-0974-43ef-9b92-e294cd84b52f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676683698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.3676683698
Directory /workspace/147.uart_fifo_reset/latest

Test location /workspace/coverage/default/148.uart_fifo_reset.840823164
Short name T273
Test name
Test status
Simulation time 61818523602 ps
CPU time 86.96 seconds
Started Jun 10 05:15:31 PM PDT 24
Finished Jun 10 05:16:58 PM PDT 24
Peak memory 200376 kb
Host smart-d93a07e6-70c0-4ea9-97d5-92f2778c7d52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840823164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.840823164
Directory /workspace/148.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_fifo_full.1337890576
Short name T152
Test name
Test status
Simulation time 35160635224 ps
CPU time 27.32 seconds
Started Jun 10 05:13:31 PM PDT 24
Finished Jun 10 05:13:59 PM PDT 24
Peak memory 200296 kb
Host smart-89030455-eadd-40f0-b266-cbfec0562653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337890576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.1337890576
Directory /workspace/15.uart_fifo_full/latest

Test location /workspace/coverage/default/15.uart_fifo_overflow.1834879311
Short name T990
Test name
Test status
Simulation time 66810119905 ps
CPU time 31.46 seconds
Started Jun 10 05:13:27 PM PDT 24
Finished Jun 10 05:13:58 PM PDT 24
Peak memory 200208 kb
Host smart-b6f18456-0bbe-451c-8262-a217aae63ac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834879311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.1834879311
Directory /workspace/15.uart_fifo_overflow/latest

Test location /workspace/coverage/default/15.uart_fifo_reset.3999875632
Short name T315
Test name
Test status
Simulation time 56226419133 ps
CPU time 102.27 seconds
Started Jun 10 05:13:32 PM PDT 24
Finished Jun 10 05:15:14 PM PDT 24
Peak memory 200440 kb
Host smart-85ffcc93-36e2-4119-b97a-2a9614f01ca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999875632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.3999875632
Directory /workspace/15.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_intr.3067212070
Short name T468
Test name
Test status
Simulation time 12373308704 ps
CPU time 7.36 seconds
Started Jun 10 05:13:30 PM PDT 24
Finished Jun 10 05:13:38 PM PDT 24
Peak memory 200168 kb
Host smart-1be4f970-2791-4286-bd4d-54dcdd0e46c3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067212070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.3067212070
Directory /workspace/15.uart_intr/latest

Test location /workspace/coverage/default/15.uart_long_xfer_wo_dly.944157900
Short name T499
Test name
Test status
Simulation time 72961642821 ps
CPU time 373.23 seconds
Started Jun 10 05:13:30 PM PDT 24
Finished Jun 10 05:19:44 PM PDT 24
Peak memory 200368 kb
Host smart-a4e74aa1-f5d8-4ec5-a3c4-a825a02b0776
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=944157900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.944157900
Directory /workspace/15.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/15.uart_loopback.404617276
Short name T520
Test name
Test status
Simulation time 7978487373 ps
CPU time 8.36 seconds
Started Jun 10 05:13:28 PM PDT 24
Finished Jun 10 05:13:41 PM PDT 24
Peak memory 200208 kb
Host smart-369a2c45-d1c3-49bd-a9da-c85b6ddc94b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404617276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_loopback.404617276
Directory /workspace/15.uart_loopback/latest

Test location /workspace/coverage/default/15.uart_perf.73898550
Short name T378
Test name
Test status
Simulation time 15395692162 ps
CPU time 457.7 seconds
Started Jun 10 05:13:32 PM PDT 24
Finished Jun 10 05:21:10 PM PDT 24
Peak memory 200392 kb
Host smart-290c4896-eef1-4e0a-9b47-3522bf21be5f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=73898550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.73898550
Directory /workspace/15.uart_perf/latest

Test location /workspace/coverage/default/15.uart_rx_oversample.151602023
Short name T585
Test name
Test status
Simulation time 4804866535 ps
CPU time 42.19 seconds
Started Jun 10 05:13:25 PM PDT 24
Finished Jun 10 05:14:08 PM PDT 24
Peak memory 199652 kb
Host smart-7de5ae16-cde0-4ebb-9b58-04aabd37b336
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=151602023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.151602023
Directory /workspace/15.uart_rx_oversample/latest

Test location /workspace/coverage/default/15.uart_rx_parity_err.493186858
Short name T746
Test name
Test status
Simulation time 206253023417 ps
CPU time 157.14 seconds
Started Jun 10 05:13:26 PM PDT 24
Finished Jun 10 05:16:03 PM PDT 24
Peak memory 200276 kb
Host smart-c25d674f-a30f-4e54-9855-72a9dbe50d6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493186858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.493186858
Directory /workspace/15.uart_rx_parity_err/latest

Test location /workspace/coverage/default/15.uart_rx_start_bit_filter.2588025609
Short name T509
Test name
Test status
Simulation time 3590748880 ps
CPU time 1.98 seconds
Started Jun 10 05:13:28 PM PDT 24
Finished Jun 10 05:13:30 PM PDT 24
Peak memory 197044 kb
Host smart-5ca2fae4-e968-41c5-abb4-e2407bd41532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588025609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.2588025609
Directory /workspace/15.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/15.uart_smoke.329008190
Short name T615
Test name
Test status
Simulation time 243525853 ps
CPU time 1.25 seconds
Started Jun 10 05:13:27 PM PDT 24
Finished Jun 10 05:13:29 PM PDT 24
Peak memory 198636 kb
Host smart-6b6e92c8-b630-42c9-a332-a390d68a9d61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329008190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_smoke.329008190
Directory /workspace/15.uart_smoke/latest

Test location /workspace/coverage/default/15.uart_stress_all.763655451
Short name T901
Test name
Test status
Simulation time 98077330509 ps
CPU time 90.92 seconds
Started Jun 10 05:13:32 PM PDT 24
Finished Jun 10 05:15:03 PM PDT 24
Peak memory 200348 kb
Host smart-9465edac-f633-4a75-a07a-a0db9aa58605
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763655451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.763655451
Directory /workspace/15.uart_stress_all/latest

Test location /workspace/coverage/default/15.uart_tx_ovrd.1142847407
Short name T398
Test name
Test status
Simulation time 119500270 ps
CPU time 1.11 seconds
Started Jun 10 05:13:31 PM PDT 24
Finished Jun 10 05:13:32 PM PDT 24
Peak memory 198676 kb
Host smart-607a1473-8819-4506-a7ae-f7c1781358ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142847407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.1142847407
Directory /workspace/15.uart_tx_ovrd/latest

Test location /workspace/coverage/default/15.uart_tx_rx.2266696423
Short name T997
Test name
Test status
Simulation time 147936391307 ps
CPU time 56.39 seconds
Started Jun 10 05:13:32 PM PDT 24
Finished Jun 10 05:14:28 PM PDT 24
Peak memory 200304 kb
Host smart-b2f68ba9-325e-4b11-9341-672606e74427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266696423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.2266696423
Directory /workspace/15.uart_tx_rx/latest

Test location /workspace/coverage/default/150.uart_fifo_reset.2992706824
Short name T240
Test name
Test status
Simulation time 110468807449 ps
CPU time 172.71 seconds
Started Jun 10 05:15:32 PM PDT 24
Finished Jun 10 05:18:25 PM PDT 24
Peak memory 200220 kb
Host smart-09cfb62a-61fd-4c58-b81c-1425a63ffeec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992706824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.2992706824
Directory /workspace/150.uart_fifo_reset/latest

Test location /workspace/coverage/default/151.uart_fifo_reset.2159069724
Short name T710
Test name
Test status
Simulation time 34807183809 ps
CPU time 56.09 seconds
Started Jun 10 05:15:37 PM PDT 24
Finished Jun 10 05:16:34 PM PDT 24
Peak memory 200316 kb
Host smart-5aa7a016-f1b8-4e5e-962c-5c5d46d943d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159069724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.2159069724
Directory /workspace/151.uart_fifo_reset/latest

Test location /workspace/coverage/default/152.uart_fifo_reset.1780614034
Short name T1087
Test name
Test status
Simulation time 23606867448 ps
CPU time 38.1 seconds
Started Jun 10 05:15:29 PM PDT 24
Finished Jun 10 05:16:07 PM PDT 24
Peak memory 200264 kb
Host smart-b49fee78-268d-4c2a-ae1a-2c2a8ed01444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780614034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.1780614034
Directory /workspace/152.uart_fifo_reset/latest

Test location /workspace/coverage/default/154.uart_fifo_reset.2358476619
Short name T320
Test name
Test status
Simulation time 150428737367 ps
CPU time 52.83 seconds
Started Jun 10 05:15:31 PM PDT 24
Finished Jun 10 05:16:24 PM PDT 24
Peak memory 200324 kb
Host smart-577f6cd9-592b-45cd-9e1c-a7783b3eed2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358476619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.2358476619
Directory /workspace/154.uart_fifo_reset/latest

Test location /workspace/coverage/default/156.uart_fifo_reset.4232565447
Short name T451
Test name
Test status
Simulation time 59607372502 ps
CPU time 13.34 seconds
Started Jun 10 05:15:33 PM PDT 24
Finished Jun 10 05:15:47 PM PDT 24
Peak memory 200296 kb
Host smart-6c9c8340-f0f7-44d8-be72-21dd51b3d5de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232565447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.4232565447
Directory /workspace/156.uart_fifo_reset/latest

Test location /workspace/coverage/default/158.uart_fifo_reset.1973412492
Short name T802
Test name
Test status
Simulation time 49533729650 ps
CPU time 74.76 seconds
Started Jun 10 05:15:32 PM PDT 24
Finished Jun 10 05:16:48 PM PDT 24
Peak memory 200180 kb
Host smart-3a377a0d-2f85-42eb-8bb0-5e5379d57b8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973412492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.1973412492
Directory /workspace/158.uart_fifo_reset/latest

Test location /workspace/coverage/default/159.uart_fifo_reset.2224109216
Short name T222
Test name
Test status
Simulation time 81501452039 ps
CPU time 66.71 seconds
Started Jun 10 05:15:34 PM PDT 24
Finished Jun 10 05:16:41 PM PDT 24
Peak memory 200280 kb
Host smart-0dbb2f6c-80ab-491f-9c65-79fdf633f14f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224109216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.2224109216
Directory /workspace/159.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_alert_test.116122722
Short name T601
Test name
Test status
Simulation time 14190104 ps
CPU time 0.59 seconds
Started Jun 10 05:13:42 PM PDT 24
Finished Jun 10 05:13:43 PM PDT 24
Peak memory 195740 kb
Host smart-37634f46-f198-42e4-bcd4-fd3e3f2f0f6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116122722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.116122722
Directory /workspace/16.uart_alert_test/latest

Test location /workspace/coverage/default/16.uart_fifo_full.4058331372
Short name T592
Test name
Test status
Simulation time 41740284538 ps
CPU time 17.63 seconds
Started Jun 10 05:13:29 PM PDT 24
Finished Jun 10 05:13:47 PM PDT 24
Peak memory 200384 kb
Host smart-12a6b496-d96a-4ff9-b923-032995ce5c0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058331372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.4058331372
Directory /workspace/16.uart_fifo_full/latest

Test location /workspace/coverage/default/16.uart_fifo_overflow.2885249568
Short name T1075
Test name
Test status
Simulation time 56564764711 ps
CPU time 60.75 seconds
Started Jun 10 05:13:30 PM PDT 24
Finished Jun 10 05:14:31 PM PDT 24
Peak memory 200308 kb
Host smart-a8028fbd-714c-4df6-a845-41b3827ec3be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885249568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.2885249568
Directory /workspace/16.uart_fifo_overflow/latest

Test location /workspace/coverage/default/16.uart_intr.2129007253
Short name T343
Test name
Test status
Simulation time 356949306493 ps
CPU time 319.6 seconds
Started Jun 10 05:13:31 PM PDT 24
Finished Jun 10 05:18:51 PM PDT 24
Peak memory 199080 kb
Host smart-295c4014-15ee-4767-b6e7-07539ae1739a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129007253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.2129007253
Directory /workspace/16.uart_intr/latest

Test location /workspace/coverage/default/16.uart_long_xfer_wo_dly.672468324
Short name T918
Test name
Test status
Simulation time 139272116061 ps
CPU time 1290.25 seconds
Started Jun 10 05:13:31 PM PDT 24
Finished Jun 10 05:35:02 PM PDT 24
Peak memory 200288 kb
Host smart-561ae7ba-b48f-4538-80e6-beaa8d203510
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=672468324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.672468324
Directory /workspace/16.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/16.uart_loopback.623618747
Short name T794
Test name
Test status
Simulation time 4821452151 ps
CPU time 2.79 seconds
Started Jun 10 05:13:31 PM PDT 24
Finished Jun 10 05:13:34 PM PDT 24
Peak memory 199216 kb
Host smart-acae2d6c-3f8b-438f-9995-e289d7539917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623618747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_loopback.623618747
Directory /workspace/16.uart_loopback/latest

Test location /workspace/coverage/default/16.uart_perf.3695219200
Short name T1006
Test name
Test status
Simulation time 12426223835 ps
CPU time 635.11 seconds
Started Jun 10 05:13:40 PM PDT 24
Finished Jun 10 05:24:15 PM PDT 24
Peak memory 200248 kb
Host smart-be0ed916-542e-4436-8db4-5a97714c54b1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3695219200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.3695219200
Directory /workspace/16.uart_perf/latest

Test location /workspace/coverage/default/16.uart_rx_oversample.2223599577
Short name T767
Test name
Test status
Simulation time 3938672784 ps
CPU time 8.08 seconds
Started Jun 10 05:13:55 PM PDT 24
Finished Jun 10 05:14:04 PM PDT 24
Peak memory 198672 kb
Host smart-2846ce30-5d6d-4130-8f93-5f21377b870e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2223599577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.2223599577
Directory /workspace/16.uart_rx_oversample/latest

Test location /workspace/coverage/default/16.uart_rx_parity_err.1854947864
Short name T145
Test name
Test status
Simulation time 223087381999 ps
CPU time 370.74 seconds
Started Jun 10 05:13:30 PM PDT 24
Finished Jun 10 05:19:41 PM PDT 24
Peak memory 200312 kb
Host smart-b60d99c8-958e-4cfa-8a28-bbfd092c696c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854947864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.1854947864
Directory /workspace/16.uart_rx_parity_err/latest

Test location /workspace/coverage/default/16.uart_rx_start_bit_filter.4230906742
Short name T673
Test name
Test status
Simulation time 35890985050 ps
CPU time 13.98 seconds
Started Jun 10 05:13:32 PM PDT 24
Finished Jun 10 05:13:47 PM PDT 24
Peak memory 196352 kb
Host smart-71cf4722-c335-4f13-a0bd-6f248bbb4658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230906742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.4230906742
Directory /workspace/16.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/16.uart_smoke.1519941578
Short name T617
Test name
Test status
Simulation time 89608396 ps
CPU time 1.01 seconds
Started Jun 10 05:13:26 PM PDT 24
Finished Jun 10 05:13:28 PM PDT 24
Peak memory 198268 kb
Host smart-982b56ec-43f8-4a5b-8ca6-f674360851eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519941578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_smoke.1519941578
Directory /workspace/16.uart_smoke/latest

Test location /workspace/coverage/default/16.uart_stress_all_with_rand_reset.4191834299
Short name T535
Test name
Test status
Simulation time 17603504444 ps
CPU time 459.85 seconds
Started Jun 10 05:13:55 PM PDT 24
Finished Jun 10 05:21:36 PM PDT 24
Peak memory 216712 kb
Host smart-2138aa41-d167-4613-ba31-e857e5cfb3f7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191834299 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 16.uart_stress_all_with_rand_reset.4191834299
Directory /workspace/16.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.uart_tx_ovrd.1011547774
Short name T1052
Test name
Test status
Simulation time 3807481752 ps
CPU time 1.7 seconds
Started Jun 10 05:13:29 PM PDT 24
Finished Jun 10 05:13:32 PM PDT 24
Peak memory 199376 kb
Host smart-282451e8-1f7f-49c3-a1a5-edef6add26af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011547774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.1011547774
Directory /workspace/16.uart_tx_ovrd/latest

Test location /workspace/coverage/default/16.uart_tx_rx.4204377695
Short name T561
Test name
Test status
Simulation time 323120035991 ps
CPU time 32.48 seconds
Started Jun 10 05:13:30 PM PDT 24
Finished Jun 10 05:14:03 PM PDT 24
Peak memory 200308 kb
Host smart-6fb528b7-724c-4d55-8c4e-fa7f21d1a472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204377695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.4204377695
Directory /workspace/16.uart_tx_rx/latest

Test location /workspace/coverage/default/160.uart_fifo_reset.2786140250
Short name T705
Test name
Test status
Simulation time 18817560071 ps
CPU time 26.45 seconds
Started Jun 10 05:15:36 PM PDT 24
Finished Jun 10 05:16:02 PM PDT 24
Peak memory 199800 kb
Host smart-16373b2d-6ea5-4815-b185-f6490b214d16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786140250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.2786140250
Directory /workspace/160.uart_fifo_reset/latest

Test location /workspace/coverage/default/161.uart_fifo_reset.2748479564
Short name T175
Test name
Test status
Simulation time 52541824068 ps
CPU time 31.07 seconds
Started Jun 10 05:15:38 PM PDT 24
Finished Jun 10 05:16:09 PM PDT 24
Peak memory 200248 kb
Host smart-8ab48c68-4d9d-4864-8eb4-d8a5ed0646ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748479564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.2748479564
Directory /workspace/161.uart_fifo_reset/latest

Test location /workspace/coverage/default/162.uart_fifo_reset.4146369640
Short name T566
Test name
Test status
Simulation time 53318534794 ps
CPU time 83.72 seconds
Started Jun 10 05:15:34 PM PDT 24
Finished Jun 10 05:16:58 PM PDT 24
Peak memory 200200 kb
Host smart-af3b70f7-206b-4b01-8d31-30a95515bd0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146369640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.4146369640
Directory /workspace/162.uart_fifo_reset/latest

Test location /workspace/coverage/default/163.uart_fifo_reset.2716168186
Short name T68
Test name
Test status
Simulation time 141878541630 ps
CPU time 53.69 seconds
Started Jun 10 05:15:41 PM PDT 24
Finished Jun 10 05:16:35 PM PDT 24
Peak memory 200296 kb
Host smart-452dce3e-e629-4d36-89c3-035e3f4cf017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716168186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.2716168186
Directory /workspace/163.uart_fifo_reset/latest

Test location /workspace/coverage/default/164.uart_fifo_reset.1217122792
Short name T206
Test name
Test status
Simulation time 117386720749 ps
CPU time 121.58 seconds
Started Jun 10 05:15:39 PM PDT 24
Finished Jun 10 05:17:40 PM PDT 24
Peak memory 200380 kb
Host smart-ea8f0890-5fa9-40f7-bc4e-68d536d3ffb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217122792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.1217122792
Directory /workspace/164.uart_fifo_reset/latest

Test location /workspace/coverage/default/165.uart_fifo_reset.933328540
Short name T36
Test name
Test status
Simulation time 107637513606 ps
CPU time 48.11 seconds
Started Jun 10 05:15:35 PM PDT 24
Finished Jun 10 05:16:23 PM PDT 24
Peak memory 200188 kb
Host smart-7184d880-19b4-4259-b9e1-049f3fd1f9ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933328540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.933328540
Directory /workspace/165.uart_fifo_reset/latest

Test location /workspace/coverage/default/166.uart_fifo_reset.244028860
Short name T43
Test name
Test status
Simulation time 228043409486 ps
CPU time 48.43 seconds
Started Jun 10 05:15:35 PM PDT 24
Finished Jun 10 05:16:24 PM PDT 24
Peak memory 200384 kb
Host smart-9a65cd8a-89d5-4b85-af0a-d7c79bf77f29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244028860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.244028860
Directory /workspace/166.uart_fifo_reset/latest

Test location /workspace/coverage/default/167.uart_fifo_reset.1301763819
Short name T268
Test name
Test status
Simulation time 117515291177 ps
CPU time 105.99 seconds
Started Jun 10 05:15:33 PM PDT 24
Finished Jun 10 05:17:20 PM PDT 24
Peak memory 200392 kb
Host smart-5b795d52-15e0-41e1-ac61-8bdc155676f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301763819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.1301763819
Directory /workspace/167.uart_fifo_reset/latest

Test location /workspace/coverage/default/169.uart_fifo_reset.4079985019
Short name T256
Test name
Test status
Simulation time 35552836586 ps
CPU time 9.97 seconds
Started Jun 10 05:15:38 PM PDT 24
Finished Jun 10 05:15:48 PM PDT 24
Peak memory 200224 kb
Host smart-6ea443d7-2640-42fc-b30d-d6d6e968042c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079985019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.4079985019
Directory /workspace/169.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_alert_test.3124784126
Short name T924
Test name
Test status
Simulation time 12588436 ps
CPU time 0.56 seconds
Started Jun 10 05:13:34 PM PDT 24
Finished Jun 10 05:13:36 PM PDT 24
Peak memory 195172 kb
Host smart-95b5fa7b-f193-40be-b835-b27681e9899b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124784126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.3124784126
Directory /workspace/17.uart_alert_test/latest

Test location /workspace/coverage/default/17.uart_fifo_full.906281698
Short name T625
Test name
Test status
Simulation time 82267821652 ps
CPU time 62.61 seconds
Started Jun 10 05:13:34 PM PDT 24
Finished Jun 10 05:14:37 PM PDT 24
Peak memory 200380 kb
Host smart-6868c79e-bdf2-4f37-a0ac-fce20e12ce3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906281698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.906281698
Directory /workspace/17.uart_fifo_full/latest

Test location /workspace/coverage/default/17.uart_fifo_overflow.1629660430
Short name T410
Test name
Test status
Simulation time 207300898376 ps
CPU time 86.63 seconds
Started Jun 10 05:13:30 PM PDT 24
Finished Jun 10 05:14:58 PM PDT 24
Peak memory 200360 kb
Host smart-c25de618-12da-4194-9180-fd95ae341f0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629660430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.1629660430
Directory /workspace/17.uart_fifo_overflow/latest

Test location /workspace/coverage/default/17.uart_fifo_reset.776789541
Short name T351
Test name
Test status
Simulation time 12149762446 ps
CPU time 21.16 seconds
Started Jun 10 05:13:40 PM PDT 24
Finished Jun 10 05:14:02 PM PDT 24
Peak memory 200312 kb
Host smart-197d348c-d290-4c37-b3bd-c47d32e7c132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776789541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.776789541
Directory /workspace/17.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_intr.662770059
Short name T854
Test name
Test status
Simulation time 14012377795 ps
CPU time 11.84 seconds
Started Jun 10 05:13:36 PM PDT 24
Finished Jun 10 05:13:49 PM PDT 24
Peak memory 196824 kb
Host smart-9801e193-1746-4db0-b3de-f4e953122b8e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662770059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.662770059
Directory /workspace/17.uart_intr/latest

Test location /workspace/coverage/default/17.uart_long_xfer_wo_dly.2615518018
Short name T323
Test name
Test status
Simulation time 74882172574 ps
CPU time 262.08 seconds
Started Jun 10 05:13:46 PM PDT 24
Finished Jun 10 05:18:09 PM PDT 24
Peak memory 200316 kb
Host smart-52835849-afb0-4eed-a1a1-e425aae94c98
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2615518018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.2615518018
Directory /workspace/17.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/17.uart_loopback.3018468647
Short name T121
Test name
Test status
Simulation time 6323321069 ps
CPU time 12.01 seconds
Started Jun 10 05:13:43 PM PDT 24
Finished Jun 10 05:13:55 PM PDT 24
Peak memory 198584 kb
Host smart-e1bfb186-5c6e-4c74-89e9-12c086f2db3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018468647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_loopback.3018468647
Directory /workspace/17.uart_loopback/latest

Test location /workspace/coverage/default/17.uart_perf.2871416287
Short name T1054
Test name
Test status
Simulation time 13161554649 ps
CPU time 512.72 seconds
Started Jun 10 05:13:32 PM PDT 24
Finished Jun 10 05:22:05 PM PDT 24
Peak memory 200252 kb
Host smart-831a0ec3-f25f-4620-bbba-9d9659d16379
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2871416287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.2871416287
Directory /workspace/17.uart_perf/latest

Test location /workspace/coverage/default/17.uart_rx_oversample.3034309462
Short name T954
Test name
Test status
Simulation time 4001681408 ps
CPU time 25.31 seconds
Started Jun 10 05:13:31 PM PDT 24
Finished Jun 10 05:13:57 PM PDT 24
Peak memory 198788 kb
Host smart-dac0b77b-1290-4210-9b58-9bca64b7c1d8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3034309462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.3034309462
Directory /workspace/17.uart_rx_oversample/latest

Test location /workspace/coverage/default/17.uart_rx_parity_err.1812844724
Short name T16
Test name
Test status
Simulation time 25016755968 ps
CPU time 44.16 seconds
Started Jun 10 05:13:36 PM PDT 24
Finished Jun 10 05:14:20 PM PDT 24
Peak memory 200384 kb
Host smart-f2c50a0d-8df1-444a-938d-55afe554277b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812844724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.1812844724
Directory /workspace/17.uart_rx_parity_err/latest

Test location /workspace/coverage/default/17.uart_rx_start_bit_filter.3703983628
Short name T868
Test name
Test status
Simulation time 4070399956 ps
CPU time 2.3 seconds
Started Jun 10 05:13:42 PM PDT 24
Finished Jun 10 05:13:45 PM PDT 24
Peak memory 196584 kb
Host smart-4bcfdb30-e1f9-4c95-9ebd-90959d5eb186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703983628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.3703983628
Directory /workspace/17.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/17.uart_smoke.1478772811
Short name T430
Test name
Test status
Simulation time 291173929 ps
CPU time 1.72 seconds
Started Jun 10 05:13:33 PM PDT 24
Finished Jun 10 05:13:35 PM PDT 24
Peak memory 199332 kb
Host smart-c00ddd06-a4ea-4bd6-863c-84d3f7ce3277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478772811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_smoke.1478772811
Directory /workspace/17.uart_smoke/latest

Test location /workspace/coverage/default/17.uart_stress_all.2958080188
Short name T480
Test name
Test status
Simulation time 64589681666 ps
CPU time 140.96 seconds
Started Jun 10 05:13:46 PM PDT 24
Finished Jun 10 05:16:08 PM PDT 24
Peak memory 200308 kb
Host smart-409a195b-dbbb-429b-b6a1-b41a69927bd6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958080188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.2958080188
Directory /workspace/17.uart_stress_all/latest

Test location /workspace/coverage/default/17.uart_tx_ovrd.931095948
Short name T829
Test name
Test status
Simulation time 9267622421 ps
CPU time 7.8 seconds
Started Jun 10 05:13:32 PM PDT 24
Finished Jun 10 05:13:40 PM PDT 24
Peak memory 200000 kb
Host smart-ae943e54-9974-4797-accf-d1eaaec04c73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931095948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.931095948
Directory /workspace/17.uart_tx_ovrd/latest

Test location /workspace/coverage/default/17.uart_tx_rx.1959134532
Short name T761
Test name
Test status
Simulation time 23845557527 ps
CPU time 37.63 seconds
Started Jun 10 05:13:39 PM PDT 24
Finished Jun 10 05:14:17 PM PDT 24
Peak memory 200320 kb
Host smart-fa2b39e6-b6b7-4f65-8e81-ba80a8db53fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959134532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.1959134532
Directory /workspace/17.uart_tx_rx/latest

Test location /workspace/coverage/default/170.uart_fifo_reset.1456802656
Short name T197
Test name
Test status
Simulation time 18898278421 ps
CPU time 48.75 seconds
Started Jun 10 05:15:37 PM PDT 24
Finished Jun 10 05:16:26 PM PDT 24
Peak memory 200380 kb
Host smart-184132f7-0b31-4958-b490-8106191bcf46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456802656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.1456802656
Directory /workspace/170.uart_fifo_reset/latest

Test location /workspace/coverage/default/171.uart_fifo_reset.3692838000
Short name T763
Test name
Test status
Simulation time 228920065512 ps
CPU time 55.05 seconds
Started Jun 10 05:15:36 PM PDT 24
Finished Jun 10 05:16:32 PM PDT 24
Peak memory 200252 kb
Host smart-f3f69661-a330-4879-931b-80fb88b7755e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692838000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.3692838000
Directory /workspace/171.uart_fifo_reset/latest

Test location /workspace/coverage/default/174.uart_fifo_reset.1953285529
Short name T518
Test name
Test status
Simulation time 71236442304 ps
CPU time 432.3 seconds
Started Jun 10 05:15:35 PM PDT 24
Finished Jun 10 05:22:47 PM PDT 24
Peak memory 200296 kb
Host smart-5d54685c-a0e3-456f-9a1c-8c2cf82e1dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953285529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.1953285529
Directory /workspace/174.uart_fifo_reset/latest

Test location /workspace/coverage/default/175.uart_fifo_reset.1269141147
Short name T1067
Test name
Test status
Simulation time 127283179090 ps
CPU time 230.13 seconds
Started Jun 10 05:15:36 PM PDT 24
Finished Jun 10 05:19:27 PM PDT 24
Peak memory 200104 kb
Host smart-6a721fb9-c4b7-4448-acba-a46c07c86c15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269141147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.1269141147
Directory /workspace/175.uart_fifo_reset/latest

Test location /workspace/coverage/default/176.uart_fifo_reset.3705279850
Short name T431
Test name
Test status
Simulation time 64785753217 ps
CPU time 61.1 seconds
Started Jun 10 05:15:37 PM PDT 24
Finished Jun 10 05:16:38 PM PDT 24
Peak memory 200308 kb
Host smart-888094d0-e7c1-4b0f-b50e-8bade23c8ce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705279850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.3705279850
Directory /workspace/176.uart_fifo_reset/latest

Test location /workspace/coverage/default/177.uart_fifo_reset.600687380
Short name T188
Test name
Test status
Simulation time 87725729568 ps
CPU time 37.19 seconds
Started Jun 10 05:15:35 PM PDT 24
Finished Jun 10 05:16:12 PM PDT 24
Peak memory 200220 kb
Host smart-fff58a7f-eb10-4cc3-89f8-74ab423f7623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600687380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.600687380
Directory /workspace/177.uart_fifo_reset/latest

Test location /workspace/coverage/default/178.uart_fifo_reset.1160317586
Short name T1020
Test name
Test status
Simulation time 215807783793 ps
CPU time 197.7 seconds
Started Jun 10 05:15:36 PM PDT 24
Finished Jun 10 05:18:54 PM PDT 24
Peak memory 200304 kb
Host smart-2f26410b-eb79-48fd-8664-a613ba7aec24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160317586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.1160317586
Directory /workspace/178.uart_fifo_reset/latest

Test location /workspace/coverage/default/179.uart_fifo_reset.1474002971
Short name T195
Test name
Test status
Simulation time 52355497864 ps
CPU time 25.72 seconds
Started Jun 10 05:15:36 PM PDT 24
Finished Jun 10 05:16:02 PM PDT 24
Peak memory 200260 kb
Host smart-eade940d-0b0a-42d7-89d1-d0fa3ceeb36a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474002971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.1474002971
Directory /workspace/179.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_alert_test.3372853169
Short name T1001
Test name
Test status
Simulation time 33082940 ps
CPU time 0.56 seconds
Started Jun 10 05:13:38 PM PDT 24
Finished Jun 10 05:13:39 PM PDT 24
Peak memory 195628 kb
Host smart-3e1a78d6-5804-49bd-aee4-a66dbfa04408
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372853169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.3372853169
Directory /workspace/18.uart_alert_test/latest

Test location /workspace/coverage/default/18.uart_fifo_full.3700321635
Short name T857
Test name
Test status
Simulation time 59274546756 ps
CPU time 101.19 seconds
Started Jun 10 05:13:30 PM PDT 24
Finished Jun 10 05:15:12 PM PDT 24
Peak memory 200328 kb
Host smart-2cbf3217-2e59-4fcc-afec-ec3f7efb7a9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700321635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.3700321635
Directory /workspace/18.uart_fifo_full/latest

Test location /workspace/coverage/default/18.uart_fifo_overflow.2942916973
Short name T943
Test name
Test status
Simulation time 76486560595 ps
CPU time 33.82 seconds
Started Jun 10 05:13:33 PM PDT 24
Finished Jun 10 05:14:08 PM PDT 24
Peak memory 200388 kb
Host smart-0081a450-af5e-4b5a-b50f-719dc55d40c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942916973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.2942916973
Directory /workspace/18.uart_fifo_overflow/latest

Test location /workspace/coverage/default/18.uart_fifo_reset.21983525
Short name T807
Test name
Test status
Simulation time 31891198188 ps
CPU time 26.08 seconds
Started Jun 10 05:13:47 PM PDT 24
Finished Jun 10 05:14:13 PM PDT 24
Peak memory 200136 kb
Host smart-58ec2a0f-fcac-45d3-8da0-7621b45d9d87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21983525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.21983525
Directory /workspace/18.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_intr.3984305246
Short name T530
Test name
Test status
Simulation time 198871688652 ps
CPU time 307.32 seconds
Started Jun 10 05:13:38 PM PDT 24
Finished Jun 10 05:18:46 PM PDT 24
Peak memory 200224 kb
Host smart-5acc5e9f-a591-4e92-ae91-9f6ff94710fc
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984305246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.3984305246
Directory /workspace/18.uart_intr/latest

Test location /workspace/coverage/default/18.uart_long_xfer_wo_dly.4094028440
Short name T1000
Test name
Test status
Simulation time 56318302896 ps
CPU time 344.31 seconds
Started Jun 10 05:13:34 PM PDT 24
Finished Jun 10 05:19:19 PM PDT 24
Peak memory 200444 kb
Host smart-22d76c06-bf48-4b09-8cb6-5b097c9dbe59
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4094028440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.4094028440
Directory /workspace/18.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/18.uart_loopback.4224737048
Short name T484
Test name
Test status
Simulation time 1294033136 ps
CPU time 2.9 seconds
Started Jun 10 05:13:47 PM PDT 24
Finished Jun 10 05:13:50 PM PDT 24
Peak memory 197708 kb
Host smart-0675caf8-5a33-40d8-9fbc-a0ee8f5366e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224737048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_loopback.4224737048
Directory /workspace/18.uart_loopback/latest

Test location /workspace/coverage/default/18.uart_rx_oversample.205108625
Short name T370
Test name
Test status
Simulation time 4284763027 ps
CPU time 8.27 seconds
Started Jun 10 05:13:46 PM PDT 24
Finished Jun 10 05:13:55 PM PDT 24
Peak memory 199000 kb
Host smart-7aff8454-8fc2-4f39-b5c5-0f7f46c230a7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=205108625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.205108625
Directory /workspace/18.uart_rx_oversample/latest

Test location /workspace/coverage/default/18.uart_rx_parity_err.2448040102
Short name T402
Test name
Test status
Simulation time 47422898226 ps
CPU time 79.54 seconds
Started Jun 10 05:13:44 PM PDT 24
Finished Jun 10 05:15:04 PM PDT 24
Peak memory 200304 kb
Host smart-81c90e19-3cf6-41cc-a901-27979680e45c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448040102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.2448040102
Directory /workspace/18.uart_rx_parity_err/latest

Test location /workspace/coverage/default/18.uart_rx_start_bit_filter.2664476900
Short name T922
Test name
Test status
Simulation time 1830976536 ps
CPU time 2.25 seconds
Started Jun 10 05:13:34 PM PDT 24
Finished Jun 10 05:13:37 PM PDT 24
Peak memory 196096 kb
Host smart-81c1bd9a-e4b6-49cf-a4b0-8a9eb2fcfd15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664476900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.2664476900
Directory /workspace/18.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/18.uart_smoke.3969721189
Short name T48
Test name
Test status
Simulation time 5903408108 ps
CPU time 13.93 seconds
Started Jun 10 05:13:35 PM PDT 24
Finished Jun 10 05:13:50 PM PDT 24
Peak memory 199512 kb
Host smart-208504dd-6fc0-4e79-a061-d7e87f73c31d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969721189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_smoke.3969721189
Directory /workspace/18.uart_smoke/latest

Test location /workspace/coverage/default/18.uart_stress_all.756234573
Short name T280
Test name
Test status
Simulation time 353440985729 ps
CPU time 639.38 seconds
Started Jun 10 05:13:33 PM PDT 24
Finished Jun 10 05:24:13 PM PDT 24
Peak memory 200352 kb
Host smart-f81aa1f9-a087-4e9d-8623-f939d4d24c57
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756234573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.756234573
Directory /workspace/18.uart_stress_all/latest

Test location /workspace/coverage/default/18.uart_tx_ovrd.4251799979
Short name T527
Test name
Test status
Simulation time 1167478101 ps
CPU time 4.98 seconds
Started Jun 10 05:13:48 PM PDT 24
Finished Jun 10 05:13:54 PM PDT 24
Peak memory 198544 kb
Host smart-ef4abb32-0f78-417a-9c84-f457cd5d78f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251799979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.4251799979
Directory /workspace/18.uart_tx_ovrd/latest

Test location /workspace/coverage/default/18.uart_tx_rx.3148314727
Short name T1024
Test name
Test status
Simulation time 33520775167 ps
CPU time 51.83 seconds
Started Jun 10 05:13:38 PM PDT 24
Finished Jun 10 05:14:31 PM PDT 24
Peak memory 200320 kb
Host smart-a7a12b33-6617-4205-8f31-e12756db6409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148314727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.3148314727
Directory /workspace/18.uart_tx_rx/latest

Test location /workspace/coverage/default/180.uart_fifo_reset.2924819698
Short name T1029
Test name
Test status
Simulation time 30741292195 ps
CPU time 46.14 seconds
Started Jun 10 05:15:37 PM PDT 24
Finished Jun 10 05:16:24 PM PDT 24
Peak memory 200384 kb
Host smart-180f568e-a546-40e3-818f-8942a443e2f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924819698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.2924819698
Directory /workspace/180.uart_fifo_reset/latest

Test location /workspace/coverage/default/181.uart_fifo_reset.3780422722
Short name T564
Test name
Test status
Simulation time 46497935194 ps
CPU time 22.14 seconds
Started Jun 10 05:15:36 PM PDT 24
Finished Jun 10 05:15:59 PM PDT 24
Peak memory 200312 kb
Host smart-809e49dc-db12-4d72-b08d-8a015705a172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780422722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.3780422722
Directory /workspace/181.uart_fifo_reset/latest

Test location /workspace/coverage/default/184.uart_fifo_reset.624042136
Short name T654
Test name
Test status
Simulation time 59301984792 ps
CPU time 6.8 seconds
Started Jun 10 05:15:44 PM PDT 24
Finished Jun 10 05:15:51 PM PDT 24
Peak memory 200220 kb
Host smart-af030409-6f16-41bd-a5a7-afc4d82ffe1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624042136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.624042136
Directory /workspace/184.uart_fifo_reset/latest

Test location /workspace/coverage/default/187.uart_fifo_reset.3991657158
Short name T1026
Test name
Test status
Simulation time 80043831271 ps
CPU time 37.95 seconds
Started Jun 10 05:15:41 PM PDT 24
Finished Jun 10 05:16:19 PM PDT 24
Peak memory 200240 kb
Host smart-ff46e87e-a95c-4c9e-9806-4f94e4863e5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991657158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.3991657158
Directory /workspace/187.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_alert_test.3312708716
Short name T393
Test name
Test status
Simulation time 76314413 ps
CPU time 0.55 seconds
Started Jun 10 05:13:39 PM PDT 24
Finished Jun 10 05:13:40 PM PDT 24
Peak memory 195624 kb
Host smart-f1e58ac1-ccc5-4fe2-8fb2-d3391e2338e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312708716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.3312708716
Directory /workspace/19.uart_alert_test/latest

Test location /workspace/coverage/default/19.uart_fifo_full.771259020
Short name T843
Test name
Test status
Simulation time 33797257284 ps
CPU time 28.4 seconds
Started Jun 10 05:13:34 PM PDT 24
Finished Jun 10 05:14:03 PM PDT 24
Peak memory 200296 kb
Host smart-2c89c6e8-5c62-4865-ab12-8affbbc0462d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771259020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.771259020
Directory /workspace/19.uart_fifo_full/latest

Test location /workspace/coverage/default/19.uart_fifo_overflow.954597190
Short name T179
Test name
Test status
Simulation time 29169600531 ps
CPU time 10.13 seconds
Started Jun 10 05:13:36 PM PDT 24
Finished Jun 10 05:13:46 PM PDT 24
Peak memory 199872 kb
Host smart-20ade432-e3f9-482c-9e55-7b15bba637da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954597190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.954597190
Directory /workspace/19.uart_fifo_overflow/latest

Test location /workspace/coverage/default/19.uart_fifo_reset.3775593240
Short name T539
Test name
Test status
Simulation time 36149803357 ps
CPU time 30.24 seconds
Started Jun 10 05:13:36 PM PDT 24
Finished Jun 10 05:14:07 PM PDT 24
Peak memory 200272 kb
Host smart-1bbf48e3-fac6-4681-9a07-085fbf766a89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775593240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.3775593240
Directory /workspace/19.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_intr.3316257239
Short name T284
Test name
Test status
Simulation time 46809645232 ps
CPU time 5.07 seconds
Started Jun 10 05:13:36 PM PDT 24
Finished Jun 10 05:13:42 PM PDT 24
Peak memory 199724 kb
Host smart-f713606f-0c0c-445e-8072-cd029ff5d01d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316257239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.3316257239
Directory /workspace/19.uart_intr/latest

Test location /workspace/coverage/default/19.uart_long_xfer_wo_dly.852868345
Short name T1088
Test name
Test status
Simulation time 147239570499 ps
CPU time 181.35 seconds
Started Jun 10 05:13:37 PM PDT 24
Finished Jun 10 05:16:39 PM PDT 24
Peak memory 199976 kb
Host smart-6f2ad688-d60a-40f2-8e88-ade16568cf48
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=852868345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.852868345
Directory /workspace/19.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/19.uart_loopback.1640332732
Short name T444
Test name
Test status
Simulation time 5641319915 ps
CPU time 9.08 seconds
Started Jun 10 05:13:36 PM PDT 24
Finished Jun 10 05:13:45 PM PDT 24
Peak memory 199320 kb
Host smart-bc3ef5d7-554f-4eba-b6d3-a77ee237ad34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640332732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_loopback.1640332732
Directory /workspace/19.uart_loopback/latest

Test location /workspace/coverage/default/19.uart_perf.1501272098
Short name T633
Test name
Test status
Simulation time 15994515836 ps
CPU time 229.43 seconds
Started Jun 10 05:13:37 PM PDT 24
Finished Jun 10 05:17:27 PM PDT 24
Peak memory 200232 kb
Host smart-9afb2d74-2463-42c0-bd51-e510def0d2dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1501272098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.1501272098
Directory /workspace/19.uart_perf/latest

Test location /workspace/coverage/default/19.uart_rx_oversample.2340852565
Short name T498
Test name
Test status
Simulation time 3131579519 ps
CPU time 27.94 seconds
Started Jun 10 05:13:40 PM PDT 24
Finished Jun 10 05:14:08 PM PDT 24
Peak memory 199348 kb
Host smart-b55b62e3-20e4-45ac-bedd-c054751ecb65
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2340852565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.2340852565
Directory /workspace/19.uart_rx_oversample/latest

Test location /workspace/coverage/default/19.uart_rx_parity_err.305846965
Short name T629
Test name
Test status
Simulation time 143242093285 ps
CPU time 36.84 seconds
Started Jun 10 05:13:36 PM PDT 24
Finished Jun 10 05:14:14 PM PDT 24
Peak memory 200372 kb
Host smart-8d8f1798-32b5-4a7b-804c-8879763e4b7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305846965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.305846965
Directory /workspace/19.uart_rx_parity_err/latest

Test location /workspace/coverage/default/19.uart_rx_start_bit_filter.1388938445
Short name T1059
Test name
Test status
Simulation time 3934128553 ps
CPU time 2.33 seconds
Started Jun 10 05:13:37 PM PDT 24
Finished Jun 10 05:13:40 PM PDT 24
Peak memory 196616 kb
Host smart-882f5e87-7457-483f-a5d8-6a6bf76eb40b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388938445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.1388938445
Directory /workspace/19.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/19.uart_smoke.1914908231
Short name T846
Test name
Test status
Simulation time 579112434 ps
CPU time 1.97 seconds
Started Jun 10 05:13:34 PM PDT 24
Finished Jun 10 05:13:36 PM PDT 24
Peak memory 199180 kb
Host smart-196003da-9cfd-4bc8-86c0-56534dd0d67a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914908231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_smoke.1914908231
Directory /workspace/19.uart_smoke/latest

Test location /workspace/coverage/default/19.uart_stress_all.3067268607
Short name T90
Test name
Test status
Simulation time 100298396093 ps
CPU time 22.06 seconds
Started Jun 10 05:13:38 PM PDT 24
Finished Jun 10 05:14:01 PM PDT 24
Peak memory 200344 kb
Host smart-db037473-a502-4b90-b197-ec8a2d43b08b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067268607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.3067268607
Directory /workspace/19.uart_stress_all/latest

Test location /workspace/coverage/default/19.uart_stress_all_with_rand_reset.2643161142
Short name T134
Test name
Test status
Simulation time 90382949256 ps
CPU time 914.65 seconds
Started Jun 10 05:13:37 PM PDT 24
Finished Jun 10 05:28:52 PM PDT 24
Peak memory 225136 kb
Host smart-585ac491-9afe-418e-851c-6f0f43b15f40
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643161142 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 19.uart_stress_all_with_rand_reset.2643161142
Directory /workspace/19.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.uart_tx_ovrd.2537843516
Short name T1037
Test name
Test status
Simulation time 6418038451 ps
CPU time 18.59 seconds
Started Jun 10 05:13:40 PM PDT 24
Finished Jun 10 05:13:59 PM PDT 24
Peak memory 200288 kb
Host smart-bdfe4968-97c5-4e7a-960a-43ae1fbfa9fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537843516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.2537843516
Directory /workspace/19.uart_tx_ovrd/latest

Test location /workspace/coverage/default/19.uart_tx_rx.3354271068
Short name T278
Test name
Test status
Simulation time 49381518709 ps
CPU time 83.46 seconds
Started Jun 10 05:13:40 PM PDT 24
Finished Jun 10 05:15:04 PM PDT 24
Peak memory 200328 kb
Host smart-fd595ed6-9e10-4656-b74e-ad7a60ca77e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354271068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.3354271068
Directory /workspace/19.uart_tx_rx/latest

Test location /workspace/coverage/default/191.uart_fifo_reset.1747951860
Short name T205
Test name
Test status
Simulation time 31034830760 ps
CPU time 51.11 seconds
Started Jun 10 05:15:41 PM PDT 24
Finished Jun 10 05:16:33 PM PDT 24
Peak memory 199660 kb
Host smart-dfb6d54c-da8e-4643-910c-1153f7e1d20f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747951860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.1747951860
Directory /workspace/191.uart_fifo_reset/latest

Test location /workspace/coverage/default/192.uart_fifo_reset.3297288611
Short name T880
Test name
Test status
Simulation time 166886460718 ps
CPU time 31.55 seconds
Started Jun 10 05:15:41 PM PDT 24
Finished Jun 10 05:16:13 PM PDT 24
Peak memory 200356 kb
Host smart-6316ac76-ece4-41d9-a479-e546acbbfd82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297288611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.3297288611
Directory /workspace/192.uart_fifo_reset/latest

Test location /workspace/coverage/default/193.uart_fifo_reset.871168460
Short name T603
Test name
Test status
Simulation time 25484987410 ps
CPU time 38.33 seconds
Started Jun 10 05:15:41 PM PDT 24
Finished Jun 10 05:16:20 PM PDT 24
Peak memory 200228 kb
Host smart-f6b8fa08-5639-43ea-9a60-b2ebbafd674d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871168460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.871168460
Directory /workspace/193.uart_fifo_reset/latest

Test location /workspace/coverage/default/194.uart_fifo_reset.2993780152
Short name T219
Test name
Test status
Simulation time 50807780220 ps
CPU time 20.84 seconds
Started Jun 10 05:15:44 PM PDT 24
Finished Jun 10 05:16:05 PM PDT 24
Peak memory 200076 kb
Host smart-5f8d17d0-234f-4d7f-8493-b9e024f7e17b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993780152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.2993780152
Directory /workspace/194.uart_fifo_reset/latest

Test location /workspace/coverage/default/195.uart_fifo_reset.1927367040
Short name T1049
Test name
Test status
Simulation time 116095989190 ps
CPU time 145.12 seconds
Started Jun 10 05:15:39 PM PDT 24
Finished Jun 10 05:18:04 PM PDT 24
Peak memory 200512 kb
Host smart-68465abd-6133-4aa1-aac7-1ccc706f9e8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927367040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.1927367040
Directory /workspace/195.uart_fifo_reset/latest

Test location /workspace/coverage/default/196.uart_fifo_reset.3449247873
Short name T692
Test name
Test status
Simulation time 103748474179 ps
CPU time 83.19 seconds
Started Jun 10 05:15:40 PM PDT 24
Finished Jun 10 05:17:03 PM PDT 24
Peak memory 200316 kb
Host smart-618ec68a-4c79-4742-aa4c-1593fcdeb199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449247873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.3449247873
Directory /workspace/196.uart_fifo_reset/latest

Test location /workspace/coverage/default/198.uart_fifo_reset.3891725029
Short name T1028
Test name
Test status
Simulation time 42091537997 ps
CPU time 63.81 seconds
Started Jun 10 05:15:45 PM PDT 24
Finished Jun 10 05:16:49 PM PDT 24
Peak memory 200284 kb
Host smart-f25276b5-43b3-42d4-8695-f0105ece2c86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891725029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.3891725029
Directory /workspace/198.uart_fifo_reset/latest

Test location /workspace/coverage/default/199.uart_fifo_reset.4114699658
Short name T89
Test name
Test status
Simulation time 143333616370 ps
CPU time 42.38 seconds
Started Jun 10 05:15:39 PM PDT 24
Finished Jun 10 05:16:21 PM PDT 24
Peak memory 200260 kb
Host smart-9c92b89d-4515-4780-b191-47839bea5a6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114699658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.4114699658
Directory /workspace/199.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_alert_test.2444543359
Short name T381
Test name
Test status
Simulation time 58720492 ps
CPU time 0.56 seconds
Started Jun 10 05:12:46 PM PDT 24
Finished Jun 10 05:12:47 PM PDT 24
Peak memory 195956 kb
Host smart-44baa190-6114-4cc8-a7a9-5cf32333e347
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444543359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.2444543359
Directory /workspace/2.uart_alert_test/latest

Test location /workspace/coverage/default/2.uart_fifo_full.3103554239
Short name T970
Test name
Test status
Simulation time 141929086983 ps
CPU time 52.22 seconds
Started Jun 10 05:12:44 PM PDT 24
Finished Jun 10 05:13:37 PM PDT 24
Peak memory 200432 kb
Host smart-9d2a8c25-4356-4ee2-a458-63bb441859f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103554239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.3103554239
Directory /workspace/2.uart_fifo_full/latest

Test location /workspace/coverage/default/2.uart_fifo_overflow.1388983865
Short name T628
Test name
Test status
Simulation time 115540856839 ps
CPU time 42.65 seconds
Started Jun 10 05:12:48 PM PDT 24
Finished Jun 10 05:13:31 PM PDT 24
Peak memory 200284 kb
Host smart-bdd169a0-5838-41b1-9f8f-9b1cbb902bcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388983865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.1388983865
Directory /workspace/2.uart_fifo_overflow/latest

Test location /workspace/coverage/default/2.uart_fifo_reset.3733512821
Short name T303
Test name
Test status
Simulation time 130010063464 ps
CPU time 258.75 seconds
Started Jun 10 05:12:49 PM PDT 24
Finished Jun 10 05:17:08 PM PDT 24
Peak memory 200372 kb
Host smart-64e3ec9a-6035-4605-bd13-ede82800562a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733512821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.3733512821
Directory /workspace/2.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_intr.3452787052
Short name T554
Test name
Test status
Simulation time 37503983422 ps
CPU time 5.44 seconds
Started Jun 10 05:12:48 PM PDT 24
Finished Jun 10 05:12:54 PM PDT 24
Peak memory 200064 kb
Host smart-0ce83182-a096-4f59-b186-88a3173a8cf5
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452787052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.3452787052
Directory /workspace/2.uart_intr/latest

Test location /workspace/coverage/default/2.uart_long_xfer_wo_dly.516919159
Short name T666
Test name
Test status
Simulation time 103198232092 ps
CPU time 217.08 seconds
Started Jun 10 05:12:46 PM PDT 24
Finished Jun 10 05:16:23 PM PDT 24
Peak memory 200292 kb
Host smart-6bef764c-23f2-490e-87d6-8c0829dc3944
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=516919159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.516919159
Directory /workspace/2.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/2.uart_loopback.1268568494
Short name T929
Test name
Test status
Simulation time 2413550444 ps
CPU time 2.99 seconds
Started Jun 10 05:12:52 PM PDT 24
Finished Jun 10 05:12:55 PM PDT 24
Peak memory 196676 kb
Host smart-45e69229-959c-4f99-a5bf-78ce5b9191c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268568494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_loopback.1268568494
Directory /workspace/2.uart_loopback/latest

Test location /workspace/coverage/default/2.uart_perf.205571568
Short name T942
Test name
Test status
Simulation time 12438654975 ps
CPU time 297.67 seconds
Started Jun 10 05:12:47 PM PDT 24
Finished Jun 10 05:17:45 PM PDT 24
Peak memory 200492 kb
Host smart-69297d6a-9d24-4906-9d3d-3a89813ba39b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=205571568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.205571568
Directory /workspace/2.uart_perf/latest

Test location /workspace/coverage/default/2.uart_rx_oversample.1805623487
Short name T476
Test name
Test status
Simulation time 6345667318 ps
CPU time 15.84 seconds
Started Jun 10 05:12:49 PM PDT 24
Finished Jun 10 05:13:05 PM PDT 24
Peak memory 199440 kb
Host smart-be4528ff-0b15-4b61-9973-28cec1ecca0c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1805623487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.1805623487
Directory /workspace/2.uart_rx_oversample/latest

Test location /workspace/coverage/default/2.uart_rx_parity_err.1939553669
Short name T531
Test name
Test status
Simulation time 194658603794 ps
CPU time 48.84 seconds
Started Jun 10 05:12:49 PM PDT 24
Finished Jun 10 05:13:38 PM PDT 24
Peak memory 199960 kb
Host smart-a622b7a3-7703-42c3-bf0e-50f3edfe4abe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939553669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.1939553669
Directory /workspace/2.uart_rx_parity_err/latest

Test location /workspace/coverage/default/2.uart_rx_start_bit_filter.1966168845
Short name T107
Test name
Test status
Simulation time 4023978599 ps
CPU time 3.68 seconds
Started Jun 10 05:12:42 PM PDT 24
Finished Jun 10 05:12:46 PM PDT 24
Peak memory 197116 kb
Host smart-cd6941c5-6baa-433d-87df-919bbe3cc394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966168845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.1966168845
Directory /workspace/2.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/2.uart_sec_cm.1685832573
Short name T103
Test name
Test status
Simulation time 160343838 ps
CPU time 0.89 seconds
Started Jun 10 05:12:53 PM PDT 24
Finished Jun 10 05:12:54 PM PDT 24
Peak memory 218764 kb
Host smart-7b1b79a5-c865-42db-a886-1728bcef40c4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685832573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.1685832573
Directory /workspace/2.uart_sec_cm/latest

Test location /workspace/coverage/default/2.uart_smoke.1678254001
Short name T693
Test name
Test status
Simulation time 5735024952 ps
CPU time 7.96 seconds
Started Jun 10 05:12:41 PM PDT 24
Finished Jun 10 05:12:49 PM PDT 24
Peak memory 199500 kb
Host smart-64bee484-dcf0-43f5-82c0-746f90e2f47a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678254001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_smoke.1678254001
Directory /workspace/2.uart_smoke/latest

Test location /workspace/coverage/default/2.uart_tx_ovrd.3363362914
Short name T774
Test name
Test status
Simulation time 556489812 ps
CPU time 1.8 seconds
Started Jun 10 05:12:46 PM PDT 24
Finished Jun 10 05:12:48 PM PDT 24
Peak memory 199208 kb
Host smart-e4f08d71-1c40-4c9a-a4e2-5312983c874c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363362914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.3363362914
Directory /workspace/2.uart_tx_ovrd/latest

Test location /workspace/coverage/default/2.uart_tx_rx.3895173134
Short name T881
Test name
Test status
Simulation time 16357968576 ps
CPU time 29.14 seconds
Started Jun 10 05:12:45 PM PDT 24
Finished Jun 10 05:13:15 PM PDT 24
Peak memory 200304 kb
Host smart-2b89143a-8337-4480-b1a8-91739dc68450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895173134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.3895173134
Directory /workspace/2.uart_tx_rx/latest

Test location /workspace/coverage/default/20.uart_alert_test.2635114672
Short name T797
Test name
Test status
Simulation time 15106664 ps
CPU time 0.55 seconds
Started Jun 10 05:13:36 PM PDT 24
Finished Jun 10 05:13:37 PM PDT 24
Peak memory 196008 kb
Host smart-a35e9a7c-9728-49f4-9862-943829963b07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635114672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.2635114672
Directory /workspace/20.uart_alert_test/latest

Test location /workspace/coverage/default/20.uart_fifo_full.2045526557
Short name T541
Test name
Test status
Simulation time 21693852542 ps
CPU time 21.36 seconds
Started Jun 10 05:13:36 PM PDT 24
Finished Jun 10 05:13:58 PM PDT 24
Peak memory 200304 kb
Host smart-63963b87-e6ee-4b70-a1f4-b42659f60773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045526557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.2045526557
Directory /workspace/20.uart_fifo_full/latest

Test location /workspace/coverage/default/20.uart_fifo_reset.2943648101
Short name T931
Test name
Test status
Simulation time 215072733112 ps
CPU time 98.38 seconds
Started Jun 10 05:14:05 PM PDT 24
Finished Jun 10 05:15:43 PM PDT 24
Peak memory 200180 kb
Host smart-26992358-1b50-462d-abf3-f57ad1bc285a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943648101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.2943648101
Directory /workspace/20.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_intr.458490081
Short name T993
Test name
Test status
Simulation time 52384825812 ps
CPU time 23.5 seconds
Started Jun 10 05:13:39 PM PDT 24
Finished Jun 10 05:14:03 PM PDT 24
Peak memory 200392 kb
Host smart-dea4a08b-01fe-42c0-bf07-4d7cea96d7e9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458490081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.458490081
Directory /workspace/20.uart_intr/latest

Test location /workspace/coverage/default/20.uart_long_xfer_wo_dly.3493244050
Short name T122
Test name
Test status
Simulation time 106060920032 ps
CPU time 546.14 seconds
Started Jun 10 05:13:37 PM PDT 24
Finished Jun 10 05:22:44 PM PDT 24
Peak memory 199984 kb
Host smart-7031af32-3724-481c-9307-a1fba7a27948
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3493244050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.3493244050
Directory /workspace/20.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/20.uart_loopback.116452835
Short name T734
Test name
Test status
Simulation time 3750073977 ps
CPU time 3.67 seconds
Started Jun 10 05:13:36 PM PDT 24
Finished Jun 10 05:13:40 PM PDT 24
Peak memory 197788 kb
Host smart-6235e3ba-921a-4295-81be-3cb076cf3f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116452835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_loopback.116452835
Directory /workspace/20.uart_loopback/latest

Test location /workspace/coverage/default/20.uart_perf.2741175223
Short name T264
Test name
Test status
Simulation time 19254576939 ps
CPU time 918.04 seconds
Started Jun 10 05:13:38 PM PDT 24
Finished Jun 10 05:28:57 PM PDT 24
Peak memory 200460 kb
Host smart-99055025-deed-4203-b7e7-a335c3014fa7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2741175223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.2741175223
Directory /workspace/20.uart_perf/latest

Test location /workspace/coverage/default/20.uart_rx_oversample.2485125526
Short name T1015
Test name
Test status
Simulation time 3788951711 ps
CPU time 19.6 seconds
Started Jun 10 05:13:52 PM PDT 24
Finished Jun 10 05:14:12 PM PDT 24
Peak memory 199156 kb
Host smart-c83345c3-7383-4362-a059-6d37eaf1c275
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2485125526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.2485125526
Directory /workspace/20.uart_rx_oversample/latest

Test location /workspace/coverage/default/20.uart_rx_parity_err.700064295
Short name T953
Test name
Test status
Simulation time 175033754373 ps
CPU time 59.87 seconds
Started Jun 10 05:13:38 PM PDT 24
Finished Jun 10 05:14:38 PM PDT 24
Peak memory 200092 kb
Host smart-ed99d0cb-526d-446e-90ea-5f66679f321e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700064295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.700064295
Directory /workspace/20.uart_rx_parity_err/latest

Test location /workspace/coverage/default/20.uart_rx_start_bit_filter.899075451
Short name T1035
Test name
Test status
Simulation time 41626747972 ps
CPU time 68.5 seconds
Started Jun 10 05:13:37 PM PDT 24
Finished Jun 10 05:14:46 PM PDT 24
Peak memory 196404 kb
Host smart-b2ebd9e8-634d-4a59-b228-762720e3a15c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899075451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.899075451
Directory /workspace/20.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/20.uart_smoke.2802648002
Short name T465
Test name
Test status
Simulation time 455399390 ps
CPU time 2.83 seconds
Started Jun 10 05:13:39 PM PDT 24
Finished Jun 10 05:13:42 PM PDT 24
Peak memory 199200 kb
Host smart-4cb88e53-343d-4c6a-9e0b-41be05c28600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802648002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_smoke.2802648002
Directory /workspace/20.uart_smoke/latest

Test location /workspace/coverage/default/20.uart_stress_all.516896326
Short name T793
Test name
Test status
Simulation time 19916018567 ps
CPU time 12.53 seconds
Started Jun 10 05:13:35 PM PDT 24
Finished Jun 10 05:13:48 PM PDT 24
Peak memory 200356 kb
Host smart-6da4e76b-3733-43ec-a987-5b10311d731b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516896326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.516896326
Directory /workspace/20.uart_stress_all/latest

Test location /workspace/coverage/default/20.uart_tx_ovrd.1903999489
Short name T340
Test name
Test status
Simulation time 1966011926 ps
CPU time 2.57 seconds
Started Jun 10 05:14:01 PM PDT 24
Finished Jun 10 05:14:04 PM PDT 24
Peak memory 198576 kb
Host smart-84971552-d7cf-4c08-acc9-98ae14d60f5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903999489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.1903999489
Directory /workspace/20.uart_tx_ovrd/latest

Test location /workspace/coverage/default/20.uart_tx_rx.3744542284
Short name T1089
Test name
Test status
Simulation time 26699233777 ps
CPU time 12.35 seconds
Started Jun 10 05:13:37 PM PDT 24
Finished Jun 10 05:13:50 PM PDT 24
Peak memory 200048 kb
Host smart-4aacd3dc-fd83-451a-b9cc-7af77f71c4ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744542284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.3744542284
Directory /workspace/20.uart_tx_rx/latest

Test location /workspace/coverage/default/200.uart_fifo_reset.916073153
Short name T200
Test name
Test status
Simulation time 141203410453 ps
CPU time 407.22 seconds
Started Jun 10 05:15:39 PM PDT 24
Finished Jun 10 05:22:27 PM PDT 24
Peak memory 200252 kb
Host smart-5004ceb9-534e-4ac8-8703-2b5ab9da57e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916073153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.916073153
Directory /workspace/200.uart_fifo_reset/latest

Test location /workspace/coverage/default/201.uart_fifo_reset.3211173782
Short name T701
Test name
Test status
Simulation time 13515555440 ps
CPU time 22.06 seconds
Started Jun 10 05:15:41 PM PDT 24
Finished Jun 10 05:16:03 PM PDT 24
Peak memory 200240 kb
Host smart-263995d8-7b92-471e-95e5-7b58318fe1a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211173782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.3211173782
Directory /workspace/201.uart_fifo_reset/latest

Test location /workspace/coverage/default/203.uart_fifo_reset.1645585093
Short name T783
Test name
Test status
Simulation time 10534535564 ps
CPU time 19.78 seconds
Started Jun 10 05:15:40 PM PDT 24
Finished Jun 10 05:16:00 PM PDT 24
Peak memory 200320 kb
Host smart-f44fb960-5119-43db-9c36-2e9c219ce09b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645585093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.1645585093
Directory /workspace/203.uart_fifo_reset/latest

Test location /workspace/coverage/default/204.uart_fifo_reset.3298334747
Short name T927
Test name
Test status
Simulation time 27537747878 ps
CPU time 20.39 seconds
Started Jun 10 05:15:45 PM PDT 24
Finished Jun 10 05:16:05 PM PDT 24
Peak memory 200348 kb
Host smart-96546344-676b-4944-8375-5281fe08ab7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298334747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.3298334747
Directory /workspace/204.uart_fifo_reset/latest

Test location /workspace/coverage/default/205.uart_fifo_reset.1281587111
Short name T202
Test name
Test status
Simulation time 13786166474 ps
CPU time 25.03 seconds
Started Jun 10 05:15:46 PM PDT 24
Finished Jun 10 05:16:11 PM PDT 24
Peak memory 200248 kb
Host smart-46a11607-2f31-447d-9361-03cff11911a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281587111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.1281587111
Directory /workspace/205.uart_fifo_reset/latest

Test location /workspace/coverage/default/206.uart_fifo_reset.3358907892
Short name T605
Test name
Test status
Simulation time 29428620532 ps
CPU time 65.23 seconds
Started Jun 10 05:15:42 PM PDT 24
Finished Jun 10 05:16:47 PM PDT 24
Peak memory 200360 kb
Host smart-3d5f2657-b29e-4c07-8736-7467b438deca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358907892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.3358907892
Directory /workspace/206.uart_fifo_reset/latest

Test location /workspace/coverage/default/207.uart_fifo_reset.4147267181
Short name T243
Test name
Test status
Simulation time 122111637011 ps
CPU time 218.69 seconds
Started Jun 10 05:15:44 PM PDT 24
Finished Jun 10 05:19:23 PM PDT 24
Peak memory 200332 kb
Host smart-2c999acf-1fae-49ca-a2eb-c0f9fc9201a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147267181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.4147267181
Directory /workspace/207.uart_fifo_reset/latest

Test location /workspace/coverage/default/208.uart_fifo_reset.3679928492
Short name T869
Test name
Test status
Simulation time 35334934250 ps
CPU time 97.29 seconds
Started Jun 10 05:15:44 PM PDT 24
Finished Jun 10 05:17:22 PM PDT 24
Peak memory 200184 kb
Host smart-422781c7-8ed4-4066-ac8f-6add8946d30d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679928492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.3679928492
Directory /workspace/208.uart_fifo_reset/latest

Test location /workspace/coverage/default/209.uart_fifo_reset.3175009224
Short name T349
Test name
Test status
Simulation time 33280937539 ps
CPU time 11.99 seconds
Started Jun 10 05:15:46 PM PDT 24
Finished Jun 10 05:15:59 PM PDT 24
Peak memory 200152 kb
Host smart-c75faf8e-8343-4cdb-a8ca-89dc5c60e6bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175009224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.3175009224
Directory /workspace/209.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_alert_test.3191878618
Short name T414
Test name
Test status
Simulation time 13469175 ps
CPU time 0.56 seconds
Started Jun 10 05:13:53 PM PDT 24
Finished Jun 10 05:13:54 PM PDT 24
Peak memory 195388 kb
Host smart-8bd40595-56c0-4a34-b9fb-f507237c17cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191878618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.3191878618
Directory /workspace/21.uart_alert_test/latest

Test location /workspace/coverage/default/21.uart_fifo_full.2238037400
Short name T317
Test name
Test status
Simulation time 33553457127 ps
CPU time 54.92 seconds
Started Jun 10 05:13:38 PM PDT 24
Finished Jun 10 05:14:33 PM PDT 24
Peak memory 200384 kb
Host smart-c4f62e8a-6da8-4a5c-879f-c83a61948405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238037400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.2238037400
Directory /workspace/21.uart_fifo_full/latest

Test location /workspace/coverage/default/21.uart_fifo_overflow.3625222824
Short name T461
Test name
Test status
Simulation time 54813137127 ps
CPU time 13.86 seconds
Started Jun 10 05:13:47 PM PDT 24
Finished Jun 10 05:14:01 PM PDT 24
Peak memory 200312 kb
Host smart-0bcfbb49-607d-4af0-8343-4702d31e029f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625222824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.3625222824
Directory /workspace/21.uart_fifo_overflow/latest

Test location /workspace/coverage/default/21.uart_fifo_reset.1353087748
Short name T120
Test name
Test status
Simulation time 70493245627 ps
CPU time 19.49 seconds
Started Jun 10 05:13:37 PM PDT 24
Finished Jun 10 05:13:57 PM PDT 24
Peak memory 200396 kb
Host smart-b0002154-872f-436c-ae55-04f3bb85b0bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353087748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.1353087748
Directory /workspace/21.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_intr.2025925559
Short name T935
Test name
Test status
Simulation time 10408679155 ps
CPU time 14.48 seconds
Started Jun 10 05:13:37 PM PDT 24
Finished Jun 10 05:13:52 PM PDT 24
Peak memory 197204 kb
Host smart-95bbd6ef-5bac-4118-bb0f-08dab9de3476
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025925559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.2025925559
Directory /workspace/21.uart_intr/latest

Test location /workspace/coverage/default/21.uart_long_xfer_wo_dly.339663100
Short name T422
Test name
Test status
Simulation time 160644724037 ps
CPU time 974.54 seconds
Started Jun 10 05:13:39 PM PDT 24
Finished Jun 10 05:29:54 PM PDT 24
Peak memory 200332 kb
Host smart-d82c721b-4f2a-43f6-8409-132febd61cda
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=339663100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.339663100
Directory /workspace/21.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/21.uart_loopback.3581280564
Short name T401
Test name
Test status
Simulation time 5778185558 ps
CPU time 8.24 seconds
Started Jun 10 05:13:35 PM PDT 24
Finished Jun 10 05:13:44 PM PDT 24
Peak memory 199828 kb
Host smart-f9e3b873-c49f-46b3-860d-df0b5cc4b68c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581280564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_loopback.3581280564
Directory /workspace/21.uart_loopback/latest

Test location /workspace/coverage/default/21.uart_perf.1411835336
Short name T781
Test name
Test status
Simulation time 7142603848 ps
CPU time 93.7 seconds
Started Jun 10 05:13:51 PM PDT 24
Finished Jun 10 05:15:25 PM PDT 24
Peak memory 200272 kb
Host smart-2074aa5e-84e6-4801-905d-826ac718b706
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1411835336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.1411835336
Directory /workspace/21.uart_perf/latest

Test location /workspace/coverage/default/21.uart_rx_oversample.356452208
Short name T879
Test name
Test status
Simulation time 3580191886 ps
CPU time 27.23 seconds
Started Jun 10 05:13:53 PM PDT 24
Finished Jun 10 05:14:20 PM PDT 24
Peak memory 199128 kb
Host smart-70be0c5f-b1c0-4db1-8016-e9131e1db496
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=356452208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.356452208
Directory /workspace/21.uart_rx_oversample/latest

Test location /workspace/coverage/default/21.uart_rx_parity_err.3031549072
Short name T347
Test name
Test status
Simulation time 13843014909 ps
CPU time 24.53 seconds
Started Jun 10 05:13:43 PM PDT 24
Finished Jun 10 05:14:08 PM PDT 24
Peak memory 200292 kb
Host smart-76e189fc-f2ba-4e85-92b0-0421571190ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031549072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.3031549072
Directory /workspace/21.uart_rx_parity_err/latest

Test location /workspace/coverage/default/21.uart_rx_start_bit_filter.2140236073
Short name T534
Test name
Test status
Simulation time 1856030329 ps
CPU time 3.68 seconds
Started Jun 10 05:13:38 PM PDT 24
Finished Jun 10 05:13:43 PM PDT 24
Peak memory 195828 kb
Host smart-53f488fd-e894-4a2a-993f-146847de377f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140236073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.2140236073
Directory /workspace/21.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/21.uart_smoke.2767986040
Short name T324
Test name
Test status
Simulation time 5355744985 ps
CPU time 9.6 seconds
Started Jun 10 05:13:39 PM PDT 24
Finished Jun 10 05:13:49 PM PDT 24
Peak memory 200324 kb
Host smart-c2518902-462b-425b-b26e-a3b6d78068c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767986040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_smoke.2767986040
Directory /workspace/21.uart_smoke/latest

Test location /workspace/coverage/default/21.uart_stress_all_with_rand_reset.1488723835
Short name T34
Test name
Test status
Simulation time 37742621491 ps
CPU time 575.7 seconds
Started Jun 10 05:13:53 PM PDT 24
Finished Jun 10 05:23:29 PM PDT 24
Peak memory 213884 kb
Host smart-b6abc1ab-b773-4d06-a7e9-560ba8e13775
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488723835 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 21.uart_stress_all_with_rand_reset.1488723835
Directory /workspace/21.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.uart_tx_ovrd.334293164
Short name T849
Test name
Test status
Simulation time 1106350074 ps
CPU time 1.4 seconds
Started Jun 10 05:13:38 PM PDT 24
Finished Jun 10 05:13:40 PM PDT 24
Peak memory 198640 kb
Host smart-aaeef625-b3e0-4ecd-83ed-ff7a1378c49c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334293164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.334293164
Directory /workspace/21.uart_tx_ovrd/latest

Test location /workspace/coverage/default/21.uart_tx_rx.733110497
Short name T1085
Test name
Test status
Simulation time 8114883870 ps
CPU time 7.04 seconds
Started Jun 10 05:13:59 PM PDT 24
Finished Jun 10 05:14:06 PM PDT 24
Peak memory 198072 kb
Host smart-e64cea5e-d160-417e-9f09-145569417045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733110497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.733110497
Directory /workspace/21.uart_tx_rx/latest

Test location /workspace/coverage/default/210.uart_fifo_reset.233617100
Short name T260
Test name
Test status
Simulation time 48480064385 ps
CPU time 94.46 seconds
Started Jun 10 05:15:47 PM PDT 24
Finished Jun 10 05:17:21 PM PDT 24
Peak memory 200356 kb
Host smart-89f505cb-344e-4d5b-94eb-948e48578934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233617100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.233617100
Directory /workspace/210.uart_fifo_reset/latest

Test location /workspace/coverage/default/211.uart_fifo_reset.3822735707
Short name T955
Test name
Test status
Simulation time 10289947601 ps
CPU time 18.72 seconds
Started Jun 10 05:15:46 PM PDT 24
Finished Jun 10 05:16:05 PM PDT 24
Peak memory 200300 kb
Host smart-d34f0b46-c721-4f5e-95ad-188a254c4722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822735707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.3822735707
Directory /workspace/211.uart_fifo_reset/latest

Test location /workspace/coverage/default/212.uart_fifo_reset.1453422789
Short name T976
Test name
Test status
Simulation time 123775444870 ps
CPU time 146.96 seconds
Started Jun 10 05:15:46 PM PDT 24
Finished Jun 10 05:18:13 PM PDT 24
Peak memory 200160 kb
Host smart-5fd2be5a-5e33-449b-a0e9-e8149424176a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453422789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.1453422789
Directory /workspace/212.uart_fifo_reset/latest

Test location /workspace/coverage/default/214.uart_fifo_reset.4292753704
Short name T656
Test name
Test status
Simulation time 203810515224 ps
CPU time 80.53 seconds
Started Jun 10 05:15:47 PM PDT 24
Finished Jun 10 05:17:08 PM PDT 24
Peak memory 200384 kb
Host smart-e8542e95-fcb7-4ed6-9db0-61a62d85479e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292753704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.4292753704
Directory /workspace/214.uart_fifo_reset/latest

Test location /workspace/coverage/default/215.uart_fifo_reset.3824597582
Short name T235
Test name
Test status
Simulation time 80123671036 ps
CPU time 57.18 seconds
Started Jun 10 05:15:45 PM PDT 24
Finished Jun 10 05:16:43 PM PDT 24
Peak memory 200288 kb
Host smart-77257f7f-7ec2-4015-85a3-98ac8765cb4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824597582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.3824597582
Directory /workspace/215.uart_fifo_reset/latest

Test location /workspace/coverage/default/216.uart_fifo_reset.3274800057
Short name T647
Test name
Test status
Simulation time 49139738894 ps
CPU time 9.13 seconds
Started Jun 10 05:15:46 PM PDT 24
Finished Jun 10 05:15:55 PM PDT 24
Peak memory 200208 kb
Host smart-e089500e-3c15-43a7-b2a9-c9e0caa2b4f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274800057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.3274800057
Directory /workspace/216.uart_fifo_reset/latest

Test location /workspace/coverage/default/217.uart_fifo_reset.288696935
Short name T557
Test name
Test status
Simulation time 25254851368 ps
CPU time 48.72 seconds
Started Jun 10 05:15:47 PM PDT 24
Finished Jun 10 05:16:36 PM PDT 24
Peak memory 200348 kb
Host smart-f2cf1d45-6b86-4a06-979b-ac7d1264736f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288696935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.288696935
Directory /workspace/217.uart_fifo_reset/latest

Test location /workspace/coverage/default/218.uart_fifo_reset.2657480919
Short name T127
Test name
Test status
Simulation time 74853559984 ps
CPU time 11.35 seconds
Started Jun 10 05:15:44 PM PDT 24
Finished Jun 10 05:15:55 PM PDT 24
Peak memory 200304 kb
Host smart-90b4ce84-ff9d-4985-a92a-04c80e41ff9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657480919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.2657480919
Directory /workspace/218.uart_fifo_reset/latest

Test location /workspace/coverage/default/219.uart_fifo_reset.2476708876
Short name T111
Test name
Test status
Simulation time 6553624512 ps
CPU time 10.66 seconds
Started Jun 10 05:15:44 PM PDT 24
Finished Jun 10 05:15:55 PM PDT 24
Peak memory 200136 kb
Host smart-0a99e437-15dc-40b6-aff1-664d593c617e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476708876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.2476708876
Directory /workspace/219.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_alert_test.733570783
Short name T798
Test name
Test status
Simulation time 32449177 ps
CPU time 0.54 seconds
Started Jun 10 05:13:52 PM PDT 24
Finished Jun 10 05:13:53 PM PDT 24
Peak memory 195576 kb
Host smart-8255f841-7f5a-4c60-b52c-c87e3923e470
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733570783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.733570783
Directory /workspace/22.uart_alert_test/latest

Test location /workspace/coverage/default/22.uart_fifo_full.2276320879
Short name T1019
Test name
Test status
Simulation time 29690390776 ps
CPU time 49.75 seconds
Started Jun 10 05:13:48 PM PDT 24
Finished Jun 10 05:14:38 PM PDT 24
Peak memory 200332 kb
Host smart-72311582-5c1c-4fd4-b719-78dc10dc64d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276320879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.2276320879
Directory /workspace/22.uart_fifo_full/latest

Test location /workspace/coverage/default/22.uart_fifo_overflow.1590739780
Short name T630
Test name
Test status
Simulation time 33905999134 ps
CPU time 17.29 seconds
Started Jun 10 05:13:39 PM PDT 24
Finished Jun 10 05:13:56 PM PDT 24
Peak memory 200400 kb
Host smart-d73a0879-180d-4624-b978-8af1ba5d2c65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590739780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.1590739780
Directory /workspace/22.uart_fifo_overflow/latest

Test location /workspace/coverage/default/22.uart_fifo_reset.1209800839
Short name T244
Test name
Test status
Simulation time 81721343485 ps
CPU time 15.16 seconds
Started Jun 10 05:13:50 PM PDT 24
Finished Jun 10 05:14:05 PM PDT 24
Peak memory 200228 kb
Host smart-b716c20d-e04b-47d9-81b5-435df1d7b77b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209800839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.1209800839
Directory /workspace/22.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_intr.269751073
Short name T501
Test name
Test status
Simulation time 51886043241 ps
CPU time 52.65 seconds
Started Jun 10 05:13:47 PM PDT 24
Finished Jun 10 05:14:40 PM PDT 24
Peak memory 200292 kb
Host smart-9fed5617-5864-4fca-b371-014194c51496
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269751073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.269751073
Directory /workspace/22.uart_intr/latest

Test location /workspace/coverage/default/22.uart_long_xfer_wo_dly.482629298
Short name T731
Test name
Test status
Simulation time 160768119568 ps
CPU time 1151.51 seconds
Started Jun 10 05:13:51 PM PDT 24
Finished Jun 10 05:33:03 PM PDT 24
Peak memory 200168 kb
Host smart-54952ef6-06bb-451a-bd05-3fffb8bbe566
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=482629298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.482629298
Directory /workspace/22.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/22.uart_loopback.3969377082
Short name T583
Test name
Test status
Simulation time 12554658919 ps
CPU time 9.64 seconds
Started Jun 10 05:13:47 PM PDT 24
Finished Jun 10 05:13:57 PM PDT 24
Peak memory 200236 kb
Host smart-a9d4c8d3-fb96-4577-8d84-6eab2ef17eba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969377082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_loopback.3969377082
Directory /workspace/22.uart_loopback/latest

Test location /workspace/coverage/default/22.uart_rx_oversample.117471033
Short name T573
Test name
Test status
Simulation time 6057500443 ps
CPU time 28.93 seconds
Started Jun 10 05:13:43 PM PDT 24
Finished Jun 10 05:14:12 PM PDT 24
Peak memory 199124 kb
Host smart-d5e5df01-df6f-4e89-ac24-0bd3b43d2f7d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=117471033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.117471033
Directory /workspace/22.uart_rx_oversample/latest

Test location /workspace/coverage/default/22.uart_rx_parity_err.2012871130
Short name T735
Test name
Test status
Simulation time 44029836862 ps
CPU time 39.76 seconds
Started Jun 10 05:13:40 PM PDT 24
Finished Jun 10 05:14:20 PM PDT 24
Peak memory 200272 kb
Host smart-65a786ae-6f82-4cb5-9169-d6cddcc0c580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012871130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.2012871130
Directory /workspace/22.uart_rx_parity_err/latest

Test location /workspace/coverage/default/22.uart_rx_start_bit_filter.1863643791
Short name T39
Test name
Test status
Simulation time 35531200875 ps
CPU time 3.32 seconds
Started Jun 10 05:13:40 PM PDT 24
Finished Jun 10 05:13:44 PM PDT 24
Peak memory 196552 kb
Host smart-adc3ad56-3a9e-4725-b296-ab715e80d183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863643791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.1863643791
Directory /workspace/22.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/22.uart_smoke.2869524205
Short name T799
Test name
Test status
Simulation time 5734458262 ps
CPU time 10.19 seconds
Started Jun 10 05:13:45 PM PDT 24
Finished Jun 10 05:13:56 PM PDT 24
Peak memory 199612 kb
Host smart-b0762df3-6b47-4338-8deb-0971d36f43ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869524205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_smoke.2869524205
Directory /workspace/22.uart_smoke/latest

Test location /workspace/coverage/default/22.uart_stress_all.2041054774
Short name T842
Test name
Test status
Simulation time 84645384232 ps
CPU time 26.36 seconds
Started Jun 10 05:13:46 PM PDT 24
Finished Jun 10 05:14:13 PM PDT 24
Peak memory 200296 kb
Host smart-c015332c-6f62-4025-88bb-9d7bfc1249a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041054774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.2041054774
Directory /workspace/22.uart_stress_all/latest

Test location /workspace/coverage/default/22.uart_tx_ovrd.2460612055
Short name T285
Test name
Test status
Simulation time 7985175618 ps
CPU time 9.49 seconds
Started Jun 10 05:13:41 PM PDT 24
Finished Jun 10 05:13:51 PM PDT 24
Peak memory 200376 kb
Host smart-5b82a040-d5af-4117-a4a2-39291045ce61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460612055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.2460612055
Directory /workspace/22.uart_tx_ovrd/latest

Test location /workspace/coverage/default/22.uart_tx_rx.3957385786
Short name T563
Test name
Test status
Simulation time 48384631680 ps
CPU time 109.94 seconds
Started Jun 10 05:13:42 PM PDT 24
Finished Jun 10 05:15:38 PM PDT 24
Peak memory 200332 kb
Host smart-441fa965-2d43-4c13-a69e-a94d35237455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957385786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.3957385786
Directory /workspace/22.uart_tx_rx/latest

Test location /workspace/coverage/default/220.uart_fifo_reset.4077268394
Short name T1072
Test name
Test status
Simulation time 88372176802 ps
CPU time 151.75 seconds
Started Jun 10 05:15:45 PM PDT 24
Finished Jun 10 05:18:17 PM PDT 24
Peak memory 200340 kb
Host smart-4a2c925a-4d8b-4a4b-854a-ae7f885e9b79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077268394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.4077268394
Directory /workspace/220.uart_fifo_reset/latest

Test location /workspace/coverage/default/221.uart_fifo_reset.644776095
Short name T620
Test name
Test status
Simulation time 28010003312 ps
CPU time 42.08 seconds
Started Jun 10 05:15:50 PM PDT 24
Finished Jun 10 05:16:32 PM PDT 24
Peak memory 200296 kb
Host smart-5134d1cd-209b-4355-8648-e741879354a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644776095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.644776095
Directory /workspace/221.uart_fifo_reset/latest

Test location /workspace/coverage/default/222.uart_fifo_reset.31091251
Short name T474
Test name
Test status
Simulation time 33028924373 ps
CPU time 54.27 seconds
Started Jun 10 05:15:47 PM PDT 24
Finished Jun 10 05:16:42 PM PDT 24
Peak memory 200364 kb
Host smart-587c6e1d-f64c-4f0c-9834-6a8ef87795d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31091251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.31091251
Directory /workspace/222.uart_fifo_reset/latest

Test location /workspace/coverage/default/223.uart_fifo_reset.534763314
Short name T871
Test name
Test status
Simulation time 81213511992 ps
CPU time 87.57 seconds
Started Jun 10 05:15:49 PM PDT 24
Finished Jun 10 05:17:17 PM PDT 24
Peak memory 200300 kb
Host smart-b9f7df69-4996-419a-9b7c-f57b7db31daa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534763314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.534763314
Directory /workspace/223.uart_fifo_reset/latest

Test location /workspace/coverage/default/224.uart_fifo_reset.223281494
Short name T859
Test name
Test status
Simulation time 167002224371 ps
CPU time 126.44 seconds
Started Jun 10 05:15:50 PM PDT 24
Finished Jun 10 05:17:57 PM PDT 24
Peak memory 200308 kb
Host smart-398be45a-14e1-4aa9-95f3-647bf0d2d81c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223281494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.223281494
Directory /workspace/224.uart_fifo_reset/latest

Test location /workspace/coverage/default/225.uart_fifo_reset.2646640741
Short name T160
Test name
Test status
Simulation time 15788070204 ps
CPU time 23.61 seconds
Started Jun 10 05:15:51 PM PDT 24
Finished Jun 10 05:16:15 PM PDT 24
Peak memory 200264 kb
Host smart-05b6c7ab-55ef-496c-a0c1-e1ee83749284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646640741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.2646640741
Directory /workspace/225.uart_fifo_reset/latest

Test location /workspace/coverage/default/226.uart_fifo_reset.1995230146
Short name T213
Test name
Test status
Simulation time 60814677500 ps
CPU time 103.05 seconds
Started Jun 10 05:15:51 PM PDT 24
Finished Jun 10 05:17:34 PM PDT 24
Peak memory 200328 kb
Host smart-9d923e71-157f-4e7e-9ab9-83cf51069211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995230146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.1995230146
Directory /workspace/226.uart_fifo_reset/latest

Test location /workspace/coverage/default/227.uart_fifo_reset.1933938217
Short name T88
Test name
Test status
Simulation time 17583149814 ps
CPU time 28.85 seconds
Started Jun 10 05:15:49 PM PDT 24
Finished Jun 10 05:16:18 PM PDT 24
Peak memory 200352 kb
Host smart-f2430598-10d0-4e00-974b-fa471a582d8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933938217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.1933938217
Directory /workspace/227.uart_fifo_reset/latest

Test location /workspace/coverage/default/228.uart_fifo_reset.4144689483
Short name T208
Test name
Test status
Simulation time 163669956843 ps
CPU time 21.04 seconds
Started Jun 10 05:15:51 PM PDT 24
Finished Jun 10 05:16:12 PM PDT 24
Peak memory 200288 kb
Host smart-8499a28e-8189-49df-a1e4-a1a5624f3ce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144689483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.4144689483
Directory /workspace/228.uart_fifo_reset/latest

Test location /workspace/coverage/default/229.uart_fifo_reset.1782947957
Short name T773
Test name
Test status
Simulation time 31063809126 ps
CPU time 68.11 seconds
Started Jun 10 05:15:50 PM PDT 24
Finished Jun 10 05:16:58 PM PDT 24
Peak memory 200280 kb
Host smart-987f1d98-79f2-4fe2-921e-d944c6c87c4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782947957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.1782947957
Directory /workspace/229.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_alert_test.1991903538
Short name T725
Test name
Test status
Simulation time 25550854 ps
CPU time 0.58 seconds
Started Jun 10 05:13:47 PM PDT 24
Finished Jun 10 05:13:48 PM PDT 24
Peak memory 195944 kb
Host smart-23d378a0-6477-413f-956b-110c966824c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991903538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.1991903538
Directory /workspace/23.uart_alert_test/latest

Test location /workspace/coverage/default/23.uart_fifo_full.2351967254
Short name T300
Test name
Test status
Simulation time 38200495220 ps
CPU time 34.73 seconds
Started Jun 10 05:13:39 PM PDT 24
Finished Jun 10 05:14:14 PM PDT 24
Peak memory 200396 kb
Host smart-b259176a-1a2a-4a2e-baa9-590c6e87c35a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351967254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.2351967254
Directory /workspace/23.uart_fifo_full/latest

Test location /workspace/coverage/default/23.uart_fifo_overflow.3471442626
Short name T598
Test name
Test status
Simulation time 86893742384 ps
CPU time 202.87 seconds
Started Jun 10 05:13:59 PM PDT 24
Finished Jun 10 05:17:23 PM PDT 24
Peak memory 200208 kb
Host smart-80c6db06-dfb3-4d26-83e1-6d04447f5dd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471442626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.3471442626
Directory /workspace/23.uart_fifo_overflow/latest

Test location /workspace/coverage/default/23.uart_fifo_reset.2876576167
Short name T230
Test name
Test status
Simulation time 15408055420 ps
CPU time 26.15 seconds
Started Jun 10 05:13:52 PM PDT 24
Finished Jun 10 05:14:18 PM PDT 24
Peak memory 200360 kb
Host smart-dfc94d38-3093-433d-b405-5413448be627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876576167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.2876576167
Directory /workspace/23.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_intr.1323217420
Short name T697
Test name
Test status
Simulation time 44291410129 ps
CPU time 9.24 seconds
Started Jun 10 05:13:51 PM PDT 24
Finished Jun 10 05:14:00 PM PDT 24
Peak memory 200288 kb
Host smart-07711bfd-a87f-4287-87fa-3faed7787fe8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323217420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.1323217420
Directory /workspace/23.uart_intr/latest

Test location /workspace/coverage/default/23.uart_long_xfer_wo_dly.493051239
Short name T366
Test name
Test status
Simulation time 36945928306 ps
CPU time 37.68 seconds
Started Jun 10 05:13:46 PM PDT 24
Finished Jun 10 05:14:24 PM PDT 24
Peak memory 200292 kb
Host smart-41018219-098b-4ddd-a893-0404ad6fe4eb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=493051239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.493051239
Directory /workspace/23.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/23.uart_loopback.3035963050
Short name T420
Test name
Test status
Simulation time 9007073269 ps
CPU time 17.51 seconds
Started Jun 10 05:13:52 PM PDT 24
Finished Jun 10 05:14:09 PM PDT 24
Peak memory 199412 kb
Host smart-090fe31a-b14d-40ba-a20c-28ee845b6964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035963050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_loopback.3035963050
Directory /workspace/23.uart_loopback/latest

Test location /workspace/coverage/default/23.uart_perf.3703152275
Short name T754
Test name
Test status
Simulation time 7408843814 ps
CPU time 142.91 seconds
Started Jun 10 05:13:48 PM PDT 24
Finished Jun 10 05:16:11 PM PDT 24
Peak memory 200172 kb
Host smart-2bdd11a6-d609-473d-826a-e876de49aa44
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3703152275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.3703152275
Directory /workspace/23.uart_perf/latest

Test location /workspace/coverage/default/23.uart_rx_oversample.3792922981
Short name T471
Test name
Test status
Simulation time 5806871853 ps
CPU time 12.59 seconds
Started Jun 10 05:13:41 PM PDT 24
Finished Jun 10 05:13:54 PM PDT 24
Peak memory 198976 kb
Host smart-f2ec2341-2c55-49c2-b89c-18f5125d075a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3792922981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.3792922981
Directory /workspace/23.uart_rx_oversample/latest

Test location /workspace/coverage/default/23.uart_rx_parity_err.3592099456
Short name T672
Test name
Test status
Simulation time 90168326350 ps
CPU time 143.51 seconds
Started Jun 10 05:14:04 PM PDT 24
Finished Jun 10 05:16:28 PM PDT 24
Peak memory 200212 kb
Host smart-7e9aa43a-c43d-48eb-9040-b5707bcc619d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592099456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.3592099456
Directory /workspace/23.uart_rx_parity_err/latest

Test location /workspace/coverage/default/23.uart_rx_start_bit_filter.661185992
Short name T481
Test name
Test status
Simulation time 4106483720 ps
CPU time 2.17 seconds
Started Jun 10 05:13:42 PM PDT 24
Finished Jun 10 05:13:44 PM PDT 24
Peak memory 196500 kb
Host smart-4afe0e1d-5683-4593-af5a-eb814726dd28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661185992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.661185992
Directory /workspace/23.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/23.uart_smoke.316837688
Short name T831
Test name
Test status
Simulation time 5532044322 ps
CPU time 10.79 seconds
Started Jun 10 05:13:40 PM PDT 24
Finished Jun 10 05:13:51 PM PDT 24
Peak memory 200352 kb
Host smart-0a8703bd-5310-4f18-ba95-713f68422989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316837688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_smoke.316837688
Directory /workspace/23.uart_smoke/latest

Test location /workspace/coverage/default/23.uart_tx_ovrd.3990920982
Short name T941
Test name
Test status
Simulation time 461333859 ps
CPU time 1.52 seconds
Started Jun 10 05:13:45 PM PDT 24
Finished Jun 10 05:13:46 PM PDT 24
Peak memory 200232 kb
Host smart-0fdc8587-1234-4536-ad0f-a26a95580e32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990920982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.3990920982
Directory /workspace/23.uart_tx_ovrd/latest

Test location /workspace/coverage/default/230.uart_fifo_reset.2240277133
Short name T1078
Test name
Test status
Simulation time 33453868995 ps
CPU time 15.56 seconds
Started Jun 10 05:15:50 PM PDT 24
Finished Jun 10 05:16:06 PM PDT 24
Peak memory 200256 kb
Host smart-212bd9c8-546e-4cf5-873e-25b997a2df6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240277133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.2240277133
Directory /workspace/230.uart_fifo_reset/latest

Test location /workspace/coverage/default/231.uart_fifo_reset.3745712078
Short name T971
Test name
Test status
Simulation time 90153095280 ps
CPU time 16.11 seconds
Started Jun 10 05:15:50 PM PDT 24
Finished Jun 10 05:16:07 PM PDT 24
Peak memory 200356 kb
Host smart-b5f71c58-7542-489f-b711-73591445660f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745712078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.3745712078
Directory /workspace/231.uart_fifo_reset/latest

Test location /workspace/coverage/default/232.uart_fifo_reset.346779719
Short name T350
Test name
Test status
Simulation time 24849485364 ps
CPU time 34.46 seconds
Started Jun 10 05:15:50 PM PDT 24
Finished Jun 10 05:16:25 PM PDT 24
Peak memory 200280 kb
Host smart-cee570bc-d2eb-4178-8e19-605c2914f374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346779719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.346779719
Directory /workspace/232.uart_fifo_reset/latest

Test location /workspace/coverage/default/233.uart_fifo_reset.3517132557
Short name T910
Test name
Test status
Simulation time 67455850966 ps
CPU time 50.53 seconds
Started Jun 10 05:15:50 PM PDT 24
Finished Jun 10 05:16:41 PM PDT 24
Peak memory 200296 kb
Host smart-0cb100f1-1aa4-48d3-ac49-b19b109348d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517132557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.3517132557
Directory /workspace/233.uart_fifo_reset/latest

Test location /workspace/coverage/default/235.uart_fifo_reset.3106095445
Short name T690
Test name
Test status
Simulation time 85678217632 ps
CPU time 15.41 seconds
Started Jun 10 05:15:52 PM PDT 24
Finished Jun 10 05:16:08 PM PDT 24
Peak memory 200160 kb
Host smart-b76479ce-b7f9-4da5-b16b-92dc40f673ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106095445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.3106095445
Directory /workspace/235.uart_fifo_reset/latest

Test location /workspace/coverage/default/236.uart_fifo_reset.3367429462
Short name T247
Test name
Test status
Simulation time 129271238197 ps
CPU time 52.19 seconds
Started Jun 10 05:15:50 PM PDT 24
Finished Jun 10 05:16:42 PM PDT 24
Peak memory 200160 kb
Host smart-490b24e7-9a01-4aee-929f-6338c51e3e76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367429462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.3367429462
Directory /workspace/236.uart_fifo_reset/latest

Test location /workspace/coverage/default/237.uart_fifo_reset.1984150374
Short name T1051
Test name
Test status
Simulation time 193215756468 ps
CPU time 49.29 seconds
Started Jun 10 05:15:52 PM PDT 24
Finished Jun 10 05:16:42 PM PDT 24
Peak memory 200104 kb
Host smart-5c7e7dad-7406-42ba-a81c-8ef4f5a4a823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984150374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.1984150374
Directory /workspace/237.uart_fifo_reset/latest

Test location /workspace/coverage/default/238.uart_fifo_reset.3595944125
Short name T1043
Test name
Test status
Simulation time 52647906325 ps
CPU time 26.95 seconds
Started Jun 10 05:15:52 PM PDT 24
Finished Jun 10 05:16:19 PM PDT 24
Peak memory 200256 kb
Host smart-4b8fec15-bc09-4413-bb54-5f3ebb0ba53e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595944125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.3595944125
Directory /workspace/238.uart_fifo_reset/latest

Test location /workspace/coverage/default/239.uart_fifo_reset.1924419812
Short name T655
Test name
Test status
Simulation time 97636737680 ps
CPU time 71.4 seconds
Started Jun 10 05:15:55 PM PDT 24
Finished Jun 10 05:17:06 PM PDT 24
Peak memory 200392 kb
Host smart-766529fd-0883-4221-a459-fb5b0603a294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924419812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.1924419812
Directory /workspace/239.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_alert_test.1077940329
Short name T524
Test name
Test status
Simulation time 33241151 ps
CPU time 0.56 seconds
Started Jun 10 05:13:59 PM PDT 24
Finished Jun 10 05:14:00 PM PDT 24
Peak memory 195684 kb
Host smart-516c018d-ab26-454b-879b-04b55bf6097d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077940329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.1077940329
Directory /workspace/24.uart_alert_test/latest

Test location /workspace/coverage/default/24.uart_fifo_full.1264762020
Short name T311
Test name
Test status
Simulation time 24098485284 ps
CPU time 20.26 seconds
Started Jun 10 05:13:52 PM PDT 24
Finished Jun 10 05:14:13 PM PDT 24
Peak memory 200344 kb
Host smart-0e01f9fc-2691-4c80-87b6-ee16e38ac757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264762020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.1264762020
Directory /workspace/24.uart_fifo_full/latest

Test location /workspace/coverage/default/24.uart_fifo_overflow.4029590652
Short name T619
Test name
Test status
Simulation time 135899048499 ps
CPU time 99.91 seconds
Started Jun 10 05:13:55 PM PDT 24
Finished Jun 10 05:15:35 PM PDT 24
Peak memory 200044 kb
Host smart-683a5341-e1b5-4cac-9338-6622397d9ce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029590652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.4029590652
Directory /workspace/24.uart_fifo_overflow/latest

Test location /workspace/coverage/default/24.uart_fifo_reset.3327784961
Short name T856
Test name
Test status
Simulation time 132362912969 ps
CPU time 349.12 seconds
Started Jun 10 05:13:43 PM PDT 24
Finished Jun 10 05:19:32 PM PDT 24
Peak memory 200280 kb
Host smart-ac218865-a0ed-4e2e-8d34-30ed9acadec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327784961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.3327784961
Directory /workspace/24.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_intr.2921297900
Short name T964
Test name
Test status
Simulation time 320210231575 ps
CPU time 222.14 seconds
Started Jun 10 05:13:41 PM PDT 24
Finished Jun 10 05:17:24 PM PDT 24
Peak memory 200336 kb
Host smart-b8061402-1874-4c72-9121-f498a242a3b2
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921297900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.2921297900
Directory /workspace/24.uart_intr/latest

Test location /workspace/coverage/default/24.uart_long_xfer_wo_dly.4053022555
Short name T342
Test name
Test status
Simulation time 192265857780 ps
CPU time 1711.97 seconds
Started Jun 10 05:13:45 PM PDT 24
Finished Jun 10 05:42:17 PM PDT 24
Peak memory 200524 kb
Host smart-3d636125-0b03-4d62-93b2-7e486d88dfd3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4053022555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.4053022555
Directory /workspace/24.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/24.uart_loopback.3773706552
Short name T1016
Test name
Test status
Simulation time 8612099711 ps
CPU time 15.26 seconds
Started Jun 10 05:13:51 PM PDT 24
Finished Jun 10 05:14:07 PM PDT 24
Peak memory 199916 kb
Host smart-291f611b-867c-4d30-a6d0-5bffdc823103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773706552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_loopback.3773706552
Directory /workspace/24.uart_loopback/latest

Test location /workspace/coverage/default/24.uart_perf.1406390926
Short name T984
Test name
Test status
Simulation time 19653932897 ps
CPU time 1088.99 seconds
Started Jun 10 05:14:02 PM PDT 24
Finished Jun 10 05:32:11 PM PDT 24
Peak memory 200204 kb
Host smart-150726bc-329b-4669-8113-463a0bdd82fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1406390926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.1406390926
Directory /workspace/24.uart_perf/latest

Test location /workspace/coverage/default/24.uart_rx_oversample.199090200
Short name T1013
Test name
Test status
Simulation time 3281418926 ps
CPU time 16.6 seconds
Started Jun 10 05:13:41 PM PDT 24
Finished Jun 10 05:13:58 PM PDT 24
Peak memory 199236 kb
Host smart-ff4a5f7a-5a14-4525-8463-04872dbb3e14
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=199090200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.199090200
Directory /workspace/24.uart_rx_oversample/latest

Test location /workspace/coverage/default/24.uart_rx_parity_err.2270490109
Short name T894
Test name
Test status
Simulation time 27589188710 ps
CPU time 38.74 seconds
Started Jun 10 05:13:39 PM PDT 24
Finished Jun 10 05:14:18 PM PDT 24
Peak memory 200300 kb
Host smart-e2dd2b55-feb7-4a3a-9bbe-80c7eb33ff18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270490109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.2270490109
Directory /workspace/24.uart_rx_parity_err/latest

Test location /workspace/coverage/default/24.uart_rx_start_bit_filter.3541953249
Short name T836
Test name
Test status
Simulation time 47740802898 ps
CPU time 36.63 seconds
Started Jun 10 05:13:43 PM PDT 24
Finished Jun 10 05:14:20 PM PDT 24
Peak memory 196432 kb
Host smart-3c27c19d-80fa-4c08-8aa8-3b174c82a2a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541953249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.3541953249
Directory /workspace/24.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/24.uart_smoke.374340576
Short name T1010
Test name
Test status
Simulation time 471525336 ps
CPU time 2.06 seconds
Started Jun 10 05:13:41 PM PDT 24
Finished Jun 10 05:13:43 PM PDT 24
Peak memory 199960 kb
Host smart-15c55499-22b3-4e28-a3ed-144152ef0c57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374340576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_smoke.374340576
Directory /workspace/24.uart_smoke/latest

Test location /workspace/coverage/default/24.uart_stress_all_with_rand_reset.1240490016
Short name T816
Test name
Test status
Simulation time 30893659873 ps
CPU time 188.91 seconds
Started Jun 10 05:13:55 PM PDT 24
Finished Jun 10 05:17:04 PM PDT 24
Peak memory 216128 kb
Host smart-8103c559-1316-4c70-a961-1ac1d98eb7ab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240490016 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 24.uart_stress_all_with_rand_reset.1240490016
Directory /workspace/24.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.uart_tx_ovrd.2677198638
Short name T274
Test name
Test status
Simulation time 1871859278 ps
CPU time 1.92 seconds
Started Jun 10 05:13:49 PM PDT 24
Finished Jun 10 05:13:51 PM PDT 24
Peak memory 198352 kb
Host smart-9db318ef-aeea-48ef-bd67-8e36d8e910ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677198638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.2677198638
Directory /workspace/24.uart_tx_ovrd/latest

Test location /workspace/coverage/default/24.uart_tx_rx.3685874587
Short name T824
Test name
Test status
Simulation time 182381880140 ps
CPU time 33.44 seconds
Started Jun 10 05:13:41 PM PDT 24
Finished Jun 10 05:14:15 PM PDT 24
Peak memory 200324 kb
Host smart-60f2eac0-2f90-479e-a60f-b020ea463136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685874587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.3685874587
Directory /workspace/24.uart_tx_rx/latest

Test location /workspace/coverage/default/240.uart_fifo_reset.1411074244
Short name T916
Test name
Test status
Simulation time 41119005671 ps
CPU time 17.36 seconds
Started Jun 10 05:15:54 PM PDT 24
Finished Jun 10 05:16:11 PM PDT 24
Peak memory 200092 kb
Host smart-87d44eba-fbff-4607-a83c-09bf9eacc215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411074244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.1411074244
Directory /workspace/240.uart_fifo_reset/latest

Test location /workspace/coverage/default/241.uart_fifo_reset.3351420228
Short name T682
Test name
Test status
Simulation time 194085551032 ps
CPU time 41.26 seconds
Started Jun 10 05:15:57 PM PDT 24
Finished Jun 10 05:16:38 PM PDT 24
Peak memory 200316 kb
Host smart-db1a0806-f31b-4900-a750-021cec8c9f89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351420228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.3351420228
Directory /workspace/241.uart_fifo_reset/latest

Test location /workspace/coverage/default/242.uart_fifo_reset.2915451626
Short name T828
Test name
Test status
Simulation time 43792584403 ps
CPU time 59.61 seconds
Started Jun 10 05:15:56 PM PDT 24
Finished Jun 10 05:16:56 PM PDT 24
Peak memory 200256 kb
Host smart-7a87bdbb-81bb-4070-b279-0356f1580b71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915451626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.2915451626
Directory /workspace/242.uart_fifo_reset/latest

Test location /workspace/coverage/default/243.uart_fifo_reset.31073479
Short name T624
Test name
Test status
Simulation time 10142109449 ps
CPU time 16.53 seconds
Started Jun 10 05:15:54 PM PDT 24
Finished Jun 10 05:16:11 PM PDT 24
Peak memory 200312 kb
Host smart-3c1548b0-6be1-4710-9c69-33141b3dfdb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31073479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.31073479
Directory /workspace/243.uart_fifo_reset/latest

Test location /workspace/coverage/default/244.uart_fifo_reset.3464486840
Short name T327
Test name
Test status
Simulation time 132120383567 ps
CPU time 60.76 seconds
Started Jun 10 05:15:54 PM PDT 24
Finished Jun 10 05:16:55 PM PDT 24
Peak memory 200356 kb
Host smart-1b178fda-fa4a-4208-a727-1ad7fc216f96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464486840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.3464486840
Directory /workspace/244.uart_fifo_reset/latest

Test location /workspace/coverage/default/245.uart_fifo_reset.3656592805
Short name T920
Test name
Test status
Simulation time 109094457624 ps
CPU time 287.06 seconds
Started Jun 10 05:15:55 PM PDT 24
Finished Jun 10 05:20:42 PM PDT 24
Peak memory 200300 kb
Host smart-ca21ce15-7893-488e-a78f-aee22f9b598d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656592805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.3656592805
Directory /workspace/245.uart_fifo_reset/latest

Test location /workspace/coverage/default/246.uart_fifo_reset.1839445527
Short name T875
Test name
Test status
Simulation time 109769898239 ps
CPU time 84.19 seconds
Started Jun 10 05:15:56 PM PDT 24
Finished Jun 10 05:17:21 PM PDT 24
Peak memory 200216 kb
Host smart-318a6bfc-3429-4b25-845d-a533169ddc59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839445527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.1839445527
Directory /workspace/246.uart_fifo_reset/latest

Test location /workspace/coverage/default/247.uart_fifo_reset.3845184408
Short name T259
Test name
Test status
Simulation time 117437854394 ps
CPU time 102.52 seconds
Started Jun 10 05:15:53 PM PDT 24
Finished Jun 10 05:17:36 PM PDT 24
Peak memory 200348 kb
Host smart-f3a29828-4f8a-45f3-a59a-3d6abca2362b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845184408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.3845184408
Directory /workspace/247.uart_fifo_reset/latest

Test location /workspace/coverage/default/248.uart_fifo_reset.1747427670
Short name T128
Test name
Test status
Simulation time 15354115589 ps
CPU time 29.07 seconds
Started Jun 10 05:16:01 PM PDT 24
Finished Jun 10 05:16:30 PM PDT 24
Peak memory 200384 kb
Host smart-de618345-a939-464b-b6d6-318f887252c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747427670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.1747427670
Directory /workspace/248.uart_fifo_reset/latest

Test location /workspace/coverage/default/249.uart_fifo_reset.2837407823
Short name T933
Test name
Test status
Simulation time 21295896513 ps
CPU time 19.13 seconds
Started Jun 10 05:16:00 PM PDT 24
Finished Jun 10 05:16:19 PM PDT 24
Peak memory 200324 kb
Host smart-f3ff12d7-5a0b-4218-9063-009c3f2255a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837407823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.2837407823
Directory /workspace/249.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_alert_test.3346254852
Short name T389
Test name
Test status
Simulation time 11235345 ps
CPU time 0.58 seconds
Started Jun 10 05:13:56 PM PDT 24
Finished Jun 10 05:13:57 PM PDT 24
Peak memory 195580 kb
Host smart-1b084b44-b3d5-4f8b-836b-a58aae6fa385
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346254852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.3346254852
Directory /workspace/25.uart_alert_test/latest

Test location /workspace/coverage/default/25.uart_fifo_full.4079623163
Short name T1
Test name
Test status
Simulation time 13847752213 ps
CPU time 11.77 seconds
Started Jun 10 05:13:52 PM PDT 24
Finished Jun 10 05:14:04 PM PDT 24
Peak memory 200192 kb
Host smart-a5dd7de0-d0cd-4185-a8fa-11bb39d8ac47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079623163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.4079623163
Directory /workspace/25.uart_fifo_full/latest

Test location /workspace/coverage/default/25.uart_fifo_overflow.3656002882
Short name T639
Test name
Test status
Simulation time 51694356486 ps
CPU time 131.43 seconds
Started Jun 10 05:13:59 PM PDT 24
Finished Jun 10 05:16:11 PM PDT 24
Peak memory 200232 kb
Host smart-0670619a-e278-4e45-b06a-82f57af2f33c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656002882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.3656002882
Directory /workspace/25.uart_fifo_overflow/latest

Test location /workspace/coverage/default/25.uart_fifo_reset.1358008516
Short name T329
Test name
Test status
Simulation time 25378625612 ps
CPU time 54.8 seconds
Started Jun 10 05:14:03 PM PDT 24
Finished Jun 10 05:14:58 PM PDT 24
Peak memory 200248 kb
Host smart-58189c41-7462-4f16-b297-c8a206d79f55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358008516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.1358008516
Directory /workspace/25.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_long_xfer_wo_dly.1221285929
Short name T969
Test name
Test status
Simulation time 88212912144 ps
CPU time 504.07 seconds
Started Jun 10 05:13:46 PM PDT 24
Finished Jun 10 05:22:10 PM PDT 24
Peak memory 200228 kb
Host smart-59fb6933-cd48-44b1-ae9e-f7a27a978653
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1221285929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.1221285929
Directory /workspace/25.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/25.uart_loopback.2356399192
Short name T472
Test name
Test status
Simulation time 5076969543 ps
CPU time 9.57 seconds
Started Jun 10 05:13:44 PM PDT 24
Finished Jun 10 05:13:54 PM PDT 24
Peak memory 199472 kb
Host smart-26f1ef5b-273e-4806-a8e5-167a6243b252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356399192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_loopback.2356399192
Directory /workspace/25.uart_loopback/latest

Test location /workspace/coverage/default/25.uart_perf.1978535000
Short name T838
Test name
Test status
Simulation time 12060790260 ps
CPU time 643.53 seconds
Started Jun 10 05:13:51 PM PDT 24
Finished Jun 10 05:24:35 PM PDT 24
Peak memory 200192 kb
Host smart-b176f11b-63dd-42e8-9d78-90b3076f0dcf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1978535000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.1978535000
Directory /workspace/25.uart_perf/latest

Test location /workspace/coverage/default/25.uart_rx_oversample.589518960
Short name T626
Test name
Test status
Simulation time 4897519118 ps
CPU time 47.68 seconds
Started Jun 10 05:13:54 PM PDT 24
Finished Jun 10 05:14:43 PM PDT 24
Peak memory 199592 kb
Host smart-f40a99a7-3fe2-4522-9389-2527002b1db0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=589518960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.589518960
Directory /workspace/25.uart_rx_oversample/latest

Test location /workspace/coverage/default/25.uart_rx_parity_err.3910833232
Short name T932
Test name
Test status
Simulation time 39881177898 ps
CPU time 19.16 seconds
Started Jun 10 05:14:01 PM PDT 24
Finished Jun 10 05:14:20 PM PDT 24
Peak memory 200324 kb
Host smart-db81170c-5a5c-4f71-8845-15bd53e90a0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910833232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.3910833232
Directory /workspace/25.uart_rx_parity_err/latest

Test location /workspace/coverage/default/25.uart_rx_start_bit_filter.3322620158
Short name T296
Test name
Test status
Simulation time 39550742765 ps
CPU time 54.56 seconds
Started Jun 10 05:13:47 PM PDT 24
Finished Jun 10 05:14:42 PM PDT 24
Peak memory 196400 kb
Host smart-99628eba-c29a-40a2-b178-c174a80a1c23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322620158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.3322620158
Directory /workspace/25.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/25.uart_smoke.452741744
Short name T957
Test name
Test status
Simulation time 602772925 ps
CPU time 2.33 seconds
Started Jun 10 05:13:53 PM PDT 24
Finished Jun 10 05:13:56 PM PDT 24
Peak memory 198704 kb
Host smart-1402e4a8-97ac-466c-8b73-c302bd9f73a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452741744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_smoke.452741744
Directory /workspace/25.uart_smoke/latest

Test location /workspace/coverage/default/25.uart_stress_all.2288609396
Short name T186
Test name
Test status
Simulation time 222037224737 ps
CPU time 506.54 seconds
Started Jun 10 05:13:55 PM PDT 24
Finished Jun 10 05:22:22 PM PDT 24
Peak memory 200352 kb
Host smart-a669fc8e-af3c-4e77-94c8-523d1b42f400
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288609396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.2288609396
Directory /workspace/25.uart_stress_all/latest

Test location /workspace/coverage/default/25.uart_stress_all_with_rand_reset.30444233
Short name T718
Test name
Test status
Simulation time 186872552512 ps
CPU time 237.83 seconds
Started Jun 10 05:13:54 PM PDT 24
Finished Jun 10 05:17:53 PM PDT 24
Peak memory 216780 kb
Host smart-0a80e742-d689-48c0-8d0e-d6aa079c1a13
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30444233 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 25.uart_stress_all_with_rand_reset.30444233
Directory /workspace/25.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.uart_tx_ovrd.2494197661
Short name T779
Test name
Test status
Simulation time 631680606 ps
CPU time 2.36 seconds
Started Jun 10 05:13:55 PM PDT 24
Finished Jun 10 05:13:58 PM PDT 24
Peak memory 199028 kb
Host smart-0c7677ac-885f-4590-a0a8-e3f512ccd554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494197661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.2494197661
Directory /workspace/25.uart_tx_ovrd/latest

Test location /workspace/coverage/default/25.uart_tx_rx.1766508467
Short name T463
Test name
Test status
Simulation time 40465862582 ps
CPU time 33.15 seconds
Started Jun 10 05:13:52 PM PDT 24
Finished Jun 10 05:14:26 PM PDT 24
Peak memory 200244 kb
Host smart-6fee1111-5fb5-486e-b48c-746df29e0b3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766508467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.1766508467
Directory /workspace/25.uart_tx_rx/latest

Test location /workspace/coverage/default/250.uart_fifo_reset.3051584630
Short name T637
Test name
Test status
Simulation time 42461933420 ps
CPU time 22.28 seconds
Started Jun 10 05:16:02 PM PDT 24
Finished Jun 10 05:16:25 PM PDT 24
Peak memory 200356 kb
Host smart-2152805c-5751-4ab2-b6d8-6d791baf1c4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051584630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.3051584630
Directory /workspace/250.uart_fifo_reset/latest

Test location /workspace/coverage/default/251.uart_fifo_reset.4158223009
Short name T440
Test name
Test status
Simulation time 186924027285 ps
CPU time 75.55 seconds
Started Jun 10 05:15:59 PM PDT 24
Finished Jun 10 05:17:15 PM PDT 24
Peak memory 200312 kb
Host smart-f9362c95-388c-4f64-8ffb-16107a2b4104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158223009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.4158223009
Directory /workspace/251.uart_fifo_reset/latest

Test location /workspace/coverage/default/253.uart_fifo_reset.3213654084
Short name T560
Test name
Test status
Simulation time 218452061103 ps
CPU time 123.31 seconds
Started Jun 10 05:16:00 PM PDT 24
Finished Jun 10 05:18:03 PM PDT 24
Peak memory 200232 kb
Host smart-481a0e01-4f12-4ed5-9b4c-c689befbbf77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213654084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.3213654084
Directory /workspace/253.uart_fifo_reset/latest

Test location /workspace/coverage/default/254.uart_fifo_reset.717561997
Short name T683
Test name
Test status
Simulation time 44982819904 ps
CPU time 44.52 seconds
Started Jun 10 05:15:59 PM PDT 24
Finished Jun 10 05:16:43 PM PDT 24
Peak memory 200308 kb
Host smart-5c1ec4fc-059b-4722-8522-1b9bfd45900a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717561997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.717561997
Directory /workspace/254.uart_fifo_reset/latest

Test location /workspace/coverage/default/255.uart_fifo_reset.2841690991
Short name T890
Test name
Test status
Simulation time 99485203949 ps
CPU time 159.11 seconds
Started Jun 10 05:16:00 PM PDT 24
Finished Jun 10 05:18:39 PM PDT 24
Peak memory 200352 kb
Host smart-8de1be2d-cad5-4973-a67d-ac601f2f96dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841690991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.2841690991
Directory /workspace/255.uart_fifo_reset/latest

Test location /workspace/coverage/default/256.uart_fifo_reset.2868347051
Short name T210
Test name
Test status
Simulation time 107858182769 ps
CPU time 30.82 seconds
Started Jun 10 05:15:59 PM PDT 24
Finished Jun 10 05:16:30 PM PDT 24
Peak memory 200180 kb
Host smart-2e4efc6c-aa02-40ad-a5bc-9e50ecd1b470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868347051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.2868347051
Directory /workspace/256.uart_fifo_reset/latest

Test location /workspace/coverage/default/258.uart_fifo_reset.76038354
Short name T194
Test name
Test status
Simulation time 75455420437 ps
CPU time 43.52 seconds
Started Jun 10 05:16:00 PM PDT 24
Finished Jun 10 05:16:43 PM PDT 24
Peak memory 200336 kb
Host smart-46f19c04-7279-4e68-acbb-0ed9ed5c31ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76038354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.76038354
Directory /workspace/258.uart_fifo_reset/latest

Test location /workspace/coverage/default/259.uart_fifo_reset.2186009384
Short name T551
Test name
Test status
Simulation time 57401121633 ps
CPU time 95.16 seconds
Started Jun 10 05:16:04 PM PDT 24
Finished Jun 10 05:17:39 PM PDT 24
Peak memory 200356 kb
Host smart-f349b2f9-5924-4fd5-bc26-40fcfb2bbbe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186009384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.2186009384
Directory /workspace/259.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_alert_test.3634623749
Short name T477
Test name
Test status
Simulation time 138623510 ps
CPU time 0.58 seconds
Started Jun 10 05:14:00 PM PDT 24
Finished Jun 10 05:14:01 PM PDT 24
Peak memory 195620 kb
Host smart-3de73d66-935c-4237-a813-645e918228f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634623749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.3634623749
Directory /workspace/26.uart_alert_test/latest

Test location /workspace/coverage/default/26.uart_fifo_full.2951324380
Short name T170
Test name
Test status
Simulation time 263040498170 ps
CPU time 169.13 seconds
Started Jun 10 05:13:54 PM PDT 24
Finished Jun 10 05:16:44 PM PDT 24
Peak memory 200384 kb
Host smart-276bb99e-c5f3-47c8-8d11-5df21d8ef1c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951324380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.2951324380
Directory /workspace/26.uart_fifo_full/latest

Test location /workspace/coverage/default/26.uart_fifo_reset.217284657
Short name T66
Test name
Test status
Simulation time 119834286909 ps
CPU time 65.74 seconds
Started Jun 10 05:13:54 PM PDT 24
Finished Jun 10 05:15:01 PM PDT 24
Peak memory 200204 kb
Host smart-67c18a5c-7ce5-4011-befe-3b164a652a30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217284657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.217284657
Directory /workspace/26.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_intr.3149252866
Short name T594
Test name
Test status
Simulation time 44743776178 ps
CPU time 20.19 seconds
Started Jun 10 05:13:51 PM PDT 24
Finished Jun 10 05:14:11 PM PDT 24
Peak memory 200380 kb
Host smart-00507b76-5306-4025-91d9-2ef15de16f0b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149252866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.3149252866
Directory /workspace/26.uart_intr/latest

Test location /workspace/coverage/default/26.uart_long_xfer_wo_dly.584501494
Short name T1062
Test name
Test status
Simulation time 74936157834 ps
CPU time 231.3 seconds
Started Jun 10 05:13:47 PM PDT 24
Finished Jun 10 05:17:39 PM PDT 24
Peak memory 200224 kb
Host smart-903e207d-61c0-4fea-8684-39c608d5374a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=584501494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.584501494
Directory /workspace/26.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/26.uart_loopback.682890292
Short name T1053
Test name
Test status
Simulation time 2547565764 ps
CPU time 3.82 seconds
Started Jun 10 05:13:55 PM PDT 24
Finished Jun 10 05:13:59 PM PDT 24
Peak memory 198860 kb
Host smart-5c8359ff-7405-4d46-8cc2-f113726fc54b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682890292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_loopback.682890292
Directory /workspace/26.uart_loopback/latest

Test location /workspace/coverage/default/26.uart_noise_filter.2828835111
Short name T983
Test name
Test status
Simulation time 23577941223 ps
CPU time 9.78 seconds
Started Jun 10 05:13:55 PM PDT 24
Finished Jun 10 05:14:05 PM PDT 24
Peak memory 197780 kb
Host smart-d2a62b99-d1e7-48d8-b03a-915bf8e99a2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828835111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_noise_filter.2828835111
Directory /workspace/26.uart_noise_filter/latest

Test location /workspace/coverage/default/26.uart_perf.2386995871
Short name T733
Test name
Test status
Simulation time 1974481551 ps
CPU time 23.75 seconds
Started Jun 10 05:13:50 PM PDT 24
Finished Jun 10 05:14:14 PM PDT 24
Peak memory 200240 kb
Host smart-f9e271ad-37c0-4dfb-b843-90449867300e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2386995871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.2386995871
Directory /workspace/26.uart_perf/latest

Test location /workspace/coverage/default/26.uart_rx_oversample.1153120670
Short name T540
Test name
Test status
Simulation time 5628746417 ps
CPU time 13.41 seconds
Started Jun 10 05:13:49 PM PDT 24
Finished Jun 10 05:14:02 PM PDT 24
Peak memory 198584 kb
Host smart-e0a3aee4-b50a-46a1-9140-16403a7aea0b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1153120670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.1153120670
Directory /workspace/26.uart_rx_oversample/latest

Test location /workspace/coverage/default/26.uart_rx_start_bit_filter.1568769925
Short name T371
Test name
Test status
Simulation time 1451984454 ps
CPU time 1.17 seconds
Started Jun 10 05:13:51 PM PDT 24
Finished Jun 10 05:13:53 PM PDT 24
Peak memory 195832 kb
Host smart-836c64f2-f422-4a7b-986e-6037e795bde9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568769925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.1568769925
Directory /workspace/26.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/26.uart_smoke.1287597310
Short name T291
Test name
Test status
Simulation time 10535066593 ps
CPU time 23.08 seconds
Started Jun 10 05:14:03 PM PDT 24
Finished Jun 10 05:14:26 PM PDT 24
Peak memory 199884 kb
Host smart-0586c9ef-92a9-4c41-8545-357bfed74744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287597310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_smoke.1287597310
Directory /workspace/26.uart_smoke/latest

Test location /workspace/coverage/default/26.uart_tx_ovrd.1183145010
Short name T515
Test name
Test status
Simulation time 940486739 ps
CPU time 4.88 seconds
Started Jun 10 05:13:50 PM PDT 24
Finished Jun 10 05:13:55 PM PDT 24
Peak memory 199964 kb
Host smart-e4ad7353-c866-486c-8bfd-8f9bb81ee9e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183145010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.1183145010
Directory /workspace/26.uart_tx_ovrd/latest

Test location /workspace/coverage/default/26.uart_tx_rx.2467468562
Short name T361
Test name
Test status
Simulation time 12987070574 ps
CPU time 22.26 seconds
Started Jun 10 05:13:55 PM PDT 24
Finished Jun 10 05:14:17 PM PDT 24
Peak memory 197844 kb
Host smart-8336c166-ae2a-44d6-a8c1-eb9effb445de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467468562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.2467468562
Directory /workspace/26.uart_tx_rx/latest

Test location /workspace/coverage/default/260.uart_fifo_reset.220333197
Short name T621
Test name
Test status
Simulation time 135358036508 ps
CPU time 52.03 seconds
Started Jun 10 05:16:05 PM PDT 24
Finished Jun 10 05:16:58 PM PDT 24
Peak memory 200368 kb
Host smart-e33da198-db6a-4172-8421-0ab895b2e43a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220333197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.220333197
Directory /workspace/260.uart_fifo_reset/latest

Test location /workspace/coverage/default/261.uart_fifo_reset.3946957615
Short name T940
Test name
Test status
Simulation time 69069712781 ps
CPU time 8 seconds
Started Jun 10 05:16:03 PM PDT 24
Finished Jun 10 05:16:11 PM PDT 24
Peak memory 200476 kb
Host smart-235162f4-70bf-467f-9970-092d7119ee3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946957615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.3946957615
Directory /workspace/261.uart_fifo_reset/latest

Test location /workspace/coverage/default/262.uart_fifo_reset.1183324798
Short name T1048
Test name
Test status
Simulation time 37726592816 ps
CPU time 68.04 seconds
Started Jun 10 05:16:13 PM PDT 24
Finished Jun 10 05:17:21 PM PDT 24
Peak memory 200320 kb
Host smart-a5c50272-0878-4809-8095-7ef4c3e3c439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183324798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.1183324798
Directory /workspace/262.uart_fifo_reset/latest

Test location /workspace/coverage/default/263.uart_fifo_reset.1182111411
Short name T905
Test name
Test status
Simulation time 24914725399 ps
CPU time 21.01 seconds
Started Jun 10 05:16:03 PM PDT 24
Finished Jun 10 05:16:24 PM PDT 24
Peak memory 200232 kb
Host smart-66a961d1-00eb-4c76-8ab5-45299a98e375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182111411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.1182111411
Directory /workspace/263.uart_fifo_reset/latest

Test location /workspace/coverage/default/264.uart_fifo_reset.1142427656
Short name T727
Test name
Test status
Simulation time 229096034128 ps
CPU time 84.28 seconds
Started Jun 10 05:16:03 PM PDT 24
Finished Jun 10 05:17:28 PM PDT 24
Peak memory 200316 kb
Host smart-868fc976-6ed2-4dfe-800d-d706333d4833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142427656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.1142427656
Directory /workspace/264.uart_fifo_reset/latest

Test location /workspace/coverage/default/265.uart_fifo_reset.3477723979
Short name T209
Test name
Test status
Simulation time 14991429068 ps
CPU time 25.99 seconds
Started Jun 10 05:16:05 PM PDT 24
Finished Jun 10 05:16:32 PM PDT 24
Peak memory 200360 kb
Host smart-a63da3fc-f7cf-48f3-924f-6f34702bea84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477723979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.3477723979
Directory /workspace/265.uart_fifo_reset/latest

Test location /workspace/coverage/default/267.uart_fifo_reset.3822274113
Short name T994
Test name
Test status
Simulation time 204415107268 ps
CPU time 110.08 seconds
Started Jun 10 05:16:06 PM PDT 24
Finished Jun 10 05:17:57 PM PDT 24
Peak memory 200252 kb
Host smart-d73dcbef-9cb3-4dbd-a46d-43c81323f0b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822274113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.3822274113
Directory /workspace/267.uart_fifo_reset/latest

Test location /workspace/coverage/default/268.uart_fifo_reset.1990285575
Short name T1041
Test name
Test status
Simulation time 60160031790 ps
CPU time 44.95 seconds
Started Jun 10 05:16:07 PM PDT 24
Finished Jun 10 05:16:52 PM PDT 24
Peak memory 200284 kb
Host smart-3ac9236c-9ad5-41cb-8819-af3232e7355c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990285575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.1990285575
Directory /workspace/268.uart_fifo_reset/latest

Test location /workspace/coverage/default/269.uart_fifo_reset.2890583707
Short name T631
Test name
Test status
Simulation time 96961851593 ps
CPU time 145.62 seconds
Started Jun 10 05:16:10 PM PDT 24
Finished Jun 10 05:18:36 PM PDT 24
Peak memory 200272 kb
Host smart-6953bfbe-4d77-43dc-85df-6f26eb34cbbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890583707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.2890583707
Directory /workspace/269.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_alert_test.2736640361
Short name T356
Test name
Test status
Simulation time 23718548 ps
CPU time 0.56 seconds
Started Jun 10 05:13:54 PM PDT 24
Finished Jun 10 05:13:55 PM PDT 24
Peak memory 195760 kb
Host smart-c60cc609-cb32-4467-ac9b-e7549eae0944
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736640361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.2736640361
Directory /workspace/27.uart_alert_test/latest

Test location /workspace/coverage/default/27.uart_fifo_full.2052263128
Short name T853
Test name
Test status
Simulation time 276736068696 ps
CPU time 182.08 seconds
Started Jun 10 05:14:03 PM PDT 24
Finished Jun 10 05:17:06 PM PDT 24
Peak memory 200352 kb
Host smart-75ec1c52-90c6-4d80-b15d-0a0928a9e984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052263128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.2052263128
Directory /workspace/27.uart_fifo_full/latest

Test location /workspace/coverage/default/27.uart_fifo_overflow.3541626685
Short name T819
Test name
Test status
Simulation time 214783595397 ps
CPU time 290.88 seconds
Started Jun 10 05:13:58 PM PDT 24
Finished Jun 10 05:18:49 PM PDT 24
Peak memory 200284 kb
Host smart-c6d22331-ac3c-4536-a9ff-be2e2ce13e44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541626685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.3541626685
Directory /workspace/27.uart_fifo_overflow/latest

Test location /workspace/coverage/default/27.uart_fifo_reset.268950279
Short name T307
Test name
Test status
Simulation time 25854795871 ps
CPU time 11.33 seconds
Started Jun 10 05:14:04 PM PDT 24
Finished Jun 10 05:14:15 PM PDT 24
Peak memory 200324 kb
Host smart-de3bb18e-bc71-4e13-abba-5cbacf5e515a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268950279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.268950279
Directory /workspace/27.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_intr.4164939409
Short name T818
Test name
Test status
Simulation time 24988274221 ps
CPU time 11.76 seconds
Started Jun 10 05:14:02 PM PDT 24
Finished Jun 10 05:14:14 PM PDT 24
Peak memory 200296 kb
Host smart-acf53e54-f291-4e59-ac91-2a163ce7e0df
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164939409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.4164939409
Directory /workspace/27.uart_intr/latest

Test location /workspace/coverage/default/27.uart_long_xfer_wo_dly.2734779556
Short name T768
Test name
Test status
Simulation time 105134265742 ps
CPU time 486.65 seconds
Started Jun 10 05:13:56 PM PDT 24
Finished Jun 10 05:22:03 PM PDT 24
Peak memory 200440 kb
Host smart-a71f386a-770a-4db1-9e09-9cb6e2f8853e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2734779556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.2734779556
Directory /workspace/27.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/27.uart_loopback.203236660
Short name T9
Test name
Test status
Simulation time 8291274441 ps
CPU time 10 seconds
Started Jun 10 05:14:08 PM PDT 24
Finished Jun 10 05:14:18 PM PDT 24
Peak memory 200284 kb
Host smart-9323f87b-f403-4d96-8629-7a6561fb35bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203236660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_loopback.203236660
Directory /workspace/27.uart_loopback/latest

Test location /workspace/coverage/default/27.uart_perf.4228035070
Short name T866
Test name
Test status
Simulation time 10952854191 ps
CPU time 578.86 seconds
Started Jun 10 05:14:07 PM PDT 24
Finished Jun 10 05:23:46 PM PDT 24
Peak memory 200204 kb
Host smart-f6133b7c-dbda-4251-879a-540b85b2ec91
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4228035070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.4228035070
Directory /workspace/27.uart_perf/latest

Test location /workspace/coverage/default/27.uart_rx_oversample.1334641649
Short name T399
Test name
Test status
Simulation time 5253750146 ps
CPU time 41.77 seconds
Started Jun 10 05:14:09 PM PDT 24
Finished Jun 10 05:14:51 PM PDT 24
Peak memory 198700 kb
Host smart-ded0f412-5438-4239-908d-624bfe4605d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1334641649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.1334641649
Directory /workspace/27.uart_rx_oversample/latest

Test location /workspace/coverage/default/27.uart_rx_parity_err.3210082987
Short name T433
Test name
Test status
Simulation time 73609961531 ps
CPU time 11.39 seconds
Started Jun 10 05:14:09 PM PDT 24
Finished Jun 10 05:14:21 PM PDT 24
Peak memory 200324 kb
Host smart-722a156a-2ba2-4e4d-bcb1-7e21257b5157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210082987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.3210082987
Directory /workspace/27.uart_rx_parity_err/latest

Test location /workspace/coverage/default/27.uart_rx_start_bit_filter.3275253383
Short name T695
Test name
Test status
Simulation time 2227808404 ps
CPU time 1.61 seconds
Started Jun 10 05:13:55 PM PDT 24
Finished Jun 10 05:13:57 PM PDT 24
Peak memory 195700 kb
Host smart-29f94350-cae9-4588-9cfb-7d89a79964f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275253383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.3275253383
Directory /workspace/27.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/27.uart_smoke.1214944832
Short name T123
Test name
Test status
Simulation time 933942002 ps
CPU time 3.53 seconds
Started Jun 10 05:13:59 PM PDT 24
Finished Jun 10 05:14:03 PM PDT 24
Peak memory 198528 kb
Host smart-7fda828c-d53d-4905-8ec4-d590b039de10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214944832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_smoke.1214944832
Directory /workspace/27.uart_smoke/latest

Test location /workspace/coverage/default/27.uart_stress_all.3337135264
Short name T497
Test name
Test status
Simulation time 166358500291 ps
CPU time 262.31 seconds
Started Jun 10 05:14:04 PM PDT 24
Finished Jun 10 05:18:27 PM PDT 24
Peak memory 200408 kb
Host smart-941b8491-2611-4ee0-893e-ef30396e4bf6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337135264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.3337135264
Directory /workspace/27.uart_stress_all/latest

Test location /workspace/coverage/default/27.uart_stress_all_with_rand_reset.3735869622
Short name T840
Test name
Test status
Simulation time 48213389890 ps
CPU time 257.82 seconds
Started Jun 10 05:14:05 PM PDT 24
Finished Jun 10 05:18:24 PM PDT 24
Peak memory 216796 kb
Host smart-5e70c429-538b-49d6-8c13-210742a767c3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735869622 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 27.uart_stress_all_with_rand_reset.3735869622
Directory /workspace/27.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.uart_tx_ovrd.419262411
Short name T884
Test name
Test status
Simulation time 1197839569 ps
CPU time 4.43 seconds
Started Jun 10 05:13:58 PM PDT 24
Finished Jun 10 05:14:03 PM PDT 24
Peak memory 199276 kb
Host smart-e607534c-3084-4891-a27b-21ea2deb960c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419262411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.419262411
Directory /workspace/27.uart_tx_ovrd/latest

Test location /workspace/coverage/default/27.uart_tx_rx.545483614
Short name T46
Test name
Test status
Simulation time 56529030878 ps
CPU time 96.94 seconds
Started Jun 10 05:14:04 PM PDT 24
Finished Jun 10 05:15:41 PM PDT 24
Peak memory 200240 kb
Host smart-2a2a7bc9-7515-4f56-b414-9dfcb44cb469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545483614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.545483614
Directory /workspace/27.uart_tx_rx/latest

Test location /workspace/coverage/default/271.uart_fifo_reset.3966687692
Short name T811
Test name
Test status
Simulation time 28962612293 ps
CPU time 24.61 seconds
Started Jun 10 05:16:10 PM PDT 24
Finished Jun 10 05:16:35 PM PDT 24
Peak memory 200256 kb
Host smart-c602da6f-9e7c-4fe8-b54f-7cd9cd6d0b02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966687692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.3966687692
Directory /workspace/271.uart_fifo_reset/latest

Test location /workspace/coverage/default/272.uart_fifo_reset.391221880
Short name T641
Test name
Test status
Simulation time 273304619866 ps
CPU time 124.76 seconds
Started Jun 10 05:16:22 PM PDT 24
Finished Jun 10 05:18:27 PM PDT 24
Peak memory 200280 kb
Host smart-fa9efd71-ecdb-4b20-8a70-3c82a11805cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391221880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.391221880
Directory /workspace/272.uart_fifo_reset/latest

Test location /workspace/coverage/default/273.uart_fifo_reset.2626566800
Short name T1046
Test name
Test status
Simulation time 412619792993 ps
CPU time 57.78 seconds
Started Jun 10 05:16:12 PM PDT 24
Finished Jun 10 05:17:11 PM PDT 24
Peak memory 200192 kb
Host smart-223d5b2f-1930-4dae-af9c-aa8f5f98f30b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626566800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.2626566800
Directory /workspace/273.uart_fifo_reset/latest

Test location /workspace/coverage/default/274.uart_fifo_reset.400549604
Short name T150
Test name
Test status
Simulation time 105611375302 ps
CPU time 159.19 seconds
Started Jun 10 05:16:08 PM PDT 24
Finished Jun 10 05:18:48 PM PDT 24
Peak memory 200252 kb
Host smart-eb0f06b5-c6b9-471b-8c17-83d39e976c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400549604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.400549604
Directory /workspace/274.uart_fifo_reset/latest

Test location /workspace/coverage/default/275.uart_fifo_reset.1943143361
Short name T548
Test name
Test status
Simulation time 48011210748 ps
CPU time 79.23 seconds
Started Jun 10 05:16:12 PM PDT 24
Finished Jun 10 05:17:32 PM PDT 24
Peak memory 200308 kb
Host smart-343529d5-f0ec-47aa-8ba5-a64dc4806289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943143361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.1943143361
Directory /workspace/275.uart_fifo_reset/latest

Test location /workspace/coverage/default/277.uart_fifo_reset.171699799
Short name T187
Test name
Test status
Simulation time 60572826574 ps
CPU time 46.71 seconds
Started Jun 10 05:16:10 PM PDT 24
Finished Jun 10 05:16:57 PM PDT 24
Peak memory 200360 kb
Host smart-a939ddf9-598d-4b5c-9a52-0f7b0182b37f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171699799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.171699799
Directory /workspace/277.uart_fifo_reset/latest

Test location /workspace/coverage/default/278.uart_fifo_reset.2912544557
Short name T292
Test name
Test status
Simulation time 101991109148 ps
CPU time 165.66 seconds
Started Jun 10 05:16:09 PM PDT 24
Finished Jun 10 05:18:54 PM PDT 24
Peak memory 200352 kb
Host smart-66e3eb21-738c-4ddb-b14d-9e0fd99b698b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912544557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.2912544557
Directory /workspace/278.uart_fifo_reset/latest

Test location /workspace/coverage/default/279.uart_fifo_reset.756239634
Short name T460
Test name
Test status
Simulation time 102358224125 ps
CPU time 203.69 seconds
Started Jun 10 05:16:19 PM PDT 24
Finished Jun 10 05:19:43 PM PDT 24
Peak memory 200316 kb
Host smart-f59ce1c9-f8a9-4e74-81e8-13ab1d6c9ba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756239634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.756239634
Directory /workspace/279.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_alert_test.1307817210
Short name T1033
Test name
Test status
Simulation time 14024734 ps
CPU time 0.59 seconds
Started Jun 10 05:14:03 PM PDT 24
Finished Jun 10 05:14:04 PM PDT 24
Peak memory 196012 kb
Host smart-1f651ad8-e57f-448c-9dc9-0dd1a867ada8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307817210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.1307817210
Directory /workspace/28.uart_alert_test/latest

Test location /workspace/coverage/default/28.uart_fifo_full.4285581899
Short name T1030
Test name
Test status
Simulation time 124004270913 ps
CPU time 169.91 seconds
Started Jun 10 05:13:56 PM PDT 24
Finished Jun 10 05:16:47 PM PDT 24
Peak memory 200320 kb
Host smart-33a01793-0bba-47ba-944a-e5736d9a3a3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285581899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.4285581899
Directory /workspace/28.uart_fifo_full/latest

Test location /workspace/coverage/default/28.uart_fifo_overflow.748154491
Short name T163
Test name
Test status
Simulation time 113927541822 ps
CPU time 112.41 seconds
Started Jun 10 05:13:57 PM PDT 24
Finished Jun 10 05:15:50 PM PDT 24
Peak memory 200340 kb
Host smart-0adf0155-664c-42df-bbd7-76bdcfbee1a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748154491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.748154491
Directory /workspace/28.uart_fifo_overflow/latest

Test location /workspace/coverage/default/28.uart_fifo_reset.2012516236
Short name T739
Test name
Test status
Simulation time 161869090904 ps
CPU time 54.74 seconds
Started Jun 10 05:14:00 PM PDT 24
Finished Jun 10 05:14:55 PM PDT 24
Peak memory 200308 kb
Host smart-04d289e3-3e31-49d4-aed6-473b2a1972fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012516236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.2012516236
Directory /workspace/28.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_intr.2246472679
Short name T262
Test name
Test status
Simulation time 49309405720 ps
CPU time 58.57 seconds
Started Jun 10 05:14:06 PM PDT 24
Finished Jun 10 05:15:05 PM PDT 24
Peak memory 200228 kb
Host smart-e8ad20dc-b962-4f2c-8ca8-3c1290a4e8b7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246472679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.2246472679
Directory /workspace/28.uart_intr/latest

Test location /workspace/coverage/default/28.uart_long_xfer_wo_dly.3002511436
Short name T427
Test name
Test status
Simulation time 143439517417 ps
CPU time 482.17 seconds
Started Jun 10 05:14:12 PM PDT 24
Finished Jun 10 05:22:15 PM PDT 24
Peak memory 200240 kb
Host smart-a80474d0-a49b-467d-8c36-4097ffa2eaef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3002511436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.3002511436
Directory /workspace/28.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/28.uart_loopback.3721926892
Short name T429
Test name
Test status
Simulation time 1597778107 ps
CPU time 2.18 seconds
Started Jun 10 05:14:08 PM PDT 24
Finished Jun 10 05:14:10 PM PDT 24
Peak memory 196444 kb
Host smart-c1fbba18-4d14-42a9-97d3-fcb09fdd26d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721926892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_loopback.3721926892
Directory /workspace/28.uart_loopback/latest

Test location /workspace/coverage/default/28.uart_perf.4010023907
Short name T948
Test name
Test status
Simulation time 4476660717 ps
CPU time 176.76 seconds
Started Jun 10 05:14:09 PM PDT 24
Finished Jun 10 05:17:06 PM PDT 24
Peak memory 200268 kb
Host smart-6c0cddb7-210c-4a41-b13d-a20b71f1bf0c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4010023907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.4010023907
Directory /workspace/28.uart_perf/latest

Test location /workspace/coverage/default/28.uart_rx_oversample.3701104402
Short name T925
Test name
Test status
Simulation time 7281791557 ps
CPU time 64.34 seconds
Started Jun 10 05:14:06 PM PDT 24
Finished Jun 10 05:15:10 PM PDT 24
Peak memory 198488 kb
Host smart-5a3365d5-f1e7-43f5-b47a-5cced02ed305
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3701104402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.3701104402
Directory /workspace/28.uart_rx_oversample/latest

Test location /workspace/coverage/default/28.uart_rx_parity_err.3103520445
Short name T142
Test name
Test status
Simulation time 117733238125 ps
CPU time 54.58 seconds
Started Jun 10 05:14:05 PM PDT 24
Finished Jun 10 05:15:00 PM PDT 24
Peak memory 200236 kb
Host smart-26a1e751-4b2e-4a6b-8971-379507728b60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103520445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.3103520445
Directory /workspace/28.uart_rx_parity_err/latest

Test location /workspace/coverage/default/28.uart_rx_start_bit_filter.2926300432
Short name T965
Test name
Test status
Simulation time 41756228247 ps
CPU time 18.27 seconds
Started Jun 10 05:14:04 PM PDT 24
Finished Jun 10 05:14:22 PM PDT 24
Peak memory 196364 kb
Host smart-1d892f3b-4e31-419f-9cbf-3623079ae140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926300432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.2926300432
Directory /workspace/28.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/28.uart_smoke.3352652229
Short name T646
Test name
Test status
Simulation time 720587867 ps
CPU time 1.31 seconds
Started Jun 10 05:14:04 PM PDT 24
Finished Jun 10 05:14:05 PM PDT 24
Peak memory 198996 kb
Host smart-0f98beea-7cc6-4d00-9905-953828171bd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352652229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_smoke.3352652229
Directory /workspace/28.uart_smoke/latest

Test location /workspace/coverage/default/28.uart_stress_all.443664986
Short name T834
Test name
Test status
Simulation time 457343567476 ps
CPU time 652.15 seconds
Started Jun 10 05:13:56 PM PDT 24
Finished Jun 10 05:24:49 PM PDT 24
Peak memory 200324 kb
Host smart-c4234afb-6295-4305-bc79-17fa12223afb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443664986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.443664986
Directory /workspace/28.uart_stress_all/latest

Test location /workspace/coverage/default/28.uart_stress_all_with_rand_reset.2777406018
Short name T580
Test name
Test status
Simulation time 111570022299 ps
CPU time 293.15 seconds
Started Jun 10 05:14:03 PM PDT 24
Finished Jun 10 05:18:57 PM PDT 24
Peak memory 216880 kb
Host smart-13386d34-9d4c-4539-9f07-1c9a16d7223d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777406018 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 28.uart_stress_all_with_rand_reset.2777406018
Directory /workspace/28.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.uart_tx_ovrd.3593486252
Short name T723
Test name
Test status
Simulation time 1153422420 ps
CPU time 3.99 seconds
Started Jun 10 05:13:54 PM PDT 24
Finished Jun 10 05:13:59 PM PDT 24
Peak memory 198708 kb
Host smart-ba0e9a14-3951-45bb-9f00-03808911bb68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593486252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.3593486252
Directory /workspace/28.uart_tx_ovrd/latest

Test location /workspace/coverage/default/28.uart_tx_rx.2472188785
Short name T516
Test name
Test status
Simulation time 32435462963 ps
CPU time 48 seconds
Started Jun 10 05:13:53 PM PDT 24
Finished Jun 10 05:14:42 PM PDT 24
Peak memory 200336 kb
Host smart-6862e98e-a828-4529-9e2c-63fdc6883b14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472188785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.2472188785
Directory /workspace/28.uart_tx_rx/latest

Test location /workspace/coverage/default/280.uart_fifo_reset.562235677
Short name T1042
Test name
Test status
Simulation time 55024348539 ps
CPU time 83.12 seconds
Started Jun 10 05:16:12 PM PDT 24
Finished Jun 10 05:17:36 PM PDT 24
Peak memory 200392 kb
Host smart-6c025922-1134-410c-ac66-82c5e3ef7579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562235677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.562235677
Directory /workspace/280.uart_fifo_reset/latest

Test location /workspace/coverage/default/281.uart_fifo_reset.1455206355
Short name T232
Test name
Test status
Simulation time 22318170446 ps
CPU time 38.02 seconds
Started Jun 10 05:16:17 PM PDT 24
Finished Jun 10 05:16:56 PM PDT 24
Peak memory 200360 kb
Host smart-b2bfa955-1b4f-47df-bac5-ba9b30f53273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455206355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.1455206355
Directory /workspace/281.uart_fifo_reset/latest

Test location /workspace/coverage/default/282.uart_fifo_reset.477474341
Short name T334
Test name
Test status
Simulation time 75000602961 ps
CPU time 33.58 seconds
Started Jun 10 05:16:13 PM PDT 24
Finished Jun 10 05:16:47 PM PDT 24
Peak memory 200240 kb
Host smart-7bd25667-cf43-41e1-95d4-7164e534d337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477474341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.477474341
Directory /workspace/282.uart_fifo_reset/latest

Test location /workspace/coverage/default/283.uart_fifo_reset.1591065320
Short name T110
Test name
Test status
Simulation time 23554794373 ps
CPU time 10.86 seconds
Started Jun 10 05:16:12 PM PDT 24
Finished Jun 10 05:16:24 PM PDT 24
Peak memory 200292 kb
Host smart-307febad-d0db-4a8a-a939-6d22c9cfef3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591065320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.1591065320
Directory /workspace/283.uart_fifo_reset/latest

Test location /workspace/coverage/default/284.uart_fifo_reset.3947995351
Short name T189
Test name
Test status
Simulation time 160074370172 ps
CPU time 71.15 seconds
Started Jun 10 05:16:14 PM PDT 24
Finished Jun 10 05:17:25 PM PDT 24
Peak memory 200220 kb
Host smart-ad54d775-60cb-4cb9-8f20-64071da93568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947995351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.3947995351
Directory /workspace/284.uart_fifo_reset/latest

Test location /workspace/coverage/default/285.uart_fifo_reset.1539345984
Short name T556
Test name
Test status
Simulation time 19023757714 ps
CPU time 14.99 seconds
Started Jun 10 05:16:14 PM PDT 24
Finished Jun 10 05:16:30 PM PDT 24
Peak memory 200360 kb
Host smart-f8e636f3-5d5f-472b-86aa-b79935633de6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539345984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.1539345984
Directory /workspace/285.uart_fifo_reset/latest

Test location /workspace/coverage/default/286.uart_fifo_reset.99528802
Short name T236
Test name
Test status
Simulation time 58164476954 ps
CPU time 23.85 seconds
Started Jun 10 05:16:10 PM PDT 24
Finished Jun 10 05:16:34 PM PDT 24
Peak memory 200188 kb
Host smart-59c57ed5-f88f-4065-81fe-8b3109155ea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99528802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.99528802
Directory /workspace/286.uart_fifo_reset/latest

Test location /workspace/coverage/default/287.uart_fifo_reset.4092401968
Short name T47
Test name
Test status
Simulation time 137727925460 ps
CPU time 127.53 seconds
Started Jun 10 05:16:19 PM PDT 24
Finished Jun 10 05:18:27 PM PDT 24
Peak memory 200320 kb
Host smart-517aea5c-2dfd-4f32-8046-c87cfae16183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092401968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.4092401968
Directory /workspace/287.uart_fifo_reset/latest

Test location /workspace/coverage/default/288.uart_fifo_reset.2141263478
Short name T1055
Test name
Test status
Simulation time 57513261478 ps
CPU time 25.03 seconds
Started Jun 10 05:16:09 PM PDT 24
Finished Jun 10 05:16:35 PM PDT 24
Peak memory 199896 kb
Host smart-f9a3118f-2ae8-45d0-9d59-6d58fb3cf042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141263478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.2141263478
Directory /workspace/288.uart_fifo_reset/latest

Test location /workspace/coverage/default/289.uart_fifo_reset.2307195692
Short name T713
Test name
Test status
Simulation time 82475068665 ps
CPU time 37.25 seconds
Started Jun 10 05:16:13 PM PDT 24
Finished Jun 10 05:16:51 PM PDT 24
Peak memory 200148 kb
Host smart-912e4e1e-ec0d-471e-984d-719b33649109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307195692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.2307195692
Directory /workspace/289.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_alert_test.2980206817
Short name T387
Test name
Test status
Simulation time 14605737 ps
CPU time 0.55 seconds
Started Jun 10 05:14:12 PM PDT 24
Finished Jun 10 05:14:12 PM PDT 24
Peak memory 195976 kb
Host smart-4e0dcf43-156c-4df0-92d0-d492fca4b10b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980206817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.2980206817
Directory /workspace/29.uart_alert_test/latest

Test location /workspace/coverage/default/29.uart_fifo_full.3451852423
Short name T795
Test name
Test status
Simulation time 104986618403 ps
CPU time 69.91 seconds
Started Jun 10 05:14:09 PM PDT 24
Finished Jun 10 05:15:19 PM PDT 24
Peak memory 200356 kb
Host smart-5eb0cf53-61d7-4fc8-9822-8fe90eba533d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451852423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.3451852423
Directory /workspace/29.uart_fifo_full/latest

Test location /workspace/coverage/default/29.uart_fifo_reset.2687341020
Short name T447
Test name
Test status
Simulation time 42347322716 ps
CPU time 13.59 seconds
Started Jun 10 05:14:05 PM PDT 24
Finished Jun 10 05:14:19 PM PDT 24
Peak memory 200352 kb
Host smart-ce711c15-ed95-40e8-b04c-13ee88d0a4db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687341020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.2687341020
Directory /workspace/29.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_intr.12610414
Short name T547
Test name
Test status
Simulation time 12793223238 ps
CPU time 11.3 seconds
Started Jun 10 05:14:04 PM PDT 24
Finished Jun 10 05:14:15 PM PDT 24
Peak memory 197860 kb
Host smart-121e3766-1892-4f11-92bc-679aa5c37e62
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12610414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.12610414
Directory /workspace/29.uart_intr/latest

Test location /workspace/coverage/default/29.uart_long_xfer_wo_dly.2777774568
Short name T69
Test name
Test status
Simulation time 82435175070 ps
CPU time 293.59 seconds
Started Jun 10 05:14:09 PM PDT 24
Finished Jun 10 05:19:03 PM PDT 24
Peak memory 200304 kb
Host smart-0bbe0579-2ac6-4a85-a82f-161c63d28b46
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2777774568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.2777774568
Directory /workspace/29.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/29.uart_loopback.952758745
Short name T662
Test name
Test status
Simulation time 1497651575 ps
CPU time 3.02 seconds
Started Jun 10 05:14:09 PM PDT 24
Finished Jun 10 05:14:13 PM PDT 24
Peak memory 198736 kb
Host smart-2a06a7cd-37d3-422c-838c-559be4148d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952758745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_loopback.952758745
Directory /workspace/29.uart_loopback/latest

Test location /workspace/coverage/default/29.uart_perf.582876183
Short name T740
Test name
Test status
Simulation time 29120661016 ps
CPU time 98.86 seconds
Started Jun 10 05:14:08 PM PDT 24
Finished Jun 10 05:15:47 PM PDT 24
Peak memory 200216 kb
Host smart-3e74246e-b79c-45af-bb4b-6446220df842
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=582876183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.582876183
Directory /workspace/29.uart_perf/latest

Test location /workspace/coverage/default/29.uart_rx_oversample.241619153
Short name T973
Test name
Test status
Simulation time 7222829892 ps
CPU time 30.8 seconds
Started Jun 10 05:14:05 PM PDT 24
Finished Jun 10 05:14:36 PM PDT 24
Peak memory 198560 kb
Host smart-66d9664f-dffb-4359-8b7f-4465d357586e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=241619153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.241619153
Directory /workspace/29.uart_rx_oversample/latest

Test location /workspace/coverage/default/29.uart_rx_parity_err.1530710984
Short name T870
Test name
Test status
Simulation time 33123906610 ps
CPU time 52.92 seconds
Started Jun 10 05:14:07 PM PDT 24
Finished Jun 10 05:15:01 PM PDT 24
Peak memory 198840 kb
Host smart-7796c0d4-84fc-4af4-95bd-34094df3454c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530710984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.1530710984
Directory /workspace/29.uart_rx_parity_err/latest

Test location /workspace/coverage/default/29.uart_rx_start_bit_filter.2572394990
Short name T379
Test name
Test status
Simulation time 27120004520 ps
CPU time 5.2 seconds
Started Jun 10 05:13:55 PM PDT 24
Finished Jun 10 05:14:00 PM PDT 24
Peak memory 196164 kb
Host smart-967f0bfe-ba67-4612-b485-1adc743292c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572394990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.2572394990
Directory /workspace/29.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/29.uart_smoke.152835955
Short name T938
Test name
Test status
Simulation time 147504661 ps
CPU time 0.86 seconds
Started Jun 10 05:14:07 PM PDT 24
Finished Jun 10 05:14:08 PM PDT 24
Peak memory 197916 kb
Host smart-8454c7c2-8fe4-449c-8ed0-814d2d88cdcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152835955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_smoke.152835955
Directory /workspace/29.uart_smoke/latest

Test location /workspace/coverage/default/29.uart_stress_all.1574768305
Short name T947
Test name
Test status
Simulation time 11381774022 ps
CPU time 138.71 seconds
Started Jun 10 05:14:10 PM PDT 24
Finished Jun 10 05:16:29 PM PDT 24
Peak memory 200272 kb
Host smart-34b223ad-e14c-4de1-b137-595bf0faa9f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574768305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.1574768305
Directory /workspace/29.uart_stress_all/latest

Test location /workspace/coverage/default/29.uart_stress_all_with_rand_reset.924102138
Short name T345
Test name
Test status
Simulation time 45299917816 ps
CPU time 217.36 seconds
Started Jun 10 05:14:10 PM PDT 24
Finished Jun 10 05:17:47 PM PDT 24
Peak memory 216460 kb
Host smart-276938bc-8cb0-4ba9-8d37-d5cbe2fa7430
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924102138 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 29.uart_stress_all_with_rand_reset.924102138
Directory /workspace/29.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.uart_tx_ovrd.1449692624
Short name T576
Test name
Test status
Simulation time 1307575230 ps
CPU time 4.29 seconds
Started Jun 10 05:14:03 PM PDT 24
Finished Jun 10 05:14:08 PM PDT 24
Peak memory 200124 kb
Host smart-0e27def6-d3d5-443f-bb6c-afa0d58b1d51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449692624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.1449692624
Directory /workspace/29.uart_tx_ovrd/latest

Test location /workspace/coverage/default/29.uart_tx_rx.654983901
Short name T753
Test name
Test status
Simulation time 121063033313 ps
CPU time 62.59 seconds
Started Jun 10 05:13:59 PM PDT 24
Finished Jun 10 05:15:02 PM PDT 24
Peak memory 200308 kb
Host smart-880d062f-1898-4e6c-881d-42cb4f105506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654983901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.654983901
Directory /workspace/29.uart_tx_rx/latest

Test location /workspace/coverage/default/290.uart_fifo_reset.3764618870
Short name T217
Test name
Test status
Simulation time 58377797088 ps
CPU time 54.47 seconds
Started Jun 10 05:16:13 PM PDT 24
Finished Jun 10 05:17:08 PM PDT 24
Peak memory 200276 kb
Host smart-84bf7246-206a-4454-b471-5485ecfb0494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764618870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.3764618870
Directory /workspace/290.uart_fifo_reset/latest

Test location /workspace/coverage/default/291.uart_fifo_reset.905360855
Short name T226
Test name
Test status
Simulation time 8371134363 ps
CPU time 14.86 seconds
Started Jun 10 05:16:13 PM PDT 24
Finished Jun 10 05:16:28 PM PDT 24
Peak memory 200324 kb
Host smart-78c0710f-9bd8-49ad-afa3-156a3f66cc86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905360855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.905360855
Directory /workspace/291.uart_fifo_reset/latest

Test location /workspace/coverage/default/292.uart_fifo_reset.3216808240
Short name T562
Test name
Test status
Simulation time 46229244726 ps
CPU time 81.95 seconds
Started Jun 10 05:16:16 PM PDT 24
Finished Jun 10 05:17:38 PM PDT 24
Peak memory 200360 kb
Host smart-ed258e51-94e0-481b-84c6-ffba9248d7c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216808240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.3216808240
Directory /workspace/292.uart_fifo_reset/latest

Test location /workspace/coverage/default/293.uart_fifo_reset.1749659254
Short name T1066
Test name
Test status
Simulation time 55810905145 ps
CPU time 22.5 seconds
Started Jun 10 05:16:14 PM PDT 24
Finished Jun 10 05:16:37 PM PDT 24
Peak memory 200268 kb
Host smart-a3a7990d-5bc5-499b-b920-b7db7a0a0430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749659254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.1749659254
Directory /workspace/293.uart_fifo_reset/latest

Test location /workspace/coverage/default/294.uart_fifo_reset.3844711983
Short name T724
Test name
Test status
Simulation time 266196431347 ps
CPU time 136.97 seconds
Started Jun 10 05:16:13 PM PDT 24
Finished Jun 10 05:18:30 PM PDT 24
Peak memory 200024 kb
Host smart-ae502276-102d-42d2-aecd-1bf458dc4bbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844711983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.3844711983
Directory /workspace/294.uart_fifo_reset/latest

Test location /workspace/coverage/default/295.uart_fifo_reset.1398839577
Short name T454
Test name
Test status
Simulation time 34407461734 ps
CPU time 15.7 seconds
Started Jun 10 05:16:19 PM PDT 24
Finished Jun 10 05:16:35 PM PDT 24
Peak memory 200356 kb
Host smart-28051a84-05e7-4e3f-804d-4d26c399a5ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398839577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.1398839577
Directory /workspace/295.uart_fifo_reset/latest

Test location /workspace/coverage/default/296.uart_fifo_reset.4272252457
Short name T826
Test name
Test status
Simulation time 8738101942 ps
CPU time 12.85 seconds
Started Jun 10 05:16:14 PM PDT 24
Finished Jun 10 05:16:28 PM PDT 24
Peak memory 199988 kb
Host smart-f9303f3b-9d6c-4685-91ab-25a71f41eb1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272252457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.4272252457
Directory /workspace/296.uart_fifo_reset/latest

Test location /workspace/coverage/default/297.uart_fifo_reset.3996591978
Short name T892
Test name
Test status
Simulation time 83448774859 ps
CPU time 62.16 seconds
Started Jun 10 05:16:12 PM PDT 24
Finished Jun 10 05:17:15 PM PDT 24
Peak memory 200264 kb
Host smart-199e2569-f9c1-4ba4-b37c-2f115dec09ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996591978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.3996591978
Directory /workspace/297.uart_fifo_reset/latest

Test location /workspace/coverage/default/298.uart_fifo_reset.40365992
Short name T479
Test name
Test status
Simulation time 12714747463 ps
CPU time 22.45 seconds
Started Jun 10 05:16:12 PM PDT 24
Finished Jun 10 05:16:35 PM PDT 24
Peak memory 200380 kb
Host smart-6d7fbbbe-5699-4812-9502-f15c5896a454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40365992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.40365992
Directory /workspace/298.uart_fifo_reset/latest

Test location /workspace/coverage/default/299.uart_fifo_reset.3180977306
Short name T722
Test name
Test status
Simulation time 107447471354 ps
CPU time 57.85 seconds
Started Jun 10 05:16:14 PM PDT 24
Finished Jun 10 05:17:13 PM PDT 24
Peak memory 200300 kb
Host smart-ba6f259e-0758-4fe2-92e8-7ab6b0234102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180977306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.3180977306
Directory /workspace/299.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_alert_test.3964505479
Short name T958
Test name
Test status
Simulation time 29910324 ps
CPU time 0.63 seconds
Started Jun 10 05:12:56 PM PDT 24
Finished Jun 10 05:12:57 PM PDT 24
Peak memory 195720 kb
Host smart-afcbecbe-7978-4be0-8d8c-aa5985d63760
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964505479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.3964505479
Directory /workspace/3.uart_alert_test/latest

Test location /workspace/coverage/default/3.uart_fifo_full.2557901727
Short name T591
Test name
Test status
Simulation time 26402201290 ps
CPU time 15.05 seconds
Started Jun 10 05:12:49 PM PDT 24
Finished Jun 10 05:13:05 PM PDT 24
Peak memory 200224 kb
Host smart-3850458b-df46-4383-8875-08ec0bebbe88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557901727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.2557901727
Directory /workspace/3.uart_fifo_full/latest

Test location /workspace/coverage/default/3.uart_fifo_overflow.2260911500
Short name T426
Test name
Test status
Simulation time 23710825075 ps
CPU time 14.81 seconds
Started Jun 10 05:12:45 PM PDT 24
Finished Jun 10 05:13:01 PM PDT 24
Peak memory 200312 kb
Host smart-28c31c53-e153-4fdb-b524-52c4b1ad9ce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260911500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.2260911500
Directory /workspace/3.uart_fifo_overflow/latest

Test location /workspace/coverage/default/3.uart_fifo_reset.341128224
Short name T199
Test name
Test status
Simulation time 39812504221 ps
CPU time 87.62 seconds
Started Jun 10 05:12:52 PM PDT 24
Finished Jun 10 05:14:20 PM PDT 24
Peak memory 200312 kb
Host smart-5de4eb44-2174-4edf-9525-e82c687b0f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341128224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.341128224
Directory /workspace/3.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_intr.2787988245
Short name T788
Test name
Test status
Simulation time 48412856807 ps
CPU time 92.17 seconds
Started Jun 10 05:12:51 PM PDT 24
Finished Jun 10 05:14:23 PM PDT 24
Peak memory 200236 kb
Host smart-d2393831-6bae-41c9-aebf-f2962569c885
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787988245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.2787988245
Directory /workspace/3.uart_intr/latest

Test location /workspace/coverage/default/3.uart_long_xfer_wo_dly.4268250872
Short name T542
Test name
Test status
Simulation time 65377358149 ps
CPU time 180.46 seconds
Started Jun 10 05:12:52 PM PDT 24
Finished Jun 10 05:15:53 PM PDT 24
Peak memory 200384 kb
Host smart-bbc2513f-e850-4953-ae4f-a6cb05a71ed4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4268250872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.4268250872
Directory /workspace/3.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/3.uart_loopback.3325343592
Short name T369
Test name
Test status
Simulation time 951459684 ps
CPU time 2.21 seconds
Started Jun 10 05:12:51 PM PDT 24
Finished Jun 10 05:12:54 PM PDT 24
Peak memory 196216 kb
Host smart-f1096666-e43c-4695-9f8f-83282b4ae6fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325343592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_loopback.3325343592
Directory /workspace/3.uart_loopback/latest

Test location /workspace/coverage/default/3.uart_perf.2346279570
Short name T344
Test name
Test status
Simulation time 6928539445 ps
CPU time 65.35 seconds
Started Jun 10 05:12:52 PM PDT 24
Finished Jun 10 05:13:58 PM PDT 24
Peak memory 200268 kb
Host smart-d328921b-373c-42bc-9f95-75a665039747
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2346279570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.2346279570
Directory /workspace/3.uart_perf/latest

Test location /workspace/coverage/default/3.uart_rx_oversample.2721674338
Short name T982
Test name
Test status
Simulation time 7030448194 ps
CPU time 63.69 seconds
Started Jun 10 05:12:53 PM PDT 24
Finished Jun 10 05:13:57 PM PDT 24
Peak memory 198524 kb
Host smart-97f11b66-7a00-4a46-96e7-6cd3248b840a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2721674338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.2721674338
Directory /workspace/3.uart_rx_oversample/latest

Test location /workspace/coverage/default/3.uart_rx_parity_err.4239458097
Short name T510
Test name
Test status
Simulation time 200970960274 ps
CPU time 87.87 seconds
Started Jun 10 05:12:52 PM PDT 24
Finished Jun 10 05:14:20 PM PDT 24
Peak memory 200308 kb
Host smart-a5ea247b-d123-4492-8504-36e0fe6beacb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239458097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.4239458097
Directory /workspace/3.uart_rx_parity_err/latest

Test location /workspace/coverage/default/3.uart_rx_start_bit_filter.14734376
Short name T588
Test name
Test status
Simulation time 49818085834 ps
CPU time 20.15 seconds
Started Jun 10 05:12:50 PM PDT 24
Finished Jun 10 05:13:11 PM PDT 24
Peak memory 196316 kb
Host smart-1801e5c6-bf61-4e6c-9752-96e2a7af46e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14734376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.14734376
Directory /workspace/3.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/3.uart_sec_cm.2383389331
Short name T102
Test name
Test status
Simulation time 440073292 ps
CPU time 0.93 seconds
Started Jun 10 05:12:54 PM PDT 24
Finished Jun 10 05:12:55 PM PDT 24
Peak memory 218684 kb
Host smart-f95a0e4b-c0b0-41a7-8345-4db2dd3ac616
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383389331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.2383389331
Directory /workspace/3.uart_sec_cm/latest

Test location /workspace/coverage/default/3.uart_smoke.4048304267
Short name T803
Test name
Test status
Simulation time 501294642 ps
CPU time 1.94 seconds
Started Jun 10 05:12:51 PM PDT 24
Finished Jun 10 05:12:53 PM PDT 24
Peak memory 199124 kb
Host smart-37606417-4de8-4f3f-a2ec-eded05dd2348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048304267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_smoke.4048304267
Directory /workspace/3.uart_smoke/latest

Test location /workspace/coverage/default/3.uart_stress_all.667183398
Short name T590
Test name
Test status
Simulation time 136847172609 ps
CPU time 170.32 seconds
Started Jun 10 05:12:49 PM PDT 24
Finished Jun 10 05:15:39 PM PDT 24
Peak memory 200360 kb
Host smart-aa49c47e-dcf1-46b1-ad59-9324a6d68e56
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667183398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.667183398
Directory /workspace/3.uart_stress_all/latest

Test location /workspace/coverage/default/3.uart_stress_all_with_rand_reset.2601802822
Short name T115
Test name
Test status
Simulation time 19503504332 ps
CPU time 171.91 seconds
Started Jun 10 05:12:51 PM PDT 24
Finished Jun 10 05:15:44 PM PDT 24
Peak memory 208772 kb
Host smart-c17d76ed-a44f-4eb3-a3e5-040284dc1d1b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601802822 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.uart_stress_all_with_rand_reset.2601802822
Directory /workspace/3.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.uart_tx_ovrd.2235480816
Short name T439
Test name
Test status
Simulation time 7141329567 ps
CPU time 13.36 seconds
Started Jun 10 05:12:51 PM PDT 24
Finished Jun 10 05:13:04 PM PDT 24
Peak memory 199844 kb
Host smart-b3233813-7711-4050-af3d-3013855bee42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235480816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.2235480816
Directory /workspace/3.uart_tx_ovrd/latest

Test location /workspace/coverage/default/3.uart_tx_rx.1159258724
Short name T717
Test name
Test status
Simulation time 63699805350 ps
CPU time 37.63 seconds
Started Jun 10 05:12:48 PM PDT 24
Finished Jun 10 05:13:26 PM PDT 24
Peak memory 200364 kb
Host smart-bee18862-5f60-4405-b2ce-dbf0378a74e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159258724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.1159258724
Directory /workspace/3.uart_tx_rx/latest

Test location /workspace/coverage/default/30.uart_alert_test.124639704
Short name T368
Test name
Test status
Simulation time 13782689 ps
CPU time 0.59 seconds
Started Jun 10 05:14:13 PM PDT 24
Finished Jun 10 05:14:14 PM PDT 24
Peak memory 195940 kb
Host smart-fe1cffac-4680-47fb-95b5-ef1083c2d14c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124639704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.124639704
Directory /workspace/30.uart_alert_test/latest

Test location /workspace/coverage/default/30.uart_fifo_full.1200685667
Short name T760
Test name
Test status
Simulation time 40479310052 ps
CPU time 16.96 seconds
Started Jun 10 05:14:12 PM PDT 24
Finished Jun 10 05:14:29 PM PDT 24
Peak memory 200328 kb
Host smart-5cacf0c1-8bd3-413f-837d-9cca155d6ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200685667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.1200685667
Directory /workspace/30.uart_fifo_full/latest

Test location /workspace/coverage/default/30.uart_fifo_overflow.3426695855
Short name T634
Test name
Test status
Simulation time 229773247246 ps
CPU time 323.18 seconds
Started Jun 10 05:14:09 PM PDT 24
Finished Jun 10 05:19:33 PM PDT 24
Peak memory 200384 kb
Host smart-f031a822-0763-4e02-8119-76923d5f1bde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426695855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.3426695855
Directory /workspace/30.uart_fifo_overflow/latest

Test location /workspace/coverage/default/30.uart_intr.3177726318
Short name T265
Test name
Test status
Simulation time 178106752678 ps
CPU time 338.46 seconds
Started Jun 10 05:14:11 PM PDT 24
Finished Jun 10 05:19:50 PM PDT 24
Peak memory 200264 kb
Host smart-93897214-094a-4a38-b11e-6874dbfc6b53
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177726318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.3177726318
Directory /workspace/30.uart_intr/latest

Test location /workspace/coverage/default/30.uart_long_xfer_wo_dly.2803057534
Short name T1082
Test name
Test status
Simulation time 64032949570 ps
CPU time 480.37 seconds
Started Jun 10 05:14:00 PM PDT 24
Finished Jun 10 05:22:00 PM PDT 24
Peak memory 200304 kb
Host smart-40d12b77-835d-4074-a227-62196804df80
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2803057534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.2803057534
Directory /workspace/30.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/30.uart_loopback.1463252348
Short name T375
Test name
Test status
Simulation time 3031531557 ps
CPU time 2.75 seconds
Started Jun 10 05:14:05 PM PDT 24
Finished Jun 10 05:14:08 PM PDT 24
Peak memory 199064 kb
Host smart-2109c237-e5cd-490a-9e1b-325b3258583e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463252348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_loopback.1463252348
Directory /workspace/30.uart_loopback/latest

Test location /workspace/coverage/default/30.uart_perf.1753187177
Short name T652
Test name
Test status
Simulation time 7059031430 ps
CPU time 380.58 seconds
Started Jun 10 05:14:10 PM PDT 24
Finished Jun 10 05:20:31 PM PDT 24
Peak memory 200264 kb
Host smart-df5c86c8-81b3-49dc-b574-eef01d1211e2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1753187177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.1753187177
Directory /workspace/30.uart_perf/latest

Test location /workspace/coverage/default/30.uart_rx_oversample.4128292539
Short name T417
Test name
Test status
Simulation time 4245596089 ps
CPU time 31.7 seconds
Started Jun 10 05:14:07 PM PDT 24
Finished Jun 10 05:14:40 PM PDT 24
Peak memory 198992 kb
Host smart-ffb6ca0a-ac15-4bd7-95c5-5eb234dfe819
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4128292539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.4128292539
Directory /workspace/30.uart_rx_oversample/latest

Test location /workspace/coverage/default/30.uart_rx_parity_err.1425160664
Short name T517
Test name
Test status
Simulation time 130635219679 ps
CPU time 60.2 seconds
Started Jun 10 05:14:14 PM PDT 24
Finished Jun 10 05:15:15 PM PDT 24
Peak memory 200208 kb
Host smart-37889317-2c66-452d-bb4f-8169528fde87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425160664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.1425160664
Directory /workspace/30.uart_rx_parity_err/latest

Test location /workspace/coverage/default/30.uart_rx_start_bit_filter.4069874059
Short name T397
Test name
Test status
Simulation time 32858490582 ps
CPU time 47.17 seconds
Started Jun 10 05:14:04 PM PDT 24
Finished Jun 10 05:14:52 PM PDT 24
Peak memory 196352 kb
Host smart-cebbb5d6-2bd1-47fd-9b80-105e5574cfe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069874059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.4069874059
Directory /workspace/30.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/30.uart_smoke.2135449689
Short name T1084
Test name
Test status
Simulation time 802346443 ps
CPU time 2.97 seconds
Started Jun 10 05:14:09 PM PDT 24
Finished Jun 10 05:14:13 PM PDT 24
Peak memory 200084 kb
Host smart-1346bb3b-df28-49cb-b90e-259a14f7d62f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135449689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_smoke.2135449689
Directory /workspace/30.uart_smoke/latest

Test location /workspace/coverage/default/30.uart_stress_all.2189439036
Short name T1025
Test name
Test status
Simulation time 215137012828 ps
CPU time 90.39 seconds
Started Jun 10 05:14:03 PM PDT 24
Finished Jun 10 05:15:33 PM PDT 24
Peak memory 198612 kb
Host smart-972826c9-7fc0-422a-babc-651620236b9c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189439036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.2189439036
Directory /workspace/30.uart_stress_all/latest

Test location /workspace/coverage/default/30.uart_tx_ovrd.62619353
Short name T589
Test name
Test status
Simulation time 880414461 ps
CPU time 1.69 seconds
Started Jun 10 05:14:09 PM PDT 24
Finished Jun 10 05:14:11 PM PDT 24
Peak memory 200200 kb
Host smart-f8799ec2-2b87-4f0b-a4c0-b58832b26f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62619353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.62619353
Directory /workspace/30.uart_tx_ovrd/latest

Test location /workspace/coverage/default/30.uart_tx_rx.3699268907
Short name T504
Test name
Test status
Simulation time 35971995913 ps
CPU time 65.41 seconds
Started Jun 10 05:14:13 PM PDT 24
Finished Jun 10 05:15:19 PM PDT 24
Peak memory 200312 kb
Host smart-5cec4b20-24d9-4daf-9636-b916ac9dab5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699268907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.3699268907
Directory /workspace/30.uart_tx_rx/latest

Test location /workspace/coverage/default/31.uart_alert_test.2798248429
Short name T364
Test name
Test status
Simulation time 23150763 ps
CPU time 0.58 seconds
Started Jun 10 05:14:07 PM PDT 24
Finished Jun 10 05:14:08 PM PDT 24
Peak memory 195912 kb
Host smart-6145e229-60e0-49ef-aed4-9ec3f6e79392
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798248429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.2798248429
Directory /workspace/31.uart_alert_test/latest

Test location /workspace/coverage/default/31.uart_fifo_full.92762178
Short name T443
Test name
Test status
Simulation time 324981014351 ps
CPU time 152.82 seconds
Started Jun 10 05:14:11 PM PDT 24
Finished Jun 10 05:16:44 PM PDT 24
Peak memory 200304 kb
Host smart-e9d90c3b-04b9-4573-b7fc-81f65bb939f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92762178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.92762178
Directory /workspace/31.uart_fifo_full/latest

Test location /workspace/coverage/default/31.uart_fifo_overflow.3986834742
Short name T318
Test name
Test status
Simulation time 36670289208 ps
CPU time 16.17 seconds
Started Jun 10 05:14:05 PM PDT 24
Finished Jun 10 05:14:22 PM PDT 24
Peak memory 198348 kb
Host smart-88da72b2-6c05-40fc-83b4-5195ca843fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986834742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.3986834742
Directory /workspace/31.uart_fifo_overflow/latest

Test location /workspace/coverage/default/31.uart_fifo_reset.691480505
Short name T112
Test name
Test status
Simulation time 140590252515 ps
CPU time 254.75 seconds
Started Jun 10 05:14:05 PM PDT 24
Finished Jun 10 05:18:20 PM PDT 24
Peak memory 200328 kb
Host smart-6504e033-1810-418d-8380-1e434c9e3b05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691480505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.691480505
Directory /workspace/31.uart_fifo_reset/latest

Test location /workspace/coverage/default/31.uart_intr.4210167267
Short name T1007
Test name
Test status
Simulation time 10601097381 ps
CPU time 5.24 seconds
Started Jun 10 05:14:07 PM PDT 24
Finished Jun 10 05:14:13 PM PDT 24
Peak memory 198060 kb
Host smart-fa00dadd-f2aa-4b87-88f2-4c3b14905ba3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210167267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.4210167267
Directory /workspace/31.uart_intr/latest

Test location /workspace/coverage/default/31.uart_long_xfer_wo_dly.438912232
Short name T844
Test name
Test status
Simulation time 118965240900 ps
CPU time 233.92 seconds
Started Jun 10 05:14:11 PM PDT 24
Finished Jun 10 05:18:05 PM PDT 24
Peak memory 200284 kb
Host smart-8fe7037c-6adb-457c-89b8-fc7da1f0e6dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=438912232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.438912232
Directory /workspace/31.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/31.uart_loopback.1043358906
Short name T358
Test name
Test status
Simulation time 2002260911 ps
CPU time 2.44 seconds
Started Jun 10 05:14:09 PM PDT 24
Finished Jun 10 05:14:12 PM PDT 24
Peak memory 198920 kb
Host smart-9a246582-efbf-4679-94f1-90b57ee0da5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043358906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_loopback.1043358906
Directory /workspace/31.uart_loopback/latest

Test location /workspace/coverage/default/31.uart_perf.1061449777
Short name T383
Test name
Test status
Simulation time 10491792546 ps
CPU time 560.22 seconds
Started Jun 10 05:14:08 PM PDT 24
Finished Jun 10 05:23:29 PM PDT 24
Peak memory 200256 kb
Host smart-e109e3e1-dd85-48af-adf1-f54440d92db3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1061449777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.1061449777
Directory /workspace/31.uart_perf/latest

Test location /workspace/coverage/default/31.uart_rx_oversample.1525078257
Short name T949
Test name
Test status
Simulation time 6598262451 ps
CPU time 13.74 seconds
Started Jun 10 05:14:12 PM PDT 24
Finished Jun 10 05:14:27 PM PDT 24
Peak memory 199348 kb
Host smart-0774d56d-c074-43ba-a1d4-1530e1dfac81
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1525078257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.1525078257
Directory /workspace/31.uart_rx_oversample/latest

Test location /workspace/coverage/default/31.uart_rx_parity_err.1169094781
Short name T529
Test name
Test status
Simulation time 132000964293 ps
CPU time 111.37 seconds
Started Jun 10 05:14:11 PM PDT 24
Finished Jun 10 05:16:02 PM PDT 24
Peak memory 200320 kb
Host smart-90a25c8c-179b-4744-ad04-81a20b2696f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169094781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.1169094781
Directory /workspace/31.uart_rx_parity_err/latest

Test location /workspace/coverage/default/31.uart_rx_start_bit_filter.3323483143
Short name T614
Test name
Test status
Simulation time 2762325529 ps
CPU time 5.16 seconds
Started Jun 10 05:14:10 PM PDT 24
Finished Jun 10 05:14:16 PM PDT 24
Peak memory 196784 kb
Host smart-aa3be003-0f02-4716-ae78-074ddfbc419b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323483143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.3323483143
Directory /workspace/31.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/31.uart_smoke.2762405628
Short name T907
Test name
Test status
Simulation time 6280064339 ps
CPU time 10.69 seconds
Started Jun 10 05:14:11 PM PDT 24
Finished Jun 10 05:14:22 PM PDT 24
Peak memory 200264 kb
Host smart-fa33597e-5630-43c7-8ef7-124d9ed30069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762405628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_smoke.2762405628
Directory /workspace/31.uart_smoke/latest

Test location /workspace/coverage/default/31.uart_stress_all_with_rand_reset.3118284136
Short name T106
Test name
Test status
Simulation time 24380838014 ps
CPU time 302.39 seconds
Started Jun 10 05:14:17 PM PDT 24
Finished Jun 10 05:19:20 PM PDT 24
Peak memory 216804 kb
Host smart-b05ea78c-2cbc-45f0-b1d6-7debac93b660
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118284136 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 31.uart_stress_all_with_rand_reset.3118284136
Directory /workspace/31.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.uart_tx_ovrd.309042557
Short name T18
Test name
Test status
Simulation time 7130099984 ps
CPU time 10.88 seconds
Started Jun 10 05:14:06 PM PDT 24
Finished Jun 10 05:14:17 PM PDT 24
Peak memory 200272 kb
Host smart-b122dec6-2523-4e59-8d84-ebed2c260286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309042557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.309042557
Directory /workspace/31.uart_tx_ovrd/latest

Test location /workspace/coverage/default/31.uart_tx_rx.721263297
Short name T336
Test name
Test status
Simulation time 47991733114 ps
CPU time 114.9 seconds
Started Jun 10 05:14:05 PM PDT 24
Finished Jun 10 05:16:00 PM PDT 24
Peak memory 200212 kb
Host smart-44a04aff-e2e9-48e0-ae43-e8b3861d3880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721263297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.721263297
Directory /workspace/31.uart_tx_rx/latest

Test location /workspace/coverage/default/32.uart_alert_test.4029505639
Short name T751
Test name
Test status
Simulation time 203138223 ps
CPU time 0.55 seconds
Started Jun 10 05:14:10 PM PDT 24
Finished Jun 10 05:14:11 PM PDT 24
Peak memory 195632 kb
Host smart-5adfae4c-ed9a-4b8e-aaf9-f886d9d33321
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029505639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.4029505639
Directory /workspace/32.uart_alert_test/latest

Test location /workspace/coverage/default/32.uart_fifo_overflow.2821535256
Short name T885
Test name
Test status
Simulation time 81304561672 ps
CPU time 34.52 seconds
Started Jun 10 05:14:14 PM PDT 24
Finished Jun 10 05:14:49 PM PDT 24
Peak memory 200152 kb
Host smart-9b390e7c-d38b-44a5-b9ec-5e3e987f9334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821535256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.2821535256
Directory /workspace/32.uart_fifo_overflow/latest

Test location /workspace/coverage/default/32.uart_fifo_reset.2586504296
Short name T762
Test name
Test status
Simulation time 12376664433 ps
CPU time 23.79 seconds
Started Jun 10 05:14:14 PM PDT 24
Finished Jun 10 05:14:38 PM PDT 24
Peak memory 200348 kb
Host smart-2fed7255-fd69-4979-bc15-108b6f691b08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586504296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.2586504296
Directory /workspace/32.uart_fifo_reset/latest

Test location /workspace/coverage/default/32.uart_intr.2029723043
Short name T1080
Test name
Test status
Simulation time 4515286459 ps
CPU time 2.19 seconds
Started Jun 10 05:14:11 PM PDT 24
Finished Jun 10 05:14:14 PM PDT 24
Peak memory 196192 kb
Host smart-0ab0665d-67a7-4045-892f-de61f2a1c413
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029723043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.2029723043
Directory /workspace/32.uart_intr/latest

Test location /workspace/coverage/default/32.uart_long_xfer_wo_dly.3902212325
Short name T470
Test name
Test status
Simulation time 34565456164 ps
CPU time 87.41 seconds
Started Jun 10 05:14:10 PM PDT 24
Finished Jun 10 05:15:38 PM PDT 24
Peak memory 200228 kb
Host smart-33beedc4-196f-49d6-8520-220568c531f3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3902212325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.3902212325
Directory /workspace/32.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/32.uart_loopback.2630878702
Short name T855
Test name
Test status
Simulation time 189405688 ps
CPU time 0.96 seconds
Started Jun 10 05:14:14 PM PDT 24
Finished Jun 10 05:14:15 PM PDT 24
Peak memory 198440 kb
Host smart-f33fadec-bb5d-4489-b2d5-21978b4a21df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630878702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_loopback.2630878702
Directory /workspace/32.uart_loopback/latest

Test location /workspace/coverage/default/32.uart_perf.674788385
Short name T689
Test name
Test status
Simulation time 28280535828 ps
CPU time 1693.45 seconds
Started Jun 10 05:14:19 PM PDT 24
Finished Jun 10 05:42:33 PM PDT 24
Peak memory 200148 kb
Host smart-4e7c4579-2f73-408e-9b11-45d39736461d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=674788385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.674788385
Directory /workspace/32.uart_perf/latest

Test location /workspace/coverage/default/32.uart_rx_oversample.3594926395
Short name T800
Test name
Test status
Simulation time 6439936082 ps
CPU time 13.08 seconds
Started Jun 10 05:14:16 PM PDT 24
Finished Jun 10 05:14:29 PM PDT 24
Peak memory 199584 kb
Host smart-55a44376-a097-47c1-a546-12fde62e4570
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3594926395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.3594926395
Directory /workspace/32.uart_rx_oversample/latest

Test location /workspace/coverage/default/32.uart_rx_start_bit_filter.3265463013
Short name T450
Test name
Test status
Simulation time 2807333369 ps
CPU time 2.94 seconds
Started Jun 10 05:14:09 PM PDT 24
Finished Jun 10 05:14:12 PM PDT 24
Peak memory 196144 kb
Host smart-1846dba2-7f86-4587-8c77-7ab377a70d5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265463013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.3265463013
Directory /workspace/32.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/32.uart_smoke.361236442
Short name T898
Test name
Test status
Simulation time 5832089353 ps
CPU time 12.85 seconds
Started Jun 10 05:14:09 PM PDT 24
Finished Jun 10 05:14:23 PM PDT 24
Peak memory 200208 kb
Host smart-eeb4ba76-7293-497d-a70d-b2b6a73056af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361236442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_smoke.361236442
Directory /workspace/32.uart_smoke/latest

Test location /workspace/coverage/default/32.uart_stress_all.3667014663
Short name T180
Test name
Test status
Simulation time 162890018491 ps
CPU time 284.32 seconds
Started Jun 10 05:14:21 PM PDT 24
Finished Jun 10 05:19:06 PM PDT 24
Peak memory 200288 kb
Host smart-4a6616d2-95c2-4564-af90-c2bebfbd4ba3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667014663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.3667014663
Directory /workspace/32.uart_stress_all/latest

Test location /workspace/coverage/default/32.uart_stress_all_with_rand_reset.841741749
Short name T974
Test name
Test status
Simulation time 9954449556 ps
CPU time 113.54 seconds
Started Jun 10 05:14:08 PM PDT 24
Finished Jun 10 05:16:02 PM PDT 24
Peak memory 216816 kb
Host smart-de825482-c5df-4fbd-ba3c-8574a4ec4d89
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841741749 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 32.uart_stress_all_with_rand_reset.841741749
Directory /workspace/32.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.uart_tx_ovrd.4001377283
Short name T771
Test name
Test status
Simulation time 6504789355 ps
CPU time 20.25 seconds
Started Jun 10 05:14:10 PM PDT 24
Finished Jun 10 05:14:31 PM PDT 24
Peak memory 200364 kb
Host smart-1f6c7f9a-7552-4b75-9d83-561780b0fa93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001377283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.4001377283
Directory /workspace/32.uart_tx_ovrd/latest

Test location /workspace/coverage/default/32.uart_tx_rx.1080826757
Short name T597
Test name
Test status
Simulation time 149309690396 ps
CPU time 23.48 seconds
Started Jun 10 05:14:14 PM PDT 24
Finished Jun 10 05:14:38 PM PDT 24
Peak memory 200308 kb
Host smart-13b0765d-14bc-44fd-91da-28281f6e6653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080826757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.1080826757
Directory /workspace/32.uart_tx_rx/latest

Test location /workspace/coverage/default/33.uart_alert_test.413240724
Short name T70
Test name
Test status
Simulation time 37108846 ps
CPU time 0.55 seconds
Started Jun 10 05:14:15 PM PDT 24
Finished Jun 10 05:14:16 PM PDT 24
Peak memory 195560 kb
Host smart-0f086b5b-c0ea-4290-b3e1-4848db98ec54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413240724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.413240724
Directory /workspace/33.uart_alert_test/latest

Test location /workspace/coverage/default/33.uart_fifo_full.3550357402
Short name T437
Test name
Test status
Simulation time 61675677254 ps
CPU time 24.95 seconds
Started Jun 10 05:14:08 PM PDT 24
Finished Jun 10 05:14:33 PM PDT 24
Peak memory 200224 kb
Host smart-e2802fc4-f275-4ad0-b788-f220e99898cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550357402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.3550357402
Directory /workspace/33.uart_fifo_full/latest

Test location /workspace/coverage/default/33.uart_fifo_overflow.3829934170
Short name T852
Test name
Test status
Simulation time 16958724620 ps
CPU time 28.25 seconds
Started Jun 10 05:14:12 PM PDT 24
Finished Jun 10 05:14:41 PM PDT 24
Peak memory 200320 kb
Host smart-5ff03d13-a13d-4608-9da8-9a12e8285a37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829934170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.3829934170
Directory /workspace/33.uart_fifo_overflow/latest

Test location /workspace/coverage/default/33.uart_fifo_reset.3595968353
Short name T782
Test name
Test status
Simulation time 111516861913 ps
CPU time 188.15 seconds
Started Jun 10 05:14:08 PM PDT 24
Finished Jun 10 05:17:16 PM PDT 24
Peak memory 200292 kb
Host smart-fddd7280-4631-44b3-ae1e-bcce55884a0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595968353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.3595968353
Directory /workspace/33.uart_fifo_reset/latest

Test location /workspace/coverage/default/33.uart_intr.3947520812
Short name T295
Test name
Test status
Simulation time 40815018296 ps
CPU time 12.12 seconds
Started Jun 10 05:14:19 PM PDT 24
Finished Jun 10 05:14:31 PM PDT 24
Peak memory 200196 kb
Host smart-0586fe19-2d4b-4d8f-9baa-ab037ae9d1fa
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947520812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.3947520812
Directory /workspace/33.uart_intr/latest

Test location /workspace/coverage/default/33.uart_long_xfer_wo_dly.2966989066
Short name T967
Test name
Test status
Simulation time 45154828574 ps
CPU time 72.15 seconds
Started Jun 10 05:14:22 PM PDT 24
Finished Jun 10 05:15:34 PM PDT 24
Peak memory 200340 kb
Host smart-b4161f6c-c456-4bb2-8535-7079d499cd01
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2966989066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.2966989066
Directory /workspace/33.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/33.uart_loopback.616085604
Short name T766
Test name
Test status
Simulation time 5726983366 ps
CPU time 7.15 seconds
Started Jun 10 05:14:11 PM PDT 24
Finished Jun 10 05:14:19 PM PDT 24
Peak memory 200256 kb
Host smart-4e950c3d-c581-4750-b9e5-ea15df9403db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616085604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_loopback.616085604
Directory /workspace/33.uart_loopback/latest

Test location /workspace/coverage/default/33.uart_perf.113636783
Short name T681
Test name
Test status
Simulation time 5745077621 ps
CPU time 246.65 seconds
Started Jun 10 05:14:09 PM PDT 24
Finished Jun 10 05:18:16 PM PDT 24
Peak memory 200300 kb
Host smart-679e890c-746e-41ec-ae14-c388da68176a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=113636783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.113636783
Directory /workspace/33.uart_perf/latest

Test location /workspace/coverage/default/33.uart_rx_oversample.1293312073
Short name T403
Test name
Test status
Simulation time 1392839501 ps
CPU time 1.06 seconds
Started Jun 10 05:14:07 PM PDT 24
Finished Jun 10 05:14:09 PM PDT 24
Peak memory 195928 kb
Host smart-80437c07-863e-421d-beeb-74fa8799bd91
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1293312073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.1293312073
Directory /workspace/33.uart_rx_oversample/latest

Test location /workspace/coverage/default/33.uart_rx_parity_err.3744527752
Short name T348
Test name
Test status
Simulation time 43661044567 ps
CPU time 21.11 seconds
Started Jun 10 05:14:11 PM PDT 24
Finished Jun 10 05:14:33 PM PDT 24
Peak memory 200304 kb
Host smart-6664f570-9b57-4fc9-b89d-485292b62402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744527752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.3744527752
Directory /workspace/33.uart_rx_parity_err/latest

Test location /workspace/coverage/default/33.uart_rx_start_bit_filter.3690012152
Short name T308
Test name
Test status
Simulation time 4154901536 ps
CPU time 3.86 seconds
Started Jun 10 05:14:09 PM PDT 24
Finished Jun 10 05:14:13 PM PDT 24
Peak memory 196828 kb
Host smart-bcd4a322-bd1a-47b8-9e8d-203e4b463138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690012152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.3690012152
Directory /workspace/33.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/33.uart_smoke.2284344440
Short name T302
Test name
Test status
Simulation time 106713297 ps
CPU time 0.73 seconds
Started Jun 10 05:14:20 PM PDT 24
Finished Jun 10 05:14:21 PM PDT 24
Peak memory 197264 kb
Host smart-4fea21d8-bec0-4b4a-a607-537489a79a38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284344440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_smoke.2284344440
Directory /workspace/33.uart_smoke/latest

Test location /workspace/coverage/default/33.uart_stress_all.400907
Short name T577
Test name
Test status
Simulation time 157009014863 ps
CPU time 240.91 seconds
Started Jun 10 05:14:22 PM PDT 24
Finished Jun 10 05:18:23 PM PDT 24
Peak memory 200272 kb
Host smart-d1a624bd-a545-49be-9dc8-1f74597646de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.400907
Directory /workspace/33.uart_stress_all/latest

Test location /workspace/coverage/default/33.uart_tx_ovrd.784819828
Short name T987
Test name
Test status
Simulation time 1208275390 ps
CPU time 2.82 seconds
Started Jun 10 05:14:14 PM PDT 24
Finished Jun 10 05:14:17 PM PDT 24
Peak memory 198968 kb
Host smart-af78c6f6-023d-4be0-bb8f-aa3fef2cd5e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784819828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.784819828
Directory /workspace/33.uart_tx_ovrd/latest

Test location /workspace/coverage/default/33.uart_tx_rx.1331893743
Short name T860
Test name
Test status
Simulation time 19535048443 ps
CPU time 16.15 seconds
Started Jun 10 05:14:12 PM PDT 24
Finished Jun 10 05:14:29 PM PDT 24
Peak memory 200392 kb
Host smart-a392b7ca-bea8-44cb-9fd4-fb7706d2178a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331893743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.1331893743
Directory /workspace/33.uart_tx_rx/latest

Test location /workspace/coverage/default/34.uart_alert_test.94951630
Short name T917
Test name
Test status
Simulation time 15073602 ps
CPU time 0.55 seconds
Started Jun 10 05:14:17 PM PDT 24
Finished Jun 10 05:14:18 PM PDT 24
Peak memory 195680 kb
Host smart-da9d928f-ad1e-43c0-aa8f-99b1fbd825d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94951630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.94951630
Directory /workspace/34.uart_alert_test/latest

Test location /workspace/coverage/default/34.uart_fifo_full.2965693579
Short name T496
Test name
Test status
Simulation time 28494030541 ps
CPU time 8.83 seconds
Started Jun 10 05:14:16 PM PDT 24
Finished Jun 10 05:14:25 PM PDT 24
Peak memory 199472 kb
Host smart-8ccbf271-70dd-4e1b-8a81-c657168d0422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965693579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.2965693579
Directory /workspace/34.uart_fifo_full/latest

Test location /workspace/coverage/default/34.uart_fifo_overflow.4271679585
Short name T1004
Test name
Test status
Simulation time 92001186881 ps
CPU time 179.88 seconds
Started Jun 10 05:14:19 PM PDT 24
Finished Jun 10 05:17:19 PM PDT 24
Peak memory 200236 kb
Host smart-faf18fa6-a4fb-46f9-88c9-b5baea2c1869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271679585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.4271679585
Directory /workspace/34.uart_fifo_overflow/latest

Test location /workspace/coverage/default/34.uart_fifo_reset.1846278781
Short name T253
Test name
Test status
Simulation time 17749778523 ps
CPU time 17.47 seconds
Started Jun 10 05:14:12 PM PDT 24
Finished Jun 10 05:14:30 PM PDT 24
Peak memory 200412 kb
Host smart-c59b87fa-5aa6-4402-87f7-8dc59bde725c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846278781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.1846278781
Directory /workspace/34.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_intr.488041489
Short name T685
Test name
Test status
Simulation time 211962386629 ps
CPU time 392.64 seconds
Started Jun 10 05:14:17 PM PDT 24
Finished Jun 10 05:20:50 PM PDT 24
Peak memory 200268 kb
Host smart-e21dc724-fa5c-48bf-a512-e152653edfa9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488041489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.488041489
Directory /workspace/34.uart_intr/latest

Test location /workspace/coverage/default/34.uart_long_xfer_wo_dly.3280318573
Short name T728
Test name
Test status
Simulation time 85453639099 ps
CPU time 321.66 seconds
Started Jun 10 05:14:21 PM PDT 24
Finished Jun 10 05:19:43 PM PDT 24
Peak memory 200188 kb
Host smart-0ff4849e-9057-46ff-9675-907ca1c6579c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3280318573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.3280318573
Directory /workspace/34.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/34.uart_loopback.845226085
Short name T353
Test name
Test status
Simulation time 4470183588 ps
CPU time 10.58 seconds
Started Jun 10 05:14:17 PM PDT 24
Finished Jun 10 05:14:28 PM PDT 24
Peak memory 199468 kb
Host smart-36413b8b-9789-4688-a7aa-b803e6d033b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845226085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_loopback.845226085
Directory /workspace/34.uart_loopback/latest

Test location /workspace/coverage/default/34.uart_perf.1443447330
Short name T861
Test name
Test status
Simulation time 16555873363 ps
CPU time 851.97 seconds
Started Jun 10 05:14:17 PM PDT 24
Finished Jun 10 05:28:30 PM PDT 24
Peak memory 200224 kb
Host smart-883591de-423c-448e-82aa-4557ede6d6a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1443447330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.1443447330
Directory /workspace/34.uart_perf/latest

Test location /workspace/coverage/default/34.uart_rx_oversample.778739154
Short name T1009
Test name
Test status
Simulation time 5480290185 ps
CPU time 11.96 seconds
Started Jun 10 05:14:15 PM PDT 24
Finished Jun 10 05:14:27 PM PDT 24
Peak memory 199376 kb
Host smart-6d885145-09f1-423e-b994-7a29d791996c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=778739154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.778739154
Directory /workspace/34.uart_rx_oversample/latest

Test location /workspace/coverage/default/34.uart_rx_parity_err.2223276906
Short name T579
Test name
Test status
Simulation time 100227762099 ps
CPU time 79.08 seconds
Started Jun 10 05:14:18 PM PDT 24
Finished Jun 10 05:15:37 PM PDT 24
Peak memory 200348 kb
Host smart-9e25cae0-84fa-495d-a5dd-a16c1638538e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223276906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.2223276906
Directory /workspace/34.uart_rx_parity_err/latest

Test location /workspace/coverage/default/34.uart_rx_start_bit_filter.3486622273
Short name T385
Test name
Test status
Simulation time 3553696142 ps
CPU time 6.73 seconds
Started Jun 10 05:14:16 PM PDT 24
Finished Jun 10 05:14:23 PM PDT 24
Peak memory 196652 kb
Host smart-48ef3cf6-cb01-4adf-8840-fca858ca2d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486622273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.3486622273
Directory /workspace/34.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/34.uart_smoke.3883637060
Short name T275
Test name
Test status
Simulation time 11595016885 ps
CPU time 13.36 seconds
Started Jun 10 05:14:21 PM PDT 24
Finished Jun 10 05:14:34 PM PDT 24
Peak memory 200136 kb
Host smart-ddb4f7b8-7e2a-40d7-a9ad-b0dc394875d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883637060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_smoke.3883637060
Directory /workspace/34.uart_smoke/latest

Test location /workspace/coverage/default/34.uart_stress_all.2018064894
Short name T185
Test name
Test status
Simulation time 322410913909 ps
CPU time 320.46 seconds
Started Jun 10 05:14:21 PM PDT 24
Finished Jun 10 05:19:42 PM PDT 24
Peak memory 200300 kb
Host smart-06ba31eb-970e-4b2b-b3b6-eb410c1f65db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018064894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.2018064894
Directory /workspace/34.uart_stress_all/latest

Test location /workspace/coverage/default/34.uart_tx_ovrd.1392918268
Short name T1081
Test name
Test status
Simulation time 9918040544 ps
CPU time 2.35 seconds
Started Jun 10 05:14:17 PM PDT 24
Finished Jun 10 05:14:19 PM PDT 24
Peak memory 199540 kb
Host smart-e0e7bb43-76e7-467d-87f5-c901d4a2d7bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392918268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.1392918268
Directory /workspace/34.uart_tx_ovrd/latest

Test location /workspace/coverage/default/34.uart_tx_rx.1661401023
Short name T395
Test name
Test status
Simulation time 61160018699 ps
CPU time 16.2 seconds
Started Jun 10 05:14:15 PM PDT 24
Finished Jun 10 05:14:32 PM PDT 24
Peak memory 199836 kb
Host smart-665cff1d-e4ca-41c6-9cff-613f7cd1f3f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661401023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.1661401023
Directory /workspace/34.uart_tx_rx/latest

Test location /workspace/coverage/default/35.uart_alert_test.3926607487
Short name T921
Test name
Test status
Simulation time 24133590 ps
CPU time 0.56 seconds
Started Jun 10 05:14:19 PM PDT 24
Finished Jun 10 05:14:20 PM PDT 24
Peak memory 195920 kb
Host smart-730f4ef3-0b0f-474a-afdd-eed1eca86375
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926607487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.3926607487
Directory /workspace/35.uart_alert_test/latest

Test location /workspace/coverage/default/35.uart_fifo_full.4126458498
Short name T1068
Test name
Test status
Simulation time 179617100911 ps
CPU time 141.69 seconds
Started Jun 10 05:14:13 PM PDT 24
Finished Jun 10 05:16:36 PM PDT 24
Peak memory 200284 kb
Host smart-8f2b2f11-fd4f-4277-ac3a-a33023db6952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126458498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.4126458498
Directory /workspace/35.uart_fifo_full/latest

Test location /workspace/coverage/default/35.uart_fifo_overflow.50118165
Short name T712
Test name
Test status
Simulation time 76463135213 ps
CPU time 32.1 seconds
Started Jun 10 05:14:24 PM PDT 24
Finished Jun 10 05:14:57 PM PDT 24
Peak memory 200256 kb
Host smart-d1ddac79-cc26-4cc8-8661-b8463d5fc465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50118165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.50118165
Directory /workspace/35.uart_fifo_overflow/latest

Test location /workspace/coverage/default/35.uart_fifo_reset.1103078603
Short name T612
Test name
Test status
Simulation time 95136375345 ps
CPU time 141.19 seconds
Started Jun 10 05:14:20 PM PDT 24
Finished Jun 10 05:16:42 PM PDT 24
Peak memory 200240 kb
Host smart-84403fe1-8e84-4e8c-9caa-76d7ff43efba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103078603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.1103078603
Directory /workspace/35.uart_fifo_reset/latest

Test location /workspace/coverage/default/35.uart_intr.1636841869
Short name T675
Test name
Test status
Simulation time 68253923251 ps
CPU time 119.94 seconds
Started Jun 10 05:14:46 PM PDT 24
Finished Jun 10 05:16:46 PM PDT 24
Peak memory 200368 kb
Host smart-4b600bfb-4d03-42e5-8cbf-14b4f389db5c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636841869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.1636841869
Directory /workspace/35.uart_intr/latest

Test location /workspace/coverage/default/35.uart_long_xfer_wo_dly.3580850614
Short name T455
Test name
Test status
Simulation time 123090656524 ps
CPU time 140.3 seconds
Started Jun 10 05:14:25 PM PDT 24
Finished Jun 10 05:16:46 PM PDT 24
Peak memory 200316 kb
Host smart-579317f9-3b91-4ccd-8976-f3da7fa1204a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3580850614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.3580850614
Directory /workspace/35.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/35.uart_loopback.4238004882
Short name T456
Test name
Test status
Simulation time 9041681354 ps
CPU time 5.64 seconds
Started Jun 10 05:14:22 PM PDT 24
Finished Jun 10 05:14:28 PM PDT 24
Peak memory 200296 kb
Host smart-69bb7150-ff9e-48e1-80f5-ae0b09481505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238004882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_loopback.4238004882
Directory /workspace/35.uart_loopback/latest

Test location /workspace/coverage/default/35.uart_perf.2964680490
Short name T602
Test name
Test status
Simulation time 7701791286 ps
CPU time 386.95 seconds
Started Jun 10 05:14:24 PM PDT 24
Finished Jun 10 05:20:51 PM PDT 24
Peak memory 200276 kb
Host smart-a4e94a9c-361e-4a0e-a080-c8d18df1a76a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2964680490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.2964680490
Directory /workspace/35.uart_perf/latest

Test location /workspace/coverage/default/35.uart_rx_oversample.4218503197
Short name T367
Test name
Test status
Simulation time 4933373265 ps
CPU time 11.32 seconds
Started Jun 10 05:14:19 PM PDT 24
Finished Jun 10 05:14:31 PM PDT 24
Peak memory 199600 kb
Host smart-1ccf0e6e-f6e2-4cb6-8c2b-a16239f5ac47
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4218503197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.4218503197
Directory /workspace/35.uart_rx_oversample/latest

Test location /workspace/coverage/default/35.uart_rx_parity_err.3341785212
Short name T3
Test name
Test status
Simulation time 104282962832 ps
CPU time 157.18 seconds
Started Jun 10 05:14:18 PM PDT 24
Finished Jun 10 05:16:55 PM PDT 24
Peak memory 199804 kb
Host smart-7bb0be1e-a838-4c50-bf71-0ba913c34560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341785212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.3341785212
Directory /workspace/35.uart_rx_parity_err/latest

Test location /workspace/coverage/default/35.uart_rx_start_bit_filter.3177388864
Short name T595
Test name
Test status
Simulation time 3375133852 ps
CPU time 5.8 seconds
Started Jun 10 05:14:26 PM PDT 24
Finished Jun 10 05:14:32 PM PDT 24
Peak memory 196816 kb
Host smart-e7afbecd-7d84-4b94-a180-0d4843f27063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177388864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.3177388864
Directory /workspace/35.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/35.uart_smoke.3698414646
Short name T396
Test name
Test status
Simulation time 510725148 ps
CPU time 1.66 seconds
Started Jun 10 05:14:21 PM PDT 24
Finished Jun 10 05:14:23 PM PDT 24
Peak memory 199968 kb
Host smart-61cefd06-b098-4b4a-a3e8-d56b58a76815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698414646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_smoke.3698414646
Directory /workspace/35.uart_smoke/latest

Test location /workspace/coverage/default/35.uart_stress_all.1464154417
Short name T532
Test name
Test status
Simulation time 14480317049 ps
CPU time 23.2 seconds
Started Jun 10 05:14:21 PM PDT 24
Finished Jun 10 05:14:44 PM PDT 24
Peak memory 200308 kb
Host smart-bed0bc6a-a70d-4508-bd7b-6c64eddc1b26
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464154417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.1464154417
Directory /workspace/35.uart_stress_all/latest

Test location /workspace/coverage/default/35.uart_tx_ovrd.987068969
Short name T902
Test name
Test status
Simulation time 6273540161 ps
CPU time 25.67 seconds
Started Jun 10 05:14:17 PM PDT 24
Finished Jun 10 05:14:43 PM PDT 24
Peak memory 200400 kb
Host smart-8112df1c-a9be-4aff-a422-775f03696689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987068969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.987068969
Directory /workspace/35.uart_tx_ovrd/latest

Test location /workspace/coverage/default/35.uart_tx_rx.3830607654
Short name T298
Test name
Test status
Simulation time 101084935528 ps
CPU time 109.67 seconds
Started Jun 10 05:14:17 PM PDT 24
Finished Jun 10 05:16:07 PM PDT 24
Peak memory 200344 kb
Host smart-d9b48496-dfc1-450b-9806-ee1aaf1dfb7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830607654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.3830607654
Directory /workspace/35.uart_tx_rx/latest

Test location /workspace/coverage/default/36.uart_alert_test.1999508096
Short name T386
Test name
Test status
Simulation time 14867874 ps
CPU time 0.61 seconds
Started Jun 10 05:14:24 PM PDT 24
Finished Jun 10 05:14:25 PM PDT 24
Peak memory 194636 kb
Host smart-82c87e6e-7f7f-45d5-a8c7-ccc34ce65eb1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999508096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.1999508096
Directory /workspace/36.uart_alert_test/latest

Test location /workspace/coverage/default/36.uart_fifo_full.2318448323
Short name T665
Test name
Test status
Simulation time 138537847149 ps
CPU time 517.41 seconds
Started Jun 10 05:14:19 PM PDT 24
Finished Jun 10 05:22:57 PM PDT 24
Peak memory 200196 kb
Host smart-47ed582a-a93a-4af8-8459-7ed35e6349b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318448323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.2318448323
Directory /workspace/36.uart_fifo_full/latest

Test location /workspace/coverage/default/36.uart_fifo_overflow.3438205520
Short name T790
Test name
Test status
Simulation time 156461236196 ps
CPU time 62 seconds
Started Jun 10 05:14:24 PM PDT 24
Finished Jun 10 05:15:26 PM PDT 24
Peak memory 200384 kb
Host smart-7a3cbb54-e25d-46bd-806a-474c0a35eaf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438205520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.3438205520
Directory /workspace/36.uart_fifo_overflow/latest

Test location /workspace/coverage/default/36.uart_fifo_reset.3581241710
Short name T251
Test name
Test status
Simulation time 81688680471 ps
CPU time 19.57 seconds
Started Jun 10 05:14:24 PM PDT 24
Finished Jun 10 05:14:44 PM PDT 24
Peak memory 200336 kb
Host smart-06188ef8-c8e4-45a3-a5c7-a88a95df8e39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581241710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.3581241710
Directory /workspace/36.uart_fifo_reset/latest

Test location /workspace/coverage/default/36.uart_intr.2463494609
Short name T549
Test name
Test status
Simulation time 15655156859 ps
CPU time 2.89 seconds
Started Jun 10 05:14:22 PM PDT 24
Finished Jun 10 05:14:25 PM PDT 24
Peak memory 199688 kb
Host smart-3ebd2c6e-8b4b-4e1e-935f-0e31245c4e52
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463494609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.2463494609
Directory /workspace/36.uart_intr/latest

Test location /workspace/coverage/default/36.uart_long_xfer_wo_dly.2860606274
Short name T512
Test name
Test status
Simulation time 159095098775 ps
CPU time 1011.67 seconds
Started Jun 10 05:14:28 PM PDT 24
Finished Jun 10 05:31:20 PM PDT 24
Peak memory 200356 kb
Host smart-88f24a46-c81c-4b9e-8c83-53965b99bf89
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2860606274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.2860606274
Directory /workspace/36.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/36.uart_loopback.3003761206
Short name T365
Test name
Test status
Simulation time 10217485881 ps
CPU time 3.43 seconds
Started Jun 10 05:14:21 PM PDT 24
Finished Jun 10 05:14:25 PM PDT 24
Peak memory 199976 kb
Host smart-8a17768e-0526-419c-993d-be43f7194493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003761206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_loopback.3003761206
Directory /workspace/36.uart_loopback/latest

Test location /workspace/coverage/default/36.uart_perf.178647736
Short name T506
Test name
Test status
Simulation time 7334834087 ps
CPU time 455.58 seconds
Started Jun 10 05:14:21 PM PDT 24
Finished Jun 10 05:21:57 PM PDT 24
Peak memory 200232 kb
Host smart-6cff8277-43f1-4e06-ae3e-d584124a4071
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=178647736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.178647736
Directory /workspace/36.uart_perf/latest

Test location /workspace/coverage/default/36.uart_rx_oversample.4164675266
Short name T543
Test name
Test status
Simulation time 5958914302 ps
CPU time 53.73 seconds
Started Jun 10 05:14:19 PM PDT 24
Finished Jun 10 05:15:13 PM PDT 24
Peak memory 199440 kb
Host smart-57429d85-0b81-4eef-9f42-28662bc56b3b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4164675266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.4164675266
Directory /workspace/36.uart_rx_oversample/latest

Test location /workspace/coverage/default/36.uart_rx_parity_err.2478405108
Short name T671
Test name
Test status
Simulation time 115852399723 ps
CPU time 99.92 seconds
Started Jun 10 05:14:21 PM PDT 24
Finished Jun 10 05:16:01 PM PDT 24
Peak memory 200372 kb
Host smart-27e7141d-79e3-47f1-aa69-3e839cc1028b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478405108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.2478405108
Directory /workspace/36.uart_rx_parity_err/latest

Test location /workspace/coverage/default/36.uart_rx_start_bit_filter.202245159
Short name T1032
Test name
Test status
Simulation time 6665693800 ps
CPU time 5.56 seconds
Started Jun 10 05:14:19 PM PDT 24
Finished Jun 10 05:14:25 PM PDT 24
Peak memory 196348 kb
Host smart-0a463b86-2b4f-45ea-9416-96a3f7143be3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202245159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.202245159
Directory /workspace/36.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/36.uart_smoke.3509133833
Short name T478
Test name
Test status
Simulation time 300403400 ps
CPU time 1.04 seconds
Started Jun 10 05:14:18 PM PDT 24
Finished Jun 10 05:14:20 PM PDT 24
Peak memory 199928 kb
Host smart-94d4b901-2e4e-4779-a57e-ed8f28e87414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509133833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_smoke.3509133833
Directory /workspace/36.uart_smoke/latest

Test location /workspace/coverage/default/36.uart_stress_all.3515961716
Short name T269
Test name
Test status
Simulation time 101861271106 ps
CPU time 190.86 seconds
Started Jun 10 05:14:22 PM PDT 24
Finished Jun 10 05:17:33 PM PDT 24
Peak memory 200304 kb
Host smart-5993289e-b1e0-49ca-87d8-d115c3f48fd7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515961716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.3515961716
Directory /workspace/36.uart_stress_all/latest

Test location /workspace/coverage/default/36.uart_tx_ovrd.2428035701
Short name T635
Test name
Test status
Simulation time 7329616052 ps
CPU time 8.48 seconds
Started Jun 10 05:14:24 PM PDT 24
Finished Jun 10 05:14:32 PM PDT 24
Peak memory 200440 kb
Host smart-89dc258d-4d79-4e60-9c98-756b1c3689f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428035701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.2428035701
Directory /workspace/36.uart_tx_ovrd/latest

Test location /workspace/coverage/default/36.uart_tx_rx.1812465114
Short name T696
Test name
Test status
Simulation time 133348774260 ps
CPU time 93.92 seconds
Started Jun 10 05:14:22 PM PDT 24
Finished Jun 10 05:15:56 PM PDT 24
Peak memory 200276 kb
Host smart-43941370-65ec-4964-96eb-5802a4ff1119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812465114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.1812465114
Directory /workspace/36.uart_tx_rx/latest

Test location /workspace/coverage/default/37.uart_alert_test.1814495774
Short name T558
Test name
Test status
Simulation time 39645742 ps
CPU time 0.55 seconds
Started Jun 10 05:14:23 PM PDT 24
Finished Jun 10 05:14:24 PM PDT 24
Peak memory 194700 kb
Host smart-4f38a965-3441-45e1-9039-9f25f477d36b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814495774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.1814495774
Directory /workspace/37.uart_alert_test/latest

Test location /workspace/coverage/default/37.uart_fifo_full.3184102596
Short name T138
Test name
Test status
Simulation time 70974143491 ps
CPU time 157.77 seconds
Started Jun 10 05:14:25 PM PDT 24
Finished Jun 10 05:17:03 PM PDT 24
Peak memory 200296 kb
Host smart-f0f5bc52-3db8-4540-809e-f8b88b795863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184102596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.3184102596
Directory /workspace/37.uart_fifo_full/latest

Test location /workspace/coverage/default/37.uart_fifo_overflow.4042534162
Short name T575
Test name
Test status
Simulation time 26671045964 ps
CPU time 45.67 seconds
Started Jun 10 05:14:21 PM PDT 24
Finished Jun 10 05:15:07 PM PDT 24
Peak memory 200228 kb
Host smart-0a6b3387-299f-46f2-8896-ae9952cc4b7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042534162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.4042534162
Directory /workspace/37.uart_fifo_overflow/latest

Test location /workspace/coverage/default/37.uart_fifo_reset.1728991632
Short name T610
Test name
Test status
Simulation time 99125961225 ps
CPU time 121.25 seconds
Started Jun 10 05:14:23 PM PDT 24
Finished Jun 10 05:16:24 PM PDT 24
Peak memory 200292 kb
Host smart-22660928-67f1-43cf-856b-da2feceba5eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728991632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.1728991632
Directory /workspace/37.uart_fifo_reset/latest

Test location /workspace/coverage/default/37.uart_intr.166789021
Short name T919
Test name
Test status
Simulation time 20609648160 ps
CPU time 10 seconds
Started Jun 10 05:14:28 PM PDT 24
Finished Jun 10 05:14:38 PM PDT 24
Peak memory 200288 kb
Host smart-5cbb3b8f-398e-4f28-b151-1e3b6007daa5
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166789021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.166789021
Directory /workspace/37.uart_intr/latest

Test location /workspace/coverage/default/37.uart_long_xfer_wo_dly.3227763625
Short name T413
Test name
Test status
Simulation time 114729280543 ps
CPU time 566.77 seconds
Started Jun 10 05:14:24 PM PDT 24
Finished Jun 10 05:23:51 PM PDT 24
Peak memory 200400 kb
Host smart-c41db66e-5ab8-456a-9e9c-694bf2da2235
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3227763625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.3227763625
Directory /workspace/37.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/37.uart_loopback.229131997
Short name T995
Test name
Test status
Simulation time 6515559203 ps
CPU time 13.79 seconds
Started Jun 10 05:14:22 PM PDT 24
Finished Jun 10 05:14:36 PM PDT 24
Peak memory 200112 kb
Host smart-5d16be97-2ff2-4204-88d9-4e4974ec84ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229131997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_loopback.229131997
Directory /workspace/37.uart_loopback/latest

Test location /workspace/coverage/default/37.uart_perf.3469482852
Short name T750
Test name
Test status
Simulation time 26668082947 ps
CPU time 355.17 seconds
Started Jun 10 05:14:22 PM PDT 24
Finished Jun 10 05:20:18 PM PDT 24
Peak memory 200248 kb
Host smart-bd65ed6e-24ff-420d-805f-17921a0f35a9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3469482852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.3469482852
Directory /workspace/37.uart_perf/latest

Test location /workspace/coverage/default/37.uart_rx_oversample.366822724
Short name T1011
Test name
Test status
Simulation time 1311929493 ps
CPU time 0.67 seconds
Started Jun 10 05:14:23 PM PDT 24
Finished Jun 10 05:14:24 PM PDT 24
Peak memory 195760 kb
Host smart-74297774-27d2-4dde-9b1c-6efc31a8acc9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=366822724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.366822724
Directory /workspace/37.uart_rx_oversample/latest

Test location /workspace/coverage/default/37.uart_rx_parity_err.3646920750
Short name T981
Test name
Test status
Simulation time 39171610726 ps
CPU time 23.38 seconds
Started Jun 10 05:14:26 PM PDT 24
Finished Jun 10 05:14:49 PM PDT 24
Peak memory 200324 kb
Host smart-e74d8c0b-2dd3-4a22-809d-921c677ad74c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646920750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.3646920750
Directory /workspace/37.uart_rx_parity_err/latest

Test location /workspace/coverage/default/37.uart_rx_start_bit_filter.73458299
Short name T581
Test name
Test status
Simulation time 42167659076 ps
CPU time 38.34 seconds
Started Jun 10 05:14:28 PM PDT 24
Finished Jun 10 05:15:07 PM PDT 24
Peak memory 196352 kb
Host smart-9b994a1c-6cdf-4fe6-bd0e-4f947c09d9a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73458299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.73458299
Directory /workspace/37.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/37.uart_smoke.4055528765
Short name T780
Test name
Test status
Simulation time 528747624 ps
CPU time 1.88 seconds
Started Jun 10 05:14:23 PM PDT 24
Finished Jun 10 05:14:26 PM PDT 24
Peak memory 199920 kb
Host smart-489821f8-43c7-46ce-9663-125250558874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055528765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_smoke.4055528765
Directory /workspace/37.uart_smoke/latest

Test location /workspace/coverage/default/37.uart_stress_all.3240237218
Short name T770
Test name
Test status
Simulation time 205835318040 ps
CPU time 219.37 seconds
Started Jun 10 05:14:22 PM PDT 24
Finished Jun 10 05:18:02 PM PDT 24
Peak memory 200220 kb
Host smart-55526a0a-8b02-4e99-8873-2ecd57782599
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240237218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.3240237218
Directory /workspace/37.uart_stress_all/latest

Test location /workspace/coverage/default/37.uart_stress_all_with_rand_reset.271395034
Short name T114
Test name
Test status
Simulation time 44860593419 ps
CPU time 201.49 seconds
Started Jun 10 05:14:28 PM PDT 24
Finished Jun 10 05:17:49 PM PDT 24
Peak memory 216320 kb
Host smart-0bab75e9-5950-4376-b47f-64a1d0b482b6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271395034 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 37.uart_stress_all_with_rand_reset.271395034
Directory /workspace/37.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.uart_tx_ovrd.3131659435
Short name T897
Test name
Test status
Simulation time 12898266408 ps
CPU time 5.67 seconds
Started Jun 10 05:14:26 PM PDT 24
Finished Jun 10 05:14:32 PM PDT 24
Peak memory 200352 kb
Host smart-1ec6baa7-4286-4e32-b4e7-d17754f71b11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131659435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.3131659435
Directory /workspace/37.uart_tx_ovrd/latest

Test location /workspace/coverage/default/37.uart_tx_rx.303681565
Short name T719
Test name
Test status
Simulation time 90311337052 ps
CPU time 105.1 seconds
Started Jun 10 05:14:22 PM PDT 24
Finished Jun 10 05:16:08 PM PDT 24
Peak memory 200320 kb
Host smart-bd304599-d89c-45be-8973-f6070231ea03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303681565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.303681565
Directory /workspace/37.uart_tx_rx/latest

Test location /workspace/coverage/default/38.uart_alert_test.1035281722
Short name T650
Test name
Test status
Simulation time 48155945 ps
CPU time 0.59 seconds
Started Jun 10 05:14:32 PM PDT 24
Finished Jun 10 05:14:33 PM PDT 24
Peak memory 196032 kb
Host smart-5498440c-d3d5-4a81-9214-f0395b070dc4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035281722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.1035281722
Directory /workspace/38.uart_alert_test/latest

Test location /workspace/coverage/default/38.uart_fifo_overflow.593360134
Short name T787
Test name
Test status
Simulation time 18912922488 ps
CPU time 21.9 seconds
Started Jun 10 05:14:36 PM PDT 24
Finished Jun 10 05:14:58 PM PDT 24
Peak memory 200300 kb
Host smart-9931fc84-25a8-4856-bcf1-b759f87ebaf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593360134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.593360134
Directory /workspace/38.uart_fifo_overflow/latest

Test location /workspace/coverage/default/38.uart_fifo_reset.4293075124
Short name T201
Test name
Test status
Simulation time 24121709967 ps
CPU time 41.74 seconds
Started Jun 10 05:14:31 PM PDT 24
Finished Jun 10 05:15:13 PM PDT 24
Peak memory 200328 kb
Host smart-cc8446a9-c9fc-41fe-9edf-cd6c8bb650d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293075124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.4293075124
Directory /workspace/38.uart_fifo_reset/latest

Test location /workspace/coverage/default/38.uart_intr.755875059
Short name T12
Test name
Test status
Simulation time 41895790227 ps
CPU time 64.63 seconds
Started Jun 10 05:14:35 PM PDT 24
Finished Jun 10 05:15:39 PM PDT 24
Peak memory 199088 kb
Host smart-87661d20-95db-4e3e-a398-85156d8edd70
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755875059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.755875059
Directory /workspace/38.uart_intr/latest

Test location /workspace/coverage/default/38.uart_long_xfer_wo_dly.3239958665
Short name T1017
Test name
Test status
Simulation time 107641406977 ps
CPU time 268.55 seconds
Started Jun 10 05:14:31 PM PDT 24
Finished Jun 10 05:19:00 PM PDT 24
Peak memory 200376 kb
Host smart-ffeb7a42-28af-45a2-b12a-703e8e0ba273
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3239958665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.3239958665
Directory /workspace/38.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/38.uart_loopback.2884398058
Short name T928
Test name
Test status
Simulation time 7694790762 ps
CPU time 16.88 seconds
Started Jun 10 05:14:36 PM PDT 24
Finished Jun 10 05:14:53 PM PDT 24
Peak memory 200100 kb
Host smart-6d224fdb-b838-47fc-b43c-9f546f4dd344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884398058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_loopback.2884398058
Directory /workspace/38.uart_loopback/latest

Test location /workspace/coverage/default/38.uart_perf.985447107
Short name T888
Test name
Test status
Simulation time 12485485217 ps
CPU time 86.54 seconds
Started Jun 10 05:14:27 PM PDT 24
Finished Jun 10 05:15:54 PM PDT 24
Peak memory 200260 kb
Host smart-f42d4e41-d626-492b-a016-06286a6c775f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=985447107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.985447107
Directory /workspace/38.uart_perf/latest

Test location /workspace/coverage/default/38.uart_rx_oversample.194365602
Short name T1002
Test name
Test status
Simulation time 1907554720 ps
CPU time 9.22 seconds
Started Jun 10 05:14:36 PM PDT 24
Finished Jun 10 05:14:46 PM PDT 24
Peak memory 198912 kb
Host smart-9a0a9adc-96c4-4a3a-8b4b-dba9e077469f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=194365602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.194365602
Directory /workspace/38.uart_rx_oversample/latest

Test location /workspace/coverage/default/38.uart_rx_parity_err.52043203
Short name T434
Test name
Test status
Simulation time 43960179137 ps
CPU time 19.48 seconds
Started Jun 10 05:14:37 PM PDT 24
Finished Jun 10 05:14:57 PM PDT 24
Peak memory 200388 kb
Host smart-e19bbd12-b215-4441-bca3-1718e9ecf249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52043203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.52043203
Directory /workspace/38.uart_rx_parity_err/latest

Test location /workspace/coverage/default/38.uart_rx_start_bit_filter.2987982868
Short name T572
Test name
Test status
Simulation time 51258871085 ps
CPU time 76.83 seconds
Started Jun 10 05:14:42 PM PDT 24
Finished Jun 10 05:15:59 PM PDT 24
Peak memory 196420 kb
Host smart-220333e3-c444-462f-8360-a16d77643c65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987982868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.2987982868
Directory /workspace/38.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/38.uart_smoke.2553624853
Short name T525
Test name
Test status
Simulation time 568563875 ps
CPU time 0.99 seconds
Started Jun 10 05:14:25 PM PDT 24
Finished Jun 10 05:14:26 PM PDT 24
Peak memory 198796 kb
Host smart-4b46fe1f-bf5e-4e3e-80d1-ea939f111471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553624853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_smoke.2553624853
Directory /workspace/38.uart_smoke/latest

Test location /workspace/coverage/default/38.uart_stress_all.831741668
Short name T963
Test name
Test status
Simulation time 82990110548 ps
CPU time 152.07 seconds
Started Jun 10 05:14:36 PM PDT 24
Finished Jun 10 05:17:08 PM PDT 24
Peak memory 200260 kb
Host smart-f6cc3290-3dfb-430b-b817-e13241f81ae8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831741668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.831741668
Directory /workspace/38.uart_stress_all/latest

Test location /workspace/coverage/default/38.uart_tx_ovrd.1639476969
Short name T863
Test name
Test status
Simulation time 607448779 ps
CPU time 2 seconds
Started Jun 10 05:14:27 PM PDT 24
Finished Jun 10 05:14:30 PM PDT 24
Peak memory 198960 kb
Host smart-068af00a-097c-4934-8691-a136bf754d22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639476969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.1639476969
Directory /workspace/38.uart_tx_ovrd/latest

Test location /workspace/coverage/default/38.uart_tx_rx.289599077
Short name T331
Test name
Test status
Simulation time 62345368626 ps
CPU time 29.89 seconds
Started Jun 10 05:14:28 PM PDT 24
Finished Jun 10 05:14:58 PM PDT 24
Peak memory 200328 kb
Host smart-e3b471a3-f512-4567-bdc9-5bc80f39674a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289599077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.289599077
Directory /workspace/38.uart_tx_rx/latest

Test location /workspace/coverage/default/39.uart_alert_test.3832811551
Short name T23
Test name
Test status
Simulation time 62670606 ps
CPU time 0.57 seconds
Started Jun 10 05:14:38 PM PDT 24
Finished Jun 10 05:14:39 PM PDT 24
Peak memory 195760 kb
Host smart-8bf4052f-9c98-4d05-9970-ea5d7c3020d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832811551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.3832811551
Directory /workspace/39.uart_alert_test/latest

Test location /workspace/coverage/default/39.uart_fifo_full.2697863533
Short name T979
Test name
Test status
Simulation time 46676576760 ps
CPU time 21.55 seconds
Started Jun 10 05:14:30 PM PDT 24
Finished Jun 10 05:14:51 PM PDT 24
Peak memory 200320 kb
Host smart-be896dbf-5ccc-4a95-b3b3-3e1195b0761d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697863533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.2697863533
Directory /workspace/39.uart_fifo_full/latest

Test location /workspace/coverage/default/39.uart_fifo_overflow.142688975
Short name T109
Test name
Test status
Simulation time 143242535036 ps
CPU time 248.6 seconds
Started Jun 10 05:14:28 PM PDT 24
Finished Jun 10 05:18:37 PM PDT 24
Peak memory 200372 kb
Host smart-fc97a237-4048-4977-a672-b11f36c10291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142688975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.142688975
Directory /workspace/39.uart_fifo_overflow/latest

Test location /workspace/coverage/default/39.uart_fifo_reset.1548734785
Short name T207
Test name
Test status
Simulation time 70186132498 ps
CPU time 108.4 seconds
Started Jun 10 05:14:28 PM PDT 24
Finished Jun 10 05:16:17 PM PDT 24
Peak memory 200396 kb
Host smart-fb9fd72d-bd8d-4232-a9cf-a89f186ba256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548734785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.1548734785
Directory /workspace/39.uart_fifo_reset/latest

Test location /workspace/coverage/default/39.uart_intr.1895342535
Short name T287
Test name
Test status
Simulation time 77264468797 ps
CPU time 127.47 seconds
Started Jun 10 05:14:39 PM PDT 24
Finished Jun 10 05:16:47 PM PDT 24
Peak memory 200312 kb
Host smart-ab0772f6-1049-4c8e-8f26-ef8ac4f63daa
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895342535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.1895342535
Directory /workspace/39.uart_intr/latest

Test location /workspace/coverage/default/39.uart_long_xfer_wo_dly.1765380457
Short name T322
Test name
Test status
Simulation time 175535913029 ps
CPU time 1713.15 seconds
Started Jun 10 05:14:37 PM PDT 24
Finished Jun 10 05:43:11 PM PDT 24
Peak memory 200300 kb
Host smart-5f9d686a-4d76-4f1d-a797-022cf0552ada
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1765380457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.1765380457
Directory /workspace/39.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/39.uart_loopback.612366693
Short name T360
Test name
Test status
Simulation time 5987419804 ps
CPU time 11.5 seconds
Started Jun 10 05:14:32 PM PDT 24
Finished Jun 10 05:14:44 PM PDT 24
Peak memory 199844 kb
Host smart-e6e5c823-1e77-461f-9953-36ea906bf891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612366693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_loopback.612366693
Directory /workspace/39.uart_loopback/latest

Test location /workspace/coverage/default/39.uart_perf.1428417500
Short name T694
Test name
Test status
Simulation time 19072055067 ps
CPU time 188.24 seconds
Started Jun 10 05:14:31 PM PDT 24
Finished Jun 10 05:17:39 PM PDT 24
Peak memory 200288 kb
Host smart-487f5740-9929-4c5c-80fd-ee14ba41544d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1428417500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.1428417500
Directory /workspace/39.uart_perf/latest

Test location /workspace/coverage/default/39.uart_rx_oversample.2756121977
Short name T485
Test name
Test status
Simulation time 6141224780 ps
CPU time 7.35 seconds
Started Jun 10 05:14:37 PM PDT 24
Finished Jun 10 05:14:45 PM PDT 24
Peak memory 199504 kb
Host smart-cae46804-5bea-4a50-8942-28c66f91f4db
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2756121977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.2756121977
Directory /workspace/39.uart_rx_oversample/latest

Test location /workspace/coverage/default/39.uart_rx_parity_err.2130125128
Short name T792
Test name
Test status
Simulation time 41016369867 ps
CPU time 23.35 seconds
Started Jun 10 05:14:41 PM PDT 24
Finished Jun 10 05:15:05 PM PDT 24
Peak memory 200340 kb
Host smart-33ffd82c-296d-49a7-b1f5-b7da8bdf6298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130125128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.2130125128
Directory /workspace/39.uart_rx_parity_err/latest

Test location /workspace/coverage/default/39.uart_rx_start_bit_filter.2038301725
Short name T914
Test name
Test status
Simulation time 1740947203 ps
CPU time 3.49 seconds
Started Jun 10 05:14:30 PM PDT 24
Finished Jun 10 05:14:34 PM PDT 24
Peak memory 195760 kb
Host smart-23636d84-9797-44db-bbfc-3ccbba7fd2f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038301725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.2038301725
Directory /workspace/39.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/39.uart_smoke.3078189404
Short name T864
Test name
Test status
Simulation time 308783672 ps
CPU time 1.45 seconds
Started Jun 10 05:14:36 PM PDT 24
Finished Jun 10 05:14:38 PM PDT 24
Peak memory 199244 kb
Host smart-ca3283bf-969e-4caa-9a86-90c031f4dea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078189404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_smoke.3078189404
Directory /workspace/39.uart_smoke/latest

Test location /workspace/coverage/default/39.uart_stress_all.749866111
Short name T850
Test name
Test status
Simulation time 60017619237 ps
CPU time 234.45 seconds
Started Jun 10 05:14:31 PM PDT 24
Finished Jun 10 05:18:26 PM PDT 24
Peak memory 200296 kb
Host smart-d0fa9f8d-8015-498c-afc8-e250e422200f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749866111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.749866111
Directory /workspace/39.uart_stress_all/latest

Test location /workspace/coverage/default/39.uart_tx_ovrd.3711774972
Short name T412
Test name
Test status
Simulation time 2518237137 ps
CPU time 1.27 seconds
Started Jun 10 05:14:37 PM PDT 24
Finished Jun 10 05:14:39 PM PDT 24
Peak memory 198740 kb
Host smart-1f2ec7c3-a390-4eea-9a5c-9788940079a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711774972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.3711774972
Directory /workspace/39.uart_tx_ovrd/latest

Test location /workspace/coverage/default/39.uart_tx_rx.1947693843
Short name T325
Test name
Test status
Simulation time 81225914135 ps
CPU time 55.21 seconds
Started Jun 10 05:14:29 PM PDT 24
Finished Jun 10 05:15:25 PM PDT 24
Peak memory 200260 kb
Host smart-af0b6ede-faa8-4645-b909-b4fc5a23f1f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947693843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.1947693843
Directory /workspace/39.uart_tx_rx/latest

Test location /workspace/coverage/default/4.uart_alert_test.1903668271
Short name T488
Test name
Test status
Simulation time 13972311 ps
CPU time 0.57 seconds
Started Jun 10 05:12:58 PM PDT 24
Finished Jun 10 05:12:59 PM PDT 24
Peak memory 194708 kb
Host smart-7a4e772e-f9cb-46db-b09c-de1c913894b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903668271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.1903668271
Directory /workspace/4.uart_alert_test/latest

Test location /workspace/coverage/default/4.uart_fifo_full.4281051426
Short name T408
Test name
Test status
Simulation time 121366678940 ps
CPU time 41.42 seconds
Started Jun 10 05:12:56 PM PDT 24
Finished Jun 10 05:13:37 PM PDT 24
Peak memory 200268 kb
Host smart-8153be9a-742a-440d-bada-6b59601dd92e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281051426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.4281051426
Directory /workspace/4.uart_fifo_full/latest

Test location /workspace/coverage/default/4.uart_fifo_overflow.3212498053
Short name T1091
Test name
Test status
Simulation time 77647693696 ps
CPU time 71.44 seconds
Started Jun 10 05:12:56 PM PDT 24
Finished Jun 10 05:14:08 PM PDT 24
Peak memory 200332 kb
Host smart-98885b7e-c32b-44ac-ba56-92bf2d0fd0af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212498053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.3212498053
Directory /workspace/4.uart_fifo_overflow/latest

Test location /workspace/coverage/default/4.uart_fifo_reset.370241986
Short name T862
Test name
Test status
Simulation time 26279532016 ps
CPU time 53.8 seconds
Started Jun 10 05:12:59 PM PDT 24
Finished Jun 10 05:13:53 PM PDT 24
Peak memory 200320 kb
Host smart-b4219db6-f6b1-4386-a21d-98f1de2c0580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370241986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.370241986
Directory /workspace/4.uart_fifo_reset/latest

Test location /workspace/coverage/default/4.uart_intr.1437138500
Short name T769
Test name
Test status
Simulation time 11156404948 ps
CPU time 5.02 seconds
Started Jun 10 05:12:58 PM PDT 24
Finished Jun 10 05:13:03 PM PDT 24
Peak memory 197264 kb
Host smart-10974d58-ae4c-4952-90f4-4965dd879136
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437138500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.1437138500
Directory /workspace/4.uart_intr/latest

Test location /workspace/coverage/default/4.uart_long_xfer_wo_dly.4171378187
Short name T373
Test name
Test status
Simulation time 104407884126 ps
CPU time 138.24 seconds
Started Jun 10 05:12:55 PM PDT 24
Finished Jun 10 05:15:14 PM PDT 24
Peak memory 200352 kb
Host smart-5d7add3f-3f2c-4911-9b29-526fc530ea79
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4171378187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.4171378187
Directory /workspace/4.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/4.uart_loopback.644985330
Short name T483
Test name
Test status
Simulation time 11936304139 ps
CPU time 10.49 seconds
Started Jun 10 05:13:01 PM PDT 24
Finished Jun 10 05:13:11 PM PDT 24
Peak memory 200088 kb
Host smart-50a66e7c-e99e-4c5d-bfcb-a0e0feecaafb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644985330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_loopback.644985330
Directory /workspace/4.uart_loopback/latest

Test location /workspace/coverage/default/4.uart_perf.3716482155
Short name T988
Test name
Test status
Simulation time 4023998268 ps
CPU time 219.61 seconds
Started Jun 10 05:12:56 PM PDT 24
Finished Jun 10 05:16:35 PM PDT 24
Peak memory 200164 kb
Host smart-45f7d3f8-8f4a-4884-80ee-ba297ac1ddb9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3716482155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.3716482155
Directory /workspace/4.uart_perf/latest

Test location /workspace/coverage/default/4.uart_rx_oversample.3175452108
Short name T804
Test name
Test status
Simulation time 3906271722 ps
CPU time 2.37 seconds
Started Jun 10 05:12:59 PM PDT 24
Finished Jun 10 05:13:02 PM PDT 24
Peak memory 198836 kb
Host smart-3eecabdd-0a22-4742-b40d-426bebf591d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3175452108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.3175452108
Directory /workspace/4.uart_rx_oversample/latest

Test location /workspace/coverage/default/4.uart_rx_parity_err.2499725145
Short name T908
Test name
Test status
Simulation time 121116953615 ps
CPU time 67.29 seconds
Started Jun 10 05:12:55 PM PDT 24
Finished Jun 10 05:14:03 PM PDT 24
Peak memory 200280 kb
Host smart-e4f0867b-599b-419a-a40f-4c5c2f6532f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499725145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.2499725145
Directory /workspace/4.uart_rx_parity_err/latest

Test location /workspace/coverage/default/4.uart_rx_start_bit_filter.1474226210
Short name T574
Test name
Test status
Simulation time 4150044487 ps
CPU time 7.53 seconds
Started Jun 10 05:12:55 PM PDT 24
Finished Jun 10 05:13:03 PM PDT 24
Peak memory 196372 kb
Host smart-0a018201-4bba-49d1-a09f-b07ed8b48ee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474226210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.1474226210
Directory /workspace/4.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/4.uart_sec_cm.1725019250
Short name T26
Test name
Test status
Simulation time 104438364 ps
CPU time 0.86 seconds
Started Jun 10 05:13:03 PM PDT 24
Finished Jun 10 05:13:05 PM PDT 24
Peak memory 218532 kb
Host smart-a7998df2-2106-48ff-81c1-a5b5c85bea11
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725019250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.1725019250
Directory /workspace/4.uart_sec_cm/latest

Test location /workspace/coverage/default/4.uart_smoke.3451716665
Short name T847
Test name
Test status
Simulation time 1020250929 ps
CPU time 1.72 seconds
Started Jun 10 05:12:56 PM PDT 24
Finished Jun 10 05:12:58 PM PDT 24
Peak memory 198532 kb
Host smart-1bcf1479-5ca9-4a18-89a1-6018e8f58012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451716665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_smoke.3451716665
Directory /workspace/4.uart_smoke/latest

Test location /workspace/coverage/default/4.uart_stress_all.1546063015
Short name T459
Test name
Test status
Simulation time 306571019402 ps
CPU time 1662.69 seconds
Started Jun 10 05:12:56 PM PDT 24
Finished Jun 10 05:40:39 PM PDT 24
Peak memory 200392 kb
Host smart-ca0b45bc-09f0-49b0-89ca-aec928ab03fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546063015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.1546063015
Directory /workspace/4.uart_stress_all/latest

Test location /workspace/coverage/default/4.uart_stress_all_with_rand_reset.857079042
Short name T815
Test name
Test status
Simulation time 151835565495 ps
CPU time 571.49 seconds
Started Jun 10 05:12:56 PM PDT 24
Finished Jun 10 05:22:28 PM PDT 24
Peak memory 216804 kb
Host smart-85b186b3-d309-45cb-856e-ae0471e65af4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857079042 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 4.uart_stress_all_with_rand_reset.857079042
Directory /workspace/4.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.uart_tx_ovrd.3132532917
Short name T830
Test name
Test status
Simulation time 754905549 ps
CPU time 2.33 seconds
Started Jun 10 05:12:58 PM PDT 24
Finished Jun 10 05:13:00 PM PDT 24
Peak memory 198716 kb
Host smart-e6cf6a29-5142-4816-9874-38744fa4e89f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132532917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.3132532917
Directory /workspace/4.uart_tx_ovrd/latest

Test location /workspace/coverage/default/4.uart_tx_rx.3093800238
Short name T105
Test name
Test status
Simulation time 81615981452 ps
CPU time 90.25 seconds
Started Jun 10 05:12:56 PM PDT 24
Finished Jun 10 05:14:26 PM PDT 24
Peak memory 200220 kb
Host smart-3c07fb22-111c-4e22-b185-0081f7f0def0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093800238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.3093800238
Directory /workspace/4.uart_tx_rx/latest

Test location /workspace/coverage/default/40.uart_alert_test.1903344526
Short name T25
Test name
Test status
Simulation time 11248440 ps
CPU time 0.57 seconds
Started Jun 10 05:14:39 PM PDT 24
Finished Jun 10 05:14:40 PM PDT 24
Peak memory 195108 kb
Host smart-569caa47-3784-453c-bbbd-fdcb358c43bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903344526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.1903344526
Directory /workspace/40.uart_alert_test/latest

Test location /workspace/coverage/default/40.uart_fifo_full.2615942880
Short name T887
Test name
Test status
Simulation time 30965196233 ps
CPU time 9.3 seconds
Started Jun 10 05:14:41 PM PDT 24
Finished Jun 10 05:14:50 PM PDT 24
Peak memory 200116 kb
Host smart-4c81d248-1db3-4903-8d99-6ea2523103d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615942880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.2615942880
Directory /workspace/40.uart_fifo_full/latest

Test location /workspace/coverage/default/40.uart_fifo_overflow.3489506129
Short name T876
Test name
Test status
Simulation time 249433341933 ps
CPU time 414.95 seconds
Started Jun 10 05:14:40 PM PDT 24
Finished Jun 10 05:21:35 PM PDT 24
Peak memory 200276 kb
Host smart-c2b2fad2-677a-4d14-852a-4a371dbf0563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489506129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.3489506129
Directory /workspace/40.uart_fifo_overflow/latest

Test location /workspace/coverage/default/40.uart_fifo_reset.394900119
Short name T645
Test name
Test status
Simulation time 35925716109 ps
CPU time 51.37 seconds
Started Jun 10 05:14:39 PM PDT 24
Finished Jun 10 05:15:31 PM PDT 24
Peak memory 199944 kb
Host smart-d8fabd52-b0f5-49c2-991b-b1c35071f57f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394900119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.394900119
Directory /workspace/40.uart_fifo_reset/latest

Test location /workspace/coverage/default/40.uart_intr.1750467893
Short name T833
Test name
Test status
Simulation time 8355889434 ps
CPU time 19.6 seconds
Started Jun 10 05:14:40 PM PDT 24
Finished Jun 10 05:15:00 PM PDT 24
Peak memory 200496 kb
Host smart-b6da6d8c-1d00-4e33-b994-439ce255e4e3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750467893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.1750467893
Directory /workspace/40.uart_intr/latest

Test location /workspace/coverage/default/40.uart_long_xfer_wo_dly.3889555266
Short name T38
Test name
Test status
Simulation time 59970486398 ps
CPU time 500.75 seconds
Started Jun 10 05:14:35 PM PDT 24
Finished Jun 10 05:22:56 PM PDT 24
Peak memory 200372 kb
Host smart-4a4ba348-5ca3-4c73-a8f2-8a03a60157cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3889555266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.3889555266
Directory /workspace/40.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/40.uart_loopback.776864867
Short name T489
Test name
Test status
Simulation time 8171143133 ps
CPU time 15.71 seconds
Started Jun 10 05:14:39 PM PDT 24
Finished Jun 10 05:14:55 PM PDT 24
Peak memory 198812 kb
Host smart-94e8fa05-e950-4f9f-851d-911df2f146f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776864867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_loopback.776864867
Directory /workspace/40.uart_loopback/latest

Test location /workspace/coverage/default/40.uart_perf.3870011974
Short name T514
Test name
Test status
Simulation time 33358043863 ps
CPU time 945.7 seconds
Started Jun 10 05:14:35 PM PDT 24
Finished Jun 10 05:30:21 PM PDT 24
Peak memory 200128 kb
Host smart-f55102ce-e2a3-413a-b042-4efb0459faf0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3870011974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.3870011974
Directory /workspace/40.uart_perf/latest

Test location /workspace/coverage/default/40.uart_rx_oversample.3882064359
Short name T923
Test name
Test status
Simulation time 6167269059 ps
CPU time 57.23 seconds
Started Jun 10 05:14:32 PM PDT 24
Finished Jun 10 05:15:30 PM PDT 24
Peak memory 200172 kb
Host smart-ef8c45b3-7bb4-4a8d-bba2-888bbda39e45
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3882064359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.3882064359
Directory /workspace/40.uart_rx_oversample/latest

Test location /workspace/coverage/default/40.uart_rx_parity_err.4121685062
Short name T930
Test name
Test status
Simulation time 152090902119 ps
CPU time 201.82 seconds
Started Jun 10 05:14:41 PM PDT 24
Finished Jun 10 05:18:03 PM PDT 24
Peak memory 200480 kb
Host smart-733ce099-3375-49b8-8cc8-bbef3f691a17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121685062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.4121685062
Directory /workspace/40.uart_rx_parity_err/latest

Test location /workspace/coverage/default/40.uart_rx_start_bit_filter.1166393812
Short name T406
Test name
Test status
Simulation time 4240303268 ps
CPU time 2.56 seconds
Started Jun 10 05:14:42 PM PDT 24
Finished Jun 10 05:14:45 PM PDT 24
Peak memory 196612 kb
Host smart-5606553f-0ba9-4480-acac-c2b94651d48d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166393812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.1166393812
Directory /workspace/40.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/40.uart_smoke.3253136793
Short name T952
Test name
Test status
Simulation time 493413748 ps
CPU time 4.24 seconds
Started Jun 10 05:14:40 PM PDT 24
Finished Jun 10 05:14:44 PM PDT 24
Peak memory 199060 kb
Host smart-b1a7c35e-6c6f-4e7b-93b6-41ed32aba4ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253136793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_smoke.3253136793
Directory /workspace/40.uart_smoke/latest

Test location /workspace/coverage/default/40.uart_stress_all.415017044
Short name T809
Test name
Test status
Simulation time 178015039339 ps
CPU time 100.93 seconds
Started Jun 10 05:14:38 PM PDT 24
Finished Jun 10 05:16:20 PM PDT 24
Peak memory 200200 kb
Host smart-edfa7cf0-4cfa-4686-9c77-f3ba8c0c5496
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415017044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.415017044
Directory /workspace/40.uart_stress_all/latest

Test location /workspace/coverage/default/40.uart_stress_all_with_rand_reset.1856731852
Short name T1012
Test name
Test status
Simulation time 282570227897 ps
CPU time 995.26 seconds
Started Jun 10 05:14:39 PM PDT 24
Finished Jun 10 05:31:15 PM PDT 24
Peak memory 227144 kb
Host smart-3588ef59-d316-4209-bd97-4892864255fe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856731852 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 40.uart_stress_all_with_rand_reset.1856731852
Directory /workspace/40.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.uart_tx_ovrd.3163751575
Short name T729
Test name
Test status
Simulation time 797147613 ps
CPU time 2.83 seconds
Started Jun 10 05:14:43 PM PDT 24
Finished Jun 10 05:14:47 PM PDT 24
Peak memory 199132 kb
Host smart-6f56cfec-c8f2-491e-8494-a1e1f29f0a07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163751575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.3163751575
Directory /workspace/40.uart_tx_ovrd/latest

Test location /workspace/coverage/default/40.uart_tx_rx.3086662651
Short name T445
Test name
Test status
Simulation time 44652003493 ps
CPU time 31.66 seconds
Started Jun 10 05:14:41 PM PDT 24
Finished Jun 10 05:15:13 PM PDT 24
Peak memory 200336 kb
Host smart-1eb24b74-36fe-45e8-9346-d048097c8be1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086662651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.3086662651
Directory /workspace/40.uart_tx_rx/latest

Test location /workspace/coverage/default/41.uart_alert_test.938942300
Short name T409
Test name
Test status
Simulation time 153322091 ps
CPU time 0.54 seconds
Started Jun 10 05:14:34 PM PDT 24
Finished Jun 10 05:14:35 PM PDT 24
Peak memory 194864 kb
Host smart-391b4768-6bea-4065-b99c-0635e6281012
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938942300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.938942300
Directory /workspace/41.uart_alert_test/latest

Test location /workspace/coverage/default/41.uart_fifo_full.1020159640
Short name T999
Test name
Test status
Simulation time 21359431989 ps
CPU time 44.48 seconds
Started Jun 10 05:14:37 PM PDT 24
Finished Jun 10 05:15:21 PM PDT 24
Peak memory 200300 kb
Host smart-ff151f91-18eb-4908-be44-62c7440f12e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020159640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.1020159640
Directory /workspace/41.uart_fifo_full/latest

Test location /workspace/coverage/default/41.uart_fifo_overflow.1303465496
Short name T171
Test name
Test status
Simulation time 57296323943 ps
CPU time 18.64 seconds
Started Jun 10 05:14:32 PM PDT 24
Finished Jun 10 05:14:51 PM PDT 24
Peak memory 200316 kb
Host smart-d710f607-0bd3-47af-8e2b-d0a8ab5b082e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303465496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.1303465496
Directory /workspace/41.uart_fifo_overflow/latest

Test location /workspace/coverage/default/41.uart_fifo_reset.1625340965
Short name T211
Test name
Test status
Simulation time 73820020624 ps
CPU time 103.67 seconds
Started Jun 10 05:14:44 PM PDT 24
Finished Jun 10 05:16:28 PM PDT 24
Peak memory 200304 kb
Host smart-1d8fb9c2-a390-4170-bf17-d3e1548bc476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625340965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.1625340965
Directory /workspace/41.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_intr.895154214
Short name T1031
Test name
Test status
Simulation time 35089062529 ps
CPU time 18.44 seconds
Started Jun 10 05:14:36 PM PDT 24
Finished Jun 10 05:14:55 PM PDT 24
Peak memory 200224 kb
Host smart-c6698797-0036-4fea-8560-333988345e26
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895154214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.895154214
Directory /workspace/41.uart_intr/latest

Test location /workspace/coverage/default/41.uart_long_xfer_wo_dly.713945248
Short name T377
Test name
Test status
Simulation time 133418314106 ps
CPU time 176.35 seconds
Started Jun 10 05:14:33 PM PDT 24
Finished Jun 10 05:17:30 PM PDT 24
Peak memory 200268 kb
Host smart-d5e324d0-afba-453e-8f94-d3f118b5697b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=713945248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.713945248
Directory /workspace/41.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/41.uart_loopback.4014967225
Short name T552
Test name
Test status
Simulation time 1315244706 ps
CPU time 2.51 seconds
Started Jun 10 05:14:34 PM PDT 24
Finished Jun 10 05:14:37 PM PDT 24
Peak memory 196132 kb
Host smart-69034227-976c-483c-9c71-125deb82bbaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014967225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_loopback.4014967225
Directory /workspace/41.uart_loopback/latest

Test location /workspace/coverage/default/41.uart_perf.405603936
Short name T757
Test name
Test status
Simulation time 7432969332 ps
CPU time 329.27 seconds
Started Jun 10 05:14:31 PM PDT 24
Finished Jun 10 05:20:01 PM PDT 24
Peak memory 200352 kb
Host smart-03b14f82-7289-4f4e-95db-6ed81393991a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=405603936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.405603936
Directory /workspace/41.uart_perf/latest

Test location /workspace/coverage/default/41.uart_rx_oversample.988007882
Short name T707
Test name
Test status
Simulation time 7028627175 ps
CPU time 14.37 seconds
Started Jun 10 05:14:36 PM PDT 24
Finished Jun 10 05:14:51 PM PDT 24
Peak memory 197996 kb
Host smart-ee0ea314-803b-421e-9552-d8b2b3fd01b1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=988007882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.988007882
Directory /workspace/41.uart_rx_oversample/latest

Test location /workspace/coverage/default/41.uart_rx_parity_err.938229919
Short name T996
Test name
Test status
Simulation time 126935029949 ps
CPU time 116.88 seconds
Started Jun 10 05:14:38 PM PDT 24
Finished Jun 10 05:16:36 PM PDT 24
Peak memory 200348 kb
Host smart-3294bfb1-77e2-412b-94c1-71251ab246d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938229919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.938229919
Directory /workspace/41.uart_rx_parity_err/latest

Test location /workspace/coverage/default/41.uart_rx_start_bit_filter.3595557422
Short name T667
Test name
Test status
Simulation time 6861330789 ps
CPU time 1.85 seconds
Started Jun 10 05:14:38 PM PDT 24
Finished Jun 10 05:14:40 PM PDT 24
Peak memory 196324 kb
Host smart-f7f46ed3-7443-4495-82f2-bc9c2a652cdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595557422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.3595557422
Directory /workspace/41.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/41.uart_smoke.3171655809
Short name T677
Test name
Test status
Simulation time 955221741 ps
CPU time 1.29 seconds
Started Jun 10 05:14:39 PM PDT 24
Finished Jun 10 05:14:40 PM PDT 24
Peak memory 199956 kb
Host smart-75d71938-b493-4710-99e9-cea12c7778cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171655809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_smoke.3171655809
Directory /workspace/41.uart_smoke/latest

Test location /workspace/coverage/default/41.uart_tx_ovrd.1612155330
Short name T1044
Test name
Test status
Simulation time 1278408816 ps
CPU time 6.15 seconds
Started Jun 10 05:14:39 PM PDT 24
Finished Jun 10 05:14:46 PM PDT 24
Peak memory 199200 kb
Host smart-be81dc34-fff5-4bde-9f63-2fe2ac00de21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612155330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.1612155330
Directory /workspace/41.uart_tx_ovrd/latest

Test location /workspace/coverage/default/41.uart_tx_rx.1964214569
Short name T263
Test name
Test status
Simulation time 60106769136 ps
CPU time 27.76 seconds
Started Jun 10 05:14:42 PM PDT 24
Finished Jun 10 05:15:10 PM PDT 24
Peak memory 200408 kb
Host smart-d1afe3eb-0612-46a2-a8cf-34232b28bdda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964214569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.1964214569
Directory /workspace/41.uart_tx_rx/latest

Test location /workspace/coverage/default/42.uart_alert_test.1716978039
Short name T493
Test name
Test status
Simulation time 12504882 ps
CPU time 0.58 seconds
Started Jun 10 05:14:41 PM PDT 24
Finished Jun 10 05:14:42 PM PDT 24
Peak memory 195644 kb
Host smart-882c9485-e012-4824-8c61-99e43005eb5b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716978039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.1716978039
Directory /workspace/42.uart_alert_test/latest

Test location /workspace/coverage/default/42.uart_fifo_full.1794932026
Short name T827
Test name
Test status
Simulation time 20712916284 ps
CPU time 18.6 seconds
Started Jun 10 05:14:42 PM PDT 24
Finished Jun 10 05:15:01 PM PDT 24
Peak memory 200256 kb
Host smart-9fe09989-8418-4a2c-961e-c15792052223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794932026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.1794932026
Directory /workspace/42.uart_fifo_full/latest

Test location /workspace/coverage/default/42.uart_fifo_overflow.3634945664
Short name T165
Test name
Test status
Simulation time 22572245342 ps
CPU time 10.92 seconds
Started Jun 10 05:14:44 PM PDT 24
Finished Jun 10 05:14:55 PM PDT 24
Peak memory 199260 kb
Host smart-5dbccd06-57e1-4e6c-95dd-0a6f6d4f53b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634945664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.3634945664
Directory /workspace/42.uart_fifo_overflow/latest

Test location /workspace/coverage/default/42.uart_fifo_reset.2342308781
Short name T977
Test name
Test status
Simulation time 140517003496 ps
CPU time 100.08 seconds
Started Jun 10 05:14:38 PM PDT 24
Finished Jun 10 05:16:19 PM PDT 24
Peak memory 200292 kb
Host smart-53d73a35-844b-43af-bf6e-8bcd55297947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342308781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.2342308781
Directory /workspace/42.uart_fifo_reset/latest

Test location /workspace/coverage/default/42.uart_intr.1683817667
Short name T130
Test name
Test status
Simulation time 57870118134 ps
CPU time 92.19 seconds
Started Jun 10 05:14:41 PM PDT 24
Finished Jun 10 05:16:13 PM PDT 24
Peak memory 200372 kb
Host smart-27dcb61a-dbc0-4328-b52e-4f2661262a53
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683817667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.1683817667
Directory /workspace/42.uart_intr/latest

Test location /workspace/coverage/default/42.uart_long_xfer_wo_dly.3806780173
Short name T546
Test name
Test status
Simulation time 53090058595 ps
CPU time 309.84 seconds
Started Jun 10 05:14:42 PM PDT 24
Finished Jun 10 05:19:52 PM PDT 24
Peak memory 200172 kb
Host smart-00f10d37-0bea-41bf-a465-8dc040d15a03
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3806780173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.3806780173
Directory /workspace/42.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/42.uart_loopback.524571942
Short name T400
Test name
Test status
Simulation time 11848693224 ps
CPU time 14.23 seconds
Started Jun 10 05:14:41 PM PDT 24
Finished Jun 10 05:14:56 PM PDT 24
Peak memory 200140 kb
Host smart-15ef09ec-f344-436f-b6fd-6697317bf008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524571942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_loopback.524571942
Directory /workspace/42.uart_loopback/latest

Test location /workspace/coverage/default/42.uart_perf.1906165212
Short name T425
Test name
Test status
Simulation time 16627711632 ps
CPU time 92.35 seconds
Started Jun 10 05:14:42 PM PDT 24
Finished Jun 10 05:16:15 PM PDT 24
Peak memory 200376 kb
Host smart-22fa4059-7577-43ae-94f3-aa06bc43b1a8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1906165212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.1906165212
Directory /workspace/42.uart_perf/latest

Test location /workspace/coverage/default/42.uart_rx_oversample.25011447
Short name T660
Test name
Test status
Simulation time 6713373664 ps
CPU time 55.36 seconds
Started Jun 10 05:14:40 PM PDT 24
Finished Jun 10 05:15:35 PM PDT 24
Peak memory 199800 kb
Host smart-94b07059-f267-43c0-96bc-56a993775b95
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=25011447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.25011447
Directory /workspace/42.uart_rx_oversample/latest

Test location /workspace/coverage/default/42.uart_rx_parity_err.3361611537
Short name T67
Test name
Test status
Simulation time 51874999101 ps
CPU time 17.29 seconds
Started Jun 10 05:14:44 PM PDT 24
Finished Jun 10 05:15:01 PM PDT 24
Peak memory 200008 kb
Host smart-905f7551-503f-4a02-a019-5440e408d8b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361611537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.3361611537
Directory /workspace/42.uart_rx_parity_err/latest

Test location /workspace/coverage/default/42.uart_rx_start_bit_filter.3972960829
Short name T714
Test name
Test status
Simulation time 3226877954 ps
CPU time 5.14 seconds
Started Jun 10 05:14:41 PM PDT 24
Finished Jun 10 05:14:47 PM PDT 24
Peak memory 196260 kb
Host smart-cf55ac9c-ae43-41b7-9c90-591646cc75c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972960829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.3972960829
Directory /workspace/42.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/42.uart_smoke.3655424267
Short name T449
Test name
Test status
Simulation time 293914038 ps
CPU time 1.89 seconds
Started Jun 10 05:14:43 PM PDT 24
Finished Jun 10 05:14:45 PM PDT 24
Peak memory 198744 kb
Host smart-447e8293-4e85-4874-a069-6f446ca01dd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655424267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_smoke.3655424267
Directory /workspace/42.uart_smoke/latest

Test location /workspace/coverage/default/42.uart_stress_all_with_rand_reset.4173828583
Short name T1008
Test name
Test status
Simulation time 33671880878 ps
CPU time 327.03 seconds
Started Jun 10 05:14:41 PM PDT 24
Finished Jun 10 05:20:08 PM PDT 24
Peak memory 216884 kb
Host smart-50abbd81-acaa-49d7-856b-808e380bed86
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173828583 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 42.uart_stress_all_with_rand_reset.4173828583
Directory /workspace/42.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.uart_tx_ovrd.1744825908
Short name T286
Test name
Test status
Simulation time 2179788807 ps
CPU time 1.98 seconds
Started Jun 10 05:14:43 PM PDT 24
Finished Jun 10 05:14:45 PM PDT 24
Peak memory 198928 kb
Host smart-8bb3c379-89d3-423a-9fc1-65e62146123a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744825908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.1744825908
Directory /workspace/42.uart_tx_ovrd/latest

Test location /workspace/coverage/default/42.uart_tx_rx.1357087135
Short name T642
Test name
Test status
Simulation time 55285698894 ps
CPU time 69 seconds
Started Jun 10 05:14:45 PM PDT 24
Finished Jun 10 05:15:55 PM PDT 24
Peak memory 200204 kb
Host smart-e061e9fe-667f-45db-ab06-b459dc1c5a2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357087135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.1357087135
Directory /workspace/42.uart_tx_rx/latest

Test location /workspace/coverage/default/43.uart_alert_test.97050394
Short name T500
Test name
Test status
Simulation time 32242559 ps
CPU time 0.57 seconds
Started Jun 10 05:14:44 PM PDT 24
Finished Jun 10 05:14:45 PM PDT 24
Peak memory 195504 kb
Host smart-7ad068d6-516e-4144-adab-1797e39bd9ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97050394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.97050394
Directory /workspace/43.uart_alert_test/latest

Test location /workspace/coverage/default/43.uart_fifo_full.4172822448
Short name T555
Test name
Test status
Simulation time 104867893506 ps
CPU time 36.09 seconds
Started Jun 10 05:14:36 PM PDT 24
Finished Jun 10 05:15:13 PM PDT 24
Peak memory 200224 kb
Host smart-ae7dc1c6-fb82-495b-9c0f-f571a9111a97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172822448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.4172822448
Directory /workspace/43.uart_fifo_full/latest

Test location /workspace/coverage/default/43.uart_fifo_overflow.3480920877
Short name T341
Test name
Test status
Simulation time 246829329567 ps
CPU time 57.3 seconds
Started Jun 10 05:14:38 PM PDT 24
Finished Jun 10 05:15:36 PM PDT 24
Peak memory 200240 kb
Host smart-abb029d2-6333-41a1-8192-da485b9a7895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480920877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.3480920877
Directory /workspace/43.uart_fifo_overflow/latest

Test location /workspace/coverage/default/43.uart_fifo_reset.1811618958
Short name T669
Test name
Test status
Simulation time 70530786176 ps
CPU time 25.15 seconds
Started Jun 10 05:14:36 PM PDT 24
Finished Jun 10 05:15:02 PM PDT 24
Peak memory 200376 kb
Host smart-df9e8227-71ca-46fb-8eb0-f9d62a3520c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811618958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.1811618958
Directory /workspace/43.uart_fifo_reset/latest

Test location /workspace/coverage/default/43.uart_long_xfer_wo_dly.408935354
Short name T467
Test name
Test status
Simulation time 56266771986 ps
CPU time 160.63 seconds
Started Jun 10 05:14:44 PM PDT 24
Finished Jun 10 05:17:25 PM PDT 24
Peak memory 200108 kb
Host smart-dbdd9e10-c429-4720-956f-3717f5e8615b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=408935354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.408935354
Directory /workspace/43.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/43.uart_loopback.3849640099
Short name T390
Test name
Test status
Simulation time 1883166427 ps
CPU time 0.99 seconds
Started Jun 10 05:14:40 PM PDT 24
Finished Jun 10 05:14:41 PM PDT 24
Peak memory 196356 kb
Host smart-df0447d0-b7b3-4201-8922-13688b2ba2aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849640099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_loopback.3849640099
Directory /workspace/43.uart_loopback/latest

Test location /workspace/coverage/default/43.uart_perf.1222354394
Short name T1060
Test name
Test status
Simulation time 22891097547 ps
CPU time 106.02 seconds
Started Jun 10 05:14:46 PM PDT 24
Finished Jun 10 05:16:33 PM PDT 24
Peak memory 200260 kb
Host smart-24087d1f-7d4f-4cf9-8c1f-e3974a5c90a2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1222354394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.1222354394
Directory /workspace/43.uart_perf/latest

Test location /workspace/coverage/default/43.uart_rx_oversample.3741745661
Short name T17
Test name
Test status
Simulation time 5381802323 ps
CPU time 3.06 seconds
Started Jun 10 05:14:36 PM PDT 24
Finished Jun 10 05:14:40 PM PDT 24
Peak memory 199400 kb
Host smart-ef7700e7-05ef-44d0-9b36-42b295fda385
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3741745661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.3741745661
Directory /workspace/43.uart_rx_oversample/latest

Test location /workspace/coverage/default/43.uart_rx_parity_err.3677364432
Short name T686
Test name
Test status
Simulation time 15441558225 ps
CPU time 27.31 seconds
Started Jun 10 05:14:43 PM PDT 24
Finished Jun 10 05:15:11 PM PDT 24
Peak memory 200256 kb
Host smart-99821536-cc7c-47ad-ac1c-13fc78f500aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677364432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.3677364432
Directory /workspace/43.uart_rx_parity_err/latest

Test location /workspace/coverage/default/43.uart_rx_start_bit_filter.1797215348
Short name T622
Test name
Test status
Simulation time 1834275728 ps
CPU time 1.3 seconds
Started Jun 10 05:14:41 PM PDT 24
Finished Jun 10 05:14:43 PM PDT 24
Peak memory 195648 kb
Host smart-31811c5d-c7aa-43a6-a2b9-94dd29dbdfb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797215348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.1797215348
Directory /workspace/43.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/43.uart_smoke.1990634186
Short name T475
Test name
Test status
Simulation time 5567018494 ps
CPU time 6.83 seconds
Started Jun 10 05:14:34 PM PDT 24
Finished Jun 10 05:14:41 PM PDT 24
Peak memory 200232 kb
Host smart-5bd6ff9c-0697-4347-a325-5d9a753394db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990634186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_smoke.1990634186
Directory /workspace/43.uart_smoke/latest

Test location /workspace/coverage/default/43.uart_stress_all.798489508
Short name T279
Test name
Test status
Simulation time 317505430050 ps
CPU time 535.61 seconds
Started Jun 10 05:14:42 PM PDT 24
Finished Jun 10 05:23:38 PM PDT 24
Peak memory 200216 kb
Host smart-dedbf89d-abf4-4114-b8b1-3070ac7f4ef7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798489508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.798489508
Directory /workspace/43.uart_stress_all/latest

Test location /workspace/coverage/default/43.uart_tx_ovrd.1966702639
Short name T759
Test name
Test status
Simulation time 8156581384 ps
CPU time 10.99 seconds
Started Jun 10 05:14:41 PM PDT 24
Finished Jun 10 05:14:52 PM PDT 24
Peak memory 200288 kb
Host smart-d9597432-cca3-46f2-8e86-1f510ec5d5c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966702639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.1966702639
Directory /workspace/43.uart_tx_ovrd/latest

Test location /workspace/coverage/default/43.uart_tx_rx.3563720297
Short name T8
Test name
Test status
Simulation time 138941623345 ps
CPU time 66.03 seconds
Started Jun 10 05:14:41 PM PDT 24
Finished Jun 10 05:15:48 PM PDT 24
Peak memory 200244 kb
Host smart-014c7c92-f48e-412b-977d-4bc98eb9dd68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563720297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.3563720297
Directory /workspace/43.uart_tx_rx/latest

Test location /workspace/coverage/default/44.uart_alert_test.682639635
Short name T765
Test name
Test status
Simulation time 116248929 ps
CPU time 0.55 seconds
Started Jun 10 05:14:45 PM PDT 24
Finished Jun 10 05:14:46 PM PDT 24
Peak memory 195668 kb
Host smart-c2f33a00-4f43-4209-ba11-04c2d24735a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682639635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.682639635
Directory /workspace/44.uart_alert_test/latest

Test location /workspace/coverage/default/44.uart_fifo_full.1589951016
Short name T1027
Test name
Test status
Simulation time 92643647380 ps
CPU time 133.28 seconds
Started Jun 10 05:14:50 PM PDT 24
Finished Jun 10 05:17:03 PM PDT 24
Peak memory 200312 kb
Host smart-0105c4da-60bb-4f01-a5c0-2dd0a9964a89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589951016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.1589951016
Directory /workspace/44.uart_fifo_full/latest

Test location /workspace/coverage/default/44.uart_fifo_overflow.795777679
Short name T1023
Test name
Test status
Simulation time 53468944452 ps
CPU time 30.93 seconds
Started Jun 10 05:14:47 PM PDT 24
Finished Jun 10 05:15:18 PM PDT 24
Peak memory 200300 kb
Host smart-eb206a3e-fab6-4926-bb3b-d64526b7433f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795777679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.795777679
Directory /workspace/44.uart_fifo_overflow/latest

Test location /workspace/coverage/default/44.uart_fifo_reset.955281209
Short name T277
Test name
Test status
Simulation time 147582539965 ps
CPU time 326.82 seconds
Started Jun 10 05:14:43 PM PDT 24
Finished Jun 10 05:20:10 PM PDT 24
Peak memory 200296 kb
Host smart-586766c2-a276-430f-a1b8-f1ec0c3c970a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955281209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.955281209
Directory /workspace/44.uart_fifo_reset/latest

Test location /workspace/coverage/default/44.uart_intr.110385656
Short name T962
Test name
Test status
Simulation time 53371347715 ps
CPU time 100.63 seconds
Started Jun 10 05:14:41 PM PDT 24
Finished Jun 10 05:16:22 PM PDT 24
Peak memory 199348 kb
Host smart-1110ac51-c703-40f7-bb87-30abe6dd76a5
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110385656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.110385656
Directory /workspace/44.uart_intr/latest

Test location /workspace/coverage/default/44.uart_long_xfer_wo_dly.1654517962
Short name T640
Test name
Test status
Simulation time 103222667755 ps
CPU time 389.91 seconds
Started Jun 10 05:14:45 PM PDT 24
Finished Jun 10 05:21:16 PM PDT 24
Peak memory 200344 kb
Host smart-14b360fd-9568-4f8c-8c0f-6c10814f73ff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1654517962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.1654517962
Directory /workspace/44.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/44.uart_loopback.76709078
Short name T355
Test name
Test status
Simulation time 2893715180 ps
CPU time 5.81 seconds
Started Jun 10 05:14:43 PM PDT 24
Finished Jun 10 05:14:50 PM PDT 24
Peak memory 196604 kb
Host smart-1b3e0820-fd2b-4ec1-b7d9-e9e6214cb999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76709078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_loopback.76709078
Directory /workspace/44.uart_loopback/latest

Test location /workspace/coverage/default/44.uart_perf.2076086958
Short name T419
Test name
Test status
Simulation time 9550625902 ps
CPU time 366.07 seconds
Started Jun 10 05:14:41 PM PDT 24
Finished Jun 10 05:20:48 PM PDT 24
Peak memory 200264 kb
Host smart-0fbba92b-3a77-43c4-a9e7-b25fde64a926
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2076086958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.2076086958
Directory /workspace/44.uart_perf/latest

Test location /workspace/coverage/default/44.uart_rx_oversample.3749154040
Short name T700
Test name
Test status
Simulation time 6000552571 ps
CPU time 9.27 seconds
Started Jun 10 05:14:44 PM PDT 24
Finished Jun 10 05:14:54 PM PDT 24
Peak memory 198488 kb
Host smart-62b12bee-36d1-4d8f-a516-79395ea02895
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3749154040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.3749154040
Directory /workspace/44.uart_rx_oversample/latest

Test location /workspace/coverage/default/44.uart_rx_parity_err.412141807
Short name T143
Test name
Test status
Simulation time 68674285112 ps
CPU time 14.03 seconds
Started Jun 10 05:14:45 PM PDT 24
Finished Jun 10 05:15:00 PM PDT 24
Peak memory 200144 kb
Host smart-7dc82142-bd8c-4389-8092-c1913d0127f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412141807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.412141807
Directory /workspace/44.uart_rx_parity_err/latest

Test location /workspace/coverage/default/44.uart_rx_start_bit_filter.2344534361
Short name T338
Test name
Test status
Simulation time 4394068912 ps
CPU time 1.43 seconds
Started Jun 10 05:14:42 PM PDT 24
Finished Jun 10 05:14:44 PM PDT 24
Peak memory 196416 kb
Host smart-aafdd7fb-2963-4879-b5b2-4e51ad65bb86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344534361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.2344534361
Directory /workspace/44.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/44.uart_smoke.1513314777
Short name T424
Test name
Test status
Simulation time 6085118039 ps
CPU time 16.33 seconds
Started Jun 10 05:14:44 PM PDT 24
Finished Jun 10 05:15:00 PM PDT 24
Peak memory 199548 kb
Host smart-ec1f8699-1435-410d-a64f-328ba4bfbfd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513314777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_smoke.1513314777
Directory /workspace/44.uart_smoke/latest

Test location /workspace/coverage/default/44.uart_stress_all_with_rand_reset.949335692
Short name T1003
Test name
Test status
Simulation time 63795657856 ps
CPU time 333.17 seconds
Started Jun 10 05:14:43 PM PDT 24
Finished Jun 10 05:20:16 PM PDT 24
Peak memory 208680 kb
Host smart-9744ad3d-5733-44a9-a96e-4705b0851d30
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949335692 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 44.uart_stress_all_with_rand_reset.949335692
Directory /workspace/44.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.uart_tx_ovrd.1598913091
Short name T817
Test name
Test status
Simulation time 1350825589 ps
CPU time 2.58 seconds
Started Jun 10 05:14:42 PM PDT 24
Finished Jun 10 05:14:45 PM PDT 24
Peak memory 199128 kb
Host smart-07c54998-759a-47ad-a8b0-60c32c2c2021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598913091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.1598913091
Directory /workspace/44.uart_tx_ovrd/latest

Test location /workspace/coverage/default/44.uart_tx_rx.1999180772
Short name T961
Test name
Test status
Simulation time 79985625780 ps
CPU time 136.54 seconds
Started Jun 10 05:14:45 PM PDT 24
Finished Jun 10 05:17:03 PM PDT 24
Peak memory 200340 kb
Host smart-acd51579-5dde-4279-b4d7-ce8d5931b5c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999180772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.1999180772
Directory /workspace/44.uart_tx_rx/latest

Test location /workspace/coverage/default/45.uart_alert_test.96154487
Short name T104
Test name
Test status
Simulation time 49696110 ps
CPU time 0.53 seconds
Started Jun 10 05:14:44 PM PDT 24
Finished Jun 10 05:14:45 PM PDT 24
Peak memory 195996 kb
Host smart-bd9b24c4-af80-433d-b38d-0a74fe66b057
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96154487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.96154487
Directory /workspace/45.uart_alert_test/latest

Test location /workspace/coverage/default/45.uart_fifo_full.1189173912
Short name T900
Test name
Test status
Simulation time 15965674399 ps
CPU time 26.06 seconds
Started Jun 10 05:14:47 PM PDT 24
Finished Jun 10 05:15:13 PM PDT 24
Peak memory 200068 kb
Host smart-ed89a62d-8836-4439-8451-b18c7d7b20ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189173912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.1189173912
Directory /workspace/45.uart_fifo_full/latest

Test location /workspace/coverage/default/45.uart_fifo_overflow.590338286
Short name T1074
Test name
Test status
Simulation time 83077217445 ps
CPU time 213.33 seconds
Started Jun 10 05:14:50 PM PDT 24
Finished Jun 10 05:18:24 PM PDT 24
Peak memory 200344 kb
Host smart-009da772-b624-4e89-bb79-ca530f5a7a01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590338286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.590338286
Directory /workspace/45.uart_fifo_overflow/latest

Test location /workspace/coverage/default/45.uart_intr.1820507084
Short name T391
Test name
Test status
Simulation time 312497070562 ps
CPU time 37.87 seconds
Started Jun 10 05:14:50 PM PDT 24
Finished Jun 10 05:15:29 PM PDT 24
Peak memory 200264 kb
Host smart-df2de3c0-a35b-4feb-ac33-280bca300e8a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820507084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.1820507084
Directory /workspace/45.uart_intr/latest

Test location /workspace/coverage/default/45.uart_long_xfer_wo_dly.1699199316
Short name T41
Test name
Test status
Simulation time 144302440558 ps
CPU time 436.44 seconds
Started Jun 10 05:14:51 PM PDT 24
Finished Jun 10 05:22:07 PM PDT 24
Peak memory 200360 kb
Host smart-541feba5-ee74-478f-8ee3-3c4993f9a419
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1699199316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.1699199316
Directory /workspace/45.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/45.uart_loopback.2393668478
Short name T703
Test name
Test status
Simulation time 6385488966 ps
CPU time 4.61 seconds
Started Jun 10 05:14:46 PM PDT 24
Finished Jun 10 05:14:51 PM PDT 24
Peak memory 199544 kb
Host smart-b6b83290-4a7c-46b3-903a-da136cdb7fef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393668478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_loopback.2393668478
Directory /workspace/45.uart_loopback/latest

Test location /workspace/coverage/default/45.uart_perf.2093049857
Short name T1073
Test name
Test status
Simulation time 17171145015 ps
CPU time 198.03 seconds
Started Jun 10 05:14:51 PM PDT 24
Finished Jun 10 05:18:10 PM PDT 24
Peak memory 200160 kb
Host smart-a8e57af5-432a-47f6-90eb-480b17d48d8c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2093049857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.2093049857
Directory /workspace/45.uart_perf/latest

Test location /workspace/coverage/default/45.uart_rx_oversample.3021764086
Short name T14
Test name
Test status
Simulation time 6282688773 ps
CPU time 12.27 seconds
Started Jun 10 05:14:45 PM PDT 24
Finished Jun 10 05:14:57 PM PDT 24
Peak memory 198968 kb
Host smart-8a3391c1-25d6-470f-9333-68e3cd9c09b6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3021764086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.3021764086
Directory /workspace/45.uart_rx_oversample/latest

Test location /workspace/coverage/default/45.uart_rx_parity_err.3544733660
Short name T283
Test name
Test status
Simulation time 213348549946 ps
CPU time 148.66 seconds
Started Jun 10 05:14:48 PM PDT 24
Finished Jun 10 05:17:17 PM PDT 24
Peak memory 200300 kb
Host smart-f94d2e38-73c9-4ab1-a7a1-25e5c548bbad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544733660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.3544733660
Directory /workspace/45.uart_rx_parity_err/latest

Test location /workspace/coverage/default/45.uart_rx_start_bit_filter.874339142
Short name T457
Test name
Test status
Simulation time 6750420228 ps
CPU time 11.29 seconds
Started Jun 10 05:14:51 PM PDT 24
Finished Jun 10 05:15:02 PM PDT 24
Peak memory 196444 kb
Host smart-dc3249d0-ba00-4ece-8aa9-c6fb51879c70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874339142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.874339142
Directory /workspace/45.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/45.uart_smoke.1620575764
Short name T64
Test name
Test status
Simulation time 291349125 ps
CPU time 1.57 seconds
Started Jun 10 05:14:51 PM PDT 24
Finished Jun 10 05:14:53 PM PDT 24
Peak memory 199144 kb
Host smart-dd170428-00f9-4226-8f24-7ad085f1dac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620575764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_smoke.1620575764
Directory /workspace/45.uart_smoke/latest

Test location /workspace/coverage/default/45.uart_stress_all.2426389989
Short name T1064
Test name
Test status
Simulation time 27257971111 ps
CPU time 23.64 seconds
Started Jun 10 05:14:50 PM PDT 24
Finished Jun 10 05:15:13 PM PDT 24
Peak memory 200248 kb
Host smart-68c137f4-27bf-4f32-ace2-64164480126a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426389989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.2426389989
Directory /workspace/45.uart_stress_all/latest

Test location /workspace/coverage/default/45.uart_tx_ovrd.4087011497
Short name T1071
Test name
Test status
Simulation time 7312014129 ps
CPU time 30.65 seconds
Started Jun 10 05:14:49 PM PDT 24
Finished Jun 10 05:15:20 PM PDT 24
Peak memory 200244 kb
Host smart-c3153f30-a647-463b-8c46-7749abcb5c7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087011497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.4087011497
Directory /workspace/45.uart_tx_ovrd/latest

Test location /workspace/coverage/default/45.uart_tx_rx.1666273425
Short name T1040
Test name
Test status
Simulation time 56809850216 ps
CPU time 34.81 seconds
Started Jun 10 05:14:51 PM PDT 24
Finished Jun 10 05:15:26 PM PDT 24
Peak memory 200256 kb
Host smart-01f68ef9-76b9-467b-81c2-1bd641a2e6bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666273425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.1666273425
Directory /workspace/45.uart_tx_rx/latest

Test location /workspace/coverage/default/46.uart_alert_test.50016146
Short name T865
Test name
Test status
Simulation time 16715096 ps
CPU time 0.57 seconds
Started Jun 10 05:14:56 PM PDT 24
Finished Jun 10 05:14:57 PM PDT 24
Peak memory 194572 kb
Host smart-fbd0a12a-cc04-4fbb-a3a7-63884c0fb2fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50016146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.50016146
Directory /workspace/46.uart_alert_test/latest

Test location /workspace/coverage/default/46.uart_fifo_full.1494603774
Short name T732
Test name
Test status
Simulation time 66262369852 ps
CPU time 46.89 seconds
Started Jun 10 05:14:55 PM PDT 24
Finished Jun 10 05:15:42 PM PDT 24
Peak memory 200212 kb
Host smart-d7deac17-1e06-4aa6-a356-69ec1798cd8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494603774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.1494603774
Directory /workspace/46.uart_fifo_full/latest

Test location /workspace/coverage/default/46.uart_fifo_overflow.2186192094
Short name T288
Test name
Test status
Simulation time 121076803627 ps
CPU time 189.88 seconds
Started Jun 10 05:14:55 PM PDT 24
Finished Jun 10 05:18:05 PM PDT 24
Peak memory 200256 kb
Host smart-bfadbe38-7841-4b38-ab61-c67c2100c3ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186192094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.2186192094
Directory /workspace/46.uart_fifo_overflow/latest

Test location /workspace/coverage/default/46.uart_fifo_reset.2586348322
Short name T147
Test name
Test status
Simulation time 104532559795 ps
CPU time 85.14 seconds
Started Jun 10 05:14:46 PM PDT 24
Finished Jun 10 05:16:11 PM PDT 24
Peak memory 200388 kb
Host smart-ae1c0e10-cfbd-413b-a96e-18b0cab4bd4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586348322 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.2586348322
Directory /workspace/46.uart_fifo_reset/latest

Test location /workspace/coverage/default/46.uart_intr.3756903068
Short name T680
Test name
Test status
Simulation time 36754066012 ps
CPU time 47.76 seconds
Started Jun 10 05:14:48 PM PDT 24
Finished Jun 10 05:15:36 PM PDT 24
Peak memory 197652 kb
Host smart-0723acc4-27a0-4899-ad9d-06b9ef1854d0
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756903068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.3756903068
Directory /workspace/46.uart_intr/latest

Test location /workspace/coverage/default/46.uart_long_xfer_wo_dly.1146565206
Short name T418
Test name
Test status
Simulation time 145207581790 ps
CPU time 301.25 seconds
Started Jun 10 05:14:55 PM PDT 24
Finished Jun 10 05:19:57 PM PDT 24
Peak memory 200368 kb
Host smart-3f007292-2f33-4d0a-9033-00467d003848
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1146565206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.1146565206
Directory /workspace/46.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/46.uart_loopback.3322982616
Short name T384
Test name
Test status
Simulation time 4782866838 ps
CPU time 2.93 seconds
Started Jun 10 05:14:47 PM PDT 24
Finished Jun 10 05:14:51 PM PDT 24
Peak memory 196600 kb
Host smart-eddd9807-a35f-4b10-8db4-b9446cc579c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322982616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_loopback.3322982616
Directory /workspace/46.uart_loopback/latest

Test location /workspace/coverage/default/46.uart_perf.4036457001
Short name T310
Test name
Test status
Simulation time 11107280943 ps
CPU time 608.53 seconds
Started Jun 10 05:14:56 PM PDT 24
Finished Jun 10 05:25:05 PM PDT 24
Peak memory 200148 kb
Host smart-7cf367d2-5b66-47c4-b063-16fdddbc0e81
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4036457001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.4036457001
Directory /workspace/46.uart_perf/latest

Test location /workspace/coverage/default/46.uart_rx_oversample.2699912255
Short name T438
Test name
Test status
Simulation time 4390548377 ps
CPU time 4.13 seconds
Started Jun 10 05:14:53 PM PDT 24
Finished Jun 10 05:14:57 PM PDT 24
Peak memory 200356 kb
Host smart-b1305c2c-abac-495f-9cb6-b109e050b700
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2699912255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.2699912255
Directory /workspace/46.uart_rx_oversample/latest

Test location /workspace/coverage/default/46.uart_rx_parity_err.4253213483
Short name T664
Test name
Test status
Simulation time 51859351115 ps
CPU time 70.01 seconds
Started Jun 10 05:14:54 PM PDT 24
Finished Jun 10 05:16:05 PM PDT 24
Peak memory 200260 kb
Host smart-266c5d0a-e8cc-44dc-af1e-214d720dacf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253213483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.4253213483
Directory /workspace/46.uart_rx_parity_err/latest

Test location /workspace/coverage/default/46.uart_rx_start_bit_filter.2217267606
Short name T989
Test name
Test status
Simulation time 43635343737 ps
CPU time 15.45 seconds
Started Jun 10 05:14:55 PM PDT 24
Finished Jun 10 05:15:11 PM PDT 24
Peak memory 195976 kb
Host smart-e76b7537-20c0-4055-87d3-9798bed70c5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217267606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.2217267606
Directory /workspace/46.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/46.uart_smoke.513378443
Short name T658
Test name
Test status
Simulation time 6110001557 ps
CPU time 7.47 seconds
Started Jun 10 05:14:51 PM PDT 24
Finished Jun 10 05:14:59 PM PDT 24
Peak memory 200064 kb
Host smart-7d876830-1e68-4cc0-ab4b-3db67094240c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513378443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_smoke.513378443
Directory /workspace/46.uart_smoke/latest

Test location /workspace/coverage/default/46.uart_stress_all.3102178537
Short name T182
Test name
Test status
Simulation time 116967004770 ps
CPU time 168.13 seconds
Started Jun 10 05:14:54 PM PDT 24
Finished Jun 10 05:17:43 PM PDT 24
Peak memory 200248 kb
Host smart-6c4405bc-5c05-4549-8afd-5a3159e9f272
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102178537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.3102178537
Directory /workspace/46.uart_stress_all/latest

Test location /workspace/coverage/default/46.uart_stress_all_with_rand_reset.3927606763
Short name T223
Test name
Test status
Simulation time 125037596229 ps
CPU time 527.29 seconds
Started Jun 10 05:14:52 PM PDT 24
Finished Jun 10 05:23:40 PM PDT 24
Peak memory 216736 kb
Host smart-669ea9e5-432f-4eb6-b370-0dcfc8a6c145
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927606763 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 46.uart_stress_all_with_rand_reset.3927606763
Directory /workspace/46.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.uart_tx_ovrd.2934939802
Short name T1070
Test name
Test status
Simulation time 947805439 ps
CPU time 3.76 seconds
Started Jun 10 05:14:50 PM PDT 24
Finished Jun 10 05:14:54 PM PDT 24
Peak memory 199468 kb
Host smart-32f7a089-0d75-4412-9b4b-e38bf0c5dab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934939802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.2934939802
Directory /workspace/46.uart_tx_ovrd/latest

Test location /workspace/coverage/default/46.uart_tx_rx.1117878610
Short name T521
Test name
Test status
Simulation time 68371384765 ps
CPU time 117.35 seconds
Started Jun 10 05:14:47 PM PDT 24
Finished Jun 10 05:16:45 PM PDT 24
Peak memory 200252 kb
Host smart-26eee271-b810-46d3-82a8-89c4d3a52686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117878610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.1117878610
Directory /workspace/46.uart_tx_rx/latest

Test location /workspace/coverage/default/47.uart_alert_test.1923112112
Short name T778
Test name
Test status
Simulation time 20938509 ps
CPU time 0.55 seconds
Started Jun 10 05:14:48 PM PDT 24
Finished Jun 10 05:14:49 PM PDT 24
Peak memory 194608 kb
Host smart-7a8f59a3-d321-44f1-92ba-1e828ac0e296
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923112112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.1923112112
Directory /workspace/47.uart_alert_test/latest

Test location /workspace/coverage/default/47.uart_fifo_full.2855807493
Short name T998
Test name
Test status
Simulation time 68495677340 ps
CPU time 40.45 seconds
Started Jun 10 05:14:51 PM PDT 24
Finished Jun 10 05:15:32 PM PDT 24
Peak memory 200184 kb
Host smart-f4c2cd42-d97e-4e59-b6a8-88dd6d460996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855807493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.2855807493
Directory /workspace/47.uart_fifo_full/latest

Test location /workspace/coverage/default/47.uart_fifo_overflow.2757717757
Short name T946
Test name
Test status
Simulation time 394717331557 ps
CPU time 91.13 seconds
Started Jun 10 05:14:49 PM PDT 24
Finished Jun 10 05:16:21 PM PDT 24
Peak memory 200312 kb
Host smart-22256bb8-73fb-4301-8a3d-67c043da3131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757717757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.2757717757
Directory /workspace/47.uart_fifo_overflow/latest

Test location /workspace/coverage/default/47.uart_long_xfer_wo_dly.1104355048
Short name T519
Test name
Test status
Simulation time 202389322017 ps
CPU time 1490.09 seconds
Started Jun 10 05:14:52 PM PDT 24
Finished Jun 10 05:39:43 PM PDT 24
Peak memory 200188 kb
Host smart-aed3f68a-ca92-4525-b849-5535817696b2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1104355048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.1104355048
Directory /workspace/47.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/47.uart_loopback.3709481297
Short name T407
Test name
Test status
Simulation time 9433776352 ps
CPU time 5.73 seconds
Started Jun 10 05:14:56 PM PDT 24
Finished Jun 10 05:15:02 PM PDT 24
Peak memory 199040 kb
Host smart-47451d22-0464-4b1e-81b8-dd1022bea9f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709481297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_loopback.3709481297
Directory /workspace/47.uart_loopback/latest

Test location /workspace/coverage/default/47.uart_perf.2571773371
Short name T939
Test name
Test status
Simulation time 5326973144 ps
CPU time 307.45 seconds
Started Jun 10 05:14:55 PM PDT 24
Finished Jun 10 05:20:03 PM PDT 24
Peak memory 200340 kb
Host smart-0271cbe1-35a9-4e93-8a33-c9c70d78af06
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2571773371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.2571773371
Directory /workspace/47.uart_perf/latest

Test location /workspace/coverage/default/47.uart_rx_oversample.2775520387
Short name T357
Test name
Test status
Simulation time 2026027933 ps
CPU time 5.87 seconds
Started Jun 10 05:14:50 PM PDT 24
Finished Jun 10 05:14:56 PM PDT 24
Peak memory 198460 kb
Host smart-de671198-ae4a-4891-b917-7535071a13ce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2775520387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.2775520387
Directory /workspace/47.uart_rx_oversample/latest

Test location /workspace/coverage/default/47.uart_rx_parity_err.538217094
Short name T254
Test name
Test status
Simulation time 123657655541 ps
CPU time 56.01 seconds
Started Jun 10 05:14:56 PM PDT 24
Finished Jun 10 05:15:52 PM PDT 24
Peak memory 200068 kb
Host smart-7c4651ee-b2fe-4d75-bff6-654805f2e3f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538217094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.538217094
Directory /workspace/47.uart_rx_parity_err/latest

Test location /workspace/coverage/default/47.uart_rx_start_bit_filter.330065329
Short name T495
Test name
Test status
Simulation time 3300621267 ps
CPU time 2.11 seconds
Started Jun 10 05:14:56 PM PDT 24
Finished Jun 10 05:14:58 PM PDT 24
Peak memory 196540 kb
Host smart-dc84b58d-0592-423c-8099-c4a9fef19ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330065329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.330065329
Directory /workspace/47.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/47.uart_smoke.3582998708
Short name T623
Test name
Test status
Simulation time 156703144 ps
CPU time 0.8 seconds
Started Jun 10 05:14:56 PM PDT 24
Finished Jun 10 05:14:57 PM PDT 24
Peak memory 198112 kb
Host smart-11c92f1c-9fe9-48da-9ab8-1268e4368326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582998708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_smoke.3582998708
Directory /workspace/47.uart_smoke/latest

Test location /workspace/coverage/default/47.uart_stress_all.2948706384
Short name T1063
Test name
Test status
Simulation time 232243263642 ps
CPU time 89.01 seconds
Started Jun 10 05:14:49 PM PDT 24
Finished Jun 10 05:16:19 PM PDT 24
Peak memory 200328 kb
Host smart-e4de1982-b964-4d24-9520-a400d29515c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948706384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.2948706384
Directory /workspace/47.uart_stress_all/latest

Test location /workspace/coverage/default/47.uart_tx_ovrd.1674681143
Short name T709
Test name
Test status
Simulation time 3327076755 ps
CPU time 2 seconds
Started Jun 10 05:14:53 PM PDT 24
Finished Jun 10 05:14:56 PM PDT 24
Peak memory 199336 kb
Host smart-765c54a8-e95e-4a1f-877b-151ab0233466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674681143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.1674681143
Directory /workspace/47.uart_tx_ovrd/latest

Test location /workspace/coverage/default/47.uart_tx_rx.270294781
Short name T446
Test name
Test status
Simulation time 41101493747 ps
CPU time 18.32 seconds
Started Jun 10 05:14:50 PM PDT 24
Finished Jun 10 05:15:08 PM PDT 24
Peak memory 200280 kb
Host smart-e2ac2d72-dc87-4875-9f66-987eacbf4557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270294781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.270294781
Directory /workspace/47.uart_tx_rx/latest

Test location /workspace/coverage/default/48.uart_alert_test.4283270343
Short name T587
Test name
Test status
Simulation time 21261832 ps
CPU time 0.54 seconds
Started Jun 10 05:14:54 PM PDT 24
Finished Jun 10 05:14:55 PM PDT 24
Peak memory 195916 kb
Host smart-ea94f5a6-42df-4f34-8662-2145207c4756
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283270343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.4283270343
Directory /workspace/48.uart_alert_test/latest

Test location /workspace/coverage/default/48.uart_fifo_full.1574166349
Short name T50
Test name
Test status
Simulation time 42075371051 ps
CPU time 71.55 seconds
Started Jun 10 05:14:57 PM PDT 24
Finished Jun 10 05:16:09 PM PDT 24
Peak memory 200292 kb
Host smart-113e2ca4-f8d2-4431-9b2a-82e7198444d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574166349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.1574166349
Directory /workspace/48.uart_fifo_full/latest

Test location /workspace/coverage/default/48.uart_fifo_overflow.1402806850
Short name T749
Test name
Test status
Simulation time 101141257520 ps
CPU time 191.3 seconds
Started Jun 10 05:14:54 PM PDT 24
Finished Jun 10 05:18:06 PM PDT 24
Peak memory 200524 kb
Host smart-bbe711e0-7151-4c10-b0df-9c5ca43b7b70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402806850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.1402806850
Directory /workspace/48.uart_fifo_overflow/latest

Test location /workspace/coverage/default/48.uart_intr.4162649907
Short name T40
Test name
Test status
Simulation time 9662184229 ps
CPU time 4.56 seconds
Started Jun 10 05:14:54 PM PDT 24
Finished Jun 10 05:14:58 PM PDT 24
Peak memory 197000 kb
Host smart-cabaf245-c9ee-4096-a46b-e5e90ab8f662
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162649907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.4162649907
Directory /workspace/48.uart_intr/latest

Test location /workspace/coverage/default/48.uart_long_xfer_wo_dly.1041246866
Short name T899
Test name
Test status
Simulation time 56710714810 ps
CPU time 213.24 seconds
Started Jun 10 05:14:54 PM PDT 24
Finished Jun 10 05:18:28 PM PDT 24
Peak memory 200264 kb
Host smart-ab0bec07-7e7a-4d93-9ecd-c49b31b35835
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1041246866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.1041246866
Directory /workspace/48.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/48.uart_loopback.333856915
Short name T464
Test name
Test status
Simulation time 5421176647 ps
CPU time 10.45 seconds
Started Jun 10 05:14:56 PM PDT 24
Finished Jun 10 05:15:07 PM PDT 24
Peak memory 200012 kb
Host smart-1425be49-cd65-45b8-af1a-80d17fa969b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333856915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_loopback.333856915
Directory /workspace/48.uart_loopback/latest

Test location /workspace/coverage/default/48.uart_noise_filter.2207128576
Short name T648
Test name
Test status
Simulation time 7339940174 ps
CPU time 10.32 seconds
Started Jun 10 05:14:54 PM PDT 24
Finished Jun 10 05:15:04 PM PDT 24
Peak memory 200408 kb
Host smart-7718bed6-3e3e-4be3-974d-5bcb8e6238cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207128576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_noise_filter.2207128576
Directory /workspace/48.uart_noise_filter/latest

Test location /workspace/coverage/default/48.uart_perf.2363531607
Short name T839
Test name
Test status
Simulation time 10961485901 ps
CPU time 624.72 seconds
Started Jun 10 05:14:55 PM PDT 24
Finished Jun 10 05:25:20 PM PDT 24
Peak memory 200344 kb
Host smart-774b8d50-6b92-49ff-9967-4b05988afbac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2363531607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.2363531607
Directory /workspace/48.uart_perf/latest

Test location /workspace/coverage/default/48.uart_rx_oversample.2489380889
Short name T674
Test name
Test status
Simulation time 1894463302 ps
CPU time 9.33 seconds
Started Jun 10 05:14:52 PM PDT 24
Finished Jun 10 05:15:02 PM PDT 24
Peak memory 198176 kb
Host smart-b3c396ab-870c-42c5-8876-1d12706e9568
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2489380889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.2489380889
Directory /workspace/48.uart_rx_oversample/latest

Test location /workspace/coverage/default/48.uart_rx_parity_err.3947572322
Short name T736
Test name
Test status
Simulation time 12595189727 ps
CPU time 22.41 seconds
Started Jun 10 05:14:54 PM PDT 24
Finished Jun 10 05:15:17 PM PDT 24
Peak memory 200244 kb
Host smart-e837378f-4205-4ddd-b986-8754045729cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947572322 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.3947572322
Directory /workspace/48.uart_rx_parity_err/latest

Test location /workspace/coverage/default/48.uart_rx_start_bit_filter.3062723200
Short name T874
Test name
Test status
Simulation time 5035373429 ps
CPU time 4.28 seconds
Started Jun 10 05:14:56 PM PDT 24
Finished Jun 10 05:15:01 PM PDT 24
Peak memory 196416 kb
Host smart-cf4914db-1415-4b03-be3d-73d86265f8ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062723200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.3062723200
Directory /workspace/48.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/48.uart_smoke.5010339
Short name T441
Test name
Test status
Simulation time 84097026 ps
CPU time 0.87 seconds
Started Jun 10 05:14:54 PM PDT 24
Finished Jun 10 05:14:55 PM PDT 24
Peak memory 197488 kb
Host smart-85449a32-1e7f-420b-b032-55108dcdba85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5010339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_smoke.5010339
Directory /workspace/48.uart_smoke/latest

Test location /workspace/coverage/default/48.uart_tx_ovrd.3615314704
Short name T600
Test name
Test status
Simulation time 854335385 ps
CPU time 3.11 seconds
Started Jun 10 05:14:53 PM PDT 24
Finished Jun 10 05:14:57 PM PDT 24
Peak memory 199184 kb
Host smart-ed0e6fc3-c726-4fd5-b22a-e36a5c40e3e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615314704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.3615314704
Directory /workspace/48.uart_tx_ovrd/latest

Test location /workspace/coverage/default/48.uart_tx_rx.3960354914
Short name T71
Test name
Test status
Simulation time 11372110098 ps
CPU time 20.77 seconds
Started Jun 10 05:14:53 PM PDT 24
Finished Jun 10 05:15:14 PM PDT 24
Peak memory 200420 kb
Host smart-4f4cfb4f-8e33-44a1-8178-c0bd4ac027e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960354914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.3960354914
Directory /workspace/48.uart_tx_rx/latest

Test location /workspace/coverage/default/49.uart_alert_test.2948151514
Short name T877
Test name
Test status
Simulation time 48366069 ps
CPU time 0.56 seconds
Started Jun 10 05:15:03 PM PDT 24
Finished Jun 10 05:15:04 PM PDT 24
Peak memory 195660 kb
Host smart-70a671f3-bef4-4c47-bb49-4ef03264cb9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948151514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.2948151514
Directory /workspace/49.uart_alert_test/latest

Test location /workspace/coverage/default/49.uart_fifo_full.1874227580
Short name T772
Test name
Test status
Simulation time 163417211611 ps
CPU time 67.18 seconds
Started Jun 10 05:14:59 PM PDT 24
Finished Jun 10 05:16:06 PM PDT 24
Peak memory 200184 kb
Host smart-0941c02b-232d-41b2-ae93-fb278fa95632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874227580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.1874227580
Directory /workspace/49.uart_fifo_full/latest

Test location /workspace/coverage/default/49.uart_fifo_overflow.1472457223
Short name T270
Test name
Test status
Simulation time 109134513022 ps
CPU time 44.64 seconds
Started Jun 10 05:14:55 PM PDT 24
Finished Jun 10 05:15:40 PM PDT 24
Peak memory 200328 kb
Host smart-ebe6e532-1f84-4a5d-bba3-ec0fe956abfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472457223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.1472457223
Directory /workspace/49.uart_fifo_overflow/latest

Test location /workspace/coverage/default/49.uart_fifo_reset.3306526911
Short name T316
Test name
Test status
Simulation time 28105148038 ps
CPU time 16.98 seconds
Started Jun 10 05:14:56 PM PDT 24
Finished Jun 10 05:15:14 PM PDT 24
Peak memory 200292 kb
Host smart-eee5df10-9dd6-4c3c-8355-47cfb4e6516c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306526911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.3306526911
Directory /workspace/49.uart_fifo_reset/latest

Test location /workspace/coverage/default/49.uart_intr.1392401887
Short name T359
Test name
Test status
Simulation time 15619934806 ps
CPU time 2.91 seconds
Started Jun 10 05:14:58 PM PDT 24
Finished Jun 10 05:15:01 PM PDT 24
Peak memory 197260 kb
Host smart-82565210-4873-4fc7-9122-2f52e1d3e268
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392401887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.1392401887
Directory /workspace/49.uart_intr/latest

Test location /workspace/coverage/default/49.uart_long_xfer_wo_dly.951654077
Short name T806
Test name
Test status
Simulation time 117690804770 ps
CPU time 534.9 seconds
Started Jun 10 05:15:02 PM PDT 24
Finished Jun 10 05:23:58 PM PDT 24
Peak memory 200308 kb
Host smart-caebeb38-3719-4f32-8b64-96fa7da48ed5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=951654077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.951654077
Directory /workspace/49.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/49.uart_loopback.2240064031
Short name T873
Test name
Test status
Simulation time 14883428247 ps
CPU time 9.56 seconds
Started Jun 10 05:15:01 PM PDT 24
Finished Jun 10 05:15:11 PM PDT 24
Peak memory 200248 kb
Host smart-7a408840-5243-4390-aedb-8849d4929601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240064031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_loopback.2240064031
Directory /workspace/49.uart_loopback/latest

Test location /workspace/coverage/default/49.uart_perf.3088637387
Short name T565
Test name
Test status
Simulation time 10549742229 ps
CPU time 275.37 seconds
Started Jun 10 05:15:01 PM PDT 24
Finished Jun 10 05:19:37 PM PDT 24
Peak memory 200244 kb
Host smart-3ea7a888-5610-4063-bfaf-126e7043a477
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3088637387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.3088637387
Directory /workspace/49.uart_perf/latest

Test location /workspace/coverage/default/49.uart_rx_oversample.441767759
Short name T442
Test name
Test status
Simulation time 6604478841 ps
CPU time 61.86 seconds
Started Jun 10 05:14:56 PM PDT 24
Finished Jun 10 05:15:58 PM PDT 24
Peak memory 199220 kb
Host smart-3b8c0873-3518-46c4-9dba-61f503ed0360
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=441767759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.441767759
Directory /workspace/49.uart_rx_oversample/latest

Test location /workspace/coverage/default/49.uart_rx_parity_err.2629440166
Short name T1034
Test name
Test status
Simulation time 158601716049 ps
CPU time 80.32 seconds
Started Jun 10 05:14:58 PM PDT 24
Finished Jun 10 05:16:19 PM PDT 24
Peak memory 199972 kb
Host smart-e04bb68b-2c3f-4a86-9ddf-5ef3dce238ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629440166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.2629440166
Directory /workspace/49.uart_rx_parity_err/latest

Test location /workspace/coverage/default/49.uart_rx_start_bit_filter.3066314067
Short name T676
Test name
Test status
Simulation time 3509005009 ps
CPU time 4.68 seconds
Started Jun 10 05:15:00 PM PDT 24
Finished Jun 10 05:15:05 PM PDT 24
Peak memory 196396 kb
Host smart-e287a075-cdaf-459d-be83-da0039a379a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066314067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.3066314067
Directory /workspace/49.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/49.uart_smoke.2940926633
Short name T975
Test name
Test status
Simulation time 916943744 ps
CPU time 1.97 seconds
Started Jun 10 05:14:53 PM PDT 24
Finished Jun 10 05:14:56 PM PDT 24
Peak memory 200228 kb
Host smart-3e62ff5d-40dd-44dd-ae76-730dabdb86eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940926633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_smoke.2940926633
Directory /workspace/49.uart_smoke/latest

Test location /workspace/coverage/default/49.uart_stress_all_with_rand_reset.3892591725
Short name T837
Test name
Test status
Simulation time 8977368490 ps
CPU time 100.93 seconds
Started Jun 10 05:14:58 PM PDT 24
Finished Jun 10 05:16:39 PM PDT 24
Peak memory 216772 kb
Host smart-fffc1693-034d-4317-a04c-0a8a7824cbd1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892591725 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 49.uart_stress_all_with_rand_reset.3892591725
Directory /workspace/49.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.uart_tx_ovrd.482102381
Short name T1050
Test name
Test status
Simulation time 8216213300 ps
CPU time 9.43 seconds
Started Jun 10 05:14:58 PM PDT 24
Finished Jun 10 05:15:07 PM PDT 24
Peak memory 200260 kb
Host smart-32faab21-2db0-4c57-bce4-271ae0f37b59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482102381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.482102381
Directory /workspace/49.uart_tx_ovrd/latest

Test location /workspace/coverage/default/49.uart_tx_rx.3788864037
Short name T730
Test name
Test status
Simulation time 57300827557 ps
CPU time 9.47 seconds
Started Jun 10 05:14:56 PM PDT 24
Finished Jun 10 05:15:06 PM PDT 24
Peak memory 197564 kb
Host smart-6e8fc3bd-930e-44eb-9f7c-b5ac2a76237a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788864037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.3788864037
Directory /workspace/49.uart_tx_rx/latest

Test location /workspace/coverage/default/5.uart_alert_test.1369073281
Short name T607
Test name
Test status
Simulation time 16428271 ps
CPU time 0.59 seconds
Started Jun 10 05:13:01 PM PDT 24
Finished Jun 10 05:13:02 PM PDT 24
Peak memory 195652 kb
Host smart-d375ff11-161a-4f19-9e66-003e393fcbe4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369073281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.1369073281
Directory /workspace/5.uart_alert_test/latest

Test location /workspace/coverage/default/5.uart_fifo_full.3663266957
Short name T452
Test name
Test status
Simulation time 30968775481 ps
CPU time 50.66 seconds
Started Jun 10 05:12:59 PM PDT 24
Finished Jun 10 05:13:50 PM PDT 24
Peak memory 200268 kb
Host smart-7e4e62e7-e18d-43bc-8e44-d27b81de228d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663266957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.3663266957
Directory /workspace/5.uart_fifo_full/latest

Test location /workspace/coverage/default/5.uart_fifo_overflow.3003788696
Short name T659
Test name
Test status
Simulation time 122450783652 ps
CPU time 95.94 seconds
Started Jun 10 05:13:01 PM PDT 24
Finished Jun 10 05:14:37 PM PDT 24
Peak memory 200256 kb
Host smart-5ee6362d-6331-418b-a537-5572d4de2cfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003788696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.3003788696
Directory /workspace/5.uart_fifo_overflow/latest

Test location /workspace/coverage/default/5.uart_fifo_reset.1637860582
Short name T462
Test name
Test status
Simulation time 13352811155 ps
CPU time 23.25 seconds
Started Jun 10 05:13:02 PM PDT 24
Finished Jun 10 05:13:26 PM PDT 24
Peak memory 200212 kb
Host smart-50d853a5-588f-4907-8084-61f25a0234fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637860582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.1637860582
Directory /workspace/5.uart_fifo_reset/latest

Test location /workspace/coverage/default/5.uart_intr.2777924651
Short name T131
Test name
Test status
Simulation time 230566056904 ps
CPU time 122.37 seconds
Started Jun 10 05:13:11 PM PDT 24
Finished Jun 10 05:15:14 PM PDT 24
Peak memory 199836 kb
Host smart-0bbc6729-f7b1-4aea-a43a-fd6ce306e758
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777924651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.2777924651
Directory /workspace/5.uart_intr/latest

Test location /workspace/coverage/default/5.uart_long_xfer_wo_dly.594250129
Short name T448
Test name
Test status
Simulation time 65484042357 ps
CPU time 484.81 seconds
Started Jun 10 05:13:02 PM PDT 24
Finished Jun 10 05:21:07 PM PDT 24
Peak memory 200272 kb
Host smart-ba0b6f80-a4a7-4dd5-bacd-66bfa7c29810
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=594250129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.594250129
Directory /workspace/5.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/5.uart_loopback.946488654
Short name T11
Test name
Test status
Simulation time 3954188296 ps
CPU time 1.85 seconds
Started Jun 10 05:12:58 PM PDT 24
Finished Jun 10 05:13:00 PM PDT 24
Peak memory 199528 kb
Host smart-7b7a4346-ab16-4423-8276-6c1deaf51630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946488654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_loopback.946488654
Directory /workspace/5.uart_loopback/latest

Test location /workspace/coverage/default/5.uart_perf.3716738503
Short name T805
Test name
Test status
Simulation time 16132353751 ps
CPU time 231.05 seconds
Started Jun 10 05:12:58 PM PDT 24
Finished Jun 10 05:16:50 PM PDT 24
Peak memory 200308 kb
Host smart-ca882f24-b962-43b0-b466-93c3d33170a7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3716738503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.3716738503
Directory /workspace/5.uart_perf/latest

Test location /workspace/coverage/default/5.uart_rx_oversample.2450853224
Short name T968
Test name
Test status
Simulation time 4022634785 ps
CPU time 33.2 seconds
Started Jun 10 05:13:02 PM PDT 24
Finished Jun 10 05:13:35 PM PDT 24
Peak memory 198652 kb
Host smart-f1f737fe-9f86-4a5e-998c-e108e16427ca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2450853224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.2450853224
Directory /workspace/5.uart_rx_oversample/latest

Test location /workspace/coverage/default/5.uart_rx_parity_err.870969608
Short name T494
Test name
Test status
Simulation time 89056485703 ps
CPU time 44.13 seconds
Started Jun 10 05:13:00 PM PDT 24
Finished Jun 10 05:13:44 PM PDT 24
Peak memory 200296 kb
Host smart-abb66e66-40f1-4f5f-8e27-c837ae50a261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870969608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.870969608
Directory /workspace/5.uart_rx_parity_err/latest

Test location /workspace/coverage/default/5.uart_rx_start_bit_filter.2201330948
Short name T848
Test name
Test status
Simulation time 4830039088 ps
CPU time 8.93 seconds
Started Jun 10 05:12:59 PM PDT 24
Finished Jun 10 05:13:08 PM PDT 24
Peak memory 196380 kb
Host smart-ff5d5122-68ef-447e-a48b-405011c5bdf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201330948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.2201330948
Directory /workspace/5.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/5.uart_smoke.3803982298
Short name T526
Test name
Test status
Simulation time 106312997 ps
CPU time 0.96 seconds
Started Jun 10 05:12:57 PM PDT 24
Finished Jun 10 05:12:58 PM PDT 24
Peak memory 197536 kb
Host smart-df062cda-1b46-418e-a05e-99d24939fbf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803982298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_smoke.3803982298
Directory /workspace/5.uart_smoke/latest

Test location /workspace/coverage/default/5.uart_stress_all_with_rand_reset.1038627689
Short name T613
Test name
Test status
Simulation time 55880924109 ps
CPU time 1365.57 seconds
Started Jun 10 05:12:59 PM PDT 24
Finished Jun 10 05:35:45 PM PDT 24
Peak memory 216736 kb
Host smart-a1aa68df-8425-4fb0-9627-3285b7cf8cd0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038627689 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 5.uart_stress_all_with_rand_reset.1038627689
Directory /workspace/5.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.uart_tx_ovrd.3822372050
Short name T814
Test name
Test status
Simulation time 609446251 ps
CPU time 1.49 seconds
Started Jun 10 05:13:01 PM PDT 24
Finished Jun 10 05:13:02 PM PDT 24
Peak memory 199160 kb
Host smart-d064de06-185a-4891-b775-20f4ea12ea45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822372050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.3822372050
Directory /workspace/5.uart_tx_ovrd/latest

Test location /workspace/coverage/default/5.uart_tx_rx.3377670921
Short name T777
Test name
Test status
Simulation time 196937201635 ps
CPU time 79.01 seconds
Started Jun 10 05:13:11 PM PDT 24
Finished Jun 10 05:14:31 PM PDT 24
Peak memory 200260 kb
Host smart-b96902f8-42d5-420b-b33e-c7d71caeb9ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377670921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.3377670921
Directory /workspace/5.uart_tx_rx/latest

Test location /workspace/coverage/default/50.uart_fifo_reset.1613764790
Short name T627
Test name
Test status
Simulation time 37810133806 ps
CPU time 33.47 seconds
Started Jun 10 05:15:01 PM PDT 24
Finished Jun 10 05:15:35 PM PDT 24
Peak memory 200360 kb
Host smart-82f5e139-d11f-4dca-a7ad-00d802a16700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613764790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.1613764790
Directory /workspace/50.uart_fifo_reset/latest

Test location /workspace/coverage/default/50.uart_stress_all_with_rand_reset.348854696
Short name T466
Test name
Test status
Simulation time 17241838068 ps
CPU time 142.99 seconds
Started Jun 10 05:15:03 PM PDT 24
Finished Jun 10 05:17:26 PM PDT 24
Peak memory 216932 kb
Host smart-fd7db8ad-ad76-4bbf-b7b2-3e571cd529b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348854696 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 50.uart_stress_all_with_rand_reset.348854696
Directory /workspace/50.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.uart_fifo_reset.1063498003
Short name T661
Test name
Test status
Simulation time 48332830789 ps
CPU time 7.99 seconds
Started Jun 10 05:14:57 PM PDT 24
Finished Jun 10 05:15:06 PM PDT 24
Peak memory 200324 kb
Host smart-dfc91f65-ddf0-4a30-b10a-a9a6682a01d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063498003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.1063498003
Directory /workspace/52.uart_fifo_reset/latest

Test location /workspace/coverage/default/53.uart_fifo_reset.2175941497
Short name T578
Test name
Test status
Simulation time 24230628272 ps
CPU time 11.21 seconds
Started Jun 10 05:14:59 PM PDT 24
Finished Jun 10 05:15:11 PM PDT 24
Peak memory 200352 kb
Host smart-52c03829-e1d4-41fe-b5af-a8945d43d333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175941497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.2175941497
Directory /workspace/53.uart_fifo_reset/latest

Test location /workspace/coverage/default/53.uart_stress_all_with_rand_reset.3839442404
Short name T116
Test name
Test status
Simulation time 58159141350 ps
CPU time 526.9 seconds
Started Jun 10 05:15:00 PM PDT 24
Finished Jun 10 05:23:47 PM PDT 24
Peak memory 210892 kb
Host smart-9fcdbab0-fab5-43b6-ad52-2732c8efb3b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839442404 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 53.uart_stress_all_with_rand_reset.3839442404
Directory /workspace/53.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.uart_fifo_reset.3637184812
Short name T841
Test name
Test status
Simulation time 80102332984 ps
CPU time 54.5 seconds
Started Jun 10 05:14:58 PM PDT 24
Finished Jun 10 05:15:53 PM PDT 24
Peak memory 200160 kb
Host smart-ebd41d91-2d33-45e5-a783-9d6914c873ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637184812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.3637184812
Directory /workspace/54.uart_fifo_reset/latest

Test location /workspace/coverage/default/54.uart_stress_all_with_rand_reset.1234040145
Short name T59
Test name
Test status
Simulation time 26110858582 ps
CPU time 262.14 seconds
Started Jun 10 05:14:58 PM PDT 24
Finished Jun 10 05:19:21 PM PDT 24
Peak memory 208608 kb
Host smart-f51414c0-847e-424a-8780-5a28936cbef3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234040145 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 54.uart_stress_all_with_rand_reset.1234040145
Directory /workspace/54.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.uart_fifo_reset.3775891200
Short name T571
Test name
Test status
Simulation time 57939958672 ps
CPU time 99.4 seconds
Started Jun 10 05:14:58 PM PDT 24
Finished Jun 10 05:16:38 PM PDT 24
Peak memory 200276 kb
Host smart-f44970b7-1d65-4c34-8990-80b22c9e3f23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775891200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.3775891200
Directory /workspace/55.uart_fifo_reset/latest

Test location /workspace/coverage/default/55.uart_stress_all_with_rand_reset.1473242488
Short name T61
Test name
Test status
Simulation time 254606222840 ps
CPU time 1190.24 seconds
Started Jun 10 05:15:03 PM PDT 24
Finished Jun 10 05:34:53 PM PDT 24
Peak memory 216760 kb
Host smart-9e1cf751-c645-4b96-9c5d-2f0bd463d881
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473242488 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 55.uart_stress_all_with_rand_reset.1473242488
Directory /workspace/55.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/56.uart_fifo_reset.3585412851
Short name T168
Test name
Test status
Simulation time 18673551986 ps
CPU time 17.49 seconds
Started Jun 10 05:14:58 PM PDT 24
Finished Jun 10 05:15:16 PM PDT 24
Peak memory 200316 kb
Host smart-aaca0abb-120c-4380-8ab1-f1fbecd971cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585412851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.3585412851
Directory /workspace/56.uart_fifo_reset/latest

Test location /workspace/coverage/default/57.uart_fifo_reset.2895718546
Short name T339
Test name
Test status
Simulation time 82838183533 ps
CPU time 85.57 seconds
Started Jun 10 05:15:06 PM PDT 24
Finished Jun 10 05:16:32 PM PDT 24
Peak memory 200280 kb
Host smart-49a19202-db89-4fb5-964a-7456e64fd635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895718546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.2895718546
Directory /workspace/57.uart_fifo_reset/latest

Test location /workspace/coverage/default/57.uart_stress_all_with_rand_reset.1013069898
Short name T62
Test name
Test status
Simulation time 68847385197 ps
CPU time 389.41 seconds
Started Jun 10 05:15:07 PM PDT 24
Finished Jun 10 05:21:36 PM PDT 24
Peak memory 216804 kb
Host smart-0a66729c-d2a6-44ac-b4d3-99999d6b3443
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013069898 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 57.uart_stress_all_with_rand_reset.1013069898
Directory /workspace/57.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/58.uart_fifo_reset.1692725477
Short name T1022
Test name
Test status
Simulation time 141024104502 ps
CPU time 225.88 seconds
Started Jun 10 05:15:03 PM PDT 24
Finished Jun 10 05:18:49 PM PDT 24
Peak memory 200324 kb
Host smart-1cefd153-e999-4447-88fc-7b290d539994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692725477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.1692725477
Directory /workspace/58.uart_fifo_reset/latest

Test location /workspace/coverage/default/58.uart_stress_all_with_rand_reset.335336627
Short name T148
Test name
Test status
Simulation time 161137526468 ps
CPU time 742.71 seconds
Started Jun 10 05:15:02 PM PDT 24
Finished Jun 10 05:27:26 PM PDT 24
Peak memory 225232 kb
Host smart-45ddda3d-5ad5-4cda-825a-486df84e50fe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335336627 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 58.uart_stress_all_with_rand_reset.335336627
Directory /workspace/58.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/59.uart_fifo_reset.3964358263
Short name T936
Test name
Test status
Simulation time 267945893990 ps
CPU time 59.2 seconds
Started Jun 10 05:15:02 PM PDT 24
Finished Jun 10 05:16:02 PM PDT 24
Peak memory 200308 kb
Host smart-da657aea-33e5-46e3-9c59-08e6a572d5f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964358263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.3964358263
Directory /workspace/59.uart_fifo_reset/latest

Test location /workspace/coverage/default/59.uart_stress_all_with_rand_reset.3426260553
Short name T522
Test name
Test status
Simulation time 117930183515 ps
CPU time 1908.24 seconds
Started Jun 10 05:15:03 PM PDT 24
Finished Jun 10 05:46:52 PM PDT 24
Peak memory 225116 kb
Host smart-aff25e5b-f619-448b-9441-fd3abd1f554f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426260553 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 59.uart_stress_all_with_rand_reset.3426260553
Directory /workspace/59.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_alert_test.2799815991
Short name T743
Test name
Test status
Simulation time 11947505 ps
CPU time 0.57 seconds
Started Jun 10 05:13:09 PM PDT 24
Finished Jun 10 05:13:10 PM PDT 24
Peak memory 196028 kb
Host smart-27f83ca6-0a20-4b4b-9c79-d8fd944d6428
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799815991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.2799815991
Directory /workspace/6.uart_alert_test/latest

Test location /workspace/coverage/default/6.uart_fifo_full.3971556927
Short name T786
Test name
Test status
Simulation time 35438407561 ps
CPU time 67.53 seconds
Started Jun 10 05:13:11 PM PDT 24
Finished Jun 10 05:14:19 PM PDT 24
Peak memory 200248 kb
Host smart-57ae2850-4b79-4ca8-8cfc-33f0bbf2247e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971556927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.3971556927
Directory /workspace/6.uart_fifo_full/latest

Test location /workspace/coverage/default/6.uart_fifo_overflow.2231173241
Short name T301
Test name
Test status
Simulation time 111540432821 ps
CPU time 77.06 seconds
Started Jun 10 05:13:06 PM PDT 24
Finished Jun 10 05:14:23 PM PDT 24
Peak memory 200208 kb
Host smart-3f7711f2-cb07-44c8-a6fc-2399bfeb9605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231173241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.2231173241
Directory /workspace/6.uart_fifo_overflow/latest

Test location /workspace/coverage/default/6.uart_fifo_reset.2398880466
Short name T153
Test name
Test status
Simulation time 57417466833 ps
CPU time 18.97 seconds
Started Jun 10 05:13:07 PM PDT 24
Finished Jun 10 05:13:26 PM PDT 24
Peak memory 200276 kb
Host smart-a53d1e3f-367e-473a-ac96-0474b6a52c55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398880466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.2398880466
Directory /workspace/6.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_intr.1762015091
Short name T321
Test name
Test status
Simulation time 29645006936 ps
CPU time 13.63 seconds
Started Jun 10 05:13:05 PM PDT 24
Finished Jun 10 05:13:19 PM PDT 24
Peak memory 200288 kb
Host smart-7a7636da-8269-4673-9917-c43556fee2dc
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762015091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.1762015091
Directory /workspace/6.uart_intr/latest

Test location /workspace/coverage/default/6.uart_long_xfer_wo_dly.476686959
Short name T789
Test name
Test status
Simulation time 36430908886 ps
CPU time 219.12 seconds
Started Jun 10 05:13:11 PM PDT 24
Finished Jun 10 05:16:51 PM PDT 24
Peak memory 200348 kb
Host smart-26be2124-b84d-4983-8179-907c0386c5c5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=476686959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.476686959
Directory /workspace/6.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/6.uart_loopback.3839397672
Short name T20
Test name
Test status
Simulation time 2958185560 ps
CPU time 2.06 seconds
Started Jun 10 05:13:05 PM PDT 24
Finished Jun 10 05:13:08 PM PDT 24
Peak memory 196440 kb
Host smart-ec6424cb-901b-4edd-b548-fa54105eb724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839397672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_loopback.3839397672
Directory /workspace/6.uart_loopback/latest

Test location /workspace/coverage/default/6.uart_noise_filter.872945655
Short name T756
Test name
Test status
Simulation time 36394976558 ps
CPU time 60.68 seconds
Started Jun 10 05:13:06 PM PDT 24
Finished Jun 10 05:14:08 PM PDT 24
Peak memory 200268 kb
Host smart-0f4e2e3f-8eaa-42fa-b57b-78b02620863d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872945655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_noise_filter.872945655
Directory /workspace/6.uart_noise_filter/latest

Test location /workspace/coverage/default/6.uart_perf.1980121700
Short name T1005
Test name
Test status
Simulation time 14782553226 ps
CPU time 203.76 seconds
Started Jun 10 05:13:11 PM PDT 24
Finished Jun 10 05:16:36 PM PDT 24
Peak memory 200188 kb
Host smart-7b20371d-13fc-4323-b0fb-a2ffdd02d501
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1980121700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.1980121700
Directory /workspace/6.uart_perf/latest

Test location /workspace/coverage/default/6.uart_rx_oversample.1565045530
Short name T65
Test name
Test status
Simulation time 2737155702 ps
CPU time 19.29 seconds
Started Jun 10 05:13:02 PM PDT 24
Finished Jun 10 05:13:22 PM PDT 24
Peak memory 198920 kb
Host smart-146f908c-949e-4b0d-92a6-62c0fe089e02
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1565045530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.1565045530
Directory /workspace/6.uart_rx_oversample/latest

Test location /workspace/coverage/default/6.uart_rx_parity_err.3431566083
Short name T945
Test name
Test status
Simulation time 91176607245 ps
CPU time 34.96 seconds
Started Jun 10 05:13:02 PM PDT 24
Finished Jun 10 05:13:37 PM PDT 24
Peak memory 200132 kb
Host smart-a78f98fe-f9ff-48d7-8a12-256f4f84850e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431566083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.3431566083
Directory /workspace/6.uart_rx_parity_err/latest

Test location /workspace/coverage/default/6.uart_rx_start_bit_filter.1645383540
Short name T668
Test name
Test status
Simulation time 3850973533 ps
CPU time 6.1 seconds
Started Jun 10 05:13:03 PM PDT 24
Finished Jun 10 05:13:09 PM PDT 24
Peak memory 196812 kb
Host smart-226dc922-b6d2-4c44-b46f-e31bc5bc651e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645383540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.1645383540
Directory /workspace/6.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/6.uart_smoke.1109115095
Short name T267
Test name
Test status
Simulation time 10571846700 ps
CPU time 28.14 seconds
Started Jun 10 05:13:02 PM PDT 24
Finished Jun 10 05:13:31 PM PDT 24
Peak memory 200244 kb
Host smart-fee746da-549c-4773-b275-7a9609803a63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109115095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_smoke.1109115095
Directory /workspace/6.uart_smoke/latest

Test location /workspace/coverage/default/6.uart_stress_all.1195093894
Short name T708
Test name
Test status
Simulation time 361619187720 ps
CPU time 1249.82 seconds
Started Jun 10 05:13:12 PM PDT 24
Finished Jun 10 05:34:03 PM PDT 24
Peak memory 200364 kb
Host smart-2ea79987-03d4-4c94-85b2-822267b632a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195093894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.1195093894
Directory /workspace/6.uart_stress_all/latest

Test location /workspace/coverage/default/6.uart_stress_all_with_rand_reset.1402051482
Short name T32
Test name
Test status
Simulation time 94060717987 ps
CPU time 330.94 seconds
Started Jun 10 05:13:03 PM PDT 24
Finished Jun 10 05:18:35 PM PDT 24
Peak memory 216204 kb
Host smart-3a0b2246-81e8-4f92-90ea-ec591544e9bd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402051482 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 6.uart_stress_all_with_rand_reset.1402051482
Directory /workspace/6.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_tx_ovrd.978616029
Short name T741
Test name
Test status
Simulation time 678809537 ps
CPU time 3.34 seconds
Started Jun 10 05:13:04 PM PDT 24
Finished Jun 10 05:13:08 PM PDT 24
Peak memory 199272 kb
Host smart-13174e3d-3ddb-46e8-8efa-c765ac11e7bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978616029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.978616029
Directory /workspace/6.uart_tx_ovrd/latest

Test location /workspace/coverage/default/6.uart_tx_rx.2042270340
Short name T528
Test name
Test status
Simulation time 27372120132 ps
CPU time 25.57 seconds
Started Jun 10 05:12:59 PM PDT 24
Finished Jun 10 05:13:25 PM PDT 24
Peak memory 200328 kb
Host smart-bf971630-8927-4a6f-9375-199af49bc698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042270340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.2042270340
Directory /workspace/6.uart_tx_rx/latest

Test location /workspace/coverage/default/60.uart_fifo_reset.3126696722
Short name T297
Test name
Test status
Simulation time 50193931320 ps
CPU time 80.77 seconds
Started Jun 10 05:15:03 PM PDT 24
Finished Jun 10 05:16:24 PM PDT 24
Peak memory 200384 kb
Host smart-212b2fb2-f6b2-423c-a86a-83e3e4c0a43b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126696722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.3126696722
Directory /workspace/60.uart_fifo_reset/latest

Test location /workspace/coverage/default/61.uart_fifo_reset.4138168857
Short name T691
Test name
Test status
Simulation time 89826939047 ps
CPU time 203.24 seconds
Started Jun 10 05:15:04 PM PDT 24
Finished Jun 10 05:18:27 PM PDT 24
Peak memory 200228 kb
Host smart-f0ea8f52-b880-4edf-8319-8959d2b2177b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138168857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.4138168857
Directory /workspace/61.uart_fifo_reset/latest

Test location /workspace/coverage/default/61.uart_stress_all_with_rand_reset.2030249914
Short name T57
Test name
Test status
Simulation time 21778312201 ps
CPU time 253.49 seconds
Started Jun 10 05:15:04 PM PDT 24
Finished Jun 10 05:19:18 PM PDT 24
Peak memory 216208 kb
Host smart-3e012e51-c8c8-4d4b-89c3-dc3950114dc9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030249914 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 61.uart_stress_all_with_rand_reset.2030249914
Directory /workspace/61.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.uart_fifo_reset.2140814841
Short name T632
Test name
Test status
Simulation time 36311563321 ps
CPU time 14.08 seconds
Started Jun 10 05:15:04 PM PDT 24
Finished Jun 10 05:15:19 PM PDT 24
Peak memory 200316 kb
Host smart-f0cc9b6e-633e-442e-bf2f-62e56f807389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140814841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.2140814841
Directory /workspace/62.uart_fifo_reset/latest

Test location /workspace/coverage/default/63.uart_fifo_reset.34870928
Short name T252
Test name
Test status
Simulation time 33990195422 ps
CPU time 47.19 seconds
Started Jun 10 05:15:01 PM PDT 24
Finished Jun 10 05:15:49 PM PDT 24
Peak memory 200248 kb
Host smart-6dcf0d22-eb3b-40f5-a974-1c50756ef006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34870928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.34870928
Directory /workspace/63.uart_fifo_reset/latest

Test location /workspace/coverage/default/64.uart_fifo_reset.489933085
Short name T785
Test name
Test status
Simulation time 9618961704 ps
CPU time 18.89 seconds
Started Jun 10 05:15:04 PM PDT 24
Finished Jun 10 05:15:23 PM PDT 24
Peak memory 200268 kb
Host smart-7a50871c-b26a-4616-9a3f-cb6878d7fa60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489933085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.489933085
Directory /workspace/64.uart_fifo_reset/latest

Test location /workspace/coverage/default/64.uart_stress_all_with_rand_reset.1731946196
Short name T991
Test name
Test status
Simulation time 37394207466 ps
CPU time 616.02 seconds
Started Jun 10 05:15:02 PM PDT 24
Finished Jun 10 05:25:19 PM PDT 24
Peak memory 216948 kb
Host smart-54f9ca55-a2cb-4387-9215-6ee31a9ebf26
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731946196 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 64.uart_stress_all_with_rand_reset.1731946196
Directory /workspace/64.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/65.uart_fifo_reset.1540670190
Short name T586
Test name
Test status
Simulation time 60337159768 ps
CPU time 57.66 seconds
Started Jun 10 05:15:05 PM PDT 24
Finished Jun 10 05:16:03 PM PDT 24
Peak memory 200312 kb
Host smart-239e5817-97ec-45a5-a3b2-0f39c1ba99b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540670190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.1540670190
Directory /workspace/65.uart_fifo_reset/latest

Test location /workspace/coverage/default/66.uart_fifo_reset.1867317083
Short name T333
Test name
Test status
Simulation time 94661972393 ps
CPU time 12.61 seconds
Started Jun 10 05:15:01 PM PDT 24
Finished Jun 10 05:15:14 PM PDT 24
Peak memory 199664 kb
Host smart-310a468b-5f0a-41c0-a2b7-4a0916f84ece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867317083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.1867317083
Directory /workspace/66.uart_fifo_reset/latest

Test location /workspace/coverage/default/67.uart_fifo_reset.1715368353
Short name T747
Test name
Test status
Simulation time 235435990964 ps
CPU time 364.12 seconds
Started Jun 10 05:15:03 PM PDT 24
Finished Jun 10 05:21:07 PM PDT 24
Peak memory 200368 kb
Host smart-85bf9d3a-3135-4aab-a2c4-3e390fe362e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715368353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.1715368353
Directory /workspace/67.uart_fifo_reset/latest

Test location /workspace/coverage/default/68.uart_fifo_reset.1050536642
Short name T638
Test name
Test status
Simulation time 57146853158 ps
CPU time 96 seconds
Started Jun 10 05:15:07 PM PDT 24
Finished Jun 10 05:16:44 PM PDT 24
Peak memory 200240 kb
Host smart-c404ecc4-865f-416e-bb52-bbad54d11d8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050536642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.1050536642
Directory /workspace/68.uart_fifo_reset/latest

Test location /workspace/coverage/default/68.uart_stress_all_with_rand_reset.3983956066
Short name T1047
Test name
Test status
Simulation time 121503398535 ps
CPU time 1479.4 seconds
Started Jun 10 05:15:11 PM PDT 24
Finished Jun 10 05:39:51 PM PDT 24
Peak memory 225000 kb
Host smart-f71a8001-d324-4396-8118-0e67098320df
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983956066 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 68.uart_stress_all_with_rand_reset.3983956066
Directory /workspace/68.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.uart_fifo_reset.815242824
Short name T290
Test name
Test status
Simulation time 32232042804 ps
CPU time 56.98 seconds
Started Jun 10 05:15:10 PM PDT 24
Finished Jun 10 05:16:08 PM PDT 24
Peak memory 200388 kb
Host smart-ea0374ea-b662-4309-966f-331a27ff82f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815242824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.815242824
Directory /workspace/69.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_alert_test.2146601032
Short name T536
Test name
Test status
Simulation time 21051823 ps
CPU time 0.56 seconds
Started Jun 10 05:13:10 PM PDT 24
Finished Jun 10 05:13:11 PM PDT 24
Peak memory 196056 kb
Host smart-0aa42a20-e2db-438f-a535-aa7e12b3e0ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146601032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.2146601032
Directory /workspace/7.uart_alert_test/latest

Test location /workspace/coverage/default/7.uart_fifo_full.733125579
Short name T169
Test name
Test status
Simulation time 147212925368 ps
CPU time 85.91 seconds
Started Jun 10 05:13:04 PM PDT 24
Finished Jun 10 05:14:30 PM PDT 24
Peak memory 200352 kb
Host smart-7450c7d8-e266-45f5-a077-fa785d8adaaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733125579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.733125579
Directory /workspace/7.uart_fifo_full/latest

Test location /workspace/coverage/default/7.uart_fifo_overflow.1911892458
Short name T335
Test name
Test status
Simulation time 37700273896 ps
CPU time 64.65 seconds
Started Jun 10 05:13:05 PM PDT 24
Finished Jun 10 05:14:10 PM PDT 24
Peak memory 200312 kb
Host smart-1851ecc6-f988-488e-9cf5-516b76b972c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911892458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.1911892458
Directory /workspace/7.uart_fifo_overflow/latest

Test location /workspace/coverage/default/7.uart_fifo_reset.1250263083
Short name T272
Test name
Test status
Simulation time 85149127206 ps
CPU time 187.75 seconds
Started Jun 10 05:13:11 PM PDT 24
Finished Jun 10 05:16:19 PM PDT 24
Peak memory 200212 kb
Host smart-15a18e75-7d26-4feb-833e-d5ace391353b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250263083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.1250263083
Directory /workspace/7.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_intr.164688385
Short name T569
Test name
Test status
Simulation time 27347554630 ps
CPU time 32.62 seconds
Started Jun 10 05:13:15 PM PDT 24
Finished Jun 10 05:13:48 PM PDT 24
Peak memory 200376 kb
Host smart-1180e350-52d9-452c-9477-14b3316a2f07
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164688385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.164688385
Directory /workspace/7.uart_intr/latest

Test location /workspace/coverage/default/7.uart_long_xfer_wo_dly.1816464969
Short name T523
Test name
Test status
Simulation time 53894624831 ps
CPU time 262.16 seconds
Started Jun 10 05:13:09 PM PDT 24
Finished Jun 10 05:17:32 PM PDT 24
Peak memory 200308 kb
Host smart-adb316ca-3214-4824-8ced-056c901f8676
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1816464969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.1816464969
Directory /workspace/7.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/7.uart_loopback.772130696
Short name T744
Test name
Test status
Simulation time 2499669918 ps
CPU time 2.16 seconds
Started Jun 10 05:13:10 PM PDT 24
Finished Jun 10 05:13:12 PM PDT 24
Peak memory 199092 kb
Host smart-5e522fc3-a431-42c1-b721-a44dc662fe1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772130696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_loopback.772130696
Directory /workspace/7.uart_loopback/latest

Test location /workspace/coverage/default/7.uart_perf.475113310
Short name T832
Test name
Test status
Simulation time 15208863469 ps
CPU time 545.87 seconds
Started Jun 10 05:13:06 PM PDT 24
Finished Jun 10 05:22:13 PM PDT 24
Peak memory 200248 kb
Host smart-7edfc049-31a3-42bf-91e6-121b8f3b5d73
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=475113310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.475113310
Directory /workspace/7.uart_perf/latest

Test location /workspace/coverage/default/7.uart_rx_oversample.2533390245
Short name T362
Test name
Test status
Simulation time 7383604919 ps
CPU time 6.7 seconds
Started Jun 10 05:13:04 PM PDT 24
Finished Jun 10 05:13:12 PM PDT 24
Peak memory 200280 kb
Host smart-f39dd4d7-b430-4c28-8fdc-54a721b0bb48
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2533390245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.2533390245
Directory /workspace/7.uart_rx_oversample/latest

Test location /workspace/coverage/default/7.uart_rx_parity_err.1579464658
Short name T934
Test name
Test status
Simulation time 23543528463 ps
CPU time 19.67 seconds
Started Jun 10 05:13:06 PM PDT 24
Finished Jun 10 05:13:27 PM PDT 24
Peak memory 200320 kb
Host smart-39b37031-f5dd-4161-a30d-45b06ffaa1b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579464658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.1579464658
Directory /workspace/7.uart_rx_parity_err/latest

Test location /workspace/coverage/default/7.uart_rx_start_bit_filter.3629315535
Short name T715
Test name
Test status
Simulation time 2102049019 ps
CPU time 4.17 seconds
Started Jun 10 05:13:06 PM PDT 24
Finished Jun 10 05:13:11 PM PDT 24
Peak memory 195748 kb
Host smart-4f7ef5cf-30ca-470e-a9e7-ff86bf9c914c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629315535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.3629315535
Directory /workspace/7.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/7.uart_smoke.1154506436
Short name T436
Test name
Test status
Simulation time 471996502 ps
CPU time 2.1 seconds
Started Jun 10 05:13:04 PM PDT 24
Finished Jun 10 05:13:07 PM PDT 24
Peak memory 199872 kb
Host smart-4082f8f5-f031-4d10-b68d-b79f516bf65b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154506436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_smoke.1154506436
Directory /workspace/7.uart_smoke/latest

Test location /workspace/coverage/default/7.uart_stress_all.3548199975
Short name T231
Test name
Test status
Simulation time 569387143131 ps
CPU time 722.97 seconds
Started Jun 10 05:13:11 PM PDT 24
Finished Jun 10 05:25:14 PM PDT 24
Peak memory 200260 kb
Host smart-2bdd729a-6ef6-4c8f-ae57-3d62262d5cbc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548199975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.3548199975
Directory /workspace/7.uart_stress_all/latest

Test location /workspace/coverage/default/7.uart_stress_all_with_rand_reset.3526077529
Short name T1069
Test name
Test status
Simulation time 252271128854 ps
CPU time 637.6 seconds
Started Jun 10 05:13:08 PM PDT 24
Finished Jun 10 05:23:46 PM PDT 24
Peak memory 216836 kb
Host smart-e0d56d22-cc84-4850-96ac-ea859d4a1fb3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526077529 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 7.uart_stress_all_with_rand_reset.3526077529
Directory /workspace/7.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_tx_ovrd.4085870431
Short name T748
Test name
Test status
Simulation time 761123626 ps
CPU time 2.73 seconds
Started Jun 10 05:13:08 PM PDT 24
Finished Jun 10 05:13:11 PM PDT 24
Peak memory 199204 kb
Host smart-c7ff8d4d-72b0-4f93-bcba-397002615ef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085870431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.4085870431
Directory /workspace/7.uart_tx_ovrd/latest

Test location /workspace/coverage/default/7.uart_tx_rx.995604259
Short name T304
Test name
Test status
Simulation time 4905346853 ps
CPU time 7.73 seconds
Started Jun 10 05:13:15 PM PDT 24
Finished Jun 10 05:13:23 PM PDT 24
Peak memory 197448 kb
Host smart-8480585e-d322-49a7-95ac-5a58b1d1d43f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995604259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.995604259
Directory /workspace/7.uart_tx_rx/latest

Test location /workspace/coverage/default/70.uart_stress_all_with_rand_reset.1457539226
Short name T352
Test name
Test status
Simulation time 53017572668 ps
CPU time 272.31 seconds
Started Jun 10 05:15:08 PM PDT 24
Finished Jun 10 05:19:40 PM PDT 24
Peak memory 208640 kb
Host smart-ae002281-1af9-4029-8972-acee60c053b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457539226 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 70.uart_stress_all_with_rand_reset.1457539226
Directory /workspace/70.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/71.uart_fifo_reset.1883389670
Short name T416
Test name
Test status
Simulation time 47053048906 ps
CPU time 106.59 seconds
Started Jun 10 05:15:09 PM PDT 24
Finished Jun 10 05:16:56 PM PDT 24
Peak memory 200320 kb
Host smart-18b0d6be-fd66-4759-904b-cd09595702b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883389670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.1883389670
Directory /workspace/71.uart_fifo_reset/latest

Test location /workspace/coverage/default/73.uart_fifo_reset.882586203
Short name T258
Test name
Test status
Simulation time 111602377653 ps
CPU time 127.94 seconds
Started Jun 10 05:15:08 PM PDT 24
Finished Jun 10 05:17:16 PM PDT 24
Peak memory 200300 kb
Host smart-e6f340fc-f3be-4e32-a596-a8c3e2302ff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882586203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.882586203
Directory /workspace/73.uart_fifo_reset/latest

Test location /workspace/coverage/default/73.uart_stress_all_with_rand_reset.1671586285
Short name T337
Test name
Test status
Simulation time 44202200487 ps
CPU time 548.64 seconds
Started Jun 10 05:15:12 PM PDT 24
Finished Jun 10 05:24:21 PM PDT 24
Peak memory 216752 kb
Host smart-e121eb72-5c5d-4b6d-8102-7c847963ee26
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671586285 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 73.uart_stress_all_with_rand_reset.1671586285
Directory /workspace/73.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.uart_fifo_reset.610783611
Short name T663
Test name
Test status
Simulation time 70654382456 ps
CPU time 60.87 seconds
Started Jun 10 05:15:06 PM PDT 24
Finished Jun 10 05:16:08 PM PDT 24
Peak memory 200288 kb
Host smart-938ab4b0-af7c-4fce-b5a4-b16864504cef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610783611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.610783611
Directory /workspace/75.uart_fifo_reset/latest

Test location /workspace/coverage/default/75.uart_stress_all_with_rand_reset.1103018539
Short name T1036
Test name
Test status
Simulation time 97359275514 ps
CPU time 572.35 seconds
Started Jun 10 05:15:10 PM PDT 24
Finished Jun 10 05:24:42 PM PDT 24
Peak memory 216860 kb
Host smart-1d20e0f1-e54d-4ec1-bacb-b0a9286b6ab6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103018539 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 75.uart_stress_all_with_rand_reset.1103018539
Directory /workspace/75.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/76.uart_stress_all_with_rand_reset.3284962199
Short name T878
Test name
Test status
Simulation time 227201926044 ps
CPU time 750.4 seconds
Started Jun 10 05:15:14 PM PDT 24
Finished Jun 10 05:27:45 PM PDT 24
Peak memory 225032 kb
Host smart-c6cb46fa-75ba-4605-a403-76fea29f7b4b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284962199 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 76.uart_stress_all_with_rand_reset.3284962199
Directory /workspace/76.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/77.uart_fifo_reset.3089095386
Short name T192
Test name
Test status
Simulation time 204275968717 ps
CPU time 71.52 seconds
Started Jun 10 05:15:07 PM PDT 24
Finished Jun 10 05:16:19 PM PDT 24
Peak memory 200300 kb
Host smart-105d2992-1841-434d-9c1c-c9c29c120374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089095386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.3089095386
Directory /workspace/77.uart_fifo_reset/latest

Test location /workspace/coverage/default/77.uart_stress_all_with_rand_reset.1004145393
Short name T29
Test name
Test status
Simulation time 51367067885 ps
CPU time 377.79 seconds
Started Jun 10 05:15:08 PM PDT 24
Finished Jun 10 05:21:27 PM PDT 24
Peak memory 216072 kb
Host smart-e21db116-bf66-4a67-bc67-736791a653fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004145393 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 77.uart_stress_all_with_rand_reset.1004145393
Directory /workspace/77.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/78.uart_fifo_reset.3261827029
Short name T141
Test name
Test status
Simulation time 131126448310 ps
CPU time 105.05 seconds
Started Jun 10 05:15:14 PM PDT 24
Finished Jun 10 05:16:59 PM PDT 24
Peak memory 200216 kb
Host smart-149edfdf-234a-4562-bfc0-29dd85f9a25a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261827029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.3261827029
Directory /workspace/78.uart_fifo_reset/latest

Test location /workspace/coverage/default/78.uart_stress_all_with_rand_reset.2116463987
Short name T176
Test name
Test status
Simulation time 171874112225 ps
CPU time 671.49 seconds
Started Jun 10 05:15:08 PM PDT 24
Finished Jun 10 05:26:20 PM PDT 24
Peak memory 216840 kb
Host smart-6ffe4e90-a124-4ea8-929e-8209fc7a3b4c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116463987 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 78.uart_stress_all_with_rand_reset.2116463987
Directory /workspace/78.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.uart_fifo_reset.2653706298
Short name T216
Test name
Test status
Simulation time 52589399767 ps
CPU time 20.92 seconds
Started Jun 10 05:15:15 PM PDT 24
Finished Jun 10 05:15:36 PM PDT 24
Peak memory 200176 kb
Host smart-25063da4-0722-4b4d-bfff-decbec47d181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653706298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.2653706298
Directory /workspace/79.uart_fifo_reset/latest

Test location /workspace/coverage/default/79.uart_stress_all_with_rand_reset.623397734
Short name T604
Test name
Test status
Simulation time 40706421448 ps
CPU time 855.94 seconds
Started Jun 10 05:15:10 PM PDT 24
Finished Jun 10 05:29:26 PM PDT 24
Peak memory 216240 kb
Host smart-35e3a83e-a517-4586-8fff-d6bd0a9ab718
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623397734 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 79.uart_stress_all_with_rand_reset.623397734
Directory /workspace/79.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_alert_test.3706323767
Short name T423
Test name
Test status
Simulation time 101288566 ps
CPU time 0.55 seconds
Started Jun 10 05:13:16 PM PDT 24
Finished Jun 10 05:13:17 PM PDT 24
Peak memory 195388 kb
Host smart-df010131-f862-472c-bada-b2cb8baaf6b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706323767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.3706323767
Directory /workspace/8.uart_alert_test/latest

Test location /workspace/coverage/default/8.uart_fifo_full.885270395
Short name T166
Test name
Test status
Simulation time 85984828095 ps
CPU time 45.56 seconds
Started Jun 10 05:13:10 PM PDT 24
Finished Jun 10 05:13:56 PM PDT 24
Peak memory 200384 kb
Host smart-fd6910f5-b24b-4d55-8fbb-d3bbdd767209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885270395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.885270395
Directory /workspace/8.uart_fifo_full/latest

Test location /workspace/coverage/default/8.uart_fifo_overflow.2216163070
Short name T162
Test name
Test status
Simulation time 8199149491 ps
CPU time 15.42 seconds
Started Jun 10 05:13:07 PM PDT 24
Finished Jun 10 05:13:23 PM PDT 24
Peak memory 199968 kb
Host smart-ed29fa8b-d473-486e-ad7f-1f369a02912c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216163070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.2216163070
Directory /workspace/8.uart_fifo_overflow/latest

Test location /workspace/coverage/default/8.uart_fifo_reset.937566458
Short name T486
Test name
Test status
Simulation time 15698041316 ps
CPU time 23.35 seconds
Started Jun 10 05:13:08 PM PDT 24
Finished Jun 10 05:13:31 PM PDT 24
Peak memory 200128 kb
Host smart-6b354d00-f017-4cd4-959e-85d88180707e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937566458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.937566458
Directory /workspace/8.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_intr.3930350598
Short name T392
Test name
Test status
Simulation time 138321596566 ps
CPU time 373.89 seconds
Started Jun 10 05:13:09 PM PDT 24
Finished Jun 10 05:19:23 PM PDT 24
Peak memory 200272 kb
Host smart-bcdb0c99-9bb2-46cb-9552-91845f18b72e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930350598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.3930350598
Directory /workspace/8.uart_intr/latest

Test location /workspace/coverage/default/8.uart_long_xfer_wo_dly.3300352127
Short name T599
Test name
Test status
Simulation time 109733345045 ps
CPU time 259.73 seconds
Started Jun 10 05:13:13 PM PDT 24
Finished Jun 10 05:17:33 PM PDT 24
Peak memory 200252 kb
Host smart-27230506-24ee-4b97-8c96-d0459a93574a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3300352127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.3300352127
Directory /workspace/8.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/8.uart_loopback.3479319984
Short name T755
Test name
Test status
Simulation time 11660427440 ps
CPU time 32.93 seconds
Started Jun 10 05:13:14 PM PDT 24
Finished Jun 10 05:13:48 PM PDT 24
Peak memory 199888 kb
Host smart-538342fe-6727-4ca4-8379-14c717250cf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479319984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_loopback.3479319984
Directory /workspace/8.uart_loopback/latest

Test location /workspace/coverage/default/8.uart_perf.844581483
Short name T332
Test name
Test status
Simulation time 19570466820 ps
CPU time 183.38 seconds
Started Jun 10 05:13:13 PM PDT 24
Finished Jun 10 05:16:16 PM PDT 24
Peak memory 200384 kb
Host smart-62c4e08f-a159-4745-b42d-77e404c59f3b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=844581483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.844581483
Directory /workspace/8.uart_perf/latest

Test location /workspace/coverage/default/8.uart_rx_oversample.106147082
Short name T491
Test name
Test status
Simulation time 2657122253 ps
CPU time 4.68 seconds
Started Jun 10 05:13:08 PM PDT 24
Finished Jun 10 05:13:13 PM PDT 24
Peak memory 198652 kb
Host smart-71366c91-9fd2-4e38-b7f4-dbcf25069142
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=106147082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.106147082
Directory /workspace/8.uart_rx_oversample/latest

Test location /workspace/coverage/default/8.uart_rx_parity_err.4285356535
Short name T435
Test name
Test status
Simulation time 100158438987 ps
CPU time 158.76 seconds
Started Jun 10 05:13:11 PM PDT 24
Finished Jun 10 05:15:50 PM PDT 24
Peak memory 200352 kb
Host smart-bf25dc77-f224-4b00-bcd4-3a82d555e8c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285356535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.4285356535
Directory /workspace/8.uart_rx_parity_err/latest

Test location /workspace/coverage/default/8.uart_rx_start_bit_filter.4121497518
Short name T752
Test name
Test status
Simulation time 2091364553 ps
CPU time 1.62 seconds
Started Jun 10 05:13:11 PM PDT 24
Finished Jun 10 05:13:13 PM PDT 24
Peak memory 195856 kb
Host smart-2e34156f-a6b7-4f51-a72f-0335d5872982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121497518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.4121497518
Directory /workspace/8.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/8.uart_smoke.2323026019
Short name T950
Test name
Test status
Simulation time 517548878 ps
CPU time 1.68 seconds
Started Jun 10 05:13:10 PM PDT 24
Finished Jun 10 05:13:12 PM PDT 24
Peak memory 198816 kb
Host smart-0437ecfb-dbc3-4935-9edb-26d393fe29c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323026019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_smoke.2323026019
Directory /workspace/8.uart_smoke/latest

Test location /workspace/coverage/default/8.uart_stress_all.3891454250
Short name T822
Test name
Test status
Simulation time 386115975139 ps
CPU time 133.07 seconds
Started Jun 10 05:13:13 PM PDT 24
Finished Jun 10 05:15:27 PM PDT 24
Peak memory 200176 kb
Host smart-16c31ac9-3a5b-41eb-b4ca-f760c080d6dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891454250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.3891454250
Directory /workspace/8.uart_stress_all/latest

Test location /workspace/coverage/default/8.uart_stress_all_with_rand_reset.537476717
Short name T764
Test name
Test status
Simulation time 24821264311 ps
CPU time 148.04 seconds
Started Jun 10 05:13:12 PM PDT 24
Finished Jun 10 05:15:40 PM PDT 24
Peak memory 216596 kb
Host smart-d39512e5-75e3-46fb-9d96-a397e425eff7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537476717 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 8.uart_stress_all_with_rand_reset.537476717
Directory /workspace/8.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_tx_ovrd.845507581
Short name T559
Test name
Test status
Simulation time 1461176666 ps
CPU time 2.73 seconds
Started Jun 10 05:13:08 PM PDT 24
Finished Jun 10 05:13:11 PM PDT 24
Peak memory 198720 kb
Host smart-4a7ba43e-c9e6-4627-8186-e366b3aa6916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845507581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.845507581
Directory /workspace/8.uart_tx_ovrd/latest

Test location /workspace/coverage/default/8.uart_tx_rx.3098206456
Short name T913
Test name
Test status
Simulation time 88673051365 ps
CPU time 24.62 seconds
Started Jun 10 05:13:09 PM PDT 24
Finished Jun 10 05:13:34 PM PDT 24
Peak memory 200320 kb
Host smart-7d58f387-0dda-49b1-8010-e392eb81ee8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098206456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.3098206456
Directory /workspace/8.uart_tx_rx/latest

Test location /workspace/coverage/default/80.uart_fifo_reset.2717185338
Short name T858
Test name
Test status
Simulation time 102288252357 ps
CPU time 112.98 seconds
Started Jun 10 05:15:07 PM PDT 24
Finished Jun 10 05:17:01 PM PDT 24
Peak memory 200388 kb
Host smart-1f6dd5f0-e434-413b-99cb-0c04a0129d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717185338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.2717185338
Directory /workspace/80.uart_fifo_reset/latest

Test location /workspace/coverage/default/80.uart_stress_all_with_rand_reset.1117146612
Short name T687
Test name
Test status
Simulation time 76732026262 ps
CPU time 348.07 seconds
Started Jun 10 05:15:14 PM PDT 24
Finished Jun 10 05:21:03 PM PDT 24
Peak memory 217068 kb
Host smart-0f7d80a4-734b-4011-9f2c-008ee12487a7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117146612 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 80.uart_stress_all_with_rand_reset.1117146612
Directory /workspace/80.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/81.uart_fifo_reset.2083376041
Short name T698
Test name
Test status
Simulation time 45965123429 ps
CPU time 22.83 seconds
Started Jun 10 05:15:11 PM PDT 24
Finished Jun 10 05:15:35 PM PDT 24
Peak memory 200384 kb
Host smart-c4ee9f3d-a893-4236-ab1e-d0ac1c160365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083376041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.2083376041
Directory /workspace/81.uart_fifo_reset/latest

Test location /workspace/coverage/default/81.uart_stress_all_with_rand_reset.2997861810
Short name T608
Test name
Test status
Simulation time 23051492840 ps
CPU time 248.1 seconds
Started Jun 10 05:15:13 PM PDT 24
Finished Jun 10 05:19:22 PM PDT 24
Peak memory 208596 kb
Host smart-2b906070-2c73-4014-886a-e63d4be355c3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997861810 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 81.uart_stress_all_with_rand_reset.2997861810
Directory /workspace/81.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.uart_fifo_reset.3049213577
Short name T53
Test name
Test status
Simulation time 14079228968 ps
CPU time 20.62 seconds
Started Jun 10 05:15:11 PM PDT 24
Finished Jun 10 05:15:32 PM PDT 24
Peak memory 200328 kb
Host smart-c66ef40a-3b5b-4f4e-8b13-39e90a7b4318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049213577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.3049213577
Directory /workspace/82.uart_fifo_reset/latest

Test location /workspace/coverage/default/83.uart_fifo_reset.4090697435
Short name T649
Test name
Test status
Simulation time 58528017080 ps
CPU time 21.57 seconds
Started Jun 10 05:15:16 PM PDT 24
Finished Jun 10 05:15:38 PM PDT 24
Peak memory 200348 kb
Host smart-098fead4-4b81-41cc-8367-84a0c80bf025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090697435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.4090697435
Directory /workspace/83.uart_fifo_reset/latest

Test location /workspace/coverage/default/83.uart_stress_all_with_rand_reset.1533729817
Short name T117
Test name
Test status
Simulation time 11962109617 ps
CPU time 167.33 seconds
Started Jun 10 05:15:12 PM PDT 24
Finished Jun 10 05:18:00 PM PDT 24
Peak memory 216612 kb
Host smart-97b30bdf-22c0-41d8-bebc-e92445512756
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533729817 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 83.uart_stress_all_with_rand_reset.1533729817
Directory /workspace/83.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/84.uart_fifo_reset.2350247873
Short name T616
Test name
Test status
Simulation time 105650438351 ps
CPU time 142.73 seconds
Started Jun 10 05:15:13 PM PDT 24
Finished Jun 10 05:17:36 PM PDT 24
Peak memory 200280 kb
Host smart-f805de6a-b967-4caf-81df-9a2b9aad2381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350247873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.2350247873
Directory /workspace/84.uart_fifo_reset/latest

Test location /workspace/coverage/default/84.uart_stress_all_with_rand_reset.842216491
Short name T845
Test name
Test status
Simulation time 104603194056 ps
CPU time 638.64 seconds
Started Jun 10 05:15:13 PM PDT 24
Finished Jun 10 05:25:52 PM PDT 24
Peak memory 209252 kb
Host smart-ebbfc79e-f633-4fc7-8066-63ee861973f6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842216491 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 84.uart_stress_all_with_rand_reset.842216491
Directory /workspace/84.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.uart_fifo_reset.221735976
Short name T737
Test name
Test status
Simulation time 84743379987 ps
CPU time 9.78 seconds
Started Jun 10 05:15:17 PM PDT 24
Finished Jun 10 05:15:27 PM PDT 24
Peak memory 200316 kb
Host smart-38c593b4-4633-4178-b19a-9a33e304bb08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221735976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.221735976
Directory /workspace/85.uart_fifo_reset/latest

Test location /workspace/coverage/default/85.uart_stress_all_with_rand_reset.2090113802
Short name T553
Test name
Test status
Simulation time 54615219295 ps
CPU time 630.65 seconds
Started Jun 10 05:15:11 PM PDT 24
Finished Jun 10 05:25:42 PM PDT 24
Peak memory 216716 kb
Host smart-5fd5bf93-825e-486c-a22e-1b6498d58ed3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090113802 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 85.uart_stress_all_with_rand_reset.2090113802
Directory /workspace/85.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.uart_fifo_reset.3552319337
Short name T2
Test name
Test status
Simulation time 17639072502 ps
CPU time 32.02 seconds
Started Jun 10 05:15:13 PM PDT 24
Finished Jun 10 05:15:45 PM PDT 24
Peak memory 199124 kb
Host smart-469d566b-9de0-45c9-9b19-cce08ec32ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552319337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.3552319337
Directory /workspace/86.uart_fifo_reset/latest

Test location /workspace/coverage/default/87.uart_fifo_reset.1654701015
Short name T896
Test name
Test status
Simulation time 110561151871 ps
CPU time 89.58 seconds
Started Jun 10 05:15:14 PM PDT 24
Finished Jun 10 05:16:44 PM PDT 24
Peak memory 200428 kb
Host smart-09bb90b2-0367-4408-9b9b-312214fb1c8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654701015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.1654701015
Directory /workspace/87.uart_fifo_reset/latest

Test location /workspace/coverage/default/88.uart_fifo_reset.1599664486
Short name T490
Test name
Test status
Simulation time 71856264814 ps
CPU time 92.87 seconds
Started Jun 10 05:15:16 PM PDT 24
Finished Jun 10 05:16:50 PM PDT 24
Peak memory 200296 kb
Host smart-b2ef3935-510b-4dbf-9799-2d7e084474bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599664486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.1599664486
Directory /workspace/88.uart_fifo_reset/latest

Test location /workspace/coverage/default/88.uart_stress_all_with_rand_reset.2902626431
Short name T909
Test name
Test status
Simulation time 94593434283 ps
CPU time 1069.42 seconds
Started Jun 10 05:15:17 PM PDT 24
Finished Jun 10 05:33:07 PM PDT 24
Peak memory 216808 kb
Host smart-bfa2bf37-eeb8-4b94-bde1-feaaac2b4c03
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902626431 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 88.uart_stress_all_with_rand_reset.2902626431
Directory /workspace/88.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.uart_fifo_reset.3683723976
Short name T721
Test name
Test status
Simulation time 72303684923 ps
CPU time 123.96 seconds
Started Jun 10 05:15:45 PM PDT 24
Finished Jun 10 05:17:49 PM PDT 24
Peak memory 200376 kb
Host smart-5e65a688-4dce-4f39-ba35-29a7428a79ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683723976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.3683723976
Directory /workspace/89.uart_fifo_reset/latest

Test location /workspace/coverage/default/89.uart_stress_all_with_rand_reset.2823512792
Short name T218
Test name
Test status
Simulation time 64952227848 ps
CPU time 731.92 seconds
Started Jun 10 05:15:16 PM PDT 24
Finished Jun 10 05:27:28 PM PDT 24
Peak memory 216736 kb
Host smart-d57fa64d-0ccd-490e-bf73-b3a5df8c1106
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823512792 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 89.uart_stress_all_with_rand_reset.2823512792
Directory /workspace/89.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_alert_test.1080137240
Short name T745
Test name
Test status
Simulation time 40223354 ps
CPU time 0.59 seconds
Started Jun 10 05:13:20 PM PDT 24
Finished Jun 10 05:13:21 PM PDT 24
Peak memory 195588 kb
Host smart-7f74225f-6bd2-4a17-9825-83b57da62069
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080137240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.1080137240
Directory /workspace/9.uart_alert_test/latest

Test location /workspace/coverage/default/9.uart_fifo_full.550776949
Short name T895
Test name
Test status
Simulation time 91277408753 ps
CPU time 19.5 seconds
Started Jun 10 05:13:12 PM PDT 24
Finished Jun 10 05:13:32 PM PDT 24
Peak memory 200324 kb
Host smart-c25253bc-8d98-4253-b8f5-feb31ac79286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550776949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.550776949
Directory /workspace/9.uart_fifo_full/latest

Test location /workspace/coverage/default/9.uart_fifo_overflow.3665422376
Short name T951
Test name
Test status
Simulation time 25833743120 ps
CPU time 42.68 seconds
Started Jun 10 05:13:17 PM PDT 24
Finished Jun 10 05:14:00 PM PDT 24
Peak memory 200356 kb
Host smart-f07a97a4-6d1f-4653-9a4d-5afb4fd77c3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665422376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.3665422376
Directory /workspace/9.uart_fifo_overflow/latest

Test location /workspace/coverage/default/9.uart_fifo_reset.4159479930
Short name T570
Test name
Test status
Simulation time 128749289094 ps
CPU time 22.1 seconds
Started Jun 10 05:13:13 PM PDT 24
Finished Jun 10 05:13:35 PM PDT 24
Peak memory 200236 kb
Host smart-2e8d03c1-ba3b-4ba4-96b8-485b743a9017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159479930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.4159479930
Directory /workspace/9.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_intr.1512879304
Short name T670
Test name
Test status
Simulation time 221913633702 ps
CPU time 170.14 seconds
Started Jun 10 05:13:12 PM PDT 24
Finished Jun 10 05:16:03 PM PDT 24
Peak memory 200208 kb
Host smart-ec834caf-861f-45f9-9ac4-c6ea5001c1df
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512879304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.1512879304
Directory /workspace/9.uart_intr/latest

Test location /workspace/coverage/default/9.uart_long_xfer_wo_dly.2894904512
Short name T257
Test name
Test status
Simulation time 143303671383 ps
CPU time 607.79 seconds
Started Jun 10 05:13:15 PM PDT 24
Finished Jun 10 05:23:23 PM PDT 24
Peak memory 200228 kb
Host smart-35d957c3-8353-4d6e-9f98-3569d07922b7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2894904512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.2894904512
Directory /workspace/9.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/9.uart_loopback.1791588632
Short name T388
Test name
Test status
Simulation time 8176519582 ps
CPU time 6.92 seconds
Started Jun 10 05:13:15 PM PDT 24
Finished Jun 10 05:13:22 PM PDT 24
Peak memory 200208 kb
Host smart-a8f80b27-e46a-4ff2-881c-2abb78262eeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791588632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_loopback.1791588632
Directory /workspace/9.uart_loopback/latest

Test location /workspace/coverage/default/9.uart_perf.2957095163
Short name T886
Test name
Test status
Simulation time 13742797018 ps
CPU time 77.82 seconds
Started Jun 10 05:13:16 PM PDT 24
Finished Jun 10 05:14:34 PM PDT 24
Peak memory 200368 kb
Host smart-55baea6a-3be6-4cb7-a279-79135787beba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2957095163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.2957095163
Directory /workspace/9.uart_perf/latest

Test location /workspace/coverage/default/9.uart_rx_oversample.1393009889
Short name T1058
Test name
Test status
Simulation time 3346170835 ps
CPU time 7.26 seconds
Started Jun 10 05:13:14 PM PDT 24
Finished Jun 10 05:13:21 PM PDT 24
Peak memory 198432 kb
Host smart-60cbab50-7dab-493e-af42-0fbbfab460ca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1393009889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.1393009889
Directory /workspace/9.uart_rx_oversample/latest

Test location /workspace/coverage/default/9.uart_rx_parity_err.2958265482
Short name T742
Test name
Test status
Simulation time 132127724699 ps
CPU time 47.65 seconds
Started Jun 10 05:13:15 PM PDT 24
Finished Jun 10 05:14:03 PM PDT 24
Peak memory 200312 kb
Host smart-4b8aa8c1-1a51-4f12-98f9-d323e17a0af7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958265482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.2958265482
Directory /workspace/9.uart_rx_parity_err/latest

Test location /workspace/coverage/default/9.uart_rx_start_bit_filter.1314533732
Short name T276
Test name
Test status
Simulation time 38143908944 ps
CPU time 61.22 seconds
Started Jun 10 05:13:13 PM PDT 24
Finished Jun 10 05:14:14 PM PDT 24
Peak memory 196808 kb
Host smart-6e38b0d4-0bc2-4503-8274-87959317d5b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314533732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.1314533732
Directory /workspace/9.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/9.uart_smoke.1350099427
Short name T374
Test name
Test status
Simulation time 149146572 ps
CPU time 0.78 seconds
Started Jun 10 05:13:15 PM PDT 24
Finished Jun 10 05:13:16 PM PDT 24
Peak memory 197460 kb
Host smart-ea30f9de-cfc0-4b51-86d0-66f9e3412feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350099427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_smoke.1350099427
Directory /workspace/9.uart_smoke/latest

Test location /workspace/coverage/default/9.uart_stress_all.3996710522
Short name T618
Test name
Test status
Simulation time 28981359350 ps
CPU time 123.28 seconds
Started Jun 10 05:13:19 PM PDT 24
Finished Jun 10 05:15:23 PM PDT 24
Peak memory 200320 kb
Host smart-c26bb35b-dcf2-42c1-b0ca-c7bbef8b8dcb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996710522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.3996710522
Directory /workspace/9.uart_stress_all/latest

Test location /workspace/coverage/default/9.uart_tx_ovrd.1918747129
Short name T980
Test name
Test status
Simulation time 6943168300 ps
CPU time 14.63 seconds
Started Jun 10 05:13:13 PM PDT 24
Finished Jun 10 05:13:28 PM PDT 24
Peak memory 200200 kb
Host smart-1f646410-3f03-41cd-b362-bd687340f733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918747129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.1918747129
Directory /workspace/9.uart_tx_ovrd/latest

Test location /workspace/coverage/default/9.uart_tx_rx.1327698109
Short name T533
Test name
Test status
Simulation time 138876962319 ps
CPU time 64.65 seconds
Started Jun 10 05:13:13 PM PDT 24
Finished Jun 10 05:14:18 PM PDT 24
Peak memory 200380 kb
Host smart-ab7a610a-90cd-4d7e-b6ca-a2515c9d7b0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327698109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.1327698109
Directory /workspace/9.uart_tx_rx/latest

Test location /workspace/coverage/default/90.uart_fifo_reset.3233864254
Short name T706
Test name
Test status
Simulation time 111381521320 ps
CPU time 56.83 seconds
Started Jun 10 05:15:16 PM PDT 24
Finished Jun 10 05:16:13 PM PDT 24
Peak memory 200324 kb
Host smart-b6a85634-a579-4186-8a17-fc2272057ea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233864254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.3233864254
Directory /workspace/90.uart_fifo_reset/latest

Test location /workspace/coverage/default/90.uart_stress_all_with_rand_reset.2142125872
Short name T60
Test name
Test status
Simulation time 239274422068 ps
CPU time 917.02 seconds
Started Jun 10 05:15:15 PM PDT 24
Finished Jun 10 05:30:33 PM PDT 24
Peak memory 216080 kb
Host smart-0c5e60a3-61c7-40d4-8107-7b3939034e3a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142125872 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 90.uart_stress_all_with_rand_reset.2142125872
Directory /workspace/90.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.uart_fifo_reset.2162210376
Short name T813
Test name
Test status
Simulation time 18182923776 ps
CPU time 28.46 seconds
Started Jun 10 05:15:18 PM PDT 24
Finished Jun 10 05:15:47 PM PDT 24
Peak memory 200280 kb
Host smart-7e63ca60-b824-41a9-8629-04bdb6c13f22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162210376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.2162210376
Directory /workspace/91.uart_fifo_reset/latest

Test location /workspace/coverage/default/91.uart_stress_all_with_rand_reset.3940074541
Short name T825
Test name
Test status
Simulation time 165573289026 ps
CPU time 530.85 seconds
Started Jun 10 05:15:16 PM PDT 24
Finished Jun 10 05:24:07 PM PDT 24
Peak memory 212704 kb
Host smart-39e17f09-7360-455d-8bc3-b052bc94e4d5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940074541 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 91.uart_stress_all_with_rand_reset.3940074541
Directory /workspace/91.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.uart_fifo_reset.1589499284
Short name T405
Test name
Test status
Simulation time 15547980289 ps
CPU time 25.19 seconds
Started Jun 10 05:15:15 PM PDT 24
Finished Jun 10 05:15:41 PM PDT 24
Peak memory 200224 kb
Host smart-09a2a69a-2f6c-4d52-a0c1-88c0fda39174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589499284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.1589499284
Directory /workspace/92.uart_fifo_reset/latest

Test location /workspace/coverage/default/93.uart_stress_all_with_rand_reset.1659032489
Short name T215
Test name
Test status
Simulation time 125853480676 ps
CPU time 819.02 seconds
Started Jun 10 05:15:15 PM PDT 24
Finished Jun 10 05:28:55 PM PDT 24
Peak memory 216924 kb
Host smart-cfb4be1e-09f2-4af8-b44e-56e7acb12891
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659032489 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 93.uart_stress_all_with_rand_reset.1659032489
Directory /workspace/93.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/94.uart_fifo_reset.3822056961
Short name T55
Test name
Test status
Simulation time 26637903968 ps
CPU time 46.96 seconds
Started Jun 10 05:15:15 PM PDT 24
Finished Jun 10 05:16:02 PM PDT 24
Peak memory 200316 kb
Host smart-afaf845d-04fd-4722-8423-397679ba778a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822056961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.3822056961
Directory /workspace/94.uart_fifo_reset/latest

Test location /workspace/coverage/default/94.uart_stress_all_with_rand_reset.1988351397
Short name T177
Test name
Test status
Simulation time 81688327921 ps
CPU time 350.61 seconds
Started Jun 10 05:15:18 PM PDT 24
Finished Jun 10 05:21:09 PM PDT 24
Peak memory 213272 kb
Host smart-59f5cbbc-4c64-4662-b000-51ca0a4181e1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988351397 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 94.uart_stress_all_with_rand_reset.1988351397
Directory /workspace/94.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/95.uart_fifo_reset.3636238395
Short name T926
Test name
Test status
Simulation time 129179921901 ps
CPU time 283.28 seconds
Started Jun 10 05:15:18 PM PDT 24
Finished Jun 10 05:20:01 PM PDT 24
Peak memory 200372 kb
Host smart-92e2fac5-5d9a-4e0f-9120-5f4ca12e5698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636238395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.3636238395
Directory /workspace/95.uart_fifo_reset/latest

Test location /workspace/coverage/default/95.uart_stress_all_with_rand_reset.1086021400
Short name T118
Test name
Test status
Simulation time 56927204349 ps
CPU time 273.78 seconds
Started Jun 10 05:15:19 PM PDT 24
Finished Jun 10 05:19:53 PM PDT 24
Peak memory 216216 kb
Host smart-00a0000c-60e7-4c8b-9f70-1ab2d2203e2d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086021400 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 95.uart_stress_all_with_rand_reset.1086021400
Directory /workspace/95.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/96.uart_fifo_reset.667775554
Short name T904
Test name
Test status
Simulation time 50826051620 ps
CPU time 38.14 seconds
Started Jun 10 05:15:18 PM PDT 24
Finished Jun 10 05:15:56 PM PDT 24
Peak memory 200344 kb
Host smart-a521ed15-54f5-43fb-a462-bfcec9946b14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667775554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.667775554
Directory /workspace/96.uart_fifo_reset/latest

Test location /workspace/coverage/default/96.uart_stress_all_with_rand_reset.556025467
Short name T505
Test name
Test status
Simulation time 52750965552 ps
CPU time 230.86 seconds
Started Jun 10 05:15:17 PM PDT 24
Finished Jun 10 05:19:08 PM PDT 24
Peak memory 208484 kb
Host smart-a4b1bb17-dfe2-416a-acfe-86befe4c5652
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556025467 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 96.uart_stress_all_with_rand_reset.556025467
Directory /workspace/96.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.uart_fifo_reset.312319316
Short name T775
Test name
Test status
Simulation time 172671992211 ps
CPU time 34.12 seconds
Started Jun 10 05:15:19 PM PDT 24
Finished Jun 10 05:15:53 PM PDT 24
Peak memory 200296 kb
Host smart-09263a5a-89c9-4361-a71c-a0e46f5225f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312319316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.312319316
Directory /workspace/97.uart_fifo_reset/latest

Test location /workspace/coverage/default/97.uart_stress_all_with_rand_reset.4016023890
Short name T31
Test name
Test status
Simulation time 36131405312 ps
CPU time 386.43 seconds
Started Jun 10 05:15:17 PM PDT 24
Finished Jun 10 05:21:44 PM PDT 24
Peak memory 215904 kb
Host smart-1bcde326-9c96-4f25-b006-15daa515029f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016023890 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 97.uart_stress_all_with_rand_reset.4016023890
Directory /workspace/97.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/98.uart_fifo_reset.2349746206
Short name T144
Test name
Test status
Simulation time 63219856676 ps
CPU time 16.44 seconds
Started Jun 10 05:15:25 PM PDT 24
Finished Jun 10 05:15:41 PM PDT 24
Peak memory 200344 kb
Host smart-be22e7c4-1c6a-4ecd-9446-34c42cb0b772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349746206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.2349746206
Directory /workspace/98.uart_fifo_reset/latest

Test location /workspace/coverage/default/98.uart_stress_all_with_rand_reset.1097605494
Short name T702
Test name
Test status
Simulation time 58512556227 ps
CPU time 566.95 seconds
Started Jun 10 05:15:25 PM PDT 24
Finished Jun 10 05:24:52 PM PDT 24
Peak memory 216864 kb
Host smart-27155315-ac4a-4c16-bdd5-3a6f581e57bc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097605494 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 98.uart_stress_all_with_rand_reset.1097605494
Directory /workspace/98.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/99.uart_fifo_reset.1735555298
Short name T906
Test name
Test status
Simulation time 8883090829 ps
CPU time 18.06 seconds
Started Jun 10 05:15:19 PM PDT 24
Finished Jun 10 05:15:37 PM PDT 24
Peak memory 200280 kb
Host smart-938dc34c-ad92-406c-8a1b-1ee98acbe57a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735555298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.1735555298
Directory /workspace/99.uart_fifo_reset/latest
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