Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	94824	1			T1	457		T2	65		T3	653
all_values[1]	94824	1			T1	457		T2	65		T3	653
all_values[2]	94824	1			T1	457		T2	65		T3	653
all_values[3]	94824	1			T1	457		T2	65		T3	653
all_values[4]	94824	1			T1	457		T2	65		T3	653
all_values[5]	94824	1			T1	457		T2	65		T3	653
all_values[6]	94824	1			T1	457		T2	65		T3	653
all_values[7]	94824	1			T1	457		T2	65		T3	653
all_values[8]	94824	1			T1	457		T2	65		T3	653

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

419196

1

T1

1991

T2

182

T3

3177

auto[1]

434220

1

T1

2122

T2

403

T3

2700

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

773655

1

T1

3775

T2

451

T3

5574

auto[1]

79761

1

T1

338

T2

134

T3

303

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	24399	1			T1	236		T3	414		T9	149
all_values[0]	auto[0]	auto[1]	19132	1			T1	43		T2	30		T3	75
all_values[0]	auto[1]	auto[0]	31211	1			T1	50		T2	5		T3	68
all_values[0]	auto[1]	auto[1]	20082	1			T1	128		T2	30		T3	96
all_values[1]	auto[0]	auto[0]	39183	1			T1	199		T2	35		T3	225
all_values[1]	auto[0]	auto[1]	1470	1			T9	1		T15	2		T13	9
all_values[1]	auto[1]	auto[0]	52632	1			T1	258		T2	28		T3	428
all_values[1]	auto[1]	auto[1]	1539	1			T2	2		T8	14		T15	1
all_values[2]	auto[0]	auto[0]	47051	1			T1	361		T3	431		T5	1
all_values[2]	auto[0]	auto[1]	2254	1			T1	7		T3	7		T5	1
all_values[2]	auto[1]	auto[0]	43497	1			T1	79		T2	65		T3	207
all_values[2]	auto[1]	auto[1]	2022	1			T1	10		T3	8		T9	3
all_values[3]	auto[0]	auto[0]	43358	1			T1	51		T3	217		T5	2
all_values[3]	auto[0]	auto[1]	265	1			T8	1		T14	4		T16	2
all_values[3]	auto[1]	auto[0]	50981	1			T1	406		T2	65		T3	436
all_values[3]	auto[1]	auto[1]	220	1			T13	1		T16	2		T59	2
all_values[4]	auto[0]	auto[0]	49473	1			T1	45		T3	238		T5	2
all_values[4]	auto[0]	auto[1]	338	1			T8	22		T9	1		T15	1
all_values[4]	auto[1]	auto[0]	44651	1			T1	412		T2	53		T3	415
all_values[4]	auto[1]	auto[1]	362	1			T2	12		T15	3		T16	11
all_values[5]	auto[0]	auto[0]	48979	1			T1	37		T2	11		T3	608
all_values[5]	auto[0]	auto[1]	130	1			T59	2		T98	1		T99	4
all_values[5]	auto[1]	auto[0]	45596	1			T1	420		T2	54		T3	45
all_values[5]	auto[1]	auto[1]	119	1			T9	3		T16	1		T59	4
all_values[6]	auto[0]	auto[0]	49493	1			T1	404		T2	41		T3	522
all_values[6]	auto[0]	auto[1]	142	1			T15	3		T16	2		T59	3
all_values[6]	auto[1]	auto[0]	45068	1			T1	53		T2	24		T3	131
all_values[6]	auto[1]	auto[1]	121	1			T15	1		T59	2		T101	2
all_values[7]	auto[0]	auto[0]	48733	1			T1	199		T2	52		T3	218
all_values[7]	auto[0]	auto[1]	312	1			T2	2		T16	2		T59	3
all_values[7]	auto[1]	auto[0]	45466	1			T1	258		T2	11		T3	435
all_values[7]	auto[1]	auto[1]	313	1			T15	2		T13	14		T16	1
all_values[8]	auto[0]	auto[0]	29265	1			T1	276		T3	188		T8	27
all_values[8]	auto[0]	auto[1]	15219	1			T1	133		T2	11		T3	34
all_values[8]	auto[1]	auto[0]	34619	1			T1	31		T2	7		T3	348
all_values[8]	auto[1]	auto[1]	15721	1			T1	17		T2	47		T3	83