Unified Coverage Report :: Group :: uart_agent_pkg::uart_agent_cov::uart_reset_cg

Group : uart_agent_pkg::uart_agent_cov::uart_reset_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_agent_0.1/uart_agent_cov.sv

---

Summary for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	22	0	22	100.00

Variables for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	0
cp_rst_pos	11	0	11	100.00	100	1	1	0

Crosses for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
uart_reset_cg_cc	22	0	22	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[UartTx]

2273

1

T1

4

T2

1

T3

11

auto[UartRx]

2273

1

T1

4

T2

1

T3

11

---

Summary for Variable cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_rst_pos

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4099	1			T1	8		T2	2		T3	13
values[1]	29	1			T17	1		T27	2		T321	1
values[2]	44	1			T9	1		T13	1		T16	2
values[3]	37	1			T9	1		T13	2		T17	2
values[4]	39	1			T9	2		T25	1		T26	1
values[5]	53	1			T3	2		T9	1		T13	1
values[6]	36	1			T16	1		T17	2		T26	1
values[7]	45	1			T3	1		T16	3		T98	1
values[8]	44	1			T3	1		T9	1		T16	1
values[9]	47	1			T3	3		T9	1		T16	1
values[10]	50	1			T3	2		T9	2		T16	2

---

Summary for Cross uart_reset_cg_cc

Samples crossed: cp_dir cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	22	0	22	100.00

Automatically Generated Cross Bins for uart_reset_cg_cc

Bins

cp_dir	cp_rst_pos	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[UartTx]	values[0]	2116	1			T1	4		T2	1		T3	7
auto[UartTx]	values[1]	10	1			T27	1		T323	2		T86	1
auto[UartTx]	values[2]	16	1			T98	1		T323	1		T34	1
auto[UartTx]	values[3]	17	1			T9	1		T13	2		T17	1
auto[UartTx]	values[4]	14	1			T99	2		T145	1		T84	2
auto[UartTx]	values[5]	14	1			T25	1		T27	1		T28	1
auto[UartTx]	values[6]	16	1			T17	1		T98	2		T122	1
auto[UartTx]	values[7]	16	1			T3	1		T16	1		T102	1
auto[UartTx]	values[8]	14	1			T3	1		T84	1		T104	1
auto[UartTx]	values[9]	16	1			T3	1		T17	1		T26	1
auto[UartTx]	values[10]	19	1			T3	1		T16	1		T17	1
auto[UartRx]	values[0]	1983	1			T1	4		T2	1		T3	6
auto[UartRx]	values[1]	19	1			T17	1		T27	1		T321	1
auto[UartRx]	values[2]	28	1			T9	1		T13	1		T16	2
auto[UartRx]	values[3]	20	1			T17	1		T28	1		T99	1
auto[UartRx]	values[4]	25	1			T9	2		T25	1		T26	1
auto[UartRx]	values[5]	39	1			T3	2		T9	1		T13	1
auto[UartRx]	values[6]	20	1			T16	1		T17	1		T26	1
auto[UartRx]	values[7]	29	1			T16	2		T98	1		T81	1
auto[UartRx]	values[8]	30	1			T9	1		T16	1		T26	1
auto[UartRx]	values[9]	31	1			T3	2		T9	1		T16	1
auto[UartRx]	values[10]	31	1			T3	1		T9	2		T16	1