Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	1982	1			T1	7		T3	13		T5	1
auto[BaudRate115200]	1624	1			T1	8		T2	1		T3	11
auto[BaudRate230400]	1674	1			T1	5		T2	2		T3	6
auto[BaudRate128Kbps]	1642	1			T1	9		T3	8		T4	6
auto[BaudRate256Kbps]	1828	1			T1	8		T3	8		T4	3
auto[BaudRate1Mbps]	1539	1			T1	7		T3	19		T4	6
auto[BaudRate1p5Mbps]	1106	1			T1	2		T3	19		T5	1

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Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	1111	1			T1	46		T58	6		T279	2
freqs[25]	1190	1			T2	3		T10	2		T15	50
freqs[48]	672	1			T3	84		T290	2		T298	5
freqs[50]	669	1			T87	2		T89	10		T16	39
freqs[100]	908	1			T18	5		T30	9		T107	10

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Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	194	1			T1	7		T91	2		T33	2
auto[BaudRate9600]	freqs[25]	166	1			T10	1		T15	3		T163	4
auto[BaudRate9600]	freqs[48]	106	1			T3	13		T324	4		T26	10
auto[BaudRate9600]	freqs[50]	144	1			T87	1		T16	1		T27	8
auto[BaudRate9600]	freqs[100]	144	1			T18	1		T30	2		T107	1
auto[BaudRate115200]	freqs[24]	172	1			T1	8		T58	1		T279	1
auto[BaudRate115200]	freqs[25]	161	1			T2	1		T15	6		T163	1
auto[BaudRate115200]	freqs[48]	84	1			T3	11		T290	1		T298	1
auto[BaudRate115200]	freqs[50]	67	1			T89	4		T16	4		T27	6
auto[BaudRate115200]	freqs[100]	138	1			T30	2		T107	1		T275	1
auto[BaudRate230400]	freqs[24]	129	1			T1	5		T58	2		T91	1
auto[BaudRate230400]	freqs[25]	175	1			T2	2		T15	10		T163	1
auto[BaudRate230400]	freqs[48]	113	1			T3	6		T26	23		T117	1
auto[BaudRate230400]	freqs[50]	92	1			T87	1		T16	5		T307	1
auto[BaudRate230400]	freqs[100]	125	1			T18	1		T107	2		T282	1
auto[BaudRate128Kbps]	freqs[24]	172	1			T1	9		T58	1		T33	3
auto[BaudRate128Kbps]	freqs[25]	185	1			T15	3		T163	1		T250	1
auto[BaudRate128Kbps]	freqs[48]	69	1			T3	8		T298	1		T26	5
auto[BaudRate128Kbps]	freqs[50]	101	1			T89	2		T16	4		T307	1
auto[BaudRate128Kbps]	freqs[100]	125	1			T30	3		T107	1		T282	2
auto[BaudRate256Kbps]	freqs[24]	169	1			T1	8		T279	1		T33	3
auto[BaudRate256Kbps]	freqs[25]	204	1			T10	1		T15	17		T163	1
auto[BaudRate256Kbps]	freqs[48]	96	1			T3	8		T298	3		T26	15
auto[BaudRate256Kbps]	freqs[50]	91	1			T16	8		T27	8		T325	3
auto[BaudRate256Kbps]	freqs[100]	119	1			T18	1		T30	1		T107	2
auto[BaudRate1Mbps]	freqs[24]	198	1			T1	7		T58	2		T91	2
auto[BaudRate1Mbps]	freqs[25]	185	1			T15	11		T250	1		T288	2
auto[BaudRate1Mbps]	freqs[48]	105	1			T3	19		T26	6		T117	1
auto[BaudRate1Mbps]	freqs[50]	89	1			T89	3		T16	10		T27	8
auto[BaudRate1Mbps]	freqs[100]	138	1			T18	1		T30	1		T275	1
auto[BaudRate1p5Mbps]	freqs[25]	114	1			T163	2		T250	1		T131	1
auto[BaudRate1p5Mbps]	freqs[48]	99	1			T3	19		T290	1		T26	5
auto[BaudRate1p5Mbps]	freqs[50]	85	1			T89	1		T16	7		T27	13
auto[BaudRate1p5Mbps]	freqs[100]	119	1			T18	1		T107	3		T282	1

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded