Group : uart_env_pkg::uart_env_cov::rx_fifo_level_cg
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Group : uart_env_pkg::uart_env_cov::rx_fifo_level_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
94.92 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv



Summary for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 67 0 67 100.00
Crosses 130 10 120 92.31


Variables for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_lvl 65 0 65 100.00 100 1 1 0
cp_rst 2 0 2 100.00 100 1 1 2


Crosses for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
rx_fifo_level_cg_cc 130 10 120 92.31 100 1 1 0


Summary for Variable cp_lvl

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 65 0 65 100.00


User Defined Bins for cp_lvl

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_levels[0] 28370341 1 T1 148412 T2 1217 T3 163125
all_levels[1] 172010 1 T1 194 T3 337 T9 126
all_levels[2] 1939 1 T1 12 T9 2 T30 5
all_levels[3] 874 1 T1 6 T3 2 T9 1
all_levels[4] 611 1 T1 3 T9 1 T18 1
all_levels[5] 451 1 T1 1 T9 1 T30 1
all_levels[6] 359 1 T30 2 T106 1 T33 3
all_levels[7] 267 1 T1 5 T3 2 T11 1
all_levels[8] 241 1 T13 1 T30 2 T107 2
all_levels[9] 229 1 T1 2 T11 1 T30 1
all_levels[10] 205 1 T1 2 T9 1 T30 1
all_levels[11] 144 1 T1 1 T9 1 T18 1
all_levels[12] 124 1 T1 1 T3 1 T58 1
all_levels[13] 140 1 T3 1 T9 1 T11 1
all_levels[14] 108 1 T1 2 T3 1 T18 1
all_levels[15] 104 1 T1 2 T3 2 T58 1
all_levels[16] 109 1 T1 1 T18 1 T107 1
all_levels[17] 83 1 T30 1 T92 2 T108 1
all_levels[18] 86 1 T1 1 T58 2 T107 1
all_levels[19] 61 1 T58 1 T16 3 T25 1
all_levels[20] 64 1 T109 1 T110 2 T111 1
all_levels[21] 62 1 T1 1 T25 1 T92 1
all_levels[22] 64 1 T58 1 T17 1 T25 1
all_levels[23] 62 1 T92 1 T112 1 T27 1
all_levels[24] 46 1 T106 1 T26 1 T27 2
all_levels[25] 48 1 T112 1 T113 3 T114 1
all_levels[26] 55 1 T92 1 T27 2 T115 1
all_levels[27] 40 1 T1 2 T33 1 T27 1
all_levels[28] 53 1 T1 1 T16 3 T25 1
all_levels[29] 31 1 T28 1 T116 2 T117 1
all_levels[30] 43 1 T33 1 T118 1 T95 1
all_levels[31] 27 1 T112 1 T119 1 T120 1
all_levels[32] 30 1 T114 1 T121 1 T122 2
all_levels[33] 38 1 T1 1 T30 1 T27 1
all_levels[34] 37 1 T123 2 T111 1 T124 1
all_levels[35] 18 1 T125 1 T28 1 T117 1
all_levels[36] 21 1 T125 1 T126 1 T127 1
all_levels[37] 19 1 T27 1 T117 1 T128 1
all_levels[38] 21 1 T30 1 T25 1 T128 1
all_levels[39] 24 1 T30 1 T27 1 T117 1
all_levels[40] 19 1 T95 1 T129 1 T130 1
all_levels[41] 15 1 T131 1 T132 1 T133 1
all_levels[42] 25 1 T1 1 T76 1 T134 1
all_levels[43] 16 1 T135 1 T136 1 T137 1
all_levels[44] 15 1 T124 1 T138 1 T139 1
all_levels[45] 17 1 T95 3 T114 1 T140 1
all_levels[46] 12 1 T30 1 T141 1 T142 1
all_levels[47] 13 1 T124 1 T137 1 T143 1
all_levels[48] 11 1 T111 1 T144 1 T145 1
all_levels[49] 13 1 T1 2 T115 1 T126 1
all_levels[50] 10 1 T144 1 T102 1 T146 1
all_levels[51] 8 1 T115 1 T147 1 T102 1
all_levels[52] 5 1 T102 1 T146 1 T148 2
all_levels[53] 9 1 T149 1 T150 1 T83 1
all_levels[54] 13 1 T102 1 T151 6 T152 1
all_levels[55] 4 1 T153 1 T154 1 T155 1
all_levels[56] 6 1 T1 1 T156 1 T157 1
all_levels[57] 7 1 T92 1 T149 1 T157 1
all_levels[58] 14 1 T27 1 T158 3 T137 1
all_levels[59] 7 1 T158 1 T159 2 T160 1
all_levels[60] 10 1 T76 1 T144 1 T137 1
all_levels[61] 11 1 T132 1 T161 1 T156 1
all_levels[62] 1 1 T121 1 - - - -
all_levels[63] 2 1 T162 1 T36 1 - -
all_levels[64] 88 1 T13 1 T14 1 T25 3



Summary for Variable cp_rst

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_rst

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 28545106 1 T1 148648 T2 1187 T3 163453
auto[1] 4534 1 T1 6 T2 30 T3 18



Summary for Cross rx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 130 10 120 92.31 10


Automatically Generated Cross Bins for rx_fifo_level_cg_cc

Uncovered bins
cp_lvlcp_rstCOUNTAT LEASTNUMBERSTATUS
[all_levels[35]] [auto[1]] 0 1 1
[all_levels[41]] [auto[1]] 0 1 1
[all_levels[49] , all_levels[50] , all_levels[51]] [auto[1]] -- -- 3
[all_levels[53]] [auto[1]] 0 1 1
[all_levels[55] , all_levels[56]] [auto[1]] -- -- 2
[all_levels[62] , all_levels[63]] [auto[1]] -- -- 2


Covered bins
cp_lvlcp_rstCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_levels[0] auto[0] 28366227 1 T1 148406 T2 1187 T3 163107
all_levels[0] auto[1] 4114 1 T1 6 T2 30 T3 18
all_levels[1] auto[0] 171934 1 T1 194 T3 337 T9 126
all_levels[1] auto[1] 76 1 T30 1 T163 1 T106 1
all_levels[2] auto[0] 1911 1 T1 12 T9 2 T30 5
all_levels[2] auto[1] 28 1 T164 1 T165 1 T166 1
all_levels[3] auto[0] 856 1 T1 6 T3 2 T9 1
all_levels[3] auto[1] 18 1 T117 1 T167 1 T168 1
all_levels[4] auto[0] 595 1 T1 3 T9 1 T18 1
all_levels[4] auto[1] 16 1 T107 2 T169 1 T170 1
all_levels[5] auto[0] 435 1 T1 1 T9 1 T30 1
all_levels[5] auto[1] 16 1 T171 1 T172 1 T173 1
all_levels[6] auto[0] 345 1 T30 2 T106 1 T33 3
all_levels[6] auto[1] 14 1 T174 1 T175 1 T142 2
all_levels[7] auto[0] 255 1 T1 5 T3 2 T11 1
all_levels[7] auto[1] 12 1 T176 2 T177 1 T178 1
all_levels[8] auto[0] 231 1 T13 1 T30 2 T107 1
all_levels[8] auto[1] 10 1 T107 1 T158 1 T122 1
all_levels[9] auto[0] 214 1 T1 2 T11 1 T30 1
all_levels[9] auto[1] 15 1 T95 1 T179 1 T180 1
all_levels[10] auto[0] 193 1 T1 2 T9 1 T30 1
all_levels[10] auto[1] 12 1 T176 3 T181 1 T182 3
all_levels[11] auto[0] 140 1 T1 1 T9 1 T18 1
all_levels[11] auto[1] 4 1 T183 1 T184 1 T185 1
all_levels[12] auto[0] 114 1 T1 1 T3 1 T58 1
all_levels[12] auto[1] 10 1 T30 1 T186 1 T187 2
all_levels[13] auto[0] 132 1 T3 1 T9 1 T11 1
all_levels[13] auto[1] 8 1 T110 2 T142 2 T188 1
all_levels[14] auto[0] 100 1 T1 2 T3 1 T18 1
all_levels[14] auto[1] 8 1 T172 1 T189 2 T180 2
all_levels[15] auto[0] 100 1 T1 2 T3 2 T58 1
all_levels[15] auto[1] 4 1 T131 2 T129 1 T190 1
all_levels[16] auto[0] 101 1 T1 1 T18 1 T107 1
all_levels[16] auto[1] 8 1 T191 2 T192 1 T193 1
all_levels[17] auto[0] 78 1 T30 1 T92 2 T108 1
all_levels[17] auto[1] 5 1 T194 1 T195 1 T196 1
all_levels[18] auto[0] 81 1 T1 1 T58 1 T107 1
all_levels[18] auto[1] 5 1 T58 1 T125 1 T110 1
all_levels[19] auto[0] 55 1 T58 1 T16 1 T25 1
all_levels[19] auto[1] 6 1 T16 2 T197 1 T198 3
all_levels[20] auto[0] 53 1 T109 1 T110 2 T111 1
all_levels[20] auto[1] 11 1 T199 1 T200 1 T201 1
all_levels[21] auto[0] 56 1 T1 1 T25 1 T92 1
all_levels[21] auto[1] 6 1 T94 1 T202 1 T203 1
all_levels[22] auto[0] 57 1 T58 1 T17 1 T25 1
all_levels[22] auto[1] 7 1 T110 2 T102 1 T146 2
all_levels[23] auto[0] 48 1 T92 1 T112 1 T27 1
all_levels[23] auto[1] 14 1 T204 2 T205 1 T206 3
all_levels[24] auto[0] 43 1 T106 1 T26 1 T27 2
all_levels[24] auto[1] 3 1 T200 1 T207 1 T208 1
all_levels[25] auto[0] 40 1 T112 1 T113 2 T114 1
all_levels[25] auto[1] 8 1 T113 1 T209 2 T210 1
all_levels[26] auto[0] 54 1 T92 1 T27 2 T115 1
all_levels[26] auto[1] 1 1 T211 1 - - - -
all_levels[27] auto[0] 37 1 T1 2 T33 1 T27 1
all_levels[27] auto[1] 3 1 T212 1 T213 2 - -
all_levels[28] auto[0] 39 1 T1 1 T16 1 T25 1
all_levels[28] auto[1] 14 1 T16 2 T76 1 T204 1
all_levels[29] auto[0] 26 1 T28 1 T116 1 T117 1
all_levels[29] auto[1] 5 1 T116 1 T214 1 T215 2
all_levels[30] auto[0] 35 1 T33 1 T118 1 T95 1
all_levels[30] auto[1] 8 1 T191 1 T216 1 T162 2
all_levels[31] auto[0] 23 1 T112 1 T119 1 T120 1
all_levels[31] auto[1] 4 1 T217 2 T218 2 - -
all_levels[32] auto[0] 28 1 T114 1 T121 1 T122 2
all_levels[32] auto[1] 2 1 T219 1 T166 1 - -
all_levels[33] auto[0] 32 1 T1 1 T30 1 T27 1
all_levels[33] auto[1] 6 1 T178 1 T159 1 T220 2
all_levels[34] auto[0] 30 1 T123 1 T111 1 T124 1
all_levels[34] auto[1] 7 1 T123 1 T142 3 T221 2
all_levels[35] auto[0] 18 1 T125 1 T28 1 T117 1
all_levels[36] auto[0] 18 1 T125 1 T126 1 T127 1
all_levels[36] auto[1] 3 1 T222 1 T223 1 T224 1
all_levels[37] auto[0] 18 1 T27 1 T117 1 T128 1
all_levels[37] auto[1] 1 1 T195 1 - - - -
all_levels[38] auto[0] 20 1 T30 1 T25 1 T128 1
all_levels[38] auto[1] 1 1 T225 1 - - - -
all_levels[39] auto[0] 23 1 T30 1 T27 1 T117 1
all_levels[39] auto[1] 1 1 T226 1 - - - -
all_levels[40] auto[0] 16 1 T95 1 T129 1 T130 1
all_levels[40] auto[1] 3 1 T191 1 T218 2 - -
all_levels[41] auto[0] 15 1 T131 1 T132 1 T133 1
all_levels[42] auto[0] 21 1 T1 1 T76 1 T134 1
all_levels[42] auto[1] 4 1 T191 2 T227 1 T228 1
all_levels[43] auto[0] 15 1 T135 1 T136 1 T137 1
all_levels[43] auto[1] 1 1 T229 1 - - - -
all_levels[44] auto[0] 14 1 T124 1 T138 1 T139 1
all_levels[44] auto[1] 1 1 T196 1 - - - -
all_levels[45] auto[0] 13 1 T95 1 T114 1 T140 1
all_levels[45] auto[1] 4 1 T95 2 T194 1 T220 1
all_levels[46] auto[0] 9 1 T30 1 T141 1 T142 1
all_levels[46] auto[1] 3 1 T230 3 - - - -
all_levels[47] auto[0] 10 1 T124 1 T137 1 T143 1
all_levels[47] auto[1] 3 1 T231 1 T232 2 - -
all_levels[48] auto[0] 10 1 T111 1 T144 1 T145 1
all_levels[48] auto[1] 1 1 T233 1 - - - -
all_levels[49] auto[0] 13 1 T1 2 T115 1 T126 1
all_levels[50] auto[0] 10 1 T144 1 T102 1 T146 1
all_levels[51] auto[0] 8 1 T115 1 T147 1 T102 1
all_levels[52] auto[0] 4 1 T102 1 T146 1 T148 1
all_levels[52] auto[1] 1 1 T148 1 - - - -
all_levels[53] auto[0] 9 1 T149 1 T150 1 T83 1
all_levels[54] auto[0] 8 1 T102 1 T151 1 T152 1
all_levels[54] auto[1] 5 1 T151 5 - - - -
all_levels[55] auto[0] 4 1 T153 1 T154 1 T155 1
all_levels[56] auto[0] 6 1 T1 1 T156 1 T157 1
all_levels[57] auto[0] 6 1 T92 1 T149 1 T157 1
all_levels[57] auto[1] 1 1 T234 1 - - - -
all_levels[58] auto[0] 11 1 T27 1 T158 1 T137 1
all_levels[58] auto[1] 3 1 T158 2 T235 1 - -
all_levels[59] auto[0] 6 1 T158 1 T159 1 T160 1
all_levels[59] auto[1] 1 1 T159 1 - - - -
all_levels[60] auto[0] 8 1 T76 1 T144 1 T137 1
all_levels[60] auto[1] 2 1 T236 2 - - - -
all_levels[61] auto[0] 9 1 T132 1 T161 1 T156 1
all_levels[61] auto[1] 2 1 T237 1 T233 1 - -
all_levels[62] auto[0] 1 1 T121 1 - - - -
all_levels[63] auto[0] 2 1 T162 1 T36 1 - -
all_levels[64] auto[0] 83 1 T13 1 T14 1 T25 3
all_levels[64] auto[1] 5 1 T238 1 T239 1 T240 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%