Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	9	0	9	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	94824	1			T1	457		T2	65		T3	653
all_pins[1]	94824	1			T1	457		T2	65		T3	653
all_pins[2]	94824	1			T1	457		T2	65		T3	653
all_pins[3]	94824	1			T1	457		T2	65		T3	653
all_pins[4]	94824	1			T1	457		T2	65		T3	653
all_pins[5]	94824	1			T1	457		T2	65		T3	653
all_pins[6]	94824	1			T1	457		T2	65		T3	653
all_pins[7]	94824	1			T1	457		T2	65		T3	653
all_pins[8]	94824	1			T1	457		T2	65		T3	653

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	812115	1			T1	3953		T2	488		T3	5688
values[0x1]	41301	1			T1	160		T2	97		T3	189
transitions[0x0=>0x1]	32485	1			T1	155		T2	79		T3	126
transitions[0x1=>0x0]	32328	1			T1	155		T2	79		T3	127

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	74673	1			T1	329		T2	34		T3	556
all_pins[0]	values[0x1]	20151	1			T1	128		T2	31		T3	97
all_pins[0]	transitions[0x0=>0x1]	19599	1			T1	128		T2	31		T3	97
all_pins[0]	transitions[0x1=>0x0]	985	1			T2	2		T15	1		T91	5
all_pins[1]	values[0x0]	93287	1			T1	457		T2	63		T3	653
all_pins[1]	values[0x1]	1537	1			T2	2		T8	14		T15	1
all_pins[1]	transitions[0x0=>0x1]	1445	1			T2	2		T8	14		T16	1
all_pins[1]	transitions[0x1=>0x0]	1973	1			T1	10		T2	2		T3	8
all_pins[2]	values[0x0]	92759	1			T1	447		T2	63		T3	645
all_pins[2]	values[0x1]	2065	1			T1	10		T2	2		T3	8
all_pins[2]	transitions[0x0=>0x1]	2025	1			T1	10		T2	2		T3	8
all_pins[2]	transitions[0x1=>0x0]	180	1			T16	1		T59	2		T241	1
all_pins[3]	values[0x0]	94604	1			T1	457		T2	65		T3	653
all_pins[3]	values[0x1]	220	1			T13	1		T16	2		T59	2
all_pins[3]	transitions[0x0=>0x1]	199	1			T13	1		T59	2		T241	1
all_pins[3]	transitions[0x1=>0x0]	341	1			T2	12		T15	3		T16	9
all_pins[4]	values[0x0]	94462	1			T1	457		T2	53		T3	653
all_pins[4]	values[0x1]	362	1			T2	12		T15	3		T16	11
all_pins[4]	transitions[0x0=>0x1]	322	1			T2	9		T15	3		T16	11
all_pins[4]	transitions[0x1=>0x0]	119	1			T8	2		T9	3		T13	3
all_pins[5]	values[0x0]	94665	1			T1	457		T2	62		T3	653
all_pins[5]	values[0x1]	159	1			T2	3		T8	2		T9	3
all_pins[5]	transitions[0x0=>0x1]	127	1			T2	3		T8	2		T9	3
all_pins[5]	transitions[0x1=>0x0]	686	1			T1	5		T3	1		T8	2
all_pins[6]	values[0x0]	94106	1			T1	452		T2	65		T3	652
all_pins[6]	values[0x1]	718	1			T1	5		T3	1		T8	2
all_pins[6]	transitions[0x0=>0x1]	692	1			T1	5		T3	1		T8	2
all_pins[6]	transitions[0x1=>0x0]	287	1			T15	2		T13	14		T16	1
all_pins[7]	values[0x0]	94511	1			T1	457		T2	65		T3	653
all_pins[7]	values[0x1]	313	1			T15	2		T13	14		T16	1
all_pins[7]	transitions[0x0=>0x1]	156	1			T16	1		T25	1		T242	2
all_pins[7]	transitions[0x1=>0x0]	15619	1			T1	17		T2	47		T3	83
all_pins[8]	values[0x0]	79048	1			T1	440		T2	18		T3	570
all_pins[8]	values[0x1]	15776	1			T1	17		T2	47		T3	83
all_pins[8]	transitions[0x0=>0x1]	7920	1			T1	12		T2	32		T3	20
all_pins[8]	transitions[0x1=>0x0]	12138	1			T1	123		T2	16		T3	35